Commit | Line | Data |
---|---|---|
61ec9016 | 1 | /* |
d9bb3fb1 | 2 | * Cadence UART driver (found in Xilinx Zynq) |
61ec9016 | 3 | * |
e555a211 | 4 | * 2011 - 2014 (C) Xilinx Inc. |
61ec9016 JL |
5 | * |
6 | * This program is free software; you can redistribute it | |
7 | * and/or modify it under the terms of the GNU General Public | |
8 | * License as published by the Free Software Foundation; | |
9 | * either version 2 of the License, or (at your option) any | |
10 | * later version. | |
d9bb3fb1 SB |
11 | * |
12 | * This driver has originally been pushed by Xilinx using a Zynq-branding. This | |
13 | * still shows in the naming of this file, the kconfig symbols and some symbols | |
14 | * in the code. | |
61ec9016 JL |
15 | */ |
16 | ||
0c0c47bc VL |
17 | #if defined(CONFIG_SERIAL_XILINX_PS_UART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) |
18 | #define SUPPORT_SYSRQ | |
19 | #endif | |
20 | ||
61ec9016 | 21 | #include <linux/platform_device.h> |
ee160a38 | 22 | #include <linux/serial.h> |
0c0c47bc | 23 | #include <linux/console.h> |
61ec9016 | 24 | #include <linux/serial_core.h> |
30e1e285 | 25 | #include <linux/slab.h> |
ee160a38 JS |
26 | #include <linux/tty.h> |
27 | #include <linux/tty_flip.h> | |
2326669c | 28 | #include <linux/clk.h> |
61ec9016 JL |
29 | #include <linux/irq.h> |
30 | #include <linux/io.h> | |
31 | #include <linux/of.h> | |
578b9ce0 | 32 | #include <linux/module.h> |
61ec9016 | 33 | |
d9bb3fb1 SB |
34 | #define CDNS_UART_TTY_NAME "ttyPS" |
35 | #define CDNS_UART_NAME "xuartps" | |
36 | #define CDNS_UART_MAJOR 0 /* use dynamic node allocation */ | |
37 | #define CDNS_UART_MINOR 0 /* works best with devtmpfs */ | |
38 | #define CDNS_UART_NR_PORTS 2 | |
39 | #define CDNS_UART_FIFO_SIZE 64 /* FIFO size */ | |
9646e4fe | 40 | #define CDNS_UART_REGISTER_SPACE 0x1000 |
61ec9016 | 41 | |
85baf542 S |
42 | /* Rx Trigger level */ |
43 | static int rx_trigger_level = 56; | |
44 | module_param(rx_trigger_level, uint, S_IRUGO); | |
45 | MODULE_PARM_DESC(rx_trigger_level, "Rx trigger level, 1-63 bytes"); | |
46 | ||
47 | /* Rx Timeout */ | |
48 | static int rx_timeout = 10; | |
49 | module_param(rx_timeout, uint, S_IRUGO); | |
50 | MODULE_PARM_DESC(rx_timeout, "Rx timeout, 1-255"); | |
51 | ||
e555a211 | 52 | /* Register offsets for the UART. */ |
a8df6a51 SB |
53 | #define CDNS_UART_CR 0x00 /* Control Register */ |
54 | #define CDNS_UART_MR 0x04 /* Mode Register */ | |
55 | #define CDNS_UART_IER 0x08 /* Interrupt Enable */ | |
56 | #define CDNS_UART_IDR 0x0C /* Interrupt Disable */ | |
57 | #define CDNS_UART_IMR 0x10 /* Interrupt Mask */ | |
58 | #define CDNS_UART_ISR 0x14 /* Interrupt Status */ | |
59 | #define CDNS_UART_BAUDGEN 0x18 /* Baud Rate Generator */ | |
60 | #define CDNS_UART_RXTOUT 0x1C /* RX Timeout */ | |
61 | #define CDNS_UART_RXWM 0x20 /* RX FIFO Trigger Level */ | |
62 | #define CDNS_UART_MODEMCR 0x24 /* Modem Control */ | |
63 | #define CDNS_UART_MODEMSR 0x28 /* Modem Status */ | |
64 | #define CDNS_UART_SR 0x2C /* Channel Status */ | |
65 | #define CDNS_UART_FIFO 0x30 /* FIFO */ | |
66 | #define CDNS_UART_BAUDDIV 0x34 /* Baud Rate Divider */ | |
67 | #define CDNS_UART_FLOWDEL 0x38 /* Flow Delay */ | |
68 | #define CDNS_UART_IRRX_PWIDTH 0x3C /* IR Min Received Pulse Width */ | |
69 | #define CDNS_UART_IRTX_PWIDTH 0x40 /* IR Transmitted pulse Width */ | |
70 | #define CDNS_UART_TXWM 0x44 /* TX FIFO Trigger Level */ | |
e555a211 SB |
71 | |
72 | /* Control Register Bit Definitions */ | |
d9bb3fb1 SB |
73 | #define CDNS_UART_CR_STOPBRK 0x00000100 /* Stop TX break */ |
74 | #define CDNS_UART_CR_STARTBRK 0x00000080 /* Set TX break */ | |
75 | #define CDNS_UART_CR_TX_DIS 0x00000020 /* TX disabled. */ | |
76 | #define CDNS_UART_CR_TX_EN 0x00000010 /* TX enabled */ | |
77 | #define CDNS_UART_CR_RX_DIS 0x00000008 /* RX disabled. */ | |
78 | #define CDNS_UART_CR_RX_EN 0x00000004 /* RX enabled */ | |
79 | #define CDNS_UART_CR_TXRST 0x00000002 /* TX logic reset */ | |
80 | #define CDNS_UART_CR_RXRST 0x00000001 /* RX logic reset */ | |
81 | #define CDNS_UART_CR_RST_TO 0x00000040 /* Restart Timeout Counter */ | |
61ec9016 | 82 | |
e555a211 SB |
83 | /* |
84 | * Mode Register: | |
61ec9016 JL |
85 | * The mode register (MR) defines the mode of transfer as well as the data |
86 | * format. If this register is modified during transmission or reception, | |
87 | * data validity cannot be guaranteed. | |
61ec9016 | 88 | */ |
d9bb3fb1 SB |
89 | #define CDNS_UART_MR_CLKSEL 0x00000001 /* Pre-scalar selection */ |
90 | #define CDNS_UART_MR_CHMODE_L_LOOP 0x00000200 /* Local loop back mode */ | |
91 | #define CDNS_UART_MR_CHMODE_NORM 0x00000000 /* Normal mode */ | |
61ec9016 | 92 | |
d9bb3fb1 SB |
93 | #define CDNS_UART_MR_STOPMODE_2_BIT 0x00000080 /* 2 stop bits */ |
94 | #define CDNS_UART_MR_STOPMODE_1_BIT 0x00000000 /* 1 stop bit */ | |
61ec9016 | 95 | |
d9bb3fb1 SB |
96 | #define CDNS_UART_MR_PARITY_NONE 0x00000020 /* No parity mode */ |
97 | #define CDNS_UART_MR_PARITY_MARK 0x00000018 /* Mark parity mode */ | |
98 | #define CDNS_UART_MR_PARITY_SPACE 0x00000010 /* Space parity mode */ | |
99 | #define CDNS_UART_MR_PARITY_ODD 0x00000008 /* Odd parity mode */ | |
100 | #define CDNS_UART_MR_PARITY_EVEN 0x00000000 /* Even parity mode */ | |
61ec9016 | 101 | |
d9bb3fb1 SB |
102 | #define CDNS_UART_MR_CHARLEN_6_BIT 0x00000006 /* 6 bits data */ |
103 | #define CDNS_UART_MR_CHARLEN_7_BIT 0x00000004 /* 7 bits data */ | |
104 | #define CDNS_UART_MR_CHARLEN_8_BIT 0x00000000 /* 8 bits data */ | |
61ec9016 | 105 | |
e555a211 SB |
106 | /* |
107 | * Interrupt Registers: | |
61ec9016 JL |
108 | * Interrupt control logic uses the interrupt enable register (IER) and the |
109 | * interrupt disable register (IDR) to set the value of the bits in the | |
110 | * interrupt mask register (IMR). The IMR determines whether to pass an | |
111 | * interrupt to the interrupt status register (ISR). | |
112 | * Writing a 1 to IER Enables an interrupt, writing a 1 to IDR disables an | |
113 | * interrupt. IMR and ISR are read only, and IER and IDR are write only. | |
114 | * Reading either IER or IDR returns 0x00. | |
61ec9016 JL |
115 | * All four registers have the same bit definitions. |
116 | */ | |
d9bb3fb1 SB |
117 | #define CDNS_UART_IXR_TOUT 0x00000100 /* RX Timeout error interrupt */ |
118 | #define CDNS_UART_IXR_PARITY 0x00000080 /* Parity error interrupt */ | |
119 | #define CDNS_UART_IXR_FRAMING 0x00000040 /* Framing error interrupt */ | |
120 | #define CDNS_UART_IXR_OVERRUN 0x00000020 /* Overrun error interrupt */ | |
121 | #define CDNS_UART_IXR_TXFULL 0x00000010 /* TX FIFO Full interrupt */ | |
122 | #define CDNS_UART_IXR_TXEMPTY 0x00000008 /* TX FIFO empty interrupt */ | |
123 | #define CDNS_UART_ISR_RXEMPTY 0x00000002 /* RX FIFO empty interrupt */ | |
124 | #define CDNS_UART_IXR_RXTRIG 0x00000001 /* RX FIFO trigger interrupt */ | |
125 | #define CDNS_UART_IXR_RXFULL 0x00000004 /* RX FIFO full interrupt. */ | |
126 | #define CDNS_UART_IXR_RXEMPTY 0x00000002 /* RX FIFO empty interrupt. */ | |
127 | #define CDNS_UART_IXR_MASK 0x00001FFF /* Valid bit mask */ | |
61ec9016 | 128 | |
373e882f SB |
129 | #define CDNS_UART_RX_IRQS (CDNS_UART_IXR_PARITY | CDNS_UART_IXR_FRAMING | \ |
130 | CDNS_UART_IXR_OVERRUN | CDNS_UART_IXR_RXTRIG | \ | |
131 | CDNS_UART_IXR_TOUT) | |
132 | ||
0c0c47bc | 133 | /* Goes in read_status_mask for break detection as the HW doesn't do it*/ |
d9bb3fb1 | 134 | #define CDNS_UART_IXR_BRK 0x80000000 |
0c0c47bc | 135 | |
19038ad9 LPC |
136 | /* |
137 | * Modem Control register: | |
138 | * The read/write Modem Control register controls the interface with the modem | |
139 | * or data set, or a peripheral device emulating a modem. | |
140 | */ | |
141 | #define CDNS_UART_MODEMCR_FCM 0x00000020 /* Automatic flow control mode */ | |
142 | #define CDNS_UART_MODEMCR_RTS 0x00000002 /* Request to send output control */ | |
143 | #define CDNS_UART_MODEMCR_DTR 0x00000001 /* Data Terminal Ready */ | |
144 | ||
e555a211 SB |
145 | /* |
146 | * Channel Status Register: | |
61ec9016 JL |
147 | * The channel status register (CSR) is provided to enable the control logic |
148 | * to monitor the status of bits in the channel interrupt status register, | |
149 | * even if these are masked out by the interrupt mask register. | |
150 | */ | |
d9bb3fb1 SB |
151 | #define CDNS_UART_SR_RXEMPTY 0x00000002 /* RX FIFO empty */ |
152 | #define CDNS_UART_SR_TXEMPTY 0x00000008 /* TX FIFO empty */ | |
153 | #define CDNS_UART_SR_TXFULL 0x00000010 /* TX FIFO full */ | |
154 | #define CDNS_UART_SR_RXTRIG 0x00000001 /* Rx Trigger */ | |
61ec9016 | 155 | |
e6b39bfd | 156 | /* baud dividers min/max values */ |
d9bb3fb1 SB |
157 | #define CDNS_UART_BDIV_MIN 4 |
158 | #define CDNS_UART_BDIV_MAX 255 | |
159 | #define CDNS_UART_CD_MAX 65535 | |
e6b39bfd | 160 | |
30e1e285 | 161 | /** |
d9bb3fb1 | 162 | * struct cdns_uart - device data |
489810a1 | 163 | * @port: Pointer to the UART port |
d9bb3fb1 SB |
164 | * @uartclk: Reference clock |
165 | * @pclk: APB clock | |
489810a1 MS |
166 | * @baud: Current baud rate |
167 | * @clk_rate_change_nb: Notifier block for clock changes | |
30e1e285 | 168 | */ |
d9bb3fb1 | 169 | struct cdns_uart { |
c4b0510c | 170 | struct uart_port *port; |
d9bb3fb1 SB |
171 | struct clk *uartclk; |
172 | struct clk *pclk; | |
c4b0510c SB |
173 | unsigned int baud; |
174 | struct notifier_block clk_rate_change_nb; | |
30e1e285 | 175 | }; |
d9bb3fb1 SB |
176 | #define to_cdns_uart(_nb) container_of(_nb, struct cdns_uart, \ |
177 | clk_rate_change_nb); | |
30e1e285 | 178 | |
5ede4a5c | 179 | static void cdns_uart_handle_rx(struct uart_port *port, unsigned int isrstatus) |
61ec9016 | 180 | { |
0c0c47bc VL |
181 | /* |
182 | * There is no hardware break detection, so we interpret framing | |
183 | * error with all-zeros data as a break sequence. Most of the time, | |
184 | * there's another non-zero byte at the end of the sequence. | |
185 | */ | |
d9bb3fb1 | 186 | if (isrstatus & CDNS_UART_IXR_FRAMING) { |
a8df6a51 | 187 | while (!(readl(port->membase + CDNS_UART_SR) & |
d9bb3fb1 | 188 | CDNS_UART_SR_RXEMPTY)) { |
a8df6a51 | 189 | if (!readl(port->membase + CDNS_UART_FIFO)) { |
d9bb3fb1 SB |
190 | port->read_status_mask |= CDNS_UART_IXR_BRK; |
191 | isrstatus &= ~CDNS_UART_IXR_FRAMING; | |
0c0c47bc VL |
192 | } |
193 | } | |
a8df6a51 | 194 | writel(CDNS_UART_IXR_FRAMING, port->membase + CDNS_UART_ISR); |
0c0c47bc VL |
195 | } |
196 | ||
61ec9016 | 197 | /* drop byte with parity error if IGNPAR specified */ |
d9bb3fb1 SB |
198 | if (isrstatus & port->ignore_status_mask & CDNS_UART_IXR_PARITY) |
199 | isrstatus &= ~(CDNS_UART_IXR_RXTRIG | CDNS_UART_IXR_TOUT); | |
61ec9016 JL |
200 | |
201 | isrstatus &= port->read_status_mask; | |
202 | isrstatus &= ~port->ignore_status_mask; | |
203 | ||
354fb1a7 SB |
204 | if (!(isrstatus & (CDNS_UART_IXR_TOUT | CDNS_UART_IXR_RXTRIG))) |
205 | return; | |
206 | ||
a8df6a51 | 207 | while (!(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_RXEMPTY)) { |
354fb1a7 SB |
208 | u32 data; |
209 | char status = TTY_NORMAL; | |
210 | ||
a8df6a51 | 211 | data = readl(port->membase + CDNS_UART_FIFO); |
354fb1a7 SB |
212 | |
213 | /* Non-NULL byte after BREAK is garbage (99%) */ | |
214 | if (data && (port->read_status_mask & CDNS_UART_IXR_BRK)) { | |
215 | port->read_status_mask &= ~CDNS_UART_IXR_BRK; | |
216 | port->icount.brk++; | |
217 | if (uart_handle_break(port)) | |
218 | continue; | |
219 | } | |
0c0c47bc | 220 | |
74ea66d4 SB |
221 | if (uart_handle_sysrq_char(port, data)) |
222 | continue; | |
0c0c47bc | 223 | |
354fb1a7 | 224 | port->icount.rx++; |
61ec9016 | 225 | |
354fb1a7 SB |
226 | if (isrstatus & CDNS_UART_IXR_PARITY) { |
227 | port->icount.parity++; | |
228 | status = TTY_PARITY; | |
229 | } else if (isrstatus & CDNS_UART_IXR_FRAMING) { | |
230 | port->icount.frame++; | |
231 | status = TTY_FRAME; | |
232 | } else if (isrstatus & CDNS_UART_IXR_OVERRUN) { | |
233 | port->icount.overrun++; | |
61ec9016 | 234 | } |
354fb1a7 SB |
235 | |
236 | uart_insert_char(port, isrstatus, CDNS_UART_IXR_OVERRUN, | |
237 | data, status); | |
61ec9016 | 238 | } |
354fb1a7 | 239 | tty_flip_buffer_push(&port->state->port); |
5ede4a5c SB |
240 | } |
241 | ||
242 | /** | |
243 | * cdns_uart_isr - Interrupt handler | |
244 | * @irq: Irq number | |
245 | * @dev_id: Id of the port | |
246 | * | |
247 | * Return: IRQHANDLED | |
248 | */ | |
249 | static irqreturn_t cdns_uart_isr(int irq, void *dev_id) | |
250 | { | |
251 | struct uart_port *port = (struct uart_port *)dev_id; | |
252 | unsigned long flags; | |
253 | unsigned int isrstatus, numbytes; | |
254 | ||
255 | spin_lock_irqsave(&port->lock, flags); | |
256 | ||
257 | /* Read the interrupt status register to determine which | |
258 | * interrupt(s) is/are active. | |
259 | */ | |
a8df6a51 | 260 | isrstatus = readl(port->membase + CDNS_UART_ISR); |
5ede4a5c | 261 | |
373e882f SB |
262 | if (isrstatus & CDNS_UART_RX_IRQS) |
263 | cdns_uart_handle_rx(port, isrstatus); | |
61ec9016 JL |
264 | |
265 | /* Dispatch an appropriate handler */ | |
d9bb3fb1 | 266 | if ((isrstatus & CDNS_UART_IXR_TXEMPTY) == CDNS_UART_IXR_TXEMPTY) { |
61ec9016 | 267 | if (uart_circ_empty(&port->state->xmit)) { |
19f22efd | 268 | writel(CDNS_UART_IXR_TXEMPTY, |
a8df6a51 | 269 | port->membase + CDNS_UART_IDR); |
61ec9016 JL |
270 | } else { |
271 | numbytes = port->fifosize; | |
272 | /* Break if no more data available in the UART buffer */ | |
273 | while (numbytes--) { | |
274 | if (uart_circ_empty(&port->state->xmit)) | |
275 | break; | |
276 | /* Get the data from the UART circular buffer | |
d9bb3fb1 | 277 | * and write it to the cdns_uart's TX_FIFO |
61ec9016 JL |
278 | * register. |
279 | */ | |
19f22efd TB |
280 | writel(port->state->xmit.buf[ |
281 | port->state->xmit.tail], | |
a8df6a51 | 282 | port->membase + CDNS_UART_FIFO); |
61ec9016 JL |
283 | |
284 | port->icount.tx++; | |
285 | ||
286 | /* Adjust the tail of the UART buffer and wrap | |
287 | * the buffer if it reaches limit. | |
288 | */ | |
289 | port->state->xmit.tail = | |
e555a211 | 290 | (port->state->xmit.tail + 1) & |
61ec9016 JL |
291 | (UART_XMIT_SIZE - 1); |
292 | } | |
293 | ||
294 | if (uart_circ_chars_pending( | |
295 | &port->state->xmit) < WAKEUP_CHARS) | |
296 | uart_write_wakeup(port); | |
297 | } | |
298 | } | |
299 | ||
a8df6a51 | 300 | writel(isrstatus, port->membase + CDNS_UART_ISR); |
61ec9016 JL |
301 | |
302 | /* be sure to release the lock and tty before leaving */ | |
303 | spin_unlock_irqrestore(&port->lock, flags); | |
61ec9016 JL |
304 | |
305 | return IRQ_HANDLED; | |
306 | } | |
307 | ||
308 | /** | |
d9bb3fb1 | 309 | * cdns_uart_calc_baud_divs - Calculate baud rate divisors |
e6b39bfd SB |
310 | * @clk: UART module input clock |
311 | * @baud: Desired baud rate | |
312 | * @rbdiv: BDIV value (return value) | |
313 | * @rcd: CD value (return value) | |
314 | * @div8: Value for clk_sel bit in mod (return value) | |
489810a1 | 315 | * Return: baud rate, requested baud when possible, or actual baud when there |
e6b39bfd SB |
316 | * was too much error, zero if no valid divisors are found. |
317 | * | |
318 | * Formula to obtain baud rate is | |
319 | * baud_tx/rx rate = clk/CD * (BDIV + 1) | |
320 | * input_clk = (Uart User Defined Clock or Apb Clock) | |
321 | * depends on UCLKEN in MR Reg | |
322 | * clk = input_clk or input_clk/8; | |
323 | * depends on CLKS in MR reg | |
324 | * CD and BDIV depends on values in | |
325 | * baud rate generate register | |
326 | * baud rate clock divisor register | |
327 | */ | |
d9bb3fb1 SB |
328 | static unsigned int cdns_uart_calc_baud_divs(unsigned int clk, |
329 | unsigned int baud, u32 *rbdiv, u32 *rcd, int *div8) | |
61ec9016 | 330 | { |
e6b39bfd SB |
331 | u32 cd, bdiv; |
332 | unsigned int calc_baud; | |
333 | unsigned int bestbaud = 0; | |
61ec9016 | 334 | unsigned int bauderror; |
e6b39bfd | 335 | unsigned int besterror = ~0; |
61ec9016 | 336 | |
d9bb3fb1 | 337 | if (baud < clk / ((CDNS_UART_BDIV_MAX + 1) * CDNS_UART_CD_MAX)) { |
e6b39bfd SB |
338 | *div8 = 1; |
339 | clk /= 8; | |
340 | } else { | |
341 | *div8 = 0; | |
342 | } | |
61ec9016 | 343 | |
d9bb3fb1 | 344 | for (bdiv = CDNS_UART_BDIV_MIN; bdiv <= CDNS_UART_BDIV_MAX; bdiv++) { |
e6b39bfd | 345 | cd = DIV_ROUND_CLOSEST(clk, baud * (bdiv + 1)); |
d9bb3fb1 | 346 | if (cd < 1 || cd > CDNS_UART_CD_MAX) |
61ec9016 JL |
347 | continue; |
348 | ||
e6b39bfd | 349 | calc_baud = clk / (cd * (bdiv + 1)); |
61ec9016 JL |
350 | |
351 | if (baud > calc_baud) | |
352 | bauderror = baud - calc_baud; | |
353 | else | |
354 | bauderror = calc_baud - baud; | |
355 | ||
e6b39bfd SB |
356 | if (besterror > bauderror) { |
357 | *rbdiv = bdiv; | |
358 | *rcd = cd; | |
359 | bestbaud = calc_baud; | |
360 | besterror = bauderror; | |
61ec9016 JL |
361 | } |
362 | } | |
e6b39bfd SB |
363 | /* use the values when percent error is acceptable */ |
364 | if (((besterror * 100) / baud) < 3) | |
365 | bestbaud = baud; | |
366 | ||
367 | return bestbaud; | |
368 | } | |
61ec9016 | 369 | |
e6b39bfd | 370 | /** |
d9bb3fb1 | 371 | * cdns_uart_set_baud_rate - Calculate and set the baud rate |
e6b39bfd SB |
372 | * @port: Handle to the uart port structure |
373 | * @baud: Baud rate to set | |
489810a1 | 374 | * Return: baud rate, requested baud when possible, or actual baud when there |
e6b39bfd SB |
375 | * was too much error, zero if no valid divisors are found. |
376 | */ | |
d9bb3fb1 | 377 | static unsigned int cdns_uart_set_baud_rate(struct uart_port *port, |
e6b39bfd SB |
378 | unsigned int baud) |
379 | { | |
380 | unsigned int calc_baud; | |
d54b181e | 381 | u32 cd = 0, bdiv = 0; |
e6b39bfd SB |
382 | u32 mreg; |
383 | int div8; | |
d9bb3fb1 | 384 | struct cdns_uart *cdns_uart = port->private_data; |
e6b39bfd | 385 | |
d9bb3fb1 | 386 | calc_baud = cdns_uart_calc_baud_divs(port->uartclk, baud, &bdiv, &cd, |
e6b39bfd SB |
387 | &div8); |
388 | ||
389 | /* Write new divisors to hardware */ | |
a8df6a51 | 390 | mreg = readl(port->membase + CDNS_UART_MR); |
e6b39bfd | 391 | if (div8) |
d9bb3fb1 | 392 | mreg |= CDNS_UART_MR_CLKSEL; |
e6b39bfd | 393 | else |
d9bb3fb1 | 394 | mreg &= ~CDNS_UART_MR_CLKSEL; |
a8df6a51 SB |
395 | writel(mreg, port->membase + CDNS_UART_MR); |
396 | writel(cd, port->membase + CDNS_UART_BAUDGEN); | |
397 | writel(bdiv, port->membase + CDNS_UART_BAUDDIV); | |
d9bb3fb1 | 398 | cdns_uart->baud = baud; |
61ec9016 JL |
399 | |
400 | return calc_baud; | |
401 | } | |
402 | ||
7ac57347 | 403 | #ifdef CONFIG_COMMON_CLK |
c4b0510c | 404 | /** |
d9bb3fb1 | 405 | * cdns_uart_clk_notitifer_cb - Clock notifier callback |
c4b0510c SB |
406 | * @nb: Notifier block |
407 | * @event: Notify event | |
408 | * @data: Notifier data | |
e555a211 | 409 | * Return: NOTIFY_OK or NOTIFY_DONE on success, NOTIFY_BAD on error. |
c4b0510c | 410 | */ |
d9bb3fb1 | 411 | static int cdns_uart_clk_notifier_cb(struct notifier_block *nb, |
c4b0510c SB |
412 | unsigned long event, void *data) |
413 | { | |
414 | u32 ctrl_reg; | |
415 | struct uart_port *port; | |
416 | int locked = 0; | |
417 | struct clk_notifier_data *ndata = data; | |
418 | unsigned long flags = 0; | |
d9bb3fb1 | 419 | struct cdns_uart *cdns_uart = to_cdns_uart(nb); |
c4b0510c | 420 | |
d9bb3fb1 | 421 | port = cdns_uart->port; |
c4b0510c SB |
422 | if (port->suspended) |
423 | return NOTIFY_OK; | |
424 | ||
425 | switch (event) { | |
426 | case PRE_RATE_CHANGE: | |
427 | { | |
e555a211 | 428 | u32 bdiv, cd; |
c4b0510c SB |
429 | int div8; |
430 | ||
431 | /* | |
432 | * Find out if current baud-rate can be achieved with new clock | |
433 | * frequency. | |
434 | */ | |
d9bb3fb1 | 435 | if (!cdns_uart_calc_baud_divs(ndata->new_rate, cdns_uart->baud, |
5ce15d2d SB |
436 | &bdiv, &cd, &div8)) { |
437 | dev_warn(port->dev, "clock rate change rejected\n"); | |
c4b0510c | 438 | return NOTIFY_BAD; |
5ce15d2d | 439 | } |
c4b0510c | 440 | |
d9bb3fb1 | 441 | spin_lock_irqsave(&cdns_uart->port->lock, flags); |
c4b0510c SB |
442 | |
443 | /* Disable the TX and RX to set baud rate */ | |
a8df6a51 | 444 | ctrl_reg = readl(port->membase + CDNS_UART_CR); |
d9bb3fb1 | 445 | ctrl_reg |= CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS; |
a8df6a51 | 446 | writel(ctrl_reg, port->membase + CDNS_UART_CR); |
c4b0510c | 447 | |
d9bb3fb1 | 448 | spin_unlock_irqrestore(&cdns_uart->port->lock, flags); |
c4b0510c SB |
449 | |
450 | return NOTIFY_OK; | |
451 | } | |
452 | case POST_RATE_CHANGE: | |
453 | /* | |
454 | * Set clk dividers to generate correct baud with new clock | |
455 | * frequency. | |
456 | */ | |
457 | ||
d9bb3fb1 | 458 | spin_lock_irqsave(&cdns_uart->port->lock, flags); |
c4b0510c SB |
459 | |
460 | locked = 1; | |
461 | port->uartclk = ndata->new_rate; | |
462 | ||
d9bb3fb1 SB |
463 | cdns_uart->baud = cdns_uart_set_baud_rate(cdns_uart->port, |
464 | cdns_uart->baud); | |
c4b0510c SB |
465 | /* fall through */ |
466 | case ABORT_RATE_CHANGE: | |
467 | if (!locked) | |
d9bb3fb1 | 468 | spin_lock_irqsave(&cdns_uart->port->lock, flags); |
c4b0510c SB |
469 | |
470 | /* Set TX/RX Reset */ | |
a8df6a51 | 471 | ctrl_reg = readl(port->membase + CDNS_UART_CR); |
d9bb3fb1 | 472 | ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST; |
a8df6a51 | 473 | writel(ctrl_reg, port->membase + CDNS_UART_CR); |
c4b0510c | 474 | |
a8df6a51 | 475 | while (readl(port->membase + CDNS_UART_CR) & |
d9bb3fb1 | 476 | (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST)) |
c4b0510c SB |
477 | cpu_relax(); |
478 | ||
479 | /* | |
480 | * Clear the RX disable and TX disable bits and then set the TX | |
481 | * enable bit and RX enable bit to enable the transmitter and | |
482 | * receiver. | |
483 | */ | |
a8df6a51 SB |
484 | writel(rx_timeout, port->membase + CDNS_UART_RXTOUT); |
485 | ctrl_reg = readl(port->membase + CDNS_UART_CR); | |
d9bb3fb1 SB |
486 | ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS); |
487 | ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN; | |
a8df6a51 | 488 | writel(ctrl_reg, port->membase + CDNS_UART_CR); |
c4b0510c | 489 | |
d9bb3fb1 | 490 | spin_unlock_irqrestore(&cdns_uart->port->lock, flags); |
c4b0510c SB |
491 | |
492 | return NOTIFY_OK; | |
493 | default: | |
494 | return NOTIFY_DONE; | |
495 | } | |
496 | } | |
7ac57347 | 497 | #endif |
c4b0510c | 498 | |
61ec9016 | 499 | /** |
d9bb3fb1 | 500 | * cdns_uart_start_tx - Start transmitting bytes |
61ec9016 | 501 | * @port: Handle to the uart port structure |
489810a1 | 502 | */ |
d9bb3fb1 | 503 | static void cdns_uart_start_tx(struct uart_port *port) |
61ec9016 JL |
504 | { |
505 | unsigned int status, numbytes = port->fifosize; | |
506 | ||
ea8dd8e5 | 507 | if (uart_tx_stopped(port)) |
61ec9016 JL |
508 | return; |
509 | ||
e3538c37 SB |
510 | /* |
511 | * Set the TX enable bit and clear the TX disable bit to enable the | |
61ec9016 JL |
512 | * transmitter. |
513 | */ | |
a8df6a51 | 514 | status = readl(port->membase + CDNS_UART_CR); |
e3538c37 SB |
515 | status &= ~CDNS_UART_CR_TX_DIS; |
516 | status |= CDNS_UART_CR_TX_EN; | |
a8df6a51 | 517 | writel(status, port->membase + CDNS_UART_CR); |
61ec9016 | 518 | |
ea8dd8e5 SB |
519 | if (uart_circ_empty(&port->state->xmit)) |
520 | return; | |
521 | ||
a8df6a51 | 522 | while (numbytes-- && ((readl(port->membase + CDNS_UART_SR) & |
d9bb3fb1 | 523 | CDNS_UART_SR_TXFULL)) != CDNS_UART_SR_TXFULL) { |
61ec9016 JL |
524 | /* Break if no more data available in the UART buffer */ |
525 | if (uart_circ_empty(&port->state->xmit)) | |
526 | break; | |
527 | ||
528 | /* Get the data from the UART circular buffer and | |
d9bb3fb1 | 529 | * write it to the cdns_uart's TX_FIFO register. |
61ec9016 | 530 | */ |
19f22efd | 531 | writel(port->state->xmit.buf[port->state->xmit.tail], |
a8df6a51 | 532 | port->membase + CDNS_UART_FIFO); |
61ec9016 JL |
533 | port->icount.tx++; |
534 | ||
535 | /* Adjust the tail of the UART buffer and wrap | |
536 | * the buffer if it reaches limit. | |
537 | */ | |
538 | port->state->xmit.tail = (port->state->xmit.tail + 1) & | |
539 | (UART_XMIT_SIZE - 1); | |
540 | } | |
a8df6a51 | 541 | writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_ISR); |
61ec9016 | 542 | /* Enable the TX Empty interrupt */ |
a8df6a51 | 543 | writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_IER); |
61ec9016 JL |
544 | |
545 | if (uart_circ_chars_pending(&port->state->xmit) < WAKEUP_CHARS) | |
546 | uart_write_wakeup(port); | |
547 | } | |
548 | ||
549 | /** | |
d9bb3fb1 | 550 | * cdns_uart_stop_tx - Stop TX |
61ec9016 | 551 | * @port: Handle to the uart port structure |
489810a1 | 552 | */ |
d9bb3fb1 | 553 | static void cdns_uart_stop_tx(struct uart_port *port) |
61ec9016 JL |
554 | { |
555 | unsigned int regval; | |
556 | ||
a8df6a51 | 557 | regval = readl(port->membase + CDNS_UART_CR); |
d9bb3fb1 | 558 | regval |= CDNS_UART_CR_TX_DIS; |
61ec9016 | 559 | /* Disable the transmitter */ |
a8df6a51 | 560 | writel(regval, port->membase + CDNS_UART_CR); |
61ec9016 JL |
561 | } |
562 | ||
563 | /** | |
d9bb3fb1 | 564 | * cdns_uart_stop_rx - Stop RX |
61ec9016 | 565 | * @port: Handle to the uart port structure |
489810a1 | 566 | */ |
d9bb3fb1 | 567 | static void cdns_uart_stop_rx(struct uart_port *port) |
61ec9016 JL |
568 | { |
569 | unsigned int regval; | |
570 | ||
373e882f | 571 | /* Disable RX IRQs */ |
a8df6a51 | 572 | writel(CDNS_UART_RX_IRQS, port->membase + CDNS_UART_IDR); |
373e882f SB |
573 | |
574 | /* Disable the receiver */ | |
a8df6a51 | 575 | regval = readl(port->membase + CDNS_UART_CR); |
d9bb3fb1 | 576 | regval |= CDNS_UART_CR_RX_DIS; |
a8df6a51 | 577 | writel(regval, port->membase + CDNS_UART_CR); |
61ec9016 JL |
578 | } |
579 | ||
580 | /** | |
d9bb3fb1 | 581 | * cdns_uart_tx_empty - Check whether TX is empty |
61ec9016 JL |
582 | * @port: Handle to the uart port structure |
583 | * | |
489810a1 MS |
584 | * Return: TIOCSER_TEMT on success, 0 otherwise |
585 | */ | |
d9bb3fb1 | 586 | static unsigned int cdns_uart_tx_empty(struct uart_port *port) |
61ec9016 JL |
587 | { |
588 | unsigned int status; | |
589 | ||
a8df6a51 | 590 | status = readl(port->membase + CDNS_UART_SR) & |
19f22efd | 591 | CDNS_UART_SR_TXEMPTY; |
61ec9016 JL |
592 | return status ? TIOCSER_TEMT : 0; |
593 | } | |
594 | ||
595 | /** | |
d9bb3fb1 | 596 | * cdns_uart_break_ctl - Based on the input ctl we have to start or stop |
61ec9016 JL |
597 | * transmitting char breaks |
598 | * @port: Handle to the uart port structure | |
599 | * @ctl: Value based on which start or stop decision is taken | |
489810a1 | 600 | */ |
d9bb3fb1 | 601 | static void cdns_uart_break_ctl(struct uart_port *port, int ctl) |
61ec9016 JL |
602 | { |
603 | unsigned int status; | |
604 | unsigned long flags; | |
605 | ||
606 | spin_lock_irqsave(&port->lock, flags); | |
607 | ||
a8df6a51 | 608 | status = readl(port->membase + CDNS_UART_CR); |
61ec9016 JL |
609 | |
610 | if (ctl == -1) | |
19f22efd | 611 | writel(CDNS_UART_CR_STARTBRK | status, |
a8df6a51 | 612 | port->membase + CDNS_UART_CR); |
61ec9016 | 613 | else { |
d9bb3fb1 | 614 | if ((status & CDNS_UART_CR_STOPBRK) == 0) |
19f22efd | 615 | writel(CDNS_UART_CR_STOPBRK | status, |
a8df6a51 | 616 | port->membase + CDNS_UART_CR); |
61ec9016 JL |
617 | } |
618 | spin_unlock_irqrestore(&port->lock, flags); | |
619 | } | |
620 | ||
621 | /** | |
d9bb3fb1 | 622 | * cdns_uart_set_termios - termios operations, handling data length, parity, |
61ec9016 JL |
623 | * stop bits, flow control, baud rate |
624 | * @port: Handle to the uart port structure | |
625 | * @termios: Handle to the input termios structure | |
626 | * @old: Values of the previously saved termios structure | |
489810a1 | 627 | */ |
d9bb3fb1 | 628 | static void cdns_uart_set_termios(struct uart_port *port, |
61ec9016 JL |
629 | struct ktermios *termios, struct ktermios *old) |
630 | { | |
631 | unsigned int cval = 0; | |
e6b39bfd | 632 | unsigned int baud, minbaud, maxbaud; |
61ec9016 JL |
633 | unsigned long flags; |
634 | unsigned int ctrl_reg, mode_reg; | |
635 | ||
636 | spin_lock_irqsave(&port->lock, flags); | |
637 | ||
6ecde472 | 638 | /* Wait for the transmit FIFO to empty before making changes */ |
a8df6a51 | 639 | if (!(readl(port->membase + CDNS_UART_CR) & |
19f22efd | 640 | CDNS_UART_CR_TX_DIS)) { |
a8df6a51 | 641 | while (!(readl(port->membase + CDNS_UART_SR) & |
6ecde472 NR |
642 | CDNS_UART_SR_TXEMPTY)) { |
643 | cpu_relax(); | |
644 | } | |
61ec9016 JL |
645 | } |
646 | ||
647 | /* Disable the TX and RX to set baud rate */ | |
a8df6a51 | 648 | ctrl_reg = readl(port->membase + CDNS_UART_CR); |
d9bb3fb1 | 649 | ctrl_reg |= CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS; |
a8df6a51 | 650 | writel(ctrl_reg, port->membase + CDNS_UART_CR); |
61ec9016 | 651 | |
e6b39bfd SB |
652 | /* |
653 | * Min baud rate = 6bps and Max Baud Rate is 10Mbps for 100Mhz clk | |
654 | * min and max baud should be calculated here based on port->uartclk. | |
655 | * this way we get a valid baud and can safely call set_baud() | |
656 | */ | |
d9bb3fb1 SB |
657 | minbaud = port->uartclk / |
658 | ((CDNS_UART_BDIV_MAX + 1) * CDNS_UART_CD_MAX * 8); | |
659 | maxbaud = port->uartclk / (CDNS_UART_BDIV_MIN + 1); | |
e6b39bfd | 660 | baud = uart_get_baud_rate(port, termios, old, minbaud, maxbaud); |
d9bb3fb1 | 661 | baud = cdns_uart_set_baud_rate(port, baud); |
61ec9016 JL |
662 | if (tty_termios_baud_rate(termios)) |
663 | tty_termios_encode_baud_rate(termios, baud, baud); | |
664 | ||
e555a211 | 665 | /* Update the per-port timeout. */ |
61ec9016 JL |
666 | uart_update_timeout(port, termios->c_cflag, baud); |
667 | ||
668 | /* Set TX/RX Reset */ | |
a8df6a51 | 669 | ctrl_reg = readl(port->membase + CDNS_UART_CR); |
d9bb3fb1 | 670 | ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST; |
a8df6a51 | 671 | writel(ctrl_reg, port->membase + CDNS_UART_CR); |
61ec9016 | 672 | |
e555a211 SB |
673 | /* |
674 | * Clear the RX disable and TX disable bits and then set the TX enable | |
61ec9016 JL |
675 | * bit and RX enable bit to enable the transmitter and receiver. |
676 | */ | |
a8df6a51 | 677 | ctrl_reg = readl(port->membase + CDNS_UART_CR); |
d9bb3fb1 SB |
678 | ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS); |
679 | ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN; | |
a8df6a51 | 680 | writel(ctrl_reg, port->membase + CDNS_UART_CR); |
61ec9016 | 681 | |
a8df6a51 | 682 | writel(rx_timeout, port->membase + CDNS_UART_RXTOUT); |
61ec9016 | 683 | |
d9bb3fb1 SB |
684 | port->read_status_mask = CDNS_UART_IXR_TXEMPTY | CDNS_UART_IXR_RXTRIG | |
685 | CDNS_UART_IXR_OVERRUN | CDNS_UART_IXR_TOUT; | |
61ec9016 JL |
686 | port->ignore_status_mask = 0; |
687 | ||
688 | if (termios->c_iflag & INPCK) | |
d9bb3fb1 SB |
689 | port->read_status_mask |= CDNS_UART_IXR_PARITY | |
690 | CDNS_UART_IXR_FRAMING; | |
61ec9016 JL |
691 | |
692 | if (termios->c_iflag & IGNPAR) | |
d9bb3fb1 SB |
693 | port->ignore_status_mask |= CDNS_UART_IXR_PARITY | |
694 | CDNS_UART_IXR_FRAMING | CDNS_UART_IXR_OVERRUN; | |
61ec9016 JL |
695 | |
696 | /* ignore all characters if CREAD is not set */ | |
697 | if ((termios->c_cflag & CREAD) == 0) | |
d9bb3fb1 SB |
698 | port->ignore_status_mask |= CDNS_UART_IXR_RXTRIG | |
699 | CDNS_UART_IXR_TOUT | CDNS_UART_IXR_PARITY | | |
700 | CDNS_UART_IXR_FRAMING | CDNS_UART_IXR_OVERRUN; | |
61ec9016 | 701 | |
a8df6a51 | 702 | mode_reg = readl(port->membase + CDNS_UART_MR); |
61ec9016 JL |
703 | |
704 | /* Handling Data Size */ | |
705 | switch (termios->c_cflag & CSIZE) { | |
706 | case CS6: | |
d9bb3fb1 | 707 | cval |= CDNS_UART_MR_CHARLEN_6_BIT; |
61ec9016 JL |
708 | break; |
709 | case CS7: | |
d9bb3fb1 | 710 | cval |= CDNS_UART_MR_CHARLEN_7_BIT; |
61ec9016 JL |
711 | break; |
712 | default: | |
713 | case CS8: | |
d9bb3fb1 | 714 | cval |= CDNS_UART_MR_CHARLEN_8_BIT; |
61ec9016 JL |
715 | termios->c_cflag &= ~CSIZE; |
716 | termios->c_cflag |= CS8; | |
717 | break; | |
718 | } | |
719 | ||
720 | /* Handling Parity and Stop Bits length */ | |
721 | if (termios->c_cflag & CSTOPB) | |
d9bb3fb1 | 722 | cval |= CDNS_UART_MR_STOPMODE_2_BIT; /* 2 STOP bits */ |
61ec9016 | 723 | else |
d9bb3fb1 | 724 | cval |= CDNS_UART_MR_STOPMODE_1_BIT; /* 1 STOP bit */ |
61ec9016 JL |
725 | |
726 | if (termios->c_cflag & PARENB) { | |
727 | /* Mark or Space parity */ | |
728 | if (termios->c_cflag & CMSPAR) { | |
729 | if (termios->c_cflag & PARODD) | |
d9bb3fb1 | 730 | cval |= CDNS_UART_MR_PARITY_MARK; |
61ec9016 | 731 | else |
d9bb3fb1 | 732 | cval |= CDNS_UART_MR_PARITY_SPACE; |
e6b39bfd SB |
733 | } else { |
734 | if (termios->c_cflag & PARODD) | |
d9bb3fb1 | 735 | cval |= CDNS_UART_MR_PARITY_ODD; |
61ec9016 | 736 | else |
d9bb3fb1 | 737 | cval |= CDNS_UART_MR_PARITY_EVEN; |
e6b39bfd SB |
738 | } |
739 | } else { | |
d9bb3fb1 | 740 | cval |= CDNS_UART_MR_PARITY_NONE; |
e6b39bfd SB |
741 | } |
742 | cval |= mode_reg & 1; | |
a8df6a51 | 743 | writel(cval, port->membase + CDNS_UART_MR); |
61ec9016 JL |
744 | |
745 | spin_unlock_irqrestore(&port->lock, flags); | |
746 | } | |
747 | ||
748 | /** | |
d9bb3fb1 | 749 | * cdns_uart_startup - Called when an application opens a cdns_uart port |
61ec9016 JL |
750 | * @port: Handle to the uart port structure |
751 | * | |
e555a211 | 752 | * Return: 0 on success, negative errno otherwise |
489810a1 | 753 | */ |
d9bb3fb1 | 754 | static int cdns_uart_startup(struct uart_port *port) |
61ec9016 | 755 | { |
55861d11 | 756 | int ret; |
6e14f7c1 | 757 | unsigned long flags; |
55861d11 | 758 | unsigned int status = 0; |
61ec9016 | 759 | |
6e14f7c1 SB |
760 | spin_lock_irqsave(&port->lock, flags); |
761 | ||
61ec9016 | 762 | /* Disable the TX and RX */ |
19f22efd | 763 | writel(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS, |
a8df6a51 | 764 | port->membase + CDNS_UART_CR); |
61ec9016 JL |
765 | |
766 | /* Set the Control Register with TX/RX Enable, TX/RX Reset, | |
767 | * no break chars. | |
768 | */ | |
19f22efd | 769 | writel(CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST, |
a8df6a51 | 770 | port->membase + CDNS_UART_CR); |
61ec9016 | 771 | |
6e14f7c1 SB |
772 | /* |
773 | * Clear the RX disable bit and then set the RX enable bit to enable | |
774 | * the receiver. | |
61ec9016 | 775 | */ |
a8df6a51 | 776 | status = readl(port->membase + CDNS_UART_CR); |
6e14f7c1 SB |
777 | status &= CDNS_UART_CR_RX_DIS; |
778 | status |= CDNS_UART_CR_RX_EN; | |
a8df6a51 | 779 | writel(status, port->membase + CDNS_UART_CR); |
61ec9016 JL |
780 | |
781 | /* Set the Mode Register with normal mode,8 data bits,1 stop bit, | |
782 | * no parity. | |
783 | */ | |
19f22efd | 784 | writel(CDNS_UART_MR_CHMODE_NORM | CDNS_UART_MR_STOPMODE_1_BIT |
d9bb3fb1 | 785 | | CDNS_UART_MR_PARITY_NONE | CDNS_UART_MR_CHARLEN_8_BIT, |
a8df6a51 | 786 | port->membase + CDNS_UART_MR); |
61ec9016 | 787 | |
85baf542 S |
788 | /* |
789 | * Set the RX FIFO Trigger level to use most of the FIFO, but it | |
790 | * can be tuned with a module parameter | |
791 | */ | |
a8df6a51 | 792 | writel(rx_trigger_level, port->membase + CDNS_UART_RXWM); |
61ec9016 | 793 | |
85baf542 S |
794 | /* |
795 | * Receive Timeout register is enabled but it | |
796 | * can be tuned with a module parameter | |
797 | */ | |
a8df6a51 | 798 | writel(rx_timeout, port->membase + CDNS_UART_RXTOUT); |
61ec9016 | 799 | |
855f6fd9 | 800 | /* Clear out any pending interrupts before enabling them */ |
a8df6a51 SB |
801 | writel(readl(port->membase + CDNS_UART_ISR), |
802 | port->membase + CDNS_UART_ISR); | |
61ec9016 | 803 | |
55861d11 SB |
804 | spin_unlock_irqrestore(&port->lock, flags); |
805 | ||
806 | ret = request_irq(port->irq, cdns_uart_isr, 0, CDNS_UART_NAME, port); | |
807 | if (ret) { | |
808 | dev_err(port->dev, "request_irq '%d' failed with %d\n", | |
809 | port->irq, ret); | |
810 | return ret; | |
811 | } | |
812 | ||
61ec9016 | 813 | /* Set the Interrupt Registers with desired interrupts */ |
a8df6a51 | 814 | writel(CDNS_UART_RX_IRQS, port->membase + CDNS_UART_IER); |
61ec9016 | 815 | |
55861d11 | 816 | return 0; |
61ec9016 JL |
817 | } |
818 | ||
819 | /** | |
d9bb3fb1 | 820 | * cdns_uart_shutdown - Called when an application closes a cdns_uart port |
61ec9016 | 821 | * @port: Handle to the uart port structure |
489810a1 | 822 | */ |
d9bb3fb1 | 823 | static void cdns_uart_shutdown(struct uart_port *port) |
61ec9016 JL |
824 | { |
825 | int status; | |
a19eda0f SB |
826 | unsigned long flags; |
827 | ||
828 | spin_lock_irqsave(&port->lock, flags); | |
61ec9016 JL |
829 | |
830 | /* Disable interrupts */ | |
a8df6a51 SB |
831 | status = readl(port->membase + CDNS_UART_IMR); |
832 | writel(status, port->membase + CDNS_UART_IDR); | |
833 | writel(0xffffffff, port->membase + CDNS_UART_ISR); | |
61ec9016 JL |
834 | |
835 | /* Disable the TX and RX */ | |
19f22efd | 836 | writel(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS, |
a8df6a51 | 837 | port->membase + CDNS_UART_CR); |
a19eda0f SB |
838 | |
839 | spin_unlock_irqrestore(&port->lock, flags); | |
840 | ||
61ec9016 JL |
841 | free_irq(port->irq, port); |
842 | } | |
843 | ||
844 | /** | |
d9bb3fb1 | 845 | * cdns_uart_type - Set UART type to cdns_uart port |
61ec9016 JL |
846 | * @port: Handle to the uart port structure |
847 | * | |
489810a1 MS |
848 | * Return: string on success, NULL otherwise |
849 | */ | |
d9bb3fb1 | 850 | static const char *cdns_uart_type(struct uart_port *port) |
61ec9016 | 851 | { |
d9bb3fb1 | 852 | return port->type == PORT_XUARTPS ? CDNS_UART_NAME : NULL; |
61ec9016 JL |
853 | } |
854 | ||
855 | /** | |
d9bb3fb1 | 856 | * cdns_uart_verify_port - Verify the port params |
61ec9016 JL |
857 | * @port: Handle to the uart port structure |
858 | * @ser: Handle to the structure whose members are compared | |
859 | * | |
e555a211 | 860 | * Return: 0 on success, negative errno otherwise. |
489810a1 | 861 | */ |
d9bb3fb1 | 862 | static int cdns_uart_verify_port(struct uart_port *port, |
61ec9016 JL |
863 | struct serial_struct *ser) |
864 | { | |
865 | if (ser->type != PORT_UNKNOWN && ser->type != PORT_XUARTPS) | |
866 | return -EINVAL; | |
867 | if (port->irq != ser->irq) | |
868 | return -EINVAL; | |
869 | if (ser->io_type != UPIO_MEM) | |
870 | return -EINVAL; | |
871 | if (port->iobase != ser->port) | |
872 | return -EINVAL; | |
873 | if (ser->hub6 != 0) | |
874 | return -EINVAL; | |
875 | return 0; | |
876 | } | |
877 | ||
878 | /** | |
d9bb3fb1 SB |
879 | * cdns_uart_request_port - Claim the memory region attached to cdns_uart port, |
880 | * called when the driver adds a cdns_uart port via | |
61ec9016 JL |
881 | * uart_add_one_port() |
882 | * @port: Handle to the uart port structure | |
883 | * | |
e555a211 | 884 | * Return: 0 on success, negative errno otherwise. |
489810a1 | 885 | */ |
d9bb3fb1 | 886 | static int cdns_uart_request_port(struct uart_port *port) |
61ec9016 | 887 | { |
d9bb3fb1 SB |
888 | if (!request_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE, |
889 | CDNS_UART_NAME)) { | |
61ec9016 JL |
890 | return -ENOMEM; |
891 | } | |
892 | ||
d9bb3fb1 | 893 | port->membase = ioremap(port->mapbase, CDNS_UART_REGISTER_SPACE); |
61ec9016 JL |
894 | if (!port->membase) { |
895 | dev_err(port->dev, "Unable to map registers\n"); | |
d9bb3fb1 | 896 | release_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE); |
61ec9016 JL |
897 | return -ENOMEM; |
898 | } | |
899 | return 0; | |
900 | } | |
901 | ||
902 | /** | |
d9bb3fb1 | 903 | * cdns_uart_release_port - Release UART port |
61ec9016 | 904 | * @port: Handle to the uart port structure |
e555a211 | 905 | * |
d9bb3fb1 SB |
906 | * Release the memory region attached to a cdns_uart port. Called when the |
907 | * driver removes a cdns_uart port via uart_remove_one_port(). | |
489810a1 | 908 | */ |
d9bb3fb1 | 909 | static void cdns_uart_release_port(struct uart_port *port) |
61ec9016 | 910 | { |
d9bb3fb1 | 911 | release_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE); |
61ec9016 JL |
912 | iounmap(port->membase); |
913 | port->membase = NULL; | |
914 | } | |
915 | ||
916 | /** | |
d9bb3fb1 | 917 | * cdns_uart_config_port - Configure UART port |
61ec9016 JL |
918 | * @port: Handle to the uart port structure |
919 | * @flags: If any | |
489810a1 | 920 | */ |
d9bb3fb1 | 921 | static void cdns_uart_config_port(struct uart_port *port, int flags) |
61ec9016 | 922 | { |
d9bb3fb1 | 923 | if (flags & UART_CONFIG_TYPE && cdns_uart_request_port(port) == 0) |
61ec9016 JL |
924 | port->type = PORT_XUARTPS; |
925 | } | |
926 | ||
927 | /** | |
d9bb3fb1 | 928 | * cdns_uart_get_mctrl - Get the modem control state |
61ec9016 JL |
929 | * @port: Handle to the uart port structure |
930 | * | |
489810a1 MS |
931 | * Return: the modem control state |
932 | */ | |
d9bb3fb1 | 933 | static unsigned int cdns_uart_get_mctrl(struct uart_port *port) |
61ec9016 JL |
934 | { |
935 | return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR; | |
936 | } | |
937 | ||
d9bb3fb1 | 938 | static void cdns_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) |
61ec9016 | 939 | { |
19038ad9 LPC |
940 | u32 val; |
941 | ||
a8df6a51 | 942 | val = readl(port->membase + CDNS_UART_MODEMCR); |
19038ad9 LPC |
943 | |
944 | val &= ~(CDNS_UART_MODEMCR_RTS | CDNS_UART_MODEMCR_DTR); | |
945 | ||
946 | if (mctrl & TIOCM_RTS) | |
947 | val |= CDNS_UART_MODEMCR_RTS; | |
948 | if (mctrl & TIOCM_DTR) | |
949 | val |= CDNS_UART_MODEMCR_DTR; | |
950 | ||
a8df6a51 | 951 | writel(val, port->membase + CDNS_UART_MODEMCR); |
61ec9016 JL |
952 | } |
953 | ||
6ee04c6c | 954 | #ifdef CONFIG_CONSOLE_POLL |
d9bb3fb1 | 955 | static int cdns_uart_poll_get_char(struct uart_port *port) |
6ee04c6c | 956 | { |
6ee04c6c | 957 | int c; |
f0f54a80 | 958 | unsigned long flags; |
6ee04c6c | 959 | |
f0f54a80 | 960 | spin_lock_irqsave(&port->lock, flags); |
6ee04c6c VL |
961 | |
962 | /* Check if FIFO is empty */ | |
a8df6a51 | 963 | if (readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_RXEMPTY) |
6ee04c6c VL |
964 | c = NO_POLL_CHAR; |
965 | else /* Read a character */ | |
a8df6a51 | 966 | c = (unsigned char) readl(port->membase + CDNS_UART_FIFO); |
6ee04c6c | 967 | |
f0f54a80 | 968 | spin_unlock_irqrestore(&port->lock, flags); |
6ee04c6c VL |
969 | |
970 | return c; | |
971 | } | |
972 | ||
d9bb3fb1 | 973 | static void cdns_uart_poll_put_char(struct uart_port *port, unsigned char c) |
6ee04c6c | 974 | { |
f0f54a80 | 975 | unsigned long flags; |
6ee04c6c | 976 | |
f0f54a80 | 977 | spin_lock_irqsave(&port->lock, flags); |
6ee04c6c VL |
978 | |
979 | /* Wait until FIFO is empty */ | |
a8df6a51 | 980 | while (!(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXEMPTY)) |
6ee04c6c VL |
981 | cpu_relax(); |
982 | ||
983 | /* Write a character */ | |
a8df6a51 | 984 | writel(c, port->membase + CDNS_UART_FIFO); |
6ee04c6c VL |
985 | |
986 | /* Wait until FIFO is empty */ | |
a8df6a51 | 987 | while (!(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXEMPTY)) |
6ee04c6c VL |
988 | cpu_relax(); |
989 | ||
f0f54a80 | 990 | spin_unlock_irqrestore(&port->lock, flags); |
6ee04c6c VL |
991 | |
992 | return; | |
993 | } | |
994 | #endif | |
995 | ||
d9bb3fb1 SB |
996 | static struct uart_ops cdns_uart_ops = { |
997 | .set_mctrl = cdns_uart_set_mctrl, | |
998 | .get_mctrl = cdns_uart_get_mctrl, | |
d9bb3fb1 SB |
999 | .start_tx = cdns_uart_start_tx, |
1000 | .stop_tx = cdns_uart_stop_tx, | |
1001 | .stop_rx = cdns_uart_stop_rx, | |
1002 | .tx_empty = cdns_uart_tx_empty, | |
1003 | .break_ctl = cdns_uart_break_ctl, | |
1004 | .set_termios = cdns_uart_set_termios, | |
1005 | .startup = cdns_uart_startup, | |
1006 | .shutdown = cdns_uart_shutdown, | |
1007 | .type = cdns_uart_type, | |
1008 | .verify_port = cdns_uart_verify_port, | |
1009 | .request_port = cdns_uart_request_port, | |
1010 | .release_port = cdns_uart_release_port, | |
1011 | .config_port = cdns_uart_config_port, | |
6ee04c6c | 1012 | #ifdef CONFIG_CONSOLE_POLL |
d9bb3fb1 SB |
1013 | .poll_get_char = cdns_uart_poll_get_char, |
1014 | .poll_put_char = cdns_uart_poll_put_char, | |
6ee04c6c | 1015 | #endif |
61ec9016 JL |
1016 | }; |
1017 | ||
6db6df0e | 1018 | static struct uart_port cdns_uart_port[CDNS_UART_NR_PORTS]; |
61ec9016 JL |
1019 | |
1020 | /** | |
d9bb3fb1 | 1021 | * cdns_uart_get_port - Configure the port from platform device resource info |
928e9263 MS |
1022 | * @id: Port id |
1023 | * | |
489810a1 MS |
1024 | * Return: a pointer to a uart_port or NULL for failure |
1025 | */ | |
d9bb3fb1 | 1026 | static struct uart_port *cdns_uart_get_port(int id) |
61ec9016 JL |
1027 | { |
1028 | struct uart_port *port; | |
61ec9016 | 1029 | |
928e9263 | 1030 | /* Try the given port id if failed use default method */ |
d9bb3fb1 | 1031 | if (cdns_uart_port[id].mapbase != 0) { |
928e9263 | 1032 | /* Find the next unused port */ |
d9bb3fb1 SB |
1033 | for (id = 0; id < CDNS_UART_NR_PORTS; id++) |
1034 | if (cdns_uart_port[id].mapbase == 0) | |
928e9263 MS |
1035 | break; |
1036 | } | |
61ec9016 | 1037 | |
d9bb3fb1 | 1038 | if (id >= CDNS_UART_NR_PORTS) |
61ec9016 JL |
1039 | return NULL; |
1040 | ||
d9bb3fb1 | 1041 | port = &cdns_uart_port[id]; |
61ec9016 JL |
1042 | |
1043 | /* At this point, we've got an empty uart_port struct, initialize it */ | |
1044 | spin_lock_init(&port->lock); | |
1045 | port->membase = NULL; | |
61ec9016 JL |
1046 | port->irq = 0; |
1047 | port->type = PORT_UNKNOWN; | |
1048 | port->iotype = UPIO_MEM32; | |
1049 | port->flags = UPF_BOOT_AUTOCONF; | |
d9bb3fb1 SB |
1050 | port->ops = &cdns_uart_ops; |
1051 | port->fifosize = CDNS_UART_FIFO_SIZE; | |
61ec9016 JL |
1052 | port->line = id; |
1053 | port->dev = NULL; | |
1054 | return port; | |
1055 | } | |
1056 | ||
61ec9016 JL |
1057 | #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE |
1058 | /** | |
d9bb3fb1 | 1059 | * cdns_uart_console_wait_tx - Wait for the TX to be full |
61ec9016 | 1060 | * @port: Handle to the uart port structure |
489810a1 | 1061 | */ |
d9bb3fb1 | 1062 | static void cdns_uart_console_wait_tx(struct uart_port *port) |
61ec9016 | 1063 | { |
a8df6a51 | 1064 | while (!(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXEMPTY)) |
61ec9016 JL |
1065 | barrier(); |
1066 | } | |
1067 | ||
1068 | /** | |
d9bb3fb1 | 1069 | * cdns_uart_console_putchar - write the character to the FIFO buffer |
61ec9016 JL |
1070 | * @port: Handle to the uart port structure |
1071 | * @ch: Character to be written | |
489810a1 | 1072 | */ |
d9bb3fb1 | 1073 | static void cdns_uart_console_putchar(struct uart_port *port, int ch) |
61ec9016 | 1074 | { |
d9bb3fb1 | 1075 | cdns_uart_console_wait_tx(port); |
a8df6a51 | 1076 | writel(ch, port->membase + CDNS_UART_FIFO); |
61ec9016 JL |
1077 | } |
1078 | ||
54585ba0 MY |
1079 | static void __init cdns_early_write(struct console *con, const char *s, |
1080 | unsigned n) | |
6fa62fc4 MS |
1081 | { |
1082 | struct earlycon_device *dev = con->data; | |
1083 | ||
1084 | uart_console_write(&dev->port, s, n, cdns_uart_console_putchar); | |
1085 | } | |
1086 | ||
1087 | static int __init cdns_early_console_setup(struct earlycon_device *device, | |
1088 | const char *opt) | |
1089 | { | |
1090 | if (!device->port.membase) | |
1091 | return -ENODEV; | |
1092 | ||
1093 | device->con->write = cdns_early_write; | |
1094 | ||
1095 | return 0; | |
1096 | } | |
1097 | EARLYCON_DECLARE(cdns, cdns_early_console_setup); | |
1098 | ||
61ec9016 | 1099 | /** |
d9bb3fb1 | 1100 | * cdns_uart_console_write - perform write operation |
489810a1 | 1101 | * @co: Console handle |
61ec9016 JL |
1102 | * @s: Pointer to character array |
1103 | * @count: No of characters | |
489810a1 | 1104 | */ |
d9bb3fb1 | 1105 | static void cdns_uart_console_write(struct console *co, const char *s, |
61ec9016 JL |
1106 | unsigned int count) |
1107 | { | |
d9bb3fb1 | 1108 | struct uart_port *port = &cdns_uart_port[co->index]; |
61ec9016 | 1109 | unsigned long flags; |
d3755f5e | 1110 | unsigned int imr, ctrl; |
61ec9016 JL |
1111 | int locked = 1; |
1112 | ||
74ea66d4 SB |
1113 | if (port->sysrq) |
1114 | locked = 0; | |
1115 | else if (oops_in_progress) | |
61ec9016 JL |
1116 | locked = spin_trylock_irqsave(&port->lock, flags); |
1117 | else | |
1118 | spin_lock_irqsave(&port->lock, flags); | |
1119 | ||
1120 | /* save and disable interrupt */ | |
a8df6a51 SB |
1121 | imr = readl(port->membase + CDNS_UART_IMR); |
1122 | writel(imr, port->membase + CDNS_UART_IDR); | |
61ec9016 | 1123 | |
d3755f5e LPC |
1124 | /* |
1125 | * Make sure that the tx part is enabled. Set the TX enable bit and | |
1126 | * clear the TX disable bit to enable the transmitter. | |
1127 | */ | |
a8df6a51 | 1128 | ctrl = readl(port->membase + CDNS_UART_CR); |
e3538c37 SB |
1129 | ctrl &= ~CDNS_UART_CR_TX_DIS; |
1130 | ctrl |= CDNS_UART_CR_TX_EN; | |
a8df6a51 | 1131 | writel(ctrl, port->membase + CDNS_UART_CR); |
d3755f5e | 1132 | |
d9bb3fb1 SB |
1133 | uart_console_write(port, s, count, cdns_uart_console_putchar); |
1134 | cdns_uart_console_wait_tx(port); | |
61ec9016 | 1135 | |
a8df6a51 | 1136 | writel(ctrl, port->membase + CDNS_UART_CR); |
d3755f5e | 1137 | |
b494a5fa | 1138 | /* restore interrupt state */ |
a8df6a51 | 1139 | writel(imr, port->membase + CDNS_UART_IER); |
61ec9016 JL |
1140 | |
1141 | if (locked) | |
1142 | spin_unlock_irqrestore(&port->lock, flags); | |
1143 | } | |
1144 | ||
1145 | /** | |
d9bb3fb1 | 1146 | * cdns_uart_console_setup - Initialize the uart to default config |
61ec9016 JL |
1147 | * @co: Console handle |
1148 | * @options: Initial settings of uart | |
1149 | * | |
e555a211 | 1150 | * Return: 0 on success, negative errno otherwise. |
489810a1 | 1151 | */ |
d9bb3fb1 | 1152 | static int __init cdns_uart_console_setup(struct console *co, char *options) |
61ec9016 | 1153 | { |
d9bb3fb1 | 1154 | struct uart_port *port = &cdns_uart_port[co->index]; |
61ec9016 JL |
1155 | int baud = 9600; |
1156 | int bits = 8; | |
1157 | int parity = 'n'; | |
1158 | int flow = 'n'; | |
1159 | ||
d9bb3fb1 | 1160 | if (co->index < 0 || co->index >= CDNS_UART_NR_PORTS) |
61ec9016 JL |
1161 | return -EINVAL; |
1162 | ||
136debf7 | 1163 | if (!port->membase) { |
f6415491 PC |
1164 | pr_debug("console on " CDNS_UART_TTY_NAME "%i not present\n", |
1165 | co->index); | |
61ec9016 JL |
1166 | return -ENODEV; |
1167 | } | |
1168 | ||
1169 | if (options) | |
1170 | uart_parse_options(options, &baud, &parity, &bits, &flow); | |
1171 | ||
1172 | return uart_set_options(port, co, baud, parity, bits, flow); | |
1173 | } | |
1174 | ||
d9bb3fb1 | 1175 | static struct uart_driver cdns_uart_uart_driver; |
61ec9016 | 1176 | |
d9bb3fb1 SB |
1177 | static struct console cdns_uart_console = { |
1178 | .name = CDNS_UART_TTY_NAME, | |
1179 | .write = cdns_uart_console_write, | |
61ec9016 | 1180 | .device = uart_console_device, |
d9bb3fb1 | 1181 | .setup = cdns_uart_console_setup, |
61ec9016 JL |
1182 | .flags = CON_PRINTBUFFER, |
1183 | .index = -1, /* Specified on the cmdline (e.g. console=ttyPS ) */ | |
d9bb3fb1 | 1184 | .data = &cdns_uart_uart_driver, |
61ec9016 JL |
1185 | }; |
1186 | ||
1187 | /** | |
d9bb3fb1 | 1188 | * cdns_uart_console_init - Initialization call |
61ec9016 | 1189 | * |
e555a211 | 1190 | * Return: 0 on success, negative errno otherwise |
489810a1 | 1191 | */ |
d9bb3fb1 | 1192 | static int __init cdns_uart_console_init(void) |
61ec9016 | 1193 | { |
d9bb3fb1 | 1194 | register_console(&cdns_uart_console); |
61ec9016 JL |
1195 | return 0; |
1196 | } | |
1197 | ||
d9bb3fb1 | 1198 | console_initcall(cdns_uart_console_init); |
61ec9016 JL |
1199 | |
1200 | #endif /* CONFIG_SERIAL_XILINX_PS_UART_CONSOLE */ | |
1201 | ||
d9bb3fb1 | 1202 | static struct uart_driver cdns_uart_uart_driver = { |
e555a211 | 1203 | .owner = THIS_MODULE, |
d9bb3fb1 SB |
1204 | .driver_name = CDNS_UART_NAME, |
1205 | .dev_name = CDNS_UART_TTY_NAME, | |
1206 | .major = CDNS_UART_MAJOR, | |
1207 | .minor = CDNS_UART_MINOR, | |
1208 | .nr = CDNS_UART_NR_PORTS, | |
d3641f64 | 1209 | #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE |
d9bb3fb1 | 1210 | .cons = &cdns_uart_console, |
d3641f64 SB |
1211 | #endif |
1212 | }; | |
1213 | ||
4b47d9aa SB |
1214 | #ifdef CONFIG_PM_SLEEP |
1215 | /** | |
d9bb3fb1 | 1216 | * cdns_uart_suspend - suspend event |
4b47d9aa SB |
1217 | * @device: Pointer to the device structure |
1218 | * | |
489810a1 | 1219 | * Return: 0 |
4b47d9aa | 1220 | */ |
d9bb3fb1 | 1221 | static int cdns_uart_suspend(struct device *device) |
4b47d9aa SB |
1222 | { |
1223 | struct uart_port *port = dev_get_drvdata(device); | |
1224 | struct tty_struct *tty; | |
1225 | struct device *tty_dev; | |
1226 | int may_wake = 0; | |
1227 | ||
1228 | /* Get the tty which could be NULL so don't assume it's valid */ | |
1229 | tty = tty_port_tty_get(&port->state->port); | |
1230 | if (tty) { | |
1231 | tty_dev = tty->dev; | |
1232 | may_wake = device_may_wakeup(tty_dev); | |
1233 | tty_kref_put(tty); | |
1234 | } | |
1235 | ||
1236 | /* | |
1237 | * Call the API provided in serial_core.c file which handles | |
1238 | * the suspend. | |
1239 | */ | |
d9bb3fb1 | 1240 | uart_suspend_port(&cdns_uart_uart_driver, port); |
4b47d9aa | 1241 | if (console_suspend_enabled && !may_wake) { |
d9bb3fb1 | 1242 | struct cdns_uart *cdns_uart = port->private_data; |
4b47d9aa | 1243 | |
d9bb3fb1 SB |
1244 | clk_disable(cdns_uart->uartclk); |
1245 | clk_disable(cdns_uart->pclk); | |
4b47d9aa SB |
1246 | } else { |
1247 | unsigned long flags = 0; | |
1248 | ||
1249 | spin_lock_irqsave(&port->lock, flags); | |
1250 | /* Empty the receive FIFO 1st before making changes */ | |
a8df6a51 | 1251 | while (!(readl(port->membase + CDNS_UART_SR) & |
d9bb3fb1 | 1252 | CDNS_UART_SR_RXEMPTY)) |
a8df6a51 | 1253 | readl(port->membase + CDNS_UART_FIFO); |
4b47d9aa | 1254 | /* set RX trigger level to 1 */ |
a8df6a51 | 1255 | writel(1, port->membase + CDNS_UART_RXWM); |
4b47d9aa | 1256 | /* disable RX timeout interrups */ |
a8df6a51 | 1257 | writel(CDNS_UART_IXR_TOUT, port->membase + CDNS_UART_IDR); |
4b47d9aa SB |
1258 | spin_unlock_irqrestore(&port->lock, flags); |
1259 | } | |
1260 | ||
1261 | return 0; | |
1262 | } | |
1263 | ||
1264 | /** | |
d9bb3fb1 | 1265 | * cdns_uart_resume - Resume after a previous suspend |
4b47d9aa SB |
1266 | * @device: Pointer to the device structure |
1267 | * | |
489810a1 | 1268 | * Return: 0 |
4b47d9aa | 1269 | */ |
d9bb3fb1 | 1270 | static int cdns_uart_resume(struct device *device) |
4b47d9aa SB |
1271 | { |
1272 | struct uart_port *port = dev_get_drvdata(device); | |
1273 | unsigned long flags = 0; | |
1274 | u32 ctrl_reg; | |
1275 | struct tty_struct *tty; | |
1276 | struct device *tty_dev; | |
1277 | int may_wake = 0; | |
1278 | ||
1279 | /* Get the tty which could be NULL so don't assume it's valid */ | |
1280 | tty = tty_port_tty_get(&port->state->port); | |
1281 | if (tty) { | |
1282 | tty_dev = tty->dev; | |
1283 | may_wake = device_may_wakeup(tty_dev); | |
1284 | tty_kref_put(tty); | |
1285 | } | |
1286 | ||
1287 | if (console_suspend_enabled && !may_wake) { | |
d9bb3fb1 | 1288 | struct cdns_uart *cdns_uart = port->private_data; |
4b47d9aa | 1289 | |
d9bb3fb1 SB |
1290 | clk_enable(cdns_uart->pclk); |
1291 | clk_enable(cdns_uart->uartclk); | |
4b47d9aa SB |
1292 | |
1293 | spin_lock_irqsave(&port->lock, flags); | |
1294 | ||
1295 | /* Set TX/RX Reset */ | |
a8df6a51 | 1296 | ctrl_reg = readl(port->membase + CDNS_UART_CR); |
d9bb3fb1 | 1297 | ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST; |
a8df6a51 SB |
1298 | writel(ctrl_reg, port->membase + CDNS_UART_CR); |
1299 | while (readl(port->membase + CDNS_UART_CR) & | |
d9bb3fb1 | 1300 | (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST)) |
4b47d9aa SB |
1301 | cpu_relax(); |
1302 | ||
1303 | /* restore rx timeout value */ | |
a8df6a51 | 1304 | writel(rx_timeout, port->membase + CDNS_UART_RXTOUT); |
4b47d9aa | 1305 | /* Enable Tx/Rx */ |
a8df6a51 | 1306 | ctrl_reg = readl(port->membase + CDNS_UART_CR); |
d9bb3fb1 SB |
1307 | ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS); |
1308 | ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN; | |
a8df6a51 | 1309 | writel(ctrl_reg, port->membase + CDNS_UART_CR); |
4b47d9aa SB |
1310 | |
1311 | spin_unlock_irqrestore(&port->lock, flags); | |
1312 | } else { | |
1313 | spin_lock_irqsave(&port->lock, flags); | |
1314 | /* restore original rx trigger level */ | |
a8df6a51 | 1315 | writel(rx_trigger_level, port->membase + CDNS_UART_RXWM); |
4b47d9aa | 1316 | /* enable RX timeout interrupt */ |
a8df6a51 | 1317 | writel(CDNS_UART_IXR_TOUT, port->membase + CDNS_UART_IER); |
4b47d9aa SB |
1318 | spin_unlock_irqrestore(&port->lock, flags); |
1319 | } | |
1320 | ||
d9bb3fb1 | 1321 | return uart_resume_port(&cdns_uart_uart_driver, port); |
4b47d9aa SB |
1322 | } |
1323 | #endif /* ! CONFIG_PM_SLEEP */ | |
1324 | ||
d9bb3fb1 SB |
1325 | static SIMPLE_DEV_PM_OPS(cdns_uart_dev_pm_ops, cdns_uart_suspend, |
1326 | cdns_uart_resume); | |
4b47d9aa | 1327 | |
61ec9016 | 1328 | /** |
d9bb3fb1 | 1329 | * cdns_uart_probe - Platform driver probe |
61ec9016 JL |
1330 | * @pdev: Pointer to the platform device structure |
1331 | * | |
e555a211 | 1332 | * Return: 0 on success, negative errno otherwise |
489810a1 | 1333 | */ |
d9bb3fb1 | 1334 | static int cdns_uart_probe(struct platform_device *pdev) |
61ec9016 | 1335 | { |
5c90c07b | 1336 | int rc, id, irq; |
61ec9016 | 1337 | struct uart_port *port; |
5c90c07b | 1338 | struct resource *res; |
d9bb3fb1 | 1339 | struct cdns_uart *cdns_uart_data; |
61ec9016 | 1340 | |
d9bb3fb1 | 1341 | cdns_uart_data = devm_kzalloc(&pdev->dev, sizeof(*cdns_uart_data), |
c03cae17 | 1342 | GFP_KERNEL); |
d9bb3fb1 | 1343 | if (!cdns_uart_data) |
30e1e285 SB |
1344 | return -ENOMEM; |
1345 | ||
d9bb3fb1 SB |
1346 | cdns_uart_data->pclk = devm_clk_get(&pdev->dev, "pclk"); |
1347 | if (IS_ERR(cdns_uart_data->pclk)) { | |
1348 | cdns_uart_data->pclk = devm_clk_get(&pdev->dev, "aper_clk"); | |
1349 | if (!IS_ERR(cdns_uart_data->pclk)) | |
1350 | dev_err(&pdev->dev, "clock name 'aper_clk' is deprecated.\n"); | |
1351 | } | |
1352 | if (IS_ERR(cdns_uart_data->pclk)) { | |
1353 | dev_err(&pdev->dev, "pclk clock not found.\n"); | |
1354 | return PTR_ERR(cdns_uart_data->pclk); | |
1355 | } | |
1356 | ||
1357 | cdns_uart_data->uartclk = devm_clk_get(&pdev->dev, "uart_clk"); | |
1358 | if (IS_ERR(cdns_uart_data->uartclk)) { | |
1359 | cdns_uart_data->uartclk = devm_clk_get(&pdev->dev, "ref_clk"); | |
1360 | if (!IS_ERR(cdns_uart_data->uartclk)) | |
1361 | dev_err(&pdev->dev, "clock name 'ref_clk' is deprecated.\n"); | |
30e1e285 | 1362 | } |
d9bb3fb1 SB |
1363 | if (IS_ERR(cdns_uart_data->uartclk)) { |
1364 | dev_err(&pdev->dev, "uart_clk clock not found.\n"); | |
1365 | return PTR_ERR(cdns_uart_data->uartclk); | |
2326669c JC |
1366 | } |
1367 | ||
d9bb3fb1 | 1368 | rc = clk_prepare_enable(cdns_uart_data->pclk); |
30e1e285 | 1369 | if (rc) { |
d9bb3fb1 | 1370 | dev_err(&pdev->dev, "Unable to enable pclk clock.\n"); |
c03cae17 | 1371 | return rc; |
30e1e285 | 1372 | } |
d9bb3fb1 | 1373 | rc = clk_prepare_enable(cdns_uart_data->uartclk); |
2326669c | 1374 | if (rc) { |
30e1e285 | 1375 | dev_err(&pdev->dev, "Unable to enable device clock.\n"); |
d9bb3fb1 | 1376 | goto err_out_clk_dis_pclk; |
61ec9016 JL |
1377 | } |
1378 | ||
1379 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
30e1e285 SB |
1380 | if (!res) { |
1381 | rc = -ENODEV; | |
1382 | goto err_out_clk_disable; | |
1383 | } | |
61ec9016 | 1384 | |
5c90c07b MS |
1385 | irq = platform_get_irq(pdev, 0); |
1386 | if (irq <= 0) { | |
1387 | rc = -ENXIO; | |
30e1e285 SB |
1388 | goto err_out_clk_disable; |
1389 | } | |
61ec9016 | 1390 | |
7ac57347 | 1391 | #ifdef CONFIG_COMMON_CLK |
d9bb3fb1 SB |
1392 | cdns_uart_data->clk_rate_change_nb.notifier_call = |
1393 | cdns_uart_clk_notifier_cb; | |
1394 | if (clk_notifier_register(cdns_uart_data->uartclk, | |
1395 | &cdns_uart_data->clk_rate_change_nb)) | |
c4b0510c | 1396 | dev_warn(&pdev->dev, "Unable to register clock notifier.\n"); |
7ac57347 | 1397 | #endif |
928e9263 MS |
1398 | /* Look for a serialN alias */ |
1399 | id = of_alias_get_id(pdev->dev.of_node, "serial"); | |
1400 | if (id < 0) | |
1401 | id = 0; | |
c4b0510c | 1402 | |
61ec9016 | 1403 | /* Initialize the port structure */ |
d9bb3fb1 | 1404 | port = cdns_uart_get_port(id); |
61ec9016 JL |
1405 | |
1406 | if (!port) { | |
1407 | dev_err(&pdev->dev, "Cannot get uart_port structure\n"); | |
30e1e285 | 1408 | rc = -ENODEV; |
c4b0510c | 1409 | goto err_out_notif_unreg; |
61ec9016 | 1410 | } |
30e1e285 | 1411 | |
354fb1a7 SB |
1412 | /* |
1413 | * Register the port. | |
1414 | * This function also registers this device with the tty layer | |
1415 | * and triggers invocation of the config_port() entry point. | |
1416 | */ | |
1417 | port->mapbase = res->start; | |
1418 | port->irq = irq; | |
1419 | port->dev = &pdev->dev; | |
1420 | port->uartclk = clk_get_rate(cdns_uart_data->uartclk); | |
1421 | port->private_data = cdns_uart_data; | |
1422 | cdns_uart_data->port = port; | |
1423 | platform_set_drvdata(pdev, port); | |
1424 | ||
1425 | rc = uart_add_one_port(&cdns_uart_uart_driver, port); | |
1426 | if (rc) { | |
1427 | dev_err(&pdev->dev, | |
1428 | "uart_add_one_port() failed; err=%i\n", rc); | |
1429 | goto err_out_notif_unreg; | |
1430 | } | |
1431 | ||
1432 | return 0; | |
1433 | ||
c4b0510c | 1434 | err_out_notif_unreg: |
7ac57347 | 1435 | #ifdef CONFIG_COMMON_CLK |
d9bb3fb1 SB |
1436 | clk_notifier_unregister(cdns_uart_data->uartclk, |
1437 | &cdns_uart_data->clk_rate_change_nb); | |
7ac57347 | 1438 | #endif |
30e1e285 | 1439 | err_out_clk_disable: |
d9bb3fb1 SB |
1440 | clk_disable_unprepare(cdns_uart_data->uartclk); |
1441 | err_out_clk_dis_pclk: | |
1442 | clk_disable_unprepare(cdns_uart_data->pclk); | |
30e1e285 SB |
1443 | |
1444 | return rc; | |
61ec9016 JL |
1445 | } |
1446 | ||
1447 | /** | |
d9bb3fb1 | 1448 | * cdns_uart_remove - called when the platform driver is unregistered |
61ec9016 JL |
1449 | * @pdev: Pointer to the platform device structure |
1450 | * | |
e555a211 | 1451 | * Return: 0 on success, negative errno otherwise |
489810a1 | 1452 | */ |
d9bb3fb1 | 1453 | static int cdns_uart_remove(struct platform_device *pdev) |
61ec9016 | 1454 | { |
696faedd | 1455 | struct uart_port *port = platform_get_drvdata(pdev); |
d9bb3fb1 | 1456 | struct cdns_uart *cdns_uart_data = port->private_data; |
2326669c | 1457 | int rc; |
61ec9016 | 1458 | |
d9bb3fb1 | 1459 | /* Remove the cdns_uart port from the serial core */ |
7ac57347 | 1460 | #ifdef CONFIG_COMMON_CLK |
d9bb3fb1 SB |
1461 | clk_notifier_unregister(cdns_uart_data->uartclk, |
1462 | &cdns_uart_data->clk_rate_change_nb); | |
7ac57347 | 1463 | #endif |
d9bb3fb1 | 1464 | rc = uart_remove_one_port(&cdns_uart_uart_driver, port); |
2326669c | 1465 | port->mapbase = 0; |
d9bb3fb1 SB |
1466 | clk_disable_unprepare(cdns_uart_data->uartclk); |
1467 | clk_disable_unprepare(cdns_uart_data->pclk); | |
61ec9016 JL |
1468 | return rc; |
1469 | } | |
1470 | ||
61ec9016 | 1471 | /* Match table for of_platform binding */ |
ed0bb232 | 1472 | static const struct of_device_id cdns_uart_of_match[] = { |
61ec9016 | 1473 | { .compatible = "xlnx,xuartps", }, |
d9bb3fb1 | 1474 | { .compatible = "cdns,uart-r1p8", }, |
61ec9016 JL |
1475 | {} |
1476 | }; | |
d9bb3fb1 | 1477 | MODULE_DEVICE_TABLE(of, cdns_uart_of_match); |
61ec9016 | 1478 | |
d9bb3fb1 SB |
1479 | static struct platform_driver cdns_uart_platform_driver = { |
1480 | .probe = cdns_uart_probe, | |
1481 | .remove = cdns_uart_remove, | |
61ec9016 | 1482 | .driver = { |
d9bb3fb1 SB |
1483 | .name = CDNS_UART_NAME, |
1484 | .of_match_table = cdns_uart_of_match, | |
1485 | .pm = &cdns_uart_dev_pm_ops, | |
61ec9016 JL |
1486 | }, |
1487 | }; | |
1488 | ||
d9bb3fb1 | 1489 | static int __init cdns_uart_init(void) |
61ec9016 JL |
1490 | { |
1491 | int retval = 0; | |
1492 | ||
d9bb3fb1 SB |
1493 | /* Register the cdns_uart driver with the serial core */ |
1494 | retval = uart_register_driver(&cdns_uart_uart_driver); | |
61ec9016 JL |
1495 | if (retval) |
1496 | return retval; | |
1497 | ||
1498 | /* Register the platform driver */ | |
d9bb3fb1 | 1499 | retval = platform_driver_register(&cdns_uart_platform_driver); |
61ec9016 | 1500 | if (retval) |
d9bb3fb1 | 1501 | uart_unregister_driver(&cdns_uart_uart_driver); |
61ec9016 JL |
1502 | |
1503 | return retval; | |
1504 | } | |
1505 | ||
d9bb3fb1 | 1506 | static void __exit cdns_uart_exit(void) |
61ec9016 | 1507 | { |
61ec9016 | 1508 | /* Unregister the platform driver */ |
d9bb3fb1 | 1509 | platform_driver_unregister(&cdns_uart_platform_driver); |
61ec9016 | 1510 | |
d9bb3fb1 SB |
1511 | /* Unregister the cdns_uart driver */ |
1512 | uart_unregister_driver(&cdns_uart_uart_driver); | |
61ec9016 JL |
1513 | } |
1514 | ||
d9bb3fb1 SB |
1515 | module_init(cdns_uart_init); |
1516 | module_exit(cdns_uart_exit); | |
61ec9016 | 1517 | |
d9bb3fb1 | 1518 | MODULE_DESCRIPTION("Driver for Cadence UART"); |
61ec9016 JL |
1519 | MODULE_AUTHOR("Xilinx Inc."); |
1520 | MODULE_LICENSE("GPL"); |