Commit | Line | Data |
---|---|---|
e3b3d0f5 | 1 | // SPDX-License-Identifier: GPL-2.0+ |
61ec9016 | 2 | /* |
d9bb3fb1 | 3 | * Cadence UART driver (found in Xilinx Zynq) |
61ec9016 | 4 | * |
e555a211 | 5 | * 2011 - 2014 (C) Xilinx Inc. |
61ec9016 | 6 | * |
d9bb3fb1 SB |
7 | * This driver has originally been pushed by Xilinx using a Zynq-branding. This |
8 | * still shows in the naming of this file, the kconfig symbols and some symbols | |
9 | * in the code. | |
61ec9016 JL |
10 | */ |
11 | ||
0c0c47bc VL |
12 | #if defined(CONFIG_SERIAL_XILINX_PS_UART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) |
13 | #define SUPPORT_SYSRQ | |
14 | #endif | |
15 | ||
61ec9016 | 16 | #include <linux/platform_device.h> |
ee160a38 | 17 | #include <linux/serial.h> |
0c0c47bc | 18 | #include <linux/console.h> |
61ec9016 | 19 | #include <linux/serial_core.h> |
30e1e285 | 20 | #include <linux/slab.h> |
ee160a38 JS |
21 | #include <linux/tty.h> |
22 | #include <linux/tty_flip.h> | |
2326669c | 23 | #include <linux/clk.h> |
61ec9016 JL |
24 | #include <linux/irq.h> |
25 | #include <linux/io.h> | |
26 | #include <linux/of.h> | |
578b9ce0 | 27 | #include <linux/module.h> |
d62100f1 | 28 | #include <linux/pm_runtime.h> |
61ec9016 | 29 | |
d9bb3fb1 SB |
30 | #define CDNS_UART_TTY_NAME "ttyPS" |
31 | #define CDNS_UART_NAME "xuartps" | |
32 | #define CDNS_UART_MAJOR 0 /* use dynamic node allocation */ | |
33 | #define CDNS_UART_MINOR 0 /* works best with devtmpfs */ | |
34 | #define CDNS_UART_NR_PORTS 2 | |
35 | #define CDNS_UART_FIFO_SIZE 64 /* FIFO size */ | |
9646e4fe | 36 | #define CDNS_UART_REGISTER_SPACE 0x1000 |
61ec9016 | 37 | |
85baf542 S |
38 | /* Rx Trigger level */ |
39 | static int rx_trigger_level = 56; | |
40 | module_param(rx_trigger_level, uint, S_IRUGO); | |
41 | MODULE_PARM_DESC(rx_trigger_level, "Rx trigger level, 1-63 bytes"); | |
42 | ||
43 | /* Rx Timeout */ | |
44 | static int rx_timeout = 10; | |
45 | module_param(rx_timeout, uint, S_IRUGO); | |
46 | MODULE_PARM_DESC(rx_timeout, "Rx timeout, 1-255"); | |
47 | ||
e555a211 | 48 | /* Register offsets for the UART. */ |
a8df6a51 SB |
49 | #define CDNS_UART_CR 0x00 /* Control Register */ |
50 | #define CDNS_UART_MR 0x04 /* Mode Register */ | |
51 | #define CDNS_UART_IER 0x08 /* Interrupt Enable */ | |
52 | #define CDNS_UART_IDR 0x0C /* Interrupt Disable */ | |
53 | #define CDNS_UART_IMR 0x10 /* Interrupt Mask */ | |
54 | #define CDNS_UART_ISR 0x14 /* Interrupt Status */ | |
55 | #define CDNS_UART_BAUDGEN 0x18 /* Baud Rate Generator */ | |
3816b2f8 | 56 | #define CDNS_UART_RXTOUT 0x1C /* RX Timeout */ |
a8df6a51 SB |
57 | #define CDNS_UART_RXWM 0x20 /* RX FIFO Trigger Level */ |
58 | #define CDNS_UART_MODEMCR 0x24 /* Modem Control */ | |
59 | #define CDNS_UART_MODEMSR 0x28 /* Modem Status */ | |
60 | #define CDNS_UART_SR 0x2C /* Channel Status */ | |
61 | #define CDNS_UART_FIFO 0x30 /* FIFO */ | |
62 | #define CDNS_UART_BAUDDIV 0x34 /* Baud Rate Divider */ | |
63 | #define CDNS_UART_FLOWDEL 0x38 /* Flow Delay */ | |
64 | #define CDNS_UART_IRRX_PWIDTH 0x3C /* IR Min Received Pulse Width */ | |
65 | #define CDNS_UART_IRTX_PWIDTH 0x40 /* IR Transmitted pulse Width */ | |
66 | #define CDNS_UART_TXWM 0x44 /* TX FIFO Trigger Level */ | |
3816b2f8 | 67 | #define CDNS_UART_RXBS 0x48 /* RX FIFO byte status register */ |
e555a211 SB |
68 | |
69 | /* Control Register Bit Definitions */ | |
d9bb3fb1 SB |
70 | #define CDNS_UART_CR_STOPBRK 0x00000100 /* Stop TX break */ |
71 | #define CDNS_UART_CR_STARTBRK 0x00000080 /* Set TX break */ | |
72 | #define CDNS_UART_CR_TX_DIS 0x00000020 /* TX disabled. */ | |
73 | #define CDNS_UART_CR_TX_EN 0x00000010 /* TX enabled */ | |
74 | #define CDNS_UART_CR_RX_DIS 0x00000008 /* RX disabled. */ | |
75 | #define CDNS_UART_CR_RX_EN 0x00000004 /* RX enabled */ | |
76 | #define CDNS_UART_CR_TXRST 0x00000002 /* TX logic reset */ | |
77 | #define CDNS_UART_CR_RXRST 0x00000001 /* RX logic reset */ | |
78 | #define CDNS_UART_CR_RST_TO 0x00000040 /* Restart Timeout Counter */ | |
3816b2f8 NM |
79 | #define CDNS_UART_RXBS_PARITY 0x00000001 /* Parity error status */ |
80 | #define CDNS_UART_RXBS_FRAMING 0x00000002 /* Framing error status */ | |
81 | #define CDNS_UART_RXBS_BRK 0x00000004 /* Overrun error status */ | |
61ec9016 | 82 | |
e555a211 SB |
83 | /* |
84 | * Mode Register: | |
61ec9016 JL |
85 | * The mode register (MR) defines the mode of transfer as well as the data |
86 | * format. If this register is modified during transmission or reception, | |
87 | * data validity cannot be guaranteed. | |
61ec9016 | 88 | */ |
d9bb3fb1 SB |
89 | #define CDNS_UART_MR_CLKSEL 0x00000001 /* Pre-scalar selection */ |
90 | #define CDNS_UART_MR_CHMODE_L_LOOP 0x00000200 /* Local loop back mode */ | |
91 | #define CDNS_UART_MR_CHMODE_NORM 0x00000000 /* Normal mode */ | |
5935a2b3 | 92 | #define CDNS_UART_MR_CHMODE_MASK 0x00000300 /* Mask for mode bits */ |
61ec9016 | 93 | |
d9bb3fb1 SB |
94 | #define CDNS_UART_MR_STOPMODE_2_BIT 0x00000080 /* 2 stop bits */ |
95 | #define CDNS_UART_MR_STOPMODE_1_BIT 0x00000000 /* 1 stop bit */ | |
61ec9016 | 96 | |
d9bb3fb1 SB |
97 | #define CDNS_UART_MR_PARITY_NONE 0x00000020 /* No parity mode */ |
98 | #define CDNS_UART_MR_PARITY_MARK 0x00000018 /* Mark parity mode */ | |
99 | #define CDNS_UART_MR_PARITY_SPACE 0x00000010 /* Space parity mode */ | |
100 | #define CDNS_UART_MR_PARITY_ODD 0x00000008 /* Odd parity mode */ | |
101 | #define CDNS_UART_MR_PARITY_EVEN 0x00000000 /* Even parity mode */ | |
61ec9016 | 102 | |
d9bb3fb1 SB |
103 | #define CDNS_UART_MR_CHARLEN_6_BIT 0x00000006 /* 6 bits data */ |
104 | #define CDNS_UART_MR_CHARLEN_7_BIT 0x00000004 /* 7 bits data */ | |
105 | #define CDNS_UART_MR_CHARLEN_8_BIT 0x00000000 /* 8 bits data */ | |
61ec9016 | 106 | |
e555a211 SB |
107 | /* |
108 | * Interrupt Registers: | |
61ec9016 JL |
109 | * Interrupt control logic uses the interrupt enable register (IER) and the |
110 | * interrupt disable register (IDR) to set the value of the bits in the | |
111 | * interrupt mask register (IMR). The IMR determines whether to pass an | |
112 | * interrupt to the interrupt status register (ISR). | |
113 | * Writing a 1 to IER Enables an interrupt, writing a 1 to IDR disables an | |
114 | * interrupt. IMR and ISR are read only, and IER and IDR are write only. | |
115 | * Reading either IER or IDR returns 0x00. | |
61ec9016 JL |
116 | * All four registers have the same bit definitions. |
117 | */ | |
d9bb3fb1 SB |
118 | #define CDNS_UART_IXR_TOUT 0x00000100 /* RX Timeout error interrupt */ |
119 | #define CDNS_UART_IXR_PARITY 0x00000080 /* Parity error interrupt */ | |
120 | #define CDNS_UART_IXR_FRAMING 0x00000040 /* Framing error interrupt */ | |
121 | #define CDNS_UART_IXR_OVERRUN 0x00000020 /* Overrun error interrupt */ | |
122 | #define CDNS_UART_IXR_TXFULL 0x00000010 /* TX FIFO Full interrupt */ | |
123 | #define CDNS_UART_IXR_TXEMPTY 0x00000008 /* TX FIFO empty interrupt */ | |
124 | #define CDNS_UART_ISR_RXEMPTY 0x00000002 /* RX FIFO empty interrupt */ | |
125 | #define CDNS_UART_IXR_RXTRIG 0x00000001 /* RX FIFO trigger interrupt */ | |
126 | #define CDNS_UART_IXR_RXFULL 0x00000004 /* RX FIFO full interrupt. */ | |
127 | #define CDNS_UART_IXR_RXEMPTY 0x00000002 /* RX FIFO empty interrupt. */ | |
128 | #define CDNS_UART_IXR_MASK 0x00001FFF /* Valid bit mask */ | |
61ec9016 | 129 | |
a3081893 AS |
130 | /* |
131 | * Do not enable parity error interrupt for the following | |
132 | * reason: When parity error interrupt is enabled, each Rx | |
133 | * parity error always results in 2 events. The first one | |
134 | * being parity error interrupt and the second one with a | |
135 | * proper Rx interrupt with the incoming data. Disabling | |
136 | * parity error interrupt ensures better handling of parity | |
137 | * error events. With this change, for a parity error case, we | |
138 | * get a Rx interrupt with parity error set in ISR register | |
139 | * and we still handle parity errors in the desired way. | |
140 | */ | |
141 | ||
142 | #define CDNS_UART_RX_IRQS (CDNS_UART_IXR_FRAMING | \ | |
143 | CDNS_UART_IXR_OVERRUN | \ | |
144 | CDNS_UART_IXR_RXTRIG | \ | |
373e882f SB |
145 | CDNS_UART_IXR_TOUT) |
146 | ||
0c0c47bc | 147 | /* Goes in read_status_mask for break detection as the HW doesn't do it*/ |
3816b2f8 | 148 | #define CDNS_UART_IXR_BRK 0x00002000 |
0c0c47bc | 149 | |
3816b2f8 | 150 | #define CDNS_UART_RXBS_SUPPORT BIT(1) |
19038ad9 LPC |
151 | /* |
152 | * Modem Control register: | |
153 | * The read/write Modem Control register controls the interface with the modem | |
154 | * or data set, or a peripheral device emulating a modem. | |
155 | */ | |
156 | #define CDNS_UART_MODEMCR_FCM 0x00000020 /* Automatic flow control mode */ | |
157 | #define CDNS_UART_MODEMCR_RTS 0x00000002 /* Request to send output control */ | |
158 | #define CDNS_UART_MODEMCR_DTR 0x00000001 /* Data Terminal Ready */ | |
159 | ||
e555a211 SB |
160 | /* |
161 | * Channel Status Register: | |
61ec9016 JL |
162 | * The channel status register (CSR) is provided to enable the control logic |
163 | * to monitor the status of bits in the channel interrupt status register, | |
164 | * even if these are masked out by the interrupt mask register. | |
165 | */ | |
d9bb3fb1 SB |
166 | #define CDNS_UART_SR_RXEMPTY 0x00000002 /* RX FIFO empty */ |
167 | #define CDNS_UART_SR_TXEMPTY 0x00000008 /* TX FIFO empty */ | |
168 | #define CDNS_UART_SR_TXFULL 0x00000010 /* TX FIFO full */ | |
169 | #define CDNS_UART_SR_RXTRIG 0x00000001 /* Rx Trigger */ | |
61ec9016 | 170 | |
e6b39bfd | 171 | /* baud dividers min/max values */ |
d9bb3fb1 SB |
172 | #define CDNS_UART_BDIV_MIN 4 |
173 | #define CDNS_UART_BDIV_MAX 255 | |
174 | #define CDNS_UART_CD_MAX 65535 | |
d62100f1 | 175 | #define UART_AUTOSUSPEND_TIMEOUT 3000 |
e6b39bfd | 176 | |
30e1e285 | 177 | /** |
d9bb3fb1 | 178 | * struct cdns_uart - device data |
489810a1 | 179 | * @port: Pointer to the UART port |
d9bb3fb1 SB |
180 | * @uartclk: Reference clock |
181 | * @pclk: APB clock | |
489810a1 MS |
182 | * @baud: Current baud rate |
183 | * @clk_rate_change_nb: Notifier block for clock changes | |
094094a9 | 184 | * @quirks: Flags for RXBS support. |
30e1e285 | 185 | */ |
d9bb3fb1 | 186 | struct cdns_uart { |
c4b0510c | 187 | struct uart_port *port; |
d9bb3fb1 SB |
188 | struct clk *uartclk; |
189 | struct clk *pclk; | |
c4b0510c SB |
190 | unsigned int baud; |
191 | struct notifier_block clk_rate_change_nb; | |
3816b2f8 NM |
192 | u32 quirks; |
193 | }; | |
194 | struct cdns_platform_data { | |
195 | u32 quirks; | |
30e1e285 | 196 | }; |
d9bb3fb1 SB |
197 | #define to_cdns_uart(_nb) container_of(_nb, struct cdns_uart, \ |
198 | clk_rate_change_nb); | |
30e1e285 | 199 | |
c8dbdc84 AS |
200 | /** |
201 | * cdns_uart_handle_rx - Handle the received bytes along with Rx errors. | |
202 | * @dev_id: Id of the UART port | |
203 | * @isrstatus: The interrupt status register value as read | |
204 | * Return: None | |
205 | */ | |
206 | static void cdns_uart_handle_rx(void *dev_id, unsigned int isrstatus) | |
61ec9016 | 207 | { |
c8dbdc84 | 208 | struct uart_port *port = (struct uart_port *)dev_id; |
3816b2f8 | 209 | struct cdns_uart *cdns_uart = port->private_data; |
c8dbdc84 | 210 | unsigned int data; |
3816b2f8 NM |
211 | unsigned int rxbs_status = 0; |
212 | unsigned int status_mask; | |
c8dbdc84 AS |
213 | unsigned int framerrprocessed = 0; |
214 | char status = TTY_NORMAL; | |
215 | bool is_rxbs_support; | |
3816b2f8 NM |
216 | |
217 | is_rxbs_support = cdns_uart->quirks & CDNS_UART_RXBS_SUPPORT; | |
218 | ||
c8dbdc84 AS |
219 | while ((readl(port->membase + CDNS_UART_SR) & |
220 | CDNS_UART_SR_RXEMPTY) != CDNS_UART_SR_RXEMPTY) { | |
3816b2f8 NM |
221 | if (is_rxbs_support) |
222 | rxbs_status = readl(port->membase + CDNS_UART_RXBS); | |
a8df6a51 | 223 | data = readl(port->membase + CDNS_UART_FIFO); |
c8dbdc84 AS |
224 | port->icount.rx++; |
225 | /* | |
226 | * There is no hardware break detection in Zynq, so we interpret | |
227 | * framing error with all-zeros data as a break sequence. | |
228 | * Most of the time, there's another non-zero byte at the | |
229 | * end of the sequence. | |
230 | */ | |
231 | if (!is_rxbs_support && (isrstatus & CDNS_UART_IXR_FRAMING)) { | |
232 | if (!data) { | |
233 | port->read_status_mask |= CDNS_UART_IXR_BRK; | |
234 | framerrprocessed = 1; | |
354fb1a7 | 235 | continue; |
c8dbdc84 | 236 | } |
354fb1a7 | 237 | } |
3816b2f8 NM |
238 | if (is_rxbs_support && (rxbs_status & CDNS_UART_RXBS_BRK)) { |
239 | port->icount.brk++; | |
240 | status = TTY_BREAK; | |
241 | if (uart_handle_break(port)) | |
242 | continue; | |
243 | } | |
0c0c47bc | 244 | |
c8dbdc84 AS |
245 | isrstatus &= port->read_status_mask; |
246 | isrstatus &= ~port->ignore_status_mask; | |
247 | status_mask = port->read_status_mask; | |
248 | status_mask &= ~port->ignore_status_mask; | |
249 | ||
212d249b NM |
250 | if (data && |
251 | (port->read_status_mask & CDNS_UART_IXR_BRK)) { | |
252 | port->read_status_mask &= ~CDNS_UART_IXR_BRK; | |
253 | port->icount.brk++; | |
254 | if (uart_handle_break(port)) | |
c8dbdc84 | 255 | continue; |
212d249b | 256 | } |
61ec9016 | 257 | |
212d249b NM |
258 | if (uart_handle_sysrq_char(port, data)) |
259 | continue; | |
260 | ||
261 | if (is_rxbs_support) { | |
262 | if ((rxbs_status & CDNS_UART_RXBS_PARITY) | |
263 | && (status_mask & CDNS_UART_IXR_PARITY)) { | |
264 | port->icount.parity++; | |
265 | status = TTY_PARITY; | |
266 | } | |
267 | if ((rxbs_status & CDNS_UART_RXBS_FRAMING) | |
268 | && (status_mask & CDNS_UART_IXR_PARITY)) { | |
269 | port->icount.frame++; | |
270 | status = TTY_FRAME; | |
3816b2f8 | 271 | } |
212d249b NM |
272 | } else { |
273 | if (isrstatus & CDNS_UART_IXR_PARITY) { | |
274 | port->icount.parity++; | |
275 | status = TTY_PARITY; | |
3816b2f8 | 276 | } |
212d249b NM |
277 | if ((isrstatus & CDNS_UART_IXR_FRAMING) && |
278 | !framerrprocessed) { | |
279 | port->icount.frame++; | |
280 | status = TTY_FRAME; | |
281 | } | |
282 | } | |
283 | if (isrstatus & CDNS_UART_IXR_OVERRUN) { | |
284 | port->icount.overrun++; | |
285 | tty_insert_flip_char(&port->state->port, 0, | |
286 | TTY_OVERRUN); | |
61ec9016 | 287 | } |
212d249b NM |
288 | tty_insert_flip_char(&port->state->port, data, status); |
289 | isrstatus = 0; | |
61ec9016 | 290 | } |
c8dbdc84 | 291 | spin_unlock(&port->lock); |
354fb1a7 | 292 | tty_flip_buffer_push(&port->state->port); |
c8dbdc84 | 293 | spin_lock(&port->lock); |
5ede4a5c SB |
294 | } |
295 | ||
c8dbdc84 AS |
296 | /** |
297 | * cdns_uart_handle_tx - Handle the bytes to be Txed. | |
298 | * @dev_id: Id of the UART port | |
299 | * Return: None | |
300 | */ | |
301 | static void cdns_uart_handle_tx(void *dev_id) | |
07986580 | 302 | { |
c8dbdc84 | 303 | struct uart_port *port = (struct uart_port *)dev_id; |
07986580 SB |
304 | unsigned int numbytes; |
305 | ||
306 | if (uart_circ_empty(&port->state->xmit)) { | |
307 | writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_IDR); | |
c8dbdc84 AS |
308 | } else { |
309 | numbytes = port->fifosize; | |
310 | while (numbytes && !uart_circ_empty(&port->state->xmit) && | |
311 | !(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXFULL)) { | |
312 | /* | |
313 | * Get the data from the UART circular buffer | |
314 | * and write it to the cdns_uart's TX_FIFO | |
315 | * register. | |
316 | */ | |
317 | writel( | |
318 | port->state->xmit.buf[port->state->xmit. | |
319 | tail], port->membase + CDNS_UART_FIFO); | |
320 | ||
321 | port->icount.tx++; | |
322 | ||
323 | /* | |
324 | * Adjust the tail of the UART buffer and wrap | |
325 | * the buffer if it reaches limit. | |
326 | */ | |
327 | port->state->xmit.tail = | |
328 | (port->state->xmit.tail + 1) & | |
329 | (UART_XMIT_SIZE - 1); | |
330 | ||
331 | numbytes--; | |
332 | } | |
07986580 | 333 | |
c8dbdc84 AS |
334 | if (uart_circ_chars_pending( |
335 | &port->state->xmit) < WAKEUP_CHARS) | |
336 | uart_write_wakeup(port); | |
07986580 | 337 | } |
07986580 SB |
338 | } |
339 | ||
5ede4a5c SB |
340 | /** |
341 | * cdns_uart_isr - Interrupt handler | |
342 | * @irq: Irq number | |
343 | * @dev_id: Id of the port | |
344 | * | |
345 | * Return: IRQHANDLED | |
346 | */ | |
347 | static irqreturn_t cdns_uart_isr(int irq, void *dev_id) | |
348 | { | |
349 | struct uart_port *port = (struct uart_port *)dev_id; | |
07986580 | 350 | unsigned int isrstatus; |
5ede4a5c | 351 | |
c8dbdc84 | 352 | spin_lock(&port->lock); |
5ede4a5c SB |
353 | |
354 | /* Read the interrupt status register to determine which | |
c8dbdc84 | 355 | * interrupt(s) is/are active and clear them. |
5ede4a5c | 356 | */ |
a8df6a51 | 357 | isrstatus = readl(port->membase + CDNS_UART_ISR); |
a8df6a51 | 358 | writel(isrstatus, port->membase + CDNS_UART_ISR); |
61ec9016 | 359 | |
c8dbdc84 AS |
360 | if (isrstatus & CDNS_UART_IXR_TXEMPTY) { |
361 | cdns_uart_handle_tx(dev_id); | |
362 | isrstatus &= ~CDNS_UART_IXR_TXEMPTY; | |
363 | } | |
364 | if (isrstatus & CDNS_UART_IXR_MASK) | |
365 | cdns_uart_handle_rx(dev_id, isrstatus); | |
61ec9016 | 366 | |
c8dbdc84 | 367 | spin_unlock(&port->lock); |
61ec9016 JL |
368 | return IRQ_HANDLED; |
369 | } | |
370 | ||
371 | /** | |
d9bb3fb1 | 372 | * cdns_uart_calc_baud_divs - Calculate baud rate divisors |
e6b39bfd SB |
373 | * @clk: UART module input clock |
374 | * @baud: Desired baud rate | |
375 | * @rbdiv: BDIV value (return value) | |
376 | * @rcd: CD value (return value) | |
377 | * @div8: Value for clk_sel bit in mod (return value) | |
489810a1 | 378 | * Return: baud rate, requested baud when possible, or actual baud when there |
e6b39bfd SB |
379 | * was too much error, zero if no valid divisors are found. |
380 | * | |
381 | * Formula to obtain baud rate is | |
382 | * baud_tx/rx rate = clk/CD * (BDIV + 1) | |
383 | * input_clk = (Uart User Defined Clock or Apb Clock) | |
384 | * depends on UCLKEN in MR Reg | |
385 | * clk = input_clk or input_clk/8; | |
386 | * depends on CLKS in MR reg | |
387 | * CD and BDIV depends on values in | |
388 | * baud rate generate register | |
389 | * baud rate clock divisor register | |
390 | */ | |
d9bb3fb1 SB |
391 | static unsigned int cdns_uart_calc_baud_divs(unsigned int clk, |
392 | unsigned int baud, u32 *rbdiv, u32 *rcd, int *div8) | |
61ec9016 | 393 | { |
e6b39bfd SB |
394 | u32 cd, bdiv; |
395 | unsigned int calc_baud; | |
396 | unsigned int bestbaud = 0; | |
61ec9016 | 397 | unsigned int bauderror; |
e6b39bfd | 398 | unsigned int besterror = ~0; |
61ec9016 | 399 | |
d9bb3fb1 | 400 | if (baud < clk / ((CDNS_UART_BDIV_MAX + 1) * CDNS_UART_CD_MAX)) { |
e6b39bfd SB |
401 | *div8 = 1; |
402 | clk /= 8; | |
403 | } else { | |
404 | *div8 = 0; | |
405 | } | |
61ec9016 | 406 | |
d9bb3fb1 | 407 | for (bdiv = CDNS_UART_BDIV_MIN; bdiv <= CDNS_UART_BDIV_MAX; bdiv++) { |
e6b39bfd | 408 | cd = DIV_ROUND_CLOSEST(clk, baud * (bdiv + 1)); |
d9bb3fb1 | 409 | if (cd < 1 || cd > CDNS_UART_CD_MAX) |
61ec9016 JL |
410 | continue; |
411 | ||
e6b39bfd | 412 | calc_baud = clk / (cd * (bdiv + 1)); |
61ec9016 JL |
413 | |
414 | if (baud > calc_baud) | |
415 | bauderror = baud - calc_baud; | |
416 | else | |
417 | bauderror = calc_baud - baud; | |
418 | ||
e6b39bfd SB |
419 | if (besterror > bauderror) { |
420 | *rbdiv = bdiv; | |
421 | *rcd = cd; | |
422 | bestbaud = calc_baud; | |
423 | besterror = bauderror; | |
61ec9016 JL |
424 | } |
425 | } | |
e6b39bfd SB |
426 | /* use the values when percent error is acceptable */ |
427 | if (((besterror * 100) / baud) < 3) | |
428 | bestbaud = baud; | |
429 | ||
430 | return bestbaud; | |
431 | } | |
61ec9016 | 432 | |
e6b39bfd | 433 | /** |
d9bb3fb1 | 434 | * cdns_uart_set_baud_rate - Calculate and set the baud rate |
e6b39bfd SB |
435 | * @port: Handle to the uart port structure |
436 | * @baud: Baud rate to set | |
489810a1 | 437 | * Return: baud rate, requested baud when possible, or actual baud when there |
e6b39bfd SB |
438 | * was too much error, zero if no valid divisors are found. |
439 | */ | |
d9bb3fb1 | 440 | static unsigned int cdns_uart_set_baud_rate(struct uart_port *port, |
e6b39bfd SB |
441 | unsigned int baud) |
442 | { | |
443 | unsigned int calc_baud; | |
d54b181e | 444 | u32 cd = 0, bdiv = 0; |
e6b39bfd SB |
445 | u32 mreg; |
446 | int div8; | |
d9bb3fb1 | 447 | struct cdns_uart *cdns_uart = port->private_data; |
e6b39bfd | 448 | |
d9bb3fb1 | 449 | calc_baud = cdns_uart_calc_baud_divs(port->uartclk, baud, &bdiv, &cd, |
e6b39bfd SB |
450 | &div8); |
451 | ||
452 | /* Write new divisors to hardware */ | |
a8df6a51 | 453 | mreg = readl(port->membase + CDNS_UART_MR); |
e6b39bfd | 454 | if (div8) |
d9bb3fb1 | 455 | mreg |= CDNS_UART_MR_CLKSEL; |
e6b39bfd | 456 | else |
d9bb3fb1 | 457 | mreg &= ~CDNS_UART_MR_CLKSEL; |
a8df6a51 SB |
458 | writel(mreg, port->membase + CDNS_UART_MR); |
459 | writel(cd, port->membase + CDNS_UART_BAUDGEN); | |
460 | writel(bdiv, port->membase + CDNS_UART_BAUDDIV); | |
d9bb3fb1 | 461 | cdns_uart->baud = baud; |
61ec9016 JL |
462 | |
463 | return calc_baud; | |
464 | } | |
465 | ||
7ac57347 | 466 | #ifdef CONFIG_COMMON_CLK |
c4b0510c | 467 | /** |
d9bb3fb1 | 468 | * cdns_uart_clk_notitifer_cb - Clock notifier callback |
c4b0510c SB |
469 | * @nb: Notifier block |
470 | * @event: Notify event | |
471 | * @data: Notifier data | |
e555a211 | 472 | * Return: NOTIFY_OK or NOTIFY_DONE on success, NOTIFY_BAD on error. |
c4b0510c | 473 | */ |
d9bb3fb1 | 474 | static int cdns_uart_clk_notifier_cb(struct notifier_block *nb, |
c4b0510c SB |
475 | unsigned long event, void *data) |
476 | { | |
477 | u32 ctrl_reg; | |
478 | struct uart_port *port; | |
479 | int locked = 0; | |
480 | struct clk_notifier_data *ndata = data; | |
481 | unsigned long flags = 0; | |
d9bb3fb1 | 482 | struct cdns_uart *cdns_uart = to_cdns_uart(nb); |
c4b0510c | 483 | |
d9bb3fb1 | 484 | port = cdns_uart->port; |
c4b0510c SB |
485 | if (port->suspended) |
486 | return NOTIFY_OK; | |
487 | ||
488 | switch (event) { | |
489 | case PRE_RATE_CHANGE: | |
490 | { | |
e555a211 | 491 | u32 bdiv, cd; |
c4b0510c SB |
492 | int div8; |
493 | ||
494 | /* | |
495 | * Find out if current baud-rate can be achieved with new clock | |
496 | * frequency. | |
497 | */ | |
d9bb3fb1 | 498 | if (!cdns_uart_calc_baud_divs(ndata->new_rate, cdns_uart->baud, |
5ce15d2d SB |
499 | &bdiv, &cd, &div8)) { |
500 | dev_warn(port->dev, "clock rate change rejected\n"); | |
c4b0510c | 501 | return NOTIFY_BAD; |
5ce15d2d | 502 | } |
c4b0510c | 503 | |
d9bb3fb1 | 504 | spin_lock_irqsave(&cdns_uart->port->lock, flags); |
c4b0510c SB |
505 | |
506 | /* Disable the TX and RX to set baud rate */ | |
a8df6a51 | 507 | ctrl_reg = readl(port->membase + CDNS_UART_CR); |
d9bb3fb1 | 508 | ctrl_reg |= CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS; |
a8df6a51 | 509 | writel(ctrl_reg, port->membase + CDNS_UART_CR); |
c4b0510c | 510 | |
d9bb3fb1 | 511 | spin_unlock_irqrestore(&cdns_uart->port->lock, flags); |
c4b0510c SB |
512 | |
513 | return NOTIFY_OK; | |
514 | } | |
515 | case POST_RATE_CHANGE: | |
516 | /* | |
517 | * Set clk dividers to generate correct baud with new clock | |
518 | * frequency. | |
519 | */ | |
520 | ||
d9bb3fb1 | 521 | spin_lock_irqsave(&cdns_uart->port->lock, flags); |
c4b0510c SB |
522 | |
523 | locked = 1; | |
524 | port->uartclk = ndata->new_rate; | |
525 | ||
d9bb3fb1 SB |
526 | cdns_uart->baud = cdns_uart_set_baud_rate(cdns_uart->port, |
527 | cdns_uart->baud); | |
c4b0510c SB |
528 | /* fall through */ |
529 | case ABORT_RATE_CHANGE: | |
530 | if (!locked) | |
d9bb3fb1 | 531 | spin_lock_irqsave(&cdns_uart->port->lock, flags); |
c4b0510c SB |
532 | |
533 | /* Set TX/RX Reset */ | |
a8df6a51 | 534 | ctrl_reg = readl(port->membase + CDNS_UART_CR); |
d9bb3fb1 | 535 | ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST; |
a8df6a51 | 536 | writel(ctrl_reg, port->membase + CDNS_UART_CR); |
c4b0510c | 537 | |
a8df6a51 | 538 | while (readl(port->membase + CDNS_UART_CR) & |
d9bb3fb1 | 539 | (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST)) |
c4b0510c SB |
540 | cpu_relax(); |
541 | ||
542 | /* | |
543 | * Clear the RX disable and TX disable bits and then set the TX | |
544 | * enable bit and RX enable bit to enable the transmitter and | |
545 | * receiver. | |
546 | */ | |
a8df6a51 SB |
547 | writel(rx_timeout, port->membase + CDNS_UART_RXTOUT); |
548 | ctrl_reg = readl(port->membase + CDNS_UART_CR); | |
d9bb3fb1 SB |
549 | ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS); |
550 | ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN; | |
a8df6a51 | 551 | writel(ctrl_reg, port->membase + CDNS_UART_CR); |
c4b0510c | 552 | |
d9bb3fb1 | 553 | spin_unlock_irqrestore(&cdns_uart->port->lock, flags); |
c4b0510c SB |
554 | |
555 | return NOTIFY_OK; | |
556 | default: | |
557 | return NOTIFY_DONE; | |
558 | } | |
559 | } | |
7ac57347 | 560 | #endif |
c4b0510c | 561 | |
61ec9016 | 562 | /** |
d9bb3fb1 | 563 | * cdns_uart_start_tx - Start transmitting bytes |
61ec9016 | 564 | * @port: Handle to the uart port structure |
489810a1 | 565 | */ |
d9bb3fb1 | 566 | static void cdns_uart_start_tx(struct uart_port *port) |
61ec9016 | 567 | { |
07986580 | 568 | unsigned int status; |
61ec9016 | 569 | |
ea8dd8e5 | 570 | if (uart_tx_stopped(port)) |
61ec9016 JL |
571 | return; |
572 | ||
e3538c37 SB |
573 | /* |
574 | * Set the TX enable bit and clear the TX disable bit to enable the | |
61ec9016 JL |
575 | * transmitter. |
576 | */ | |
a8df6a51 | 577 | status = readl(port->membase + CDNS_UART_CR); |
e3538c37 SB |
578 | status &= ~CDNS_UART_CR_TX_DIS; |
579 | status |= CDNS_UART_CR_TX_EN; | |
a8df6a51 | 580 | writel(status, port->membase + CDNS_UART_CR); |
61ec9016 | 581 | |
ea8dd8e5 SB |
582 | if (uart_circ_empty(&port->state->xmit)) |
583 | return; | |
584 | ||
07986580 | 585 | cdns_uart_handle_tx(port); |
61ec9016 | 586 | |
a8df6a51 | 587 | writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_ISR); |
61ec9016 | 588 | /* Enable the TX Empty interrupt */ |
a8df6a51 | 589 | writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_IER); |
61ec9016 JL |
590 | } |
591 | ||
592 | /** | |
d9bb3fb1 | 593 | * cdns_uart_stop_tx - Stop TX |
61ec9016 | 594 | * @port: Handle to the uart port structure |
489810a1 | 595 | */ |
d9bb3fb1 | 596 | static void cdns_uart_stop_tx(struct uart_port *port) |
61ec9016 JL |
597 | { |
598 | unsigned int regval; | |
599 | ||
a8df6a51 | 600 | regval = readl(port->membase + CDNS_UART_CR); |
d9bb3fb1 | 601 | regval |= CDNS_UART_CR_TX_DIS; |
61ec9016 | 602 | /* Disable the transmitter */ |
a8df6a51 | 603 | writel(regval, port->membase + CDNS_UART_CR); |
61ec9016 JL |
604 | } |
605 | ||
606 | /** | |
d9bb3fb1 | 607 | * cdns_uart_stop_rx - Stop RX |
61ec9016 | 608 | * @port: Handle to the uart port structure |
489810a1 | 609 | */ |
d9bb3fb1 | 610 | static void cdns_uart_stop_rx(struct uart_port *port) |
61ec9016 JL |
611 | { |
612 | unsigned int regval; | |
613 | ||
373e882f | 614 | /* Disable RX IRQs */ |
a8df6a51 | 615 | writel(CDNS_UART_RX_IRQS, port->membase + CDNS_UART_IDR); |
373e882f SB |
616 | |
617 | /* Disable the receiver */ | |
a8df6a51 | 618 | regval = readl(port->membase + CDNS_UART_CR); |
d9bb3fb1 | 619 | regval |= CDNS_UART_CR_RX_DIS; |
a8df6a51 | 620 | writel(regval, port->membase + CDNS_UART_CR); |
61ec9016 JL |
621 | } |
622 | ||
623 | /** | |
d9bb3fb1 | 624 | * cdns_uart_tx_empty - Check whether TX is empty |
61ec9016 JL |
625 | * @port: Handle to the uart port structure |
626 | * | |
489810a1 MS |
627 | * Return: TIOCSER_TEMT on success, 0 otherwise |
628 | */ | |
d9bb3fb1 | 629 | static unsigned int cdns_uart_tx_empty(struct uart_port *port) |
61ec9016 JL |
630 | { |
631 | unsigned int status; | |
632 | ||
a8df6a51 | 633 | status = readl(port->membase + CDNS_UART_SR) & |
19f22efd | 634 | CDNS_UART_SR_TXEMPTY; |
61ec9016 JL |
635 | return status ? TIOCSER_TEMT : 0; |
636 | } | |
637 | ||
638 | /** | |
d9bb3fb1 | 639 | * cdns_uart_break_ctl - Based on the input ctl we have to start or stop |
61ec9016 JL |
640 | * transmitting char breaks |
641 | * @port: Handle to the uart port structure | |
642 | * @ctl: Value based on which start or stop decision is taken | |
489810a1 | 643 | */ |
d9bb3fb1 | 644 | static void cdns_uart_break_ctl(struct uart_port *port, int ctl) |
61ec9016 JL |
645 | { |
646 | unsigned int status; | |
647 | unsigned long flags; | |
648 | ||
649 | spin_lock_irqsave(&port->lock, flags); | |
650 | ||
a8df6a51 | 651 | status = readl(port->membase + CDNS_UART_CR); |
61ec9016 JL |
652 | |
653 | if (ctl == -1) | |
19f22efd | 654 | writel(CDNS_UART_CR_STARTBRK | status, |
a8df6a51 | 655 | port->membase + CDNS_UART_CR); |
61ec9016 | 656 | else { |
d9bb3fb1 | 657 | if ((status & CDNS_UART_CR_STOPBRK) == 0) |
19f22efd | 658 | writel(CDNS_UART_CR_STOPBRK | status, |
a8df6a51 | 659 | port->membase + CDNS_UART_CR); |
61ec9016 JL |
660 | } |
661 | spin_unlock_irqrestore(&port->lock, flags); | |
662 | } | |
663 | ||
664 | /** | |
d9bb3fb1 | 665 | * cdns_uart_set_termios - termios operations, handling data length, parity, |
61ec9016 JL |
666 | * stop bits, flow control, baud rate |
667 | * @port: Handle to the uart port structure | |
668 | * @termios: Handle to the input termios structure | |
669 | * @old: Values of the previously saved termios structure | |
489810a1 | 670 | */ |
d9bb3fb1 | 671 | static void cdns_uart_set_termios(struct uart_port *port, |
61ec9016 JL |
672 | struct ktermios *termios, struct ktermios *old) |
673 | { | |
674 | unsigned int cval = 0; | |
e6b39bfd | 675 | unsigned int baud, minbaud, maxbaud; |
61ec9016 JL |
676 | unsigned long flags; |
677 | unsigned int ctrl_reg, mode_reg; | |
678 | ||
679 | spin_lock_irqsave(&port->lock, flags); | |
680 | ||
6ecde472 | 681 | /* Wait for the transmit FIFO to empty before making changes */ |
a8df6a51 | 682 | if (!(readl(port->membase + CDNS_UART_CR) & |
19f22efd | 683 | CDNS_UART_CR_TX_DIS)) { |
a8df6a51 | 684 | while (!(readl(port->membase + CDNS_UART_SR) & |
6ecde472 NR |
685 | CDNS_UART_SR_TXEMPTY)) { |
686 | cpu_relax(); | |
687 | } | |
61ec9016 JL |
688 | } |
689 | ||
690 | /* Disable the TX and RX to set baud rate */ | |
a8df6a51 | 691 | ctrl_reg = readl(port->membase + CDNS_UART_CR); |
d9bb3fb1 | 692 | ctrl_reg |= CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS; |
a8df6a51 | 693 | writel(ctrl_reg, port->membase + CDNS_UART_CR); |
61ec9016 | 694 | |
e6b39bfd SB |
695 | /* |
696 | * Min baud rate = 6bps and Max Baud Rate is 10Mbps for 100Mhz clk | |
697 | * min and max baud should be calculated here based on port->uartclk. | |
698 | * this way we get a valid baud and can safely call set_baud() | |
699 | */ | |
d9bb3fb1 SB |
700 | minbaud = port->uartclk / |
701 | ((CDNS_UART_BDIV_MAX + 1) * CDNS_UART_CD_MAX * 8); | |
702 | maxbaud = port->uartclk / (CDNS_UART_BDIV_MIN + 1); | |
e6b39bfd | 703 | baud = uart_get_baud_rate(port, termios, old, minbaud, maxbaud); |
d9bb3fb1 | 704 | baud = cdns_uart_set_baud_rate(port, baud); |
61ec9016 JL |
705 | if (tty_termios_baud_rate(termios)) |
706 | tty_termios_encode_baud_rate(termios, baud, baud); | |
707 | ||
e555a211 | 708 | /* Update the per-port timeout. */ |
61ec9016 JL |
709 | uart_update_timeout(port, termios->c_cflag, baud); |
710 | ||
711 | /* Set TX/RX Reset */ | |
a8df6a51 | 712 | ctrl_reg = readl(port->membase + CDNS_UART_CR); |
d9bb3fb1 | 713 | ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST; |
a8df6a51 | 714 | writel(ctrl_reg, port->membase + CDNS_UART_CR); |
61ec9016 | 715 | |
27b17ae0 NM |
716 | while (readl(port->membase + CDNS_UART_CR) & |
717 | (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST)) | |
718 | cpu_relax(); | |
719 | ||
e555a211 SB |
720 | /* |
721 | * Clear the RX disable and TX disable bits and then set the TX enable | |
61ec9016 JL |
722 | * bit and RX enable bit to enable the transmitter and receiver. |
723 | */ | |
a8df6a51 | 724 | ctrl_reg = readl(port->membase + CDNS_UART_CR); |
d9bb3fb1 SB |
725 | ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS); |
726 | ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN; | |
a8df6a51 | 727 | writel(ctrl_reg, port->membase + CDNS_UART_CR); |
61ec9016 | 728 | |
a8df6a51 | 729 | writel(rx_timeout, port->membase + CDNS_UART_RXTOUT); |
61ec9016 | 730 | |
d9bb3fb1 SB |
731 | port->read_status_mask = CDNS_UART_IXR_TXEMPTY | CDNS_UART_IXR_RXTRIG | |
732 | CDNS_UART_IXR_OVERRUN | CDNS_UART_IXR_TOUT; | |
61ec9016 JL |
733 | port->ignore_status_mask = 0; |
734 | ||
735 | if (termios->c_iflag & INPCK) | |
d9bb3fb1 SB |
736 | port->read_status_mask |= CDNS_UART_IXR_PARITY | |
737 | CDNS_UART_IXR_FRAMING; | |
61ec9016 JL |
738 | |
739 | if (termios->c_iflag & IGNPAR) | |
d9bb3fb1 SB |
740 | port->ignore_status_mask |= CDNS_UART_IXR_PARITY | |
741 | CDNS_UART_IXR_FRAMING | CDNS_UART_IXR_OVERRUN; | |
61ec9016 JL |
742 | |
743 | /* ignore all characters if CREAD is not set */ | |
744 | if ((termios->c_cflag & CREAD) == 0) | |
d9bb3fb1 SB |
745 | port->ignore_status_mask |= CDNS_UART_IXR_RXTRIG | |
746 | CDNS_UART_IXR_TOUT | CDNS_UART_IXR_PARITY | | |
747 | CDNS_UART_IXR_FRAMING | CDNS_UART_IXR_OVERRUN; | |
61ec9016 | 748 | |
a8df6a51 | 749 | mode_reg = readl(port->membase + CDNS_UART_MR); |
61ec9016 JL |
750 | |
751 | /* Handling Data Size */ | |
752 | switch (termios->c_cflag & CSIZE) { | |
753 | case CS6: | |
d9bb3fb1 | 754 | cval |= CDNS_UART_MR_CHARLEN_6_BIT; |
61ec9016 JL |
755 | break; |
756 | case CS7: | |
d9bb3fb1 | 757 | cval |= CDNS_UART_MR_CHARLEN_7_BIT; |
61ec9016 JL |
758 | break; |
759 | default: | |
760 | case CS8: | |
d9bb3fb1 | 761 | cval |= CDNS_UART_MR_CHARLEN_8_BIT; |
61ec9016 JL |
762 | termios->c_cflag &= ~CSIZE; |
763 | termios->c_cflag |= CS8; | |
764 | break; | |
765 | } | |
766 | ||
767 | /* Handling Parity and Stop Bits length */ | |
768 | if (termios->c_cflag & CSTOPB) | |
d9bb3fb1 | 769 | cval |= CDNS_UART_MR_STOPMODE_2_BIT; /* 2 STOP bits */ |
61ec9016 | 770 | else |
d9bb3fb1 | 771 | cval |= CDNS_UART_MR_STOPMODE_1_BIT; /* 1 STOP bit */ |
61ec9016 JL |
772 | |
773 | if (termios->c_cflag & PARENB) { | |
774 | /* Mark or Space parity */ | |
775 | if (termios->c_cflag & CMSPAR) { | |
776 | if (termios->c_cflag & PARODD) | |
d9bb3fb1 | 777 | cval |= CDNS_UART_MR_PARITY_MARK; |
61ec9016 | 778 | else |
d9bb3fb1 | 779 | cval |= CDNS_UART_MR_PARITY_SPACE; |
e6b39bfd SB |
780 | } else { |
781 | if (termios->c_cflag & PARODD) | |
d9bb3fb1 | 782 | cval |= CDNS_UART_MR_PARITY_ODD; |
61ec9016 | 783 | else |
d9bb3fb1 | 784 | cval |= CDNS_UART_MR_PARITY_EVEN; |
e6b39bfd SB |
785 | } |
786 | } else { | |
d9bb3fb1 | 787 | cval |= CDNS_UART_MR_PARITY_NONE; |
e6b39bfd SB |
788 | } |
789 | cval |= mode_reg & 1; | |
a8df6a51 | 790 | writel(cval, port->membase + CDNS_UART_MR); |
61ec9016 JL |
791 | |
792 | spin_unlock_irqrestore(&port->lock, flags); | |
793 | } | |
794 | ||
795 | /** | |
d9bb3fb1 | 796 | * cdns_uart_startup - Called when an application opens a cdns_uart port |
61ec9016 JL |
797 | * @port: Handle to the uart port structure |
798 | * | |
e555a211 | 799 | * Return: 0 on success, negative errno otherwise |
489810a1 | 800 | */ |
d9bb3fb1 | 801 | static int cdns_uart_startup(struct uart_port *port) |
61ec9016 | 802 | { |
3816b2f8 NM |
803 | struct cdns_uart *cdns_uart = port->private_data; |
804 | bool is_brk_support; | |
55861d11 | 805 | int ret; |
6e14f7c1 | 806 | unsigned long flags; |
55861d11 | 807 | unsigned int status = 0; |
61ec9016 | 808 | |
3816b2f8 NM |
809 | is_brk_support = cdns_uart->quirks & CDNS_UART_RXBS_SUPPORT; |
810 | ||
6e14f7c1 SB |
811 | spin_lock_irqsave(&port->lock, flags); |
812 | ||
61ec9016 | 813 | /* Disable the TX and RX */ |
19f22efd | 814 | writel(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS, |
a8df6a51 | 815 | port->membase + CDNS_UART_CR); |
61ec9016 JL |
816 | |
817 | /* Set the Control Register with TX/RX Enable, TX/RX Reset, | |
818 | * no break chars. | |
819 | */ | |
19f22efd | 820 | writel(CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST, |
a8df6a51 | 821 | port->membase + CDNS_UART_CR); |
61ec9016 | 822 | |
27b17ae0 NM |
823 | while (readl(port->membase + CDNS_UART_CR) & |
824 | (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST)) | |
825 | cpu_relax(); | |
826 | ||
6e14f7c1 SB |
827 | /* |
828 | * Clear the RX disable bit and then set the RX enable bit to enable | |
829 | * the receiver. | |
61ec9016 | 830 | */ |
a8df6a51 | 831 | status = readl(port->membase + CDNS_UART_CR); |
6e14f7c1 SB |
832 | status &= CDNS_UART_CR_RX_DIS; |
833 | status |= CDNS_UART_CR_RX_EN; | |
a8df6a51 | 834 | writel(status, port->membase + CDNS_UART_CR); |
61ec9016 JL |
835 | |
836 | /* Set the Mode Register with normal mode,8 data bits,1 stop bit, | |
837 | * no parity. | |
838 | */ | |
19f22efd | 839 | writel(CDNS_UART_MR_CHMODE_NORM | CDNS_UART_MR_STOPMODE_1_BIT |
d9bb3fb1 | 840 | | CDNS_UART_MR_PARITY_NONE | CDNS_UART_MR_CHARLEN_8_BIT, |
a8df6a51 | 841 | port->membase + CDNS_UART_MR); |
61ec9016 | 842 | |
85baf542 S |
843 | /* |
844 | * Set the RX FIFO Trigger level to use most of the FIFO, but it | |
845 | * can be tuned with a module parameter | |
846 | */ | |
a8df6a51 | 847 | writel(rx_trigger_level, port->membase + CDNS_UART_RXWM); |
61ec9016 | 848 | |
85baf542 S |
849 | /* |
850 | * Receive Timeout register is enabled but it | |
851 | * can be tuned with a module parameter | |
852 | */ | |
a8df6a51 | 853 | writel(rx_timeout, port->membase + CDNS_UART_RXTOUT); |
61ec9016 | 854 | |
855f6fd9 | 855 | /* Clear out any pending interrupts before enabling them */ |
a8df6a51 SB |
856 | writel(readl(port->membase + CDNS_UART_ISR), |
857 | port->membase + CDNS_UART_ISR); | |
61ec9016 | 858 | |
55861d11 SB |
859 | spin_unlock_irqrestore(&port->lock, flags); |
860 | ||
861 | ret = request_irq(port->irq, cdns_uart_isr, 0, CDNS_UART_NAME, port); | |
862 | if (ret) { | |
863 | dev_err(port->dev, "request_irq '%d' failed with %d\n", | |
864 | port->irq, ret); | |
865 | return ret; | |
866 | } | |
867 | ||
61ec9016 | 868 | /* Set the Interrupt Registers with desired interrupts */ |
3816b2f8 NM |
869 | if (is_brk_support) |
870 | writel(CDNS_UART_RX_IRQS | CDNS_UART_IXR_BRK, | |
871 | port->membase + CDNS_UART_IER); | |
872 | else | |
873 | writel(CDNS_UART_RX_IRQS, port->membase + CDNS_UART_IER); | |
61ec9016 | 874 | |
55861d11 | 875 | return 0; |
61ec9016 JL |
876 | } |
877 | ||
878 | /** | |
d9bb3fb1 | 879 | * cdns_uart_shutdown - Called when an application closes a cdns_uart port |
61ec9016 | 880 | * @port: Handle to the uart port structure |
489810a1 | 881 | */ |
d9bb3fb1 | 882 | static void cdns_uart_shutdown(struct uart_port *port) |
61ec9016 JL |
883 | { |
884 | int status; | |
a19eda0f SB |
885 | unsigned long flags; |
886 | ||
887 | spin_lock_irqsave(&port->lock, flags); | |
61ec9016 JL |
888 | |
889 | /* Disable interrupts */ | |
a8df6a51 SB |
890 | status = readl(port->membase + CDNS_UART_IMR); |
891 | writel(status, port->membase + CDNS_UART_IDR); | |
892 | writel(0xffffffff, port->membase + CDNS_UART_ISR); | |
61ec9016 JL |
893 | |
894 | /* Disable the TX and RX */ | |
19f22efd | 895 | writel(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS, |
a8df6a51 | 896 | port->membase + CDNS_UART_CR); |
a19eda0f SB |
897 | |
898 | spin_unlock_irqrestore(&port->lock, flags); | |
899 | ||
61ec9016 JL |
900 | free_irq(port->irq, port); |
901 | } | |
902 | ||
903 | /** | |
d9bb3fb1 | 904 | * cdns_uart_type - Set UART type to cdns_uart port |
61ec9016 JL |
905 | * @port: Handle to the uart port structure |
906 | * | |
489810a1 MS |
907 | * Return: string on success, NULL otherwise |
908 | */ | |
d9bb3fb1 | 909 | static const char *cdns_uart_type(struct uart_port *port) |
61ec9016 | 910 | { |
d9bb3fb1 | 911 | return port->type == PORT_XUARTPS ? CDNS_UART_NAME : NULL; |
61ec9016 JL |
912 | } |
913 | ||
914 | /** | |
d9bb3fb1 | 915 | * cdns_uart_verify_port - Verify the port params |
61ec9016 JL |
916 | * @port: Handle to the uart port structure |
917 | * @ser: Handle to the structure whose members are compared | |
918 | * | |
e555a211 | 919 | * Return: 0 on success, negative errno otherwise. |
489810a1 | 920 | */ |
d9bb3fb1 | 921 | static int cdns_uart_verify_port(struct uart_port *port, |
61ec9016 JL |
922 | struct serial_struct *ser) |
923 | { | |
924 | if (ser->type != PORT_UNKNOWN && ser->type != PORT_XUARTPS) | |
925 | return -EINVAL; | |
926 | if (port->irq != ser->irq) | |
927 | return -EINVAL; | |
928 | if (ser->io_type != UPIO_MEM) | |
929 | return -EINVAL; | |
930 | if (port->iobase != ser->port) | |
931 | return -EINVAL; | |
932 | if (ser->hub6 != 0) | |
933 | return -EINVAL; | |
934 | return 0; | |
935 | } | |
936 | ||
937 | /** | |
d9bb3fb1 SB |
938 | * cdns_uart_request_port - Claim the memory region attached to cdns_uart port, |
939 | * called when the driver adds a cdns_uart port via | |
61ec9016 JL |
940 | * uart_add_one_port() |
941 | * @port: Handle to the uart port structure | |
942 | * | |
e555a211 | 943 | * Return: 0 on success, negative errno otherwise. |
489810a1 | 944 | */ |
d9bb3fb1 | 945 | static int cdns_uart_request_port(struct uart_port *port) |
61ec9016 | 946 | { |
d9bb3fb1 SB |
947 | if (!request_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE, |
948 | CDNS_UART_NAME)) { | |
61ec9016 JL |
949 | return -ENOMEM; |
950 | } | |
951 | ||
d9bb3fb1 | 952 | port->membase = ioremap(port->mapbase, CDNS_UART_REGISTER_SPACE); |
61ec9016 JL |
953 | if (!port->membase) { |
954 | dev_err(port->dev, "Unable to map registers\n"); | |
d9bb3fb1 | 955 | release_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE); |
61ec9016 JL |
956 | return -ENOMEM; |
957 | } | |
958 | return 0; | |
959 | } | |
960 | ||
961 | /** | |
d9bb3fb1 | 962 | * cdns_uart_release_port - Release UART port |
61ec9016 | 963 | * @port: Handle to the uart port structure |
e555a211 | 964 | * |
d9bb3fb1 SB |
965 | * Release the memory region attached to a cdns_uart port. Called when the |
966 | * driver removes a cdns_uart port via uart_remove_one_port(). | |
489810a1 | 967 | */ |
d9bb3fb1 | 968 | static void cdns_uart_release_port(struct uart_port *port) |
61ec9016 | 969 | { |
d9bb3fb1 | 970 | release_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE); |
61ec9016 JL |
971 | iounmap(port->membase); |
972 | port->membase = NULL; | |
973 | } | |
974 | ||
975 | /** | |
d9bb3fb1 | 976 | * cdns_uart_config_port - Configure UART port |
61ec9016 JL |
977 | * @port: Handle to the uart port structure |
978 | * @flags: If any | |
489810a1 | 979 | */ |
d9bb3fb1 | 980 | static void cdns_uart_config_port(struct uart_port *port, int flags) |
61ec9016 | 981 | { |
d9bb3fb1 | 982 | if (flags & UART_CONFIG_TYPE && cdns_uart_request_port(port) == 0) |
61ec9016 JL |
983 | port->type = PORT_XUARTPS; |
984 | } | |
985 | ||
986 | /** | |
d9bb3fb1 | 987 | * cdns_uart_get_mctrl - Get the modem control state |
61ec9016 JL |
988 | * @port: Handle to the uart port structure |
989 | * | |
489810a1 MS |
990 | * Return: the modem control state |
991 | */ | |
d9bb3fb1 | 992 | static unsigned int cdns_uart_get_mctrl(struct uart_port *port) |
61ec9016 JL |
993 | { |
994 | return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR; | |
995 | } | |
996 | ||
d9bb3fb1 | 997 | static void cdns_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) |
61ec9016 | 998 | { |
19038ad9 | 999 | u32 val; |
5935a2b3 | 1000 | u32 mode_reg; |
19038ad9 | 1001 | |
a8df6a51 | 1002 | val = readl(port->membase + CDNS_UART_MODEMCR); |
5935a2b3 | 1003 | mode_reg = readl(port->membase + CDNS_UART_MR); |
19038ad9 LPC |
1004 | |
1005 | val &= ~(CDNS_UART_MODEMCR_RTS | CDNS_UART_MODEMCR_DTR); | |
5935a2b3 | 1006 | mode_reg &= ~CDNS_UART_MR_CHMODE_MASK; |
19038ad9 LPC |
1007 | |
1008 | if (mctrl & TIOCM_RTS) | |
1009 | val |= CDNS_UART_MODEMCR_RTS; | |
1010 | if (mctrl & TIOCM_DTR) | |
1011 | val |= CDNS_UART_MODEMCR_DTR; | |
5935a2b3 YK |
1012 | if (mctrl & TIOCM_LOOP) |
1013 | mode_reg |= CDNS_UART_MR_CHMODE_L_LOOP; | |
1014 | else | |
1015 | mode_reg |= CDNS_UART_MR_CHMODE_NORM; | |
19038ad9 | 1016 | |
a8df6a51 | 1017 | writel(val, port->membase + CDNS_UART_MODEMCR); |
5935a2b3 | 1018 | writel(mode_reg, port->membase + CDNS_UART_MR); |
61ec9016 JL |
1019 | } |
1020 | ||
6ee04c6c | 1021 | #ifdef CONFIG_CONSOLE_POLL |
d9bb3fb1 | 1022 | static int cdns_uart_poll_get_char(struct uart_port *port) |
6ee04c6c | 1023 | { |
6ee04c6c | 1024 | int c; |
f0f54a80 | 1025 | unsigned long flags; |
6ee04c6c | 1026 | |
f0f54a80 | 1027 | spin_lock_irqsave(&port->lock, flags); |
6ee04c6c VL |
1028 | |
1029 | /* Check if FIFO is empty */ | |
a8df6a51 | 1030 | if (readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_RXEMPTY) |
6ee04c6c VL |
1031 | c = NO_POLL_CHAR; |
1032 | else /* Read a character */ | |
a8df6a51 | 1033 | c = (unsigned char) readl(port->membase + CDNS_UART_FIFO); |
6ee04c6c | 1034 | |
f0f54a80 | 1035 | spin_unlock_irqrestore(&port->lock, flags); |
6ee04c6c VL |
1036 | |
1037 | return c; | |
1038 | } | |
1039 | ||
d9bb3fb1 | 1040 | static void cdns_uart_poll_put_char(struct uart_port *port, unsigned char c) |
6ee04c6c | 1041 | { |
f0f54a80 | 1042 | unsigned long flags; |
6ee04c6c | 1043 | |
f0f54a80 | 1044 | spin_lock_irqsave(&port->lock, flags); |
6ee04c6c VL |
1045 | |
1046 | /* Wait until FIFO is empty */ | |
a8df6a51 | 1047 | while (!(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXEMPTY)) |
6ee04c6c VL |
1048 | cpu_relax(); |
1049 | ||
1050 | /* Write a character */ | |
a8df6a51 | 1051 | writel(c, port->membase + CDNS_UART_FIFO); |
6ee04c6c VL |
1052 | |
1053 | /* Wait until FIFO is empty */ | |
a8df6a51 | 1054 | while (!(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXEMPTY)) |
6ee04c6c VL |
1055 | cpu_relax(); |
1056 | ||
f0f54a80 | 1057 | spin_unlock_irqrestore(&port->lock, flags); |
6ee04c6c VL |
1058 | |
1059 | return; | |
1060 | } | |
1061 | #endif | |
1062 | ||
210417ce SD |
1063 | static void cdns_uart_pm(struct uart_port *port, unsigned int state, |
1064 | unsigned int oldstate) | |
1065 | { | |
210417ce SD |
1066 | switch (state) { |
1067 | case UART_PM_STATE_OFF: | |
d62100f1 SD |
1068 | pm_runtime_mark_last_busy(port->dev); |
1069 | pm_runtime_put_autosuspend(port->dev); | |
210417ce SD |
1070 | break; |
1071 | default: | |
d62100f1 | 1072 | pm_runtime_get_sync(port->dev); |
210417ce SD |
1073 | break; |
1074 | } | |
1075 | } | |
1076 | ||
f098a0ae | 1077 | static const struct uart_ops cdns_uart_ops = { |
d9bb3fb1 SB |
1078 | .set_mctrl = cdns_uart_set_mctrl, |
1079 | .get_mctrl = cdns_uart_get_mctrl, | |
d9bb3fb1 SB |
1080 | .start_tx = cdns_uart_start_tx, |
1081 | .stop_tx = cdns_uart_stop_tx, | |
1082 | .stop_rx = cdns_uart_stop_rx, | |
1083 | .tx_empty = cdns_uart_tx_empty, | |
1084 | .break_ctl = cdns_uart_break_ctl, | |
1085 | .set_termios = cdns_uart_set_termios, | |
1086 | .startup = cdns_uart_startup, | |
1087 | .shutdown = cdns_uart_shutdown, | |
210417ce | 1088 | .pm = cdns_uart_pm, |
d9bb3fb1 SB |
1089 | .type = cdns_uart_type, |
1090 | .verify_port = cdns_uart_verify_port, | |
1091 | .request_port = cdns_uart_request_port, | |
1092 | .release_port = cdns_uart_release_port, | |
1093 | .config_port = cdns_uart_config_port, | |
6ee04c6c | 1094 | #ifdef CONFIG_CONSOLE_POLL |
d9bb3fb1 SB |
1095 | .poll_get_char = cdns_uart_poll_get_char, |
1096 | .poll_put_char = cdns_uart_poll_put_char, | |
6ee04c6c | 1097 | #endif |
61ec9016 JL |
1098 | }; |
1099 | ||
6db6df0e | 1100 | static struct uart_port cdns_uart_port[CDNS_UART_NR_PORTS]; |
61ec9016 JL |
1101 | |
1102 | /** | |
d9bb3fb1 | 1103 | * cdns_uart_get_port - Configure the port from platform device resource info |
928e9263 MS |
1104 | * @id: Port id |
1105 | * | |
489810a1 MS |
1106 | * Return: a pointer to a uart_port or NULL for failure |
1107 | */ | |
d9bb3fb1 | 1108 | static struct uart_port *cdns_uart_get_port(int id) |
61ec9016 JL |
1109 | { |
1110 | struct uart_port *port; | |
61ec9016 | 1111 | |
928e9263 | 1112 | /* Try the given port id if failed use default method */ |
e7d75e18 | 1113 | if (id < CDNS_UART_NR_PORTS && cdns_uart_port[id].mapbase != 0) { |
928e9263 | 1114 | /* Find the next unused port */ |
d9bb3fb1 SB |
1115 | for (id = 0; id < CDNS_UART_NR_PORTS; id++) |
1116 | if (cdns_uart_port[id].mapbase == 0) | |
928e9263 MS |
1117 | break; |
1118 | } | |
61ec9016 | 1119 | |
d9bb3fb1 | 1120 | if (id >= CDNS_UART_NR_PORTS) |
61ec9016 JL |
1121 | return NULL; |
1122 | ||
d9bb3fb1 | 1123 | port = &cdns_uart_port[id]; |
61ec9016 JL |
1124 | |
1125 | /* At this point, we've got an empty uart_port struct, initialize it */ | |
1126 | spin_lock_init(&port->lock); | |
1127 | port->membase = NULL; | |
61ec9016 JL |
1128 | port->irq = 0; |
1129 | port->type = PORT_UNKNOWN; | |
1130 | port->iotype = UPIO_MEM32; | |
1131 | port->flags = UPF_BOOT_AUTOCONF; | |
d9bb3fb1 SB |
1132 | port->ops = &cdns_uart_ops; |
1133 | port->fifosize = CDNS_UART_FIFO_SIZE; | |
61ec9016 JL |
1134 | port->line = id; |
1135 | port->dev = NULL; | |
1136 | return port; | |
1137 | } | |
1138 | ||
61ec9016 JL |
1139 | #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE |
1140 | /** | |
d9bb3fb1 | 1141 | * cdns_uart_console_wait_tx - Wait for the TX to be full |
61ec9016 | 1142 | * @port: Handle to the uart port structure |
489810a1 | 1143 | */ |
d9bb3fb1 | 1144 | static void cdns_uart_console_wait_tx(struct uart_port *port) |
61ec9016 | 1145 | { |
a8df6a51 | 1146 | while (!(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXEMPTY)) |
61ec9016 JL |
1147 | barrier(); |
1148 | } | |
1149 | ||
1150 | /** | |
d9bb3fb1 | 1151 | * cdns_uart_console_putchar - write the character to the FIFO buffer |
61ec9016 JL |
1152 | * @port: Handle to the uart port structure |
1153 | * @ch: Character to be written | |
489810a1 | 1154 | */ |
d9bb3fb1 | 1155 | static void cdns_uart_console_putchar(struct uart_port *port, int ch) |
61ec9016 | 1156 | { |
d9bb3fb1 | 1157 | cdns_uart_console_wait_tx(port); |
a8df6a51 | 1158 | writel(ch, port->membase + CDNS_UART_FIFO); |
61ec9016 JL |
1159 | } |
1160 | ||
99d27316 | 1161 | static void cdns_early_write(struct console *con, const char *s, |
54585ba0 | 1162 | unsigned n) |
6fa62fc4 MS |
1163 | { |
1164 | struct earlycon_device *dev = con->data; | |
1165 | ||
1166 | uart_console_write(&dev->port, s, n, cdns_uart_console_putchar); | |
1167 | } | |
1168 | ||
1169 | static int __init cdns_early_console_setup(struct earlycon_device *device, | |
1170 | const char *opt) | |
1171 | { | |
c41251b1 ST |
1172 | struct uart_port *port = &device->port; |
1173 | ||
1174 | if (!port->membase) | |
6fa62fc4 MS |
1175 | return -ENODEV; |
1176 | ||
c41251b1 ST |
1177 | /* initialise control register */ |
1178 | writel(CDNS_UART_CR_TX_EN|CDNS_UART_CR_TXRST|CDNS_UART_CR_RXRST, | |
1179 | port->membase + CDNS_UART_CR); | |
1180 | ||
1181 | /* only set baud if specified on command line - otherwise | |
1182 | * assume it has been initialized by a boot loader. | |
1183 | */ | |
1184 | if (device->baud) { | |
1185 | u32 cd = 0, bdiv = 0; | |
1186 | u32 mr; | |
1187 | int div8; | |
1188 | ||
1189 | cdns_uart_calc_baud_divs(port->uartclk, device->baud, | |
1190 | &bdiv, &cd, &div8); | |
1191 | mr = CDNS_UART_MR_PARITY_NONE; | |
1192 | if (div8) | |
1193 | mr |= CDNS_UART_MR_CLKSEL; | |
1194 | ||
1195 | writel(mr, port->membase + CDNS_UART_MR); | |
1196 | writel(cd, port->membase + CDNS_UART_BAUDGEN); | |
1197 | writel(bdiv, port->membase + CDNS_UART_BAUDDIV); | |
1198 | } | |
1199 | ||
6fa62fc4 MS |
1200 | device->con->write = cdns_early_write; |
1201 | ||
1202 | return 0; | |
1203 | } | |
93d7bbaa MS |
1204 | OF_EARLYCON_DECLARE(cdns, "xlnx,xuartps", cdns_early_console_setup); |
1205 | OF_EARLYCON_DECLARE(cdns, "cdns,uart-r1p8", cdns_early_console_setup); | |
1206 | OF_EARLYCON_DECLARE(cdns, "cdns,uart-r1p12", cdns_early_console_setup); | |
0267a4ff | 1207 | OF_EARLYCON_DECLARE(cdns, "xlnx,zynqmp-uart", cdns_early_console_setup); |
6fa62fc4 | 1208 | |
61ec9016 | 1209 | /** |
d9bb3fb1 | 1210 | * cdns_uart_console_write - perform write operation |
489810a1 | 1211 | * @co: Console handle |
61ec9016 JL |
1212 | * @s: Pointer to character array |
1213 | * @count: No of characters | |
489810a1 | 1214 | */ |
d9bb3fb1 | 1215 | static void cdns_uart_console_write(struct console *co, const char *s, |
61ec9016 JL |
1216 | unsigned int count) |
1217 | { | |
d9bb3fb1 | 1218 | struct uart_port *port = &cdns_uart_port[co->index]; |
61ec9016 | 1219 | unsigned long flags; |
d3755f5e | 1220 | unsigned int imr, ctrl; |
61ec9016 JL |
1221 | int locked = 1; |
1222 | ||
74ea66d4 SB |
1223 | if (port->sysrq) |
1224 | locked = 0; | |
1225 | else if (oops_in_progress) | |
61ec9016 JL |
1226 | locked = spin_trylock_irqsave(&port->lock, flags); |
1227 | else | |
1228 | spin_lock_irqsave(&port->lock, flags); | |
1229 | ||
1230 | /* save and disable interrupt */ | |
a8df6a51 SB |
1231 | imr = readl(port->membase + CDNS_UART_IMR); |
1232 | writel(imr, port->membase + CDNS_UART_IDR); | |
61ec9016 | 1233 | |
d3755f5e LPC |
1234 | /* |
1235 | * Make sure that the tx part is enabled. Set the TX enable bit and | |
1236 | * clear the TX disable bit to enable the transmitter. | |
1237 | */ | |
a8df6a51 | 1238 | ctrl = readl(port->membase + CDNS_UART_CR); |
e3538c37 SB |
1239 | ctrl &= ~CDNS_UART_CR_TX_DIS; |
1240 | ctrl |= CDNS_UART_CR_TX_EN; | |
a8df6a51 | 1241 | writel(ctrl, port->membase + CDNS_UART_CR); |
d3755f5e | 1242 | |
d9bb3fb1 SB |
1243 | uart_console_write(port, s, count, cdns_uart_console_putchar); |
1244 | cdns_uart_console_wait_tx(port); | |
61ec9016 | 1245 | |
a8df6a51 | 1246 | writel(ctrl, port->membase + CDNS_UART_CR); |
d3755f5e | 1247 | |
b494a5fa | 1248 | /* restore interrupt state */ |
a8df6a51 | 1249 | writel(imr, port->membase + CDNS_UART_IER); |
61ec9016 JL |
1250 | |
1251 | if (locked) | |
1252 | spin_unlock_irqrestore(&port->lock, flags); | |
1253 | } | |
1254 | ||
1255 | /** | |
d9bb3fb1 | 1256 | * cdns_uart_console_setup - Initialize the uart to default config |
61ec9016 JL |
1257 | * @co: Console handle |
1258 | * @options: Initial settings of uart | |
1259 | * | |
e555a211 | 1260 | * Return: 0 on success, negative errno otherwise. |
489810a1 | 1261 | */ |
d9bb3fb1 | 1262 | static int __init cdns_uart_console_setup(struct console *co, char *options) |
61ec9016 | 1263 | { |
d9bb3fb1 | 1264 | struct uart_port *port = &cdns_uart_port[co->index]; |
61ec9016 JL |
1265 | int baud = 9600; |
1266 | int bits = 8; | |
1267 | int parity = 'n'; | |
1268 | int flow = 'n'; | |
1269 | ||
d9bb3fb1 | 1270 | if (co->index < 0 || co->index >= CDNS_UART_NR_PORTS) |
61ec9016 JL |
1271 | return -EINVAL; |
1272 | ||
136debf7 | 1273 | if (!port->membase) { |
f6415491 PC |
1274 | pr_debug("console on " CDNS_UART_TTY_NAME "%i not present\n", |
1275 | co->index); | |
61ec9016 JL |
1276 | return -ENODEV; |
1277 | } | |
1278 | ||
1279 | if (options) | |
1280 | uart_parse_options(options, &baud, &parity, &bits, &flow); | |
1281 | ||
1282 | return uart_set_options(port, co, baud, parity, bits, flow); | |
1283 | } | |
1284 | ||
d9bb3fb1 | 1285 | static struct uart_driver cdns_uart_uart_driver; |
61ec9016 | 1286 | |
d9bb3fb1 SB |
1287 | static struct console cdns_uart_console = { |
1288 | .name = CDNS_UART_TTY_NAME, | |
1289 | .write = cdns_uart_console_write, | |
61ec9016 | 1290 | .device = uart_console_device, |
d9bb3fb1 | 1291 | .setup = cdns_uart_console_setup, |
61ec9016 JL |
1292 | .flags = CON_PRINTBUFFER, |
1293 | .index = -1, /* Specified on the cmdline (e.g. console=ttyPS ) */ | |
d9bb3fb1 | 1294 | .data = &cdns_uart_uart_driver, |
61ec9016 JL |
1295 | }; |
1296 | ||
1297 | /** | |
d9bb3fb1 | 1298 | * cdns_uart_console_init - Initialization call |
61ec9016 | 1299 | * |
e555a211 | 1300 | * Return: 0 on success, negative errno otherwise |
489810a1 | 1301 | */ |
d9bb3fb1 | 1302 | static int __init cdns_uart_console_init(void) |
61ec9016 | 1303 | { |
d9bb3fb1 | 1304 | register_console(&cdns_uart_console); |
61ec9016 JL |
1305 | return 0; |
1306 | } | |
1307 | ||
d9bb3fb1 | 1308 | console_initcall(cdns_uart_console_init); |
61ec9016 JL |
1309 | |
1310 | #endif /* CONFIG_SERIAL_XILINX_PS_UART_CONSOLE */ | |
1311 | ||
d9bb3fb1 | 1312 | static struct uart_driver cdns_uart_uart_driver = { |
e555a211 | 1313 | .owner = THIS_MODULE, |
d9bb3fb1 SB |
1314 | .driver_name = CDNS_UART_NAME, |
1315 | .dev_name = CDNS_UART_TTY_NAME, | |
1316 | .major = CDNS_UART_MAJOR, | |
1317 | .minor = CDNS_UART_MINOR, | |
1318 | .nr = CDNS_UART_NR_PORTS, | |
d3641f64 | 1319 | #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE |
d9bb3fb1 | 1320 | .cons = &cdns_uart_console, |
d3641f64 SB |
1321 | #endif |
1322 | }; | |
1323 | ||
4b47d9aa SB |
1324 | #ifdef CONFIG_PM_SLEEP |
1325 | /** | |
d9bb3fb1 | 1326 | * cdns_uart_suspend - suspend event |
4b47d9aa SB |
1327 | * @device: Pointer to the device structure |
1328 | * | |
489810a1 | 1329 | * Return: 0 |
4b47d9aa | 1330 | */ |
d9bb3fb1 | 1331 | static int cdns_uart_suspend(struct device *device) |
4b47d9aa SB |
1332 | { |
1333 | struct uart_port *port = dev_get_drvdata(device); | |
1334 | struct tty_struct *tty; | |
1335 | struct device *tty_dev; | |
1336 | int may_wake = 0; | |
1337 | ||
1338 | /* Get the tty which could be NULL so don't assume it's valid */ | |
1339 | tty = tty_port_tty_get(&port->state->port); | |
1340 | if (tty) { | |
1341 | tty_dev = tty->dev; | |
1342 | may_wake = device_may_wakeup(tty_dev); | |
1343 | tty_kref_put(tty); | |
1344 | } | |
1345 | ||
1346 | /* | |
1347 | * Call the API provided in serial_core.c file which handles | |
1348 | * the suspend. | |
1349 | */ | |
d9bb3fb1 | 1350 | uart_suspend_port(&cdns_uart_uart_driver, port); |
81e33b51 | 1351 | if (!(console_suspend_enabled && !may_wake)) { |
4b47d9aa SB |
1352 | unsigned long flags = 0; |
1353 | ||
1354 | spin_lock_irqsave(&port->lock, flags); | |
1355 | /* Empty the receive FIFO 1st before making changes */ | |
a8df6a51 | 1356 | while (!(readl(port->membase + CDNS_UART_SR) & |
d9bb3fb1 | 1357 | CDNS_UART_SR_RXEMPTY)) |
a8df6a51 | 1358 | readl(port->membase + CDNS_UART_FIFO); |
4b47d9aa | 1359 | /* set RX trigger level to 1 */ |
a8df6a51 | 1360 | writel(1, port->membase + CDNS_UART_RXWM); |
4b47d9aa | 1361 | /* disable RX timeout interrups */ |
a8df6a51 | 1362 | writel(CDNS_UART_IXR_TOUT, port->membase + CDNS_UART_IDR); |
4b47d9aa SB |
1363 | spin_unlock_irqrestore(&port->lock, flags); |
1364 | } | |
1365 | ||
1366 | return 0; | |
1367 | } | |
1368 | ||
1369 | /** | |
d9bb3fb1 | 1370 | * cdns_uart_resume - Resume after a previous suspend |
4b47d9aa SB |
1371 | * @device: Pointer to the device structure |
1372 | * | |
489810a1 | 1373 | * Return: 0 |
4b47d9aa | 1374 | */ |
d9bb3fb1 | 1375 | static int cdns_uart_resume(struct device *device) |
4b47d9aa SB |
1376 | { |
1377 | struct uart_port *port = dev_get_drvdata(device); | |
1378 | unsigned long flags = 0; | |
1379 | u32 ctrl_reg; | |
1380 | struct tty_struct *tty; | |
1381 | struct device *tty_dev; | |
1382 | int may_wake = 0; | |
1383 | ||
1384 | /* Get the tty which could be NULL so don't assume it's valid */ | |
1385 | tty = tty_port_tty_get(&port->state->port); | |
1386 | if (tty) { | |
1387 | tty_dev = tty->dev; | |
1388 | may_wake = device_may_wakeup(tty_dev); | |
1389 | tty_kref_put(tty); | |
1390 | } | |
1391 | ||
1392 | if (console_suspend_enabled && !may_wake) { | |
d9bb3fb1 | 1393 | struct cdns_uart *cdns_uart = port->private_data; |
4b47d9aa | 1394 | |
d9bb3fb1 SB |
1395 | clk_enable(cdns_uart->pclk); |
1396 | clk_enable(cdns_uart->uartclk); | |
4b47d9aa SB |
1397 | |
1398 | spin_lock_irqsave(&port->lock, flags); | |
1399 | ||
1400 | /* Set TX/RX Reset */ | |
a8df6a51 | 1401 | ctrl_reg = readl(port->membase + CDNS_UART_CR); |
d9bb3fb1 | 1402 | ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST; |
a8df6a51 SB |
1403 | writel(ctrl_reg, port->membase + CDNS_UART_CR); |
1404 | while (readl(port->membase + CDNS_UART_CR) & | |
d9bb3fb1 | 1405 | (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST)) |
4b47d9aa SB |
1406 | cpu_relax(); |
1407 | ||
1408 | /* restore rx timeout value */ | |
a8df6a51 | 1409 | writel(rx_timeout, port->membase + CDNS_UART_RXTOUT); |
4b47d9aa | 1410 | /* Enable Tx/Rx */ |
a8df6a51 | 1411 | ctrl_reg = readl(port->membase + CDNS_UART_CR); |
d9bb3fb1 SB |
1412 | ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS); |
1413 | ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN; | |
a8df6a51 | 1414 | writel(ctrl_reg, port->membase + CDNS_UART_CR); |
4b47d9aa | 1415 | |
81e33b51 SD |
1416 | clk_disable(cdns_uart->uartclk); |
1417 | clk_disable(cdns_uart->pclk); | |
4b47d9aa SB |
1418 | spin_unlock_irqrestore(&port->lock, flags); |
1419 | } else { | |
1420 | spin_lock_irqsave(&port->lock, flags); | |
1421 | /* restore original rx trigger level */ | |
a8df6a51 | 1422 | writel(rx_trigger_level, port->membase + CDNS_UART_RXWM); |
4b47d9aa | 1423 | /* enable RX timeout interrupt */ |
a8df6a51 | 1424 | writel(CDNS_UART_IXR_TOUT, port->membase + CDNS_UART_IER); |
4b47d9aa SB |
1425 | spin_unlock_irqrestore(&port->lock, flags); |
1426 | } | |
1427 | ||
d9bb3fb1 | 1428 | return uart_resume_port(&cdns_uart_uart_driver, port); |
4b47d9aa SB |
1429 | } |
1430 | #endif /* ! CONFIG_PM_SLEEP */ | |
d62100f1 SD |
1431 | static int __maybe_unused cdns_runtime_suspend(struct device *dev) |
1432 | { | |
1433 | struct platform_device *pdev = to_platform_device(dev); | |
1434 | struct uart_port *port = platform_get_drvdata(pdev); | |
1435 | struct cdns_uart *cdns_uart = port->private_data; | |
4b47d9aa | 1436 | |
d62100f1 SD |
1437 | clk_disable(cdns_uart->uartclk); |
1438 | clk_disable(cdns_uart->pclk); | |
1439 | return 0; | |
1440 | }; | |
1441 | ||
1442 | static int __maybe_unused cdns_runtime_resume(struct device *dev) | |
1443 | { | |
1444 | struct platform_device *pdev = to_platform_device(dev); | |
1445 | struct uart_port *port = platform_get_drvdata(pdev); | |
1446 | struct cdns_uart *cdns_uart = port->private_data; | |
1447 | ||
1448 | clk_enable(cdns_uart->pclk); | |
1449 | clk_enable(cdns_uart->uartclk); | |
1450 | return 0; | |
1451 | }; | |
1452 | ||
1453 | static const struct dev_pm_ops cdns_uart_dev_pm_ops = { | |
1454 | SET_SYSTEM_SLEEP_PM_OPS(cdns_uart_suspend, cdns_uart_resume) | |
1455 | SET_RUNTIME_PM_OPS(cdns_runtime_suspend, | |
1456 | cdns_runtime_resume, NULL) | |
1457 | }; | |
4b47d9aa | 1458 | |
3816b2f8 NM |
1459 | static const struct cdns_platform_data zynqmp_uart_def = { |
1460 | .quirks = CDNS_UART_RXBS_SUPPORT, }; | |
1461 | ||
1462 | /* Match table for of_platform binding */ | |
1463 | static const struct of_device_id cdns_uart_of_match[] = { | |
1464 | { .compatible = "xlnx,xuartps", }, | |
1465 | { .compatible = "cdns,uart-r1p8", }, | |
1466 | { .compatible = "cdns,uart-r1p12", .data = &zynqmp_uart_def }, | |
0267a4ff | 1467 | { .compatible = "xlnx,zynqmp-uart", .data = &zynqmp_uart_def }, |
3816b2f8 NM |
1468 | {} |
1469 | }; | |
1470 | MODULE_DEVICE_TABLE(of, cdns_uart_of_match); | |
1471 | ||
61ec9016 | 1472 | /** |
d9bb3fb1 | 1473 | * cdns_uart_probe - Platform driver probe |
61ec9016 JL |
1474 | * @pdev: Pointer to the platform device structure |
1475 | * | |
e555a211 | 1476 | * Return: 0 on success, negative errno otherwise |
489810a1 | 1477 | */ |
d9bb3fb1 | 1478 | static int cdns_uart_probe(struct platform_device *pdev) |
61ec9016 | 1479 | { |
5c90c07b | 1480 | int rc, id, irq; |
61ec9016 | 1481 | struct uart_port *port; |
5c90c07b | 1482 | struct resource *res; |
d9bb3fb1 | 1483 | struct cdns_uart *cdns_uart_data; |
3816b2f8 | 1484 | const struct of_device_id *match; |
61ec9016 | 1485 | |
d9bb3fb1 | 1486 | cdns_uart_data = devm_kzalloc(&pdev->dev, sizeof(*cdns_uart_data), |
c03cae17 | 1487 | GFP_KERNEL); |
d9bb3fb1 | 1488 | if (!cdns_uart_data) |
30e1e285 SB |
1489 | return -ENOMEM; |
1490 | ||
3816b2f8 NM |
1491 | match = of_match_node(cdns_uart_of_match, pdev->dev.of_node); |
1492 | if (match && match->data) { | |
1493 | const struct cdns_platform_data *data = match->data; | |
1494 | ||
1495 | cdns_uart_data->quirks = data->quirks; | |
1496 | } | |
1497 | ||
d9bb3fb1 SB |
1498 | cdns_uart_data->pclk = devm_clk_get(&pdev->dev, "pclk"); |
1499 | if (IS_ERR(cdns_uart_data->pclk)) { | |
1500 | cdns_uart_data->pclk = devm_clk_get(&pdev->dev, "aper_clk"); | |
1501 | if (!IS_ERR(cdns_uart_data->pclk)) | |
1502 | dev_err(&pdev->dev, "clock name 'aper_clk' is deprecated.\n"); | |
1503 | } | |
1504 | if (IS_ERR(cdns_uart_data->pclk)) { | |
1505 | dev_err(&pdev->dev, "pclk clock not found.\n"); | |
1506 | return PTR_ERR(cdns_uart_data->pclk); | |
1507 | } | |
1508 | ||
1509 | cdns_uart_data->uartclk = devm_clk_get(&pdev->dev, "uart_clk"); | |
1510 | if (IS_ERR(cdns_uart_data->uartclk)) { | |
1511 | cdns_uart_data->uartclk = devm_clk_get(&pdev->dev, "ref_clk"); | |
1512 | if (!IS_ERR(cdns_uart_data->uartclk)) | |
1513 | dev_err(&pdev->dev, "clock name 'ref_clk' is deprecated.\n"); | |
30e1e285 | 1514 | } |
d9bb3fb1 SB |
1515 | if (IS_ERR(cdns_uart_data->uartclk)) { |
1516 | dev_err(&pdev->dev, "uart_clk clock not found.\n"); | |
1517 | return PTR_ERR(cdns_uart_data->uartclk); | |
2326669c JC |
1518 | } |
1519 | ||
ecfc5771 | 1520 | rc = clk_prepare_enable(cdns_uart_data->pclk); |
30e1e285 | 1521 | if (rc) { |
d9bb3fb1 | 1522 | dev_err(&pdev->dev, "Unable to enable pclk clock.\n"); |
c03cae17 | 1523 | return rc; |
30e1e285 | 1524 | } |
ecfc5771 | 1525 | rc = clk_prepare_enable(cdns_uart_data->uartclk); |
2326669c | 1526 | if (rc) { |
30e1e285 | 1527 | dev_err(&pdev->dev, "Unable to enable device clock.\n"); |
d9bb3fb1 | 1528 | goto err_out_clk_dis_pclk; |
61ec9016 JL |
1529 | } |
1530 | ||
1531 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
30e1e285 SB |
1532 | if (!res) { |
1533 | rc = -ENODEV; | |
1534 | goto err_out_clk_disable; | |
1535 | } | |
61ec9016 | 1536 | |
5c90c07b MS |
1537 | irq = platform_get_irq(pdev, 0); |
1538 | if (irq <= 0) { | |
1539 | rc = -ENXIO; | |
30e1e285 SB |
1540 | goto err_out_clk_disable; |
1541 | } | |
61ec9016 | 1542 | |
7ac57347 | 1543 | #ifdef CONFIG_COMMON_CLK |
d9bb3fb1 SB |
1544 | cdns_uart_data->clk_rate_change_nb.notifier_call = |
1545 | cdns_uart_clk_notifier_cb; | |
1546 | if (clk_notifier_register(cdns_uart_data->uartclk, | |
1547 | &cdns_uart_data->clk_rate_change_nb)) | |
c4b0510c | 1548 | dev_warn(&pdev->dev, "Unable to register clock notifier.\n"); |
7ac57347 | 1549 | #endif |
928e9263 MS |
1550 | /* Look for a serialN alias */ |
1551 | id = of_alias_get_id(pdev->dev.of_node, "serial"); | |
1552 | if (id < 0) | |
1553 | id = 0; | |
c4b0510c | 1554 | |
61ec9016 | 1555 | /* Initialize the port structure */ |
d9bb3fb1 | 1556 | port = cdns_uart_get_port(id); |
61ec9016 JL |
1557 | |
1558 | if (!port) { | |
1559 | dev_err(&pdev->dev, "Cannot get uart_port structure\n"); | |
30e1e285 | 1560 | rc = -ENODEV; |
c4b0510c | 1561 | goto err_out_notif_unreg; |
61ec9016 | 1562 | } |
30e1e285 | 1563 | |
354fb1a7 SB |
1564 | /* |
1565 | * Register the port. | |
1566 | * This function also registers this device with the tty layer | |
1567 | * and triggers invocation of the config_port() entry point. | |
1568 | */ | |
1569 | port->mapbase = res->start; | |
1570 | port->irq = irq; | |
1571 | port->dev = &pdev->dev; | |
1572 | port->uartclk = clk_get_rate(cdns_uart_data->uartclk); | |
1573 | port->private_data = cdns_uart_data; | |
1574 | cdns_uart_data->port = port; | |
1575 | platform_set_drvdata(pdev, port); | |
1576 | ||
d62100f1 SD |
1577 | pm_runtime_use_autosuspend(&pdev->dev); |
1578 | pm_runtime_set_autosuspend_delay(&pdev->dev, UART_AUTOSUSPEND_TIMEOUT); | |
d62100f1 | 1579 | pm_runtime_set_active(&pdev->dev); |
ecfc5771 | 1580 | pm_runtime_enable(&pdev->dev); |
d62100f1 | 1581 | |
354fb1a7 SB |
1582 | rc = uart_add_one_port(&cdns_uart_uart_driver, port); |
1583 | if (rc) { | |
1584 | dev_err(&pdev->dev, | |
1585 | "uart_add_one_port() failed; err=%i\n", rc); | |
d653c43a | 1586 | goto err_out_pm_disable; |
354fb1a7 SB |
1587 | } |
1588 | ||
1589 | return 0; | |
1590 | ||
d653c43a SD |
1591 | err_out_pm_disable: |
1592 | pm_runtime_disable(&pdev->dev); | |
1593 | pm_runtime_set_suspended(&pdev->dev); | |
1594 | pm_runtime_dont_use_autosuspend(&pdev->dev); | |
c4b0510c | 1595 | err_out_notif_unreg: |
7ac57347 | 1596 | #ifdef CONFIG_COMMON_CLK |
d9bb3fb1 SB |
1597 | clk_notifier_unregister(cdns_uart_data->uartclk, |
1598 | &cdns_uart_data->clk_rate_change_nb); | |
7ac57347 | 1599 | #endif |
30e1e285 | 1600 | err_out_clk_disable: |
ecfc5771 | 1601 | clk_disable_unprepare(cdns_uart_data->uartclk); |
d9bb3fb1 | 1602 | err_out_clk_dis_pclk: |
ecfc5771 | 1603 | clk_disable_unprepare(cdns_uart_data->pclk); |
30e1e285 SB |
1604 | |
1605 | return rc; | |
61ec9016 JL |
1606 | } |
1607 | ||
1608 | /** | |
d9bb3fb1 | 1609 | * cdns_uart_remove - called when the platform driver is unregistered |
61ec9016 JL |
1610 | * @pdev: Pointer to the platform device structure |
1611 | * | |
e555a211 | 1612 | * Return: 0 on success, negative errno otherwise |
489810a1 | 1613 | */ |
d9bb3fb1 | 1614 | static int cdns_uart_remove(struct platform_device *pdev) |
61ec9016 | 1615 | { |
696faedd | 1616 | struct uart_port *port = platform_get_drvdata(pdev); |
d9bb3fb1 | 1617 | struct cdns_uart *cdns_uart_data = port->private_data; |
2326669c | 1618 | int rc; |
61ec9016 | 1619 | |
d9bb3fb1 | 1620 | /* Remove the cdns_uart port from the serial core */ |
7ac57347 | 1621 | #ifdef CONFIG_COMMON_CLK |
d9bb3fb1 SB |
1622 | clk_notifier_unregister(cdns_uart_data->uartclk, |
1623 | &cdns_uart_data->clk_rate_change_nb); | |
7ac57347 | 1624 | #endif |
d9bb3fb1 | 1625 | rc = uart_remove_one_port(&cdns_uart_uart_driver, port); |
2326669c | 1626 | port->mapbase = 0; |
ecfc5771 SD |
1627 | clk_disable_unprepare(cdns_uart_data->uartclk); |
1628 | clk_disable_unprepare(cdns_uart_data->pclk); | |
d62100f1 SD |
1629 | pm_runtime_disable(&pdev->dev); |
1630 | pm_runtime_set_suspended(&pdev->dev); | |
1631 | pm_runtime_dont_use_autosuspend(&pdev->dev); | |
61ec9016 JL |
1632 | return rc; |
1633 | } | |
1634 | ||
d9bb3fb1 SB |
1635 | static struct platform_driver cdns_uart_platform_driver = { |
1636 | .probe = cdns_uart_probe, | |
1637 | .remove = cdns_uart_remove, | |
61ec9016 | 1638 | .driver = { |
d9bb3fb1 SB |
1639 | .name = CDNS_UART_NAME, |
1640 | .of_match_table = cdns_uart_of_match, | |
1641 | .pm = &cdns_uart_dev_pm_ops, | |
61ec9016 JL |
1642 | }, |
1643 | }; | |
1644 | ||
d9bb3fb1 | 1645 | static int __init cdns_uart_init(void) |
61ec9016 JL |
1646 | { |
1647 | int retval = 0; | |
1648 | ||
d9bb3fb1 SB |
1649 | /* Register the cdns_uart driver with the serial core */ |
1650 | retval = uart_register_driver(&cdns_uart_uart_driver); | |
61ec9016 JL |
1651 | if (retval) |
1652 | return retval; | |
1653 | ||
1654 | /* Register the platform driver */ | |
d9bb3fb1 | 1655 | retval = platform_driver_register(&cdns_uart_platform_driver); |
61ec9016 | 1656 | if (retval) |
d9bb3fb1 | 1657 | uart_unregister_driver(&cdns_uart_uart_driver); |
61ec9016 JL |
1658 | |
1659 | return retval; | |
1660 | } | |
1661 | ||
d9bb3fb1 | 1662 | static void __exit cdns_uart_exit(void) |
61ec9016 | 1663 | { |
61ec9016 | 1664 | /* Unregister the platform driver */ |
d9bb3fb1 | 1665 | platform_driver_unregister(&cdns_uart_platform_driver); |
61ec9016 | 1666 | |
d9bb3fb1 SB |
1667 | /* Unregister the cdns_uart driver */ |
1668 | uart_unregister_driver(&cdns_uart_uart_driver); | |
61ec9016 JL |
1669 | } |
1670 | ||
1d67243a | 1671 | arch_initcall(cdns_uart_init); |
d9bb3fb1 | 1672 | module_exit(cdns_uart_exit); |
61ec9016 | 1673 | |
d9bb3fb1 | 1674 | MODULE_DESCRIPTION("Driver for Cadence UART"); |
61ec9016 JL |
1675 | MODULE_AUTHOR("Xilinx Inc."); |
1676 | MODULE_LICENSE("GPL"); |