Commit | Line | Data |
---|---|---|
61ec9016 | 1 | /* |
d9bb3fb1 | 2 | * Cadence UART driver (found in Xilinx Zynq) |
61ec9016 | 3 | * |
e555a211 | 4 | * 2011 - 2014 (C) Xilinx Inc. |
61ec9016 JL |
5 | * |
6 | * This program is free software; you can redistribute it | |
7 | * and/or modify it under the terms of the GNU General Public | |
8 | * License as published by the Free Software Foundation; | |
9 | * either version 2 of the License, or (at your option) any | |
10 | * later version. | |
d9bb3fb1 SB |
11 | * |
12 | * This driver has originally been pushed by Xilinx using a Zynq-branding. This | |
13 | * still shows in the naming of this file, the kconfig symbols and some symbols | |
14 | * in the code. | |
61ec9016 JL |
15 | */ |
16 | ||
0c0c47bc VL |
17 | #if defined(CONFIG_SERIAL_XILINX_PS_UART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) |
18 | #define SUPPORT_SYSRQ | |
19 | #endif | |
20 | ||
61ec9016 | 21 | #include <linux/platform_device.h> |
ee160a38 | 22 | #include <linux/serial.h> |
0c0c47bc | 23 | #include <linux/console.h> |
61ec9016 | 24 | #include <linux/serial_core.h> |
30e1e285 | 25 | #include <linux/slab.h> |
ee160a38 JS |
26 | #include <linux/tty.h> |
27 | #include <linux/tty_flip.h> | |
2326669c | 28 | #include <linux/clk.h> |
61ec9016 JL |
29 | #include <linux/irq.h> |
30 | #include <linux/io.h> | |
31 | #include <linux/of.h> | |
578b9ce0 | 32 | #include <linux/module.h> |
d62100f1 | 33 | #include <linux/pm_runtime.h> |
61ec9016 | 34 | |
d9bb3fb1 SB |
35 | #define CDNS_UART_TTY_NAME "ttyPS" |
36 | #define CDNS_UART_NAME "xuartps" | |
37 | #define CDNS_UART_MAJOR 0 /* use dynamic node allocation */ | |
38 | #define CDNS_UART_MINOR 0 /* works best with devtmpfs */ | |
39 | #define CDNS_UART_NR_PORTS 2 | |
40 | #define CDNS_UART_FIFO_SIZE 64 /* FIFO size */ | |
9646e4fe | 41 | #define CDNS_UART_REGISTER_SPACE 0x1000 |
61ec9016 | 42 | |
85baf542 S |
43 | /* Rx Trigger level */ |
44 | static int rx_trigger_level = 56; | |
45 | module_param(rx_trigger_level, uint, S_IRUGO); | |
46 | MODULE_PARM_DESC(rx_trigger_level, "Rx trigger level, 1-63 bytes"); | |
47 | ||
48 | /* Rx Timeout */ | |
49 | static int rx_timeout = 10; | |
50 | module_param(rx_timeout, uint, S_IRUGO); | |
51 | MODULE_PARM_DESC(rx_timeout, "Rx timeout, 1-255"); | |
52 | ||
e555a211 | 53 | /* Register offsets for the UART. */ |
a8df6a51 SB |
54 | #define CDNS_UART_CR 0x00 /* Control Register */ |
55 | #define CDNS_UART_MR 0x04 /* Mode Register */ | |
56 | #define CDNS_UART_IER 0x08 /* Interrupt Enable */ | |
57 | #define CDNS_UART_IDR 0x0C /* Interrupt Disable */ | |
58 | #define CDNS_UART_IMR 0x10 /* Interrupt Mask */ | |
59 | #define CDNS_UART_ISR 0x14 /* Interrupt Status */ | |
60 | #define CDNS_UART_BAUDGEN 0x18 /* Baud Rate Generator */ | |
3816b2f8 | 61 | #define CDNS_UART_RXTOUT 0x1C /* RX Timeout */ |
a8df6a51 SB |
62 | #define CDNS_UART_RXWM 0x20 /* RX FIFO Trigger Level */ |
63 | #define CDNS_UART_MODEMCR 0x24 /* Modem Control */ | |
64 | #define CDNS_UART_MODEMSR 0x28 /* Modem Status */ | |
65 | #define CDNS_UART_SR 0x2C /* Channel Status */ | |
66 | #define CDNS_UART_FIFO 0x30 /* FIFO */ | |
67 | #define CDNS_UART_BAUDDIV 0x34 /* Baud Rate Divider */ | |
68 | #define CDNS_UART_FLOWDEL 0x38 /* Flow Delay */ | |
69 | #define CDNS_UART_IRRX_PWIDTH 0x3C /* IR Min Received Pulse Width */ | |
70 | #define CDNS_UART_IRTX_PWIDTH 0x40 /* IR Transmitted pulse Width */ | |
71 | #define CDNS_UART_TXWM 0x44 /* TX FIFO Trigger Level */ | |
3816b2f8 | 72 | #define CDNS_UART_RXBS 0x48 /* RX FIFO byte status register */ |
e555a211 SB |
73 | |
74 | /* Control Register Bit Definitions */ | |
d9bb3fb1 SB |
75 | #define CDNS_UART_CR_STOPBRK 0x00000100 /* Stop TX break */ |
76 | #define CDNS_UART_CR_STARTBRK 0x00000080 /* Set TX break */ | |
77 | #define CDNS_UART_CR_TX_DIS 0x00000020 /* TX disabled. */ | |
78 | #define CDNS_UART_CR_TX_EN 0x00000010 /* TX enabled */ | |
79 | #define CDNS_UART_CR_RX_DIS 0x00000008 /* RX disabled. */ | |
80 | #define CDNS_UART_CR_RX_EN 0x00000004 /* RX enabled */ | |
81 | #define CDNS_UART_CR_TXRST 0x00000002 /* TX logic reset */ | |
82 | #define CDNS_UART_CR_RXRST 0x00000001 /* RX logic reset */ | |
83 | #define CDNS_UART_CR_RST_TO 0x00000040 /* Restart Timeout Counter */ | |
3816b2f8 NM |
84 | #define CDNS_UART_RXBS_PARITY 0x00000001 /* Parity error status */ |
85 | #define CDNS_UART_RXBS_FRAMING 0x00000002 /* Framing error status */ | |
86 | #define CDNS_UART_RXBS_BRK 0x00000004 /* Overrun error status */ | |
61ec9016 | 87 | |
e555a211 SB |
88 | /* |
89 | * Mode Register: | |
61ec9016 JL |
90 | * The mode register (MR) defines the mode of transfer as well as the data |
91 | * format. If this register is modified during transmission or reception, | |
92 | * data validity cannot be guaranteed. | |
61ec9016 | 93 | */ |
d9bb3fb1 SB |
94 | #define CDNS_UART_MR_CLKSEL 0x00000001 /* Pre-scalar selection */ |
95 | #define CDNS_UART_MR_CHMODE_L_LOOP 0x00000200 /* Local loop back mode */ | |
96 | #define CDNS_UART_MR_CHMODE_NORM 0x00000000 /* Normal mode */ | |
5935a2b3 | 97 | #define CDNS_UART_MR_CHMODE_MASK 0x00000300 /* Mask for mode bits */ |
61ec9016 | 98 | |
d9bb3fb1 SB |
99 | #define CDNS_UART_MR_STOPMODE_2_BIT 0x00000080 /* 2 stop bits */ |
100 | #define CDNS_UART_MR_STOPMODE_1_BIT 0x00000000 /* 1 stop bit */ | |
61ec9016 | 101 | |
d9bb3fb1 SB |
102 | #define CDNS_UART_MR_PARITY_NONE 0x00000020 /* No parity mode */ |
103 | #define CDNS_UART_MR_PARITY_MARK 0x00000018 /* Mark parity mode */ | |
104 | #define CDNS_UART_MR_PARITY_SPACE 0x00000010 /* Space parity mode */ | |
105 | #define CDNS_UART_MR_PARITY_ODD 0x00000008 /* Odd parity mode */ | |
106 | #define CDNS_UART_MR_PARITY_EVEN 0x00000000 /* Even parity mode */ | |
61ec9016 | 107 | |
d9bb3fb1 SB |
108 | #define CDNS_UART_MR_CHARLEN_6_BIT 0x00000006 /* 6 bits data */ |
109 | #define CDNS_UART_MR_CHARLEN_7_BIT 0x00000004 /* 7 bits data */ | |
110 | #define CDNS_UART_MR_CHARLEN_8_BIT 0x00000000 /* 8 bits data */ | |
61ec9016 | 111 | |
e555a211 SB |
112 | /* |
113 | * Interrupt Registers: | |
61ec9016 JL |
114 | * Interrupt control logic uses the interrupt enable register (IER) and the |
115 | * interrupt disable register (IDR) to set the value of the bits in the | |
116 | * interrupt mask register (IMR). The IMR determines whether to pass an | |
117 | * interrupt to the interrupt status register (ISR). | |
118 | * Writing a 1 to IER Enables an interrupt, writing a 1 to IDR disables an | |
119 | * interrupt. IMR and ISR are read only, and IER and IDR are write only. | |
120 | * Reading either IER or IDR returns 0x00. | |
61ec9016 JL |
121 | * All four registers have the same bit definitions. |
122 | */ | |
d9bb3fb1 SB |
123 | #define CDNS_UART_IXR_TOUT 0x00000100 /* RX Timeout error interrupt */ |
124 | #define CDNS_UART_IXR_PARITY 0x00000080 /* Parity error interrupt */ | |
125 | #define CDNS_UART_IXR_FRAMING 0x00000040 /* Framing error interrupt */ | |
126 | #define CDNS_UART_IXR_OVERRUN 0x00000020 /* Overrun error interrupt */ | |
127 | #define CDNS_UART_IXR_TXFULL 0x00000010 /* TX FIFO Full interrupt */ | |
128 | #define CDNS_UART_IXR_TXEMPTY 0x00000008 /* TX FIFO empty interrupt */ | |
129 | #define CDNS_UART_ISR_RXEMPTY 0x00000002 /* RX FIFO empty interrupt */ | |
130 | #define CDNS_UART_IXR_RXTRIG 0x00000001 /* RX FIFO trigger interrupt */ | |
131 | #define CDNS_UART_IXR_RXFULL 0x00000004 /* RX FIFO full interrupt. */ | |
132 | #define CDNS_UART_IXR_RXEMPTY 0x00000002 /* RX FIFO empty interrupt. */ | |
133 | #define CDNS_UART_IXR_MASK 0x00001FFF /* Valid bit mask */ | |
61ec9016 | 134 | |
a3081893 AS |
135 | /* |
136 | * Do not enable parity error interrupt for the following | |
137 | * reason: When parity error interrupt is enabled, each Rx | |
138 | * parity error always results in 2 events. The first one | |
139 | * being parity error interrupt and the second one with a | |
140 | * proper Rx interrupt with the incoming data. Disabling | |
141 | * parity error interrupt ensures better handling of parity | |
142 | * error events. With this change, for a parity error case, we | |
143 | * get a Rx interrupt with parity error set in ISR register | |
144 | * and we still handle parity errors in the desired way. | |
145 | */ | |
146 | ||
147 | #define CDNS_UART_RX_IRQS (CDNS_UART_IXR_FRAMING | \ | |
148 | CDNS_UART_IXR_OVERRUN | \ | |
149 | CDNS_UART_IXR_RXTRIG | \ | |
373e882f SB |
150 | CDNS_UART_IXR_TOUT) |
151 | ||
0c0c47bc | 152 | /* Goes in read_status_mask for break detection as the HW doesn't do it*/ |
3816b2f8 | 153 | #define CDNS_UART_IXR_BRK 0x00002000 |
0c0c47bc | 154 | |
3816b2f8 | 155 | #define CDNS_UART_RXBS_SUPPORT BIT(1) |
19038ad9 LPC |
156 | /* |
157 | * Modem Control register: | |
158 | * The read/write Modem Control register controls the interface with the modem | |
159 | * or data set, or a peripheral device emulating a modem. | |
160 | */ | |
161 | #define CDNS_UART_MODEMCR_FCM 0x00000020 /* Automatic flow control mode */ | |
162 | #define CDNS_UART_MODEMCR_RTS 0x00000002 /* Request to send output control */ | |
163 | #define CDNS_UART_MODEMCR_DTR 0x00000001 /* Data Terminal Ready */ | |
164 | ||
e555a211 SB |
165 | /* |
166 | * Channel Status Register: | |
61ec9016 JL |
167 | * The channel status register (CSR) is provided to enable the control logic |
168 | * to monitor the status of bits in the channel interrupt status register, | |
169 | * even if these are masked out by the interrupt mask register. | |
170 | */ | |
d9bb3fb1 SB |
171 | #define CDNS_UART_SR_RXEMPTY 0x00000002 /* RX FIFO empty */ |
172 | #define CDNS_UART_SR_TXEMPTY 0x00000008 /* TX FIFO empty */ | |
173 | #define CDNS_UART_SR_TXFULL 0x00000010 /* TX FIFO full */ | |
174 | #define CDNS_UART_SR_RXTRIG 0x00000001 /* Rx Trigger */ | |
61ec9016 | 175 | |
e6b39bfd | 176 | /* baud dividers min/max values */ |
d9bb3fb1 SB |
177 | #define CDNS_UART_BDIV_MIN 4 |
178 | #define CDNS_UART_BDIV_MAX 255 | |
179 | #define CDNS_UART_CD_MAX 65535 | |
d62100f1 | 180 | #define UART_AUTOSUSPEND_TIMEOUT 3000 |
e6b39bfd | 181 | |
30e1e285 | 182 | /** |
d9bb3fb1 | 183 | * struct cdns_uart - device data |
489810a1 | 184 | * @port: Pointer to the UART port |
d9bb3fb1 SB |
185 | * @uartclk: Reference clock |
186 | * @pclk: APB clock | |
489810a1 MS |
187 | * @baud: Current baud rate |
188 | * @clk_rate_change_nb: Notifier block for clock changes | |
30e1e285 | 189 | */ |
d9bb3fb1 | 190 | struct cdns_uart { |
c4b0510c | 191 | struct uart_port *port; |
d9bb3fb1 SB |
192 | struct clk *uartclk; |
193 | struct clk *pclk; | |
c4b0510c SB |
194 | unsigned int baud; |
195 | struct notifier_block clk_rate_change_nb; | |
3816b2f8 NM |
196 | u32 quirks; |
197 | }; | |
198 | struct cdns_platform_data { | |
199 | u32 quirks; | |
30e1e285 | 200 | }; |
d9bb3fb1 SB |
201 | #define to_cdns_uart(_nb) container_of(_nb, struct cdns_uart, \ |
202 | clk_rate_change_nb); | |
30e1e285 | 203 | |
c8dbdc84 AS |
204 | /** |
205 | * cdns_uart_handle_rx - Handle the received bytes along with Rx errors. | |
206 | * @dev_id: Id of the UART port | |
207 | * @isrstatus: The interrupt status register value as read | |
208 | * Return: None | |
209 | */ | |
210 | static void cdns_uart_handle_rx(void *dev_id, unsigned int isrstatus) | |
61ec9016 | 211 | { |
c8dbdc84 | 212 | struct uart_port *port = (struct uart_port *)dev_id; |
3816b2f8 | 213 | struct cdns_uart *cdns_uart = port->private_data; |
c8dbdc84 | 214 | unsigned int data; |
3816b2f8 NM |
215 | unsigned int rxbs_status = 0; |
216 | unsigned int status_mask; | |
c8dbdc84 AS |
217 | unsigned int framerrprocessed = 0; |
218 | char status = TTY_NORMAL; | |
219 | bool is_rxbs_support; | |
3816b2f8 NM |
220 | |
221 | is_rxbs_support = cdns_uart->quirks & CDNS_UART_RXBS_SUPPORT; | |
222 | ||
c8dbdc84 AS |
223 | while ((readl(port->membase + CDNS_UART_SR) & |
224 | CDNS_UART_SR_RXEMPTY) != CDNS_UART_SR_RXEMPTY) { | |
3816b2f8 NM |
225 | if (is_rxbs_support) |
226 | rxbs_status = readl(port->membase + CDNS_UART_RXBS); | |
a8df6a51 | 227 | data = readl(port->membase + CDNS_UART_FIFO); |
c8dbdc84 AS |
228 | port->icount.rx++; |
229 | /* | |
230 | * There is no hardware break detection in Zynq, so we interpret | |
231 | * framing error with all-zeros data as a break sequence. | |
232 | * Most of the time, there's another non-zero byte at the | |
233 | * end of the sequence. | |
234 | */ | |
235 | if (!is_rxbs_support && (isrstatus & CDNS_UART_IXR_FRAMING)) { | |
236 | if (!data) { | |
237 | port->read_status_mask |= CDNS_UART_IXR_BRK; | |
238 | framerrprocessed = 1; | |
354fb1a7 | 239 | continue; |
c8dbdc84 | 240 | } |
354fb1a7 | 241 | } |
3816b2f8 NM |
242 | if (is_rxbs_support && (rxbs_status & CDNS_UART_RXBS_BRK)) { |
243 | port->icount.brk++; | |
244 | status = TTY_BREAK; | |
245 | if (uart_handle_break(port)) | |
246 | continue; | |
247 | } | |
0c0c47bc | 248 | |
c8dbdc84 AS |
249 | isrstatus &= port->read_status_mask; |
250 | isrstatus &= ~port->ignore_status_mask; | |
251 | status_mask = port->read_status_mask; | |
252 | status_mask &= ~port->ignore_status_mask; | |
253 | ||
212d249b NM |
254 | if (data && |
255 | (port->read_status_mask & CDNS_UART_IXR_BRK)) { | |
256 | port->read_status_mask &= ~CDNS_UART_IXR_BRK; | |
257 | port->icount.brk++; | |
258 | if (uart_handle_break(port)) | |
c8dbdc84 | 259 | continue; |
212d249b | 260 | } |
61ec9016 | 261 | |
212d249b NM |
262 | if (uart_handle_sysrq_char(port, data)) |
263 | continue; | |
264 | ||
265 | if (is_rxbs_support) { | |
266 | if ((rxbs_status & CDNS_UART_RXBS_PARITY) | |
267 | && (status_mask & CDNS_UART_IXR_PARITY)) { | |
268 | port->icount.parity++; | |
269 | status = TTY_PARITY; | |
270 | } | |
271 | if ((rxbs_status & CDNS_UART_RXBS_FRAMING) | |
272 | && (status_mask & CDNS_UART_IXR_PARITY)) { | |
273 | port->icount.frame++; | |
274 | status = TTY_FRAME; | |
3816b2f8 | 275 | } |
212d249b NM |
276 | } else { |
277 | if (isrstatus & CDNS_UART_IXR_PARITY) { | |
278 | port->icount.parity++; | |
279 | status = TTY_PARITY; | |
3816b2f8 | 280 | } |
212d249b NM |
281 | if ((isrstatus & CDNS_UART_IXR_FRAMING) && |
282 | !framerrprocessed) { | |
283 | port->icount.frame++; | |
284 | status = TTY_FRAME; | |
285 | } | |
286 | } | |
287 | if (isrstatus & CDNS_UART_IXR_OVERRUN) { | |
288 | port->icount.overrun++; | |
289 | tty_insert_flip_char(&port->state->port, 0, | |
290 | TTY_OVERRUN); | |
61ec9016 | 291 | } |
212d249b NM |
292 | tty_insert_flip_char(&port->state->port, data, status); |
293 | isrstatus = 0; | |
61ec9016 | 294 | } |
c8dbdc84 | 295 | spin_unlock(&port->lock); |
354fb1a7 | 296 | tty_flip_buffer_push(&port->state->port); |
c8dbdc84 | 297 | spin_lock(&port->lock); |
5ede4a5c SB |
298 | } |
299 | ||
c8dbdc84 AS |
300 | /** |
301 | * cdns_uart_handle_tx - Handle the bytes to be Txed. | |
302 | * @dev_id: Id of the UART port | |
303 | * Return: None | |
304 | */ | |
305 | static void cdns_uart_handle_tx(void *dev_id) | |
07986580 | 306 | { |
c8dbdc84 | 307 | struct uart_port *port = (struct uart_port *)dev_id; |
07986580 SB |
308 | unsigned int numbytes; |
309 | ||
310 | if (uart_circ_empty(&port->state->xmit)) { | |
311 | writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_IDR); | |
c8dbdc84 AS |
312 | } else { |
313 | numbytes = port->fifosize; | |
314 | while (numbytes && !uart_circ_empty(&port->state->xmit) && | |
315 | !(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXFULL)) { | |
316 | /* | |
317 | * Get the data from the UART circular buffer | |
318 | * and write it to the cdns_uart's TX_FIFO | |
319 | * register. | |
320 | */ | |
321 | writel( | |
322 | port->state->xmit.buf[port->state->xmit. | |
323 | tail], port->membase + CDNS_UART_FIFO); | |
324 | ||
325 | port->icount.tx++; | |
326 | ||
327 | /* | |
328 | * Adjust the tail of the UART buffer and wrap | |
329 | * the buffer if it reaches limit. | |
330 | */ | |
331 | port->state->xmit.tail = | |
332 | (port->state->xmit.tail + 1) & | |
333 | (UART_XMIT_SIZE - 1); | |
334 | ||
335 | numbytes--; | |
336 | } | |
07986580 | 337 | |
c8dbdc84 AS |
338 | if (uart_circ_chars_pending( |
339 | &port->state->xmit) < WAKEUP_CHARS) | |
340 | uart_write_wakeup(port); | |
07986580 | 341 | } |
07986580 SB |
342 | } |
343 | ||
5ede4a5c SB |
344 | /** |
345 | * cdns_uart_isr - Interrupt handler | |
346 | * @irq: Irq number | |
347 | * @dev_id: Id of the port | |
348 | * | |
349 | * Return: IRQHANDLED | |
350 | */ | |
351 | static irqreturn_t cdns_uart_isr(int irq, void *dev_id) | |
352 | { | |
353 | struct uart_port *port = (struct uart_port *)dev_id; | |
07986580 | 354 | unsigned int isrstatus; |
5ede4a5c | 355 | |
c8dbdc84 | 356 | spin_lock(&port->lock); |
5ede4a5c SB |
357 | |
358 | /* Read the interrupt status register to determine which | |
c8dbdc84 | 359 | * interrupt(s) is/are active and clear them. |
5ede4a5c | 360 | */ |
a8df6a51 | 361 | isrstatus = readl(port->membase + CDNS_UART_ISR); |
a8df6a51 | 362 | writel(isrstatus, port->membase + CDNS_UART_ISR); |
61ec9016 | 363 | |
c8dbdc84 AS |
364 | if (isrstatus & CDNS_UART_IXR_TXEMPTY) { |
365 | cdns_uart_handle_tx(dev_id); | |
366 | isrstatus &= ~CDNS_UART_IXR_TXEMPTY; | |
367 | } | |
368 | if (isrstatus & CDNS_UART_IXR_MASK) | |
369 | cdns_uart_handle_rx(dev_id, isrstatus); | |
61ec9016 | 370 | |
c8dbdc84 | 371 | spin_unlock(&port->lock); |
61ec9016 JL |
372 | return IRQ_HANDLED; |
373 | } | |
374 | ||
375 | /** | |
d9bb3fb1 | 376 | * cdns_uart_calc_baud_divs - Calculate baud rate divisors |
e6b39bfd SB |
377 | * @clk: UART module input clock |
378 | * @baud: Desired baud rate | |
379 | * @rbdiv: BDIV value (return value) | |
380 | * @rcd: CD value (return value) | |
381 | * @div8: Value for clk_sel bit in mod (return value) | |
489810a1 | 382 | * Return: baud rate, requested baud when possible, or actual baud when there |
e6b39bfd SB |
383 | * was too much error, zero if no valid divisors are found. |
384 | * | |
385 | * Formula to obtain baud rate is | |
386 | * baud_tx/rx rate = clk/CD * (BDIV + 1) | |
387 | * input_clk = (Uart User Defined Clock or Apb Clock) | |
388 | * depends on UCLKEN in MR Reg | |
389 | * clk = input_clk or input_clk/8; | |
390 | * depends on CLKS in MR reg | |
391 | * CD and BDIV depends on values in | |
392 | * baud rate generate register | |
393 | * baud rate clock divisor register | |
394 | */ | |
d9bb3fb1 SB |
395 | static unsigned int cdns_uart_calc_baud_divs(unsigned int clk, |
396 | unsigned int baud, u32 *rbdiv, u32 *rcd, int *div8) | |
61ec9016 | 397 | { |
e6b39bfd SB |
398 | u32 cd, bdiv; |
399 | unsigned int calc_baud; | |
400 | unsigned int bestbaud = 0; | |
61ec9016 | 401 | unsigned int bauderror; |
e6b39bfd | 402 | unsigned int besterror = ~0; |
61ec9016 | 403 | |
d9bb3fb1 | 404 | if (baud < clk / ((CDNS_UART_BDIV_MAX + 1) * CDNS_UART_CD_MAX)) { |
e6b39bfd SB |
405 | *div8 = 1; |
406 | clk /= 8; | |
407 | } else { | |
408 | *div8 = 0; | |
409 | } | |
61ec9016 | 410 | |
d9bb3fb1 | 411 | for (bdiv = CDNS_UART_BDIV_MIN; bdiv <= CDNS_UART_BDIV_MAX; bdiv++) { |
e6b39bfd | 412 | cd = DIV_ROUND_CLOSEST(clk, baud * (bdiv + 1)); |
d9bb3fb1 | 413 | if (cd < 1 || cd > CDNS_UART_CD_MAX) |
61ec9016 JL |
414 | continue; |
415 | ||
e6b39bfd | 416 | calc_baud = clk / (cd * (bdiv + 1)); |
61ec9016 JL |
417 | |
418 | if (baud > calc_baud) | |
419 | bauderror = baud - calc_baud; | |
420 | else | |
421 | bauderror = calc_baud - baud; | |
422 | ||
e6b39bfd SB |
423 | if (besterror > bauderror) { |
424 | *rbdiv = bdiv; | |
425 | *rcd = cd; | |
426 | bestbaud = calc_baud; | |
427 | besterror = bauderror; | |
61ec9016 JL |
428 | } |
429 | } | |
e6b39bfd SB |
430 | /* use the values when percent error is acceptable */ |
431 | if (((besterror * 100) / baud) < 3) | |
432 | bestbaud = baud; | |
433 | ||
434 | return bestbaud; | |
435 | } | |
61ec9016 | 436 | |
e6b39bfd | 437 | /** |
d9bb3fb1 | 438 | * cdns_uart_set_baud_rate - Calculate and set the baud rate |
e6b39bfd SB |
439 | * @port: Handle to the uart port structure |
440 | * @baud: Baud rate to set | |
489810a1 | 441 | * Return: baud rate, requested baud when possible, or actual baud when there |
e6b39bfd SB |
442 | * was too much error, zero if no valid divisors are found. |
443 | */ | |
d9bb3fb1 | 444 | static unsigned int cdns_uart_set_baud_rate(struct uart_port *port, |
e6b39bfd SB |
445 | unsigned int baud) |
446 | { | |
447 | unsigned int calc_baud; | |
d54b181e | 448 | u32 cd = 0, bdiv = 0; |
e6b39bfd SB |
449 | u32 mreg; |
450 | int div8; | |
d9bb3fb1 | 451 | struct cdns_uart *cdns_uart = port->private_data; |
e6b39bfd | 452 | |
d9bb3fb1 | 453 | calc_baud = cdns_uart_calc_baud_divs(port->uartclk, baud, &bdiv, &cd, |
e6b39bfd SB |
454 | &div8); |
455 | ||
456 | /* Write new divisors to hardware */ | |
a8df6a51 | 457 | mreg = readl(port->membase + CDNS_UART_MR); |
e6b39bfd | 458 | if (div8) |
d9bb3fb1 | 459 | mreg |= CDNS_UART_MR_CLKSEL; |
e6b39bfd | 460 | else |
d9bb3fb1 | 461 | mreg &= ~CDNS_UART_MR_CLKSEL; |
a8df6a51 SB |
462 | writel(mreg, port->membase + CDNS_UART_MR); |
463 | writel(cd, port->membase + CDNS_UART_BAUDGEN); | |
464 | writel(bdiv, port->membase + CDNS_UART_BAUDDIV); | |
d9bb3fb1 | 465 | cdns_uart->baud = baud; |
61ec9016 JL |
466 | |
467 | return calc_baud; | |
468 | } | |
469 | ||
7ac57347 | 470 | #ifdef CONFIG_COMMON_CLK |
c4b0510c | 471 | /** |
d9bb3fb1 | 472 | * cdns_uart_clk_notitifer_cb - Clock notifier callback |
c4b0510c SB |
473 | * @nb: Notifier block |
474 | * @event: Notify event | |
475 | * @data: Notifier data | |
e555a211 | 476 | * Return: NOTIFY_OK or NOTIFY_DONE on success, NOTIFY_BAD on error. |
c4b0510c | 477 | */ |
d9bb3fb1 | 478 | static int cdns_uart_clk_notifier_cb(struct notifier_block *nb, |
c4b0510c SB |
479 | unsigned long event, void *data) |
480 | { | |
481 | u32 ctrl_reg; | |
482 | struct uart_port *port; | |
483 | int locked = 0; | |
484 | struct clk_notifier_data *ndata = data; | |
485 | unsigned long flags = 0; | |
d9bb3fb1 | 486 | struct cdns_uart *cdns_uart = to_cdns_uart(nb); |
c4b0510c | 487 | |
d9bb3fb1 | 488 | port = cdns_uart->port; |
c4b0510c SB |
489 | if (port->suspended) |
490 | return NOTIFY_OK; | |
491 | ||
492 | switch (event) { | |
493 | case PRE_RATE_CHANGE: | |
494 | { | |
e555a211 | 495 | u32 bdiv, cd; |
c4b0510c SB |
496 | int div8; |
497 | ||
498 | /* | |
499 | * Find out if current baud-rate can be achieved with new clock | |
500 | * frequency. | |
501 | */ | |
d9bb3fb1 | 502 | if (!cdns_uart_calc_baud_divs(ndata->new_rate, cdns_uart->baud, |
5ce15d2d SB |
503 | &bdiv, &cd, &div8)) { |
504 | dev_warn(port->dev, "clock rate change rejected\n"); | |
c4b0510c | 505 | return NOTIFY_BAD; |
5ce15d2d | 506 | } |
c4b0510c | 507 | |
d9bb3fb1 | 508 | spin_lock_irqsave(&cdns_uart->port->lock, flags); |
c4b0510c SB |
509 | |
510 | /* Disable the TX and RX to set baud rate */ | |
a8df6a51 | 511 | ctrl_reg = readl(port->membase + CDNS_UART_CR); |
d9bb3fb1 | 512 | ctrl_reg |= CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS; |
a8df6a51 | 513 | writel(ctrl_reg, port->membase + CDNS_UART_CR); |
c4b0510c | 514 | |
d9bb3fb1 | 515 | spin_unlock_irqrestore(&cdns_uart->port->lock, flags); |
c4b0510c SB |
516 | |
517 | return NOTIFY_OK; | |
518 | } | |
519 | case POST_RATE_CHANGE: | |
520 | /* | |
521 | * Set clk dividers to generate correct baud with new clock | |
522 | * frequency. | |
523 | */ | |
524 | ||
d9bb3fb1 | 525 | spin_lock_irqsave(&cdns_uart->port->lock, flags); |
c4b0510c SB |
526 | |
527 | locked = 1; | |
528 | port->uartclk = ndata->new_rate; | |
529 | ||
d9bb3fb1 SB |
530 | cdns_uart->baud = cdns_uart_set_baud_rate(cdns_uart->port, |
531 | cdns_uart->baud); | |
c4b0510c SB |
532 | /* fall through */ |
533 | case ABORT_RATE_CHANGE: | |
534 | if (!locked) | |
d9bb3fb1 | 535 | spin_lock_irqsave(&cdns_uart->port->lock, flags); |
c4b0510c SB |
536 | |
537 | /* Set TX/RX Reset */ | |
a8df6a51 | 538 | ctrl_reg = readl(port->membase + CDNS_UART_CR); |
d9bb3fb1 | 539 | ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST; |
a8df6a51 | 540 | writel(ctrl_reg, port->membase + CDNS_UART_CR); |
c4b0510c | 541 | |
a8df6a51 | 542 | while (readl(port->membase + CDNS_UART_CR) & |
d9bb3fb1 | 543 | (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST)) |
c4b0510c SB |
544 | cpu_relax(); |
545 | ||
546 | /* | |
547 | * Clear the RX disable and TX disable bits and then set the TX | |
548 | * enable bit and RX enable bit to enable the transmitter and | |
549 | * receiver. | |
550 | */ | |
a8df6a51 SB |
551 | writel(rx_timeout, port->membase + CDNS_UART_RXTOUT); |
552 | ctrl_reg = readl(port->membase + CDNS_UART_CR); | |
d9bb3fb1 SB |
553 | ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS); |
554 | ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN; | |
a8df6a51 | 555 | writel(ctrl_reg, port->membase + CDNS_UART_CR); |
c4b0510c | 556 | |
d9bb3fb1 | 557 | spin_unlock_irqrestore(&cdns_uart->port->lock, flags); |
c4b0510c SB |
558 | |
559 | return NOTIFY_OK; | |
560 | default: | |
561 | return NOTIFY_DONE; | |
562 | } | |
563 | } | |
7ac57347 | 564 | #endif |
c4b0510c | 565 | |
61ec9016 | 566 | /** |
d9bb3fb1 | 567 | * cdns_uart_start_tx - Start transmitting bytes |
61ec9016 | 568 | * @port: Handle to the uart port structure |
489810a1 | 569 | */ |
d9bb3fb1 | 570 | static void cdns_uart_start_tx(struct uart_port *port) |
61ec9016 | 571 | { |
07986580 | 572 | unsigned int status; |
61ec9016 | 573 | |
ea8dd8e5 | 574 | if (uart_tx_stopped(port)) |
61ec9016 JL |
575 | return; |
576 | ||
e3538c37 SB |
577 | /* |
578 | * Set the TX enable bit and clear the TX disable bit to enable the | |
61ec9016 JL |
579 | * transmitter. |
580 | */ | |
a8df6a51 | 581 | status = readl(port->membase + CDNS_UART_CR); |
e3538c37 SB |
582 | status &= ~CDNS_UART_CR_TX_DIS; |
583 | status |= CDNS_UART_CR_TX_EN; | |
a8df6a51 | 584 | writel(status, port->membase + CDNS_UART_CR); |
61ec9016 | 585 | |
ea8dd8e5 SB |
586 | if (uart_circ_empty(&port->state->xmit)) |
587 | return; | |
588 | ||
07986580 | 589 | cdns_uart_handle_tx(port); |
61ec9016 | 590 | |
a8df6a51 | 591 | writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_ISR); |
61ec9016 | 592 | /* Enable the TX Empty interrupt */ |
a8df6a51 | 593 | writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_IER); |
61ec9016 JL |
594 | } |
595 | ||
596 | /** | |
d9bb3fb1 | 597 | * cdns_uart_stop_tx - Stop TX |
61ec9016 | 598 | * @port: Handle to the uart port structure |
489810a1 | 599 | */ |
d9bb3fb1 | 600 | static void cdns_uart_stop_tx(struct uart_port *port) |
61ec9016 JL |
601 | { |
602 | unsigned int regval; | |
603 | ||
a8df6a51 | 604 | regval = readl(port->membase + CDNS_UART_CR); |
d9bb3fb1 | 605 | regval |= CDNS_UART_CR_TX_DIS; |
61ec9016 | 606 | /* Disable the transmitter */ |
a8df6a51 | 607 | writel(regval, port->membase + CDNS_UART_CR); |
61ec9016 JL |
608 | } |
609 | ||
610 | /** | |
d9bb3fb1 | 611 | * cdns_uart_stop_rx - Stop RX |
61ec9016 | 612 | * @port: Handle to the uart port structure |
489810a1 | 613 | */ |
d9bb3fb1 | 614 | static void cdns_uart_stop_rx(struct uart_port *port) |
61ec9016 JL |
615 | { |
616 | unsigned int regval; | |
617 | ||
373e882f | 618 | /* Disable RX IRQs */ |
a8df6a51 | 619 | writel(CDNS_UART_RX_IRQS, port->membase + CDNS_UART_IDR); |
373e882f SB |
620 | |
621 | /* Disable the receiver */ | |
a8df6a51 | 622 | regval = readl(port->membase + CDNS_UART_CR); |
d9bb3fb1 | 623 | regval |= CDNS_UART_CR_RX_DIS; |
a8df6a51 | 624 | writel(regval, port->membase + CDNS_UART_CR); |
61ec9016 JL |
625 | } |
626 | ||
627 | /** | |
d9bb3fb1 | 628 | * cdns_uart_tx_empty - Check whether TX is empty |
61ec9016 JL |
629 | * @port: Handle to the uart port structure |
630 | * | |
489810a1 MS |
631 | * Return: TIOCSER_TEMT on success, 0 otherwise |
632 | */ | |
d9bb3fb1 | 633 | static unsigned int cdns_uart_tx_empty(struct uart_port *port) |
61ec9016 JL |
634 | { |
635 | unsigned int status; | |
636 | ||
a8df6a51 | 637 | status = readl(port->membase + CDNS_UART_SR) & |
19f22efd | 638 | CDNS_UART_SR_TXEMPTY; |
61ec9016 JL |
639 | return status ? TIOCSER_TEMT : 0; |
640 | } | |
641 | ||
642 | /** | |
d9bb3fb1 | 643 | * cdns_uart_break_ctl - Based on the input ctl we have to start or stop |
61ec9016 JL |
644 | * transmitting char breaks |
645 | * @port: Handle to the uart port structure | |
646 | * @ctl: Value based on which start or stop decision is taken | |
489810a1 | 647 | */ |
d9bb3fb1 | 648 | static void cdns_uart_break_ctl(struct uart_port *port, int ctl) |
61ec9016 JL |
649 | { |
650 | unsigned int status; | |
651 | unsigned long flags; | |
652 | ||
653 | spin_lock_irqsave(&port->lock, flags); | |
654 | ||
a8df6a51 | 655 | status = readl(port->membase + CDNS_UART_CR); |
61ec9016 JL |
656 | |
657 | if (ctl == -1) | |
19f22efd | 658 | writel(CDNS_UART_CR_STARTBRK | status, |
a8df6a51 | 659 | port->membase + CDNS_UART_CR); |
61ec9016 | 660 | else { |
d9bb3fb1 | 661 | if ((status & CDNS_UART_CR_STOPBRK) == 0) |
19f22efd | 662 | writel(CDNS_UART_CR_STOPBRK | status, |
a8df6a51 | 663 | port->membase + CDNS_UART_CR); |
61ec9016 JL |
664 | } |
665 | spin_unlock_irqrestore(&port->lock, flags); | |
666 | } | |
667 | ||
668 | /** | |
d9bb3fb1 | 669 | * cdns_uart_set_termios - termios operations, handling data length, parity, |
61ec9016 JL |
670 | * stop bits, flow control, baud rate |
671 | * @port: Handle to the uart port structure | |
672 | * @termios: Handle to the input termios structure | |
673 | * @old: Values of the previously saved termios structure | |
489810a1 | 674 | */ |
d9bb3fb1 | 675 | static void cdns_uart_set_termios(struct uart_port *port, |
61ec9016 JL |
676 | struct ktermios *termios, struct ktermios *old) |
677 | { | |
678 | unsigned int cval = 0; | |
e6b39bfd | 679 | unsigned int baud, minbaud, maxbaud; |
61ec9016 JL |
680 | unsigned long flags; |
681 | unsigned int ctrl_reg, mode_reg; | |
682 | ||
683 | spin_lock_irqsave(&port->lock, flags); | |
684 | ||
6ecde472 | 685 | /* Wait for the transmit FIFO to empty before making changes */ |
a8df6a51 | 686 | if (!(readl(port->membase + CDNS_UART_CR) & |
19f22efd | 687 | CDNS_UART_CR_TX_DIS)) { |
a8df6a51 | 688 | while (!(readl(port->membase + CDNS_UART_SR) & |
6ecde472 NR |
689 | CDNS_UART_SR_TXEMPTY)) { |
690 | cpu_relax(); | |
691 | } | |
61ec9016 JL |
692 | } |
693 | ||
694 | /* Disable the TX and RX to set baud rate */ | |
a8df6a51 | 695 | ctrl_reg = readl(port->membase + CDNS_UART_CR); |
d9bb3fb1 | 696 | ctrl_reg |= CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS; |
a8df6a51 | 697 | writel(ctrl_reg, port->membase + CDNS_UART_CR); |
61ec9016 | 698 | |
e6b39bfd SB |
699 | /* |
700 | * Min baud rate = 6bps and Max Baud Rate is 10Mbps for 100Mhz clk | |
701 | * min and max baud should be calculated here based on port->uartclk. | |
702 | * this way we get a valid baud and can safely call set_baud() | |
703 | */ | |
d9bb3fb1 SB |
704 | minbaud = port->uartclk / |
705 | ((CDNS_UART_BDIV_MAX + 1) * CDNS_UART_CD_MAX * 8); | |
706 | maxbaud = port->uartclk / (CDNS_UART_BDIV_MIN + 1); | |
e6b39bfd | 707 | baud = uart_get_baud_rate(port, termios, old, minbaud, maxbaud); |
d9bb3fb1 | 708 | baud = cdns_uart_set_baud_rate(port, baud); |
61ec9016 JL |
709 | if (tty_termios_baud_rate(termios)) |
710 | tty_termios_encode_baud_rate(termios, baud, baud); | |
711 | ||
e555a211 | 712 | /* Update the per-port timeout. */ |
61ec9016 JL |
713 | uart_update_timeout(port, termios->c_cflag, baud); |
714 | ||
715 | /* Set TX/RX Reset */ | |
a8df6a51 | 716 | ctrl_reg = readl(port->membase + CDNS_UART_CR); |
d9bb3fb1 | 717 | ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST; |
a8df6a51 | 718 | writel(ctrl_reg, port->membase + CDNS_UART_CR); |
61ec9016 | 719 | |
27b17ae0 NM |
720 | while (readl(port->membase + CDNS_UART_CR) & |
721 | (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST)) | |
722 | cpu_relax(); | |
723 | ||
e555a211 SB |
724 | /* |
725 | * Clear the RX disable and TX disable bits and then set the TX enable | |
61ec9016 JL |
726 | * bit and RX enable bit to enable the transmitter and receiver. |
727 | */ | |
a8df6a51 | 728 | ctrl_reg = readl(port->membase + CDNS_UART_CR); |
d9bb3fb1 SB |
729 | ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS); |
730 | ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN; | |
a8df6a51 | 731 | writel(ctrl_reg, port->membase + CDNS_UART_CR); |
61ec9016 | 732 | |
a8df6a51 | 733 | writel(rx_timeout, port->membase + CDNS_UART_RXTOUT); |
61ec9016 | 734 | |
d9bb3fb1 SB |
735 | port->read_status_mask = CDNS_UART_IXR_TXEMPTY | CDNS_UART_IXR_RXTRIG | |
736 | CDNS_UART_IXR_OVERRUN | CDNS_UART_IXR_TOUT; | |
61ec9016 JL |
737 | port->ignore_status_mask = 0; |
738 | ||
739 | if (termios->c_iflag & INPCK) | |
d9bb3fb1 SB |
740 | port->read_status_mask |= CDNS_UART_IXR_PARITY | |
741 | CDNS_UART_IXR_FRAMING; | |
61ec9016 JL |
742 | |
743 | if (termios->c_iflag & IGNPAR) | |
d9bb3fb1 SB |
744 | port->ignore_status_mask |= CDNS_UART_IXR_PARITY | |
745 | CDNS_UART_IXR_FRAMING | CDNS_UART_IXR_OVERRUN; | |
61ec9016 JL |
746 | |
747 | /* ignore all characters if CREAD is not set */ | |
748 | if ((termios->c_cflag & CREAD) == 0) | |
d9bb3fb1 SB |
749 | port->ignore_status_mask |= CDNS_UART_IXR_RXTRIG | |
750 | CDNS_UART_IXR_TOUT | CDNS_UART_IXR_PARITY | | |
751 | CDNS_UART_IXR_FRAMING | CDNS_UART_IXR_OVERRUN; | |
61ec9016 | 752 | |
a8df6a51 | 753 | mode_reg = readl(port->membase + CDNS_UART_MR); |
61ec9016 JL |
754 | |
755 | /* Handling Data Size */ | |
756 | switch (termios->c_cflag & CSIZE) { | |
757 | case CS6: | |
d9bb3fb1 | 758 | cval |= CDNS_UART_MR_CHARLEN_6_BIT; |
61ec9016 JL |
759 | break; |
760 | case CS7: | |
d9bb3fb1 | 761 | cval |= CDNS_UART_MR_CHARLEN_7_BIT; |
61ec9016 JL |
762 | break; |
763 | default: | |
764 | case CS8: | |
d9bb3fb1 | 765 | cval |= CDNS_UART_MR_CHARLEN_8_BIT; |
61ec9016 JL |
766 | termios->c_cflag &= ~CSIZE; |
767 | termios->c_cflag |= CS8; | |
768 | break; | |
769 | } | |
770 | ||
771 | /* Handling Parity and Stop Bits length */ | |
772 | if (termios->c_cflag & CSTOPB) | |
d9bb3fb1 | 773 | cval |= CDNS_UART_MR_STOPMODE_2_BIT; /* 2 STOP bits */ |
61ec9016 | 774 | else |
d9bb3fb1 | 775 | cval |= CDNS_UART_MR_STOPMODE_1_BIT; /* 1 STOP bit */ |
61ec9016 JL |
776 | |
777 | if (termios->c_cflag & PARENB) { | |
778 | /* Mark or Space parity */ | |
779 | if (termios->c_cflag & CMSPAR) { | |
780 | if (termios->c_cflag & PARODD) | |
d9bb3fb1 | 781 | cval |= CDNS_UART_MR_PARITY_MARK; |
61ec9016 | 782 | else |
d9bb3fb1 | 783 | cval |= CDNS_UART_MR_PARITY_SPACE; |
e6b39bfd SB |
784 | } else { |
785 | if (termios->c_cflag & PARODD) | |
d9bb3fb1 | 786 | cval |= CDNS_UART_MR_PARITY_ODD; |
61ec9016 | 787 | else |
d9bb3fb1 | 788 | cval |= CDNS_UART_MR_PARITY_EVEN; |
e6b39bfd SB |
789 | } |
790 | } else { | |
d9bb3fb1 | 791 | cval |= CDNS_UART_MR_PARITY_NONE; |
e6b39bfd SB |
792 | } |
793 | cval |= mode_reg & 1; | |
a8df6a51 | 794 | writel(cval, port->membase + CDNS_UART_MR); |
61ec9016 JL |
795 | |
796 | spin_unlock_irqrestore(&port->lock, flags); | |
797 | } | |
798 | ||
799 | /** | |
d9bb3fb1 | 800 | * cdns_uart_startup - Called when an application opens a cdns_uart port |
61ec9016 JL |
801 | * @port: Handle to the uart port structure |
802 | * | |
e555a211 | 803 | * Return: 0 on success, negative errno otherwise |
489810a1 | 804 | */ |
d9bb3fb1 | 805 | static int cdns_uart_startup(struct uart_port *port) |
61ec9016 | 806 | { |
3816b2f8 NM |
807 | struct cdns_uart *cdns_uart = port->private_data; |
808 | bool is_brk_support; | |
55861d11 | 809 | int ret; |
6e14f7c1 | 810 | unsigned long flags; |
55861d11 | 811 | unsigned int status = 0; |
61ec9016 | 812 | |
3816b2f8 NM |
813 | is_brk_support = cdns_uart->quirks & CDNS_UART_RXBS_SUPPORT; |
814 | ||
6e14f7c1 SB |
815 | spin_lock_irqsave(&port->lock, flags); |
816 | ||
61ec9016 | 817 | /* Disable the TX and RX */ |
19f22efd | 818 | writel(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS, |
a8df6a51 | 819 | port->membase + CDNS_UART_CR); |
61ec9016 JL |
820 | |
821 | /* Set the Control Register with TX/RX Enable, TX/RX Reset, | |
822 | * no break chars. | |
823 | */ | |
19f22efd | 824 | writel(CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST, |
a8df6a51 | 825 | port->membase + CDNS_UART_CR); |
61ec9016 | 826 | |
27b17ae0 NM |
827 | while (readl(port->membase + CDNS_UART_CR) & |
828 | (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST)) | |
829 | cpu_relax(); | |
830 | ||
6e14f7c1 SB |
831 | /* |
832 | * Clear the RX disable bit and then set the RX enable bit to enable | |
833 | * the receiver. | |
61ec9016 | 834 | */ |
a8df6a51 | 835 | status = readl(port->membase + CDNS_UART_CR); |
6e14f7c1 SB |
836 | status &= CDNS_UART_CR_RX_DIS; |
837 | status |= CDNS_UART_CR_RX_EN; | |
a8df6a51 | 838 | writel(status, port->membase + CDNS_UART_CR); |
61ec9016 JL |
839 | |
840 | /* Set the Mode Register with normal mode,8 data bits,1 stop bit, | |
841 | * no parity. | |
842 | */ | |
19f22efd | 843 | writel(CDNS_UART_MR_CHMODE_NORM | CDNS_UART_MR_STOPMODE_1_BIT |
d9bb3fb1 | 844 | | CDNS_UART_MR_PARITY_NONE | CDNS_UART_MR_CHARLEN_8_BIT, |
a8df6a51 | 845 | port->membase + CDNS_UART_MR); |
61ec9016 | 846 | |
85baf542 S |
847 | /* |
848 | * Set the RX FIFO Trigger level to use most of the FIFO, but it | |
849 | * can be tuned with a module parameter | |
850 | */ | |
a8df6a51 | 851 | writel(rx_trigger_level, port->membase + CDNS_UART_RXWM); |
61ec9016 | 852 | |
85baf542 S |
853 | /* |
854 | * Receive Timeout register is enabled but it | |
855 | * can be tuned with a module parameter | |
856 | */ | |
a8df6a51 | 857 | writel(rx_timeout, port->membase + CDNS_UART_RXTOUT); |
61ec9016 | 858 | |
855f6fd9 | 859 | /* Clear out any pending interrupts before enabling them */ |
a8df6a51 SB |
860 | writel(readl(port->membase + CDNS_UART_ISR), |
861 | port->membase + CDNS_UART_ISR); | |
61ec9016 | 862 | |
55861d11 SB |
863 | spin_unlock_irqrestore(&port->lock, flags); |
864 | ||
865 | ret = request_irq(port->irq, cdns_uart_isr, 0, CDNS_UART_NAME, port); | |
866 | if (ret) { | |
867 | dev_err(port->dev, "request_irq '%d' failed with %d\n", | |
868 | port->irq, ret); | |
869 | return ret; | |
870 | } | |
871 | ||
61ec9016 | 872 | /* Set the Interrupt Registers with desired interrupts */ |
3816b2f8 NM |
873 | if (is_brk_support) |
874 | writel(CDNS_UART_RX_IRQS | CDNS_UART_IXR_BRK, | |
875 | port->membase + CDNS_UART_IER); | |
876 | else | |
877 | writel(CDNS_UART_RX_IRQS, port->membase + CDNS_UART_IER); | |
61ec9016 | 878 | |
55861d11 | 879 | return 0; |
61ec9016 JL |
880 | } |
881 | ||
882 | /** | |
d9bb3fb1 | 883 | * cdns_uart_shutdown - Called when an application closes a cdns_uart port |
61ec9016 | 884 | * @port: Handle to the uart port structure |
489810a1 | 885 | */ |
d9bb3fb1 | 886 | static void cdns_uart_shutdown(struct uart_port *port) |
61ec9016 JL |
887 | { |
888 | int status; | |
a19eda0f SB |
889 | unsigned long flags; |
890 | ||
891 | spin_lock_irqsave(&port->lock, flags); | |
61ec9016 JL |
892 | |
893 | /* Disable interrupts */ | |
a8df6a51 SB |
894 | status = readl(port->membase + CDNS_UART_IMR); |
895 | writel(status, port->membase + CDNS_UART_IDR); | |
896 | writel(0xffffffff, port->membase + CDNS_UART_ISR); | |
61ec9016 JL |
897 | |
898 | /* Disable the TX and RX */ | |
19f22efd | 899 | writel(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS, |
a8df6a51 | 900 | port->membase + CDNS_UART_CR); |
a19eda0f SB |
901 | |
902 | spin_unlock_irqrestore(&port->lock, flags); | |
903 | ||
61ec9016 JL |
904 | free_irq(port->irq, port); |
905 | } | |
906 | ||
907 | /** | |
d9bb3fb1 | 908 | * cdns_uart_type - Set UART type to cdns_uart port |
61ec9016 JL |
909 | * @port: Handle to the uart port structure |
910 | * | |
489810a1 MS |
911 | * Return: string on success, NULL otherwise |
912 | */ | |
d9bb3fb1 | 913 | static const char *cdns_uart_type(struct uart_port *port) |
61ec9016 | 914 | { |
d9bb3fb1 | 915 | return port->type == PORT_XUARTPS ? CDNS_UART_NAME : NULL; |
61ec9016 JL |
916 | } |
917 | ||
918 | /** | |
d9bb3fb1 | 919 | * cdns_uart_verify_port - Verify the port params |
61ec9016 JL |
920 | * @port: Handle to the uart port structure |
921 | * @ser: Handle to the structure whose members are compared | |
922 | * | |
e555a211 | 923 | * Return: 0 on success, negative errno otherwise. |
489810a1 | 924 | */ |
d9bb3fb1 | 925 | static int cdns_uart_verify_port(struct uart_port *port, |
61ec9016 JL |
926 | struct serial_struct *ser) |
927 | { | |
928 | if (ser->type != PORT_UNKNOWN && ser->type != PORT_XUARTPS) | |
929 | return -EINVAL; | |
930 | if (port->irq != ser->irq) | |
931 | return -EINVAL; | |
932 | if (ser->io_type != UPIO_MEM) | |
933 | return -EINVAL; | |
934 | if (port->iobase != ser->port) | |
935 | return -EINVAL; | |
936 | if (ser->hub6 != 0) | |
937 | return -EINVAL; | |
938 | return 0; | |
939 | } | |
940 | ||
941 | /** | |
d9bb3fb1 SB |
942 | * cdns_uart_request_port - Claim the memory region attached to cdns_uart port, |
943 | * called when the driver adds a cdns_uart port via | |
61ec9016 JL |
944 | * uart_add_one_port() |
945 | * @port: Handle to the uart port structure | |
946 | * | |
e555a211 | 947 | * Return: 0 on success, negative errno otherwise. |
489810a1 | 948 | */ |
d9bb3fb1 | 949 | static int cdns_uart_request_port(struct uart_port *port) |
61ec9016 | 950 | { |
d9bb3fb1 SB |
951 | if (!request_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE, |
952 | CDNS_UART_NAME)) { | |
61ec9016 JL |
953 | return -ENOMEM; |
954 | } | |
955 | ||
d9bb3fb1 | 956 | port->membase = ioremap(port->mapbase, CDNS_UART_REGISTER_SPACE); |
61ec9016 JL |
957 | if (!port->membase) { |
958 | dev_err(port->dev, "Unable to map registers\n"); | |
d9bb3fb1 | 959 | release_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE); |
61ec9016 JL |
960 | return -ENOMEM; |
961 | } | |
962 | return 0; | |
963 | } | |
964 | ||
965 | /** | |
d9bb3fb1 | 966 | * cdns_uart_release_port - Release UART port |
61ec9016 | 967 | * @port: Handle to the uart port structure |
e555a211 | 968 | * |
d9bb3fb1 SB |
969 | * Release the memory region attached to a cdns_uart port. Called when the |
970 | * driver removes a cdns_uart port via uart_remove_one_port(). | |
489810a1 | 971 | */ |
d9bb3fb1 | 972 | static void cdns_uart_release_port(struct uart_port *port) |
61ec9016 | 973 | { |
d9bb3fb1 | 974 | release_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE); |
61ec9016 JL |
975 | iounmap(port->membase); |
976 | port->membase = NULL; | |
977 | } | |
978 | ||
979 | /** | |
d9bb3fb1 | 980 | * cdns_uart_config_port - Configure UART port |
61ec9016 JL |
981 | * @port: Handle to the uart port structure |
982 | * @flags: If any | |
489810a1 | 983 | */ |
d9bb3fb1 | 984 | static void cdns_uart_config_port(struct uart_port *port, int flags) |
61ec9016 | 985 | { |
d9bb3fb1 | 986 | if (flags & UART_CONFIG_TYPE && cdns_uart_request_port(port) == 0) |
61ec9016 JL |
987 | port->type = PORT_XUARTPS; |
988 | } | |
989 | ||
990 | /** | |
d9bb3fb1 | 991 | * cdns_uart_get_mctrl - Get the modem control state |
61ec9016 JL |
992 | * @port: Handle to the uart port structure |
993 | * | |
489810a1 MS |
994 | * Return: the modem control state |
995 | */ | |
d9bb3fb1 | 996 | static unsigned int cdns_uart_get_mctrl(struct uart_port *port) |
61ec9016 JL |
997 | { |
998 | return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR; | |
999 | } | |
1000 | ||
d9bb3fb1 | 1001 | static void cdns_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) |
61ec9016 | 1002 | { |
19038ad9 | 1003 | u32 val; |
5935a2b3 | 1004 | u32 mode_reg; |
19038ad9 | 1005 | |
a8df6a51 | 1006 | val = readl(port->membase + CDNS_UART_MODEMCR); |
5935a2b3 | 1007 | mode_reg = readl(port->membase + CDNS_UART_MR); |
19038ad9 LPC |
1008 | |
1009 | val &= ~(CDNS_UART_MODEMCR_RTS | CDNS_UART_MODEMCR_DTR); | |
5935a2b3 | 1010 | mode_reg &= ~CDNS_UART_MR_CHMODE_MASK; |
19038ad9 LPC |
1011 | |
1012 | if (mctrl & TIOCM_RTS) | |
1013 | val |= CDNS_UART_MODEMCR_RTS; | |
1014 | if (mctrl & TIOCM_DTR) | |
1015 | val |= CDNS_UART_MODEMCR_DTR; | |
5935a2b3 YK |
1016 | if (mctrl & TIOCM_LOOP) |
1017 | mode_reg |= CDNS_UART_MR_CHMODE_L_LOOP; | |
1018 | else | |
1019 | mode_reg |= CDNS_UART_MR_CHMODE_NORM; | |
19038ad9 | 1020 | |
a8df6a51 | 1021 | writel(val, port->membase + CDNS_UART_MODEMCR); |
5935a2b3 | 1022 | writel(mode_reg, port->membase + CDNS_UART_MR); |
61ec9016 JL |
1023 | } |
1024 | ||
6ee04c6c | 1025 | #ifdef CONFIG_CONSOLE_POLL |
d9bb3fb1 | 1026 | static int cdns_uart_poll_get_char(struct uart_port *port) |
6ee04c6c | 1027 | { |
6ee04c6c | 1028 | int c; |
f0f54a80 | 1029 | unsigned long flags; |
6ee04c6c | 1030 | |
f0f54a80 | 1031 | spin_lock_irqsave(&port->lock, flags); |
6ee04c6c VL |
1032 | |
1033 | /* Check if FIFO is empty */ | |
a8df6a51 | 1034 | if (readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_RXEMPTY) |
6ee04c6c VL |
1035 | c = NO_POLL_CHAR; |
1036 | else /* Read a character */ | |
a8df6a51 | 1037 | c = (unsigned char) readl(port->membase + CDNS_UART_FIFO); |
6ee04c6c | 1038 | |
f0f54a80 | 1039 | spin_unlock_irqrestore(&port->lock, flags); |
6ee04c6c VL |
1040 | |
1041 | return c; | |
1042 | } | |
1043 | ||
d9bb3fb1 | 1044 | static void cdns_uart_poll_put_char(struct uart_port *port, unsigned char c) |
6ee04c6c | 1045 | { |
f0f54a80 | 1046 | unsigned long flags; |
6ee04c6c | 1047 | |
f0f54a80 | 1048 | spin_lock_irqsave(&port->lock, flags); |
6ee04c6c VL |
1049 | |
1050 | /* Wait until FIFO is empty */ | |
a8df6a51 | 1051 | while (!(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXEMPTY)) |
6ee04c6c VL |
1052 | cpu_relax(); |
1053 | ||
1054 | /* Write a character */ | |
a8df6a51 | 1055 | writel(c, port->membase + CDNS_UART_FIFO); |
6ee04c6c VL |
1056 | |
1057 | /* Wait until FIFO is empty */ | |
a8df6a51 | 1058 | while (!(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXEMPTY)) |
6ee04c6c VL |
1059 | cpu_relax(); |
1060 | ||
f0f54a80 | 1061 | spin_unlock_irqrestore(&port->lock, flags); |
6ee04c6c VL |
1062 | |
1063 | return; | |
1064 | } | |
1065 | #endif | |
1066 | ||
210417ce SD |
1067 | static void cdns_uart_pm(struct uart_port *port, unsigned int state, |
1068 | unsigned int oldstate) | |
1069 | { | |
210417ce SD |
1070 | switch (state) { |
1071 | case UART_PM_STATE_OFF: | |
d62100f1 SD |
1072 | pm_runtime_mark_last_busy(port->dev); |
1073 | pm_runtime_put_autosuspend(port->dev); | |
210417ce SD |
1074 | break; |
1075 | default: | |
d62100f1 | 1076 | pm_runtime_get_sync(port->dev); |
210417ce SD |
1077 | break; |
1078 | } | |
1079 | } | |
1080 | ||
f098a0ae | 1081 | static const struct uart_ops cdns_uart_ops = { |
d9bb3fb1 SB |
1082 | .set_mctrl = cdns_uart_set_mctrl, |
1083 | .get_mctrl = cdns_uart_get_mctrl, | |
d9bb3fb1 SB |
1084 | .start_tx = cdns_uart_start_tx, |
1085 | .stop_tx = cdns_uart_stop_tx, | |
1086 | .stop_rx = cdns_uart_stop_rx, | |
1087 | .tx_empty = cdns_uart_tx_empty, | |
1088 | .break_ctl = cdns_uart_break_ctl, | |
1089 | .set_termios = cdns_uart_set_termios, | |
1090 | .startup = cdns_uart_startup, | |
1091 | .shutdown = cdns_uart_shutdown, | |
210417ce | 1092 | .pm = cdns_uart_pm, |
d9bb3fb1 SB |
1093 | .type = cdns_uart_type, |
1094 | .verify_port = cdns_uart_verify_port, | |
1095 | .request_port = cdns_uart_request_port, | |
1096 | .release_port = cdns_uart_release_port, | |
1097 | .config_port = cdns_uart_config_port, | |
6ee04c6c | 1098 | #ifdef CONFIG_CONSOLE_POLL |
d9bb3fb1 SB |
1099 | .poll_get_char = cdns_uart_poll_get_char, |
1100 | .poll_put_char = cdns_uart_poll_put_char, | |
6ee04c6c | 1101 | #endif |
61ec9016 JL |
1102 | }; |
1103 | ||
6db6df0e | 1104 | static struct uart_port cdns_uart_port[CDNS_UART_NR_PORTS]; |
61ec9016 JL |
1105 | |
1106 | /** | |
d9bb3fb1 | 1107 | * cdns_uart_get_port - Configure the port from platform device resource info |
928e9263 MS |
1108 | * @id: Port id |
1109 | * | |
489810a1 MS |
1110 | * Return: a pointer to a uart_port or NULL for failure |
1111 | */ | |
d9bb3fb1 | 1112 | static struct uart_port *cdns_uart_get_port(int id) |
61ec9016 JL |
1113 | { |
1114 | struct uart_port *port; | |
61ec9016 | 1115 | |
928e9263 | 1116 | /* Try the given port id if failed use default method */ |
d9bb3fb1 | 1117 | if (cdns_uart_port[id].mapbase != 0) { |
928e9263 | 1118 | /* Find the next unused port */ |
d9bb3fb1 SB |
1119 | for (id = 0; id < CDNS_UART_NR_PORTS; id++) |
1120 | if (cdns_uart_port[id].mapbase == 0) | |
928e9263 MS |
1121 | break; |
1122 | } | |
61ec9016 | 1123 | |
d9bb3fb1 | 1124 | if (id >= CDNS_UART_NR_PORTS) |
61ec9016 JL |
1125 | return NULL; |
1126 | ||
d9bb3fb1 | 1127 | port = &cdns_uart_port[id]; |
61ec9016 JL |
1128 | |
1129 | /* At this point, we've got an empty uart_port struct, initialize it */ | |
1130 | spin_lock_init(&port->lock); | |
1131 | port->membase = NULL; | |
61ec9016 JL |
1132 | port->irq = 0; |
1133 | port->type = PORT_UNKNOWN; | |
1134 | port->iotype = UPIO_MEM32; | |
1135 | port->flags = UPF_BOOT_AUTOCONF; | |
d9bb3fb1 SB |
1136 | port->ops = &cdns_uart_ops; |
1137 | port->fifosize = CDNS_UART_FIFO_SIZE; | |
61ec9016 JL |
1138 | port->line = id; |
1139 | port->dev = NULL; | |
1140 | return port; | |
1141 | } | |
1142 | ||
61ec9016 JL |
1143 | #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE |
1144 | /** | |
d9bb3fb1 | 1145 | * cdns_uart_console_wait_tx - Wait for the TX to be full |
61ec9016 | 1146 | * @port: Handle to the uart port structure |
489810a1 | 1147 | */ |
d9bb3fb1 | 1148 | static void cdns_uart_console_wait_tx(struct uart_port *port) |
61ec9016 | 1149 | { |
a8df6a51 | 1150 | while (!(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXEMPTY)) |
61ec9016 JL |
1151 | barrier(); |
1152 | } | |
1153 | ||
1154 | /** | |
d9bb3fb1 | 1155 | * cdns_uart_console_putchar - write the character to the FIFO buffer |
61ec9016 JL |
1156 | * @port: Handle to the uart port structure |
1157 | * @ch: Character to be written | |
489810a1 | 1158 | */ |
d9bb3fb1 | 1159 | static void cdns_uart_console_putchar(struct uart_port *port, int ch) |
61ec9016 | 1160 | { |
d9bb3fb1 | 1161 | cdns_uart_console_wait_tx(port); |
a8df6a51 | 1162 | writel(ch, port->membase + CDNS_UART_FIFO); |
61ec9016 JL |
1163 | } |
1164 | ||
54585ba0 MY |
1165 | static void __init cdns_early_write(struct console *con, const char *s, |
1166 | unsigned n) | |
6fa62fc4 MS |
1167 | { |
1168 | struct earlycon_device *dev = con->data; | |
1169 | ||
1170 | uart_console_write(&dev->port, s, n, cdns_uart_console_putchar); | |
1171 | } | |
1172 | ||
1173 | static int __init cdns_early_console_setup(struct earlycon_device *device, | |
1174 | const char *opt) | |
1175 | { | |
c41251b1 ST |
1176 | struct uart_port *port = &device->port; |
1177 | ||
1178 | if (!port->membase) | |
6fa62fc4 MS |
1179 | return -ENODEV; |
1180 | ||
c41251b1 ST |
1181 | /* initialise control register */ |
1182 | writel(CDNS_UART_CR_TX_EN|CDNS_UART_CR_TXRST|CDNS_UART_CR_RXRST, | |
1183 | port->membase + CDNS_UART_CR); | |
1184 | ||
1185 | /* only set baud if specified on command line - otherwise | |
1186 | * assume it has been initialized by a boot loader. | |
1187 | */ | |
1188 | if (device->baud) { | |
1189 | u32 cd = 0, bdiv = 0; | |
1190 | u32 mr; | |
1191 | int div8; | |
1192 | ||
1193 | cdns_uart_calc_baud_divs(port->uartclk, device->baud, | |
1194 | &bdiv, &cd, &div8); | |
1195 | mr = CDNS_UART_MR_PARITY_NONE; | |
1196 | if (div8) | |
1197 | mr |= CDNS_UART_MR_CLKSEL; | |
1198 | ||
1199 | writel(mr, port->membase + CDNS_UART_MR); | |
1200 | writel(cd, port->membase + CDNS_UART_BAUDGEN); | |
1201 | writel(bdiv, port->membase + CDNS_UART_BAUDDIV); | |
1202 | } | |
1203 | ||
6fa62fc4 MS |
1204 | device->con->write = cdns_early_write; |
1205 | ||
1206 | return 0; | |
1207 | } | |
93d7bbaa MS |
1208 | OF_EARLYCON_DECLARE(cdns, "xlnx,xuartps", cdns_early_console_setup); |
1209 | OF_EARLYCON_DECLARE(cdns, "cdns,uart-r1p8", cdns_early_console_setup); | |
1210 | OF_EARLYCON_DECLARE(cdns, "cdns,uart-r1p12", cdns_early_console_setup); | |
0267a4ff | 1211 | OF_EARLYCON_DECLARE(cdns, "xlnx,zynqmp-uart", cdns_early_console_setup); |
6fa62fc4 | 1212 | |
61ec9016 | 1213 | /** |
d9bb3fb1 | 1214 | * cdns_uart_console_write - perform write operation |
489810a1 | 1215 | * @co: Console handle |
61ec9016 JL |
1216 | * @s: Pointer to character array |
1217 | * @count: No of characters | |
489810a1 | 1218 | */ |
d9bb3fb1 | 1219 | static void cdns_uart_console_write(struct console *co, const char *s, |
61ec9016 JL |
1220 | unsigned int count) |
1221 | { | |
d9bb3fb1 | 1222 | struct uart_port *port = &cdns_uart_port[co->index]; |
61ec9016 | 1223 | unsigned long flags; |
d3755f5e | 1224 | unsigned int imr, ctrl; |
61ec9016 JL |
1225 | int locked = 1; |
1226 | ||
74ea66d4 SB |
1227 | if (port->sysrq) |
1228 | locked = 0; | |
1229 | else if (oops_in_progress) | |
61ec9016 JL |
1230 | locked = spin_trylock_irqsave(&port->lock, flags); |
1231 | else | |
1232 | spin_lock_irqsave(&port->lock, flags); | |
1233 | ||
1234 | /* save and disable interrupt */ | |
a8df6a51 SB |
1235 | imr = readl(port->membase + CDNS_UART_IMR); |
1236 | writel(imr, port->membase + CDNS_UART_IDR); | |
61ec9016 | 1237 | |
d3755f5e LPC |
1238 | /* |
1239 | * Make sure that the tx part is enabled. Set the TX enable bit and | |
1240 | * clear the TX disable bit to enable the transmitter. | |
1241 | */ | |
a8df6a51 | 1242 | ctrl = readl(port->membase + CDNS_UART_CR); |
e3538c37 SB |
1243 | ctrl &= ~CDNS_UART_CR_TX_DIS; |
1244 | ctrl |= CDNS_UART_CR_TX_EN; | |
a8df6a51 | 1245 | writel(ctrl, port->membase + CDNS_UART_CR); |
d3755f5e | 1246 | |
d9bb3fb1 SB |
1247 | uart_console_write(port, s, count, cdns_uart_console_putchar); |
1248 | cdns_uart_console_wait_tx(port); | |
61ec9016 | 1249 | |
a8df6a51 | 1250 | writel(ctrl, port->membase + CDNS_UART_CR); |
d3755f5e | 1251 | |
b494a5fa | 1252 | /* restore interrupt state */ |
a8df6a51 | 1253 | writel(imr, port->membase + CDNS_UART_IER); |
61ec9016 JL |
1254 | |
1255 | if (locked) | |
1256 | spin_unlock_irqrestore(&port->lock, flags); | |
1257 | } | |
1258 | ||
1259 | /** | |
d9bb3fb1 | 1260 | * cdns_uart_console_setup - Initialize the uart to default config |
61ec9016 JL |
1261 | * @co: Console handle |
1262 | * @options: Initial settings of uart | |
1263 | * | |
e555a211 | 1264 | * Return: 0 on success, negative errno otherwise. |
489810a1 | 1265 | */ |
d9bb3fb1 | 1266 | static int __init cdns_uart_console_setup(struct console *co, char *options) |
61ec9016 | 1267 | { |
d9bb3fb1 | 1268 | struct uart_port *port = &cdns_uart_port[co->index]; |
61ec9016 JL |
1269 | int baud = 9600; |
1270 | int bits = 8; | |
1271 | int parity = 'n'; | |
1272 | int flow = 'n'; | |
1273 | ||
d9bb3fb1 | 1274 | if (co->index < 0 || co->index >= CDNS_UART_NR_PORTS) |
61ec9016 JL |
1275 | return -EINVAL; |
1276 | ||
136debf7 | 1277 | if (!port->membase) { |
f6415491 PC |
1278 | pr_debug("console on " CDNS_UART_TTY_NAME "%i not present\n", |
1279 | co->index); | |
61ec9016 JL |
1280 | return -ENODEV; |
1281 | } | |
1282 | ||
1283 | if (options) | |
1284 | uart_parse_options(options, &baud, &parity, &bits, &flow); | |
1285 | ||
1286 | return uart_set_options(port, co, baud, parity, bits, flow); | |
1287 | } | |
1288 | ||
d9bb3fb1 | 1289 | static struct uart_driver cdns_uart_uart_driver; |
61ec9016 | 1290 | |
d9bb3fb1 SB |
1291 | static struct console cdns_uart_console = { |
1292 | .name = CDNS_UART_TTY_NAME, | |
1293 | .write = cdns_uart_console_write, | |
61ec9016 | 1294 | .device = uart_console_device, |
d9bb3fb1 | 1295 | .setup = cdns_uart_console_setup, |
61ec9016 JL |
1296 | .flags = CON_PRINTBUFFER, |
1297 | .index = -1, /* Specified on the cmdline (e.g. console=ttyPS ) */ | |
d9bb3fb1 | 1298 | .data = &cdns_uart_uart_driver, |
61ec9016 JL |
1299 | }; |
1300 | ||
1301 | /** | |
d9bb3fb1 | 1302 | * cdns_uart_console_init - Initialization call |
61ec9016 | 1303 | * |
e555a211 | 1304 | * Return: 0 on success, negative errno otherwise |
489810a1 | 1305 | */ |
d9bb3fb1 | 1306 | static int __init cdns_uart_console_init(void) |
61ec9016 | 1307 | { |
d9bb3fb1 | 1308 | register_console(&cdns_uart_console); |
61ec9016 JL |
1309 | return 0; |
1310 | } | |
1311 | ||
d9bb3fb1 | 1312 | console_initcall(cdns_uart_console_init); |
61ec9016 JL |
1313 | |
1314 | #endif /* CONFIG_SERIAL_XILINX_PS_UART_CONSOLE */ | |
1315 | ||
d9bb3fb1 | 1316 | static struct uart_driver cdns_uart_uart_driver = { |
e555a211 | 1317 | .owner = THIS_MODULE, |
d9bb3fb1 SB |
1318 | .driver_name = CDNS_UART_NAME, |
1319 | .dev_name = CDNS_UART_TTY_NAME, | |
1320 | .major = CDNS_UART_MAJOR, | |
1321 | .minor = CDNS_UART_MINOR, | |
1322 | .nr = CDNS_UART_NR_PORTS, | |
d3641f64 | 1323 | #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE |
d9bb3fb1 | 1324 | .cons = &cdns_uart_console, |
d3641f64 SB |
1325 | #endif |
1326 | }; | |
1327 | ||
4b47d9aa SB |
1328 | #ifdef CONFIG_PM_SLEEP |
1329 | /** | |
d9bb3fb1 | 1330 | * cdns_uart_suspend - suspend event |
4b47d9aa SB |
1331 | * @device: Pointer to the device structure |
1332 | * | |
489810a1 | 1333 | * Return: 0 |
4b47d9aa | 1334 | */ |
d9bb3fb1 | 1335 | static int cdns_uart_suspend(struct device *device) |
4b47d9aa SB |
1336 | { |
1337 | struct uart_port *port = dev_get_drvdata(device); | |
1338 | struct tty_struct *tty; | |
1339 | struct device *tty_dev; | |
1340 | int may_wake = 0; | |
1341 | ||
1342 | /* Get the tty which could be NULL so don't assume it's valid */ | |
1343 | tty = tty_port_tty_get(&port->state->port); | |
1344 | if (tty) { | |
1345 | tty_dev = tty->dev; | |
1346 | may_wake = device_may_wakeup(tty_dev); | |
1347 | tty_kref_put(tty); | |
1348 | } | |
1349 | ||
1350 | /* | |
1351 | * Call the API provided in serial_core.c file which handles | |
1352 | * the suspend. | |
1353 | */ | |
d9bb3fb1 | 1354 | uart_suspend_port(&cdns_uart_uart_driver, port); |
81e33b51 | 1355 | if (!(console_suspend_enabled && !may_wake)) { |
4b47d9aa SB |
1356 | unsigned long flags = 0; |
1357 | ||
1358 | spin_lock_irqsave(&port->lock, flags); | |
1359 | /* Empty the receive FIFO 1st before making changes */ | |
a8df6a51 | 1360 | while (!(readl(port->membase + CDNS_UART_SR) & |
d9bb3fb1 | 1361 | CDNS_UART_SR_RXEMPTY)) |
a8df6a51 | 1362 | readl(port->membase + CDNS_UART_FIFO); |
4b47d9aa | 1363 | /* set RX trigger level to 1 */ |
a8df6a51 | 1364 | writel(1, port->membase + CDNS_UART_RXWM); |
4b47d9aa | 1365 | /* disable RX timeout interrups */ |
a8df6a51 | 1366 | writel(CDNS_UART_IXR_TOUT, port->membase + CDNS_UART_IDR); |
4b47d9aa SB |
1367 | spin_unlock_irqrestore(&port->lock, flags); |
1368 | } | |
1369 | ||
1370 | return 0; | |
1371 | } | |
1372 | ||
1373 | /** | |
d9bb3fb1 | 1374 | * cdns_uart_resume - Resume after a previous suspend |
4b47d9aa SB |
1375 | * @device: Pointer to the device structure |
1376 | * | |
489810a1 | 1377 | * Return: 0 |
4b47d9aa | 1378 | */ |
d9bb3fb1 | 1379 | static int cdns_uart_resume(struct device *device) |
4b47d9aa SB |
1380 | { |
1381 | struct uart_port *port = dev_get_drvdata(device); | |
1382 | unsigned long flags = 0; | |
1383 | u32 ctrl_reg; | |
1384 | struct tty_struct *tty; | |
1385 | struct device *tty_dev; | |
1386 | int may_wake = 0; | |
1387 | ||
1388 | /* Get the tty which could be NULL so don't assume it's valid */ | |
1389 | tty = tty_port_tty_get(&port->state->port); | |
1390 | if (tty) { | |
1391 | tty_dev = tty->dev; | |
1392 | may_wake = device_may_wakeup(tty_dev); | |
1393 | tty_kref_put(tty); | |
1394 | } | |
1395 | ||
1396 | if (console_suspend_enabled && !may_wake) { | |
d9bb3fb1 | 1397 | struct cdns_uart *cdns_uart = port->private_data; |
4b47d9aa | 1398 | |
d9bb3fb1 SB |
1399 | clk_enable(cdns_uart->pclk); |
1400 | clk_enable(cdns_uart->uartclk); | |
4b47d9aa SB |
1401 | |
1402 | spin_lock_irqsave(&port->lock, flags); | |
1403 | ||
1404 | /* Set TX/RX Reset */ | |
a8df6a51 | 1405 | ctrl_reg = readl(port->membase + CDNS_UART_CR); |
d9bb3fb1 | 1406 | ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST; |
a8df6a51 SB |
1407 | writel(ctrl_reg, port->membase + CDNS_UART_CR); |
1408 | while (readl(port->membase + CDNS_UART_CR) & | |
d9bb3fb1 | 1409 | (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST)) |
4b47d9aa SB |
1410 | cpu_relax(); |
1411 | ||
1412 | /* restore rx timeout value */ | |
a8df6a51 | 1413 | writel(rx_timeout, port->membase + CDNS_UART_RXTOUT); |
4b47d9aa | 1414 | /* Enable Tx/Rx */ |
a8df6a51 | 1415 | ctrl_reg = readl(port->membase + CDNS_UART_CR); |
d9bb3fb1 SB |
1416 | ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS); |
1417 | ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN; | |
a8df6a51 | 1418 | writel(ctrl_reg, port->membase + CDNS_UART_CR); |
4b47d9aa | 1419 | |
81e33b51 SD |
1420 | clk_disable(cdns_uart->uartclk); |
1421 | clk_disable(cdns_uart->pclk); | |
4b47d9aa SB |
1422 | spin_unlock_irqrestore(&port->lock, flags); |
1423 | } else { | |
1424 | spin_lock_irqsave(&port->lock, flags); | |
1425 | /* restore original rx trigger level */ | |
a8df6a51 | 1426 | writel(rx_trigger_level, port->membase + CDNS_UART_RXWM); |
4b47d9aa | 1427 | /* enable RX timeout interrupt */ |
a8df6a51 | 1428 | writel(CDNS_UART_IXR_TOUT, port->membase + CDNS_UART_IER); |
4b47d9aa SB |
1429 | spin_unlock_irqrestore(&port->lock, flags); |
1430 | } | |
1431 | ||
d9bb3fb1 | 1432 | return uart_resume_port(&cdns_uart_uart_driver, port); |
4b47d9aa SB |
1433 | } |
1434 | #endif /* ! CONFIG_PM_SLEEP */ | |
d62100f1 SD |
1435 | static int __maybe_unused cdns_runtime_suspend(struct device *dev) |
1436 | { | |
1437 | struct platform_device *pdev = to_platform_device(dev); | |
1438 | struct uart_port *port = platform_get_drvdata(pdev); | |
1439 | struct cdns_uart *cdns_uart = port->private_data; | |
4b47d9aa | 1440 | |
d62100f1 SD |
1441 | clk_disable(cdns_uart->uartclk); |
1442 | clk_disable(cdns_uart->pclk); | |
1443 | return 0; | |
1444 | }; | |
1445 | ||
1446 | static int __maybe_unused cdns_runtime_resume(struct device *dev) | |
1447 | { | |
1448 | struct platform_device *pdev = to_platform_device(dev); | |
1449 | struct uart_port *port = platform_get_drvdata(pdev); | |
1450 | struct cdns_uart *cdns_uart = port->private_data; | |
1451 | ||
1452 | clk_enable(cdns_uart->pclk); | |
1453 | clk_enable(cdns_uart->uartclk); | |
1454 | return 0; | |
1455 | }; | |
1456 | ||
1457 | static const struct dev_pm_ops cdns_uart_dev_pm_ops = { | |
1458 | SET_SYSTEM_SLEEP_PM_OPS(cdns_uart_suspend, cdns_uart_resume) | |
1459 | SET_RUNTIME_PM_OPS(cdns_runtime_suspend, | |
1460 | cdns_runtime_resume, NULL) | |
1461 | }; | |
4b47d9aa | 1462 | |
3816b2f8 NM |
1463 | static const struct cdns_platform_data zynqmp_uart_def = { |
1464 | .quirks = CDNS_UART_RXBS_SUPPORT, }; | |
1465 | ||
1466 | /* Match table for of_platform binding */ | |
1467 | static const struct of_device_id cdns_uart_of_match[] = { | |
1468 | { .compatible = "xlnx,xuartps", }, | |
1469 | { .compatible = "cdns,uart-r1p8", }, | |
1470 | { .compatible = "cdns,uart-r1p12", .data = &zynqmp_uart_def }, | |
0267a4ff | 1471 | { .compatible = "xlnx,zynqmp-uart", .data = &zynqmp_uart_def }, |
3816b2f8 NM |
1472 | {} |
1473 | }; | |
1474 | MODULE_DEVICE_TABLE(of, cdns_uart_of_match); | |
1475 | ||
61ec9016 | 1476 | /** |
d9bb3fb1 | 1477 | * cdns_uart_probe - Platform driver probe |
61ec9016 JL |
1478 | * @pdev: Pointer to the platform device structure |
1479 | * | |
e555a211 | 1480 | * Return: 0 on success, negative errno otherwise |
489810a1 | 1481 | */ |
d9bb3fb1 | 1482 | static int cdns_uart_probe(struct platform_device *pdev) |
61ec9016 | 1483 | { |
5c90c07b | 1484 | int rc, id, irq; |
61ec9016 | 1485 | struct uart_port *port; |
5c90c07b | 1486 | struct resource *res; |
d9bb3fb1 | 1487 | struct cdns_uart *cdns_uart_data; |
3816b2f8 | 1488 | const struct of_device_id *match; |
61ec9016 | 1489 | |
d9bb3fb1 | 1490 | cdns_uart_data = devm_kzalloc(&pdev->dev, sizeof(*cdns_uart_data), |
c03cae17 | 1491 | GFP_KERNEL); |
d9bb3fb1 | 1492 | if (!cdns_uart_data) |
30e1e285 SB |
1493 | return -ENOMEM; |
1494 | ||
3816b2f8 NM |
1495 | match = of_match_node(cdns_uart_of_match, pdev->dev.of_node); |
1496 | if (match && match->data) { | |
1497 | const struct cdns_platform_data *data = match->data; | |
1498 | ||
1499 | cdns_uart_data->quirks = data->quirks; | |
1500 | } | |
1501 | ||
d9bb3fb1 SB |
1502 | cdns_uart_data->pclk = devm_clk_get(&pdev->dev, "pclk"); |
1503 | if (IS_ERR(cdns_uart_data->pclk)) { | |
1504 | cdns_uart_data->pclk = devm_clk_get(&pdev->dev, "aper_clk"); | |
1505 | if (!IS_ERR(cdns_uart_data->pclk)) | |
1506 | dev_err(&pdev->dev, "clock name 'aper_clk' is deprecated.\n"); | |
1507 | } | |
1508 | if (IS_ERR(cdns_uart_data->pclk)) { | |
1509 | dev_err(&pdev->dev, "pclk clock not found.\n"); | |
1510 | return PTR_ERR(cdns_uart_data->pclk); | |
1511 | } | |
1512 | ||
1513 | cdns_uart_data->uartclk = devm_clk_get(&pdev->dev, "uart_clk"); | |
1514 | if (IS_ERR(cdns_uart_data->uartclk)) { | |
1515 | cdns_uart_data->uartclk = devm_clk_get(&pdev->dev, "ref_clk"); | |
1516 | if (!IS_ERR(cdns_uart_data->uartclk)) | |
1517 | dev_err(&pdev->dev, "clock name 'ref_clk' is deprecated.\n"); | |
30e1e285 | 1518 | } |
d9bb3fb1 SB |
1519 | if (IS_ERR(cdns_uart_data->uartclk)) { |
1520 | dev_err(&pdev->dev, "uart_clk clock not found.\n"); | |
1521 | return PTR_ERR(cdns_uart_data->uartclk); | |
2326669c JC |
1522 | } |
1523 | ||
ecfc5771 | 1524 | rc = clk_prepare_enable(cdns_uart_data->pclk); |
30e1e285 | 1525 | if (rc) { |
d9bb3fb1 | 1526 | dev_err(&pdev->dev, "Unable to enable pclk clock.\n"); |
c03cae17 | 1527 | return rc; |
30e1e285 | 1528 | } |
ecfc5771 | 1529 | rc = clk_prepare_enable(cdns_uart_data->uartclk); |
2326669c | 1530 | if (rc) { |
30e1e285 | 1531 | dev_err(&pdev->dev, "Unable to enable device clock.\n"); |
d9bb3fb1 | 1532 | goto err_out_clk_dis_pclk; |
61ec9016 JL |
1533 | } |
1534 | ||
1535 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
30e1e285 SB |
1536 | if (!res) { |
1537 | rc = -ENODEV; | |
1538 | goto err_out_clk_disable; | |
1539 | } | |
61ec9016 | 1540 | |
5c90c07b MS |
1541 | irq = platform_get_irq(pdev, 0); |
1542 | if (irq <= 0) { | |
1543 | rc = -ENXIO; | |
30e1e285 SB |
1544 | goto err_out_clk_disable; |
1545 | } | |
61ec9016 | 1546 | |
7ac57347 | 1547 | #ifdef CONFIG_COMMON_CLK |
d9bb3fb1 SB |
1548 | cdns_uart_data->clk_rate_change_nb.notifier_call = |
1549 | cdns_uart_clk_notifier_cb; | |
1550 | if (clk_notifier_register(cdns_uart_data->uartclk, | |
1551 | &cdns_uart_data->clk_rate_change_nb)) | |
c4b0510c | 1552 | dev_warn(&pdev->dev, "Unable to register clock notifier.\n"); |
7ac57347 | 1553 | #endif |
928e9263 MS |
1554 | /* Look for a serialN alias */ |
1555 | id = of_alias_get_id(pdev->dev.of_node, "serial"); | |
1556 | if (id < 0) | |
1557 | id = 0; | |
c4b0510c | 1558 | |
61ec9016 | 1559 | /* Initialize the port structure */ |
d9bb3fb1 | 1560 | port = cdns_uart_get_port(id); |
61ec9016 JL |
1561 | |
1562 | if (!port) { | |
1563 | dev_err(&pdev->dev, "Cannot get uart_port structure\n"); | |
30e1e285 | 1564 | rc = -ENODEV; |
c4b0510c | 1565 | goto err_out_notif_unreg; |
61ec9016 | 1566 | } |
30e1e285 | 1567 | |
354fb1a7 SB |
1568 | /* |
1569 | * Register the port. | |
1570 | * This function also registers this device with the tty layer | |
1571 | * and triggers invocation of the config_port() entry point. | |
1572 | */ | |
1573 | port->mapbase = res->start; | |
1574 | port->irq = irq; | |
1575 | port->dev = &pdev->dev; | |
1576 | port->uartclk = clk_get_rate(cdns_uart_data->uartclk); | |
1577 | port->private_data = cdns_uart_data; | |
1578 | cdns_uart_data->port = port; | |
1579 | platform_set_drvdata(pdev, port); | |
1580 | ||
d62100f1 SD |
1581 | pm_runtime_use_autosuspend(&pdev->dev); |
1582 | pm_runtime_set_autosuspend_delay(&pdev->dev, UART_AUTOSUSPEND_TIMEOUT); | |
d62100f1 | 1583 | pm_runtime_set_active(&pdev->dev); |
ecfc5771 | 1584 | pm_runtime_enable(&pdev->dev); |
d62100f1 | 1585 | |
354fb1a7 SB |
1586 | rc = uart_add_one_port(&cdns_uart_uart_driver, port); |
1587 | if (rc) { | |
1588 | dev_err(&pdev->dev, | |
1589 | "uart_add_one_port() failed; err=%i\n", rc); | |
1590 | goto err_out_notif_unreg; | |
1591 | } | |
1592 | ||
1593 | return 0; | |
1594 | ||
c4b0510c | 1595 | err_out_notif_unreg: |
7ac57347 | 1596 | #ifdef CONFIG_COMMON_CLK |
d9bb3fb1 SB |
1597 | clk_notifier_unregister(cdns_uart_data->uartclk, |
1598 | &cdns_uart_data->clk_rate_change_nb); | |
7ac57347 | 1599 | #endif |
30e1e285 | 1600 | err_out_clk_disable: |
d62100f1 SD |
1601 | pm_runtime_disable(&pdev->dev); |
1602 | pm_runtime_set_suspended(&pdev->dev); | |
1603 | pm_runtime_dont_use_autosuspend(&pdev->dev); | |
ecfc5771 | 1604 | clk_disable_unprepare(cdns_uart_data->uartclk); |
d9bb3fb1 | 1605 | err_out_clk_dis_pclk: |
ecfc5771 | 1606 | clk_disable_unprepare(cdns_uart_data->pclk); |
30e1e285 SB |
1607 | |
1608 | return rc; | |
61ec9016 JL |
1609 | } |
1610 | ||
1611 | /** | |
d9bb3fb1 | 1612 | * cdns_uart_remove - called when the platform driver is unregistered |
61ec9016 JL |
1613 | * @pdev: Pointer to the platform device structure |
1614 | * | |
e555a211 | 1615 | * Return: 0 on success, negative errno otherwise |
489810a1 | 1616 | */ |
d9bb3fb1 | 1617 | static int cdns_uart_remove(struct platform_device *pdev) |
61ec9016 | 1618 | { |
696faedd | 1619 | struct uart_port *port = platform_get_drvdata(pdev); |
d9bb3fb1 | 1620 | struct cdns_uart *cdns_uart_data = port->private_data; |
2326669c | 1621 | int rc; |
61ec9016 | 1622 | |
d9bb3fb1 | 1623 | /* Remove the cdns_uart port from the serial core */ |
7ac57347 | 1624 | #ifdef CONFIG_COMMON_CLK |
d9bb3fb1 SB |
1625 | clk_notifier_unregister(cdns_uart_data->uartclk, |
1626 | &cdns_uart_data->clk_rate_change_nb); | |
7ac57347 | 1627 | #endif |
d9bb3fb1 | 1628 | rc = uart_remove_one_port(&cdns_uart_uart_driver, port); |
2326669c | 1629 | port->mapbase = 0; |
ecfc5771 SD |
1630 | clk_disable_unprepare(cdns_uart_data->uartclk); |
1631 | clk_disable_unprepare(cdns_uart_data->pclk); | |
d62100f1 SD |
1632 | pm_runtime_disable(&pdev->dev); |
1633 | pm_runtime_set_suspended(&pdev->dev); | |
1634 | pm_runtime_dont_use_autosuspend(&pdev->dev); | |
61ec9016 JL |
1635 | return rc; |
1636 | } | |
1637 | ||
d9bb3fb1 SB |
1638 | static struct platform_driver cdns_uart_platform_driver = { |
1639 | .probe = cdns_uart_probe, | |
1640 | .remove = cdns_uart_remove, | |
61ec9016 | 1641 | .driver = { |
d9bb3fb1 SB |
1642 | .name = CDNS_UART_NAME, |
1643 | .of_match_table = cdns_uart_of_match, | |
1644 | .pm = &cdns_uart_dev_pm_ops, | |
61ec9016 JL |
1645 | }, |
1646 | }; | |
1647 | ||
d9bb3fb1 | 1648 | static int __init cdns_uart_init(void) |
61ec9016 JL |
1649 | { |
1650 | int retval = 0; | |
1651 | ||
d9bb3fb1 SB |
1652 | /* Register the cdns_uart driver with the serial core */ |
1653 | retval = uart_register_driver(&cdns_uart_uart_driver); | |
61ec9016 JL |
1654 | if (retval) |
1655 | return retval; | |
1656 | ||
1657 | /* Register the platform driver */ | |
d9bb3fb1 | 1658 | retval = platform_driver_register(&cdns_uart_platform_driver); |
61ec9016 | 1659 | if (retval) |
d9bb3fb1 | 1660 | uart_unregister_driver(&cdns_uart_uart_driver); |
61ec9016 JL |
1661 | |
1662 | return retval; | |
1663 | } | |
1664 | ||
d9bb3fb1 | 1665 | static void __exit cdns_uart_exit(void) |
61ec9016 | 1666 | { |
61ec9016 | 1667 | /* Unregister the platform driver */ |
d9bb3fb1 | 1668 | platform_driver_unregister(&cdns_uart_platform_driver); |
61ec9016 | 1669 | |
d9bb3fb1 SB |
1670 | /* Unregister the cdns_uart driver */ |
1671 | uart_unregister_driver(&cdns_uart_uart_driver); | |
61ec9016 JL |
1672 | } |
1673 | ||
d9bb3fb1 SB |
1674 | module_init(cdns_uart_init); |
1675 | module_exit(cdns_uart_exit); | |
61ec9016 | 1676 | |
d9bb3fb1 | 1677 | MODULE_DESCRIPTION("Driver for Cadence UART"); |
61ec9016 JL |
1678 | MODULE_AUTHOR("Xilinx Inc."); |
1679 | MODULE_LICENSE("GPL"); |