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d7584ed2 TT |
1 | /* |
2 | * Freescale QUICC Engine UART device driver | |
3 | * | |
4 | * Author: Timur Tabi <timur@freescale.com> | |
5 | * | |
6 | * Copyright 2007 Freescale Semiconductor, Inc. This file is licensed under | |
7 | * the terms of the GNU General Public License version 2. This program | |
8 | * is licensed "as is" without any warranty of any kind, whether express | |
9 | * or implied. | |
10 | * | |
11 | * This driver adds support for UART devices via Freescale's QUICC Engine | |
12 | * found on some Freescale SOCs. | |
13 | * | |
14 | * If Soft-UART support is needed but not already present, then this driver | |
15 | * will request and upload the "Soft-UART" microcode upon probe. The | |
16 | * filename of the microcode should be fsl_qe_ucode_uart_X_YZ.bin, where "X" | |
17 | * is the name of the SOC (e.g. 8323), and YZ is the revision of the SOC, | |
18 | * (e.g. "11" for 1.1). | |
19 | */ | |
20 | ||
21 | #include <linux/module.h> | |
22 | #include <linux/serial.h> | |
23 | #include <linux/serial_core.h> | |
ee160a38 JS |
24 | #include <linux/slab.h> |
25 | #include <linux/tty.h> | |
26 | #include <linux/tty_flip.h> | |
d7584ed2 | 27 | #include <linux/io.h> |
5af50730 RH |
28 | #include <linux/of_address.h> |
29 | #include <linux/of_irq.h> | |
d7584ed2 TT |
30 | #include <linux/of_platform.h> |
31 | #include <linux/dma-mapping.h> | |
32 | ||
33 | #include <linux/fs_uart_pd.h> | |
34 | #include <asm/ucc_slow.h> | |
35 | ||
36 | #include <linux/firmware.h> | |
37 | #include <asm/reg.h> | |
38 | ||
39 | /* | |
40 | * The GUMR flag for Soft UART. This would normally be defined in qe.h, | |
41 | * but Soft-UART is a hack and we want to keep everything related to it in | |
42 | * this file. | |
43 | */ | |
44 | #define UCC_SLOW_GUMR_H_SUART 0x00004000 /* Soft-UART */ | |
45 | ||
46 | /* | |
47 | * soft_uart is 1 if we need to use Soft-UART mode | |
48 | */ | |
49 | static int soft_uart; | |
50 | /* | |
51 | * firmware_loaded is 1 if the firmware has been loaded, 0 otherwise. | |
52 | */ | |
53 | static int firmware_loaded; | |
54 | ||
55 | /* Enable this macro to configure all serial ports in internal loopback | |
56 | mode */ | |
57 | /* #define LOOPBACK */ | |
58 | ||
59 | /* The major and minor device numbers are defined in | |
60 | * http://www.lanana.org/docs/device-list/devices-2.6+.txt. For the QE | |
61 | * UART, we have major number 204 and minor numbers 46 - 49, which are the | |
62 | * same as for the CPM2. This decision was made because no Freescale part | |
63 | * has both a CPM and a QE. | |
64 | */ | |
65 | #define SERIAL_QE_MAJOR 204 | |
66 | #define SERIAL_QE_MINOR 46 | |
67 | ||
68 | /* Since we only have minor numbers 46 - 49, there is a hard limit of 4 ports */ | |
69 | #define UCC_MAX_UART 4 | |
70 | ||
71 | /* The number of buffer descriptors for receiving characters. */ | |
72 | #define RX_NUM_FIFO 4 | |
73 | ||
74 | /* The number of buffer descriptors for transmitting characters. */ | |
75 | #define TX_NUM_FIFO 4 | |
76 | ||
77 | /* The maximum size of the character buffer for a single RX BD. */ | |
78 | #define RX_BUF_SIZE 32 | |
79 | ||
80 | /* The maximum size of the character buffer for a single TX BD. */ | |
81 | #define TX_BUF_SIZE 32 | |
82 | ||
83 | /* | |
84 | * The number of jiffies to wait after receiving a close command before the | |
85 | * device is actually closed. This allows the last few characters to be | |
86 | * sent over the wire. | |
87 | */ | |
88 | #define UCC_WAIT_CLOSING 100 | |
89 | ||
90 | struct ucc_uart_pram { | |
91 | struct ucc_slow_pram common; | |
92 | u8 res1[8]; /* reserved */ | |
93 | __be16 maxidl; /* Maximum idle chars */ | |
94 | __be16 idlc; /* temp idle counter */ | |
95 | __be16 brkcr; /* Break count register */ | |
96 | __be16 parec; /* receive parity error counter */ | |
97 | __be16 frmec; /* receive framing error counter */ | |
98 | __be16 nosec; /* receive noise counter */ | |
99 | __be16 brkec; /* receive break condition counter */ | |
100 | __be16 brkln; /* last received break length */ | |
101 | __be16 uaddr[2]; /* UART address character 1 & 2 */ | |
102 | __be16 rtemp; /* Temp storage */ | |
103 | __be16 toseq; /* Transmit out of sequence char */ | |
104 | __be16 cchars[8]; /* control characters 1-8 */ | |
105 | __be16 rccm; /* receive control character mask */ | |
106 | __be16 rccr; /* receive control character register */ | |
107 | __be16 rlbc; /* receive last break character */ | |
108 | __be16 res2; /* reserved */ | |
109 | __be32 res3; /* reserved, should be cleared */ | |
110 | u8 res4; /* reserved, should be cleared */ | |
111 | u8 res5[3]; /* reserved, should be cleared */ | |
112 | __be32 res6; /* reserved, should be cleared */ | |
113 | __be32 res7; /* reserved, should be cleared */ | |
114 | __be32 res8; /* reserved, should be cleared */ | |
115 | __be32 res9; /* reserved, should be cleared */ | |
116 | __be32 res10; /* reserved, should be cleared */ | |
117 | __be32 res11; /* reserved, should be cleared */ | |
118 | __be32 res12; /* reserved, should be cleared */ | |
119 | __be32 res13; /* reserved, should be cleared */ | |
120 | /* The rest is for Soft-UART only */ | |
121 | __be16 supsmr; /* 0x90, Shadow UPSMR */ | |
122 | __be16 res92; /* 0x92, reserved, initialize to 0 */ | |
123 | __be32 rx_state; /* 0x94, RX state, initialize to 0 */ | |
124 | __be32 rx_cnt; /* 0x98, RX count, initialize to 0 */ | |
125 | u8 rx_length; /* 0x9C, Char length, set to 1+CL+PEN+1+SL */ | |
126 | u8 rx_bitmark; /* 0x9D, reserved, initialize to 0 */ | |
127 | u8 rx_temp_dlst_qe; /* 0x9E, reserved, initialize to 0 */ | |
128 | u8 res14[0xBC - 0x9F]; /* reserved */ | |
129 | __be32 dump_ptr; /* 0xBC, Dump pointer */ | |
130 | __be32 rx_frame_rem; /* 0xC0, reserved, initialize to 0 */ | |
131 | u8 rx_frame_rem_size; /* 0xC4, reserved, initialize to 0 */ | |
132 | u8 tx_mode; /* 0xC5, mode, 0=AHDLC, 1=UART */ | |
133 | __be16 tx_state; /* 0xC6, TX state */ | |
134 | u8 res15[0xD0 - 0xC8]; /* reserved */ | |
135 | __be32 resD0; /* 0xD0, reserved, initialize to 0 */ | |
136 | u8 resD4; /* 0xD4, reserved, initialize to 0 */ | |
137 | __be16 resD5; /* 0xD5, reserved, initialize to 0 */ | |
138 | } __attribute__ ((packed)); | |
139 | ||
140 | /* SUPSMR definitions, for Soft-UART only */ | |
141 | #define UCC_UART_SUPSMR_SL 0x8000 | |
142 | #define UCC_UART_SUPSMR_RPM_MASK 0x6000 | |
143 | #define UCC_UART_SUPSMR_RPM_ODD 0x0000 | |
144 | #define UCC_UART_SUPSMR_RPM_LOW 0x2000 | |
145 | #define UCC_UART_SUPSMR_RPM_EVEN 0x4000 | |
146 | #define UCC_UART_SUPSMR_RPM_HIGH 0x6000 | |
147 | #define UCC_UART_SUPSMR_PEN 0x1000 | |
148 | #define UCC_UART_SUPSMR_TPM_MASK 0x0C00 | |
149 | #define UCC_UART_SUPSMR_TPM_ODD 0x0000 | |
150 | #define UCC_UART_SUPSMR_TPM_LOW 0x0400 | |
151 | #define UCC_UART_SUPSMR_TPM_EVEN 0x0800 | |
152 | #define UCC_UART_SUPSMR_TPM_HIGH 0x0C00 | |
153 | #define UCC_UART_SUPSMR_FRZ 0x0100 | |
154 | #define UCC_UART_SUPSMR_UM_MASK 0x00c0 | |
155 | #define UCC_UART_SUPSMR_UM_NORMAL 0x0000 | |
156 | #define UCC_UART_SUPSMR_UM_MAN_MULTI 0x0040 | |
157 | #define UCC_UART_SUPSMR_UM_AUTO_MULTI 0x00c0 | |
158 | #define UCC_UART_SUPSMR_CL_MASK 0x0030 | |
159 | #define UCC_UART_SUPSMR_CL_8 0x0030 | |
160 | #define UCC_UART_SUPSMR_CL_7 0x0020 | |
161 | #define UCC_UART_SUPSMR_CL_6 0x0010 | |
162 | #define UCC_UART_SUPSMR_CL_5 0x0000 | |
163 | ||
164 | #define UCC_UART_TX_STATE_AHDLC 0x00 | |
165 | #define UCC_UART_TX_STATE_UART 0x01 | |
166 | #define UCC_UART_TX_STATE_X1 0x00 | |
167 | #define UCC_UART_TX_STATE_X16 0x80 | |
168 | ||
169 | #define UCC_UART_PRAM_ALIGNMENT 0x100 | |
170 | ||
171 | #define UCC_UART_SIZE_OF_BD UCC_SLOW_SIZE_OF_BD | |
172 | #define NUM_CONTROL_CHARS 8 | |
173 | ||
174 | /* Private per-port data structure */ | |
175 | struct uart_qe_port { | |
176 | struct uart_port port; | |
177 | struct ucc_slow __iomem *uccp; | |
178 | struct ucc_uart_pram __iomem *uccup; | |
179 | struct ucc_slow_info us_info; | |
180 | struct ucc_slow_private *us_private; | |
181 | struct device_node *np; | |
182 | unsigned int ucc_num; /* First ucc is 0, not 1 */ | |
183 | ||
184 | u16 rx_nrfifos; | |
185 | u16 rx_fifosize; | |
186 | u16 tx_nrfifos; | |
187 | u16 tx_fifosize; | |
188 | int wait_closing; | |
189 | u32 flags; | |
190 | struct qe_bd *rx_bd_base; | |
191 | struct qe_bd *rx_cur; | |
192 | struct qe_bd *tx_bd_base; | |
193 | struct qe_bd *tx_cur; | |
194 | unsigned char *tx_buf; | |
195 | unsigned char *rx_buf; | |
196 | void *bd_virt; /* virtual address of the BD buffers */ | |
197 | dma_addr_t bd_dma_addr; /* bus address of the BD buffers */ | |
198 | unsigned int bd_size; /* size of BD buffer space */ | |
199 | }; | |
200 | ||
201 | static struct uart_driver ucc_uart_driver = { | |
202 | .owner = THIS_MODULE, | |
4feead71 | 203 | .driver_name = "ucc_uart", |
d7584ed2 TT |
204 | .dev_name = "ttyQE", |
205 | .major = SERIAL_QE_MAJOR, | |
206 | .minor = SERIAL_QE_MINOR, | |
207 | .nr = UCC_MAX_UART, | |
208 | }; | |
209 | ||
210 | /* | |
211 | * Virtual to physical address translation. | |
212 | * | |
213 | * Given the virtual address for a character buffer, this function returns | |
214 | * the physical (DMA) equivalent. | |
215 | */ | |
216 | static inline dma_addr_t cpu2qe_addr(void *addr, struct uart_qe_port *qe_port) | |
217 | { | |
218 | if (likely((addr >= qe_port->bd_virt)) && | |
219 | (addr < (qe_port->bd_virt + qe_port->bd_size))) | |
220 | return qe_port->bd_dma_addr + (addr - qe_port->bd_virt); | |
221 | ||
222 | /* something nasty happened */ | |
71cc2c21 | 223 | printk(KERN_ERR "%s: addr=%p\n", __func__, addr); |
d7584ed2 TT |
224 | BUG(); |
225 | return 0; | |
226 | } | |
227 | ||
228 | /* | |
229 | * Physical to virtual address translation. | |
230 | * | |
231 | * Given the physical (DMA) address for a character buffer, this function | |
232 | * returns the virtual equivalent. | |
233 | */ | |
234 | static inline void *qe2cpu_addr(dma_addr_t addr, struct uart_qe_port *qe_port) | |
235 | { | |
236 | /* sanity check */ | |
237 | if (likely((addr >= qe_port->bd_dma_addr) && | |
238 | (addr < (qe_port->bd_dma_addr + qe_port->bd_size)))) | |
239 | return qe_port->bd_virt + (addr - qe_port->bd_dma_addr); | |
240 | ||
241 | /* something nasty happened */ | |
181d5762 | 242 | printk(KERN_ERR "%s: addr=%llx\n", __func__, (u64)addr); |
d7584ed2 TT |
243 | BUG(); |
244 | return NULL; | |
245 | } | |
246 | ||
247 | /* | |
248 | * Return 1 if the QE is done transmitting all buffers for this port | |
249 | * | |
250 | * This function scans each BD in sequence. If we find a BD that is not | |
251 | * ready (READY=1), then we return 0 indicating that the QE is still sending | |
252 | * data. If we reach the last BD (WRAP=1), then we know we've scanned | |
253 | * the entire list, and all BDs are done. | |
254 | */ | |
255 | static unsigned int qe_uart_tx_empty(struct uart_port *port) | |
256 | { | |
257 | struct uart_qe_port *qe_port = | |
258 | container_of(port, struct uart_qe_port, port); | |
259 | struct qe_bd *bdp = qe_port->tx_bd_base; | |
260 | ||
261 | while (1) { | |
262 | if (in_be16(&bdp->status) & BD_SC_READY) | |
263 | /* This BD is not done, so return "not done" */ | |
264 | return 0; | |
265 | ||
266 | if (in_be16(&bdp->status) & BD_SC_WRAP) | |
267 | /* | |
268 | * This BD is done and it's the last one, so return | |
269 | * "done" | |
270 | */ | |
271 | return 1; | |
272 | ||
273 | bdp++; | |
fc811472 | 274 | } |
d7584ed2 TT |
275 | } |
276 | ||
277 | /* | |
278 | * Set the modem control lines | |
279 | * | |
280 | * Although the QE can control the modem control lines (e.g. CTS), we | |
281 | * don't need that support. This function must exist, however, otherwise | |
282 | * the kernel will panic. | |
283 | */ | |
284 | void qe_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) | |
285 | { | |
286 | } | |
287 | ||
288 | /* | |
289 | * Get the current modem control line status | |
290 | * | |
291 | * Although the QE can control the modem control lines (e.g. CTS), this | |
292 | * driver currently doesn't support that, so we always return Carrier | |
293 | * Detect, Data Set Ready, and Clear To Send. | |
294 | */ | |
295 | static unsigned int qe_uart_get_mctrl(struct uart_port *port) | |
296 | { | |
297 | return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS; | |
298 | } | |
299 | ||
300 | /* | |
301 | * Disable the transmit interrupt. | |
302 | * | |
303 | * Although this function is called "stop_tx", it does not actually stop | |
304 | * transmission of data. Instead, it tells the QE to not generate an | |
305 | * interrupt when the UCC is finished sending characters. | |
306 | */ | |
307 | static void qe_uart_stop_tx(struct uart_port *port) | |
308 | { | |
309 | struct uart_qe_port *qe_port = | |
310 | container_of(port, struct uart_qe_port, port); | |
311 | ||
312 | clrbits16(&qe_port->uccp->uccm, UCC_UART_UCCE_TX); | |
313 | } | |
314 | ||
315 | /* | |
316 | * Transmit as many characters to the HW as possible. | |
317 | * | |
318 | * This function will attempt to stuff of all the characters from the | |
319 | * kernel's transmit buffer into TX BDs. | |
320 | * | |
af901ca1 | 321 | * A return value of non-zero indicates that it successfully stuffed all |
d7584ed2 TT |
322 | * characters from the kernel buffer. |
323 | * | |
324 | * A return value of zero indicates that there are still characters in the | |
325 | * kernel's buffer that have not been transmitted, but there are no more BDs | |
326 | * available. This function should be called again after a BD has been made | |
327 | * available. | |
328 | */ | |
329 | static int qe_uart_tx_pump(struct uart_qe_port *qe_port) | |
330 | { | |
331 | struct qe_bd *bdp; | |
332 | unsigned char *p; | |
333 | unsigned int count; | |
334 | struct uart_port *port = &qe_port->port; | |
ebd2c8f6 | 335 | struct circ_buf *xmit = &port->state->xmit; |
d7584ed2 TT |
336 | |
337 | bdp = qe_port->rx_cur; | |
338 | ||
339 | /* Handle xon/xoff */ | |
340 | if (port->x_char) { | |
341 | /* Pick next descriptor and fill from buffer */ | |
342 | bdp = qe_port->tx_cur; | |
343 | ||
344 | p = qe2cpu_addr(bdp->buf, qe_port); | |
345 | ||
346 | *p++ = port->x_char; | |
347 | out_be16(&bdp->length, 1); | |
348 | setbits16(&bdp->status, BD_SC_READY); | |
349 | /* Get next BD. */ | |
350 | if (in_be16(&bdp->status) & BD_SC_WRAP) | |
351 | bdp = qe_port->tx_bd_base; | |
352 | else | |
353 | bdp++; | |
354 | qe_port->tx_cur = bdp; | |
355 | ||
356 | port->icount.tx++; | |
357 | port->x_char = 0; | |
358 | return 1; | |
359 | } | |
360 | ||
361 | if (uart_circ_empty(xmit) || uart_tx_stopped(port)) { | |
362 | qe_uart_stop_tx(port); | |
363 | return 0; | |
364 | } | |
365 | ||
366 | /* Pick next descriptor and fill from buffer */ | |
367 | bdp = qe_port->tx_cur; | |
368 | ||
369 | while (!(in_be16(&bdp->status) & BD_SC_READY) && | |
370 | (xmit->tail != xmit->head)) { | |
371 | count = 0; | |
372 | p = qe2cpu_addr(bdp->buf, qe_port); | |
373 | while (count < qe_port->tx_fifosize) { | |
374 | *p++ = xmit->buf[xmit->tail]; | |
375 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); | |
376 | port->icount.tx++; | |
377 | count++; | |
378 | if (xmit->head == xmit->tail) | |
379 | break; | |
380 | } | |
381 | ||
382 | out_be16(&bdp->length, count); | |
383 | setbits16(&bdp->status, BD_SC_READY); | |
384 | ||
385 | /* Get next BD. */ | |
386 | if (in_be16(&bdp->status) & BD_SC_WRAP) | |
387 | bdp = qe_port->tx_bd_base; | |
388 | else | |
389 | bdp++; | |
390 | } | |
391 | qe_port->tx_cur = bdp; | |
392 | ||
393 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
394 | uart_write_wakeup(port); | |
395 | ||
396 | if (uart_circ_empty(xmit)) { | |
397 | /* The kernel buffer is empty, so turn off TX interrupts. We | |
398 | don't need to be told when the QE is finished transmitting | |
399 | the data. */ | |
400 | qe_uart_stop_tx(port); | |
401 | return 0; | |
402 | } | |
403 | ||
404 | return 1; | |
405 | } | |
406 | ||
407 | /* | |
408 | * Start transmitting data | |
409 | * | |
410 | * This function will start transmitting any available data, if the port | |
411 | * isn't already transmitting data. | |
412 | */ | |
413 | static void qe_uart_start_tx(struct uart_port *port) | |
414 | { | |
415 | struct uart_qe_port *qe_port = | |
416 | container_of(port, struct uart_qe_port, port); | |
417 | ||
418 | /* If we currently are transmitting, then just return */ | |
419 | if (in_be16(&qe_port->uccp->uccm) & UCC_UART_UCCE_TX) | |
420 | return; | |
421 | ||
422 | /* Otherwise, pump the port and start transmission */ | |
423 | if (qe_uart_tx_pump(qe_port)) | |
424 | setbits16(&qe_port->uccp->uccm, UCC_UART_UCCE_TX); | |
425 | } | |
426 | ||
427 | /* | |
428 | * Stop transmitting data | |
429 | */ | |
430 | static void qe_uart_stop_rx(struct uart_port *port) | |
431 | { | |
432 | struct uart_qe_port *qe_port = | |
433 | container_of(port, struct uart_qe_port, port); | |
434 | ||
435 | clrbits16(&qe_port->uccp->uccm, UCC_UART_UCCE_RX); | |
436 | } | |
437 | ||
d7584ed2 TT |
438 | /* Start or stop sending break signal |
439 | * | |
440 | * This function controls the sending of a break signal. If break_state=1, | |
441 | * then we start sending a break signal. If break_state=0, then we stop | |
442 | * sending the break signal. | |
443 | */ | |
444 | static void qe_uart_break_ctl(struct uart_port *port, int break_state) | |
445 | { | |
446 | struct uart_qe_port *qe_port = | |
447 | container_of(port, struct uart_qe_port, port); | |
448 | ||
449 | if (break_state) | |
450 | ucc_slow_stop_tx(qe_port->us_private); | |
451 | else | |
452 | ucc_slow_restart_tx(qe_port->us_private); | |
453 | } | |
454 | ||
455 | /* ISR helper function for receiving character. | |
456 | * | |
457 | * This function is called by the ISR to handling receiving characters | |
458 | */ | |
459 | static void qe_uart_int_rx(struct uart_qe_port *qe_port) | |
460 | { | |
461 | int i; | |
462 | unsigned char ch, *cp; | |
463 | struct uart_port *port = &qe_port->port; | |
227434f8 | 464 | struct tty_port *tport = &port->state->port; |
d7584ed2 TT |
465 | struct qe_bd *bdp; |
466 | u16 status; | |
467 | unsigned int flg; | |
468 | ||
469 | /* Just loop through the closed BDs and copy the characters into | |
470 | * the buffer. | |
471 | */ | |
472 | bdp = qe_port->rx_cur; | |
473 | while (1) { | |
474 | status = in_be16(&bdp->status); | |
475 | ||
476 | /* If this one is empty, then we assume we've read them all */ | |
477 | if (status & BD_SC_EMPTY) | |
478 | break; | |
479 | ||
480 | /* get number of characters, and check space in RX buffer */ | |
481 | i = in_be16(&bdp->length); | |
482 | ||
483 | /* If we don't have enough room in RX buffer for the entire BD, | |
484 | * then we try later, which will be the next RX interrupt. | |
485 | */ | |
227434f8 | 486 | if (tty_buffer_request_room(tport, i) < i) { |
d7584ed2 TT |
487 | dev_dbg(port->dev, "ucc-uart: no room in RX buffer\n"); |
488 | return; | |
489 | } | |
490 | ||
491 | /* get pointer */ | |
492 | cp = qe2cpu_addr(bdp->buf, qe_port); | |
493 | ||
494 | /* loop through the buffer */ | |
495 | while (i-- > 0) { | |
496 | ch = *cp++; | |
497 | port->icount.rx++; | |
498 | flg = TTY_NORMAL; | |
499 | ||
500 | if (!i && status & | |
501 | (BD_SC_BR | BD_SC_FR | BD_SC_PR | BD_SC_OV)) | |
502 | goto handle_error; | |
503 | if (uart_handle_sysrq_char(port, ch)) | |
504 | continue; | |
505 | ||
506 | error_return: | |
92a19f9c | 507 | tty_insert_flip_char(tport, ch, flg); |
d7584ed2 TT |
508 | |
509 | } | |
510 | ||
511 | /* This BD is ready to be used again. Clear status. get next */ | |
512 | clrsetbits_be16(&bdp->status, BD_SC_BR | BD_SC_FR | BD_SC_PR | | |
513 | BD_SC_OV | BD_SC_ID, BD_SC_EMPTY); | |
514 | if (in_be16(&bdp->status) & BD_SC_WRAP) | |
515 | bdp = qe_port->rx_bd_base; | |
516 | else | |
517 | bdp++; | |
518 | ||
519 | } | |
520 | ||
521 | /* Write back buffer pointer */ | |
522 | qe_port->rx_cur = bdp; | |
523 | ||
524 | /* Activate BH processing */ | |
2e124b4a | 525 | tty_flip_buffer_push(tport); |
d7584ed2 TT |
526 | |
527 | return; | |
528 | ||
529 | /* Error processing */ | |
530 | ||
531 | handle_error: | |
532 | /* Statistics */ | |
533 | if (status & BD_SC_BR) | |
534 | port->icount.brk++; | |
535 | if (status & BD_SC_PR) | |
536 | port->icount.parity++; | |
537 | if (status & BD_SC_FR) | |
538 | port->icount.frame++; | |
539 | if (status & BD_SC_OV) | |
540 | port->icount.overrun++; | |
541 | ||
542 | /* Mask out ignored conditions */ | |
543 | status &= port->read_status_mask; | |
544 | ||
545 | /* Handle the remaining ones */ | |
546 | if (status & BD_SC_BR) | |
547 | flg = TTY_BREAK; | |
548 | else if (status & BD_SC_PR) | |
549 | flg = TTY_PARITY; | |
550 | else if (status & BD_SC_FR) | |
551 | flg = TTY_FRAME; | |
552 | ||
553 | /* Overrun does not affect the current character ! */ | |
554 | if (status & BD_SC_OV) | |
92a19f9c | 555 | tty_insert_flip_char(tport, 0, TTY_OVERRUN); |
d7584ed2 TT |
556 | #ifdef SUPPORT_SYSRQ |
557 | port->sysrq = 0; | |
558 | #endif | |
559 | goto error_return; | |
560 | } | |
561 | ||
562 | /* Interrupt handler | |
563 | * | |
564 | * This interrupt handler is called after a BD is processed. | |
565 | */ | |
566 | static irqreturn_t qe_uart_int(int irq, void *data) | |
567 | { | |
568 | struct uart_qe_port *qe_port = (struct uart_qe_port *) data; | |
569 | struct ucc_slow __iomem *uccp = qe_port->uccp; | |
570 | u16 events; | |
571 | ||
572 | /* Clear the interrupts */ | |
573 | events = in_be16(&uccp->ucce); | |
574 | out_be16(&uccp->ucce, events); | |
575 | ||
576 | if (events & UCC_UART_UCCE_BRKE) | |
577 | uart_handle_break(&qe_port->port); | |
578 | ||
579 | if (events & UCC_UART_UCCE_RX) | |
580 | qe_uart_int_rx(qe_port); | |
581 | ||
582 | if (events & UCC_UART_UCCE_TX) | |
583 | qe_uart_tx_pump(qe_port); | |
584 | ||
585 | return events ? IRQ_HANDLED : IRQ_NONE; | |
586 | } | |
587 | ||
588 | /* Initialize buffer descriptors | |
589 | * | |
590 | * This function initializes all of the RX and TX buffer descriptors. | |
591 | */ | |
592 | static void qe_uart_initbd(struct uart_qe_port *qe_port) | |
593 | { | |
594 | int i; | |
595 | void *bd_virt; | |
596 | struct qe_bd *bdp; | |
597 | ||
598 | /* Set the physical address of the host memory buffers in the buffer | |
599 | * descriptors, and the virtual address for us to work with. | |
600 | */ | |
601 | bd_virt = qe_port->bd_virt; | |
602 | bdp = qe_port->rx_bd_base; | |
603 | qe_port->rx_cur = qe_port->rx_bd_base; | |
604 | for (i = 0; i < (qe_port->rx_nrfifos - 1); i++) { | |
605 | out_be16(&bdp->status, BD_SC_EMPTY | BD_SC_INTRPT); | |
606 | out_be32(&bdp->buf, cpu2qe_addr(bd_virt, qe_port)); | |
607 | out_be16(&bdp->length, 0); | |
608 | bd_virt += qe_port->rx_fifosize; | |
609 | bdp++; | |
610 | } | |
611 | ||
612 | /* */ | |
613 | out_be16(&bdp->status, BD_SC_WRAP | BD_SC_EMPTY | BD_SC_INTRPT); | |
614 | out_be32(&bdp->buf, cpu2qe_addr(bd_virt, qe_port)); | |
615 | out_be16(&bdp->length, 0); | |
616 | ||
617 | /* Set the physical address of the host memory | |
618 | * buffers in the buffer descriptors, and the | |
619 | * virtual address for us to work with. | |
620 | */ | |
621 | bd_virt = qe_port->bd_virt + | |
622 | L1_CACHE_ALIGN(qe_port->rx_nrfifos * qe_port->rx_fifosize); | |
623 | qe_port->tx_cur = qe_port->tx_bd_base; | |
624 | bdp = qe_port->tx_bd_base; | |
625 | for (i = 0; i < (qe_port->tx_nrfifos - 1); i++) { | |
626 | out_be16(&bdp->status, BD_SC_INTRPT); | |
627 | out_be32(&bdp->buf, cpu2qe_addr(bd_virt, qe_port)); | |
628 | out_be16(&bdp->length, 0); | |
629 | bd_virt += qe_port->tx_fifosize; | |
630 | bdp++; | |
631 | } | |
632 | ||
633 | /* Loopback requires the preamble bit to be set on the first TX BD */ | |
634 | #ifdef LOOPBACK | |
635 | setbits16(&qe_port->tx_cur->status, BD_SC_P); | |
636 | #endif | |
637 | ||
638 | out_be16(&bdp->status, BD_SC_WRAP | BD_SC_INTRPT); | |
639 | out_be32(&bdp->buf, cpu2qe_addr(bd_virt, qe_port)); | |
640 | out_be16(&bdp->length, 0); | |
641 | } | |
642 | ||
643 | /* | |
644 | * Initialize a UCC for UART. | |
645 | * | |
646 | * This function configures a given UCC to be used as a UART device. Basic | |
647 | * UCC initialization is handled in qe_uart_request_port(). This function | |
648 | * does all the UART-specific stuff. | |
649 | */ | |
650 | static void qe_uart_init_ucc(struct uart_qe_port *qe_port) | |
651 | { | |
652 | u32 cecr_subblock; | |
653 | struct ucc_slow __iomem *uccp = qe_port->uccp; | |
654 | struct ucc_uart_pram *uccup = qe_port->uccup; | |
655 | ||
656 | unsigned int i; | |
657 | ||
658 | /* First, disable TX and RX in the UCC */ | |
659 | ucc_slow_disable(qe_port->us_private, COMM_DIR_RX_AND_TX); | |
660 | ||
661 | /* Program the UCC UART parameter RAM */ | |
662 | out_8(&uccup->common.rbmr, UCC_BMR_GBL | UCC_BMR_BO_BE); | |
663 | out_8(&uccup->common.tbmr, UCC_BMR_GBL | UCC_BMR_BO_BE); | |
664 | out_be16(&uccup->common.mrblr, qe_port->rx_fifosize); | |
665 | out_be16(&uccup->maxidl, 0x10); | |
666 | out_be16(&uccup->brkcr, 1); | |
667 | out_be16(&uccup->parec, 0); | |
668 | out_be16(&uccup->frmec, 0); | |
669 | out_be16(&uccup->nosec, 0); | |
670 | out_be16(&uccup->brkec, 0); | |
671 | out_be16(&uccup->uaddr[0], 0); | |
672 | out_be16(&uccup->uaddr[1], 0); | |
673 | out_be16(&uccup->toseq, 0); | |
674 | for (i = 0; i < 8; i++) | |
675 | out_be16(&uccup->cchars[i], 0xC000); | |
676 | out_be16(&uccup->rccm, 0xc0ff); | |
677 | ||
678 | /* Configure the GUMR registers for UART */ | |
b45cc9ef | 679 | if (soft_uart) { |
d7584ed2 TT |
680 | /* Soft-UART requires a 1X multiplier for TX */ |
681 | clrsetbits_be32(&uccp->gumr_l, | |
682 | UCC_SLOW_GUMR_L_MODE_MASK | UCC_SLOW_GUMR_L_TDCR_MASK | | |
683 | UCC_SLOW_GUMR_L_RDCR_MASK, | |
684 | UCC_SLOW_GUMR_L_MODE_UART | UCC_SLOW_GUMR_L_TDCR_1 | | |
685 | UCC_SLOW_GUMR_L_RDCR_16); | |
b45cc9ef DL |
686 | |
687 | clrsetbits_be32(&uccp->gumr_h, UCC_SLOW_GUMR_H_RFW, | |
688 | UCC_SLOW_GUMR_H_TRX | UCC_SLOW_GUMR_H_TTX); | |
689 | } else { | |
d7584ed2 TT |
690 | clrsetbits_be32(&uccp->gumr_l, |
691 | UCC_SLOW_GUMR_L_MODE_MASK | UCC_SLOW_GUMR_L_TDCR_MASK | | |
692 | UCC_SLOW_GUMR_L_RDCR_MASK, | |
693 | UCC_SLOW_GUMR_L_MODE_UART | UCC_SLOW_GUMR_L_TDCR_16 | | |
694 | UCC_SLOW_GUMR_L_RDCR_16); | |
695 | ||
b45cc9ef DL |
696 | clrsetbits_be32(&uccp->gumr_h, |
697 | UCC_SLOW_GUMR_H_TRX | UCC_SLOW_GUMR_H_TTX, | |
698 | UCC_SLOW_GUMR_H_RFW); | |
699 | } | |
d7584ed2 TT |
700 | |
701 | #ifdef LOOPBACK | |
702 | clrsetbits_be32(&uccp->gumr_l, UCC_SLOW_GUMR_L_DIAG_MASK, | |
703 | UCC_SLOW_GUMR_L_DIAG_LOOP); | |
704 | clrsetbits_be32(&uccp->gumr_h, | |
705 | UCC_SLOW_GUMR_H_CTSP | UCC_SLOW_GUMR_H_RSYN, | |
706 | UCC_SLOW_GUMR_H_CDS); | |
707 | #endif | |
708 | ||
b45cc9ef | 709 | /* Disable rx interrupts and clear all pending events. */ |
d7584ed2 TT |
710 | out_be16(&uccp->uccm, 0); |
711 | out_be16(&uccp->ucce, 0xffff); | |
712 | out_be16(&uccp->udsr, 0x7e7e); | |
713 | ||
714 | /* Initialize UPSMR */ | |
715 | out_be16(&uccp->upsmr, 0); | |
716 | ||
717 | if (soft_uart) { | |
718 | out_be16(&uccup->supsmr, 0x30); | |
719 | out_be16(&uccup->res92, 0); | |
720 | out_be32(&uccup->rx_state, 0); | |
721 | out_be32(&uccup->rx_cnt, 0); | |
722 | out_8(&uccup->rx_bitmark, 0); | |
723 | out_8(&uccup->rx_length, 10); | |
724 | out_be32(&uccup->dump_ptr, 0x4000); | |
725 | out_8(&uccup->rx_temp_dlst_qe, 0); | |
726 | out_be32(&uccup->rx_frame_rem, 0); | |
727 | out_8(&uccup->rx_frame_rem_size, 0); | |
728 | /* Soft-UART requires TX to be 1X */ | |
729 | out_8(&uccup->tx_mode, | |
730 | UCC_UART_TX_STATE_UART | UCC_UART_TX_STATE_X1); | |
731 | out_be16(&uccup->tx_state, 0); | |
732 | out_8(&uccup->resD4, 0); | |
733 | out_be16(&uccup->resD5, 0); | |
734 | ||
735 | /* Set UART mode. | |
736 | * Enable receive and transmit. | |
737 | */ | |
738 | ||
739 | /* From the microcode errata: | |
740 | * 1.GUMR_L register, set mode=0010 (QMC). | |
741 | * 2.Set GUMR_H[17] bit. (UART/AHDLC mode). | |
742 | * 3.Set GUMR_H[19:20] (Transparent mode) | |
743 | * 4.Clear GUMR_H[26] (RFW) | |
744 | * ... | |
745 | * 6.Receiver must use 16x over sampling | |
746 | */ | |
747 | clrsetbits_be32(&uccp->gumr_l, | |
748 | UCC_SLOW_GUMR_L_MODE_MASK | UCC_SLOW_GUMR_L_TDCR_MASK | | |
749 | UCC_SLOW_GUMR_L_RDCR_MASK, | |
750 | UCC_SLOW_GUMR_L_MODE_QMC | UCC_SLOW_GUMR_L_TDCR_16 | | |
751 | UCC_SLOW_GUMR_L_RDCR_16); | |
752 | ||
753 | clrsetbits_be32(&uccp->gumr_h, | |
754 | UCC_SLOW_GUMR_H_RFW | UCC_SLOW_GUMR_H_RSYN, | |
755 | UCC_SLOW_GUMR_H_SUART | UCC_SLOW_GUMR_H_TRX | | |
756 | UCC_SLOW_GUMR_H_TTX | UCC_SLOW_GUMR_H_TFL); | |
757 | ||
758 | #ifdef LOOPBACK | |
759 | clrsetbits_be32(&uccp->gumr_l, UCC_SLOW_GUMR_L_DIAG_MASK, | |
760 | UCC_SLOW_GUMR_L_DIAG_LOOP); | |
761 | clrbits32(&uccp->gumr_h, UCC_SLOW_GUMR_H_CTSP | | |
762 | UCC_SLOW_GUMR_H_CDS); | |
763 | #endif | |
764 | ||
765 | cecr_subblock = ucc_slow_get_qe_cr_subblock(qe_port->ucc_num); | |
766 | qe_issue_cmd(QE_INIT_TX_RX, cecr_subblock, | |
767 | QE_CR_PROTOCOL_UNSPECIFIED, 0); | |
b45cc9ef DL |
768 | } else { |
769 | cecr_subblock = ucc_slow_get_qe_cr_subblock(qe_port->ucc_num); | |
770 | qe_issue_cmd(QE_INIT_TX_RX, cecr_subblock, | |
771 | QE_CR_PROTOCOL_UART, 0); | |
d7584ed2 TT |
772 | } |
773 | } | |
774 | ||
775 | /* | |
776 | * Initialize the port. | |
777 | */ | |
778 | static int qe_uart_startup(struct uart_port *port) | |
779 | { | |
780 | struct uart_qe_port *qe_port = | |
781 | container_of(port, struct uart_qe_port, port); | |
782 | int ret; | |
783 | ||
784 | /* | |
785 | * If we're using Soft-UART mode, then we need to make sure the | |
786 | * firmware has been uploaded first. | |
787 | */ | |
788 | if (soft_uart && !firmware_loaded) { | |
789 | dev_err(port->dev, "Soft-UART firmware not uploaded\n"); | |
790 | return -ENODEV; | |
791 | } | |
792 | ||
793 | qe_uart_initbd(qe_port); | |
794 | qe_uart_init_ucc(qe_port); | |
795 | ||
796 | /* Install interrupt handler. */ | |
797 | ret = request_irq(port->irq, qe_uart_int, IRQF_SHARED, "ucc-uart", | |
798 | qe_port); | |
799 | if (ret) { | |
800 | dev_err(port->dev, "could not claim IRQ %u\n", port->irq); | |
801 | return ret; | |
802 | } | |
803 | ||
804 | /* Startup rx-int */ | |
805 | setbits16(&qe_port->uccp->uccm, UCC_UART_UCCE_RX); | |
806 | ucc_slow_enable(qe_port->us_private, COMM_DIR_RX_AND_TX); | |
807 | ||
808 | return 0; | |
809 | } | |
810 | ||
811 | /* | |
812 | * Shutdown the port. | |
813 | */ | |
814 | static void qe_uart_shutdown(struct uart_port *port) | |
815 | { | |
816 | struct uart_qe_port *qe_port = | |
817 | container_of(port, struct uart_qe_port, port); | |
818 | struct ucc_slow __iomem *uccp = qe_port->uccp; | |
819 | unsigned int timeout = 20; | |
820 | ||
821 | /* Disable RX and TX */ | |
822 | ||
823 | /* Wait for all the BDs marked sent */ | |
824 | while (!qe_uart_tx_empty(port)) { | |
825 | if (!--timeout) { | |
826 | dev_warn(port->dev, "shutdown timeout\n"); | |
827 | break; | |
828 | } | |
829 | set_current_state(TASK_UNINTERRUPTIBLE); | |
830 | schedule_timeout(2); | |
831 | } | |
832 | ||
833 | if (qe_port->wait_closing) { | |
834 | /* Wait a bit longer */ | |
835 | set_current_state(TASK_UNINTERRUPTIBLE); | |
836 | schedule_timeout(qe_port->wait_closing); | |
837 | } | |
838 | ||
839 | /* Stop uarts */ | |
840 | ucc_slow_disable(qe_port->us_private, COMM_DIR_RX_AND_TX); | |
841 | clrbits16(&uccp->uccm, UCC_UART_UCCE_TX | UCC_UART_UCCE_RX); | |
842 | ||
843 | /* Shut them really down and reinit buffer descriptors */ | |
844 | ucc_slow_graceful_stop_tx(qe_port->us_private); | |
845 | qe_uart_initbd(qe_port); | |
846 | ||
847 | free_irq(port->irq, qe_port); | |
848 | } | |
849 | ||
850 | /* | |
851 | * Set the serial port parameters. | |
852 | */ | |
853 | static void qe_uart_set_termios(struct uart_port *port, | |
854 | struct ktermios *termios, struct ktermios *old) | |
855 | { | |
856 | struct uart_qe_port *qe_port = | |
857 | container_of(port, struct uart_qe_port, port); | |
858 | struct ucc_slow __iomem *uccp = qe_port->uccp; | |
859 | unsigned int baud; | |
860 | unsigned long flags; | |
861 | u16 upsmr = in_be16(&uccp->upsmr); | |
862 | struct ucc_uart_pram __iomem *uccup = qe_port->uccup; | |
863 | u16 supsmr = in_be16(&uccup->supsmr); | |
864 | u8 char_length = 2; /* 1 + CL + PEN + 1 + SL */ | |
865 | ||
866 | /* Character length programmed into the mode register is the | |
867 | * sum of: 1 start bit, number of data bits, 0 or 1 parity bit, | |
868 | * 1 or 2 stop bits, minus 1. | |
869 | * The value 'bits' counts this for us. | |
870 | */ | |
871 | ||
872 | /* byte size */ | |
873 | upsmr &= UCC_UART_UPSMR_CL_MASK; | |
874 | supsmr &= UCC_UART_SUPSMR_CL_MASK; | |
875 | ||
876 | switch (termios->c_cflag & CSIZE) { | |
877 | case CS5: | |
878 | upsmr |= UCC_UART_UPSMR_CL_5; | |
879 | supsmr |= UCC_UART_SUPSMR_CL_5; | |
880 | char_length += 5; | |
881 | break; | |
882 | case CS6: | |
883 | upsmr |= UCC_UART_UPSMR_CL_6; | |
884 | supsmr |= UCC_UART_SUPSMR_CL_6; | |
885 | char_length += 6; | |
886 | break; | |
887 | case CS7: | |
888 | upsmr |= UCC_UART_UPSMR_CL_7; | |
889 | supsmr |= UCC_UART_SUPSMR_CL_7; | |
890 | char_length += 7; | |
891 | break; | |
892 | default: /* case CS8 */ | |
893 | upsmr |= UCC_UART_UPSMR_CL_8; | |
894 | supsmr |= UCC_UART_SUPSMR_CL_8; | |
895 | char_length += 8; | |
896 | break; | |
897 | } | |
898 | ||
899 | /* If CSTOPB is set, we want two stop bits */ | |
900 | if (termios->c_cflag & CSTOPB) { | |
901 | upsmr |= UCC_UART_UPSMR_SL; | |
902 | supsmr |= UCC_UART_SUPSMR_SL; | |
903 | char_length++; /* + SL */ | |
904 | } | |
905 | ||
906 | if (termios->c_cflag & PARENB) { | |
907 | upsmr |= UCC_UART_UPSMR_PEN; | |
908 | supsmr |= UCC_UART_SUPSMR_PEN; | |
909 | char_length++; /* + PEN */ | |
910 | ||
911 | if (!(termios->c_cflag & PARODD)) { | |
912 | upsmr &= ~(UCC_UART_UPSMR_RPM_MASK | | |
913 | UCC_UART_UPSMR_TPM_MASK); | |
914 | upsmr |= UCC_UART_UPSMR_RPM_EVEN | | |
915 | UCC_UART_UPSMR_TPM_EVEN; | |
916 | supsmr &= ~(UCC_UART_SUPSMR_RPM_MASK | | |
917 | UCC_UART_SUPSMR_TPM_MASK); | |
918 | supsmr |= UCC_UART_SUPSMR_RPM_EVEN | | |
919 | UCC_UART_SUPSMR_TPM_EVEN; | |
920 | } | |
921 | } | |
922 | ||
923 | /* | |
924 | * Set up parity check flag | |
925 | */ | |
926 | port->read_status_mask = BD_SC_EMPTY | BD_SC_OV; | |
927 | if (termios->c_iflag & INPCK) | |
928 | port->read_status_mask |= BD_SC_FR | BD_SC_PR; | |
ef8b9ddc | 929 | if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) |
d7584ed2 TT |
930 | port->read_status_mask |= BD_SC_BR; |
931 | ||
932 | /* | |
933 | * Characters to ignore | |
934 | */ | |
935 | port->ignore_status_mask = 0; | |
936 | if (termios->c_iflag & IGNPAR) | |
937 | port->ignore_status_mask |= BD_SC_PR | BD_SC_FR; | |
938 | if (termios->c_iflag & IGNBRK) { | |
939 | port->ignore_status_mask |= BD_SC_BR; | |
940 | /* | |
941 | * If we're ignore parity and break indicators, ignore | |
942 | * overruns too. (For real raw support). | |
943 | */ | |
944 | if (termios->c_iflag & IGNPAR) | |
945 | port->ignore_status_mask |= BD_SC_OV; | |
946 | } | |
947 | /* | |
948 | * !!! ignore all characters if CREAD is not set | |
949 | */ | |
950 | if ((termios->c_cflag & CREAD) == 0) | |
951 | port->read_status_mask &= ~BD_SC_EMPTY; | |
952 | ||
953 | baud = uart_get_baud_rate(port, termios, old, 0, 115200); | |
954 | ||
955 | /* Do we really need a spinlock here? */ | |
956 | spin_lock_irqsave(&port->lock, flags); | |
957 | ||
8e18862d CM |
958 | /* Update the per-port timeout. */ |
959 | uart_update_timeout(port, termios->c_cflag, baud); | |
960 | ||
d7584ed2 TT |
961 | out_be16(&uccp->upsmr, upsmr); |
962 | if (soft_uart) { | |
963 | out_be16(&uccup->supsmr, supsmr); | |
964 | out_8(&uccup->rx_length, char_length); | |
965 | ||
966 | /* Soft-UART requires a 1X multiplier for TX */ | |
967 | qe_setbrg(qe_port->us_info.rx_clock, baud, 16); | |
968 | qe_setbrg(qe_port->us_info.tx_clock, baud, 1); | |
969 | } else { | |
970 | qe_setbrg(qe_port->us_info.rx_clock, baud, 16); | |
971 | qe_setbrg(qe_port->us_info.tx_clock, baud, 16); | |
972 | } | |
973 | ||
974 | spin_unlock_irqrestore(&port->lock, flags); | |
975 | } | |
976 | ||
977 | /* | |
978 | * Return a pointer to a string that describes what kind of port this is. | |
979 | */ | |
980 | static const char *qe_uart_type(struct uart_port *port) | |
981 | { | |
982 | return "QE"; | |
983 | } | |
984 | ||
985 | /* | |
986 | * Allocate any memory and I/O resources required by the port. | |
987 | */ | |
988 | static int qe_uart_request_port(struct uart_port *port) | |
989 | { | |
990 | int ret; | |
991 | struct uart_qe_port *qe_port = | |
992 | container_of(port, struct uart_qe_port, port); | |
993 | struct ucc_slow_info *us_info = &qe_port->us_info; | |
994 | struct ucc_slow_private *uccs; | |
995 | unsigned int rx_size, tx_size; | |
996 | void *bd_virt; | |
997 | dma_addr_t bd_dma_addr = 0; | |
998 | ||
999 | ret = ucc_slow_init(us_info, &uccs); | |
1000 | if (ret) { | |
1001 | dev_err(port->dev, "could not initialize UCC%u\n", | |
1002 | qe_port->ucc_num); | |
1003 | return ret; | |
1004 | } | |
1005 | ||
1006 | qe_port->us_private = uccs; | |
1007 | qe_port->uccp = uccs->us_regs; | |
1008 | qe_port->uccup = (struct ucc_uart_pram *) uccs->us_pram; | |
1009 | qe_port->rx_bd_base = uccs->rx_bd; | |
1010 | qe_port->tx_bd_base = uccs->tx_bd; | |
1011 | ||
1012 | /* | |
1013 | * Allocate the transmit and receive data buffers. | |
1014 | */ | |
1015 | ||
1016 | rx_size = L1_CACHE_ALIGN(qe_port->rx_nrfifos * qe_port->rx_fifosize); | |
1017 | tx_size = L1_CACHE_ALIGN(qe_port->tx_nrfifos * qe_port->tx_fifosize); | |
1018 | ||
8b05cefc | 1019 | bd_virt = dma_alloc_coherent(port->dev, rx_size + tx_size, &bd_dma_addr, |
d7584ed2 TT |
1020 | GFP_KERNEL); |
1021 | if (!bd_virt) { | |
1022 | dev_err(port->dev, "could not allocate buffer descriptors\n"); | |
1023 | return -ENOMEM; | |
1024 | } | |
1025 | ||
1026 | qe_port->bd_virt = bd_virt; | |
1027 | qe_port->bd_dma_addr = bd_dma_addr; | |
1028 | qe_port->bd_size = rx_size + tx_size; | |
1029 | ||
1030 | qe_port->rx_buf = bd_virt; | |
1031 | qe_port->tx_buf = qe_port->rx_buf + rx_size; | |
1032 | ||
1033 | return 0; | |
1034 | } | |
1035 | ||
1036 | /* | |
1037 | * Configure the port. | |
1038 | * | |
1039 | * We say we're a CPM-type port because that's mostly true. Once the device | |
1040 | * is configured, this driver operates almost identically to the CPM serial | |
1041 | * driver. | |
1042 | */ | |
1043 | static void qe_uart_config_port(struct uart_port *port, int flags) | |
1044 | { | |
1045 | if (flags & UART_CONFIG_TYPE) { | |
1046 | port->type = PORT_CPM; | |
1047 | qe_uart_request_port(port); | |
1048 | } | |
1049 | } | |
1050 | ||
1051 | /* | |
1052 | * Release any memory and I/O resources that were allocated in | |
1053 | * qe_uart_request_port(). | |
1054 | */ | |
1055 | static void qe_uart_release_port(struct uart_port *port) | |
1056 | { | |
1057 | struct uart_qe_port *qe_port = | |
1058 | container_of(port, struct uart_qe_port, port); | |
1059 | struct ucc_slow_private *uccs = qe_port->us_private; | |
1060 | ||
8b05cefc | 1061 | dma_free_coherent(port->dev, qe_port->bd_size, qe_port->bd_virt, |
d7584ed2 TT |
1062 | qe_port->bd_dma_addr); |
1063 | ||
1064 | ucc_slow_free(uccs); | |
1065 | } | |
1066 | ||
1067 | /* | |
1068 | * Verify that the data in serial_struct is suitable for this device. | |
1069 | */ | |
1070 | static int qe_uart_verify_port(struct uart_port *port, | |
1071 | struct serial_struct *ser) | |
1072 | { | |
1073 | if (ser->type != PORT_UNKNOWN && ser->type != PORT_CPM) | |
1074 | return -EINVAL; | |
1075 | ||
a62c4133 | 1076 | if (ser->irq < 0 || ser->irq >= nr_irqs) |
d7584ed2 TT |
1077 | return -EINVAL; |
1078 | ||
1079 | if (ser->baud_base < 9600) | |
1080 | return -EINVAL; | |
1081 | ||
1082 | return 0; | |
1083 | } | |
1084 | /* UART operations | |
1085 | * | |
1086 | * Details on these functions can be found in Documentation/serial/driver | |
1087 | */ | |
1088 | static struct uart_ops qe_uart_pops = { | |
1089 | .tx_empty = qe_uart_tx_empty, | |
1090 | .set_mctrl = qe_uart_set_mctrl, | |
1091 | .get_mctrl = qe_uart_get_mctrl, | |
1092 | .stop_tx = qe_uart_stop_tx, | |
1093 | .start_tx = qe_uart_start_tx, | |
1094 | .stop_rx = qe_uart_stop_rx, | |
d7584ed2 TT |
1095 | .break_ctl = qe_uart_break_ctl, |
1096 | .startup = qe_uart_startup, | |
1097 | .shutdown = qe_uart_shutdown, | |
1098 | .set_termios = qe_uart_set_termios, | |
1099 | .type = qe_uart_type, | |
1100 | .release_port = qe_uart_release_port, | |
1101 | .request_port = qe_uart_request_port, | |
1102 | .config_port = qe_uart_config_port, | |
1103 | .verify_port = qe_uart_verify_port, | |
1104 | }; | |
1105 | ||
1106 | /* | |
1107 | * Obtain the SOC model number and revision level | |
1108 | * | |
1109 | * This function parses the device tree to obtain the SOC model. It then | |
1110 | * reads the SVR register to the revision. | |
1111 | * | |
1112 | * The device tree stores the SOC model two different ways. | |
1113 | * | |
1114 | * The new way is: | |
1115 | * | |
1116 | * cpu@0 { | |
1117 | * compatible = "PowerPC,8323"; | |
1118 | * device_type = "cpu"; | |
1119 | * ... | |
1120 | * | |
1121 | * | |
1122 | * The old way is: | |
1123 | * PowerPC,8323@0 { | |
1124 | * device_type = "cpu"; | |
1125 | * ... | |
1126 | * | |
1127 | * This code first checks the new way, and then the old way. | |
1128 | */ | |
1129 | static unsigned int soc_info(unsigned int *rev_h, unsigned int *rev_l) | |
1130 | { | |
1131 | struct device_node *np; | |
1132 | const char *soc_string; | |
1133 | unsigned int svr; | |
1134 | unsigned int soc; | |
1135 | ||
1136 | /* Find the CPU node */ | |
1137 | np = of_find_node_by_type(NULL, "cpu"); | |
1138 | if (!np) | |
1139 | return 0; | |
1140 | /* Find the compatible property */ | |
1141 | soc_string = of_get_property(np, "compatible", NULL); | |
1142 | if (!soc_string) | |
1143 | /* No compatible property, so try the name. */ | |
1144 | soc_string = np->name; | |
1145 | ||
1146 | /* Extract the SOC number from the "PowerPC," string */ | |
1147 | if ((sscanf(soc_string, "PowerPC,%u", &soc) != 1) || !soc) | |
1148 | return 0; | |
1149 | ||
1150 | /* Get the revision from the SVR */ | |
1151 | svr = mfspr(SPRN_SVR); | |
1152 | *rev_h = (svr >> 4) & 0xf; | |
1153 | *rev_l = svr & 0xf; | |
1154 | ||
1155 | return soc; | |
1156 | } | |
1157 | ||
1158 | /* | |
1159 | * requst_firmware_nowait() callback function | |
1160 | * | |
1161 | * This function is called by the kernel when a firmware is made available, | |
1162 | * or if it times out waiting for the firmware. | |
1163 | */ | |
1164 | static void uart_firmware_cont(const struct firmware *fw, void *context) | |
1165 | { | |
1166 | struct qe_firmware *firmware; | |
1167 | struct device *dev = context; | |
1168 | int ret; | |
1169 | ||
1170 | if (!fw) { | |
1171 | dev_err(dev, "firmware not found\n"); | |
1172 | return; | |
1173 | } | |
1174 | ||
1175 | firmware = (struct qe_firmware *) fw->data; | |
1176 | ||
1177 | if (firmware->header.length != fw->size) { | |
1178 | dev_err(dev, "invalid firmware\n"); | |
9ebfbd45 | 1179 | goto out; |
d7584ed2 TT |
1180 | } |
1181 | ||
1182 | ret = qe_upload_firmware(firmware); | |
1183 | if (ret) { | |
1184 | dev_err(dev, "could not load firmware\n"); | |
9ebfbd45 | 1185 | goto out; |
d7584ed2 TT |
1186 | } |
1187 | ||
1188 | firmware_loaded = 1; | |
9ebfbd45 JB |
1189 | out: |
1190 | release_firmware(fw); | |
d7584ed2 TT |
1191 | } |
1192 | ||
793218df | 1193 | static int ucc_uart_probe(struct platform_device *ofdev) |
d7584ed2 | 1194 | { |
61c7a080 | 1195 | struct device_node *np = ofdev->dev.of_node; |
d7584ed2 TT |
1196 | const unsigned int *iprop; /* Integer OF properties */ |
1197 | const char *sprop; /* String OF properties */ | |
1198 | struct uart_qe_port *qe_port = NULL; | |
1199 | struct resource res; | |
1200 | int ret; | |
1201 | ||
1202 | /* | |
1203 | * Determine if we need Soft-UART mode | |
1204 | */ | |
1205 | if (of_find_property(np, "soft-uart", NULL)) { | |
1206 | dev_dbg(&ofdev->dev, "using Soft-UART mode\n"); | |
1207 | soft_uart = 1; | |
1208 | } | |
1209 | ||
1210 | /* | |
1211 | * If we are using Soft-UART, determine if we need to upload the | |
1212 | * firmware, too. | |
1213 | */ | |
1214 | if (soft_uart) { | |
1215 | struct qe_firmware_info *qe_fw_info; | |
1216 | ||
1217 | qe_fw_info = qe_get_firmware_info(); | |
1218 | ||
1219 | /* Check if the firmware has been uploaded. */ | |
1220 | if (qe_fw_info && strstr(qe_fw_info->id, "Soft-UART")) { | |
1221 | firmware_loaded = 1; | |
1222 | } else { | |
1223 | char filename[32]; | |
1224 | unsigned int soc; | |
1225 | unsigned int rev_h; | |
1226 | unsigned int rev_l; | |
1227 | ||
1228 | soc = soc_info(&rev_h, &rev_l); | |
1229 | if (!soc) { | |
1230 | dev_err(&ofdev->dev, "unknown CPU model\n"); | |
1231 | return -ENXIO; | |
1232 | } | |
1233 | sprintf(filename, "fsl_qe_ucode_uart_%u_%u%u.bin", | |
1234 | soc, rev_h, rev_l); | |
1235 | ||
1236 | dev_info(&ofdev->dev, "waiting for firmware %s\n", | |
1237 | filename); | |
1238 | ||
1239 | /* | |
1240 | * We call request_firmware_nowait instead of | |
1241 | * request_firmware so that the driver can load and | |
1242 | * initialize the ports without holding up the rest of | |
1243 | * the kernel. If hotplug support is enabled in the | |
1244 | * kernel, then we use it. | |
1245 | */ | |
1246 | ret = request_firmware_nowait(THIS_MODULE, | |
1247 | FW_ACTION_HOTPLUG, filename, &ofdev->dev, | |
9ebfbd45 | 1248 | GFP_KERNEL, &ofdev->dev, uart_firmware_cont); |
d7584ed2 TT |
1249 | if (ret) { |
1250 | dev_err(&ofdev->dev, | |
1251 | "could not load firmware %s\n", | |
1252 | filename); | |
1253 | return ret; | |
1254 | } | |
1255 | } | |
1256 | } | |
1257 | ||
1258 | qe_port = kzalloc(sizeof(struct uart_qe_port), GFP_KERNEL); | |
1259 | if (!qe_port) { | |
1260 | dev_err(&ofdev->dev, "can't allocate QE port structure\n"); | |
1261 | return -ENOMEM; | |
1262 | } | |
1263 | ||
1264 | /* Search for IRQ and mapbase */ | |
1265 | ret = of_address_to_resource(np, 0, &res); | |
1266 | if (ret) { | |
1267 | dev_err(&ofdev->dev, "missing 'reg' property in device tree\n"); | |
48a10cdf | 1268 | goto out_free; |
d7584ed2 TT |
1269 | } |
1270 | if (!res.start) { | |
1271 | dev_err(&ofdev->dev, "invalid 'reg' property in device tree\n"); | |
48a10cdf JL |
1272 | ret = -EINVAL; |
1273 | goto out_free; | |
d7584ed2 TT |
1274 | } |
1275 | qe_port->port.mapbase = res.start; | |
1276 | ||
1277 | /* Get the UCC number (device ID) */ | |
1278 | /* UCCs are numbered 1-7 */ | |
56626f33 AV |
1279 | iprop = of_get_property(np, "cell-index", NULL); |
1280 | if (!iprop) { | |
1281 | iprop = of_get_property(np, "device-id", NULL); | |
1282 | if (!iprop) { | |
1283 | dev_err(&ofdev->dev, "UCC is unspecified in " | |
1284 | "device tree\n"); | |
48a10cdf JL |
1285 | ret = -EINVAL; |
1286 | goto out_free; | |
56626f33 AV |
1287 | } |
1288 | } | |
1289 | ||
1290 | if ((*iprop < 1) || (*iprop > UCC_MAX_NUM)) { | |
1291 | dev_err(&ofdev->dev, "no support for UCC%u\n", *iprop); | |
48a10cdf JL |
1292 | ret = -ENODEV; |
1293 | goto out_free; | |
d7584ed2 TT |
1294 | } |
1295 | qe_port->ucc_num = *iprop - 1; | |
1296 | ||
1297 | /* | |
1298 | * In the future, we should not require the BRG to be specified in the | |
1299 | * device tree. If no clock-source is specified, then just pick a BRG | |
1300 | * to use. This requires a new QE library function that manages BRG | |
1301 | * assignments. | |
1302 | */ | |
1303 | ||
1304 | sprop = of_get_property(np, "rx-clock-name", NULL); | |
1305 | if (!sprop) { | |
1306 | dev_err(&ofdev->dev, "missing rx-clock-name in device tree\n"); | |
48a10cdf JL |
1307 | ret = -ENODEV; |
1308 | goto out_free; | |
d7584ed2 TT |
1309 | } |
1310 | ||
1311 | qe_port->us_info.rx_clock = qe_clock_source(sprop); | |
1312 | if ((qe_port->us_info.rx_clock < QE_BRG1) || | |
1313 | (qe_port->us_info.rx_clock > QE_BRG16)) { | |
1314 | dev_err(&ofdev->dev, "rx-clock-name must be a BRG for UART\n"); | |
48a10cdf JL |
1315 | ret = -ENODEV; |
1316 | goto out_free; | |
d7584ed2 TT |
1317 | } |
1318 | ||
1319 | #ifdef LOOPBACK | |
1320 | /* In internal loopback mode, TX and RX must use the same clock */ | |
1321 | qe_port->us_info.tx_clock = qe_port->us_info.rx_clock; | |
1322 | #else | |
1323 | sprop = of_get_property(np, "tx-clock-name", NULL); | |
1324 | if (!sprop) { | |
1325 | dev_err(&ofdev->dev, "missing tx-clock-name in device tree\n"); | |
48a10cdf JL |
1326 | ret = -ENODEV; |
1327 | goto out_free; | |
d7584ed2 TT |
1328 | } |
1329 | qe_port->us_info.tx_clock = qe_clock_source(sprop); | |
1330 | #endif | |
1331 | if ((qe_port->us_info.tx_clock < QE_BRG1) || | |
1332 | (qe_port->us_info.tx_clock > QE_BRG16)) { | |
1333 | dev_err(&ofdev->dev, "tx-clock-name must be a BRG for UART\n"); | |
48a10cdf JL |
1334 | ret = -ENODEV; |
1335 | goto out_free; | |
d7584ed2 TT |
1336 | } |
1337 | ||
1338 | /* Get the port number, numbered 0-3 */ | |
1339 | iprop = of_get_property(np, "port-number", NULL); | |
1340 | if (!iprop) { | |
1341 | dev_err(&ofdev->dev, "missing port-number in device tree\n"); | |
48a10cdf JL |
1342 | ret = -EINVAL; |
1343 | goto out_free; | |
d7584ed2 TT |
1344 | } |
1345 | qe_port->port.line = *iprop; | |
1346 | if (qe_port->port.line >= UCC_MAX_UART) { | |
1347 | dev_err(&ofdev->dev, "port-number must be 0-%u\n", | |
1348 | UCC_MAX_UART - 1); | |
48a10cdf JL |
1349 | ret = -EINVAL; |
1350 | goto out_free; | |
d7584ed2 TT |
1351 | } |
1352 | ||
1353 | qe_port->port.irq = irq_of_parse_and_map(np, 0); | |
d4e33fac | 1354 | if (qe_port->port.irq == 0) { |
d7584ed2 TT |
1355 | dev_err(&ofdev->dev, "could not map IRQ for UCC%u\n", |
1356 | qe_port->ucc_num + 1); | |
48a10cdf JL |
1357 | ret = -EINVAL; |
1358 | goto out_free; | |
d7584ed2 TT |
1359 | } |
1360 | ||
1361 | /* | |
1362 | * Newer device trees have an "fsl,qe" compatible property for the QE | |
1363 | * node, but we still need to support older device trees. | |
1364 | */ | |
1365 | np = of_find_compatible_node(NULL, NULL, "fsl,qe"); | |
1366 | if (!np) { | |
1367 | np = of_find_node_by_type(NULL, "qe"); | |
1368 | if (!np) { | |
1369 | dev_err(&ofdev->dev, "could not find 'qe' node\n"); | |
48a10cdf JL |
1370 | ret = -EINVAL; |
1371 | goto out_free; | |
d7584ed2 TT |
1372 | } |
1373 | } | |
1374 | ||
1375 | iprop = of_get_property(np, "brg-frequency", NULL); | |
1376 | if (!iprop) { | |
1377 | dev_err(&ofdev->dev, | |
1378 | "missing brg-frequency in device tree\n"); | |
48a10cdf JL |
1379 | ret = -EINVAL; |
1380 | goto out_np; | |
d7584ed2 TT |
1381 | } |
1382 | ||
1383 | if (*iprop) | |
1384 | qe_port->port.uartclk = *iprop; | |
1385 | else { | |
1386 | /* | |
1387 | * Older versions of U-Boot do not initialize the brg-frequency | |
1388 | * property, so in this case we assume the BRG frequency is | |
1389 | * half the QE bus frequency. | |
1390 | */ | |
1391 | iprop = of_get_property(np, "bus-frequency", NULL); | |
1392 | if (!iprop) { | |
1393 | dev_err(&ofdev->dev, | |
1394 | "missing QE bus-frequency in device tree\n"); | |
48a10cdf JL |
1395 | ret = -EINVAL; |
1396 | goto out_np; | |
d7584ed2 TT |
1397 | } |
1398 | if (*iprop) | |
1399 | qe_port->port.uartclk = *iprop / 2; | |
1400 | else { | |
1401 | dev_err(&ofdev->dev, | |
1402 | "invalid QE bus-frequency in device tree\n"); | |
48a10cdf JL |
1403 | ret = -EINVAL; |
1404 | goto out_np; | |
d7584ed2 TT |
1405 | } |
1406 | } | |
1407 | ||
1408 | spin_lock_init(&qe_port->port.lock); | |
1409 | qe_port->np = np; | |
1410 | qe_port->port.dev = &ofdev->dev; | |
1411 | qe_port->port.ops = &qe_uart_pops; | |
1412 | qe_port->port.iotype = UPIO_MEM; | |
1413 | ||
1414 | qe_port->tx_nrfifos = TX_NUM_FIFO; | |
1415 | qe_port->tx_fifosize = TX_BUF_SIZE; | |
1416 | qe_port->rx_nrfifos = RX_NUM_FIFO; | |
1417 | qe_port->rx_fifosize = RX_BUF_SIZE; | |
1418 | ||
1419 | qe_port->wait_closing = UCC_WAIT_CLOSING; | |
1420 | qe_port->port.fifosize = 512; | |
1421 | qe_port->port.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP; | |
1422 | ||
1423 | qe_port->us_info.ucc_num = qe_port->ucc_num; | |
1424 | qe_port->us_info.regs = (phys_addr_t) res.start; | |
1425 | qe_port->us_info.irq = qe_port->port.irq; | |
1426 | ||
1427 | qe_port->us_info.rx_bd_ring_len = qe_port->rx_nrfifos; | |
1428 | qe_port->us_info.tx_bd_ring_len = qe_port->tx_nrfifos; | |
1429 | ||
1430 | /* Make sure ucc_slow_init() initializes both TX and RX */ | |
1431 | qe_port->us_info.init_tx = 1; | |
1432 | qe_port->us_info.init_rx = 1; | |
1433 | ||
1434 | /* Add the port to the uart sub-system. This will cause | |
1435 | * qe_uart_config_port() to be called, so the us_info structure must | |
1436 | * be initialized. | |
1437 | */ | |
1438 | ret = uart_add_one_port(&ucc_uart_driver, &qe_port->port); | |
1439 | if (ret) { | |
1440 | dev_err(&ofdev->dev, "could not add /dev/ttyQE%u\n", | |
1441 | qe_port->port.line); | |
48a10cdf | 1442 | goto out_np; |
d7584ed2 TT |
1443 | } |
1444 | ||
696faedd | 1445 | platform_set_drvdata(ofdev, qe_port); |
d7584ed2 TT |
1446 | |
1447 | dev_info(&ofdev->dev, "UCC%u assigned to /dev/ttyQE%u\n", | |
1448 | qe_port->ucc_num + 1, qe_port->port.line); | |
1449 | ||
1450 | /* Display the mknod command for this device */ | |
1451 | dev_dbg(&ofdev->dev, "mknod command is 'mknod /dev/ttyQE%u c %u %u'\n", | |
1452 | qe_port->port.line, SERIAL_QE_MAJOR, | |
1453 | SERIAL_QE_MINOR + qe_port->port.line); | |
1454 | ||
1455 | return 0; | |
48a10cdf JL |
1456 | out_np: |
1457 | of_node_put(np); | |
1458 | out_free: | |
1459 | kfree(qe_port); | |
1460 | return ret; | |
d7584ed2 TT |
1461 | } |
1462 | ||
2dc11581 | 1463 | static int ucc_uart_remove(struct platform_device *ofdev) |
d7584ed2 | 1464 | { |
696faedd | 1465 | struct uart_qe_port *qe_port = platform_get_drvdata(ofdev); |
d7584ed2 TT |
1466 | |
1467 | dev_info(&ofdev->dev, "removing /dev/ttyQE%u\n", qe_port->port.line); | |
1468 | ||
1469 | uart_remove_one_port(&ucc_uart_driver, &qe_port->port); | |
1470 | ||
d7584ed2 TT |
1471 | kfree(qe_port); |
1472 | ||
1473 | return 0; | |
1474 | } | |
1475 | ||
1476 | static struct of_device_id ucc_uart_match[] = { | |
1477 | { | |
1478 | .type = "serial", | |
1479 | .compatible = "ucc_uart", | |
1480 | }, | |
1481 | {}, | |
1482 | }; | |
1483 | MODULE_DEVICE_TABLE(of, ucc_uart_match); | |
1484 | ||
793218df | 1485 | static struct platform_driver ucc_uart_of_driver = { |
4018294b GL |
1486 | .driver = { |
1487 | .name = "ucc_uart", | |
1488 | .owner = THIS_MODULE, | |
1489 | .of_match_table = ucc_uart_match, | |
1490 | }, | |
d7584ed2 TT |
1491 | .probe = ucc_uart_probe, |
1492 | .remove = ucc_uart_remove, | |
1493 | }; | |
1494 | ||
1495 | static int __init ucc_uart_init(void) | |
1496 | { | |
1497 | int ret; | |
1498 | ||
1499 | printk(KERN_INFO "Freescale QUICC Engine UART device driver\n"); | |
1500 | #ifdef LOOPBACK | |
1501 | printk(KERN_INFO "ucc-uart: Using loopback mode\n"); | |
1502 | #endif | |
1503 | ||
1504 | ret = uart_register_driver(&ucc_uart_driver); | |
1505 | if (ret) { | |
1506 | printk(KERN_ERR "ucc-uart: could not register UART driver\n"); | |
1507 | return ret; | |
1508 | } | |
1509 | ||
793218df | 1510 | ret = platform_driver_register(&ucc_uart_of_driver); |
1b615bee | 1511 | if (ret) { |
d7584ed2 TT |
1512 | printk(KERN_ERR |
1513 | "ucc-uart: could not register platform driver\n"); | |
1b615bee LC |
1514 | uart_unregister_driver(&ucc_uart_driver); |
1515 | } | |
d7584ed2 TT |
1516 | |
1517 | return ret; | |
1518 | } | |
1519 | ||
1520 | static void __exit ucc_uart_exit(void) | |
1521 | { | |
1522 | printk(KERN_INFO | |
1523 | "Freescale QUICC Engine UART device driver unloading\n"); | |
1524 | ||
793218df | 1525 | platform_driver_unregister(&ucc_uart_of_driver); |
d7584ed2 TT |
1526 | uart_unregister_driver(&ucc_uart_driver); |
1527 | } | |
1528 | ||
1529 | module_init(ucc_uart_init); | |
1530 | module_exit(ucc_uart_exit); | |
1531 | ||
1532 | MODULE_DESCRIPTION("Freescale QUICC Engine (QE) UART"); | |
1533 | MODULE_AUTHOR("Timur Tabi <timur@freescale.com>"); | |
1534 | MODULE_LICENSE("GPL v2"); | |
1535 | MODULE_ALIAS_CHARDEV_MAJOR(SERIAL_QE_MAJOR); | |
1536 |