[linux-2.6-block.git] / drivers / tty / serial / stm32-usart.h

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (C) Maxime Coquelin 2015
 * Copyright (C) STMicroelectronics SA 2017
 * Authors:  Maxime Coquelin <mcoquelin.stm32@gmail.com>
 *	     Gerald Baeza <gerald_baeza@yahoo.fr>
 * License terms:  GNU General Public License (GPL), version 2
 */

#define DRIVER_NAME "stm32-usart"

struct stm32_usart_offsets {
	u8 cr1;
	u8 cr2;
	u8 cr3;
	u8 brr;
	u8 gtpr;
	u8 rtor;
	u8 rqr;
	u8 isr;
	u8 icr;
	u8 rdr;
	u8 tdr;
};

struct stm32_usart_config {
	u8 uart_enable_bit; /* USART_CR1_UE */
	bool has_7bits_data;
	bool has_wakeup;
	bool has_fifo;
};

struct stm32_usart_info {
	struct stm32_usart_offsets ofs;
	struct stm32_usart_config cfg;
};

#define UNDEF_REG 0xff

/* Register offsets */
struct stm32_usart_info stm32f4_info = {
	.ofs = {
		.isr	= 0x00,
		.rdr	= 0x04,
		.tdr	= 0x04,
		.brr	= 0x08,
		.cr1	= 0x0c,
		.cr2	= 0x10,
		.cr3	= 0x14,
		.gtpr	= 0x18,
		.rtor	= UNDEF_REG,
		.rqr	= UNDEF_REG,
		.icr	= UNDEF_REG,
	},
	.cfg = {
		.uart_enable_bit = 13,
		.has_7bits_data = false,
	}
};

struct stm32_usart_info stm32f7_info = {
	.ofs = {
		.cr1	= 0x00,
		.cr2	= 0x04,
		.cr3	= 0x08,
		.brr	= 0x0c,
		.gtpr	= 0x10,
		.rtor	= 0x14,
		.rqr	= 0x18,
		.isr	= 0x1c,
		.icr	= 0x20,
		.rdr	= 0x24,
		.tdr	= 0x28,
	},
	.cfg = {
		.uart_enable_bit = 0,
		.has_7bits_data = true,
	}
};

struct stm32_usart_info stm32h7_info = {
	.ofs = {
		.cr1	= 0x00,
		.cr2	= 0x04,
		.cr3	= 0x08,
		.brr	= 0x0c,
		.gtpr	= 0x10,
		.rtor	= 0x14,
		.rqr	= 0x18,
		.isr	= 0x1c,
		.icr	= 0x20,
		.rdr	= 0x24,
		.tdr	= 0x28,
	},
	.cfg = {
		.uart_enable_bit = 0,
		.has_7bits_data = true,
		.has_wakeup = true,
		.has_fifo = true,
	}
};

/* USART_SR (F4) / USART_ISR (F7) */
#define USART_SR_PE		BIT(0)
#define USART_SR_FE		BIT(1)
#define USART_SR_NF		BIT(2)
#define USART_SR_ORE		BIT(3)
#define USART_SR_IDLE		BIT(4)
#define USART_SR_RXNE		BIT(5)
#define USART_SR_TC		BIT(6)
#define USART_SR_TXE		BIT(7)
#define USART_SR_LBD		BIT(8)
#define USART_SR_CTSIF		BIT(9)
#define USART_SR_CTS		BIT(10)		/* F7 */
#define USART_SR_RTOF		BIT(11)		/* F7 */
#define USART_SR_EOBF		BIT(12)		/* F7 */
#define USART_SR_ABRE		BIT(14)		/* F7 */
#define USART_SR_ABRF		BIT(15)		/* F7 */
#define USART_SR_BUSY		BIT(16)		/* F7 */
#define USART_SR_CMF		BIT(17)		/* F7 */
#define USART_SR_SBKF		BIT(18)		/* F7 */
#define USART_SR_WUF		BIT(20)		/* H7 */
#define USART_SR_TEACK		BIT(21)		/* F7 */
#define USART_SR_ERR_MASK	(USART_SR_LBD | USART_SR_ORE | \
				 USART_SR_FE | USART_SR_PE)
/* Dummy bits */
#define USART_SR_DUMMY_RX	BIT(16)

/* USART_ICR (F7) */
#define USART_CR_TC		BIT(6)

/* USART_DR */
#define USART_DR_MASK		GENMASK(8, 0)

/* USART_BRR */
#define USART_BRR_DIV_F_MASK	GENMASK(3, 0)
#define USART_BRR_DIV_M_MASK	GENMASK(15, 4)
#define USART_BRR_DIV_M_SHIFT	4

/* USART_CR1 */
#define USART_CR1_SBK		BIT(0)
#define USART_CR1_RWU		BIT(1)		/* F4 */
#define USART_CR1_UESM		BIT(1)		/* H7 */
#define USART_CR1_RE		BIT(2)
#define USART_CR1_TE		BIT(3)
#define USART_CR1_IDLEIE	BIT(4)
#define USART_CR1_RXNEIE	BIT(5)
#define USART_CR1_TCIE		BIT(6)
#define USART_CR1_TXEIE		BIT(7)
#define USART_CR1_PEIE		BIT(8)
#define USART_CR1_PS		BIT(9)
#define USART_CR1_PCE		BIT(10)
#define USART_CR1_WAKE		BIT(11)
#define USART_CR1_M		BIT(12)
#define USART_CR1_M0		BIT(12)		/* F7 */
#define USART_CR1_MME		BIT(13)		/* F7 */
#define USART_CR1_CMIE		BIT(14)		/* F7 */
#define USART_CR1_OVER8		BIT(15)
#define USART_CR1_DEDT_MASK	GENMASK(20, 16)	/* F7 */
#define USART_CR1_DEAT_MASK	GENMASK(25, 21)	/* F7 */
#define USART_CR1_RTOIE		BIT(26)		/* F7 */
#define USART_CR1_EOBIE		BIT(27)		/* F7 */
#define USART_CR1_M1		BIT(28)		/* F7 */
#define USART_CR1_IE_MASK	(GENMASK(8, 4) | BIT(14) | BIT(26) | BIT(27))
#define USART_CR1_FIFOEN	BIT(29)		/* H7 */

/* USART_CR2 */
#define USART_CR2_ADD_MASK	GENMASK(3, 0)	/* F4 */
#define USART_CR2_ADDM7		BIT(4)		/* F7 */
#define USART_CR2_LBDL		BIT(5)
#define USART_CR2_LBDIE		BIT(6)
#define USART_CR2_LBCL		BIT(8)
#define USART_CR2_CPHA		BIT(9)
#define USART_CR2_CPOL		BIT(10)
#define USART_CR2_CLKEN		BIT(11)
#define USART_CR2_STOP_2B	BIT(13)
#define USART_CR2_STOP_MASK	GENMASK(13, 12)
#define USART_CR2_LINEN		BIT(14)
#define USART_CR2_SWAP		BIT(15)		/* F7 */
#define USART_CR2_RXINV		BIT(16)		/* F7 */
#define USART_CR2_TXINV		BIT(17)		/* F7 */
#define USART_CR2_DATAINV	BIT(18)		/* F7 */
#define USART_CR2_MSBFIRST	BIT(19)		/* F7 */
#define USART_CR2_ABREN		BIT(20)		/* F7 */
#define USART_CR2_ABRMOD_MASK	GENMASK(22, 21)	/* F7 */
#define USART_CR2_RTOEN		BIT(23)		/* F7 */
#define USART_CR2_ADD_F7_MASK	GENMASK(31, 24)	/* F7 */

/* USART_CR3 */
#define USART_CR3_EIE		BIT(0)
#define USART_CR3_IREN		BIT(1)
#define USART_CR3_IRLP		BIT(2)
#define USART_CR3_HDSEL		BIT(3)
#define USART_CR3_NACK		BIT(4)
#define USART_CR3_SCEN		BIT(5)
#define USART_CR3_DMAR		BIT(6)
#define USART_CR3_DMAT		BIT(7)
#define USART_CR3_RTSE		BIT(8)
#define USART_CR3_CTSE		BIT(9)
#define USART_CR3_CTSIE		BIT(10)
#define USART_CR3_ONEBIT	BIT(11)
#define USART_CR3_OVRDIS	BIT(12)		/* F7 */
#define USART_CR3_DDRE		BIT(13)		/* F7 */
#define USART_CR3_DEM		BIT(14)		/* F7 */
#define USART_CR3_DEP		BIT(15)		/* F7 */
#define USART_CR3_SCARCNT_MASK	GENMASK(19, 17)	/* F7 */
#define USART_CR3_WUS_MASK	GENMASK(21, 20)	/* H7 */
#define USART_CR3_WUS_START_BIT	BIT(21)		/* H7 */
#define USART_CR3_WUFIE		BIT(22)		/* H7 */

/* USART_GTPR */
#define USART_GTPR_PSC_MASK	GENMASK(7, 0)
#define USART_GTPR_GT_MASK	GENMASK(15, 8)

/* USART_RTOR */
#define USART_RTOR_RTO_MASK	GENMASK(23, 0)	/* F7 */
#define USART_RTOR_BLEN_MASK	GENMASK(31, 24)	/* F7 */

/* USART_RQR */
#define USART_RQR_ABRRQ		BIT(0)		/* F7 */
#define USART_RQR_SBKRQ		BIT(1)		/* F7 */
#define USART_RQR_MMRQ		BIT(2)		/* F7 */
#define USART_RQR_RXFRQ		BIT(3)		/* F7 */
#define USART_RQR_TXFRQ		BIT(4)		/* F7 */

/* USART_ICR */
#define USART_ICR_PECF		BIT(0)		/* F7 */
#define USART_ICR_FFECF		BIT(1)		/* F7 */
#define USART_ICR_NCF		BIT(2)		/* F7 */
#define USART_ICR_ORECF		BIT(3)		/* F7 */
#define USART_ICR_IDLECF	BIT(4)		/* F7 */
#define USART_ICR_TCCF		BIT(6)		/* F7 */
#define USART_ICR_LBDCF		BIT(8)		/* F7 */
#define USART_ICR_CTSCF		BIT(9)		/* F7 */
#define USART_ICR_RTOCF		BIT(11)		/* F7 */
#define USART_ICR_EOBCF		BIT(12)		/* F7 */
#define USART_ICR_CMCF		BIT(17)		/* F7 */
#define USART_ICR_WUCF		BIT(20)		/* H7 */

#define STM32_SERIAL_NAME "ttyS"
#define STM32_MAX_PORTS 8

#define RX_BUF_L 200		 /* dma rx buffer length     */
#define RX_BUF_P RX_BUF_L	 /* dma rx buffer period     */
#define TX_BUF_L 200		 /* dma tx buffer length     */

struct stm32_port {
	struct uart_port port;
	struct clk *clk;
	struct stm32_usart_info *info;
	struct dma_chan *rx_ch;  /* dma rx channel            */
	dma_addr_t rx_dma_buf;   /* dma rx buffer bus address */
	unsigned char *rx_buf;   /* dma rx buffer cpu address */
	struct dma_chan *tx_ch;  /* dma tx channel            */
	dma_addr_t tx_dma_buf;   /* dma tx buffer bus address */
	unsigned char *tx_buf;   /* dma tx buffer cpu address */
	int last_res;
	bool tx_dma_busy;	 /* dma tx busy               */
	bool hw_flow_control;
	bool fifoen;
	int wakeirq;
};

static struct stm32_port stm32_ports[STM32_MAX_PORTS];
static struct uart_driver stm32_usart_driver;
Commit	Line	Data
e3b3d0f5	1	// SPDX-License-Identifier: GPL-2.0
bc5a0b55 AT	2	/*
bc5a0b55 AT	3	* Copyright (C) Maxime Coquelin 2015
3e5fcbac	4	* Copyright (C) STMicroelectronics SA 2017
bc5a0b55 AT	5	* Authors: Maxime Coquelin <mcoquelin.stm32@gmail.com>
	6	* Gerald Baeza <gerald_baeza@yahoo.fr>
	7	* License terms: GNU General Public License (GPL), version 2
	8	*/
	9
	10	#define DRIVER_NAME "stm32-usart"
	11
	12	struct stm32_usart_offsets {
	13	u8 cr1;
	14	u8 cr2;
	15	u8 cr3;
	16	u8 brr;
	17	u8 gtpr;
	18	u8 rtor;
	19	u8 rqr;
	20	u8 isr;
	21	u8 icr;
	22	u8 rdr;
	23	u8 tdr;
	24	};
	25
	26	struct stm32_usart_config {
	27	u8 uart_enable_bit; /* USART_CR1_UE */
	28	bool has_7bits_data;
270e5a74	29	bool has_wakeup;
351a762a	30	bool has_fifo;
bc5a0b55 AT	31	};
	32
	33	struct stm32_usart_info {
	34	struct stm32_usart_offsets ofs;
	35	struct stm32_usart_config cfg;
	36	};
	37
b20fb13c	38	#define UNDEF_REG 0xff
bc5a0b55 AT	39
	40	/* Register offsets */
	41	struct stm32_usart_info stm32f4_info = {
	42	.ofs = {
	43	.isr = 0x00,
	44	.rdr = 0x04,
	45	.tdr = 0x04,
	46	.brr = 0x08,
	47	.cr1 = 0x0c,
	48	.cr2 = 0x10,
	49	.cr3 = 0x14,
	50	.gtpr = 0x18,
	51	.rtor = UNDEF_REG,
	52	.rqr = UNDEF_REG,
	53	.icr = UNDEF_REG,
	54	},
	55	.cfg = {
	56	.uart_enable_bit = 13,
	57	.has_7bits_data = false,
	58	}
	59	};
	60
	61	struct stm32_usart_info stm32f7_info = {
	62	.ofs = {
	63	.cr1 = 0x00,
	64	.cr2 = 0x04,
	65	.cr3 = 0x08,
	66	.brr = 0x0c,
	67	.gtpr = 0x10,
	68	.rtor = 0x14,
	69	.rqr = 0x18,
	70	.isr = 0x1c,
	71	.icr = 0x20,
	72	.rdr = 0x24,
	73	.tdr = 0x28,
	74	},
	75	.cfg = {
	76	.uart_enable_bit = 0,
	77	.has_7bits_data = true,
	78	}
	79	};
	80
270e5a74 FG	81	struct stm32_usart_info stm32h7_info = {
	82	.ofs = {
	83	.cr1 = 0x00,
	84	.cr2 = 0x04,
	85	.cr3 = 0x08,
	86	.brr = 0x0c,
	87	.gtpr = 0x10,
	88	.rtor = 0x14,
	89	.rqr = 0x18,
	90	.isr = 0x1c,
	91	.icr = 0x20,
	92	.rdr = 0x24,
	93	.tdr = 0x28,
	94	},
	95	.cfg = {
	96	.uart_enable_bit = 0,
	97	.has_7bits_data = true,
	98	.has_wakeup = true,
351a762a	99	.has_fifo = true,
270e5a74 FG	100	}
	101	};
	102
bc5a0b55 AT	103	/* USART_SR (F4) / USART_ISR (F7) */
	104	#define USART_SR_PE BIT(0)
	105	#define USART_SR_FE BIT(1)
	106	#define USART_SR_NF BIT(2)
	107	#define USART_SR_ORE BIT(3)
	108	#define USART_SR_IDLE BIT(4)
	109	#define USART_SR_RXNE BIT(5)
	110	#define USART_SR_TC BIT(6)
	111	#define USART_SR_TXE BIT(7)
	112	#define USART_SR_LBD BIT(8)
	113	#define USART_SR_CTSIF BIT(9)
	114	#define USART_SR_CTS BIT(10) /* F7 */
	115	#define USART_SR_RTOF BIT(11) /* F7 */
	116	#define USART_SR_EOBF BIT(12) /* F7 */
	117	#define USART_SR_ABRE BIT(14) /* F7 */
	118	#define USART_SR_ABRF BIT(15) /* F7 */
	119	#define USART_SR_BUSY BIT(16) /* F7 */
	120	#define USART_SR_CMF BIT(17) /* F7 */
	121	#define USART_SR_SBKF BIT(18) /* F7 */
270e5a74	122	#define USART_SR_WUF BIT(20) /* H7 */
bc5a0b55 AT	123	#define USART_SR_TEACK BIT(21) /* F7 */
	124	#define USART_SR_ERR_MASK (USART_SR_LBD \| USART_SR_ORE \| \
	125	USART_SR_FE \| USART_SR_PE)
	126	/* Dummy bits */
	127	#define USART_SR_DUMMY_RX BIT(16)
	128
34891872 AT	129	/* USART_ICR (F7) */
	130	#define USART_CR_TC BIT(6)
	131
bc5a0b55 AT	132	/* USART_DR */
	133	#define USART_DR_MASK GENMASK(8, 0)
	134
	135	/* USART_BRR */
	136	#define USART_BRR_DIV_F_MASK GENMASK(3, 0)
	137	#define USART_BRR_DIV_M_MASK GENMASK(15, 4)
	138	#define USART_BRR_DIV_M_SHIFT 4
	139
	140	/* USART_CR1 */
	141	#define USART_CR1_SBK BIT(0)
	142	#define USART_CR1_RWU BIT(1) /* F4 */
270e5a74	143	#define USART_CR1_UESM BIT(1) /* H7 */
bc5a0b55 AT	144	#define USART_CR1_RE BIT(2)
	145	#define USART_CR1_TE BIT(3)
	146	#define USART_CR1_IDLEIE BIT(4)
	147	#define USART_CR1_RXNEIE BIT(5)
	148	#define USART_CR1_TCIE BIT(6)
	149	#define USART_CR1_TXEIE BIT(7)
	150	#define USART_CR1_PEIE BIT(8)
	151	#define USART_CR1_PS BIT(9)
	152	#define USART_CR1_PCE BIT(10)
	153	#define USART_CR1_WAKE BIT(11)
	154	#define USART_CR1_M BIT(12)
	155	#define USART_CR1_M0 BIT(12) /* F7 */
	156	#define USART_CR1_MME BIT(13) /* F7 */
	157	#define USART_CR1_CMIE BIT(14) /* F7 */
	158	#define USART_CR1_OVER8 BIT(15)
	159	#define USART_CR1_DEDT_MASK GENMASK(20, 16) /* F7 */
	160	#define USART_CR1_DEAT_MASK GENMASK(25, 21) /* F7 */
	161	#define USART_CR1_RTOIE BIT(26) /* F7 */
	162	#define USART_CR1_EOBIE BIT(27) /* F7 */
	163	#define USART_CR1_M1 BIT(28) /* F7 */
	164	#define USART_CR1_IE_MASK (GENMASK(8, 4) \| BIT(14) \| BIT(26) \| BIT(27))
351a762a	165	#define USART_CR1_FIFOEN BIT(29) /* H7 */
bc5a0b55 AT	166
	167	/* USART_CR2 */
	168	#define USART_CR2_ADD_MASK GENMASK(3, 0) /* F4 */
	169	#define USART_CR2_ADDM7 BIT(4) /* F7 */
	170	#define USART_CR2_LBDL BIT(5)
	171	#define USART_CR2_LBDIE BIT(6)
	172	#define USART_CR2_LBCL BIT(8)
	173	#define USART_CR2_CPHA BIT(9)
	174	#define USART_CR2_CPOL BIT(10)
	175	#define USART_CR2_CLKEN BIT(11)
	176	#define USART_CR2_STOP_2B BIT(13)
	177	#define USART_CR2_STOP_MASK GENMASK(13, 12)
	178	#define USART_CR2_LINEN BIT(14)
	179	#define USART_CR2_SWAP BIT(15) /* F7 */
	180	#define USART_CR2_RXINV BIT(16) /* F7 */
	181	#define USART_CR2_TXINV BIT(17) /* F7 */
	182	#define USART_CR2_DATAINV BIT(18) /* F7 */
	183	#define USART_CR2_MSBFIRST BIT(19) /* F7 */
	184	#define USART_CR2_ABREN BIT(20) /* F7 */
	185	#define USART_CR2_ABRMOD_MASK GENMASK(22, 21) /* F7 */
	186	#define USART_CR2_RTOEN BIT(23) /* F7 */
	187	#define USART_CR2_ADD_F7_MASK GENMASK(31, 24) /* F7 */
	188
	189	/* USART_CR3 */
	190	#define USART_CR3_EIE BIT(0)
	191	#define USART_CR3_IREN BIT(1)
	192	#define USART_CR3_IRLP BIT(2)
	193	#define USART_CR3_HDSEL BIT(3)
	194	#define USART_CR3_NACK BIT(4)
	195	#define USART_CR3_SCEN BIT(5)
	196	#define USART_CR3_DMAR BIT(6)
	197	#define USART_CR3_DMAT BIT(7)
	198	#define USART_CR3_RTSE BIT(8)
	199	#define USART_CR3_CTSE BIT(9)
	200	#define USART_CR3_CTSIE BIT(10)
	201	#define USART_CR3_ONEBIT BIT(11)
	202	#define USART_CR3_OVRDIS BIT(12) /* F7 */
	203	#define USART_CR3_DDRE BIT(13) /* F7 */
	204	#define USART_CR3_DEM BIT(14) /* F7 */
	205	#define USART_CR3_DEP BIT(15) /* F7 */
	206	#define USART_CR3_SCARCNT_MASK GENMASK(19, 17) /* F7 */
270e5a74 FG	207	#define USART_CR3_WUS_MASK GENMASK(21, 20) /* H7 */
	208	#define USART_CR3_WUS_START_BIT BIT(21) /* H7 */
	209	#define USART_CR3_WUFIE BIT(22) /* H7 */
bc5a0b55 AT	210
	211	/* USART_GTPR */
	212	#define USART_GTPR_PSC_MASK GENMASK(7, 0)
	213	#define USART_GTPR_GT_MASK GENMASK(15, 8)
	214
	215	/* USART_RTOR */
	216	#define USART_RTOR_RTO_MASK GENMASK(23, 0) /* F7 */
	217	#define USART_RTOR_BLEN_MASK GENMASK(31, 24) /* F7 */
	218
	219	/* USART_RQR */
	220	#define USART_RQR_ABRRQ BIT(0) /* F7 */
	221	#define USART_RQR_SBKRQ BIT(1) /* F7 */
	222	#define USART_RQR_MMRQ BIT(2) /* F7 */
	223	#define USART_RQR_RXFRQ BIT(3) /* F7 */
	224	#define USART_RQR_TXFRQ BIT(4) /* F7 */
	225
	226	/* USART_ICR */
	227	#define USART_ICR_PECF BIT(0) /* F7 */
	228	#define USART_ICR_FFECF BIT(1) /* F7 */
	229	#define USART_ICR_NCF BIT(2) /* F7 */
	230	#define USART_ICR_ORECF BIT(3) /* F7 */
	231	#define USART_ICR_IDLECF BIT(4) /* F7 */
	232	#define USART_ICR_TCCF BIT(6) /* F7 */
	233	#define USART_ICR_LBDCF BIT(8) /* F7 */
	234	#define USART_ICR_CTSCF BIT(9) /* F7 */
	235	#define USART_ICR_RTOCF BIT(11) /* F7 */
	236	#define USART_ICR_EOBCF BIT(12) /* F7 */
	237	#define USART_ICR_CMCF BIT(17) /* F7 */
270e5a74	238	#define USART_ICR_WUCF BIT(20) /* H7 */
bc5a0b55 AT	239
bc5a0b55 AT	240	#define STM32_SERIAL_NAME "ttyS"
cc7aefd4	241	#define STM32_MAX_PORTS 8
bc5a0b55	242
34891872 AT	243	#define RX_BUF_L 200 /* dma rx buffer length */
	244	#define RX_BUF_P RX_BUF_L /* dma rx buffer period */
	245	#define TX_BUF_L 200 /* dma tx buffer length */
	246
bc5a0b55 AT	247	struct stm32_port {
	248	struct uart_port port;
	249	struct clk *clk;
	250	struct stm32_usart_info *info;
34891872 AT	251	struct dma_chan rx_ch; / dma rx channel */
	252	dma_addr_t rx_dma_buf; /* dma rx buffer bus address */
	253	unsigned char rx_buf; / dma rx buffer cpu address */
	254	struct dma_chan tx_ch; / dma tx channel */
	255	dma_addr_t tx_dma_buf; /* dma tx buffer bus address */
	256	unsigned char tx_buf; / dma tx buffer cpu address */
e5707915	257	int last_res;
34891872	258	bool tx_dma_busy; /* dma tx busy */
bc5a0b55	259	bool hw_flow_control;
351a762a	260	bool fifoen;
270e5a74	261	int wakeirq;
bc5a0b55 AT	262	};
	263
	264	static struct stm32_port stm32_ports[STM32_MAX_PORTS];
	265	static struct uart_driver stm32_usart_driver;