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serial: sirf: fix the typo for rts/cts gpio
[linux-2.6-block.git] / drivers / tty / serial / sirfsoc_uart.c
CommitLineData
161e773c
RW		 1/*
2 * Driver for CSR SiRFprimaII onboard UARTs.
3 *
4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
5 *
6 * Licensed under GPLv2 or later.
7 */
8
9#include <linux/module.h>
10#include <linux/ioport.h>
11#include <linux/platform_device.h>
12#include <linux/init.h>
13#include <linux/sysrq.h>
14#include <linux/console.h>
15#include <linux/tty.h>
16#include <linux/tty_flip.h>
17#include <linux/serial_core.h>
18#include <linux/serial.h>
19#include <linux/clk.h>
20#include <linux/of.h>
21#include <linux/slab.h>
22#include <linux/io.h>
2eb5618d 23#include <linux/of_gpio.h>
161e773c
RW		 24#include <asm/irq.h>
25#include <asm/mach/irq.h>
161e773c
RW		 26
27#include "sirfsoc_uart.h"
28
29static unsigned int
30sirfsoc_uart_pio_tx_chars(struct sirfsoc_uart_port *sirfport, int count);
31static unsigned int
32sirfsoc_uart_pio_rx_chars(struct uart_port *port, unsigned int max_rx_count);
33static struct uart_driver sirfsoc_uart_drv;
34
35static const struct sirfsoc_baudrate_to_regv baudrate_to_regv[] = {
36 {4000000, 2359296},
37 {3500000, 1310721},
38 {3000000, 1572865},
39 {2500000, 1245186},
40 {2000000, 1572866},
41 {1500000, 1245188},
42 {1152000, 1638404},
43 {1000000, 1572869},
44 {921600, 1114120},
45 {576000, 1245196},
46 {500000, 1245198},
47 {460800, 1572876},
48 {230400, 1310750},
49 {115200, 1310781},
50 {57600, 1310843},
51 {38400, 1114328},
52 {19200, 1114545},
53 {9600, 1114979},
54};
55
56static struct sirfsoc_uart_port sirfsoc_uart_ports[SIRFSOC_UART_NR] = {
57 [0] = {
58 .port = {
59 .iotype = UPIO_MEM,
60 .flags = UPF_BOOT_AUTOCONF,
61 .line = 0,
62 },
63 },
64 [1] = {
65 .port = {
66 .iotype = UPIO_MEM,
67 .flags = UPF_BOOT_AUTOCONF,
68 .line = 1,
69 },
70 },
71 [2] = {
72 .port = {
73 .iotype = UPIO_MEM,
74 .flags = UPF_BOOT_AUTOCONF,
75 .line = 2,
76 },
77 },
5425e03f
BS		 78 [3] = {
79 .port = {
80 .iotype = UPIO_MEM,
81 .flags = UPF_BOOT_AUTOCONF,
82 .line = 3,
83 },
84 },
85 [4] = {
86 .port = {
87 .iotype = UPIO_MEM,
88 .flags = UPF_BOOT_AUTOCONF,
89 .line = 4,
90 },
91 },
161e773c
RW		 92};
93
94static inline struct sirfsoc_uart_port *to_sirfport(struct uart_port *port)
95{
96 return container_of(port, struct sirfsoc_uart_port, port);
97}
98
99static inline unsigned int sirfsoc_uart_tx_empty(struct uart_port *port)
100{
101 unsigned long reg;
5df83111
QL		 102 struct sirfsoc_uart_port *sirfport = to_sirfport(port);
103 struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
104 struct sirfsoc_fifo_status *ufifo_st = &sirfport->uart_reg->fifo_status;
105 reg = rd_regl(port, ureg->sirfsoc_tx_fifo_status);
106
107 return (reg & ufifo_st->ff_empty(port->line)) ? TIOCSER_TEMT : 0;
161e773c
RW		 108}
109
110static unsigned int sirfsoc_uart_get_mctrl(struct uart_port *port)
111{
112 struct sirfsoc_uart_port *sirfport = to_sirfport(port);
5df83111 113 struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
2eb5618d 114 if (!sirfport->hw_flow_ctrl || !sirfport->ms_enabled)
161e773c 115 goto cts_asserted;
2eb5618d 116 if (sirfport->uart_reg->uart_type == SIRF_REAL_UART) {
5df83111
QL		 117 if (!(rd_regl(port, ureg->sirfsoc_afc_ctrl) &
118 SIRFUART_AFC_CTS_STATUS))
161e773c
RW		 119 goto cts_asserted;
120 else
121 goto cts_deasserted;
2eb5618d
QL		 122 } else {
123 if (!gpio_get_value(sirfport->cts_gpio))
124 goto cts_asserted;
125 else
126 goto cts_deasserted;
161e773c
RW		 127 }
128cts_deasserted:
129 return TIOCM_CAR | TIOCM_DSR;
130cts_asserted:
131 return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
132}
133
134static void sirfsoc_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
135{
136 struct sirfsoc_uart_port *sirfport = to_sirfport(port);
5df83111 137 struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
161e773c
RW		 138 unsigned int assert = mctrl & TIOCM_RTS;
139 unsigned int val = assert ? SIRFUART_AFC_CTRL_RX_THD : 0x0;
140 unsigned int current_val;
2eb5618d
QL		 141
142 if (!sirfport->hw_flow_ctrl || !sirfport->ms_enabled)
143 return;
144 if (sirfport->uart_reg->uart_type == SIRF_REAL_UART) {
5df83111 145 current_val = rd_regl(port, ureg->sirfsoc_afc_ctrl) & ~0xFF;
161e773c 146 val |= current_val;
5df83111 147 wr_regl(port, ureg->sirfsoc_afc_ctrl, val);
2eb5618d
QL		 148 } else {
149 if (!val)
150 gpio_set_value(sirfport->rts_gpio, 1);
151 else
152 gpio_set_value(sirfport->rts_gpio, 0);
161e773c
RW		 153 }
154}
155
156static void sirfsoc_uart_stop_tx(struct uart_port *port)
157{
909102db 158 struct sirfsoc_uart_port *sirfport = to_sirfport(port);
5df83111
QL		 159 struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
160 struct sirfsoc_int_en *uint_en = &sirfport->uart_reg->uart_int_en;
161e773c 161 unsigned int regv;
909102db
BS		 162
163 if (!sirfport->is_marco) {
5df83111
QL		 164 regv = rd_regl(port, ureg->sirfsoc_int_en_reg);
165 wr_regl(port, ureg->sirfsoc_int_en_reg,
166 regv & ~uint_en->sirfsoc_txfifo_empty_en);
167 } else
168 wr_regl(port, SIRFUART_INT_EN_CLR,
169 uint_en->sirfsoc_txfifo_empty_en);
170
161e773c
RW		 171}
172
ada1f443 173static void sirfsoc_uart_start_tx(struct uart_port *port)
161e773c
RW		 174{
175 struct sirfsoc_uart_port *sirfport = to_sirfport(port);
5df83111
QL		 176 struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
177 struct sirfsoc_int_en *uint_en = &sirfport->uart_reg->uart_int_en;
161e773c 178 unsigned long regv;
909102db 179
161e773c 180 sirfsoc_uart_pio_tx_chars(sirfport, 1);
5df83111 181 wr_regl(port, ureg->sirfsoc_tx_fifo_op, SIRFUART_FIFO_START);
909102db 182 if (!sirfport->is_marco) {
5df83111
QL		 183 regv = rd_regl(port, ureg->sirfsoc_int_en_reg);
184 wr_regl(port, ureg->sirfsoc_int_en_reg, regv |
185 uint_en->sirfsoc_txfifo_empty_en);
186 } else
187 wr_regl(port, ureg->sirfsoc_int_en_reg,
188 uint_en->sirfsoc_txfifo_empty_en);
161e773c
RW		 189}
190
191static void sirfsoc_uart_stop_rx(struct uart_port *port)
192{
909102db 193 struct sirfsoc_uart_port *sirfport = to_sirfport(port);
5df83111
QL		 194 struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
195 struct sirfsoc_int_en *uint_en = &sirfport->uart_reg->uart_int_en;
196 unsigned long reg;
197 wr_regl(port, ureg->sirfsoc_rx_fifo_op, 0);
909102db 198 if (!sirfport->is_marco) {
5df83111
QL		 199 reg = rd_regl(port, ureg->sirfsoc_int_en_reg);
200 wr_regl(port, ureg->sirfsoc_int_en_reg,
201 reg & ~(SIRFUART_RX_IO_INT_EN(port, uint_en)));
202 } else
203 wr_regl(port, SIRFUART_INT_EN_CLR,
204 SIRFUART_RX_IO_INT_EN(port, uint_en));
161e773c
RW		 205}
206
207static void sirfsoc_uart_disable_ms(struct uart_port *port)
208{
209 struct sirfsoc_uart_port *sirfport = to_sirfport(port);
5df83111
QL		 210 struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
211 struct sirfsoc_int_en *uint_en = &sirfport->uart_reg->uart_int_en;
909102db 212
161e773c
RW		 213 if (!sirfport->hw_flow_ctrl)
214 return;
2eb5618d
QL		 215 sirfport->ms_enabled = false;
216 if (sirfport->uart_reg->uart_type == SIRF_REAL_UART) {
217 wr_regl(port, ureg->sirfsoc_afc_ctrl,
218 rd_regl(port, ureg->sirfsoc_afc_ctrl) & ~0x3FF);
219 if (!sirfport->is_marco)
220 wr_regl(port, ureg->sirfsoc_int_en_reg,
221 rd_regl(port, ureg->sirfsoc_int_en_reg)&
222 ~uint_en->sirfsoc_cts_en);
223 else
224 wr_regl(port, SIRFUART_INT_EN_CLR,
225 uint_en->sirfsoc_cts_en);
5df83111 226 } else
2eb5618d
QL		 227 disable_irq(gpio_to_irq(sirfport->cts_gpio));
228}
229
230static irqreturn_t sirfsoc_uart_usp_cts_handler(int irq, void *dev_id)
231{
232 struct sirfsoc_uart_port *sirfport = (struct sirfsoc_uart_port *)dev_id;
233 struct uart_port *port = &sirfport->port;
234 if (gpio_is_valid(sirfport->cts_gpio) && sirfport->ms_enabled)
235 uart_handle_cts_change(port,
236 !gpio_get_value(sirfport->cts_gpio));
237 return IRQ_HANDLED;
161e773c
RW		 238}
239
240static void sirfsoc_uart_enable_ms(struct uart_port *port)
241{
242 struct sirfsoc_uart_port *sirfport = to_sirfport(port);
5df83111
QL		 243 struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
244 struct sirfsoc_int_en *uint_en = &sirfport->uart_reg->uart_int_en;
909102db 245
161e773c
RW		 246 if (!sirfport->hw_flow_ctrl)
247 return;
2eb5618d
QL		 248 sirfport->ms_enabled = true;
249 if (sirfport->uart_reg->uart_type == SIRF_REAL_UART) {
250 wr_regl(port, ureg->sirfsoc_afc_ctrl,
251 rd_regl(port, ureg->sirfsoc_afc_ctrl) |
252 SIRFUART_AFC_TX_EN | SIRFUART_AFC_RX_EN);
253 if (!sirfport->is_marco)
254 wr_regl(port, ureg->sirfsoc_int_en_reg,
255 rd_regl(port, ureg->sirfsoc_int_en_reg)
256 | uint_en->sirfsoc_cts_en);
257 else
258 wr_regl(port, ureg->sirfsoc_int_en_reg,
259 uint_en->sirfsoc_cts_en);
5df83111 260 } else
2eb5618d 261 enable_irq(gpio_to_irq(sirfport->cts_gpio));
161e773c
RW		 262}
263
264static void sirfsoc_uart_break_ctl(struct uart_port *port, int break_state)
265{
5df83111
QL		 266 struct sirfsoc_uart_port *sirfport = to_sirfport(port);
267 struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
268 if (sirfport->uart_reg->uart_type == SIRF_REAL_UART) {
269 unsigned long ulcon = rd_regl(port, ureg->sirfsoc_line_ctrl);
270 if (break_state)
271 ulcon |= SIRFUART_SET_BREAK;
272 else
273 ulcon &= ~SIRFUART_SET_BREAK;
274 wr_regl(port, ureg->sirfsoc_line_ctrl, ulcon);
275 }
161e773c
RW		 276}
277
278static unsigned int
279sirfsoc_uart_pio_rx_chars(struct uart_port *port, unsigned int max_rx_count)
280{
5df83111
QL		 281 struct sirfsoc_uart_port *sirfport = to_sirfport(port);
282 struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
283 struct sirfsoc_fifo_status *ufifo_st = &sirfport->uart_reg->fifo_status;
161e773c 284 unsigned int ch, rx_count = 0;
5df83111
QL		 285 struct tty_struct *tty;
286 tty = tty_port_tty_get(&port->state->port);
287 if (!tty)
288 return -ENODEV;
289 while (!(rd_regl(port, ureg->sirfsoc_rx_fifo_status) &
290 ufifo_st->ff_empty(port->line))) {
291 ch = rd_regl(port, ureg->sirfsoc_rx_fifo_data) |
292 SIRFUART_DUMMY_READ;
161e773c
RW		 293 if (unlikely(uart_handle_sysrq_char(port, ch)))
294 continue;
295 uart_insert_char(port, 0, 0, ch, TTY_NORMAL);
296 rx_count++;
297 if (rx_count >= max_rx_count)
298 break;
299 }
300
301 port->icount.rx += rx_count;
2e124b4a 302 tty_flip_buffer_push(&port->state->port);
161e773c
RW		 303
304 return rx_count;
305}
306
307static unsigned int
308sirfsoc_uart_pio_tx_chars(struct sirfsoc_uart_port *sirfport, int count)
309{
310 struct uart_port *port = &sirfport->port;
5df83111
QL		 311 struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
312 struct sirfsoc_fifo_status *ufifo_st = &sirfport->uart_reg->fifo_status;
161e773c
RW		 313 struct circ_buf *xmit = &port->state->xmit;
314 unsigned int num_tx = 0;
315 while (!uart_circ_empty(xmit) &&
5df83111
QL		 316 !(rd_regl(port, ureg->sirfsoc_tx_fifo_status) &
317 ufifo_st->ff_full(port->line)) &&
161e773c 318 count--) {
5df83111
QL		 319 wr_regl(port, ureg->sirfsoc_tx_fifo_data,
320 xmit->buf[xmit->tail]);
161e773c
RW		 321 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
322 port->icount.tx++;
323 num_tx++;
324 }
325 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
326 uart_write_wakeup(port);
327 return num_tx;
328}
329
330static irqreturn_t sirfsoc_uart_isr(int irq, void *dev_id)
331{
332 unsigned long intr_status;
333 unsigned long cts_status;
334 unsigned long flag = TTY_NORMAL;
335 struct sirfsoc_uart_port *sirfport = (struct sirfsoc_uart_port *)dev_id;
336 struct uart_port *port = &sirfport->port;
5df83111
QL		 337 struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
338 struct sirfsoc_fifo_status *ufifo_st = &sirfport->uart_reg->fifo_status;
339 struct sirfsoc_int_status *uint_st = &sirfport->uart_reg->uart_int_st;
340 struct sirfsoc_int_en *uint_en = &sirfport->uart_reg->uart_int_en;
161e773c
RW		 341 struct uart_state *state = port->state;
342 struct circ_buf *xmit = &port->state->xmit;
5425e03f 343 spin_lock(&port->lock);
5df83111
QL		 344 intr_status = rd_regl(port, ureg->sirfsoc_int_st_reg);
345 wr_regl(port, ureg->sirfsoc_int_st_reg, intr_status);
346 if (unlikely(intr_status & (SIRFUART_ERR_INT_STAT(port, uint_st)))) {
347 if (intr_status & uint_st->sirfsoc_rxd_brk) {
348 port->icount.brk++;
161e773c
RW		 349 if (uart_handle_break(port))
350 goto recv_char;
161e773c 351 }
5df83111 352 if (intr_status & uint_st->sirfsoc_rx_oflow)
161e773c 353 port->icount.overrun++;
5df83111 354 if (intr_status & uint_st->sirfsoc_frm_err) {
161e773c
RW		 355 port->icount.frame++;
356 flag = TTY_FRAME;
357 }
5df83111 358 if (intr_status & uint_st->sirfsoc_parity_err)
161e773c 359 flag = TTY_PARITY;
5df83111
QL		 360 wr_regl(port, ureg->sirfsoc_rx_fifo_op, SIRFUART_FIFO_RESET);
361 wr_regl(port, ureg->sirfsoc_rx_fifo_op, 0);
362 wr_regl(port, ureg->sirfsoc_rx_fifo_op, SIRFUART_FIFO_START);
161e773c
RW		 363 intr_status &= port->read_status_mask;
364 uart_insert_char(port, intr_status,
5df83111
QL		 365 uint_en->sirfsoc_rx_oflow_en, 0, flag);
366 tty_flip_buffer_push(&state->port);
161e773c
RW		 367 }
368recv_char:
5df83111
QL		 369 if ((sirfport->uart_reg->uart_type == SIRF_REAL_UART) &&
370 (intr_status & SIRFUART_CTS_INT_ST(uint_st))) {
371 cts_status = rd_regl(port, ureg->sirfsoc_afc_ctrl) &
372 SIRFUART_AFC_CTS_STATUS;
373 if (cts_status != 0)
374 cts_status = 0;
375 else
376 cts_status = 1;
377 uart_handle_cts_change(port, cts_status);
378 wake_up_interruptible(&state->port.delta_msr_wait);
161e773c 379 }
5df83111 380 if (intr_status & SIRFUART_RX_IO_INT_ST(uint_st))
161e773c 381 sirfsoc_uart_pio_rx_chars(port, SIRFSOC_UART_IO_RX_MAX_CNT);
5df83111 382 if (intr_status & uint_st->sirfsoc_txfifo_empty) {
161e773c 383 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
5425e03f 384 spin_unlock(&port->lock);
161e773c
RW		 385 return IRQ_HANDLED;
386 } else {
387 sirfsoc_uart_pio_tx_chars(sirfport,
388 SIRFSOC_UART_IO_TX_REASONABLE_CNT);
389 if ((uart_circ_empty(xmit)) &&
5df83111
QL		 390 (rd_regl(port, ureg->sirfsoc_tx_fifo_status) &
391 ufifo_st->ff_empty(port->line)))
161e773c
RW		 392 sirfsoc_uart_stop_tx(port);
393 }
394 }
5425e03f 395 spin_unlock(&port->lock);
161e773c
RW		 396 return IRQ_HANDLED;
397}
398
399static void sirfsoc_uart_start_rx(struct uart_port *port)
400{
909102db 401 struct sirfsoc_uart_port *sirfport = to_sirfport(port);
5df83111
QL		 402 struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
403 struct sirfsoc_int_en *uint_en = &sirfport->uart_reg->uart_int_en;
404 unsigned long regv;
909102db 405 if (!sirfport->is_marco) {
5df83111
QL		 406 regv = rd_regl(port, ureg->sirfsoc_int_en_reg);
407 wr_regl(port, ureg->sirfsoc_int_en_reg, regv |
408 SIRFUART_RX_IO_INT_EN(port, uint_en));
409 } else
410 wr_regl(port, ureg->sirfsoc_int_en_reg,
411 SIRFUART_RX_IO_INT_EN(port, uint_en));
412 wr_regl(port, ureg->sirfsoc_rx_fifo_op, SIRFUART_FIFO_RESET);
413 wr_regl(port, ureg->sirfsoc_rx_fifo_op, 0);
414 wr_regl(port, ureg->sirfsoc_rx_fifo_op, SIRFUART_FIFO_START);
415}
416
417static unsigned int
418sirfsoc_usp_calc_sample_div(unsigned long set_rate,
419 unsigned long ioclk_rate, unsigned long *sample_reg)
420{
421 unsigned long min_delta = ~0UL;
422 unsigned short sample_div;
423 unsigned long ioclk_div = 0;
424 unsigned long temp_delta;
425
426 for (sample_div = SIRF_MIN_SAMPLE_DIV;
427 sample_div <= SIRF_MAX_SAMPLE_DIV; sample_div++) {
428 temp_delta = ioclk_rate -
429 (ioclk_rate + (set_rate * sample_div) / 2)
430 / (set_rate * sample_div) * set_rate * sample_div;
909102db 431
5df83111
QL		 432 temp_delta = (temp_delta > 0) ? temp_delta : -temp_delta;
433 if (temp_delta < min_delta) {
434 ioclk_div = (2 * ioclk_rate /
435 (set_rate * sample_div) + 1) / 2 - 1;
436 if (ioclk_div > SIRF_IOCLK_DIV_MAX)
437 continue;
438 min_delta = temp_delta;
439 *sample_reg = sample_div;
440 if (!temp_delta)
441 break;
442 }
443 }
444 return ioclk_div;
161e773c
RW		 445}
446
447static unsigned int
5df83111
QL		 448sirfsoc_uart_calc_sample_div(unsigned long baud_rate,
449 unsigned long ioclk_rate, unsigned long *set_baud)
161e773c
RW		 450{
451 unsigned long min_delta = ~0UL;
452 unsigned short sample_div;
453 unsigned int regv = 0;
454 unsigned long ioclk_div;
455 unsigned long baud_tmp;
456 int temp_delta;
457
458 for (sample_div = SIRF_MIN_SAMPLE_DIV;
459 sample_div <= SIRF_MAX_SAMPLE_DIV; sample_div++) {
460 ioclk_div = (ioclk_rate / (baud_rate * (sample_div + 1))) - 1;
461 if (ioclk_div > SIRF_IOCLK_DIV_MAX)
462 continue;
463 baud_tmp = ioclk_rate / ((ioclk_div + 1) * (sample_div + 1));
464 temp_delta = baud_tmp - baud_rate;
465 temp_delta = (temp_delta > 0) ? temp_delta : -temp_delta;
466 if (temp_delta < min_delta) {
467 regv = regv & (~SIRF_IOCLK_DIV_MASK);
468 regv = regv | ioclk_div;
469 regv = regv & (~SIRF_SAMPLE_DIV_MASK);
470 regv = regv | (sample_div << SIRF_SAMPLE_DIV_SHIFT);
471 min_delta = temp_delta;
5df83111 472 *set_baud = baud_tmp;
161e773c
RW		 473 }
474 }
475 return regv;
476}
477
478static void sirfsoc_uart_set_termios(struct uart_port *port,
479 struct ktermios *termios,
480 struct ktermios *old)
481{
482 struct sirfsoc_uart_port *sirfport = to_sirfport(port);
5df83111
QL		 483 struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
484 struct sirfsoc_int_en *uint_en = &sirfport->uart_reg->uart_int_en;
161e773c
RW		 485 unsigned long config_reg = 0;
486 unsigned long baud_rate;
5df83111 487 unsigned long set_baud;
161e773c
RW		 488 unsigned long flags;
489 unsigned long ic;
490 unsigned int clk_div_reg = 0;
5df83111 491 unsigned long temp_reg_val, ioclk_rate;
161e773c
RW		 492 unsigned long rx_time_out;
493 int threshold_div;
494 int temp;
5df83111
QL		 495 u32 data_bit_len, stop_bit_len, len_val;
496 unsigned long sample_div_reg = 0xf;
497 ioclk_rate = port->uartclk;
161e773c 498
161e773c
RW		 499 switch (termios->c_cflag & CSIZE) {
500 default:
501 case CS8:
5df83111 502 data_bit_len = 8;
161e773c
RW		 503 config_reg |= SIRFUART_DATA_BIT_LEN_8;
504 break;
505 case CS7:
5df83111 506 data_bit_len = 7;
161e773c
RW		 507 config_reg |= SIRFUART_DATA_BIT_LEN_7;
508 break;
509 case CS6:
5df83111 510 data_bit_len = 6;
161e773c
RW		 511 config_reg |= SIRFUART_DATA_BIT_LEN_6;
512 break;
513 case CS5:
5df83111 514 data_bit_len = 5;
161e773c
RW		 515 config_reg |= SIRFUART_DATA_BIT_LEN_5;
516 break;
517 }
5df83111 518 if (termios->c_cflag & CSTOPB) {
161e773c 519 config_reg |= SIRFUART_STOP_BIT_LEN_2;
5df83111
QL		 520 stop_bit_len = 2;
521 } else
522 stop_bit_len = 1;
523
161e773c 524 spin_lock_irqsave(&port->lock, flags);
5df83111 525 port->read_status_mask = uint_en->sirfsoc_rx_oflow_en;
161e773c 526 port->ignore_status_mask = 0;
5df83111
QL		 527 if (sirfport->uart_reg->uart_type == SIRF_REAL_UART) {
528 if (termios->c_iflag & INPCK)
529 port->read_status_mask |= uint_en->sirfsoc_frm_err_en |
530 uint_en->sirfsoc_parity_err_en;
2eb5618d 531 } else {
5df83111
QL		 532 if (termios->c_iflag & INPCK)
533 port->read_status_mask |= uint_en->sirfsoc_frm_err_en;
534 }
161e773c 535 if (termios->c_iflag & (BRKINT | PARMRK))
5df83111
QL		 536 port->read_status_mask |= uint_en->sirfsoc_rxd_brk_en;
537 if (sirfport->uart_reg->uart_type == SIRF_REAL_UART) {
538 if (termios->c_iflag & IGNPAR)
539 port->ignore_status_mask |=
540 uint_en->sirfsoc_frm_err_en |
541 uint_en->sirfsoc_parity_err_en;
542 if (termios->c_cflag & PARENB) {
543 if (termios->c_cflag & CMSPAR) {
544 if (termios->c_cflag & PARODD)
545 config_reg |= SIRFUART_STICK_BIT_MARK;
546 else
547 config_reg |= SIRFUART_STICK_BIT_SPACE;
548 } else if (termios->c_cflag & PARODD) {
549 config_reg |= SIRFUART_STICK_BIT_ODD;
550 } else {
551 config_reg |= SIRFUART_STICK_BIT_EVEN;
552 }
553 }
2eb5618d 554 } else {
5df83111
QL		 555 if (termios->c_iflag & IGNPAR)
556 port->ignore_status_mask |=
557 uint_en->sirfsoc_frm_err_en;
558 if (termios->c_cflag & PARENB)
559 dev_warn(port->dev,
560 "USP-UART not support parity err\n");
561 }
562 if (termios->c_iflag & IGNBRK) {
161e773c 563 port->ignore_status_mask |=
5df83111
QL		 564 uint_en->sirfsoc_rxd_brk_en;
565 if (termios->c_iflag & IGNPAR)
566 port->ignore_status_mask |=
567 uint_en->sirfsoc_rx_oflow_en;
568 }
161e773c
RW		 569 if ((termios->c_cflag & CREAD) == 0)
570 port->ignore_status_mask |= SIRFUART_DUMMY_READ;
161e773c
RW		 571 /* Hardware Flow Control Settings */
572 if (UART_ENABLE_MS(port, termios->c_cflag)) {
573 if (!sirfport->ms_enabled)
574 sirfsoc_uart_enable_ms(port);
575 } else {
576 if (sirfport->ms_enabled)
577 sirfsoc_uart_disable_ms(port);
578 }
5df83111
QL		 579 baud_rate = uart_get_baud_rate(port, termios, old, 0, 4000000);
580 if (ioclk_rate == 150000000) {
ac4ce718
BS		 581 for (ic = 0; ic < SIRF_BAUD_RATE_SUPPORT_NR; ic++)
582 if (baud_rate == baudrate_to_regv[ic].baud_rate)
583 clk_div_reg = baudrate_to_regv[ic].reg_val;
584 }
5df83111
QL		 585 set_baud = baud_rate;
586 if (sirfport->uart_reg->uart_type == SIRF_REAL_UART) {
587 if (unlikely(clk_div_reg == 0))
588 clk_div_reg = sirfsoc_uart_calc_sample_div(baud_rate,
589 ioclk_rate, &set_baud);
590 wr_regl(port, ureg->sirfsoc_divisor, clk_div_reg);
2eb5618d 591 } else {
5df83111
QL		 592 clk_div_reg = sirfsoc_usp_calc_sample_div(baud_rate,
593 ioclk_rate, &sample_div_reg);
594 sample_div_reg--;
595 set_baud = ((ioclk_rate / (clk_div_reg+1) - 1) /
596 (sample_div_reg + 1));
597 /* setting usp mode 2 */
598 len_val = ((1 << 0) | (1 << 8));
599 len_val |= ((clk_div_reg & 0x3ff) << 21);
600 wr_regl(port, ureg->sirfsoc_mode2,
601 len_val);
ac4ce718 602
5df83111 603 }
161e773c 604 if (tty_termios_baud_rate(termios))
5df83111
QL		 605 tty_termios_encode_baud_rate(termios, set_baud, set_baud);
606 /* set receive timeout && data bits len */
607 rx_time_out = SIRFSOC_UART_RX_TIMEOUT(set_baud, 20000);
608 rx_time_out = SIRFUART_RECV_TIMEOUT_VALUE(rx_time_out);
609 temp_reg_val = rd_regl(port, ureg->sirfsoc_tx_fifo_op);
610 wr_regl(port, ureg->sirfsoc_rx_fifo_op, 0);
611 wr_regl(port, ureg->sirfsoc_tx_fifo_op,
612 (temp_reg_val & ~SIRFUART_FIFO_START));
613 if (sirfport->uart_reg->uart_type == SIRF_REAL_UART) {
614 config_reg |= SIRFUART_RECV_TIMEOUT(port, rx_time_out);
615 wr_regl(port, ureg->sirfsoc_line_ctrl, config_reg);
2eb5618d 616 } else {
5df83111
QL		 617 /*tx frame ctrl*/
618 len_val = (data_bit_len - 1) << 0;
619 len_val |= (data_bit_len + 1 + stop_bit_len - 1) << 16;
620 len_val |= ((data_bit_len - 1) << 24);
621 len_val |= (((clk_div_reg & 0xc00) >> 10) << 30);
622 wr_regl(port, ureg->sirfsoc_tx_frame_ctrl, len_val);
623 /*rx frame ctrl*/
624 len_val = (data_bit_len - 1) << 0;
625 len_val |= (data_bit_len + 1 + stop_bit_len - 1) << 8;
626 len_val |= (data_bit_len - 1) << 16;
627 len_val |= (((clk_div_reg & 0xf000) >> 12) << 24);
628 wr_regl(port, ureg->sirfsoc_rx_frame_ctrl, len_val);
629 /*async param*/
630 wr_regl(port, ureg->sirfsoc_async_param_reg,
631 (SIRFUART_RECV_TIMEOUT(port, rx_time_out)) |
632 (sample_div_reg & 0x3f) << 16);
633 }
634 wr_regl(port, ureg->sirfsoc_tx_dma_io_ctrl, SIRFUART_IO_MODE);
635 wr_regl(port, ureg->sirfsoc_rx_dma_io_ctrl, SIRFUART_IO_MODE);
161e773c 636 /* Reset Rx/Tx FIFO Threshold level for proper baudrate */
5df83111 637 if (set_baud < 1000000)
161e773c
RW		 638 threshold_div = 1;
639 else
640 threshold_div = 2;
5df83111
QL		 641 temp = SIRFUART_FIFO_THD(port);
642 wr_regl(port, ureg->sirfsoc_tx_fifo_ctrl, temp / threshold_div);
643 wr_regl(port, ureg->sirfsoc_rx_fifo_ctrl, temp / threshold_div);
644 temp_reg_val |= SIRFUART_FIFO_START;
645 wr_regl(port, ureg->sirfsoc_tx_fifo_op, temp_reg_val);
646 uart_update_timeout(port, termios->c_cflag, set_baud);
161e773c 647 sirfsoc_uart_start_rx(port);
5df83111 648 wr_regl(port, ureg->sirfsoc_tx_rx_en, SIRFUART_TX_EN | SIRFUART_RX_EN);
161e773c
RW		 649 spin_unlock_irqrestore(&port->lock, flags);
650}
651
652static void startup_uart_controller(struct uart_port *port)
653{
5df83111
QL		 654 struct sirfsoc_uart_port *sirfport = to_sirfport(port);
655 struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
161e773c
RW		 656 unsigned long temp_regv;
657 int temp;
5df83111
QL		 658 temp_regv = rd_regl(port, ureg->sirfsoc_tx_dma_io_ctrl);
659 wr_regl(port, ureg->sirfsoc_tx_dma_io_ctrl, temp_regv |
660 SIRFUART_IO_MODE);
661 temp_regv = rd_regl(port, ureg->sirfsoc_rx_dma_io_ctrl);
662 wr_regl(port, ureg->sirfsoc_rx_dma_io_ctrl, temp_regv |
663 SIRFUART_IO_MODE);
664 wr_regl(port, ureg->sirfsoc_tx_dma_io_len, 0);
665 wr_regl(port, ureg->sirfsoc_rx_dma_io_len, 0);
666 wr_regl(port, ureg->sirfsoc_tx_rx_en, SIRFUART_RX_EN | SIRFUART_TX_EN);
667 if (sirfport->uart_reg->uart_type == SIRF_USP_UART)
668 wr_regl(port, ureg->sirfsoc_mode1,
669 SIRFSOC_USP_ENDIAN_CTRL_LSBF |
670 SIRFSOC_USP_EN);
671 wr_regl(port, ureg->sirfsoc_tx_fifo_op, SIRFUART_FIFO_RESET);
672 wr_regl(port, ureg->sirfsoc_tx_fifo_op, 0);
673 wr_regl(port, ureg->sirfsoc_rx_fifo_op, SIRFUART_FIFO_RESET);
674 wr_regl(port, ureg->sirfsoc_rx_fifo_op, 0);
675 temp = SIRFUART_FIFO_THD(port);
676 wr_regl(port, ureg->sirfsoc_tx_fifo_ctrl, temp);
677 wr_regl(port, ureg->sirfsoc_rx_fifo_ctrl, temp);
161e773c
RW		 678}
679
680static int sirfsoc_uart_startup(struct uart_port *port)
681{
682 struct sirfsoc_uart_port *sirfport = to_sirfport(port);
683 unsigned int index = port->line;
684 int ret;
685 set_irq_flags(port->irq, IRQF_VALID | IRQF_NOAUTOEN);
686 ret = request_irq(port->irq,
687 sirfsoc_uart_isr,
688 0,
689 SIRFUART_PORT_NAME,
690 sirfport);
691 if (ret != 0) {
692 dev_err(port->dev, "UART%d request IRQ line (%d) failed.\n",
693 index, port->irq);
694 goto irq_err;
695 }
696 startup_uart_controller(port);
2eb5618d
QL		 697
698 sirfport->ms_enabled = false;
699 if (sirfport->uart_reg->uart_type == SIRF_USP_UART &&
700 sirfport->hw_flow_ctrl) {
701 set_irq_flags(gpio_to_irq(sirfport->cts_gpio),
702 IRQF_VALID | IRQF_NOAUTOEN);
703 ret = request_irq(gpio_to_irq(sirfport->cts_gpio),
704 sirfsoc_uart_usp_cts_handler, IRQF_TRIGGER_FALLING |
705 IRQF_TRIGGER_RISING, "usp_cts_irq", sirfport);
706 if (ret != 0) {
707 dev_err(port->dev, "UART-USP:request gpio irq fail\n");
708 goto init_rx_err;
709 }
710 }
711
161e773c 712 enable_irq(port->irq);
2eb5618d
QL		 713
714init_rx_err:
715 free_irq(port->irq, sirfport);
161e773c
RW		 716irq_err:
717 return ret;
718}
719
720static void sirfsoc_uart_shutdown(struct uart_port *port)
721{
722 struct sirfsoc_uart_port *sirfport = to_sirfport(port);
5df83111 723 struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
909102db 724 if (!sirfport->is_marco)
5df83111 725 wr_regl(port, ureg->sirfsoc_int_en_reg, 0);
909102db
BS		 726 else
727 wr_regl(port, SIRFUART_INT_EN_CLR, ~0UL);
728
161e773c 729 free_irq(port->irq, sirfport);
2eb5618d 730 if (sirfport->ms_enabled)
161e773c 731 sirfsoc_uart_disable_ms(port);
2eb5618d
QL		 732 if (sirfport->uart_reg->uart_type == SIRF_USP_UART &&
733 sirfport->hw_flow_ctrl) {
734 gpio_set_value(sirfport->rts_gpio, 1);
735 free_irq(gpio_to_irq(sirfport->cts_gpio), sirfport);
161e773c
RW		 736 }
737}
738
739static const char *sirfsoc_uart_type(struct uart_port *port)
740{
741 return port->type == SIRFSOC_PORT_TYPE ? SIRFUART_PORT_NAME : NULL;
742}
743
744static int sirfsoc_uart_request_port(struct uart_port *port)
745{
5df83111
QL		 746 struct sirfsoc_uart_port *sirfport = to_sirfport(port);
747 struct sirfsoc_uart_param *uart_param = &sirfport->uart_reg->uart_param;
161e773c
RW		 748 void *ret;
749 ret = request_mem_region(port->mapbase,
5df83111 750 SIRFUART_MAP_SIZE, uart_param->port_name);
161e773c
RW		 751 return ret ? 0 : -EBUSY;
752}
753
754static void sirfsoc_uart_release_port(struct uart_port *port)
755{
756 release_mem_region(port->mapbase, SIRFUART_MAP_SIZE);
757}
758
759static void sirfsoc_uart_config_port(struct uart_port *port, int flags)
760{
761 if (flags & UART_CONFIG_TYPE) {
762 port->type = SIRFSOC_PORT_TYPE;
763 sirfsoc_uart_request_port(port);
764 }
765}
766
767static struct uart_ops sirfsoc_uart_ops = {
768 .tx_empty = sirfsoc_uart_tx_empty,
769 .get_mctrl = sirfsoc_uart_get_mctrl,
770 .set_mctrl = sirfsoc_uart_set_mctrl,
771 .stop_tx = sirfsoc_uart_stop_tx,
772 .start_tx = sirfsoc_uart_start_tx,
773 .stop_rx = sirfsoc_uart_stop_rx,
774 .enable_ms = sirfsoc_uart_enable_ms,
775 .break_ctl = sirfsoc_uart_break_ctl,
776 .startup = sirfsoc_uart_startup,
777 .shutdown = sirfsoc_uart_shutdown,
778 .set_termios = sirfsoc_uart_set_termios,
779 .type = sirfsoc_uart_type,
780 .release_port = sirfsoc_uart_release_port,
781 .request_port = sirfsoc_uart_request_port,
782 .config_port = sirfsoc_uart_config_port,
783};
784
785#ifdef CONFIG_SERIAL_SIRFSOC_CONSOLE
5df83111
QL		 786static int __init
787sirfsoc_uart_console_setup(struct console *co, char *options)
161e773c
RW		 788{
789 unsigned int baud = 115200;
790 unsigned int bits = 8;
791 unsigned int parity = 'n';
792 unsigned int flow = 'n';
793 struct uart_port *port = &sirfsoc_uart_ports[co->index].port;
5df83111
QL		 794 struct sirfsoc_uart_port *sirfport = to_sirfport(port);
795 struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
161e773c
RW		 796 if (co->index < 0 || co->index >= SIRFSOC_UART_NR)
797 return -EINVAL;
798
799 if (!port->mapbase)
800 return -ENODEV;
801
5df83111
QL		 802 /* enable usp in mode1 register */
803 if (sirfport->uart_reg->uart_type == SIRF_USP_UART)
804 wr_regl(port, ureg->sirfsoc_mode1, SIRFSOC_USP_EN |
805 SIRFSOC_USP_ENDIAN_CTRL_LSBF);
161e773c
RW		 806 if (options)
807 uart_parse_options(options, &baud, &parity, &bits, &flow);
808 port->cons = co;
5df83111 809
161e773c
RW		 810 return uart_set_options(port, co, baud, parity, bits, flow);
811}
812
813static void sirfsoc_uart_console_putchar(struct uart_port *port, int ch)
814{
5df83111
QL		 815 struct sirfsoc_uart_port *sirfport = to_sirfport(port);
816 struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
817 struct sirfsoc_fifo_status *ufifo_st = &sirfport->uart_reg->fifo_status;
161e773c 818 while (rd_regl(port,
5df83111 819 ureg->sirfsoc_tx_fifo_status) & ufifo_st->ff_full(port->line))
161e773c 820 cpu_relax();
5df83111 821 wr_regb(port, ureg->sirfsoc_tx_fifo_data, ch);
161e773c
RW		 822}
823
824static void sirfsoc_uart_console_write(struct console *co, const char *s,
825 unsigned int count)
826{
827 struct uart_port *port = &sirfsoc_uart_ports[co->index].port;
828 uart_console_write(port, s, count, sirfsoc_uart_console_putchar);
829}
830
831static struct console sirfsoc_uart_console = {
832 .name = SIRFSOC_UART_NAME,
833 .device = uart_console_device,
834 .flags = CON_PRINTBUFFER,
835 .index = -1,
836 .write = sirfsoc_uart_console_write,
837 .setup = sirfsoc_uart_console_setup,
838 .data = &sirfsoc_uart_drv,
839};
840
841static int __init sirfsoc_uart_console_init(void)
842{
843 register_console(&sirfsoc_uart_console);
844 return 0;
845}
846console_initcall(sirfsoc_uart_console_init);
847#endif
848
849static struct uart_driver sirfsoc_uart_drv = {
850 .owner = THIS_MODULE,
851 .driver_name = SIRFUART_PORT_NAME,
852 .nr = SIRFSOC_UART_NR,
853 .dev_name = SIRFSOC_UART_NAME,
854 .major = SIRFSOC_UART_MAJOR,
855 .minor = SIRFSOC_UART_MINOR,
856#ifdef CONFIG_SERIAL_SIRFSOC_CONSOLE
857 .cons = &sirfsoc_uart_console,
858#else
859 .cons = NULL,
860#endif
861};
862
5df83111
QL		 863static struct of_device_id sirfsoc_uart_ids[] = {
864 { .compatible = "sirf,prima2-uart", .data = &sirfsoc_uart,},
865 { .compatible = "sirf,marco-uart", .data = &sirfsoc_uart},
866 { .compatible = "sirf,prima2-usp-uart", .data = &sirfsoc_usp},
867 {}
868};
869MODULE_DEVICE_TABLE(of, sirfsoc_uart_ids);
870
ada1f443 871static int sirfsoc_uart_probe(struct platform_device *pdev)
161e773c
RW		 872{
873 struct sirfsoc_uart_port *sirfport;
874 struct uart_port *port;
875 struct resource *res;
876 int ret;
5df83111 877 const struct of_device_id *match;
161e773c 878
5df83111 879 match = of_match_node(sirfsoc_uart_ids, pdev->dev.of_node);
161e773c
RW		 880 if (of_property_read_u32(pdev->dev.of_node, "cell-index", &pdev->id)) {
881 dev_err(&pdev->dev,
882 "Unable to find cell-index in uart node.\n");
883 ret = -EFAULT;
884 goto err;
885 }
5df83111
QL		 886 if (of_device_is_compatible(pdev->dev.of_node, "sirf,prima2-usp-uart"))
887 pdev->id += ((struct sirfsoc_uart_register *)
888 match->data)->uart_param.register_uart_nr;
161e773c
RW		 889 sirfport = &sirfsoc_uart_ports[pdev->id];
890 port = &sirfport->port;
891 port->dev = &pdev->dev;
892 port->private_data = sirfport;
5df83111 893 sirfport->uart_reg = (struct sirfsoc_uart_register *)match->data;
161e773c 894
2eb5618d
QL		 895 sirfport->hw_flow_ctrl = of_property_read_bool(pdev->dev.of_node,
896 "sirf,uart-has-rtscts");
5df83111
QL		 897 if (of_device_is_compatible(pdev->dev.of_node, "sirf,prima2-uart"))
898 sirfport->uart_reg->uart_type = SIRF_REAL_UART;
2eb5618d 899 if (of_device_is_compatible(pdev->dev.of_node, "sirf,prima2-usp-uart")) {
5df83111 900 sirfport->uart_reg->uart_type = SIRF_USP_UART;
2eb5618d
QL		 901 if (!sirfport->hw_flow_ctrl)
902 goto usp_no_flow_control;
903 if (of_find_property(pdev->dev.of_node, "cts-gpios", NULL))
904 sirfport->cts_gpio = of_get_named_gpio(
905 pdev->dev.of_node, "cts-gpios", 0);
906 else
907 sirfport->cts_gpio = -1;
908 if (of_find_property(pdev->dev.of_node, "rts-gpios", NULL))
909 sirfport->rts_gpio = of_get_named_gpio(
910 pdev->dev.of_node, "rts-gpios", 0);
911 else
912 sirfport->rts_gpio = -1;
913
914 if ((!gpio_is_valid(sirfport->cts_gpio) ||
915 !gpio_is_valid(sirfport->rts_gpio))) {
916 ret = -EINVAL;
917 dev_err(&pdev->dev,
67bc306c 918 "Usp flow control must have cts and rts gpio");
2eb5618d
QL		 919 goto err;
920 }
921 ret = devm_gpio_request(&pdev->dev, sirfport->cts_gpio,
67bc306c 922 "usp-cts-gpio");
2eb5618d 923 if (ret) {
67bc306c 924 dev_err(&pdev->dev, "Unable request cts gpio");
2eb5618d
QL		 925 goto err;
926 }
927 gpio_direction_input(sirfport->cts_gpio);
928 ret = devm_gpio_request(&pdev->dev, sirfport->rts_gpio,
67bc306c 929 "usp-rts-gpio");
2eb5618d 930 if (ret) {
67bc306c 931 dev_err(&pdev->dev, "Unable request rts gpio");
2eb5618d
QL		 932 goto err;
933 }
934 gpio_direction_output(sirfport->rts_gpio, 1);
935 }
936usp_no_flow_control:
909102db
BS		 937 if (of_device_is_compatible(pdev->dev.of_node, "sirf,marco-uart"))
938 sirfport->is_marco = true;
939
161e773c
RW		 940 if (of_property_read_u32(pdev->dev.of_node,
941 "fifosize",
942 &port->fifosize)) {
943 dev_err(&pdev->dev,
944 "Unable to find fifosize in uart node.\n");
945 ret = -EFAULT;
946 goto err;
947 }
948
949 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
950 if (res == NULL) {
951 dev_err(&pdev->dev, "Insufficient resources.\n");
952 ret = -EFAULT;
953 goto err;
954 }
955 port->mapbase = res->start;
956 port->membase = devm_ioremap(&pdev->dev, res->start, resource_size(res));
957 if (!port->membase) {
958 dev_err(&pdev->dev, "Cannot remap resource.\n");
959 ret = -ENOMEM;
960 goto err;
961 }
962 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
963 if (res == NULL) {
964 dev_err(&pdev->dev, "Insufficient resources.\n");
965 ret = -EFAULT;
9250dd57 966 goto err;
161e773c
RW		 967 }
968 port->irq = res->start;
969
ac4ce718
BS		 970 sirfport->clk = clk_get(&pdev->dev, NULL);
971 if (IS_ERR(sirfport->clk)) {
972 ret = PTR_ERR(sirfport->clk);
a343756e 973 goto err;
ac4ce718
BS		 974 }
975 clk_prepare_enable(sirfport->clk);
976 port->uartclk = clk_get_rate(sirfport->clk);
977
161e773c
RW		 978 port->ops = &sirfsoc_uart_ops;
979 spin_lock_init(&port->lock);
980
981 platform_set_drvdata(pdev, sirfport);
982 ret = uart_add_one_port(&sirfsoc_uart_drv, port);
983 if (ret != 0) {
984 dev_err(&pdev->dev, "Cannot add UART port(%d).\n", pdev->id);
985 goto port_err;
986 }
987
988 return 0;
989
990port_err:
ac4ce718
BS		 991 clk_disable_unprepare(sirfport->clk);
992 clk_put(sirfport->clk);
161e773c
RW		 993err:
994 return ret;
995}
996
997static int sirfsoc_uart_remove(struct platform_device *pdev)
998{
999 struct sirfsoc_uart_port *sirfport = platform_get_drvdata(pdev);
1000 struct uart_port *port = &sirfport->port;
ac4ce718
BS		 1001 clk_disable_unprepare(sirfport->clk);
1002 clk_put(sirfport->clk);
161e773c
RW		 1003 uart_remove_one_port(&sirfsoc_uart_drv, port);
1004 return 0;
1005}
1006
1007static int
1008sirfsoc_uart_suspend(struct platform_device *pdev, pm_message_t state)
1009{
1010 struct sirfsoc_uart_port *sirfport = platform_get_drvdata(pdev);
1011 struct uart_port *port = &sirfport->port;
1012 uart_suspend_port(&sirfsoc_uart_drv, port);
1013 return 0;
1014}
1015
1016static int sirfsoc_uart_resume(struct platform_device *pdev)
1017{
1018 struct sirfsoc_uart_port *sirfport = platform_get_drvdata(pdev);
1019 struct uart_port *port = &sirfport->port;
1020 uart_resume_port(&sirfsoc_uart_drv, port);
1021 return 0;
1022}
1023
161e773c
RW		 1024static struct platform_driver sirfsoc_uart_driver = {
1025 .probe = sirfsoc_uart_probe,
2d47b716 1026 .remove = sirfsoc_uart_remove,
161e773c
RW		 1027 .suspend = sirfsoc_uart_suspend,
1028 .resume = sirfsoc_uart_resume,
1029 .driver = {
1030 .name = SIRFUART_PORT_NAME,
1031 .owner = THIS_MODULE,
1032 .of_match_table = sirfsoc_uart_ids,
1033 },
1034};
1035
1036static int __init sirfsoc_uart_init(void)
1037{
1038 int ret = 0;
1039
1040 ret = uart_register_driver(&sirfsoc_uart_drv);
1041 if (ret)
1042 goto out;
1043
1044 ret = platform_driver_register(&sirfsoc_uart_driver);
1045 if (ret)
1046 uart_unregister_driver(&sirfsoc_uart_drv);
1047out:
1048 return ret;
1049}
1050module_init(sirfsoc_uart_init);
1051
1052static void __exit sirfsoc_uart_exit(void)
1053{
1054 platform_driver_unregister(&sirfsoc_uart_driver);
1055 uart_unregister_driver(&sirfsoc_uart_drv);
1056}
1057module_exit(sirfsoc_uart_exit);
1058
1059MODULE_LICENSE("GPL v2");
1060MODULE_AUTHOR("Bin Shi <Bin.Shi@csr.com>, Rong Wang<Rong.Wang@csr.com>");
1061MODULE_DESCRIPTION("CSR SiRFprimaII Uart Driver");
Linux 6.x block layer and io_uring tree(s)