Commit | Line | Data |
---|---|---|
161e773c RW |
1 | /* |
2 | * Driver for CSR SiRFprimaII onboard UARTs. | |
3 | * | |
4 | * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company. | |
5 | * | |
6 | * Licensed under GPLv2 or later. | |
7 | */ | |
8 | ||
9 | #include <linux/module.h> | |
10 | #include <linux/ioport.h> | |
11 | #include <linux/platform_device.h> | |
12 | #include <linux/init.h> | |
13 | #include <linux/sysrq.h> | |
14 | #include <linux/console.h> | |
15 | #include <linux/tty.h> | |
16 | #include <linux/tty_flip.h> | |
17 | #include <linux/serial_core.h> | |
18 | #include <linux/serial.h> | |
19 | #include <linux/clk.h> | |
20 | #include <linux/of.h> | |
21 | #include <linux/slab.h> | |
22 | #include <linux/io.h> | |
2eb5618d | 23 | #include <linux/of_gpio.h> |
8316d04c QL |
24 | #include <linux/dmaengine.h> |
25 | #include <linux/dma-direction.h> | |
26 | #include <linux/dma-mapping.h> | |
161e773c RW |
27 | #include <asm/irq.h> |
28 | #include <asm/mach/irq.h> | |
161e773c RW |
29 | |
30 | #include "sirfsoc_uart.h" | |
31 | ||
32 | static unsigned int | |
33 | sirfsoc_uart_pio_tx_chars(struct sirfsoc_uart_port *sirfport, int count); | |
34 | static unsigned int | |
35 | sirfsoc_uart_pio_rx_chars(struct uart_port *port, unsigned int max_rx_count); | |
36 | static struct uart_driver sirfsoc_uart_drv; | |
37 | ||
8316d04c | 38 | static void sirfsoc_uart_tx_dma_complete_callback(void *param); |
161e773c RW |
39 | static const struct sirfsoc_baudrate_to_regv baudrate_to_regv[] = { |
40 | {4000000, 2359296}, | |
41 | {3500000, 1310721}, | |
42 | {3000000, 1572865}, | |
43 | {2500000, 1245186}, | |
44 | {2000000, 1572866}, | |
45 | {1500000, 1245188}, | |
46 | {1152000, 1638404}, | |
47 | {1000000, 1572869}, | |
48 | {921600, 1114120}, | |
49 | {576000, 1245196}, | |
50 | {500000, 1245198}, | |
51 | {460800, 1572876}, | |
52 | {230400, 1310750}, | |
53 | {115200, 1310781}, | |
54 | {57600, 1310843}, | |
55 | {38400, 1114328}, | |
56 | {19200, 1114545}, | |
57 | {9600, 1114979}, | |
58 | }; | |
59 | ||
a6ffe896 | 60 | static struct sirfsoc_uart_port *sirf_ports[SIRFSOC_UART_NR]; |
161e773c RW |
61 | |
62 | static inline struct sirfsoc_uart_port *to_sirfport(struct uart_port *port) | |
63 | { | |
64 | return container_of(port, struct sirfsoc_uart_port, port); | |
65 | } | |
66 | ||
67 | static inline unsigned int sirfsoc_uart_tx_empty(struct uart_port *port) | |
68 | { | |
69 | unsigned long reg; | |
5df83111 QL |
70 | struct sirfsoc_uart_port *sirfport = to_sirfport(port); |
71 | struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg; | |
72 | struct sirfsoc_fifo_status *ufifo_st = &sirfport->uart_reg->fifo_status; | |
73 | reg = rd_regl(port, ureg->sirfsoc_tx_fifo_status); | |
cb4595a2 | 74 | return (reg & ufifo_st->ff_empty(port)) ? TIOCSER_TEMT : 0; |
161e773c RW |
75 | } |
76 | ||
77 | static unsigned int sirfsoc_uart_get_mctrl(struct uart_port *port) | |
78 | { | |
79 | struct sirfsoc_uart_port *sirfport = to_sirfport(port); | |
5df83111 | 80 | struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg; |
2eb5618d | 81 | if (!sirfport->hw_flow_ctrl || !sirfport->ms_enabled) |
161e773c | 82 | goto cts_asserted; |
2eb5618d | 83 | if (sirfport->uart_reg->uart_type == SIRF_REAL_UART) { |
5df83111 QL |
84 | if (!(rd_regl(port, ureg->sirfsoc_afc_ctrl) & |
85 | SIRFUART_AFC_CTS_STATUS)) | |
161e773c RW |
86 | goto cts_asserted; |
87 | else | |
88 | goto cts_deasserted; | |
2eb5618d QL |
89 | } else { |
90 | if (!gpio_get_value(sirfport->cts_gpio)) | |
91 | goto cts_asserted; | |
92 | else | |
93 | goto cts_deasserted; | |
161e773c RW |
94 | } |
95 | cts_deasserted: | |
96 | return TIOCM_CAR | TIOCM_DSR; | |
97 | cts_asserted: | |
98 | return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS; | |
99 | } | |
100 | ||
101 | static void sirfsoc_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) | |
102 | { | |
103 | struct sirfsoc_uart_port *sirfport = to_sirfport(port); | |
5df83111 | 104 | struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg; |
161e773c RW |
105 | unsigned int assert = mctrl & TIOCM_RTS; |
106 | unsigned int val = assert ? SIRFUART_AFC_CTRL_RX_THD : 0x0; | |
107 | unsigned int current_val; | |
2eb5618d | 108 | |
7f60f2fe QL |
109 | if (mctrl & TIOCM_LOOP) { |
110 | if (sirfport->uart_reg->uart_type == SIRF_REAL_UART) | |
111 | wr_regl(port, ureg->sirfsoc_line_ctrl, | |
112 | rd_regl(port, ureg->sirfsoc_line_ctrl) | | |
113 | SIRFUART_LOOP_BACK); | |
114 | else | |
115 | wr_regl(port, ureg->sirfsoc_mode1, | |
116 | rd_regl(port, ureg->sirfsoc_mode1) | | |
117 | SIRFSOC_USP_LOOP_BACK_CTRL); | |
118 | } else { | |
119 | if (sirfport->uart_reg->uart_type == SIRF_REAL_UART) | |
120 | wr_regl(port, ureg->sirfsoc_line_ctrl, | |
121 | rd_regl(port, ureg->sirfsoc_line_ctrl) & | |
122 | ~SIRFUART_LOOP_BACK); | |
123 | else | |
124 | wr_regl(port, ureg->sirfsoc_mode1, | |
125 | rd_regl(port, ureg->sirfsoc_mode1) & | |
126 | ~SIRFSOC_USP_LOOP_BACK_CTRL); | |
127 | } | |
128 | ||
2eb5618d QL |
129 | if (!sirfport->hw_flow_ctrl || !sirfport->ms_enabled) |
130 | return; | |
131 | if (sirfport->uart_reg->uart_type == SIRF_REAL_UART) { | |
5df83111 | 132 | current_val = rd_regl(port, ureg->sirfsoc_afc_ctrl) & ~0xFF; |
161e773c | 133 | val |= current_val; |
5df83111 | 134 | wr_regl(port, ureg->sirfsoc_afc_ctrl, val); |
2eb5618d QL |
135 | } else { |
136 | if (!val) | |
137 | gpio_set_value(sirfport->rts_gpio, 1); | |
138 | else | |
139 | gpio_set_value(sirfport->rts_gpio, 0); | |
161e773c RW |
140 | } |
141 | } | |
142 | ||
143 | static void sirfsoc_uart_stop_tx(struct uart_port *port) | |
144 | { | |
909102db | 145 | struct sirfsoc_uart_port *sirfport = to_sirfport(port); |
5df83111 QL |
146 | struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg; |
147 | struct sirfsoc_int_en *uint_en = &sirfport->uart_reg->uart_int_en; | |
909102db | 148 | |
9be16b38 | 149 | if (sirfport->tx_dma_chan) { |
8316d04c QL |
150 | if (sirfport->tx_dma_state == TX_DMA_RUNNING) { |
151 | dmaengine_pause(sirfport->tx_dma_chan); | |
152 | sirfport->tx_dma_state = TX_DMA_PAUSE; | |
153 | } else { | |
057badd6 | 154 | if (!sirfport->is_atlas7) |
8316d04c QL |
155 | wr_regl(port, ureg->sirfsoc_int_en_reg, |
156 | rd_regl(port, ureg->sirfsoc_int_en_reg) & | |
157 | ~uint_en->sirfsoc_txfifo_empty_en); | |
158 | else | |
c1b7ac6f | 159 | wr_regl(port, ureg->sirfsoc_int_en_clr_reg, |
8316d04c QL |
160 | uint_en->sirfsoc_txfifo_empty_en); |
161 | } | |
162 | } else { | |
c1b7ac6f QL |
163 | if (sirfport->uart_reg->uart_type == SIRF_USP_UART) |
164 | wr_regl(port, ureg->sirfsoc_tx_rx_en, rd_regl(port, | |
165 | ureg->sirfsoc_tx_rx_en) & ~SIRFUART_TX_EN); | |
057badd6 | 166 | if (!sirfport->is_atlas7) |
8316d04c QL |
167 | wr_regl(port, ureg->sirfsoc_int_en_reg, |
168 | rd_regl(port, ureg->sirfsoc_int_en_reg) & | |
169 | ~uint_en->sirfsoc_txfifo_empty_en); | |
170 | else | |
c1b7ac6f | 171 | wr_regl(port, ureg->sirfsoc_int_en_clr_reg, |
8316d04c QL |
172 | uint_en->sirfsoc_txfifo_empty_en); |
173 | } | |
174 | } | |
175 | ||
176 | static void sirfsoc_uart_tx_with_dma(struct sirfsoc_uart_port *sirfport) | |
177 | { | |
178 | struct uart_port *port = &sirfport->port; | |
179 | struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg; | |
180 | struct sirfsoc_int_en *uint_en = &sirfport->uart_reg->uart_int_en; | |
181 | struct circ_buf *xmit = &port->state->xmit; | |
182 | unsigned long tran_size; | |
183 | unsigned long tran_start; | |
184 | unsigned long pio_tx_size; | |
185 | ||
186 | tran_size = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE); | |
187 | tran_start = (unsigned long)(xmit->buf + xmit->tail); | |
188 | if (uart_circ_empty(xmit) || uart_tx_stopped(port) || | |
189 | !tran_size) | |
190 | return; | |
191 | if (sirfport->tx_dma_state == TX_DMA_PAUSE) { | |
192 | dmaengine_resume(sirfport->tx_dma_chan); | |
193 | return; | |
194 | } | |
195 | if (sirfport->tx_dma_state == TX_DMA_RUNNING) | |
196 | return; | |
057badd6 | 197 | if (!sirfport->is_atlas7) |
5df83111 | 198 | wr_regl(port, ureg->sirfsoc_int_en_reg, |
8316d04c QL |
199 | rd_regl(port, ureg->sirfsoc_int_en_reg)& |
200 | ~(uint_en->sirfsoc_txfifo_empty_en)); | |
201 | else | |
c1b7ac6f | 202 | wr_regl(port, ureg->sirfsoc_int_en_clr_reg, |
5df83111 | 203 | uint_en->sirfsoc_txfifo_empty_en); |
8316d04c QL |
204 | /* |
205 | * DMA requires buffer address and buffer length are both aligned with | |
206 | * 4 bytes, so we use PIO for | |
207 | * 1. if address is not aligned with 4bytes, use PIO for the first 1~3 | |
208 | * bytes, and move to DMA for the left part aligned with 4bytes | |
209 | * 2. if buffer length is not aligned with 4bytes, use DMA for aligned | |
210 | * part first, move to PIO for the left 1~3 bytes | |
211 | */ | |
212 | if (tran_size < 4 || BYTES_TO_ALIGN(tran_start)) { | |
213 | wr_regl(port, ureg->sirfsoc_tx_fifo_op, SIRFUART_FIFO_STOP); | |
214 | wr_regl(port, ureg->sirfsoc_tx_dma_io_ctrl, | |
215 | rd_regl(port, ureg->sirfsoc_tx_dma_io_ctrl)| | |
216 | SIRFUART_IO_MODE); | |
217 | if (BYTES_TO_ALIGN(tran_start)) { | |
218 | pio_tx_size = sirfsoc_uart_pio_tx_chars(sirfport, | |
219 | BYTES_TO_ALIGN(tran_start)); | |
220 | tran_size -= pio_tx_size; | |
221 | } | |
222 | if (tran_size < 4) | |
223 | sirfsoc_uart_pio_tx_chars(sirfport, tran_size); | |
057badd6 | 224 | if (!sirfport->is_atlas7) |
8316d04c QL |
225 | wr_regl(port, ureg->sirfsoc_int_en_reg, |
226 | rd_regl(port, ureg->sirfsoc_int_en_reg)| | |
227 | uint_en->sirfsoc_txfifo_empty_en); | |
228 | else | |
229 | wr_regl(port, ureg->sirfsoc_int_en_reg, | |
230 | uint_en->sirfsoc_txfifo_empty_en); | |
231 | wr_regl(port, ureg->sirfsoc_tx_fifo_op, SIRFUART_FIFO_START); | |
232 | } else { | |
233 | /* tx transfer mode switch into dma mode */ | |
234 | wr_regl(port, ureg->sirfsoc_tx_fifo_op, SIRFUART_FIFO_STOP); | |
235 | wr_regl(port, ureg->sirfsoc_tx_dma_io_ctrl, | |
236 | rd_regl(port, ureg->sirfsoc_tx_dma_io_ctrl)& | |
237 | ~SIRFUART_IO_MODE); | |
238 | wr_regl(port, ureg->sirfsoc_tx_fifo_op, SIRFUART_FIFO_START); | |
239 | tran_size &= ~(0x3); | |
240 | ||
241 | sirfport->tx_dma_addr = dma_map_single(port->dev, | |
242 | xmit->buf + xmit->tail, | |
243 | tran_size, DMA_TO_DEVICE); | |
244 | sirfport->tx_dma_desc = dmaengine_prep_slave_single( | |
245 | sirfport->tx_dma_chan, sirfport->tx_dma_addr, | |
246 | tran_size, DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT); | |
247 | if (!sirfport->tx_dma_desc) { | |
248 | dev_err(port->dev, "DMA prep slave single fail\n"); | |
249 | return; | |
250 | } | |
251 | sirfport->tx_dma_desc->callback = | |
252 | sirfsoc_uart_tx_dma_complete_callback; | |
253 | sirfport->tx_dma_desc->callback_param = (void *)sirfport; | |
254 | sirfport->transfer_size = tran_size; | |
255 | ||
256 | dmaengine_submit(sirfport->tx_dma_desc); | |
257 | dma_async_issue_pending(sirfport->tx_dma_chan); | |
258 | sirfport->tx_dma_state = TX_DMA_RUNNING; | |
259 | } | |
161e773c RW |
260 | } |
261 | ||
ada1f443 | 262 | static void sirfsoc_uart_start_tx(struct uart_port *port) |
161e773c RW |
263 | { |
264 | struct sirfsoc_uart_port *sirfport = to_sirfport(port); | |
5df83111 QL |
265 | struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg; |
266 | struct sirfsoc_int_en *uint_en = &sirfport->uart_reg->uart_int_en; | |
9be16b38 | 267 | if (sirfport->tx_dma_chan) |
8316d04c QL |
268 | sirfsoc_uart_tx_with_dma(sirfport); |
269 | else { | |
c1b7ac6f QL |
270 | if (sirfport->uart_reg->uart_type == SIRF_USP_UART) |
271 | wr_regl(port, ureg->sirfsoc_tx_rx_en, rd_regl(port, | |
272 | ureg->sirfsoc_tx_rx_en) | SIRFUART_TX_EN); | |
326707ed | 273 | wr_regl(port, ureg->sirfsoc_tx_fifo_op, SIRFUART_FIFO_STOP); |
cb4595a2 | 274 | sirfsoc_uart_pio_tx_chars(sirfport, port->fifosize); |
8316d04c | 275 | wr_regl(port, ureg->sirfsoc_tx_fifo_op, SIRFUART_FIFO_START); |
057badd6 | 276 | if (!sirfport->is_atlas7) |
8316d04c QL |
277 | wr_regl(port, ureg->sirfsoc_int_en_reg, |
278 | rd_regl(port, ureg->sirfsoc_int_en_reg)| | |
279 | uint_en->sirfsoc_txfifo_empty_en); | |
280 | else | |
281 | wr_regl(port, ureg->sirfsoc_int_en_reg, | |
282 | uint_en->sirfsoc_txfifo_empty_en); | |
283 | } | |
161e773c RW |
284 | } |
285 | ||
286 | static void sirfsoc_uart_stop_rx(struct uart_port *port) | |
287 | { | |
909102db | 288 | struct sirfsoc_uart_port *sirfport = to_sirfport(port); |
5df83111 QL |
289 | struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg; |
290 | struct sirfsoc_int_en *uint_en = &sirfport->uart_reg->uart_int_en; | |
8316d04c | 291 | |
5df83111 | 292 | wr_regl(port, ureg->sirfsoc_rx_fifo_op, 0); |
9be16b38 | 293 | if (sirfport->rx_dma_chan) { |
057badd6 | 294 | if (!sirfport->is_atlas7) |
8316d04c QL |
295 | wr_regl(port, ureg->sirfsoc_int_en_reg, |
296 | rd_regl(port, ureg->sirfsoc_int_en_reg) & | |
c1b7ac6f QL |
297 | ~(SIRFUART_RX_DMA_INT_EN(uint_en, |
298 | sirfport->uart_reg->uart_type) | | |
8316d04c QL |
299 | uint_en->sirfsoc_rx_done_en)); |
300 | else | |
c1b7ac6f QL |
301 | wr_regl(port, ureg->sirfsoc_int_en_clr_reg, |
302 | SIRFUART_RX_DMA_INT_EN(uint_en, | |
303 | sirfport->uart_reg->uart_type)| | |
304 | uint_en->sirfsoc_rx_done_en); | |
8316d04c QL |
305 | dmaengine_terminate_all(sirfport->rx_dma_chan); |
306 | } else { | |
057badd6 | 307 | if (!sirfport->is_atlas7) |
8316d04c QL |
308 | wr_regl(port, ureg->sirfsoc_int_en_reg, |
309 | rd_regl(port, ureg->sirfsoc_int_en_reg)& | |
c1b7ac6f QL |
310 | ~(SIRFUART_RX_IO_INT_EN(uint_en, |
311 | sirfport->uart_reg->uart_type))); | |
8316d04c | 312 | else |
c1b7ac6f QL |
313 | wr_regl(port, ureg->sirfsoc_int_en_clr_reg, |
314 | SIRFUART_RX_IO_INT_EN(uint_en, | |
315 | sirfport->uart_reg->uart_type)); | |
8316d04c | 316 | } |
161e773c RW |
317 | } |
318 | ||
319 | static void sirfsoc_uart_disable_ms(struct uart_port *port) | |
320 | { | |
321 | struct sirfsoc_uart_port *sirfport = to_sirfport(port); | |
5df83111 QL |
322 | struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg; |
323 | struct sirfsoc_int_en *uint_en = &sirfport->uart_reg->uart_int_en; | |
909102db | 324 | |
161e773c RW |
325 | if (!sirfport->hw_flow_ctrl) |
326 | return; | |
2eb5618d QL |
327 | sirfport->ms_enabled = false; |
328 | if (sirfport->uart_reg->uart_type == SIRF_REAL_UART) { | |
329 | wr_regl(port, ureg->sirfsoc_afc_ctrl, | |
330 | rd_regl(port, ureg->sirfsoc_afc_ctrl) & ~0x3FF); | |
057badd6 | 331 | if (!sirfport->is_atlas7) |
2eb5618d QL |
332 | wr_regl(port, ureg->sirfsoc_int_en_reg, |
333 | rd_regl(port, ureg->sirfsoc_int_en_reg)& | |
334 | ~uint_en->sirfsoc_cts_en); | |
335 | else | |
c1b7ac6f | 336 | wr_regl(port, ureg->sirfsoc_int_en_clr_reg, |
2eb5618d | 337 | uint_en->sirfsoc_cts_en); |
5df83111 | 338 | } else |
2eb5618d QL |
339 | disable_irq(gpio_to_irq(sirfport->cts_gpio)); |
340 | } | |
341 | ||
342 | static irqreturn_t sirfsoc_uart_usp_cts_handler(int irq, void *dev_id) | |
343 | { | |
344 | struct sirfsoc_uart_port *sirfport = (struct sirfsoc_uart_port *)dev_id; | |
345 | struct uart_port *port = &sirfport->port; | |
07d410e0 | 346 | spin_lock(&port->lock); |
2eb5618d QL |
347 | if (gpio_is_valid(sirfport->cts_gpio) && sirfport->ms_enabled) |
348 | uart_handle_cts_change(port, | |
349 | !gpio_get_value(sirfport->cts_gpio)); | |
07d410e0 | 350 | spin_unlock(&port->lock); |
2eb5618d | 351 | return IRQ_HANDLED; |
161e773c RW |
352 | } |
353 | ||
354 | static void sirfsoc_uart_enable_ms(struct uart_port *port) | |
355 | { | |
356 | struct sirfsoc_uart_port *sirfport = to_sirfport(port); | |
5df83111 QL |
357 | struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg; |
358 | struct sirfsoc_int_en *uint_en = &sirfport->uart_reg->uart_int_en; | |
909102db | 359 | |
161e773c RW |
360 | if (!sirfport->hw_flow_ctrl) |
361 | return; | |
2eb5618d QL |
362 | sirfport->ms_enabled = true; |
363 | if (sirfport->uart_reg->uart_type == SIRF_REAL_UART) { | |
364 | wr_regl(port, ureg->sirfsoc_afc_ctrl, | |
365 | rd_regl(port, ureg->sirfsoc_afc_ctrl) | | |
eab192ae QL |
366 | SIRFUART_AFC_TX_EN | SIRFUART_AFC_RX_EN | |
367 | SIRFUART_AFC_CTRL_RX_THD); | |
057badd6 | 368 | if (!sirfport->is_atlas7) |
2eb5618d QL |
369 | wr_regl(port, ureg->sirfsoc_int_en_reg, |
370 | rd_regl(port, ureg->sirfsoc_int_en_reg) | |
371 | | uint_en->sirfsoc_cts_en); | |
372 | else | |
373 | wr_regl(port, ureg->sirfsoc_int_en_reg, | |
374 | uint_en->sirfsoc_cts_en); | |
5df83111 | 375 | } else |
2eb5618d | 376 | enable_irq(gpio_to_irq(sirfport->cts_gpio)); |
161e773c RW |
377 | } |
378 | ||
379 | static void sirfsoc_uart_break_ctl(struct uart_port *port, int break_state) | |
380 | { | |
5df83111 QL |
381 | struct sirfsoc_uart_port *sirfport = to_sirfport(port); |
382 | struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg; | |
383 | if (sirfport->uart_reg->uart_type == SIRF_REAL_UART) { | |
384 | unsigned long ulcon = rd_regl(port, ureg->sirfsoc_line_ctrl); | |
385 | if (break_state) | |
386 | ulcon |= SIRFUART_SET_BREAK; | |
387 | else | |
388 | ulcon &= ~SIRFUART_SET_BREAK; | |
389 | wr_regl(port, ureg->sirfsoc_line_ctrl, ulcon); | |
390 | } | |
161e773c RW |
391 | } |
392 | ||
393 | static unsigned int | |
394 | sirfsoc_uart_pio_rx_chars(struct uart_port *port, unsigned int max_rx_count) | |
395 | { | |
5df83111 QL |
396 | struct sirfsoc_uart_port *sirfport = to_sirfport(port); |
397 | struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg; | |
398 | struct sirfsoc_fifo_status *ufifo_st = &sirfport->uart_reg->fifo_status; | |
161e773c | 399 | unsigned int ch, rx_count = 0; |
5df83111 QL |
400 | struct tty_struct *tty; |
401 | tty = tty_port_tty_get(&port->state->port); | |
402 | if (!tty) | |
403 | return -ENODEV; | |
404 | while (!(rd_regl(port, ureg->sirfsoc_rx_fifo_status) & | |
cb4595a2 | 405 | ufifo_st->ff_empty(port))) { |
5df83111 QL |
406 | ch = rd_regl(port, ureg->sirfsoc_rx_fifo_data) | |
407 | SIRFUART_DUMMY_READ; | |
161e773c RW |
408 | if (unlikely(uart_handle_sysrq_char(port, ch))) |
409 | continue; | |
410 | uart_insert_char(port, 0, 0, ch, TTY_NORMAL); | |
411 | rx_count++; | |
412 | if (rx_count >= max_rx_count) | |
413 | break; | |
414 | } | |
415 | ||
416 | port->icount.rx += rx_count; | |
8b9ade9f | 417 | |
161e773c RW |
418 | return rx_count; |
419 | } | |
420 | ||
421 | static unsigned int | |
422 | sirfsoc_uart_pio_tx_chars(struct sirfsoc_uart_port *sirfport, int count) | |
423 | { | |
424 | struct uart_port *port = &sirfport->port; | |
5df83111 QL |
425 | struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg; |
426 | struct sirfsoc_fifo_status *ufifo_st = &sirfport->uart_reg->fifo_status; | |
161e773c RW |
427 | struct circ_buf *xmit = &port->state->xmit; |
428 | unsigned int num_tx = 0; | |
429 | while (!uart_circ_empty(xmit) && | |
5df83111 | 430 | !(rd_regl(port, ureg->sirfsoc_tx_fifo_status) & |
cb4595a2 | 431 | ufifo_st->ff_full(port)) && |
161e773c | 432 | count--) { |
5df83111 QL |
433 | wr_regl(port, ureg->sirfsoc_tx_fifo_data, |
434 | xmit->buf[xmit->tail]); | |
161e773c RW |
435 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); |
436 | port->icount.tx++; | |
437 | num_tx++; | |
438 | } | |
439 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
440 | uart_write_wakeup(port); | |
441 | return num_tx; | |
442 | } | |
443 | ||
8316d04c QL |
444 | static void sirfsoc_uart_tx_dma_complete_callback(void *param) |
445 | { | |
446 | struct sirfsoc_uart_port *sirfport = (struct sirfsoc_uart_port *)param; | |
447 | struct uart_port *port = &sirfport->port; | |
448 | struct circ_buf *xmit = &port->state->xmit; | |
449 | unsigned long flags; | |
450 | ||
07d410e0 | 451 | spin_lock_irqsave(&port->lock, flags); |
8316d04c QL |
452 | xmit->tail = (xmit->tail + sirfport->transfer_size) & |
453 | (UART_XMIT_SIZE - 1); | |
454 | port->icount.tx += sirfport->transfer_size; | |
455 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
456 | uart_write_wakeup(port); | |
457 | if (sirfport->tx_dma_addr) | |
458 | dma_unmap_single(port->dev, sirfport->tx_dma_addr, | |
459 | sirfport->transfer_size, DMA_TO_DEVICE); | |
8316d04c QL |
460 | sirfport->tx_dma_state = TX_DMA_IDLE; |
461 | sirfsoc_uart_tx_with_dma(sirfport); | |
07d410e0 | 462 | spin_unlock_irqrestore(&port->lock, flags); |
8316d04c QL |
463 | } |
464 | ||
161e773c RW |
465 | static irqreturn_t sirfsoc_uart_isr(int irq, void *dev_id) |
466 | { | |
467 | unsigned long intr_status; | |
468 | unsigned long cts_status; | |
469 | unsigned long flag = TTY_NORMAL; | |
470 | struct sirfsoc_uart_port *sirfport = (struct sirfsoc_uart_port *)dev_id; | |
471 | struct uart_port *port = &sirfport->port; | |
5df83111 QL |
472 | struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg; |
473 | struct sirfsoc_fifo_status *ufifo_st = &sirfport->uart_reg->fifo_status; | |
474 | struct sirfsoc_int_status *uint_st = &sirfport->uart_reg->uart_int_st; | |
475 | struct sirfsoc_int_en *uint_en = &sirfport->uart_reg->uart_int_en; | |
161e773c RW |
476 | struct uart_state *state = port->state; |
477 | struct circ_buf *xmit = &port->state->xmit; | |
5425e03f | 478 | spin_lock(&port->lock); |
5df83111 QL |
479 | intr_status = rd_regl(port, ureg->sirfsoc_int_st_reg); |
480 | wr_regl(port, ureg->sirfsoc_int_st_reg, intr_status); | |
8316d04c | 481 | intr_status &= rd_regl(port, ureg->sirfsoc_int_en_reg); |
c1b7ac6f QL |
482 | if (unlikely(intr_status & (SIRFUART_ERR_INT_STAT(uint_st, |
483 | sirfport->uart_reg->uart_type)))) { | |
5df83111 QL |
484 | if (intr_status & uint_st->sirfsoc_rxd_brk) { |
485 | port->icount.brk++; | |
161e773c RW |
486 | if (uart_handle_break(port)) |
487 | goto recv_char; | |
161e773c | 488 | } |
d9e8e976 | 489 | if (intr_status & uint_st->sirfsoc_rx_oflow) { |
161e773c | 490 | port->icount.overrun++; |
d9e8e976 QL |
491 | flag = TTY_OVERRUN; |
492 | } | |
5df83111 | 493 | if (intr_status & uint_st->sirfsoc_frm_err) { |
161e773c RW |
494 | port->icount.frame++; |
495 | flag = TTY_FRAME; | |
496 | } | |
d9e8e976 QL |
497 | if (intr_status & uint_st->sirfsoc_parity_err) { |
498 | port->icount.parity++; | |
161e773c | 499 | flag = TTY_PARITY; |
d9e8e976 | 500 | } |
5df83111 QL |
501 | wr_regl(port, ureg->sirfsoc_rx_fifo_op, SIRFUART_FIFO_RESET); |
502 | wr_regl(port, ureg->sirfsoc_rx_fifo_op, 0); | |
503 | wr_regl(port, ureg->sirfsoc_rx_fifo_op, SIRFUART_FIFO_START); | |
161e773c RW |
504 | intr_status &= port->read_status_mask; |
505 | uart_insert_char(port, intr_status, | |
5df83111 | 506 | uint_en->sirfsoc_rx_oflow_en, 0, flag); |
161e773c RW |
507 | } |
508 | recv_char: | |
5df83111 | 509 | if ((sirfport->uart_reg->uart_type == SIRF_REAL_UART) && |
8316d04c QL |
510 | (intr_status & SIRFUART_CTS_INT_ST(uint_st)) && |
511 | !sirfport->tx_dma_state) { | |
5df83111 QL |
512 | cts_status = rd_regl(port, ureg->sirfsoc_afc_ctrl) & |
513 | SIRFUART_AFC_CTS_STATUS; | |
514 | if (cts_status != 0) | |
515 | cts_status = 0; | |
516 | else | |
517 | cts_status = 1; | |
518 | uart_handle_cts_change(port, cts_status); | |
519 | wake_up_interruptible(&state->port.delta_msr_wait); | |
161e773c | 520 | } |
0f17e3b4 QL |
521 | if (!sirfport->rx_dma_chan && |
522 | (intr_status & SIRFUART_RX_IO_INT_ST(uint_st))) { | |
c1b7ac6f QL |
523 | /* |
524 | * chip will trigger continuous RX_TIMEOUT interrupt | |
525 | * in RXFIFO empty and not trigger if RXFIFO recevice | |
526 | * data in limit time, original method use RX_TIMEOUT | |
527 | * will trigger lots of useless interrupt in RXFIFO | |
528 | * empty.RXFIFO received one byte will trigger RX_DONE | |
529 | * interrupt.use RX_DONE to wait for data received | |
530 | * into RXFIFO, use RX_THD/RX_FULL for lots data receive | |
531 | * and use RX_TIMEOUT for the last left data. | |
532 | */ | |
533 | if (intr_status & uint_st->sirfsoc_rx_done) { | |
534 | if (!sirfport->is_atlas7) { | |
535 | wr_regl(port, ureg->sirfsoc_int_en_reg, | |
536 | rd_regl(port, ureg->sirfsoc_int_en_reg) | |
537 | & ~(uint_en->sirfsoc_rx_done_en)); | |
538 | wr_regl(port, ureg->sirfsoc_int_en_reg, | |
539 | rd_regl(port, ureg->sirfsoc_int_en_reg) | |
540 | | (uint_en->sirfsoc_rx_timeout_en)); | |
541 | } else { | |
542 | wr_regl(port, ureg->sirfsoc_int_en_clr_reg, | |
543 | uint_en->sirfsoc_rx_done_en); | |
544 | wr_regl(port, ureg->sirfsoc_int_en_reg, | |
545 | uint_en->sirfsoc_rx_timeout_en); | |
546 | } | |
547 | } else { | |
548 | if (intr_status & uint_st->sirfsoc_rx_timeout) { | |
549 | if (!sirfport->is_atlas7) { | |
550 | wr_regl(port, ureg->sirfsoc_int_en_reg, | |
551 | rd_regl(port, ureg->sirfsoc_int_en_reg) | |
552 | & ~(uint_en->sirfsoc_rx_timeout_en)); | |
553 | wr_regl(port, ureg->sirfsoc_int_en_reg, | |
554 | rd_regl(port, ureg->sirfsoc_int_en_reg) | |
555 | | (uint_en->sirfsoc_rx_done_en)); | |
556 | } else { | |
557 | wr_regl(port, | |
558 | ureg->sirfsoc_int_en_clr_reg, | |
559 | uint_en->sirfsoc_rx_timeout_en); | |
560 | wr_regl(port, ureg->sirfsoc_int_en_reg, | |
561 | uint_en->sirfsoc_rx_done_en); | |
562 | } | |
563 | } | |
cb4595a2 | 564 | sirfsoc_uart_pio_rx_chars(port, port->fifosize); |
c1b7ac6f | 565 | } |
8316d04c | 566 | } |
07d410e0 QL |
567 | spin_unlock(&port->lock); |
568 | tty_flip_buffer_push(&state->port); | |
569 | spin_lock(&port->lock); | |
5df83111 | 570 | if (intr_status & uint_st->sirfsoc_txfifo_empty) { |
9be16b38 | 571 | if (sirfport->tx_dma_chan) |
8316d04c QL |
572 | sirfsoc_uart_tx_with_dma(sirfport); |
573 | else { | |
574 | if (uart_circ_empty(xmit) || uart_tx_stopped(port)) { | |
575 | spin_unlock(&port->lock); | |
576 | return IRQ_HANDLED; | |
577 | } else { | |
578 | sirfsoc_uart_pio_tx_chars(sirfport, | |
cb4595a2 | 579 | port->fifosize); |
8316d04c | 580 | if ((uart_circ_empty(xmit)) && |
5df83111 | 581 | (rd_regl(port, ureg->sirfsoc_tx_fifo_status) & |
cb4595a2 | 582 | ufifo_st->ff_empty(port))) |
8316d04c QL |
583 | sirfsoc_uart_stop_tx(port); |
584 | } | |
161e773c RW |
585 | } |
586 | } | |
5425e03f | 587 | spin_unlock(&port->lock); |
07d410e0 | 588 | |
161e773c RW |
589 | return IRQ_HANDLED; |
590 | } | |
591 | ||
8316d04c QL |
592 | static void sirfsoc_uart_rx_dma_complete_callback(void *param) |
593 | { | |
8316d04c QL |
594 | } |
595 | ||
596 | /* submit rx dma task into dmaengine */ | |
597 | static void sirfsoc_uart_start_next_rx_dma(struct uart_port *port) | |
161e773c | 598 | { |
909102db | 599 | struct sirfsoc_uart_port *sirfport = to_sirfport(port); |
5df83111 QL |
600 | struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg; |
601 | struct sirfsoc_int_en *uint_en = &sirfport->uart_reg->uart_int_en; | |
8316d04c QL |
602 | wr_regl(port, ureg->sirfsoc_rx_dma_io_ctrl, |
603 | rd_regl(port, ureg->sirfsoc_rx_dma_io_ctrl) & | |
604 | ~SIRFUART_IO_MODE); | |
0f17e3b4 QL |
605 | sirfport->rx_dma_items.xmit.tail = |
606 | sirfport->rx_dma_items.xmit.head = 0; | |
607 | sirfport->rx_dma_items.desc = | |
608 | dmaengine_prep_dma_cyclic(sirfport->rx_dma_chan, | |
609 | sirfport->rx_dma_items.dma_addr, SIRFSOC_RX_DMA_BUF_SIZE, | |
610 | SIRFSOC_RX_DMA_BUF_SIZE / 2, | |
611 | DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT); | |
612 | if (IS_ERR_OR_NULL(sirfport->rx_dma_items.desc)) { | |
613 | dev_err(port->dev, "DMA slave single fail\n"); | |
614 | return; | |
615 | } | |
616 | sirfport->rx_dma_items.desc->callback = | |
617 | sirfsoc_uart_rx_dma_complete_callback; | |
618 | sirfport->rx_dma_items.desc->callback_param = sirfport; | |
619 | sirfport->rx_dma_items.cookie = | |
620 | dmaengine_submit(sirfport->rx_dma_items.desc); | |
621 | dma_async_issue_pending(sirfport->rx_dma_chan); | |
057badd6 | 622 | if (!sirfport->is_atlas7) |
5df83111 | 623 | wr_regl(port, ureg->sirfsoc_int_en_reg, |
8316d04c | 624 | rd_regl(port, ureg->sirfsoc_int_en_reg) | |
c1b7ac6f QL |
625 | SIRFUART_RX_DMA_INT_EN(uint_en, |
626 | sirfport->uart_reg->uart_type)); | |
8316d04c QL |
627 | else |
628 | wr_regl(port, ureg->sirfsoc_int_en_reg, | |
c1b7ac6f QL |
629 | SIRFUART_RX_DMA_INT_EN(uint_en, |
630 | sirfport->uart_reg->uart_type)); | |
8316d04c QL |
631 | } |
632 | ||
5df83111 QL |
633 | static unsigned int |
634 | sirfsoc_usp_calc_sample_div(unsigned long set_rate, | |
635 | unsigned long ioclk_rate, unsigned long *sample_reg) | |
636 | { | |
637 | unsigned long min_delta = ~0UL; | |
638 | unsigned short sample_div; | |
639 | unsigned long ioclk_div = 0; | |
640 | unsigned long temp_delta; | |
641 | ||
cb4595a2 | 642 | for (sample_div = SIRF_USP_MIN_SAMPLE_DIV; |
5df83111 QL |
643 | sample_div <= SIRF_MAX_SAMPLE_DIV; sample_div++) { |
644 | temp_delta = ioclk_rate - | |
645 | (ioclk_rate + (set_rate * sample_div) / 2) | |
646 | / (set_rate * sample_div) * set_rate * sample_div; | |
909102db | 647 | |
5df83111 QL |
648 | temp_delta = (temp_delta > 0) ? temp_delta : -temp_delta; |
649 | if (temp_delta < min_delta) { | |
650 | ioclk_div = (2 * ioclk_rate / | |
651 | (set_rate * sample_div) + 1) / 2 - 1; | |
652 | if (ioclk_div > SIRF_IOCLK_DIV_MAX) | |
653 | continue; | |
654 | min_delta = temp_delta; | |
655 | *sample_reg = sample_div; | |
656 | if (!temp_delta) | |
657 | break; | |
658 | } | |
659 | } | |
660 | return ioclk_div; | |
161e773c RW |
661 | } |
662 | ||
663 | static unsigned int | |
5df83111 QL |
664 | sirfsoc_uart_calc_sample_div(unsigned long baud_rate, |
665 | unsigned long ioclk_rate, unsigned long *set_baud) | |
161e773c RW |
666 | { |
667 | unsigned long min_delta = ~0UL; | |
668 | unsigned short sample_div; | |
669 | unsigned int regv = 0; | |
670 | unsigned long ioclk_div; | |
671 | unsigned long baud_tmp; | |
672 | int temp_delta; | |
673 | ||
674 | for (sample_div = SIRF_MIN_SAMPLE_DIV; | |
675 | sample_div <= SIRF_MAX_SAMPLE_DIV; sample_div++) { | |
676 | ioclk_div = (ioclk_rate / (baud_rate * (sample_div + 1))) - 1; | |
677 | if (ioclk_div > SIRF_IOCLK_DIV_MAX) | |
678 | continue; | |
679 | baud_tmp = ioclk_rate / ((ioclk_div + 1) * (sample_div + 1)); | |
680 | temp_delta = baud_tmp - baud_rate; | |
681 | temp_delta = (temp_delta > 0) ? temp_delta : -temp_delta; | |
682 | if (temp_delta < min_delta) { | |
683 | regv = regv & (~SIRF_IOCLK_DIV_MASK); | |
684 | regv = regv | ioclk_div; | |
685 | regv = regv & (~SIRF_SAMPLE_DIV_MASK); | |
686 | regv = regv | (sample_div << SIRF_SAMPLE_DIV_SHIFT); | |
687 | min_delta = temp_delta; | |
5df83111 | 688 | *set_baud = baud_tmp; |
161e773c RW |
689 | } |
690 | } | |
691 | return regv; | |
692 | } | |
693 | ||
694 | static void sirfsoc_uart_set_termios(struct uart_port *port, | |
695 | struct ktermios *termios, | |
696 | struct ktermios *old) | |
697 | { | |
698 | struct sirfsoc_uart_port *sirfport = to_sirfport(port); | |
5df83111 QL |
699 | struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg; |
700 | struct sirfsoc_int_en *uint_en = &sirfport->uart_reg->uart_int_en; | |
161e773c RW |
701 | unsigned long config_reg = 0; |
702 | unsigned long baud_rate; | |
5df83111 | 703 | unsigned long set_baud; |
161e773c RW |
704 | unsigned long flags; |
705 | unsigned long ic; | |
706 | unsigned int clk_div_reg = 0; | |
8316d04c | 707 | unsigned long txfifo_op_reg, ioclk_rate; |
161e773c RW |
708 | unsigned long rx_time_out; |
709 | int threshold_div; | |
5df83111 QL |
710 | u32 data_bit_len, stop_bit_len, len_val; |
711 | unsigned long sample_div_reg = 0xf; | |
712 | ioclk_rate = port->uartclk; | |
161e773c | 713 | |
161e773c RW |
714 | switch (termios->c_cflag & CSIZE) { |
715 | default: | |
716 | case CS8: | |
5df83111 | 717 | data_bit_len = 8; |
161e773c RW |
718 | config_reg |= SIRFUART_DATA_BIT_LEN_8; |
719 | break; | |
720 | case CS7: | |
5df83111 | 721 | data_bit_len = 7; |
161e773c RW |
722 | config_reg |= SIRFUART_DATA_BIT_LEN_7; |
723 | break; | |
724 | case CS6: | |
5df83111 | 725 | data_bit_len = 6; |
161e773c RW |
726 | config_reg |= SIRFUART_DATA_BIT_LEN_6; |
727 | break; | |
728 | case CS5: | |
5df83111 | 729 | data_bit_len = 5; |
161e773c RW |
730 | config_reg |= SIRFUART_DATA_BIT_LEN_5; |
731 | break; | |
732 | } | |
5df83111 | 733 | if (termios->c_cflag & CSTOPB) { |
161e773c | 734 | config_reg |= SIRFUART_STOP_BIT_LEN_2; |
5df83111 QL |
735 | stop_bit_len = 2; |
736 | } else | |
737 | stop_bit_len = 1; | |
738 | ||
161e773c | 739 | spin_lock_irqsave(&port->lock, flags); |
5df83111 | 740 | port->read_status_mask = uint_en->sirfsoc_rx_oflow_en; |
161e773c | 741 | port->ignore_status_mask = 0; |
5df83111 QL |
742 | if (sirfport->uart_reg->uart_type == SIRF_REAL_UART) { |
743 | if (termios->c_iflag & INPCK) | |
744 | port->read_status_mask |= uint_en->sirfsoc_frm_err_en | | |
745 | uint_en->sirfsoc_parity_err_en; | |
2eb5618d | 746 | } else { |
5df83111 QL |
747 | if (termios->c_iflag & INPCK) |
748 | port->read_status_mask |= uint_en->sirfsoc_frm_err_en; | |
749 | } | |
ef8b9ddc | 750 | if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) |
5df83111 QL |
751 | port->read_status_mask |= uint_en->sirfsoc_rxd_brk_en; |
752 | if (sirfport->uart_reg->uart_type == SIRF_REAL_UART) { | |
753 | if (termios->c_iflag & IGNPAR) | |
754 | port->ignore_status_mask |= | |
755 | uint_en->sirfsoc_frm_err_en | | |
756 | uint_en->sirfsoc_parity_err_en; | |
757 | if (termios->c_cflag & PARENB) { | |
758 | if (termios->c_cflag & CMSPAR) { | |
759 | if (termios->c_cflag & PARODD) | |
760 | config_reg |= SIRFUART_STICK_BIT_MARK; | |
761 | else | |
762 | config_reg |= SIRFUART_STICK_BIT_SPACE; | |
5df83111 | 763 | } else { |
d9e8e976 QL |
764 | if (termios->c_cflag & PARODD) |
765 | config_reg |= SIRFUART_STICK_BIT_ODD; | |
766 | else | |
767 | config_reg |= SIRFUART_STICK_BIT_EVEN; | |
5df83111 QL |
768 | } |
769 | } | |
2eb5618d | 770 | } else { |
5df83111 QL |
771 | if (termios->c_iflag & IGNPAR) |
772 | port->ignore_status_mask |= | |
773 | uint_en->sirfsoc_frm_err_en; | |
774 | if (termios->c_cflag & PARENB) | |
775 | dev_warn(port->dev, | |
776 | "USP-UART not support parity err\n"); | |
777 | } | |
778 | if (termios->c_iflag & IGNBRK) { | |
161e773c | 779 | port->ignore_status_mask |= |
5df83111 QL |
780 | uint_en->sirfsoc_rxd_brk_en; |
781 | if (termios->c_iflag & IGNPAR) | |
782 | port->ignore_status_mask |= | |
783 | uint_en->sirfsoc_rx_oflow_en; | |
784 | } | |
161e773c RW |
785 | if ((termios->c_cflag & CREAD) == 0) |
786 | port->ignore_status_mask |= SIRFUART_DUMMY_READ; | |
161e773c RW |
787 | /* Hardware Flow Control Settings */ |
788 | if (UART_ENABLE_MS(port, termios->c_cflag)) { | |
789 | if (!sirfport->ms_enabled) | |
790 | sirfsoc_uart_enable_ms(port); | |
791 | } else { | |
792 | if (sirfport->ms_enabled) | |
793 | sirfsoc_uart_disable_ms(port); | |
794 | } | |
5df83111 QL |
795 | baud_rate = uart_get_baud_rate(port, termios, old, 0, 4000000); |
796 | if (ioclk_rate == 150000000) { | |
ac4ce718 BS |
797 | for (ic = 0; ic < SIRF_BAUD_RATE_SUPPORT_NR; ic++) |
798 | if (baud_rate == baudrate_to_regv[ic].baud_rate) | |
799 | clk_div_reg = baudrate_to_regv[ic].reg_val; | |
800 | } | |
5df83111 QL |
801 | set_baud = baud_rate; |
802 | if (sirfport->uart_reg->uart_type == SIRF_REAL_UART) { | |
803 | if (unlikely(clk_div_reg == 0)) | |
804 | clk_div_reg = sirfsoc_uart_calc_sample_div(baud_rate, | |
805 | ioclk_rate, &set_baud); | |
806 | wr_regl(port, ureg->sirfsoc_divisor, clk_div_reg); | |
2eb5618d | 807 | } else { |
5df83111 QL |
808 | clk_div_reg = sirfsoc_usp_calc_sample_div(baud_rate, |
809 | ioclk_rate, &sample_div_reg); | |
810 | sample_div_reg--; | |
811 | set_baud = ((ioclk_rate / (clk_div_reg+1) - 1) / | |
812 | (sample_div_reg + 1)); | |
813 | /* setting usp mode 2 */ | |
459f15c4 QL |
814 | len_val = ((1 << SIRFSOC_USP_MODE2_RXD_DELAY_OFFSET) | |
815 | (1 << SIRFSOC_USP_MODE2_TXD_DELAY_OFFSET)); | |
816 | len_val |= ((clk_div_reg & SIRFSOC_USP_MODE2_CLK_DIVISOR_MASK) | |
817 | << SIRFSOC_USP_MODE2_CLK_DIVISOR_OFFSET); | |
818 | wr_regl(port, ureg->sirfsoc_mode2, len_val); | |
5df83111 | 819 | } |
161e773c | 820 | if (tty_termios_baud_rate(termios)) |
5df83111 QL |
821 | tty_termios_encode_baud_rate(termios, set_baud, set_baud); |
822 | /* set receive timeout && data bits len */ | |
823 | rx_time_out = SIRFSOC_UART_RX_TIMEOUT(set_baud, 20000); | |
824 | rx_time_out = SIRFUART_RECV_TIMEOUT_VALUE(rx_time_out); | |
8316d04c | 825 | txfifo_op_reg = rd_regl(port, ureg->sirfsoc_tx_fifo_op); |
5df83111 | 826 | wr_regl(port, ureg->sirfsoc_tx_fifo_op, |
8316d04c | 827 | (txfifo_op_reg & ~SIRFUART_FIFO_START)); |
5df83111 | 828 | if (sirfport->uart_reg->uart_type == SIRF_REAL_UART) { |
c1b7ac6f | 829 | config_reg |= SIRFUART_UART_RECV_TIMEOUT(rx_time_out); |
5df83111 | 830 | wr_regl(port, ureg->sirfsoc_line_ctrl, config_reg); |
2eb5618d | 831 | } else { |
5df83111 | 832 | /*tx frame ctrl*/ |
459f15c4 QL |
833 | len_val = (data_bit_len - 1) << SIRFSOC_USP_TX_DATA_LEN_OFFSET; |
834 | len_val |= (data_bit_len + 1 + stop_bit_len - 1) << | |
835 | SIRFSOC_USP_TX_FRAME_LEN_OFFSET; | |
836 | len_val |= ((data_bit_len - 1) << | |
837 | SIRFSOC_USP_TX_SHIFTER_LEN_OFFSET); | |
838 | len_val |= (((clk_div_reg & 0xc00) >> 10) << | |
839 | SIRFSOC_USP_TX_CLK_DIVISOR_OFFSET); | |
5df83111 QL |
840 | wr_regl(port, ureg->sirfsoc_tx_frame_ctrl, len_val); |
841 | /*rx frame ctrl*/ | |
459f15c4 QL |
842 | len_val = (data_bit_len - 1) << SIRFSOC_USP_RX_DATA_LEN_OFFSET; |
843 | len_val |= (data_bit_len + 1 + stop_bit_len - 1) << | |
844 | SIRFSOC_USP_RX_FRAME_LEN_OFFSET; | |
845 | len_val |= (data_bit_len - 1) << | |
846 | SIRFSOC_USP_RX_SHIFTER_LEN_OFFSET; | |
847 | len_val |= (((clk_div_reg & 0xf000) >> 12) << | |
848 | SIRFSOC_USP_RX_CLK_DIVISOR_OFFSET); | |
5df83111 QL |
849 | wr_regl(port, ureg->sirfsoc_rx_frame_ctrl, len_val); |
850 | /*async param*/ | |
851 | wr_regl(port, ureg->sirfsoc_async_param_reg, | |
c1b7ac6f | 852 | (SIRFUART_USP_RECV_TIMEOUT(rx_time_out)) | |
459f15c4 QL |
853 | (sample_div_reg & SIRFSOC_USP_ASYNC_DIV2_MASK) << |
854 | SIRFSOC_USP_ASYNC_DIV2_OFFSET); | |
5df83111 | 855 | } |
9be16b38 | 856 | if (sirfport->tx_dma_chan) |
8316d04c QL |
857 | wr_regl(port, ureg->sirfsoc_tx_dma_io_ctrl, SIRFUART_DMA_MODE); |
858 | else | |
859 | wr_regl(port, ureg->sirfsoc_tx_dma_io_ctrl, SIRFUART_IO_MODE); | |
9be16b38 | 860 | if (sirfport->rx_dma_chan) |
1d26c9ff QL |
861 | wr_regl(port, ureg->sirfsoc_rx_dma_io_ctrl, |
862 | rd_regl(port, ureg->sirfsoc_rx_dma_io_ctrl) & | |
863 | ~SIRFUART_IO_MODE); | |
8316d04c | 864 | else |
1d26c9ff QL |
865 | wr_regl(port, ureg->sirfsoc_rx_dma_io_ctrl, |
866 | rd_regl(port, ureg->sirfsoc_rx_dma_io_ctrl) | | |
867 | SIRFUART_IO_MODE); | |
0f17e3b4 | 868 | sirfport->rx_period_time = 20000000; |
161e773c | 869 | /* Reset Rx/Tx FIFO Threshold level for proper baudrate */ |
5df83111 | 870 | if (set_baud < 1000000) |
161e773c RW |
871 | threshold_div = 1; |
872 | else | |
873 | threshold_div = 2; | |
8316d04c QL |
874 | wr_regl(port, ureg->sirfsoc_tx_fifo_ctrl, |
875 | SIRFUART_FIFO_THD(port) / threshold_div); | |
876 | wr_regl(port, ureg->sirfsoc_rx_fifo_ctrl, | |
877 | SIRFUART_FIFO_THD(port) / threshold_div); | |
878 | txfifo_op_reg |= SIRFUART_FIFO_START; | |
879 | wr_regl(port, ureg->sirfsoc_tx_fifo_op, txfifo_op_reg); | |
5df83111 | 880 | uart_update_timeout(port, termios->c_cflag, set_baud); |
5df83111 | 881 | wr_regl(port, ureg->sirfsoc_tx_rx_en, SIRFUART_TX_EN | SIRFUART_RX_EN); |
161e773c RW |
882 | spin_unlock_irqrestore(&port->lock, flags); |
883 | } | |
884 | ||
388faf9f QL |
885 | static void sirfsoc_uart_pm(struct uart_port *port, unsigned int state, |
886 | unsigned int oldstate) | |
887 | { | |
888 | struct sirfsoc_uart_port *sirfport = to_sirfport(port); | |
4b8038dc | 889 | if (!state) |
388faf9f | 890 | clk_prepare_enable(sirfport->clk); |
4b8038dc | 891 | else |
388faf9f QL |
892 | clk_disable_unprepare(sirfport->clk); |
893 | } | |
894 | ||
161e773c RW |
895 | static int sirfsoc_uart_startup(struct uart_port *port) |
896 | { | |
897 | struct sirfsoc_uart_port *sirfport = to_sirfport(port); | |
15cdcb12 | 898 | struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg; |
466e285b | 899 | struct sirfsoc_int_en *uint_en = &sirfport->uart_reg->uart_int_en; |
161e773c RW |
900 | unsigned int index = port->line; |
901 | int ret; | |
2a446241 | 902 | irq_modify_status(port->irq, IRQ_NOREQUEST, IRQ_NOAUTOEN); |
161e773c RW |
903 | ret = request_irq(port->irq, |
904 | sirfsoc_uart_isr, | |
905 | 0, | |
906 | SIRFUART_PORT_NAME, | |
907 | sirfport); | |
908 | if (ret != 0) { | |
909 | dev_err(port->dev, "UART%d request IRQ line (%d) failed.\n", | |
910 | index, port->irq); | |
911 | goto irq_err; | |
912 | } | |
15cdcb12 QL |
913 | /* initial hardware settings */ |
914 | wr_regl(port, ureg->sirfsoc_tx_dma_io_ctrl, | |
915 | rd_regl(port, ureg->sirfsoc_tx_dma_io_ctrl) | | |
916 | SIRFUART_IO_MODE); | |
917 | wr_regl(port, ureg->sirfsoc_rx_dma_io_ctrl, | |
918 | rd_regl(port, ureg->sirfsoc_rx_dma_io_ctrl) | | |
919 | SIRFUART_IO_MODE); | |
0f17e3b4 QL |
920 | wr_regl(port, ureg->sirfsoc_rx_dma_io_ctrl, |
921 | rd_regl(port, ureg->sirfsoc_rx_dma_io_ctrl) & | |
922 | ~SIRFUART_RX_DMA_FLUSH); | |
15cdcb12 QL |
923 | wr_regl(port, ureg->sirfsoc_tx_dma_io_len, 0); |
924 | wr_regl(port, ureg->sirfsoc_rx_dma_io_len, 0); | |
925 | wr_regl(port, ureg->sirfsoc_tx_rx_en, SIRFUART_RX_EN | SIRFUART_TX_EN); | |
926 | if (sirfport->uart_reg->uart_type == SIRF_USP_UART) | |
927 | wr_regl(port, ureg->sirfsoc_mode1, | |
928 | SIRFSOC_USP_ENDIAN_CTRL_LSBF | | |
929 | SIRFSOC_USP_EN); | |
930 | wr_regl(port, ureg->sirfsoc_tx_fifo_op, SIRFUART_FIFO_RESET); | |
15cdcb12 QL |
931 | wr_regl(port, ureg->sirfsoc_rx_fifo_op, SIRFUART_FIFO_RESET); |
932 | wr_regl(port, ureg->sirfsoc_rx_fifo_op, 0); | |
933 | wr_regl(port, ureg->sirfsoc_tx_fifo_ctrl, SIRFUART_FIFO_THD(port)); | |
934 | wr_regl(port, ureg->sirfsoc_rx_fifo_ctrl, SIRFUART_FIFO_THD(port)); | |
9be16b38 | 935 | if (sirfport->rx_dma_chan) |
8316d04c | 936 | wr_regl(port, ureg->sirfsoc_rx_fifo_level_chk, |
1d26c9ff QL |
937 | SIRFUART_RX_FIFO_CHK_SC(port->line, 0x1) | |
938 | SIRFUART_RX_FIFO_CHK_LC(port->line, 0x2) | | |
939 | SIRFUART_RX_FIFO_CHK_HC(port->line, 0x4)); | |
9be16b38 | 940 | if (sirfport->tx_dma_chan) { |
8316d04c QL |
941 | sirfport->tx_dma_state = TX_DMA_IDLE; |
942 | wr_regl(port, ureg->sirfsoc_tx_fifo_level_chk, | |
943 | SIRFUART_TX_FIFO_CHK_SC(port->line, 0x1b) | | |
944 | SIRFUART_TX_FIFO_CHK_LC(port->line, 0xe) | | |
945 | SIRFUART_TX_FIFO_CHK_HC(port->line, 0x4)); | |
946 | } | |
2eb5618d QL |
947 | sirfport->ms_enabled = false; |
948 | if (sirfport->uart_reg->uart_type == SIRF_USP_UART && | |
949 | sirfport->hw_flow_ctrl) { | |
2a446241 RH |
950 | irq_modify_status(gpio_to_irq(sirfport->cts_gpio), |
951 | IRQ_NOREQUEST, IRQ_NOAUTOEN); | |
2eb5618d QL |
952 | ret = request_irq(gpio_to_irq(sirfport->cts_gpio), |
953 | sirfsoc_uart_usp_cts_handler, IRQF_TRIGGER_FALLING | | |
954 | IRQF_TRIGGER_RISING, "usp_cts_irq", sirfport); | |
955 | if (ret != 0) { | |
956 | dev_err(port->dev, "UART-USP:request gpio irq fail\n"); | |
957 | goto init_rx_err; | |
958 | } | |
959 | } | |
1d26c9ff QL |
960 | if (sirfport->uart_reg->uart_type == SIRF_REAL_UART && |
961 | sirfport->rx_dma_chan) | |
962 | wr_regl(port, ureg->sirfsoc_swh_dma_io, | |
963 | SIRFUART_CLEAR_RX_ADDR_EN); | |
964 | if (sirfport->uart_reg->uart_type == SIRF_USP_UART && | |
965 | sirfport->rx_dma_chan) | |
966 | wr_regl(port, ureg->sirfsoc_rx_dma_io_ctrl, | |
967 | rd_regl(port, ureg->sirfsoc_rx_dma_io_ctrl) | | |
968 | SIRFSOC_USP_FRADDR_CLR_EN); | |
0f17e3b4 QL |
969 | if (sirfport->rx_dma_chan && !sirfport->is_hrt_enabled) { |
970 | sirfport->is_hrt_enabled = true; | |
971 | sirfport->rx_period_time = 20000000; | |
1d26c9ff QL |
972 | sirfport->rx_last_pos = -1; |
973 | sirfport->pio_fetch_cnt = 0; | |
0f17e3b4 QL |
974 | sirfport->rx_dma_items.xmit.tail = |
975 | sirfport->rx_dma_items.xmit.head = 0; | |
976 | hrtimer_start(&sirfport->hrt, | |
977 | ns_to_ktime(sirfport->rx_period_time), | |
978 | HRTIMER_MODE_REL); | |
979 | } | |
466e285b QL |
980 | wr_regl(port, ureg->sirfsoc_rx_fifo_op, SIRFUART_FIFO_START); |
981 | if (sirfport->rx_dma_chan) | |
982 | sirfsoc_uart_start_next_rx_dma(port); | |
983 | else { | |
984 | if (!sirfport->is_atlas7) | |
985 | wr_regl(port, ureg->sirfsoc_int_en_reg, | |
986 | rd_regl(port, ureg->sirfsoc_int_en_reg) | | |
987 | SIRFUART_RX_IO_INT_EN(uint_en, | |
988 | sirfport->uart_reg->uart_type)); | |
989 | else | |
990 | wr_regl(port, ureg->sirfsoc_int_en_reg, | |
991 | SIRFUART_RX_IO_INT_EN(uint_en, | |
992 | sirfport->uart_reg->uart_type)); | |
993 | } | |
994 | enable_irq(port->irq); | |
2eb5618d | 995 | |
15cdcb12 | 996 | return 0; |
2eb5618d QL |
997 | init_rx_err: |
998 | free_irq(port->irq, sirfport); | |
161e773c RW |
999 | irq_err: |
1000 | return ret; | |
1001 | } | |
1002 | ||
1003 | static void sirfsoc_uart_shutdown(struct uart_port *port) | |
1004 | { | |
1005 | struct sirfsoc_uart_port *sirfport = to_sirfport(port); | |
5df83111 | 1006 | struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg; |
1d26c9ff QL |
1007 | struct circ_buf *xmit; |
1008 | ||
1009 | xmit = &sirfport->rx_dma_items.xmit; | |
057badd6 | 1010 | if (!sirfport->is_atlas7) |
5df83111 | 1011 | wr_regl(port, ureg->sirfsoc_int_en_reg, 0); |
909102db | 1012 | else |
c1b7ac6f | 1013 | wr_regl(port, ureg->sirfsoc_int_en_clr_reg, ~0UL); |
909102db | 1014 | |
161e773c | 1015 | free_irq(port->irq, sirfport); |
2eb5618d | 1016 | if (sirfport->ms_enabled) |
161e773c | 1017 | sirfsoc_uart_disable_ms(port); |
2eb5618d QL |
1018 | if (sirfport->uart_reg->uart_type == SIRF_USP_UART && |
1019 | sirfport->hw_flow_ctrl) { | |
1020 | gpio_set_value(sirfport->rts_gpio, 1); | |
1021 | free_irq(gpio_to_irq(sirfport->cts_gpio), sirfport); | |
161e773c | 1022 | } |
9be16b38 | 1023 | if (sirfport->tx_dma_chan) |
8316d04c | 1024 | sirfport->tx_dma_state = TX_DMA_IDLE; |
0f17e3b4 | 1025 | if (sirfport->rx_dma_chan && sirfport->is_hrt_enabled) { |
1d26c9ff QL |
1026 | while (((rd_regl(port, ureg->sirfsoc_rx_fifo_status) & |
1027 | SIRFUART_RX_FIFO_MASK) > sirfport->pio_fetch_cnt) && | |
1028 | !CIRC_CNT(xmit->head, xmit->tail, | |
1029 | SIRFSOC_RX_DMA_BUF_SIZE)) | |
0f17e3b4 QL |
1030 | ; |
1031 | sirfport->is_hrt_enabled = false; | |
1032 | hrtimer_cancel(&sirfport->hrt); | |
1033 | } | |
161e773c RW |
1034 | } |
1035 | ||
1036 | static const char *sirfsoc_uart_type(struct uart_port *port) | |
1037 | { | |
1038 | return port->type == SIRFSOC_PORT_TYPE ? SIRFUART_PORT_NAME : NULL; | |
1039 | } | |
1040 | ||
1041 | static int sirfsoc_uart_request_port(struct uart_port *port) | |
1042 | { | |
5df83111 QL |
1043 | struct sirfsoc_uart_port *sirfport = to_sirfport(port); |
1044 | struct sirfsoc_uart_param *uart_param = &sirfport->uart_reg->uart_param; | |
161e773c RW |
1045 | void *ret; |
1046 | ret = request_mem_region(port->mapbase, | |
5df83111 | 1047 | SIRFUART_MAP_SIZE, uart_param->port_name); |
161e773c RW |
1048 | return ret ? 0 : -EBUSY; |
1049 | } | |
1050 | ||
1051 | static void sirfsoc_uart_release_port(struct uart_port *port) | |
1052 | { | |
1053 | release_mem_region(port->mapbase, SIRFUART_MAP_SIZE); | |
1054 | } | |
1055 | ||
1056 | static void sirfsoc_uart_config_port(struct uart_port *port, int flags) | |
1057 | { | |
1058 | if (flags & UART_CONFIG_TYPE) { | |
1059 | port->type = SIRFSOC_PORT_TYPE; | |
1060 | sirfsoc_uart_request_port(port); | |
1061 | } | |
1062 | } | |
1063 | ||
1064 | static struct uart_ops sirfsoc_uart_ops = { | |
1065 | .tx_empty = sirfsoc_uart_tx_empty, | |
1066 | .get_mctrl = sirfsoc_uart_get_mctrl, | |
1067 | .set_mctrl = sirfsoc_uart_set_mctrl, | |
1068 | .stop_tx = sirfsoc_uart_stop_tx, | |
1069 | .start_tx = sirfsoc_uart_start_tx, | |
1070 | .stop_rx = sirfsoc_uart_stop_rx, | |
1071 | .enable_ms = sirfsoc_uart_enable_ms, | |
1072 | .break_ctl = sirfsoc_uart_break_ctl, | |
1073 | .startup = sirfsoc_uart_startup, | |
1074 | .shutdown = sirfsoc_uart_shutdown, | |
1075 | .set_termios = sirfsoc_uart_set_termios, | |
388faf9f | 1076 | .pm = sirfsoc_uart_pm, |
161e773c RW |
1077 | .type = sirfsoc_uart_type, |
1078 | .release_port = sirfsoc_uart_release_port, | |
1079 | .request_port = sirfsoc_uart_request_port, | |
1080 | .config_port = sirfsoc_uart_config_port, | |
1081 | }; | |
1082 | ||
1083 | #ifdef CONFIG_SERIAL_SIRFSOC_CONSOLE | |
5df83111 QL |
1084 | static int __init |
1085 | sirfsoc_uart_console_setup(struct console *co, char *options) | |
161e773c RW |
1086 | { |
1087 | unsigned int baud = 115200; | |
1088 | unsigned int bits = 8; | |
1089 | unsigned int parity = 'n'; | |
1090 | unsigned int flow = 'n'; | |
a6ffe896 QL |
1091 | struct sirfsoc_uart_port *sirfport; |
1092 | struct sirfsoc_register *ureg; | |
161e773c | 1093 | if (co->index < 0 || co->index >= SIRFSOC_UART_NR) |
c35b49b7 | 1094 | co->index = 1; |
a6ffe896 QL |
1095 | sirfport = sirf_ports[co->index]; |
1096 | if (!sirfport) | |
1097 | return -ENODEV; | |
1098 | ureg = &sirfport->uart_reg->uart_reg; | |
1099 | if (!sirfport->port.mapbase) | |
161e773c RW |
1100 | return -ENODEV; |
1101 | ||
5df83111 QL |
1102 | /* enable usp in mode1 register */ |
1103 | if (sirfport->uart_reg->uart_type == SIRF_USP_UART) | |
a6ffe896 | 1104 | wr_regl(&sirfport->port, ureg->sirfsoc_mode1, SIRFSOC_USP_EN | |
5df83111 | 1105 | SIRFSOC_USP_ENDIAN_CTRL_LSBF); |
161e773c RW |
1106 | if (options) |
1107 | uart_parse_options(options, &baud, &parity, &bits, &flow); | |
a6ffe896 | 1108 | sirfport->port.cons = co; |
5df83111 | 1109 | |
8316d04c | 1110 | /* default console tx/rx transfer using io mode */ |
9be16b38 QL |
1111 | sirfport->rx_dma_chan = NULL; |
1112 | sirfport->tx_dma_chan = NULL; | |
a6ffe896 | 1113 | return uart_set_options(&sirfport->port, co, baud, parity, bits, flow); |
161e773c RW |
1114 | } |
1115 | ||
1116 | static void sirfsoc_uart_console_putchar(struct uart_port *port, int ch) | |
1117 | { | |
5df83111 QL |
1118 | struct sirfsoc_uart_port *sirfport = to_sirfport(port); |
1119 | struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg; | |
1120 | struct sirfsoc_fifo_status *ufifo_st = &sirfport->uart_reg->fifo_status; | |
cb4595a2 QL |
1121 | while (rd_regl(port, ureg->sirfsoc_tx_fifo_status) & |
1122 | ufifo_st->ff_full(port)) | |
161e773c | 1123 | cpu_relax(); |
205c384f | 1124 | wr_regl(port, ureg->sirfsoc_tx_fifo_data, ch); |
161e773c RW |
1125 | } |
1126 | ||
1127 | static void sirfsoc_uart_console_write(struct console *co, const char *s, | |
1128 | unsigned int count) | |
1129 | { | |
a6ffe896 QL |
1130 | struct sirfsoc_uart_port *sirfport = sirf_ports[co->index]; |
1131 | ||
1132 | uart_console_write(&sirfport->port, s, count, | |
1133 | sirfsoc_uart_console_putchar); | |
161e773c RW |
1134 | } |
1135 | ||
1136 | static struct console sirfsoc_uart_console = { | |
1137 | .name = SIRFSOC_UART_NAME, | |
1138 | .device = uart_console_device, | |
1139 | .flags = CON_PRINTBUFFER, | |
1140 | .index = -1, | |
1141 | .write = sirfsoc_uart_console_write, | |
1142 | .setup = sirfsoc_uart_console_setup, | |
1143 | .data = &sirfsoc_uart_drv, | |
1144 | }; | |
1145 | ||
1146 | static int __init sirfsoc_uart_console_init(void) | |
1147 | { | |
1148 | register_console(&sirfsoc_uart_console); | |
1149 | return 0; | |
1150 | } | |
1151 | console_initcall(sirfsoc_uart_console_init); | |
1152 | #endif | |
1153 | ||
1154 | static struct uart_driver sirfsoc_uart_drv = { | |
1155 | .owner = THIS_MODULE, | |
1156 | .driver_name = SIRFUART_PORT_NAME, | |
1157 | .nr = SIRFSOC_UART_NR, | |
1158 | .dev_name = SIRFSOC_UART_NAME, | |
1159 | .major = SIRFSOC_UART_MAJOR, | |
1160 | .minor = SIRFSOC_UART_MINOR, | |
1161 | #ifdef CONFIG_SERIAL_SIRFSOC_CONSOLE | |
1162 | .cons = &sirfsoc_uart_console, | |
1163 | #else | |
1164 | .cons = NULL, | |
1165 | #endif | |
1166 | }; | |
1167 | ||
0f17e3b4 QL |
1168 | static enum hrtimer_restart |
1169 | sirfsoc_uart_rx_dma_hrtimer_callback(struct hrtimer *hrt) | |
1170 | { | |
1171 | struct sirfsoc_uart_port *sirfport; | |
1172 | struct uart_port *port; | |
1173 | int count, inserted; | |
1174 | struct dma_tx_state tx_state; | |
1175 | struct tty_struct *tty; | |
1176 | struct sirfsoc_register *ureg; | |
1177 | struct circ_buf *xmit; | |
1d26c9ff QL |
1178 | struct sirfsoc_fifo_status *ufifo_st; |
1179 | int max_pio_cnt; | |
0f17e3b4 QL |
1180 | |
1181 | sirfport = container_of(hrt, struct sirfsoc_uart_port, hrt); | |
1182 | port = &sirfport->port; | |
1183 | inserted = 0; | |
1184 | tty = port->state->port.tty; | |
1185 | ureg = &sirfport->uart_reg->uart_reg; | |
1186 | xmit = &sirfport->rx_dma_items.xmit; | |
1d26c9ff QL |
1187 | ufifo_st = &sirfport->uart_reg->fifo_status; |
1188 | ||
0f17e3b4 | 1189 | dmaengine_tx_status(sirfport->rx_dma_chan, |
1d26c9ff QL |
1190 | sirfport->rx_dma_items.cookie, &tx_state); |
1191 | if (SIRFSOC_RX_DMA_BUF_SIZE - tx_state.residue != | |
1192 | sirfport->rx_last_pos) { | |
1193 | xmit->head = SIRFSOC_RX_DMA_BUF_SIZE - tx_state.residue; | |
1194 | sirfport->rx_last_pos = xmit->head; | |
1195 | sirfport->pio_fetch_cnt = 0; | |
1196 | } | |
0f17e3b4 QL |
1197 | count = CIRC_CNT_TO_END(xmit->head, xmit->tail, |
1198 | SIRFSOC_RX_DMA_BUF_SIZE); | |
1199 | while (count > 0) { | |
1200 | inserted = tty_insert_flip_string(tty->port, | |
1201 | (const unsigned char *)&xmit->buf[xmit->tail], count); | |
1202 | if (!inserted) | |
1203 | goto next_hrt; | |
1204 | port->icount.rx += inserted; | |
1205 | xmit->tail = (xmit->tail + inserted) & | |
1206 | (SIRFSOC_RX_DMA_BUF_SIZE - 1); | |
1207 | count = CIRC_CNT_TO_END(xmit->head, xmit->tail, | |
1208 | SIRFSOC_RX_DMA_BUF_SIZE); | |
1209 | tty_flip_buffer_push(tty->port); | |
1210 | } | |
1211 | /* | |
1212 | * if RX DMA buffer data have all push into tty buffer, and there is | |
1213 | * only little data(less than a dma transfer unit) left in rxfifo, | |
1214 | * fetch it out in pio mode and switch back to dma immediately | |
1215 | */ | |
1216 | if (!inserted && !count && | |
1217 | ((rd_regl(port, ureg->sirfsoc_rx_fifo_status) & | |
1d26c9ff QL |
1218 | SIRFUART_RX_FIFO_MASK) > sirfport->pio_fetch_cnt)) { |
1219 | dmaengine_pause(sirfport->rx_dma_chan); | |
0f17e3b4 QL |
1220 | /* switch to pio mode */ |
1221 | wr_regl(port, ureg->sirfsoc_rx_dma_io_ctrl, | |
1222 | rd_regl(port, ureg->sirfsoc_rx_dma_io_ctrl) | | |
1223 | SIRFUART_IO_MODE); | |
1d26c9ff QL |
1224 | /* |
1225 | * UART controller SWH_DMA_IO register have CLEAR_RX_ADDR_EN | |
1226 | * When found changing I/O to DMA mode, it clears | |
1227 | * two low bits of read point; | |
1228 | * USP have similar FRADDR_CLR_EN bit in USP_RX_DMA_IO_CTRL. | |
1229 | * Fetch data out from rxfifo into DMA buffer in PIO mode, | |
1230 | * while switch back to DMA mode, the data fetched will override | |
1231 | * by DMA, as hardware have a strange behaviour: | |
1232 | * after switch back to DMA mode, check rxfifo status it will | |
1233 | * be the number PIO fetched, so record the fetched data count | |
1234 | * to avoid the repeated fetch | |
1235 | */ | |
1236 | max_pio_cnt = 3; | |
1237 | while (!(rd_regl(port, ureg->sirfsoc_rx_fifo_status) & | |
1238 | ufifo_st->ff_empty(port)) && max_pio_cnt--) { | |
1239 | xmit->buf[xmit->head] = | |
1240 | rd_regl(port, ureg->sirfsoc_rx_fifo_data); | |
1241 | xmit->head = (xmit->head + 1) & | |
1242 | (SIRFSOC_RX_DMA_BUF_SIZE - 1); | |
1243 | sirfport->pio_fetch_cnt++; | |
0f17e3b4 | 1244 | } |
0f17e3b4 QL |
1245 | /* switch back to dma mode */ |
1246 | wr_regl(port, ureg->sirfsoc_rx_dma_io_ctrl, | |
1247 | rd_regl(port, ureg->sirfsoc_rx_dma_io_ctrl) & | |
1248 | ~SIRFUART_IO_MODE); | |
1d26c9ff | 1249 | dmaengine_resume(sirfport->rx_dma_chan); |
0f17e3b4 QL |
1250 | } |
1251 | next_hrt: | |
1252 | hrtimer_forward_now(hrt, ns_to_ktime(sirfport->rx_period_time)); | |
1253 | return HRTIMER_RESTART; | |
1254 | } | |
1255 | ||
c1b7ac6f | 1256 | static struct of_device_id sirfsoc_uart_ids[] = { |
5df83111 | 1257 | { .compatible = "sirf,prima2-uart", .data = &sirfsoc_uart,}, |
057badd6 | 1258 | { .compatible = "sirf,atlas7-uart", .data = &sirfsoc_uart}, |
5df83111 | 1259 | { .compatible = "sirf,prima2-usp-uart", .data = &sirfsoc_usp}, |
c1b7ac6f | 1260 | { .compatible = "sirf,atlas7-usp-uart", .data = &sirfsoc_usp}, |
5df83111 QL |
1261 | {} |
1262 | }; | |
1263 | MODULE_DEVICE_TABLE(of, sirfsoc_uart_ids); | |
1264 | ||
ada1f443 | 1265 | static int sirfsoc_uart_probe(struct platform_device *pdev) |
161e773c | 1266 | { |
af99c187 | 1267 | struct device_node *np = pdev->dev.of_node; |
161e773c RW |
1268 | struct sirfsoc_uart_port *sirfport; |
1269 | struct uart_port *port; | |
1270 | struct resource *res; | |
1271 | int ret; | |
9be16b38 | 1272 | struct dma_slave_config slv_cfg = { |
1d26c9ff | 1273 | .src_maxburst = 1, |
9be16b38 QL |
1274 | }; |
1275 | struct dma_slave_config tx_slv_cfg = { | |
1276 | .dst_maxburst = 2, | |
1277 | }; | |
5df83111 | 1278 | const struct of_device_id *match; |
161e773c | 1279 | |
af99c187 | 1280 | match = of_match_node(sirfsoc_uart_ids, np); |
a6ffe896 QL |
1281 | sirfport = devm_kzalloc(&pdev->dev, sizeof(*sirfport), GFP_KERNEL); |
1282 | if (!sirfport) { | |
1283 | ret = -ENOMEM; | |
161e773c RW |
1284 | goto err; |
1285 | } | |
af99c187 | 1286 | sirfport->port.line = of_alias_get_id(np, "serial"); |
a6ffe896 QL |
1287 | sirf_ports[sirfport->port.line] = sirfport; |
1288 | sirfport->port.iotype = UPIO_MEM; | |
1289 | sirfport->port.flags = UPF_BOOT_AUTOCONF; | |
161e773c RW |
1290 | port = &sirfport->port; |
1291 | port->dev = &pdev->dev; | |
1292 | port->private_data = sirfport; | |
5df83111 | 1293 | sirfport->uart_reg = (struct sirfsoc_uart_register *)match->data; |
161e773c | 1294 | |
af99c187 | 1295 | sirfport->hw_flow_ctrl = |
7f60830a GU |
1296 | of_property_read_bool(np, "uart-has-rtscts") || |
1297 | of_property_read_bool(np, "sirf,uart-has-rtscts") /* deprecated */; | |
af99c187 GU |
1298 | if (of_device_is_compatible(np, "sirf,prima2-uart") || |
1299 | of_device_is_compatible(np, "sirf,atlas7-uart")) | |
5df83111 | 1300 | sirfport->uart_reg->uart_type = SIRF_REAL_UART; |
af99c187 GU |
1301 | if (of_device_is_compatible(np, "sirf,prima2-usp-uart") || |
1302 | of_device_is_compatible(np, "sirf,atlas7-usp-uart")) { | |
5df83111 | 1303 | sirfport->uart_reg->uart_type = SIRF_USP_UART; |
2eb5618d QL |
1304 | if (!sirfport->hw_flow_ctrl) |
1305 | goto usp_no_flow_control; | |
af99c187 GU |
1306 | if (of_find_property(np, "cts-gpios", NULL)) |
1307 | sirfport->cts_gpio = | |
1308 | of_get_named_gpio(np, "cts-gpios", 0); | |
2eb5618d QL |
1309 | else |
1310 | sirfport->cts_gpio = -1; | |
af99c187 GU |
1311 | if (of_find_property(np, "rts-gpios", NULL)) |
1312 | sirfport->rts_gpio = | |
1313 | of_get_named_gpio(np, "rts-gpios", 0); | |
2eb5618d QL |
1314 | else |
1315 | sirfport->rts_gpio = -1; | |
1316 | ||
1317 | if ((!gpio_is_valid(sirfport->cts_gpio) || | |
1318 | !gpio_is_valid(sirfport->rts_gpio))) { | |
1319 | ret = -EINVAL; | |
1320 | dev_err(&pdev->dev, | |
67bc306c | 1321 | "Usp flow control must have cts and rts gpio"); |
2eb5618d QL |
1322 | goto err; |
1323 | } | |
1324 | ret = devm_gpio_request(&pdev->dev, sirfport->cts_gpio, | |
67bc306c | 1325 | "usp-cts-gpio"); |
2eb5618d | 1326 | if (ret) { |
67bc306c | 1327 | dev_err(&pdev->dev, "Unable request cts gpio"); |
2eb5618d QL |
1328 | goto err; |
1329 | } | |
1330 | gpio_direction_input(sirfport->cts_gpio); | |
1331 | ret = devm_gpio_request(&pdev->dev, sirfport->rts_gpio, | |
67bc306c | 1332 | "usp-rts-gpio"); |
2eb5618d | 1333 | if (ret) { |
67bc306c | 1334 | dev_err(&pdev->dev, "Unable request rts gpio"); |
2eb5618d QL |
1335 | goto err; |
1336 | } | |
1337 | gpio_direction_output(sirfport->rts_gpio, 1); | |
1338 | } | |
1339 | usp_no_flow_control: | |
af99c187 GU |
1340 | if (of_device_is_compatible(np, "sirf,atlas7-uart") || |
1341 | of_device_is_compatible(np, "sirf,atlas7-usp-uart")) | |
057badd6 | 1342 | sirfport->is_atlas7 = true; |
909102db | 1343 | |
af99c187 | 1344 | if (of_property_read_u32(np, "fifosize", &port->fifosize)) { |
161e773c RW |
1345 | dev_err(&pdev->dev, |
1346 | "Unable to find fifosize in uart node.\n"); | |
1347 | ret = -EFAULT; | |
1348 | goto err; | |
1349 | } | |
1350 | ||
1351 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1352 | if (res == NULL) { | |
1353 | dev_err(&pdev->dev, "Insufficient resources.\n"); | |
1354 | ret = -EFAULT; | |
1355 | goto err; | |
1356 | } | |
1357 | port->mapbase = res->start; | |
0f17e3b4 QL |
1358 | port->membase = devm_ioremap(&pdev->dev, |
1359 | res->start, resource_size(res)); | |
161e773c RW |
1360 | if (!port->membase) { |
1361 | dev_err(&pdev->dev, "Cannot remap resource.\n"); | |
1362 | ret = -ENOMEM; | |
1363 | goto err; | |
1364 | } | |
1365 | res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); | |
1366 | if (res == NULL) { | |
1367 | dev_err(&pdev->dev, "Insufficient resources.\n"); | |
1368 | ret = -EFAULT; | |
9250dd57 | 1369 | goto err; |
161e773c RW |
1370 | } |
1371 | port->irq = res->start; | |
1372 | ||
adeede73 | 1373 | sirfport->clk = devm_clk_get(&pdev->dev, NULL); |
ac4ce718 BS |
1374 | if (IS_ERR(sirfport->clk)) { |
1375 | ret = PTR_ERR(sirfport->clk); | |
a343756e | 1376 | goto err; |
ac4ce718 | 1377 | } |
ac4ce718 BS |
1378 | port->uartclk = clk_get_rate(sirfport->clk); |
1379 | ||
161e773c RW |
1380 | port->ops = &sirfsoc_uart_ops; |
1381 | spin_lock_init(&port->lock); | |
1382 | ||
1383 | platform_set_drvdata(pdev, sirfport); | |
1384 | ret = uart_add_one_port(&sirfsoc_uart_drv, port); | |
1385 | if (ret != 0) { | |
1386 | dev_err(&pdev->dev, "Cannot add UART port(%d).\n", pdev->id); | |
adeede73 | 1387 | goto err; |
161e773c RW |
1388 | } |
1389 | ||
9be16b38 | 1390 | sirfport->rx_dma_chan = dma_request_slave_channel(port->dev, "rx"); |
0f17e3b4 QL |
1391 | sirfport->rx_dma_items.xmit.buf = |
1392 | dma_alloc_coherent(port->dev, SIRFSOC_RX_DMA_BUF_SIZE, | |
1393 | &sirfport->rx_dma_items.dma_addr, GFP_KERNEL); | |
1394 | if (!sirfport->rx_dma_items.xmit.buf) { | |
1395 | dev_err(port->dev, "Uart alloc bufa failed\n"); | |
1396 | ret = -ENOMEM; | |
1397 | goto alloc_coherent_err; | |
9be16b38 | 1398 | } |
0f17e3b4 QL |
1399 | sirfport->rx_dma_items.xmit.head = |
1400 | sirfport->rx_dma_items.xmit.tail = 0; | |
9be16b38 QL |
1401 | if (sirfport->rx_dma_chan) |
1402 | dmaengine_slave_config(sirfport->rx_dma_chan, &slv_cfg); | |
1403 | sirfport->tx_dma_chan = dma_request_slave_channel(port->dev, "tx"); | |
1404 | if (sirfport->tx_dma_chan) | |
1405 | dmaengine_slave_config(sirfport->tx_dma_chan, &tx_slv_cfg); | |
0f17e3b4 QL |
1406 | if (sirfport->rx_dma_chan) { |
1407 | hrtimer_init(&sirfport->hrt, CLOCK_MONOTONIC, HRTIMER_MODE_REL); | |
1408 | sirfport->hrt.function = sirfsoc_uart_rx_dma_hrtimer_callback; | |
1409 | sirfport->is_hrt_enabled = false; | |
1410 | } | |
161e773c | 1411 | |
9be16b38 QL |
1412 | return 0; |
1413 | alloc_coherent_err: | |
0f17e3b4 QL |
1414 | dma_free_coherent(port->dev, SIRFSOC_RX_DMA_BUF_SIZE, |
1415 | sirfport->rx_dma_items.xmit.buf, | |
1416 | sirfport->rx_dma_items.dma_addr); | |
9be16b38 | 1417 | dma_release_channel(sirfport->rx_dma_chan); |
161e773c RW |
1418 | err: |
1419 | return ret; | |
1420 | } | |
1421 | ||
1422 | static int sirfsoc_uart_remove(struct platform_device *pdev) | |
1423 | { | |
1424 | struct sirfsoc_uart_port *sirfport = platform_get_drvdata(pdev); | |
1425 | struct uart_port *port = &sirfport->port; | |
161e773c | 1426 | uart_remove_one_port(&sirfsoc_uart_drv, port); |
9be16b38 | 1427 | if (sirfport->rx_dma_chan) { |
9be16b38 QL |
1428 | dmaengine_terminate_all(sirfport->rx_dma_chan); |
1429 | dma_release_channel(sirfport->rx_dma_chan); | |
0f17e3b4 QL |
1430 | dma_free_coherent(port->dev, SIRFSOC_RX_DMA_BUF_SIZE, |
1431 | sirfport->rx_dma_items.xmit.buf, | |
1432 | sirfport->rx_dma_items.dma_addr); | |
9be16b38 QL |
1433 | } |
1434 | if (sirfport->tx_dma_chan) { | |
1435 | dmaengine_terminate_all(sirfport->tx_dma_chan); | |
1436 | dma_release_channel(sirfport->tx_dma_chan); | |
1437 | } | |
161e773c RW |
1438 | return 0; |
1439 | } | |
1440 | ||
99e626f5 | 1441 | #ifdef CONFIG_PM_SLEEP |
161e773c | 1442 | static int |
99e626f5 | 1443 | sirfsoc_uart_suspend(struct device *pdev) |
161e773c | 1444 | { |
99e626f5 | 1445 | struct sirfsoc_uart_port *sirfport = dev_get_drvdata(pdev); |
161e773c RW |
1446 | struct uart_port *port = &sirfport->port; |
1447 | uart_suspend_port(&sirfsoc_uart_drv, port); | |
1448 | return 0; | |
1449 | } | |
1450 | ||
99e626f5 | 1451 | static int sirfsoc_uart_resume(struct device *pdev) |
161e773c | 1452 | { |
99e626f5 | 1453 | struct sirfsoc_uart_port *sirfport = dev_get_drvdata(pdev); |
161e773c RW |
1454 | struct uart_port *port = &sirfport->port; |
1455 | uart_resume_port(&sirfsoc_uart_drv, port); | |
1456 | return 0; | |
1457 | } | |
99e626f5 QL |
1458 | #endif |
1459 | ||
1460 | static const struct dev_pm_ops sirfsoc_uart_pm_ops = { | |
1461 | SET_SYSTEM_SLEEP_PM_OPS(sirfsoc_uart_suspend, sirfsoc_uart_resume) | |
1462 | }; | |
161e773c | 1463 | |
161e773c RW |
1464 | static struct platform_driver sirfsoc_uart_driver = { |
1465 | .probe = sirfsoc_uart_probe, | |
2d47b716 | 1466 | .remove = sirfsoc_uart_remove, |
161e773c RW |
1467 | .driver = { |
1468 | .name = SIRFUART_PORT_NAME, | |
161e773c | 1469 | .of_match_table = sirfsoc_uart_ids, |
99e626f5 | 1470 | .pm = &sirfsoc_uart_pm_ops, |
161e773c RW |
1471 | }, |
1472 | }; | |
1473 | ||
1474 | static int __init sirfsoc_uart_init(void) | |
1475 | { | |
1476 | int ret = 0; | |
1477 | ||
1478 | ret = uart_register_driver(&sirfsoc_uart_drv); | |
1479 | if (ret) | |
1480 | goto out; | |
1481 | ||
1482 | ret = platform_driver_register(&sirfsoc_uart_driver); | |
1483 | if (ret) | |
1484 | uart_unregister_driver(&sirfsoc_uart_drv); | |
1485 | out: | |
1486 | return ret; | |
1487 | } | |
1488 | module_init(sirfsoc_uart_init); | |
1489 | ||
1490 | static void __exit sirfsoc_uart_exit(void) | |
1491 | { | |
1492 | platform_driver_unregister(&sirfsoc_uart_driver); | |
1493 | uart_unregister_driver(&sirfsoc_uart_drv); | |
1494 | } | |
1495 | module_exit(sirfsoc_uart_exit); | |
1496 | ||
1497 | MODULE_LICENSE("GPL v2"); | |
1498 | MODULE_AUTHOR("Bin Shi <Bin.Shi@csr.com>, Rong Wang<Rong.Wang@csr.com>"); | |
1499 | MODULE_DESCRIPTION("CSR SiRFprimaII Uart Driver"); |