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Merge tag 'hsi-for-4.18' of git://git.kernel.org/pub/scm/linux/kernel/git/sre/linux-hsi
[linux-2.6-block.git] / drivers / tty / serial / sirfsoc_uart.c
CommitLineData
e3b3d0f5 1// SPDX-License-Identifier: GPL-2.0+
161e773c
RW		 2/*
3 * Driver for CSR SiRFprimaII onboard UARTs.
4 *
5 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
161e773c
RW		 6 */
7
8#include <linux/module.h>
9#include <linux/ioport.h>
10#include <linux/platform_device.h>
11#include <linux/init.h>
12#include <linux/sysrq.h>
13#include <linux/console.h>
14#include <linux/tty.h>
15#include <linux/tty_flip.h>
16#include <linux/serial_core.h>
17#include <linux/serial.h>
18#include <linux/clk.h>
19#include <linux/of.h>
20#include <linux/slab.h>
21#include <linux/io.h>
2eb5618d 22#include <linux/of_gpio.h>
8316d04c
QL		 23#include <linux/dmaengine.h>
24#include <linux/dma-direction.h>
25#include <linux/dma-mapping.h>
161e773c
RW		 26#include <asm/irq.h>
27#include <asm/mach/irq.h>
161e773c
RW		 28
29#include "sirfsoc_uart.h"
30
31static unsigned int
32sirfsoc_uart_pio_tx_chars(struct sirfsoc_uart_port *sirfport, int count);
33static unsigned int
34sirfsoc_uart_pio_rx_chars(struct uart_port *port, unsigned int max_rx_count);
35static struct uart_driver sirfsoc_uart_drv;
36
8316d04c 37static void sirfsoc_uart_tx_dma_complete_callback(void *param);
161e773c
RW		 38static const struct sirfsoc_baudrate_to_regv baudrate_to_regv[] = {
39 {4000000, 2359296},
40 {3500000, 1310721},
41 {3000000, 1572865},
42 {2500000, 1245186},
43 {2000000, 1572866},
44 {1500000, 1245188},
45 {1152000, 1638404},
46 {1000000, 1572869},
47 {921600, 1114120},
48 {576000, 1245196},
49 {500000, 1245198},
50 {460800, 1572876},
51 {230400, 1310750},
52 {115200, 1310781},
53 {57600, 1310843},
54 {38400, 1114328},
55 {19200, 1114545},
56 {9600, 1114979},
57};
58
a6ffe896 59static struct sirfsoc_uart_port *sirf_ports[SIRFSOC_UART_NR];
161e773c
RW		 60
61static inline struct sirfsoc_uart_port *to_sirfport(struct uart_port *port)
62{
63 return container_of(port, struct sirfsoc_uart_port, port);
64}
65
66static inline unsigned int sirfsoc_uart_tx_empty(struct uart_port *port)
67{
68 unsigned long reg;
5df83111
QL		 69 struct sirfsoc_uart_port *sirfport = to_sirfport(port);
70 struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
71 struct sirfsoc_fifo_status *ufifo_st = &sirfport->uart_reg->fifo_status;
72 reg = rd_regl(port, ureg->sirfsoc_tx_fifo_status);
cb4595a2 73 return (reg & ufifo_st->ff_empty(port)) ? TIOCSER_TEMT : 0;
161e773c
RW		 74}
75
76static unsigned int sirfsoc_uart_get_mctrl(struct uart_port *port)
77{
78 struct sirfsoc_uart_port *sirfport = to_sirfport(port);
5df83111 79 struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
2eb5618d 80 if (!sirfport->hw_flow_ctrl || !sirfport->ms_enabled)
161e773c 81 goto cts_asserted;
2eb5618d 82 if (sirfport->uart_reg->uart_type == SIRF_REAL_UART) {
5df83111
QL		 83 if (!(rd_regl(port, ureg->sirfsoc_afc_ctrl) &
84 SIRFUART_AFC_CTS_STATUS))
161e773c
RW		 85 goto cts_asserted;
86 else
87 goto cts_deasserted;
2eb5618d
QL		 88 } else {
89 if (!gpio_get_value(sirfport->cts_gpio))
90 goto cts_asserted;
91 else
92 goto cts_deasserted;
161e773c
RW		 93 }
94cts_deasserted:
95 return TIOCM_CAR | TIOCM_DSR;
96cts_asserted:
97 return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
98}
99
100static void sirfsoc_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
101{
102 struct sirfsoc_uart_port *sirfport = to_sirfport(port);
5df83111 103 struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
161e773c
RW		 104 unsigned int assert = mctrl & TIOCM_RTS;
105 unsigned int val = assert ? SIRFUART_AFC_CTRL_RX_THD : 0x0;
106 unsigned int current_val;
2eb5618d 107
7f60f2fe
QL		 108 if (mctrl & TIOCM_LOOP) {
109 if (sirfport->uart_reg->uart_type == SIRF_REAL_UART)
110 wr_regl(port, ureg->sirfsoc_line_ctrl,
111 rd_regl(port, ureg->sirfsoc_line_ctrl) |
112 SIRFUART_LOOP_BACK);
113 else
114 wr_regl(port, ureg->sirfsoc_mode1,
115 rd_regl(port, ureg->sirfsoc_mode1) |
116 SIRFSOC_USP_LOOP_BACK_CTRL);
117 } else {
118 if (sirfport->uart_reg->uart_type == SIRF_REAL_UART)
119 wr_regl(port, ureg->sirfsoc_line_ctrl,
120 rd_regl(port, ureg->sirfsoc_line_ctrl) &
121 ~SIRFUART_LOOP_BACK);
122 else
123 wr_regl(port, ureg->sirfsoc_mode1,
124 rd_regl(port, ureg->sirfsoc_mode1) &
125 ~SIRFSOC_USP_LOOP_BACK_CTRL);
126 }
127
2eb5618d
QL		 128 if (!sirfport->hw_flow_ctrl || !sirfport->ms_enabled)
129 return;
130 if (sirfport->uart_reg->uart_type == SIRF_REAL_UART) {
5df83111 131 current_val = rd_regl(port, ureg->sirfsoc_afc_ctrl) & ~0xFF;
161e773c 132 val |= current_val;
5df83111 133 wr_regl(port, ureg->sirfsoc_afc_ctrl, val);
2eb5618d
QL		 134 } else {
135 if (!val)
136 gpio_set_value(sirfport->rts_gpio, 1);
137 else
138 gpio_set_value(sirfport->rts_gpio, 0);
161e773c
RW		 139 }
140}
141
142static void sirfsoc_uart_stop_tx(struct uart_port *port)
143{
909102db 144 struct sirfsoc_uart_port *sirfport = to_sirfport(port);
5df83111
QL		 145 struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
146 struct sirfsoc_int_en *uint_en = &sirfport->uart_reg->uart_int_en;
909102db 147
9be16b38 148 if (sirfport->tx_dma_chan) {
8316d04c
QL		 149 if (sirfport->tx_dma_state == TX_DMA_RUNNING) {
150 dmaengine_pause(sirfport->tx_dma_chan);
151 sirfport->tx_dma_state = TX_DMA_PAUSE;
152 } else {
057badd6 153 if (!sirfport->is_atlas7)
8316d04c
QL		 154 wr_regl(port, ureg->sirfsoc_int_en_reg,
155 rd_regl(port, ureg->sirfsoc_int_en_reg) &
156 ~uint_en->sirfsoc_txfifo_empty_en);
157 else
c1b7ac6f 158 wr_regl(port, ureg->sirfsoc_int_en_clr_reg,
8316d04c
QL		 159 uint_en->sirfsoc_txfifo_empty_en);
160 }
161 } else {
c1b7ac6f
QL		 162 if (sirfport->uart_reg->uart_type == SIRF_USP_UART)
163 wr_regl(port, ureg->sirfsoc_tx_rx_en, rd_regl(port,
164 ureg->sirfsoc_tx_rx_en) & ~SIRFUART_TX_EN);
057badd6 165 if (!sirfport->is_atlas7)
8316d04c
QL		 166 wr_regl(port, ureg->sirfsoc_int_en_reg,
167 rd_regl(port, ureg->sirfsoc_int_en_reg) &
168 ~uint_en->sirfsoc_txfifo_empty_en);
169 else
c1b7ac6f 170 wr_regl(port, ureg->sirfsoc_int_en_clr_reg,
8316d04c
QL		 171 uint_en->sirfsoc_txfifo_empty_en);
172 }
173}
174
175static void sirfsoc_uart_tx_with_dma(struct sirfsoc_uart_port *sirfport)
176{
177 struct uart_port *port = &sirfport->port;
178 struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
179 struct sirfsoc_int_en *uint_en = &sirfport->uart_reg->uart_int_en;
180 struct circ_buf *xmit = &port->state->xmit;
181 unsigned long tran_size;
182 unsigned long tran_start;
183 unsigned long pio_tx_size;
184
185 tran_size = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
186 tran_start = (unsigned long)(xmit->buf + xmit->tail);
187 if (uart_circ_empty(xmit) || uart_tx_stopped(port) ||
188 !tran_size)
189 return;
190 if (sirfport->tx_dma_state == TX_DMA_PAUSE) {
191 dmaengine_resume(sirfport->tx_dma_chan);
192 return;
193 }
194 if (sirfport->tx_dma_state == TX_DMA_RUNNING)
195 return;
057badd6 196 if (!sirfport->is_atlas7)
5df83111 197 wr_regl(port, ureg->sirfsoc_int_en_reg,
8316d04c
QL		 198 rd_regl(port, ureg->sirfsoc_int_en_reg)&
199 ~(uint_en->sirfsoc_txfifo_empty_en));
200 else
c1b7ac6f 201 wr_regl(port, ureg->sirfsoc_int_en_clr_reg,
5df83111 202 uint_en->sirfsoc_txfifo_empty_en);
8316d04c
QL		 203 /*
204 * DMA requires buffer address and buffer length are both aligned with
205 * 4 bytes, so we use PIO for
206 * 1. if address is not aligned with 4bytes, use PIO for the first 1~3
207 * bytes, and move to DMA for the left part aligned with 4bytes
208 * 2. if buffer length is not aligned with 4bytes, use DMA for aligned
209 * part first, move to PIO for the left 1~3 bytes
210 */
211 if (tran_size < 4 || BYTES_TO_ALIGN(tran_start)) {
212 wr_regl(port, ureg->sirfsoc_tx_fifo_op, SIRFUART_FIFO_STOP);
213 wr_regl(port, ureg->sirfsoc_tx_dma_io_ctrl,
214 rd_regl(port, ureg->sirfsoc_tx_dma_io_ctrl)|
215 SIRFUART_IO_MODE);
216 if (BYTES_TO_ALIGN(tran_start)) {
217 pio_tx_size = sirfsoc_uart_pio_tx_chars(sirfport,
218 BYTES_TO_ALIGN(tran_start));
219 tran_size -= pio_tx_size;
220 }
221 if (tran_size < 4)
222 sirfsoc_uart_pio_tx_chars(sirfport, tran_size);
057badd6 223 if (!sirfport->is_atlas7)
8316d04c
QL		 224 wr_regl(port, ureg->sirfsoc_int_en_reg,
225 rd_regl(port, ureg->sirfsoc_int_en_reg)|
226 uint_en->sirfsoc_txfifo_empty_en);
227 else
228 wr_regl(port, ureg->sirfsoc_int_en_reg,
229 uint_en->sirfsoc_txfifo_empty_en);
230 wr_regl(port, ureg->sirfsoc_tx_fifo_op, SIRFUART_FIFO_START);
231 } else {
232 /* tx transfer mode switch into dma mode */
233 wr_regl(port, ureg->sirfsoc_tx_fifo_op, SIRFUART_FIFO_STOP);
234 wr_regl(port, ureg->sirfsoc_tx_dma_io_ctrl,
235 rd_regl(port, ureg->sirfsoc_tx_dma_io_ctrl)&
236 ~SIRFUART_IO_MODE);
237 wr_regl(port, ureg->sirfsoc_tx_fifo_op, SIRFUART_FIFO_START);
238 tran_size &= ~(0x3);
239
240 sirfport->tx_dma_addr = dma_map_single(port->dev,
241 xmit->buf + xmit->tail,
242 tran_size, DMA_TO_DEVICE);
243 sirfport->tx_dma_desc = dmaengine_prep_slave_single(
244 sirfport->tx_dma_chan, sirfport->tx_dma_addr,
245 tran_size, DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
246 if (!sirfport->tx_dma_desc) {
247 dev_err(port->dev, "DMA prep slave single fail\n");
248 return;
249 }
250 sirfport->tx_dma_desc->callback =
251 sirfsoc_uart_tx_dma_complete_callback;
252 sirfport->tx_dma_desc->callback_param = (void *)sirfport;
253 sirfport->transfer_size = tran_size;
254
255 dmaengine_submit(sirfport->tx_dma_desc);
256 dma_async_issue_pending(sirfport->tx_dma_chan);
257 sirfport->tx_dma_state = TX_DMA_RUNNING;
258 }
161e773c
RW		 259}
260
ada1f443 261static void sirfsoc_uart_start_tx(struct uart_port *port)
161e773c
RW		 262{
263 struct sirfsoc_uart_port *sirfport = to_sirfport(port);
5df83111
QL		 264 struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
265 struct sirfsoc_int_en *uint_en = &sirfport->uart_reg->uart_int_en;
9be16b38 266 if (sirfport->tx_dma_chan)
8316d04c
QL		 267 sirfsoc_uart_tx_with_dma(sirfport);
268 else {
c1b7ac6f
QL		 269 if (sirfport->uart_reg->uart_type == SIRF_USP_UART)
270 wr_regl(port, ureg->sirfsoc_tx_rx_en, rd_regl(port,
271 ureg->sirfsoc_tx_rx_en) | SIRFUART_TX_EN);
326707ed 272 wr_regl(port, ureg->sirfsoc_tx_fifo_op, SIRFUART_FIFO_STOP);
cb4595a2 273 sirfsoc_uart_pio_tx_chars(sirfport, port->fifosize);
8316d04c 274 wr_regl(port, ureg->sirfsoc_tx_fifo_op, SIRFUART_FIFO_START);
057badd6 275 if (!sirfport->is_atlas7)
8316d04c
QL		 276 wr_regl(port, ureg->sirfsoc_int_en_reg,
277 rd_regl(port, ureg->sirfsoc_int_en_reg)|
278 uint_en->sirfsoc_txfifo_empty_en);
279 else
280 wr_regl(port, ureg->sirfsoc_int_en_reg,
281 uint_en->sirfsoc_txfifo_empty_en);
282 }
161e773c
RW		 283}
284
285static void sirfsoc_uart_stop_rx(struct uart_port *port)
286{
909102db 287 struct sirfsoc_uart_port *sirfport = to_sirfport(port);
5df83111
QL		 288 struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
289 struct sirfsoc_int_en *uint_en = &sirfport->uart_reg->uart_int_en;
8316d04c 290
5df83111 291 wr_regl(port, ureg->sirfsoc_rx_fifo_op, 0);
9be16b38 292 if (sirfport->rx_dma_chan) {
057badd6 293 if (!sirfport->is_atlas7)
8316d04c
QL		 294 wr_regl(port, ureg->sirfsoc_int_en_reg,
295 rd_regl(port, ureg->sirfsoc_int_en_reg) &
c1b7ac6f
QL		 296 ~(SIRFUART_RX_DMA_INT_EN(uint_en,
297 sirfport->uart_reg->uart_type) |
8316d04c
QL		 298 uint_en->sirfsoc_rx_done_en));
299 else
c1b7ac6f
QL		 300 wr_regl(port, ureg->sirfsoc_int_en_clr_reg,
301 SIRFUART_RX_DMA_INT_EN(uint_en,
302 sirfport->uart_reg->uart_type)|
303 uint_en->sirfsoc_rx_done_en);
8316d04c
QL		 304 dmaengine_terminate_all(sirfport->rx_dma_chan);
305 } else {
057badd6 306 if (!sirfport->is_atlas7)
8316d04c
QL		 307 wr_regl(port, ureg->sirfsoc_int_en_reg,
308 rd_regl(port, ureg->sirfsoc_int_en_reg)&
c1b7ac6f
QL		 309 ~(SIRFUART_RX_IO_INT_EN(uint_en,
310 sirfport->uart_reg->uart_type)));
8316d04c 311 else
c1b7ac6f
QL		 312 wr_regl(port, ureg->sirfsoc_int_en_clr_reg,
313 SIRFUART_RX_IO_INT_EN(uint_en,
314 sirfport->uart_reg->uart_type));
8316d04c 315 }
161e773c
RW		 316}
317
318static void sirfsoc_uart_disable_ms(struct uart_port *port)
319{
320 struct sirfsoc_uart_port *sirfport = to_sirfport(port);
5df83111
QL		 321 struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
322 struct sirfsoc_int_en *uint_en = &sirfport->uart_reg->uart_int_en;
909102db 323
161e773c
RW		 324 if (!sirfport->hw_flow_ctrl)
325 return;
2eb5618d
QL		 326 sirfport->ms_enabled = false;
327 if (sirfport->uart_reg->uart_type == SIRF_REAL_UART) {
328 wr_regl(port, ureg->sirfsoc_afc_ctrl,
329 rd_regl(port, ureg->sirfsoc_afc_ctrl) & ~0x3FF);
057badd6 330 if (!sirfport->is_atlas7)
2eb5618d
QL		 331 wr_regl(port, ureg->sirfsoc_int_en_reg,
332 rd_regl(port, ureg->sirfsoc_int_en_reg)&
333 ~uint_en->sirfsoc_cts_en);
334 else
c1b7ac6f 335 wr_regl(port, ureg->sirfsoc_int_en_clr_reg,
2eb5618d 336 uint_en->sirfsoc_cts_en);
5df83111 337 } else
2eb5618d
QL		 338 disable_irq(gpio_to_irq(sirfport->cts_gpio));
339}
340
341static irqreturn_t sirfsoc_uart_usp_cts_handler(int irq, void *dev_id)
342{
343 struct sirfsoc_uart_port *sirfport = (struct sirfsoc_uart_port *)dev_id;
344 struct uart_port *port = &sirfport->port;
07d410e0 345 spin_lock(&port->lock);
2eb5618d
QL		 346 if (gpio_is_valid(sirfport->cts_gpio) && sirfport->ms_enabled)
347 uart_handle_cts_change(port,
348 !gpio_get_value(sirfport->cts_gpio));
07d410e0 349 spin_unlock(&port->lock);
2eb5618d 350 return IRQ_HANDLED;
161e773c
RW		 351}
352
353static void sirfsoc_uart_enable_ms(struct uart_port *port)
354{
355 struct sirfsoc_uart_port *sirfport = to_sirfport(port);
5df83111
QL		 356 struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
357 struct sirfsoc_int_en *uint_en = &sirfport->uart_reg->uart_int_en;
909102db 358
161e773c
RW		 359 if (!sirfport->hw_flow_ctrl)
360 return;
2eb5618d
QL		 361 sirfport->ms_enabled = true;
362 if (sirfport->uart_reg->uart_type == SIRF_REAL_UART) {
363 wr_regl(port, ureg->sirfsoc_afc_ctrl,
364 rd_regl(port, ureg->sirfsoc_afc_ctrl) |
eab192ae
QL		 365 SIRFUART_AFC_TX_EN | SIRFUART_AFC_RX_EN |
366 SIRFUART_AFC_CTRL_RX_THD);
057badd6 367 if (!sirfport->is_atlas7)
2eb5618d
QL		 368 wr_regl(port, ureg->sirfsoc_int_en_reg,
369 rd_regl(port, ureg->sirfsoc_int_en_reg)
370 | uint_en->sirfsoc_cts_en);
371 else
372 wr_regl(port, ureg->sirfsoc_int_en_reg,
373 uint_en->sirfsoc_cts_en);
5df83111 374 } else
2eb5618d 375 enable_irq(gpio_to_irq(sirfport->cts_gpio));
161e773c
RW		 376}
377
378static void sirfsoc_uart_break_ctl(struct uart_port *port, int break_state)
379{
5df83111
QL		 380 struct sirfsoc_uart_port *sirfport = to_sirfport(port);
381 struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
382 if (sirfport->uart_reg->uart_type == SIRF_REAL_UART) {
383 unsigned long ulcon = rd_regl(port, ureg->sirfsoc_line_ctrl);
384 if (break_state)
385 ulcon |= SIRFUART_SET_BREAK;
386 else
387 ulcon &= ~SIRFUART_SET_BREAK;
388 wr_regl(port, ureg->sirfsoc_line_ctrl, ulcon);
389 }
161e773c
RW		 390}
391
392static unsigned int
393sirfsoc_uart_pio_rx_chars(struct uart_port *port, unsigned int max_rx_count)
394{
5df83111
QL		 395 struct sirfsoc_uart_port *sirfport = to_sirfport(port);
396 struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
397 struct sirfsoc_fifo_status *ufifo_st = &sirfport->uart_reg->fifo_status;
161e773c 398 unsigned int ch, rx_count = 0;
5df83111
QL		 399 struct tty_struct *tty;
400 tty = tty_port_tty_get(&port->state->port);
401 if (!tty)
402 return -ENODEV;
403 while (!(rd_regl(port, ureg->sirfsoc_rx_fifo_status) &
cb4595a2 404 ufifo_st->ff_empty(port))) {
5df83111
QL		 405 ch = rd_regl(port, ureg->sirfsoc_rx_fifo_data) |
406 SIRFUART_DUMMY_READ;
161e773c
RW		 407 if (unlikely(uart_handle_sysrq_char(port, ch)))
408 continue;
409 uart_insert_char(port, 0, 0, ch, TTY_NORMAL);
410 rx_count++;
411 if (rx_count >= max_rx_count)
412 break;
413 }
414
415 port->icount.rx += rx_count;
8b9ade9f 416
161e773c
RW		 417 return rx_count;
418}
419
420static unsigned int
421sirfsoc_uart_pio_tx_chars(struct sirfsoc_uart_port *sirfport, int count)
422{
423 struct uart_port *port = &sirfport->port;
5df83111
QL		 424 struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
425 struct sirfsoc_fifo_status *ufifo_st = &sirfport->uart_reg->fifo_status;
161e773c
RW		 426 struct circ_buf *xmit = &port->state->xmit;
427 unsigned int num_tx = 0;
428 while (!uart_circ_empty(xmit) &&
5df83111 429 !(rd_regl(port, ureg->sirfsoc_tx_fifo_status) &
cb4595a2 430 ufifo_st->ff_full(port)) &&
161e773c 431 count--) {
5df83111
QL		 432 wr_regl(port, ureg->sirfsoc_tx_fifo_data,
433 xmit->buf[xmit->tail]);
161e773c
RW		 434 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
435 port->icount.tx++;
436 num_tx++;
437 }
438 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
439 uart_write_wakeup(port);
440 return num_tx;
441}
442
8316d04c
QL		 443static void sirfsoc_uart_tx_dma_complete_callback(void *param)
444{
445 struct sirfsoc_uart_port *sirfport = (struct sirfsoc_uart_port *)param;
446 struct uart_port *port = &sirfport->port;
447 struct circ_buf *xmit = &port->state->xmit;
448 unsigned long flags;
449
07d410e0 450 spin_lock_irqsave(&port->lock, flags);
8316d04c
QL		 451 xmit->tail = (xmit->tail + sirfport->transfer_size) &
452 (UART_XMIT_SIZE - 1);
453 port->icount.tx += sirfport->transfer_size;
454 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
455 uart_write_wakeup(port);
456 if (sirfport->tx_dma_addr)
457 dma_unmap_single(port->dev, sirfport->tx_dma_addr,
458 sirfport->transfer_size, DMA_TO_DEVICE);
8316d04c
QL		 459 sirfport->tx_dma_state = TX_DMA_IDLE;
460 sirfsoc_uart_tx_with_dma(sirfport);
07d410e0 461 spin_unlock_irqrestore(&port->lock, flags);
8316d04c
QL		 462}
463
161e773c
RW		 464static irqreturn_t sirfsoc_uart_isr(int irq, void *dev_id)
465{
466 unsigned long intr_status;
467 unsigned long cts_status;
468 unsigned long flag = TTY_NORMAL;
469 struct sirfsoc_uart_port *sirfport = (struct sirfsoc_uart_port *)dev_id;
470 struct uart_port *port = &sirfport->port;
5df83111
QL		 471 struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
472 struct sirfsoc_fifo_status *ufifo_st = &sirfport->uart_reg->fifo_status;
473 struct sirfsoc_int_status *uint_st = &sirfport->uart_reg->uart_int_st;
474 struct sirfsoc_int_en *uint_en = &sirfport->uart_reg->uart_int_en;
161e773c
RW		 475 struct uart_state *state = port->state;
476 struct circ_buf *xmit = &port->state->xmit;
5425e03f 477 spin_lock(&port->lock);
5df83111
QL		 478 intr_status = rd_regl(port, ureg->sirfsoc_int_st_reg);
479 wr_regl(port, ureg->sirfsoc_int_st_reg, intr_status);
8316d04c 480 intr_status &= rd_regl(port, ureg->sirfsoc_int_en_reg);
c1b7ac6f
QL		 481 if (unlikely(intr_status & (SIRFUART_ERR_INT_STAT(uint_st,
482 sirfport->uart_reg->uart_type)))) {
5df83111
QL		 483 if (intr_status & uint_st->sirfsoc_rxd_brk) {
484 port->icount.brk++;
161e773c
RW		 485 if (uart_handle_break(port))
486 goto recv_char;
161e773c 487 }
d9e8e976 488 if (intr_status & uint_st->sirfsoc_rx_oflow) {
161e773c 489 port->icount.overrun++;
d9e8e976
QL		 490 flag = TTY_OVERRUN;
491 }
5df83111 492 if (intr_status & uint_st->sirfsoc_frm_err) {
161e773c
RW		 493 port->icount.frame++;
494 flag = TTY_FRAME;
495 }
d9e8e976
QL		 496 if (intr_status & uint_st->sirfsoc_parity_err) {
497 port->icount.parity++;
161e773c 498 flag = TTY_PARITY;
d9e8e976 499 }
5df83111
QL		 500 wr_regl(port, ureg->sirfsoc_rx_fifo_op, SIRFUART_FIFO_RESET);
501 wr_regl(port, ureg->sirfsoc_rx_fifo_op, 0);
502 wr_regl(port, ureg->sirfsoc_rx_fifo_op, SIRFUART_FIFO_START);
161e773c
RW		 503 intr_status &= port->read_status_mask;
504 uart_insert_char(port, intr_status,
5df83111 505 uint_en->sirfsoc_rx_oflow_en, 0, flag);
161e773c
RW		 506 }
507recv_char:
5df83111 508 if ((sirfport->uart_reg->uart_type == SIRF_REAL_UART) &&
8316d04c
QL		 509 (intr_status & SIRFUART_CTS_INT_ST(uint_st)) &&
510 !sirfport->tx_dma_state) {
5df83111
QL		 511 cts_status = rd_regl(port, ureg->sirfsoc_afc_ctrl) &
512 SIRFUART_AFC_CTS_STATUS;
513 if (cts_status != 0)
514 cts_status = 0;
515 else
516 cts_status = 1;
517 uart_handle_cts_change(port, cts_status);
518 wake_up_interruptible(&state->port.delta_msr_wait);
161e773c 519 }
0f17e3b4
QL		 520 if (!sirfport->rx_dma_chan &&
521 (intr_status & SIRFUART_RX_IO_INT_ST(uint_st))) {
c1b7ac6f
QL		 522 /*
523 * chip will trigger continuous RX_TIMEOUT interrupt
524 * in RXFIFO empty and not trigger if RXFIFO recevice
525 * data in limit time, original method use RX_TIMEOUT
526 * will trigger lots of useless interrupt in RXFIFO
527 * empty.RXFIFO received one byte will trigger RX_DONE
528 * interrupt.use RX_DONE to wait for data received
529 * into RXFIFO, use RX_THD/RX_FULL for lots data receive
530 * and use RX_TIMEOUT for the last left data.
531 */
532 if (intr_status & uint_st->sirfsoc_rx_done) {
533 if (!sirfport->is_atlas7) {
534 wr_regl(port, ureg->sirfsoc_int_en_reg,
535 rd_regl(port, ureg->sirfsoc_int_en_reg)
536 & ~(uint_en->sirfsoc_rx_done_en));
537 wr_regl(port, ureg->sirfsoc_int_en_reg,
538 rd_regl(port, ureg->sirfsoc_int_en_reg)
539 | (uint_en->sirfsoc_rx_timeout_en));
540 } else {
541 wr_regl(port, ureg->sirfsoc_int_en_clr_reg,
542 uint_en->sirfsoc_rx_done_en);
543 wr_regl(port, ureg->sirfsoc_int_en_reg,
544 uint_en->sirfsoc_rx_timeout_en);
545 }
546 } else {
547 if (intr_status & uint_st->sirfsoc_rx_timeout) {
548 if (!sirfport->is_atlas7) {
549 wr_regl(port, ureg->sirfsoc_int_en_reg,
550 rd_regl(port, ureg->sirfsoc_int_en_reg)
551 & ~(uint_en->sirfsoc_rx_timeout_en));
552 wr_regl(port, ureg->sirfsoc_int_en_reg,
553 rd_regl(port, ureg->sirfsoc_int_en_reg)
554 | (uint_en->sirfsoc_rx_done_en));
555 } else {
556 wr_regl(port,
557 ureg->sirfsoc_int_en_clr_reg,
558 uint_en->sirfsoc_rx_timeout_en);
559 wr_regl(port, ureg->sirfsoc_int_en_reg,
560 uint_en->sirfsoc_rx_done_en);
561 }
562 }
cb4595a2 563 sirfsoc_uart_pio_rx_chars(port, port->fifosize);
c1b7ac6f 564 }
8316d04c 565 }
07d410e0
QL		 566 spin_unlock(&port->lock);
567 tty_flip_buffer_push(&state->port);
568 spin_lock(&port->lock);
5df83111 569 if (intr_status & uint_st->sirfsoc_txfifo_empty) {
9be16b38 570 if (sirfport->tx_dma_chan)
8316d04c
QL		 571 sirfsoc_uart_tx_with_dma(sirfport);
572 else {
573 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
574 spin_unlock(&port->lock);
575 return IRQ_HANDLED;
576 } else {
577 sirfsoc_uart_pio_tx_chars(sirfport,
cb4595a2 578 port->fifosize);
8316d04c 579 if ((uart_circ_empty(xmit)) &&
5df83111 580 (rd_regl(port, ureg->sirfsoc_tx_fifo_status) &
cb4595a2 581 ufifo_st->ff_empty(port)))
8316d04c
QL		 582 sirfsoc_uart_stop_tx(port);
583 }
161e773c
RW		 584 }
585 }
5425e03f 586 spin_unlock(&port->lock);
07d410e0 587
161e773c
RW		 588 return IRQ_HANDLED;
589}
590
8316d04c
QL		 591static void sirfsoc_uart_rx_dma_complete_callback(void *param)
592{
8316d04c
QL		 593}
594
595/* submit rx dma task into dmaengine */
596static void sirfsoc_uart_start_next_rx_dma(struct uart_port *port)
161e773c 597{
909102db 598 struct sirfsoc_uart_port *sirfport = to_sirfport(port);
5df83111
QL		 599 struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
600 struct sirfsoc_int_en *uint_en = &sirfport->uart_reg->uart_int_en;
8316d04c
QL		 601 wr_regl(port, ureg->sirfsoc_rx_dma_io_ctrl,
602 rd_regl(port, ureg->sirfsoc_rx_dma_io_ctrl) &
603 ~SIRFUART_IO_MODE);
0f17e3b4
QL		 604 sirfport->rx_dma_items.xmit.tail =
605 sirfport->rx_dma_items.xmit.head = 0;
606 sirfport->rx_dma_items.desc =
607 dmaengine_prep_dma_cyclic(sirfport->rx_dma_chan,
608 sirfport->rx_dma_items.dma_addr, SIRFSOC_RX_DMA_BUF_SIZE,
609 SIRFSOC_RX_DMA_BUF_SIZE / 2,
610 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
611 if (IS_ERR_OR_NULL(sirfport->rx_dma_items.desc)) {
612 dev_err(port->dev, "DMA slave single fail\n");
613 return;
614 }
615 sirfport->rx_dma_items.desc->callback =
616 sirfsoc_uart_rx_dma_complete_callback;
617 sirfport->rx_dma_items.desc->callback_param = sirfport;
618 sirfport->rx_dma_items.cookie =
619 dmaengine_submit(sirfport->rx_dma_items.desc);
620 dma_async_issue_pending(sirfport->rx_dma_chan);
057badd6 621 if (!sirfport->is_atlas7)
5df83111 622 wr_regl(port, ureg->sirfsoc_int_en_reg,
8316d04c 623 rd_regl(port, ureg->sirfsoc_int_en_reg) |
c1b7ac6f
QL		 624 SIRFUART_RX_DMA_INT_EN(uint_en,
625 sirfport->uart_reg->uart_type));
8316d04c
QL		 626 else
627 wr_regl(port, ureg->sirfsoc_int_en_reg,
c1b7ac6f
QL		 628 SIRFUART_RX_DMA_INT_EN(uint_en,
629 sirfport->uart_reg->uart_type));
8316d04c
QL		 630}
631
5df83111
QL		 632static unsigned int
633sirfsoc_usp_calc_sample_div(unsigned long set_rate,
634 unsigned long ioclk_rate, unsigned long *sample_reg)
635{
636 unsigned long min_delta = ~0UL;
637 unsigned short sample_div;
638 unsigned long ioclk_div = 0;
639 unsigned long temp_delta;
640
cb4595a2 641 for (sample_div = SIRF_USP_MIN_SAMPLE_DIV;
5df83111
QL		 642 sample_div <= SIRF_MAX_SAMPLE_DIV; sample_div++) {
643 temp_delta = ioclk_rate -
644 (ioclk_rate + (set_rate * sample_div) / 2)
645 / (set_rate * sample_div) * set_rate * sample_div;
909102db 646
5df83111
QL		 647 temp_delta = (temp_delta > 0) ? temp_delta : -temp_delta;
648 if (temp_delta < min_delta) {
649 ioclk_div = (2 * ioclk_rate /
650 (set_rate * sample_div) + 1) / 2 - 1;
651 if (ioclk_div > SIRF_IOCLK_DIV_MAX)
652 continue;
653 min_delta = temp_delta;
654 *sample_reg = sample_div;
655 if (!temp_delta)
656 break;
657 }
658 }
659 return ioclk_div;
161e773c
RW		 660}
661
662static unsigned int
5df83111
QL		 663sirfsoc_uart_calc_sample_div(unsigned long baud_rate,
664 unsigned long ioclk_rate, unsigned long *set_baud)
161e773c
RW		 665{
666 unsigned long min_delta = ~0UL;
667 unsigned short sample_div;
668 unsigned int regv = 0;
669 unsigned long ioclk_div;
670 unsigned long baud_tmp;
671 int temp_delta;
672
673 for (sample_div = SIRF_MIN_SAMPLE_DIV;
674 sample_div <= SIRF_MAX_SAMPLE_DIV; sample_div++) {
675 ioclk_div = (ioclk_rate / (baud_rate * (sample_div + 1))) - 1;
676 if (ioclk_div > SIRF_IOCLK_DIV_MAX)
677 continue;
678 baud_tmp = ioclk_rate / ((ioclk_div + 1) * (sample_div + 1));
679 temp_delta = baud_tmp - baud_rate;
680 temp_delta = (temp_delta > 0) ? temp_delta : -temp_delta;
681 if (temp_delta < min_delta) {
682 regv = regv & (~SIRF_IOCLK_DIV_MASK);
683 regv = regv | ioclk_div;
684 regv = regv & (~SIRF_SAMPLE_DIV_MASK);
685 regv = regv | (sample_div << SIRF_SAMPLE_DIV_SHIFT);
686 min_delta = temp_delta;
5df83111 687 *set_baud = baud_tmp;
161e773c
RW		 688 }
689 }
690 return regv;
691}
692
693static void sirfsoc_uart_set_termios(struct uart_port *port,
694 struct ktermios *termios,
695 struct ktermios *old)
696{
697 struct sirfsoc_uart_port *sirfport = to_sirfport(port);
5df83111
QL		 698 struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
699 struct sirfsoc_int_en *uint_en = &sirfport->uart_reg->uart_int_en;
161e773c
RW		 700 unsigned long config_reg = 0;
701 unsigned long baud_rate;
5df83111 702 unsigned long set_baud;
161e773c
RW		 703 unsigned long flags;
704 unsigned long ic;
705 unsigned int clk_div_reg = 0;
8316d04c 706 unsigned long txfifo_op_reg, ioclk_rate;
161e773c
RW		 707 unsigned long rx_time_out;
708 int threshold_div;
5df83111
QL		 709 u32 data_bit_len, stop_bit_len, len_val;
710 unsigned long sample_div_reg = 0xf;
711 ioclk_rate = port->uartclk;
161e773c 712
161e773c
RW		 713 switch (termios->c_cflag & CSIZE) {
714 default:
715 case CS8:
5df83111 716 data_bit_len = 8;
161e773c
RW		 717 config_reg |= SIRFUART_DATA_BIT_LEN_8;
718 break;
719 case CS7:
5df83111 720 data_bit_len = 7;
161e773c
RW		 721 config_reg |= SIRFUART_DATA_BIT_LEN_7;
722 break;
723 case CS6:
5df83111 724 data_bit_len = 6;
161e773c
RW		 725 config_reg |= SIRFUART_DATA_BIT_LEN_6;
726 break;
727 case CS5:
5df83111 728 data_bit_len = 5;
161e773c
RW		 729 config_reg |= SIRFUART_DATA_BIT_LEN_5;
730 break;
731 }
5df83111 732 if (termios->c_cflag & CSTOPB) {
161e773c 733 config_reg |= SIRFUART_STOP_BIT_LEN_2;
5df83111
QL		 734 stop_bit_len = 2;
735 } else
736 stop_bit_len = 1;
737
161e773c 738 spin_lock_irqsave(&port->lock, flags);
5df83111 739 port->read_status_mask = uint_en->sirfsoc_rx_oflow_en;
161e773c 740 port->ignore_status_mask = 0;
5df83111
QL		 741 if (sirfport->uart_reg->uart_type == SIRF_REAL_UART) {
742 if (termios->c_iflag & INPCK)
743 port->read_status_mask |= uint_en->sirfsoc_frm_err_en |
744 uint_en->sirfsoc_parity_err_en;
2eb5618d 745 } else {
5df83111
QL		 746 if (termios->c_iflag & INPCK)
747 port->read_status_mask |= uint_en->sirfsoc_frm_err_en;
748 }
ef8b9ddc 749 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
5df83111
QL		 750 port->read_status_mask |= uint_en->sirfsoc_rxd_brk_en;
751 if (sirfport->uart_reg->uart_type == SIRF_REAL_UART) {
752 if (termios->c_iflag & IGNPAR)
753 port->ignore_status_mask |=
754 uint_en->sirfsoc_frm_err_en |
755 uint_en->sirfsoc_parity_err_en;
756 if (termios->c_cflag & PARENB) {
757 if (termios->c_cflag & CMSPAR) {
758 if (termios->c_cflag & PARODD)
759 config_reg |= SIRFUART_STICK_BIT_MARK;
760 else
761 config_reg |= SIRFUART_STICK_BIT_SPACE;
5df83111 762 } else {
d9e8e976
QL		 763 if (termios->c_cflag & PARODD)
764 config_reg |= SIRFUART_STICK_BIT_ODD;
765 else
766 config_reg |= SIRFUART_STICK_BIT_EVEN;
5df83111
QL		 767 }
768 }
2eb5618d 769 } else {
5df83111
QL		 770 if (termios->c_iflag & IGNPAR)
771 port->ignore_status_mask |=
772 uint_en->sirfsoc_frm_err_en;
773 if (termios->c_cflag & PARENB)
774 dev_warn(port->dev,
775 "USP-UART not support parity err\n");
776 }
777 if (termios->c_iflag & IGNBRK) {
161e773c 778 port->ignore_status_mask |=
5df83111
QL		 779 uint_en->sirfsoc_rxd_brk_en;
780 if (termios->c_iflag & IGNPAR)
781 port->ignore_status_mask |=
782 uint_en->sirfsoc_rx_oflow_en;
783 }
161e773c
RW		 784 if ((termios->c_cflag & CREAD) == 0)
785 port->ignore_status_mask |= SIRFUART_DUMMY_READ;
161e773c
RW		 786 /* Hardware Flow Control Settings */
787 if (UART_ENABLE_MS(port, termios->c_cflag)) {
788 if (!sirfport->ms_enabled)
789 sirfsoc_uart_enable_ms(port);
790 } else {
791 if (sirfport->ms_enabled)
792 sirfsoc_uart_disable_ms(port);
793 }
5df83111
QL		 794 baud_rate = uart_get_baud_rate(port, termios, old, 0, 4000000);
795 if (ioclk_rate == 150000000) {
ac4ce718
BS		 796 for (ic = 0; ic < SIRF_BAUD_RATE_SUPPORT_NR; ic++)
797 if (baud_rate == baudrate_to_regv[ic].baud_rate)
798 clk_div_reg = baudrate_to_regv[ic].reg_val;
799 }
5df83111
QL		 800 set_baud = baud_rate;
801 if (sirfport->uart_reg->uart_type == SIRF_REAL_UART) {
802 if (unlikely(clk_div_reg == 0))
803 clk_div_reg = sirfsoc_uart_calc_sample_div(baud_rate,
804 ioclk_rate, &set_baud);
805 wr_regl(port, ureg->sirfsoc_divisor, clk_div_reg);
2eb5618d 806 } else {
5df83111
QL		 807 clk_div_reg = sirfsoc_usp_calc_sample_div(baud_rate,
808 ioclk_rate, &sample_div_reg);
809 sample_div_reg--;
810 set_baud = ((ioclk_rate / (clk_div_reg+1) - 1) /
811 (sample_div_reg + 1));
812 /* setting usp mode 2 */
459f15c4
QL		 813 len_val = ((1 << SIRFSOC_USP_MODE2_RXD_DELAY_OFFSET) |
814 (1 << SIRFSOC_USP_MODE2_TXD_DELAY_OFFSET));
815 len_val |= ((clk_div_reg & SIRFSOC_USP_MODE2_CLK_DIVISOR_MASK)
816 << SIRFSOC_USP_MODE2_CLK_DIVISOR_OFFSET);
817 wr_regl(port, ureg->sirfsoc_mode2, len_val);
5df83111 818 }
161e773c 819 if (tty_termios_baud_rate(termios))
5df83111
QL		 820 tty_termios_encode_baud_rate(termios, set_baud, set_baud);
821 /* set receive timeout && data bits len */
822 rx_time_out = SIRFSOC_UART_RX_TIMEOUT(set_baud, 20000);
823 rx_time_out = SIRFUART_RECV_TIMEOUT_VALUE(rx_time_out);
8316d04c 824 txfifo_op_reg = rd_regl(port, ureg->sirfsoc_tx_fifo_op);
5df83111 825 wr_regl(port, ureg->sirfsoc_tx_fifo_op,
8316d04c 826 (txfifo_op_reg & ~SIRFUART_FIFO_START));
5df83111 827 if (sirfport->uart_reg->uart_type == SIRF_REAL_UART) {
c1b7ac6f 828 config_reg |= SIRFUART_UART_RECV_TIMEOUT(rx_time_out);
5df83111 829 wr_regl(port, ureg->sirfsoc_line_ctrl, config_reg);
2eb5618d 830 } else {
5df83111 831 /*tx frame ctrl*/
459f15c4
QL		 832 len_val = (data_bit_len - 1) << SIRFSOC_USP_TX_DATA_LEN_OFFSET;
833 len_val |= (data_bit_len + 1 + stop_bit_len - 1) <<
834 SIRFSOC_USP_TX_FRAME_LEN_OFFSET;
835 len_val |= ((data_bit_len - 1) <<
836 SIRFSOC_USP_TX_SHIFTER_LEN_OFFSET);
837 len_val |= (((clk_div_reg & 0xc00) >> 10) <<
838 SIRFSOC_USP_TX_CLK_DIVISOR_OFFSET);
5df83111
QL		 839 wr_regl(port, ureg->sirfsoc_tx_frame_ctrl, len_val);
840 /*rx frame ctrl*/
459f15c4
QL		 841 len_val = (data_bit_len - 1) << SIRFSOC_USP_RX_DATA_LEN_OFFSET;
842 len_val |= (data_bit_len + 1 + stop_bit_len - 1) <<
843 SIRFSOC_USP_RX_FRAME_LEN_OFFSET;
844 len_val |= (data_bit_len - 1) <<
845 SIRFSOC_USP_RX_SHIFTER_LEN_OFFSET;
846 len_val |= (((clk_div_reg & 0xf000) >> 12) <<
847 SIRFSOC_USP_RX_CLK_DIVISOR_OFFSET);
5df83111
QL		 848 wr_regl(port, ureg->sirfsoc_rx_frame_ctrl, len_val);
849 /*async param*/
850 wr_regl(port, ureg->sirfsoc_async_param_reg,
c1b7ac6f 851 (SIRFUART_USP_RECV_TIMEOUT(rx_time_out)) |
459f15c4
QL		 852 (sample_div_reg & SIRFSOC_USP_ASYNC_DIV2_MASK) <<
853 SIRFSOC_USP_ASYNC_DIV2_OFFSET);
5df83111 854 }
9be16b38 855 if (sirfport->tx_dma_chan)
8316d04c
QL		 856 wr_regl(port, ureg->sirfsoc_tx_dma_io_ctrl, SIRFUART_DMA_MODE);
857 else
858 wr_regl(port, ureg->sirfsoc_tx_dma_io_ctrl, SIRFUART_IO_MODE);
9be16b38 859 if (sirfport->rx_dma_chan)
1d26c9ff
QL		 860 wr_regl(port, ureg->sirfsoc_rx_dma_io_ctrl,
861 rd_regl(port, ureg->sirfsoc_rx_dma_io_ctrl) &
862 ~SIRFUART_IO_MODE);
8316d04c 863 else
1d26c9ff
QL		 864 wr_regl(port, ureg->sirfsoc_rx_dma_io_ctrl,
865 rd_regl(port, ureg->sirfsoc_rx_dma_io_ctrl) |
866 SIRFUART_IO_MODE);
0f17e3b4 867 sirfport->rx_period_time = 20000000;
161e773c 868 /* Reset Rx/Tx FIFO Threshold level for proper baudrate */
5df83111 869 if (set_baud < 1000000)
161e773c
RW		 870 threshold_div = 1;
871 else
872 threshold_div = 2;
8316d04c
QL		 873 wr_regl(port, ureg->sirfsoc_tx_fifo_ctrl,
874 SIRFUART_FIFO_THD(port) / threshold_div);
875 wr_regl(port, ureg->sirfsoc_rx_fifo_ctrl,
876 SIRFUART_FIFO_THD(port) / threshold_div);
877 txfifo_op_reg |= SIRFUART_FIFO_START;
878 wr_regl(port, ureg->sirfsoc_tx_fifo_op, txfifo_op_reg);
5df83111 879 uart_update_timeout(port, termios->c_cflag, set_baud);
5df83111 880 wr_regl(port, ureg->sirfsoc_tx_rx_en, SIRFUART_TX_EN | SIRFUART_RX_EN);
161e773c
RW		 881 spin_unlock_irqrestore(&port->lock, flags);
882}
883
388faf9f
QL		 884static void sirfsoc_uart_pm(struct uart_port *port, unsigned int state,
885 unsigned int oldstate)
886{
887 struct sirfsoc_uart_port *sirfport = to_sirfport(port);
4b8038dc 888 if (!state)
388faf9f 889 clk_prepare_enable(sirfport->clk);
4b8038dc 890 else
388faf9f
QL		 891 clk_disable_unprepare(sirfport->clk);
892}
893
161e773c
RW		 894static int sirfsoc_uart_startup(struct uart_port *port)
895{
896 struct sirfsoc_uart_port *sirfport = to_sirfport(port);
15cdcb12 897 struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
466e285b 898 struct sirfsoc_int_en *uint_en = &sirfport->uart_reg->uart_int_en;
161e773c
RW		 899 unsigned int index = port->line;
900 int ret;
2a446241 901 irq_modify_status(port->irq, IRQ_NOREQUEST, IRQ_NOAUTOEN);
161e773c
RW		 902 ret = request_irq(port->irq,
903 sirfsoc_uart_isr,
904 0,
905 SIRFUART_PORT_NAME,
906 sirfport);
907 if (ret != 0) {
908 dev_err(port->dev, "UART%d request IRQ line (%d) failed.\n",
909 index, port->irq);
910 goto irq_err;
911 }
15cdcb12
QL		 912 /* initial hardware settings */
913 wr_regl(port, ureg->sirfsoc_tx_dma_io_ctrl,
914 rd_regl(port, ureg->sirfsoc_tx_dma_io_ctrl) |
915 SIRFUART_IO_MODE);
916 wr_regl(port, ureg->sirfsoc_rx_dma_io_ctrl,
917 rd_regl(port, ureg->sirfsoc_rx_dma_io_ctrl) |
918 SIRFUART_IO_MODE);
0f17e3b4
QL		 919 wr_regl(port, ureg->sirfsoc_rx_dma_io_ctrl,
920 rd_regl(port, ureg->sirfsoc_rx_dma_io_ctrl) &
921 ~SIRFUART_RX_DMA_FLUSH);
15cdcb12
QL		 922 wr_regl(port, ureg->sirfsoc_tx_dma_io_len, 0);
923 wr_regl(port, ureg->sirfsoc_rx_dma_io_len, 0);
924 wr_regl(port, ureg->sirfsoc_tx_rx_en, SIRFUART_RX_EN | SIRFUART_TX_EN);
925 if (sirfport->uart_reg->uart_type == SIRF_USP_UART)
926 wr_regl(port, ureg->sirfsoc_mode1,
927 SIRFSOC_USP_ENDIAN_CTRL_LSBF |
928 SIRFSOC_USP_EN);
929 wr_regl(port, ureg->sirfsoc_tx_fifo_op, SIRFUART_FIFO_RESET);
15cdcb12
QL		 930 wr_regl(port, ureg->sirfsoc_rx_fifo_op, SIRFUART_FIFO_RESET);
931 wr_regl(port, ureg->sirfsoc_rx_fifo_op, 0);
932 wr_regl(port, ureg->sirfsoc_tx_fifo_ctrl, SIRFUART_FIFO_THD(port));
933 wr_regl(port, ureg->sirfsoc_rx_fifo_ctrl, SIRFUART_FIFO_THD(port));
9be16b38 934 if (sirfport->rx_dma_chan)
8316d04c 935 wr_regl(port, ureg->sirfsoc_rx_fifo_level_chk,
1d26c9ff
QL		 936 SIRFUART_RX_FIFO_CHK_SC(port->line, 0x1) |
937 SIRFUART_RX_FIFO_CHK_LC(port->line, 0x2) |
938 SIRFUART_RX_FIFO_CHK_HC(port->line, 0x4));
9be16b38 939 if (sirfport->tx_dma_chan) {
8316d04c
QL		 940 sirfport->tx_dma_state = TX_DMA_IDLE;
941 wr_regl(port, ureg->sirfsoc_tx_fifo_level_chk,
942 SIRFUART_TX_FIFO_CHK_SC(port->line, 0x1b) |
943 SIRFUART_TX_FIFO_CHK_LC(port->line, 0xe) |
944 SIRFUART_TX_FIFO_CHK_HC(port->line, 0x4));
945 }
2eb5618d
QL		 946 sirfport->ms_enabled = false;
947 if (sirfport->uart_reg->uart_type == SIRF_USP_UART &&
948 sirfport->hw_flow_ctrl) {
2a446241
RH		 949 irq_modify_status(gpio_to_irq(sirfport->cts_gpio),
950 IRQ_NOREQUEST, IRQ_NOAUTOEN);
2eb5618d
QL		 951 ret = request_irq(gpio_to_irq(sirfport->cts_gpio),
952 sirfsoc_uart_usp_cts_handler, IRQF_TRIGGER_FALLING |
953 IRQF_TRIGGER_RISING, "usp_cts_irq", sirfport);
954 if (ret != 0) {
955 dev_err(port->dev, "UART-USP:request gpio irq fail\n");
956 goto init_rx_err;
957 }
958 }
1d26c9ff
QL		 959 if (sirfport->uart_reg->uart_type == SIRF_REAL_UART &&
960 sirfport->rx_dma_chan)
961 wr_regl(port, ureg->sirfsoc_swh_dma_io,
962 SIRFUART_CLEAR_RX_ADDR_EN);
963 if (sirfport->uart_reg->uart_type == SIRF_USP_UART &&
964 sirfport->rx_dma_chan)
965 wr_regl(port, ureg->sirfsoc_rx_dma_io_ctrl,
966 rd_regl(port, ureg->sirfsoc_rx_dma_io_ctrl) |
967 SIRFSOC_USP_FRADDR_CLR_EN);
0f17e3b4
QL		 968 if (sirfport->rx_dma_chan && !sirfport->is_hrt_enabled) {
969 sirfport->is_hrt_enabled = true;
970 sirfport->rx_period_time = 20000000;
1d26c9ff
QL		 971 sirfport->rx_last_pos = -1;
972 sirfport->pio_fetch_cnt = 0;
0f17e3b4
QL		 973 sirfport->rx_dma_items.xmit.tail =
974 sirfport->rx_dma_items.xmit.head = 0;
975 hrtimer_start(&sirfport->hrt,
976 ns_to_ktime(sirfport->rx_period_time),
977 HRTIMER_MODE_REL);
978 }
466e285b
QL		 979 wr_regl(port, ureg->sirfsoc_rx_fifo_op, SIRFUART_FIFO_START);
980 if (sirfport->rx_dma_chan)
981 sirfsoc_uart_start_next_rx_dma(port);
982 else {
983 if (!sirfport->is_atlas7)
984 wr_regl(port, ureg->sirfsoc_int_en_reg,
985 rd_regl(port, ureg->sirfsoc_int_en_reg) |
986 SIRFUART_RX_IO_INT_EN(uint_en,
987 sirfport->uart_reg->uart_type));
988 else
989 wr_regl(port, ureg->sirfsoc_int_en_reg,
990 SIRFUART_RX_IO_INT_EN(uint_en,
991 sirfport->uart_reg->uart_type));
992 }
993 enable_irq(port->irq);
2eb5618d 994
15cdcb12 995 return 0;
2eb5618d
QL		 996init_rx_err:
997 free_irq(port->irq, sirfport);
161e773c
RW		 998irq_err:
999 return ret;
1000}
1001
1002static void sirfsoc_uart_shutdown(struct uart_port *port)
1003{
1004 struct sirfsoc_uart_port *sirfport = to_sirfport(port);
5df83111 1005 struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
1d26c9ff
QL		 1006 struct circ_buf *xmit;
1007
1008 xmit = &sirfport->rx_dma_items.xmit;
057badd6 1009 if (!sirfport->is_atlas7)
5df83111 1010 wr_regl(port, ureg->sirfsoc_int_en_reg, 0);
909102db 1011 else
c1b7ac6f 1012 wr_regl(port, ureg->sirfsoc_int_en_clr_reg, ~0UL);
909102db 1013
161e773c 1014 free_irq(port->irq, sirfport);
2eb5618d 1015 if (sirfport->ms_enabled)
161e773c 1016 sirfsoc_uart_disable_ms(port);
2eb5618d
QL		 1017 if (sirfport->uart_reg->uart_type == SIRF_USP_UART &&
1018 sirfport->hw_flow_ctrl) {
1019 gpio_set_value(sirfport->rts_gpio, 1);
1020 free_irq(gpio_to_irq(sirfport->cts_gpio), sirfport);
161e773c 1021 }
9be16b38 1022 if (sirfport->tx_dma_chan)
8316d04c 1023 sirfport->tx_dma_state = TX_DMA_IDLE;
0f17e3b4 1024 if (sirfport->rx_dma_chan && sirfport->is_hrt_enabled) {
1d26c9ff
QL		 1025 while (((rd_regl(port, ureg->sirfsoc_rx_fifo_status) &
1026 SIRFUART_RX_FIFO_MASK) > sirfport->pio_fetch_cnt) &&
1027 !CIRC_CNT(xmit->head, xmit->tail,
1028 SIRFSOC_RX_DMA_BUF_SIZE))
0f17e3b4
QL		 1029 ;
1030 sirfport->is_hrt_enabled = false;
1031 hrtimer_cancel(&sirfport->hrt);
1032 }
161e773c
RW		 1033}
1034
1035static const char *sirfsoc_uart_type(struct uart_port *port)
1036{
1037 return port->type == SIRFSOC_PORT_TYPE ? SIRFUART_PORT_NAME : NULL;
1038}
1039
1040static int sirfsoc_uart_request_port(struct uart_port *port)
1041{
5df83111
QL		 1042 struct sirfsoc_uart_port *sirfport = to_sirfport(port);
1043 struct sirfsoc_uart_param *uart_param = &sirfport->uart_reg->uart_param;
161e773c
RW		 1044 void *ret;
1045 ret = request_mem_region(port->mapbase,
5df83111 1046 SIRFUART_MAP_SIZE, uart_param->port_name);
161e773c
RW		 1047 return ret ? 0 : -EBUSY;
1048}
1049
1050static void sirfsoc_uart_release_port(struct uart_port *port)
1051{
1052 release_mem_region(port->mapbase, SIRFUART_MAP_SIZE);
1053}
1054
1055static void sirfsoc_uart_config_port(struct uart_port *port, int flags)
1056{
1057 if (flags & UART_CONFIG_TYPE) {
1058 port->type = SIRFSOC_PORT_TYPE;
1059 sirfsoc_uart_request_port(port);
1060 }
1061}
1062
2331e068 1063static const struct uart_ops sirfsoc_uart_ops = {
161e773c
RW		 1064 .tx_empty = sirfsoc_uart_tx_empty,
1065 .get_mctrl = sirfsoc_uart_get_mctrl,
1066 .set_mctrl = sirfsoc_uart_set_mctrl,
1067 .stop_tx = sirfsoc_uart_stop_tx,
1068 .start_tx = sirfsoc_uart_start_tx,
1069 .stop_rx = sirfsoc_uart_stop_rx,
1070 .enable_ms = sirfsoc_uart_enable_ms,
1071 .break_ctl = sirfsoc_uart_break_ctl,
1072 .startup = sirfsoc_uart_startup,
1073 .shutdown = sirfsoc_uart_shutdown,
1074 .set_termios = sirfsoc_uart_set_termios,
388faf9f 1075 .pm = sirfsoc_uart_pm,
161e773c
RW		 1076 .type = sirfsoc_uart_type,
1077 .release_port = sirfsoc_uart_release_port,
1078 .request_port = sirfsoc_uart_request_port,
1079 .config_port = sirfsoc_uart_config_port,
1080};
1081
1082#ifdef CONFIG_SERIAL_SIRFSOC_CONSOLE
5df83111
QL		 1083static int __init
1084sirfsoc_uart_console_setup(struct console *co, char *options)
161e773c
RW		 1085{
1086 unsigned int baud = 115200;
1087 unsigned int bits = 8;
1088 unsigned int parity = 'n';
1089 unsigned int flow = 'n';
a6ffe896
QL		 1090 struct sirfsoc_uart_port *sirfport;
1091 struct sirfsoc_register *ureg;
161e773c 1092 if (co->index < 0 || co->index >= SIRFSOC_UART_NR)
c35b49b7 1093 co->index = 1;
a6ffe896
QL		 1094 sirfport = sirf_ports[co->index];
1095 if (!sirfport)
1096 return -ENODEV;
1097 ureg = &sirfport->uart_reg->uart_reg;
1098 if (!sirfport->port.mapbase)
161e773c
RW		 1099 return -ENODEV;
1100
5df83111
QL		 1101 /* enable usp in mode1 register */
1102 if (sirfport->uart_reg->uart_type == SIRF_USP_UART)
a6ffe896 1103 wr_regl(&sirfport->port, ureg->sirfsoc_mode1, SIRFSOC_USP_EN |
5df83111 1104 SIRFSOC_USP_ENDIAN_CTRL_LSBF);
161e773c
RW		 1105 if (options)
1106 uart_parse_options(options, &baud, &parity, &bits, &flow);
a6ffe896 1107 sirfport->port.cons = co;
5df83111 1108
8316d04c 1109 /* default console tx/rx transfer using io mode */
9be16b38
QL		 1110 sirfport->rx_dma_chan = NULL;
1111 sirfport->tx_dma_chan = NULL;
a6ffe896 1112 return uart_set_options(&sirfport->port, co, baud, parity, bits, flow);
161e773c
RW		 1113}
1114
1115static void sirfsoc_uart_console_putchar(struct uart_port *port, int ch)
1116{
5df83111
QL		 1117 struct sirfsoc_uart_port *sirfport = to_sirfport(port);
1118 struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
1119 struct sirfsoc_fifo_status *ufifo_st = &sirfport->uart_reg->fifo_status;
cb4595a2
QL		 1120 while (rd_regl(port, ureg->sirfsoc_tx_fifo_status) &
1121 ufifo_st->ff_full(port))
161e773c 1122 cpu_relax();
205c384f 1123 wr_regl(port, ureg->sirfsoc_tx_fifo_data, ch);
161e773c
RW		 1124}
1125
1126static void sirfsoc_uart_console_write(struct console *co, const char *s,
1127 unsigned int count)
1128{
a6ffe896
QL		 1129 struct sirfsoc_uart_port *sirfport = sirf_ports[co->index];
1130
1131 uart_console_write(&sirfport->port, s, count,
1132 sirfsoc_uart_console_putchar);
161e773c
RW		 1133}
1134
1135static struct console sirfsoc_uart_console = {
1136 .name = SIRFSOC_UART_NAME,
1137 .device = uart_console_device,
1138 .flags = CON_PRINTBUFFER,
1139 .index = -1,
1140 .write = sirfsoc_uart_console_write,
1141 .setup = sirfsoc_uart_console_setup,
1142 .data = &sirfsoc_uart_drv,
1143};
1144
1145static int __init sirfsoc_uart_console_init(void)
1146{
1147 register_console(&sirfsoc_uart_console);
1148 return 0;
1149}
1150console_initcall(sirfsoc_uart_console_init);
1151#endif
1152
1153static struct uart_driver sirfsoc_uart_drv = {
1154 .owner = THIS_MODULE,
1155 .driver_name = SIRFUART_PORT_NAME,
1156 .nr = SIRFSOC_UART_NR,
1157 .dev_name = SIRFSOC_UART_NAME,
1158 .major = SIRFSOC_UART_MAJOR,
1159 .minor = SIRFSOC_UART_MINOR,
1160#ifdef CONFIG_SERIAL_SIRFSOC_CONSOLE
1161 .cons = &sirfsoc_uart_console,
1162#else
1163 .cons = NULL,
1164#endif
1165};
1166
0f17e3b4
QL		 1167static enum hrtimer_restart
1168 sirfsoc_uart_rx_dma_hrtimer_callback(struct hrtimer *hrt)
1169{
1170 struct sirfsoc_uart_port *sirfport;
1171 struct uart_port *port;
1172 int count, inserted;
1173 struct dma_tx_state tx_state;
1174 struct tty_struct *tty;
1175 struct sirfsoc_register *ureg;
1176 struct circ_buf *xmit;
1d26c9ff
QL		 1177 struct sirfsoc_fifo_status *ufifo_st;
1178 int max_pio_cnt;
0f17e3b4
QL		 1179
1180 sirfport = container_of(hrt, struct sirfsoc_uart_port, hrt);
1181 port = &sirfport->port;
1182 inserted = 0;
1183 tty = port->state->port.tty;
1184 ureg = &sirfport->uart_reg->uart_reg;
1185 xmit = &sirfport->rx_dma_items.xmit;
1d26c9ff
QL		 1186 ufifo_st = &sirfport->uart_reg->fifo_status;
1187
0f17e3b4 1188 dmaengine_tx_status(sirfport->rx_dma_chan,
1d26c9ff
QL		 1189 sirfport->rx_dma_items.cookie, &tx_state);
1190 if (SIRFSOC_RX_DMA_BUF_SIZE - tx_state.residue !=
1191 sirfport->rx_last_pos) {
1192 xmit->head = SIRFSOC_RX_DMA_BUF_SIZE - tx_state.residue;
1193 sirfport->rx_last_pos = xmit->head;
1194 sirfport->pio_fetch_cnt = 0;
1195 }
0f17e3b4
QL		 1196 count = CIRC_CNT_TO_END(xmit->head, xmit->tail,
1197 SIRFSOC_RX_DMA_BUF_SIZE);
1198 while (count > 0) {
1199 inserted = tty_insert_flip_string(tty->port,
1200 (const unsigned char *)&xmit->buf[xmit->tail], count);
1201 if (!inserted)
1202 goto next_hrt;
1203 port->icount.rx += inserted;
1204 xmit->tail = (xmit->tail + inserted) &
1205 (SIRFSOC_RX_DMA_BUF_SIZE - 1);
1206 count = CIRC_CNT_TO_END(xmit->head, xmit->tail,
1207 SIRFSOC_RX_DMA_BUF_SIZE);
1208 tty_flip_buffer_push(tty->port);
1209 }
1210 /*
1211 * if RX DMA buffer data have all push into tty buffer, and there is
1212 * only little data(less than a dma transfer unit) left in rxfifo,
1213 * fetch it out in pio mode and switch back to dma immediately
1214 */
1215 if (!inserted && !count &&
1216 ((rd_regl(port, ureg->sirfsoc_rx_fifo_status) &
1d26c9ff
QL		 1217 SIRFUART_RX_FIFO_MASK) > sirfport->pio_fetch_cnt)) {
1218 dmaengine_pause(sirfport->rx_dma_chan);
0f17e3b4
QL		 1219 /* switch to pio mode */
1220 wr_regl(port, ureg->sirfsoc_rx_dma_io_ctrl,
1221 rd_regl(port, ureg->sirfsoc_rx_dma_io_ctrl) |
1222 SIRFUART_IO_MODE);
1d26c9ff
QL		 1223 /*
1224 * UART controller SWH_DMA_IO register have CLEAR_RX_ADDR_EN
1225 * When found changing I/O to DMA mode, it clears
1226 * two low bits of read point;
1227 * USP have similar FRADDR_CLR_EN bit in USP_RX_DMA_IO_CTRL.
1228 * Fetch data out from rxfifo into DMA buffer in PIO mode,
1229 * while switch back to DMA mode, the data fetched will override
1230 * by DMA, as hardware have a strange behaviour:
1231 * after switch back to DMA mode, check rxfifo status it will
1232 * be the number PIO fetched, so record the fetched data count
1233 * to avoid the repeated fetch
1234 */
1235 max_pio_cnt = 3;
1236 while (!(rd_regl(port, ureg->sirfsoc_rx_fifo_status) &
1237 ufifo_st->ff_empty(port)) && max_pio_cnt--) {
1238 xmit->buf[xmit->head] =
1239 rd_regl(port, ureg->sirfsoc_rx_fifo_data);
1240 xmit->head = (xmit->head + 1) &
1241 (SIRFSOC_RX_DMA_BUF_SIZE - 1);
1242 sirfport->pio_fetch_cnt++;
0f17e3b4 1243 }
0f17e3b4
QL		 1244 /* switch back to dma mode */
1245 wr_regl(port, ureg->sirfsoc_rx_dma_io_ctrl,
1246 rd_regl(port, ureg->sirfsoc_rx_dma_io_ctrl) &
1247 ~SIRFUART_IO_MODE);
1d26c9ff 1248 dmaengine_resume(sirfport->rx_dma_chan);
0f17e3b4
QL		 1249 }
1250next_hrt:
1251 hrtimer_forward_now(hrt, ns_to_ktime(sirfport->rx_period_time));
1252 return HRTIMER_RESTART;
1253}
1254
51949543 1255static const struct of_device_id sirfsoc_uart_ids[] = {
5df83111 1256 { .compatible = "sirf,prima2-uart", .data = &sirfsoc_uart,},
057badd6 1257 { .compatible = "sirf,atlas7-uart", .data = &sirfsoc_uart},
5df83111 1258 { .compatible = "sirf,prima2-usp-uart", .data = &sirfsoc_usp},
c1b7ac6f 1259 { .compatible = "sirf,atlas7-usp-uart", .data = &sirfsoc_usp},
5df83111
QL		 1260 {}
1261};
1262MODULE_DEVICE_TABLE(of, sirfsoc_uart_ids);
1263
ada1f443 1264static int sirfsoc_uart_probe(struct platform_device *pdev)
161e773c 1265{
af99c187 1266 struct device_node *np = pdev->dev.of_node;
161e773c
RW		 1267 struct sirfsoc_uart_port *sirfport;
1268 struct uart_port *port;
1269 struct resource *res;
1270 int ret;
9be16b38 1271 struct dma_slave_config slv_cfg = {
1d26c9ff 1272 .src_maxburst = 1,
9be16b38
QL		 1273 };
1274 struct dma_slave_config tx_slv_cfg = {
1275 .dst_maxburst = 2,
1276 };
5df83111 1277 const struct of_device_id *match;
161e773c 1278
af99c187 1279 match = of_match_node(sirfsoc_uart_ids, np);
a6ffe896
QL		 1280 sirfport = devm_kzalloc(&pdev->dev, sizeof(*sirfport), GFP_KERNEL);
1281 if (!sirfport) {
1282 ret = -ENOMEM;
161e773c
RW		 1283 goto err;
1284 }
af99c187 1285 sirfport->port.line = of_alias_get_id(np, "serial");
96c611c2
GU		 1286 if (sirfport->port.line >= ARRAY_SIZE(sirf_ports)) {
1287 dev_err(&pdev->dev, "serial%d out of range\n",
1288 sirfport->port.line);
1289 return -EINVAL;
1290 }
a6ffe896
QL		 1291 sirf_ports[sirfport->port.line] = sirfport;
1292 sirfport->port.iotype = UPIO_MEM;
1293 sirfport->port.flags = UPF_BOOT_AUTOCONF;
161e773c
RW		 1294 port = &sirfport->port;
1295 port->dev = &pdev->dev;
1296 port->private_data = sirfport;
5df83111 1297 sirfport->uart_reg = (struct sirfsoc_uart_register *)match->data;
161e773c 1298
af99c187 1299 sirfport->hw_flow_ctrl =
7f60830a
GU		 1300 of_property_read_bool(np, "uart-has-rtscts") ||
1301 of_property_read_bool(np, "sirf,uart-has-rtscts") /* deprecated */;
af99c187
GU		 1302 if (of_device_is_compatible(np, "sirf,prima2-uart") ||
1303 of_device_is_compatible(np, "sirf,atlas7-uart"))
5df83111 1304 sirfport->uart_reg->uart_type = SIRF_REAL_UART;
af99c187
GU		 1305 if (of_device_is_compatible(np, "sirf,prima2-usp-uart") ||
1306 of_device_is_compatible(np, "sirf,atlas7-usp-uart")) {
5df83111 1307 sirfport->uart_reg->uart_type = SIRF_USP_UART;
2eb5618d
QL		 1308 if (!sirfport->hw_flow_ctrl)
1309 goto usp_no_flow_control;
af99c187
GU		 1310 if (of_find_property(np, "cts-gpios", NULL))
1311 sirfport->cts_gpio =
1312 of_get_named_gpio(np, "cts-gpios", 0);
2eb5618d
QL		 1313 else
1314 sirfport->cts_gpio = -1;
af99c187
GU		 1315 if (of_find_property(np, "rts-gpios", NULL))
1316 sirfport->rts_gpio =
1317 of_get_named_gpio(np, "rts-gpios", 0);
2eb5618d
QL		 1318 else
1319 sirfport->rts_gpio = -1;
1320
1321 if ((!gpio_is_valid(sirfport->cts_gpio) ||
1322 !gpio_is_valid(sirfport->rts_gpio))) {
1323 ret = -EINVAL;
1324 dev_err(&pdev->dev,
67bc306c 1325 "Usp flow control must have cts and rts gpio");
2eb5618d
QL		 1326 goto err;
1327 }
1328 ret = devm_gpio_request(&pdev->dev, sirfport->cts_gpio,
67bc306c 1329 "usp-cts-gpio");
2eb5618d 1330 if (ret) {
67bc306c 1331 dev_err(&pdev->dev, "Unable request cts gpio");
2eb5618d
QL		 1332 goto err;
1333 }
1334 gpio_direction_input(sirfport->cts_gpio);
1335 ret = devm_gpio_request(&pdev->dev, sirfport->rts_gpio,
67bc306c 1336 "usp-rts-gpio");
2eb5618d 1337 if (ret) {
67bc306c 1338 dev_err(&pdev->dev, "Unable request rts gpio");
2eb5618d
QL		 1339 goto err;
1340 }
1341 gpio_direction_output(sirfport->rts_gpio, 1);
1342 }
1343usp_no_flow_control:
af99c187
GU		 1344 if (of_device_is_compatible(np, "sirf,atlas7-uart") ||
1345 of_device_is_compatible(np, "sirf,atlas7-usp-uart"))
057badd6 1346 sirfport->is_atlas7 = true;
909102db 1347
af99c187 1348 if (of_property_read_u32(np, "fifosize", &port->fifosize)) {
161e773c
RW		 1349 dev_err(&pdev->dev,
1350 "Unable to find fifosize in uart node.\n");
1351 ret = -EFAULT;
1352 goto err;
1353 }
1354
1355 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1356 if (res == NULL) {
1357 dev_err(&pdev->dev, "Insufficient resources.\n");
1358 ret = -EFAULT;
1359 goto err;
1360 }
1361 port->mapbase = res->start;
0f17e3b4
QL		 1362 port->membase = devm_ioremap(&pdev->dev,
1363 res->start, resource_size(res));
161e773c
RW		 1364 if (!port->membase) {
1365 dev_err(&pdev->dev, "Cannot remap resource.\n");
1366 ret = -ENOMEM;
1367 goto err;
1368 }
1369 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1370 if (res == NULL) {
1371 dev_err(&pdev->dev, "Insufficient resources.\n");
1372 ret = -EFAULT;
9250dd57 1373 goto err;
161e773c
RW		 1374 }
1375 port->irq = res->start;
1376
adeede73 1377 sirfport->clk = devm_clk_get(&pdev->dev, NULL);
ac4ce718
BS		 1378 if (IS_ERR(sirfport->clk)) {
1379 ret = PTR_ERR(sirfport->clk);
a343756e 1380 goto err;
ac4ce718 1381 }
ac4ce718
BS		 1382 port->uartclk = clk_get_rate(sirfport->clk);
1383
161e773c
RW		 1384 port->ops = &sirfsoc_uart_ops;
1385 spin_lock_init(&port->lock);
1386
1387 platform_set_drvdata(pdev, sirfport);
1388 ret = uart_add_one_port(&sirfsoc_uart_drv, port);
1389 if (ret != 0) {
1390 dev_err(&pdev->dev, "Cannot add UART port(%d).\n", pdev->id);
adeede73 1391 goto err;
161e773c
RW		 1392 }
1393
9be16b38 1394 sirfport->rx_dma_chan = dma_request_slave_channel(port->dev, "rx");
0f17e3b4
QL		 1395 sirfport->rx_dma_items.xmit.buf =
1396 dma_alloc_coherent(port->dev, SIRFSOC_RX_DMA_BUF_SIZE,
1397 &sirfport->rx_dma_items.dma_addr, GFP_KERNEL);
1398 if (!sirfport->rx_dma_items.xmit.buf) {
1399 dev_err(port->dev, "Uart alloc bufa failed\n");
1400 ret = -ENOMEM;
1401 goto alloc_coherent_err;
9be16b38 1402 }
0f17e3b4
QL		 1403 sirfport->rx_dma_items.xmit.head =
1404 sirfport->rx_dma_items.xmit.tail = 0;
9be16b38
QL		 1405 if (sirfport->rx_dma_chan)
1406 dmaengine_slave_config(sirfport->rx_dma_chan, &slv_cfg);
1407 sirfport->tx_dma_chan = dma_request_slave_channel(port->dev, "tx");
1408 if (sirfport->tx_dma_chan)
1409 dmaengine_slave_config(sirfport->tx_dma_chan, &tx_slv_cfg);
0f17e3b4
QL		 1410 if (sirfport->rx_dma_chan) {
1411 hrtimer_init(&sirfport->hrt, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
1412 sirfport->hrt.function = sirfsoc_uart_rx_dma_hrtimer_callback;
1413 sirfport->is_hrt_enabled = false;
1414 }
161e773c 1415
9be16b38
QL		 1416 return 0;
1417alloc_coherent_err:
0f17e3b4
QL		 1418 dma_free_coherent(port->dev, SIRFSOC_RX_DMA_BUF_SIZE,
1419 sirfport->rx_dma_items.xmit.buf,
1420 sirfport->rx_dma_items.dma_addr);
9be16b38 1421 dma_release_channel(sirfport->rx_dma_chan);
161e773c
RW		 1422err:
1423 return ret;
1424}
1425
1426static int sirfsoc_uart_remove(struct platform_device *pdev)
1427{
1428 struct sirfsoc_uart_port *sirfport = platform_get_drvdata(pdev);
1429 struct uart_port *port = &sirfport->port;
161e773c 1430 uart_remove_one_port(&sirfsoc_uart_drv, port);
9be16b38 1431 if (sirfport->rx_dma_chan) {
9be16b38
QL		 1432 dmaengine_terminate_all(sirfport->rx_dma_chan);
1433 dma_release_channel(sirfport->rx_dma_chan);
0f17e3b4
QL		 1434 dma_free_coherent(port->dev, SIRFSOC_RX_DMA_BUF_SIZE,
1435 sirfport->rx_dma_items.xmit.buf,
1436 sirfport->rx_dma_items.dma_addr);
9be16b38
QL		 1437 }
1438 if (sirfport->tx_dma_chan) {
1439 dmaengine_terminate_all(sirfport->tx_dma_chan);
1440 dma_release_channel(sirfport->tx_dma_chan);
1441 }
161e773c
RW		 1442 return 0;
1443}
1444
99e626f5 1445#ifdef CONFIG_PM_SLEEP
161e773c 1446static int
99e626f5 1447sirfsoc_uart_suspend(struct device *pdev)
161e773c 1448{
99e626f5 1449 struct sirfsoc_uart_port *sirfport = dev_get_drvdata(pdev);
161e773c
RW		 1450 struct uart_port *port = &sirfport->port;
1451 uart_suspend_port(&sirfsoc_uart_drv, port);
1452 return 0;
1453}
1454
99e626f5 1455static int sirfsoc_uart_resume(struct device *pdev)
161e773c 1456{
99e626f5 1457 struct sirfsoc_uart_port *sirfport = dev_get_drvdata(pdev);
161e773c
RW		 1458 struct uart_port *port = &sirfport->port;
1459 uart_resume_port(&sirfsoc_uart_drv, port);
1460 return 0;
1461}
99e626f5
QL		 1462#endif
1463
1464static const struct dev_pm_ops sirfsoc_uart_pm_ops = {
1465 SET_SYSTEM_SLEEP_PM_OPS(sirfsoc_uart_suspend, sirfsoc_uart_resume)
1466};
161e773c 1467
161e773c
RW		 1468static struct platform_driver sirfsoc_uart_driver = {
1469 .probe = sirfsoc_uart_probe,
2d47b716 1470 .remove = sirfsoc_uart_remove,
161e773c
RW		 1471 .driver = {
1472 .name = SIRFUART_PORT_NAME,
161e773c 1473 .of_match_table = sirfsoc_uart_ids,
99e626f5 1474 .pm = &sirfsoc_uart_pm_ops,
161e773c
RW		 1475 },
1476};
1477
1478static int __init sirfsoc_uart_init(void)
1479{
1480 int ret = 0;
1481
1482 ret = uart_register_driver(&sirfsoc_uart_drv);
1483 if (ret)
1484 goto out;
1485
1486 ret = platform_driver_register(&sirfsoc_uart_driver);
1487 if (ret)
1488 uart_unregister_driver(&sirfsoc_uart_drv);
1489out:
1490 return ret;
1491}
1492module_init(sirfsoc_uart_init);
1493
1494static void __exit sirfsoc_uart_exit(void)
1495{
1496 platform_driver_unregister(&sirfsoc_uart_driver);
1497 uart_unregister_driver(&sirfsoc_uart_drv);
1498}
1499module_exit(sirfsoc_uart_exit);
1500
1501MODULE_LICENSE("GPL v2");
1502MODULE_AUTHOR("Bin Shi <Bin.Shi@csr.com>, Rong Wang<Rong.Wang@csr.com>");
1503MODULE_DESCRIPTION("CSR SiRFprimaII Uart Driver");
Linux 6.x block layer and io_uring tree(s)