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1 | // SPDX-License-Identifier: GPL-2.0+ |
2 | /* | |
3 | * SiFive UART driver | |
4 | * Copyright (C) 2018 Paul Walmsley <paul@pwsan.com> | |
5 | * Copyright (C) 2018-2019 SiFive | |
6 | * | |
45c054d0 PW |
7 | * Based partially on: |
8 | * - drivers/tty/serial/pxa.c | |
9 | * - drivers/tty/serial/amba-pl011.c | |
10 | * - drivers/tty/serial/uartlite.c | |
11 | * - drivers/tty/serial/omap-serial.c | |
12 | * - drivers/pwm/pwm-sifive.c | |
13 | * | |
14 | * See the following sources for further documentation: | |
15 | * - Chapter 19 "Universal Asynchronous Receiver/Transmitter (UART)" of | |
16 | * SiFive FE310-G000 v2p3 | |
17 | * - The tree/master/src/main/scala/devices/uart directory of | |
18 | * https://github.com/sifive/sifive-blocks/ | |
19 | * | |
20 | * The SiFive UART design is not 8250-compatible. The following common | |
21 | * features are not supported: | |
22 | * - Word lengths other than 8 bits | |
23 | * - Break handling | |
24 | * - Parity | |
25 | * - Flow control | |
26 | * - Modem signals (DSR, RI, etc.) | |
27 | * On the other hand, the design is free from the baggage of the 8250 | |
28 | * programming model. | |
29 | */ | |
30 | ||
31 | #include <linux/clk.h> | |
32 | #include <linux/console.h> | |
33 | #include <linux/delay.h> | |
34 | #include <linux/init.h> | |
35 | #include <linux/io.h> | |
36 | #include <linux/irq.h> | |
37 | #include <linux/module.h> | |
38 | #include <linux/of.h> | |
39 | #include <linux/of_irq.h> | |
40 | #include <linux/platform_device.h> | |
41 | #include <linux/serial_core.h> | |
42 | #include <linux/serial_reg.h> | |
43 | #include <linux/slab.h> | |
44 | #include <linux/tty.h> | |
45 | #include <linux/tty_flip.h> | |
46 | ||
47 | /* | |
48 | * Register offsets | |
49 | */ | |
50 | ||
51 | /* TXDATA */ | |
52 | #define SIFIVE_SERIAL_TXDATA_OFFS 0x0 | |
53 | #define SIFIVE_SERIAL_TXDATA_FULL_SHIFT 31 | |
54 | #define SIFIVE_SERIAL_TXDATA_FULL_MASK (1 << SIFIVE_SERIAL_TXDATA_FULL_SHIFT) | |
55 | #define SIFIVE_SERIAL_TXDATA_DATA_SHIFT 0 | |
56 | #define SIFIVE_SERIAL_TXDATA_DATA_MASK (0xff << SIFIVE_SERIAL_TXDATA_DATA_SHIFT) | |
57 | ||
58 | /* RXDATA */ | |
59 | #define SIFIVE_SERIAL_RXDATA_OFFS 0x4 | |
60 | #define SIFIVE_SERIAL_RXDATA_EMPTY_SHIFT 31 | |
61 | #define SIFIVE_SERIAL_RXDATA_EMPTY_MASK (1 << SIFIVE_SERIAL_RXDATA_EMPTY_SHIFT) | |
62 | #define SIFIVE_SERIAL_RXDATA_DATA_SHIFT 0 | |
63 | #define SIFIVE_SERIAL_RXDATA_DATA_MASK (0xff << SIFIVE_SERIAL_RXDATA_DATA_SHIFT) | |
64 | ||
65 | /* TXCTRL */ | |
66 | #define SIFIVE_SERIAL_TXCTRL_OFFS 0x8 | |
67 | #define SIFIVE_SERIAL_TXCTRL_TXCNT_SHIFT 16 | |
68 | #define SIFIVE_SERIAL_TXCTRL_TXCNT_MASK (0x7 << SIFIVE_SERIAL_TXCTRL_TXCNT_SHIFT) | |
69 | #define SIFIVE_SERIAL_TXCTRL_NSTOP_SHIFT 1 | |
70 | #define SIFIVE_SERIAL_TXCTRL_NSTOP_MASK (1 << SIFIVE_SERIAL_TXCTRL_NSTOP_SHIFT) | |
71 | #define SIFIVE_SERIAL_TXCTRL_TXEN_SHIFT 0 | |
72 | #define SIFIVE_SERIAL_TXCTRL_TXEN_MASK (1 << SIFIVE_SERIAL_TXCTRL_TXEN_SHIFT) | |
73 | ||
74 | /* RXCTRL */ | |
75 | #define SIFIVE_SERIAL_RXCTRL_OFFS 0xC | |
76 | #define SIFIVE_SERIAL_RXCTRL_RXCNT_SHIFT 16 | |
77 | #define SIFIVE_SERIAL_RXCTRL_RXCNT_MASK (0x7 << SIFIVE_SERIAL_TXCTRL_TXCNT_SHIFT) | |
78 | #define SIFIVE_SERIAL_RXCTRL_RXEN_SHIFT 0 | |
79 | #define SIFIVE_SERIAL_RXCTRL_RXEN_MASK (1 << SIFIVE_SERIAL_RXCTRL_RXEN_SHIFT) | |
80 | ||
81 | /* IE */ | |
82 | #define SIFIVE_SERIAL_IE_OFFS 0x10 | |
83 | #define SIFIVE_SERIAL_IE_RXWM_SHIFT 1 | |
84 | #define SIFIVE_SERIAL_IE_RXWM_MASK (1 << SIFIVE_SERIAL_IE_RXWM_SHIFT) | |
85 | #define SIFIVE_SERIAL_IE_TXWM_SHIFT 0 | |
86 | #define SIFIVE_SERIAL_IE_TXWM_MASK (1 << SIFIVE_SERIAL_IE_TXWM_SHIFT) | |
87 | ||
88 | /* IP */ | |
89 | #define SIFIVE_SERIAL_IP_OFFS 0x14 | |
90 | #define SIFIVE_SERIAL_IP_RXWM_SHIFT 1 | |
91 | #define SIFIVE_SERIAL_IP_RXWM_MASK (1 << SIFIVE_SERIAL_IP_RXWM_SHIFT) | |
92 | #define SIFIVE_SERIAL_IP_TXWM_SHIFT 0 | |
93 | #define SIFIVE_SERIAL_IP_TXWM_MASK (1 << SIFIVE_SERIAL_IP_TXWM_SHIFT) | |
94 | ||
95 | /* DIV */ | |
96 | #define SIFIVE_SERIAL_DIV_OFFS 0x18 | |
97 | #define SIFIVE_SERIAL_DIV_DIV_SHIFT 0 | |
98 | #define SIFIVE_SERIAL_DIV_DIV_MASK (0xffff << SIFIVE_SERIAL_IP_DIV_SHIFT) | |
99 | ||
100 | /* | |
101 | * Config macros | |
102 | */ | |
103 | ||
104 | /* | |
105 | * SIFIVE_SERIAL_MAX_PORTS: maximum number of UARTs on a device that can | |
106 | * host a serial console | |
107 | */ | |
108 | #define SIFIVE_SERIAL_MAX_PORTS 8 | |
109 | ||
110 | /* | |
111 | * SIFIVE_DEFAULT_BAUD_RATE: default baud rate that the driver should | |
112 | * configure itself to use | |
113 | */ | |
114 | #define SIFIVE_DEFAULT_BAUD_RATE 115200 | |
115 | ||
116 | /* SIFIVE_SERIAL_NAME: our driver's name that we pass to the operating system */ | |
117 | #define SIFIVE_SERIAL_NAME "sifive-serial" | |
118 | ||
119 | /* SIFIVE_TTY_PREFIX: tty name prefix for SiFive serial ports */ | |
120 | #define SIFIVE_TTY_PREFIX "ttySIF" | |
121 | ||
122 | /* SIFIVE_TX_FIFO_DEPTH: depth of the TX FIFO (in bytes) */ | |
123 | #define SIFIVE_TX_FIFO_DEPTH 8 | |
124 | ||
125 | /* SIFIVE_RX_FIFO_DEPTH: depth of the TX FIFO (in bytes) */ | |
126 | #define SIFIVE_RX_FIFO_DEPTH 8 | |
127 | ||
128 | #if (SIFIVE_TX_FIFO_DEPTH != SIFIVE_RX_FIFO_DEPTH) | |
129 | #error Driver does not support configurations with different TX, RX FIFO sizes | |
130 | #endif | |
131 | ||
132 | /* | |
133 | * | |
134 | */ | |
135 | ||
136 | /** | |
180bb243 | 137 | * struct sifive_serial_port - driver-specific data extension to struct uart_port |
45c054d0 PW |
138 | * @port: struct uart_port embedded in this struct |
139 | * @dev: struct device * | |
140 | * @ier: shadowed copy of the interrupt enable register | |
45c054d0 | 141 | * @baud_rate: UART serial line rate (e.g., 115200 baud) |
180bb243 | 142 | * @clk: reference to this device's clock |
45c054d0 PW |
143 | * @clk_notifier: clock rate change notifier for upstream clock changes |
144 | * | |
145 | * Configuration data specific to this SiFive UART. | |
146 | */ | |
147 | struct sifive_serial_port { | |
148 | struct uart_port port; | |
149 | struct device *dev; | |
150 | unsigned char ier; | |
45c054d0 PW |
151 | unsigned long baud_rate; |
152 | struct clk *clk; | |
153 | struct notifier_block clk_notifier; | |
154 | }; | |
155 | ||
156 | /* | |
157 | * Structure container-of macros | |
158 | */ | |
159 | ||
160 | #define port_to_sifive_serial_port(p) (container_of((p), \ | |
161 | struct sifive_serial_port, \ | |
162 | port)) | |
163 | ||
164 | #define notifier_to_sifive_serial_port(nb) (container_of((nb), \ | |
165 | struct sifive_serial_port, \ | |
166 | clk_notifier)) | |
167 | ||
168 | /* | |
169 | * Forward declarations | |
170 | */ | |
171 | static void sifive_serial_stop_tx(struct uart_port *port); | |
172 | ||
173 | /* | |
174 | * Internal functions | |
175 | */ | |
176 | ||
177 | /** | |
178 | * __ssp_early_writel() - write to a SiFive serial port register (early) | |
179 | * @port: pointer to a struct uart_port record | |
180 | * @offs: register address offset from the IP block base address | |
181 | * @v: value to write to the register | |
182 | * | |
183 | * Given a pointer @port to a struct uart_port record, write the value | |
184 | * @v to the IP block register address offset @offs. This function is | |
185 | * intended for early console use. | |
186 | * | |
187 | * Context: Intended to be used only by the earlyconsole code. | |
188 | */ | |
189 | static void __ssp_early_writel(u32 v, u16 offs, struct uart_port *port) | |
190 | { | |
191 | writel_relaxed(v, port->membase + offs); | |
192 | } | |
193 | ||
194 | /** | |
195 | * __ssp_early_readl() - read from a SiFive serial port register (early) | |
196 | * @port: pointer to a struct uart_port record | |
197 | * @offs: register address offset from the IP block base address | |
198 | * | |
199 | * Given a pointer @port to a struct uart_port record, read the | |
200 | * contents of the IP block register located at offset @offs from the | |
201 | * IP block base and return it. This function is intended for early | |
202 | * console use. | |
203 | * | |
204 | * Context: Intended to be called only by the earlyconsole code or by | |
205 | * __ssp_readl() or __ssp_writel() (in this driver) | |
206 | * | |
207 | * Returns: the register value read from the UART. | |
208 | */ | |
209 | static u32 __ssp_early_readl(struct uart_port *port, u16 offs) | |
210 | { | |
211 | return readl_relaxed(port->membase + offs); | |
212 | } | |
213 | ||
214 | /** | |
215 | * __ssp_writel() - write to a SiFive serial port register | |
216 | * @v: value to write to the register | |
217 | * @offs: register address offset from the IP block base address | |
218 | * @ssp: pointer to a struct sifive_serial_port record | |
219 | * | |
220 | * Write the value @v to the IP block register located at offset @offs from the | |
221 | * IP block base, given a pointer @ssp to a struct sifive_serial_port record. | |
222 | * | |
223 | * Context: Any context. | |
224 | */ | |
225 | static void __ssp_writel(u32 v, u16 offs, struct sifive_serial_port *ssp) | |
226 | { | |
227 | __ssp_early_writel(v, offs, &ssp->port); | |
228 | } | |
229 | ||
230 | /** | |
231 | * __ssp_readl() - read from a SiFive serial port register | |
232 | * @ssp: pointer to a struct sifive_serial_port record | |
233 | * @offs: register address offset from the IP block base address | |
234 | * | |
235 | * Read the contents of the IP block register located at offset @offs from the | |
236 | * IP block base, given a pointer @ssp to a struct sifive_serial_port record. | |
237 | * | |
238 | * Context: Any context. | |
239 | * | |
240 | * Returns: the value of the UART register | |
241 | */ | |
242 | static u32 __ssp_readl(struct sifive_serial_port *ssp, u16 offs) | |
243 | { | |
244 | return __ssp_early_readl(&ssp->port, offs); | |
245 | } | |
246 | ||
247 | /** | |
248 | * sifive_serial_is_txfifo_full() - is the TXFIFO full? | |
249 | * @ssp: pointer to a struct sifive_serial_port | |
250 | * | |
251 | * Read the transmit FIFO "full" bit, returning a non-zero value if the | |
252 | * TX FIFO is full, or zero if space remains. Intended to be used to prevent | |
253 | * writes to the TX FIFO when it's full. | |
254 | * | |
255 | * Returns: SIFIVE_SERIAL_TXDATA_FULL_MASK (non-zero) if the transmit FIFO | |
256 | * is full, or 0 if space remains. | |
257 | */ | |
258 | static int sifive_serial_is_txfifo_full(struct sifive_serial_port *ssp) | |
259 | { | |
260 | return __ssp_readl(ssp, SIFIVE_SERIAL_TXDATA_OFFS) & | |
261 | SIFIVE_SERIAL_TXDATA_FULL_MASK; | |
262 | } | |
263 | ||
264 | /** | |
265 | * __ssp_transmit_char() - enqueue a byte to transmit onto the TX FIFO | |
266 | * @ssp: pointer to a struct sifive_serial_port | |
267 | * @ch: character to transmit | |
268 | * | |
269 | * Enqueue a byte @ch onto the transmit FIFO, given a pointer @ssp to the | |
270 | * struct sifive_serial_port * to transmit on. Caller should first check to | |
271 | * ensure that the TXFIFO has space; see sifive_serial_is_txfifo_full(). | |
272 | * | |
273 | * Context: Any context. | |
274 | */ | |
275 | static void __ssp_transmit_char(struct sifive_serial_port *ssp, int ch) | |
276 | { | |
277 | __ssp_writel(ch, SIFIVE_SERIAL_TXDATA_OFFS, ssp); | |
278 | } | |
279 | ||
280 | /** | |
281 | * __ssp_transmit_chars() - enqueue multiple bytes onto the TX FIFO | |
282 | * @ssp: pointer to a struct sifive_serial_port | |
283 | * | |
284 | * Transfer up to a TX FIFO size's worth of characters from the Linux serial | |
285 | * transmit buffer to the SiFive UART TX FIFO. | |
286 | * | |
287 | * Context: Any context. Expects @ssp->port.lock to be held by caller. | |
288 | */ | |
289 | static void __ssp_transmit_chars(struct sifive_serial_port *ssp) | |
290 | { | |
d11cc8c3 | 291 | u8 ch; |
45c054d0 | 292 | |
d11cc8c3 JSS |
293 | uart_port_tx_limited(&ssp->port, ch, SIFIVE_TX_FIFO_DEPTH, |
294 | true, | |
295 | __ssp_transmit_char(ssp, ch), | |
296 | ({})); | |
45c054d0 PW |
297 | } |
298 | ||
299 | /** | |
300 | * __ssp_enable_txwm() - enable transmit watermark interrupts | |
301 | * @ssp: pointer to a struct sifive_serial_port | |
302 | * | |
303 | * Enable interrupt generation when the transmit FIFO watermark is reached | |
304 | * on the SiFive UART referred to by @ssp. | |
305 | */ | |
306 | static void __ssp_enable_txwm(struct sifive_serial_port *ssp) | |
307 | { | |
308 | if (ssp->ier & SIFIVE_SERIAL_IE_TXWM_MASK) | |
309 | return; | |
310 | ||
311 | ssp->ier |= SIFIVE_SERIAL_IE_TXWM_MASK; | |
312 | __ssp_writel(ssp->ier, SIFIVE_SERIAL_IE_OFFS, ssp); | |
313 | } | |
314 | ||
315 | /** | |
316 | * __ssp_enable_rxwm() - enable receive watermark interrupts | |
317 | * @ssp: pointer to a struct sifive_serial_port | |
318 | * | |
319 | * Enable interrupt generation when the receive FIFO watermark is reached | |
320 | * on the SiFive UART referred to by @ssp. | |
321 | */ | |
322 | static void __ssp_enable_rxwm(struct sifive_serial_port *ssp) | |
323 | { | |
324 | if (ssp->ier & SIFIVE_SERIAL_IE_RXWM_MASK) | |
325 | return; | |
326 | ||
327 | ssp->ier |= SIFIVE_SERIAL_IE_RXWM_MASK; | |
328 | __ssp_writel(ssp->ier, SIFIVE_SERIAL_IE_OFFS, ssp); | |
329 | } | |
330 | ||
331 | /** | |
332 | * __ssp_disable_txwm() - disable transmit watermark interrupts | |
333 | * @ssp: pointer to a struct sifive_serial_port | |
334 | * | |
335 | * Disable interrupt generation when the transmit FIFO watermark is reached | |
336 | * on the UART referred to by @ssp. | |
337 | */ | |
338 | static void __ssp_disable_txwm(struct sifive_serial_port *ssp) | |
339 | { | |
340 | if (!(ssp->ier & SIFIVE_SERIAL_IE_TXWM_MASK)) | |
341 | return; | |
342 | ||
343 | ssp->ier &= ~SIFIVE_SERIAL_IE_TXWM_MASK; | |
344 | __ssp_writel(ssp->ier, SIFIVE_SERIAL_IE_OFFS, ssp); | |
345 | } | |
346 | ||
347 | /** | |
348 | * __ssp_disable_rxwm() - disable receive watermark interrupts | |
349 | * @ssp: pointer to a struct sifive_serial_port | |
350 | * | |
351 | * Disable interrupt generation when the receive FIFO watermark is reached | |
352 | * on the UART referred to by @ssp. | |
353 | */ | |
354 | static void __ssp_disable_rxwm(struct sifive_serial_port *ssp) | |
355 | { | |
356 | if (!(ssp->ier & SIFIVE_SERIAL_IE_RXWM_MASK)) | |
357 | return; | |
358 | ||
359 | ssp->ier &= ~SIFIVE_SERIAL_IE_RXWM_MASK; | |
360 | __ssp_writel(ssp->ier, SIFIVE_SERIAL_IE_OFFS, ssp); | |
361 | } | |
362 | ||
363 | /** | |
364 | * __ssp_receive_char() - receive a byte from the UART | |
365 | * @ssp: pointer to a struct sifive_serial_port | |
366 | * @is_empty: char pointer to return whether the RX FIFO is empty | |
367 | * | |
368 | * Try to read a byte from the SiFive UART RX FIFO, referenced by | |
369 | * @ssp, and to return it. Also returns the RX FIFO empty bit in | |
370 | * the char pointed to by @ch. The caller must pass the byte back to the | |
371 | * Linux serial layer if needed. | |
372 | * | |
373 | * Returns: the byte read from the UART RX FIFO. | |
374 | */ | |
375 | static char __ssp_receive_char(struct sifive_serial_port *ssp, char *is_empty) | |
376 | { | |
377 | u32 v; | |
378 | u8 ch; | |
379 | ||
380 | v = __ssp_readl(ssp, SIFIVE_SERIAL_RXDATA_OFFS); | |
381 | ||
382 | if (!is_empty) | |
383 | WARN_ON(1); | |
384 | else | |
385 | *is_empty = (v & SIFIVE_SERIAL_RXDATA_EMPTY_MASK) >> | |
386 | SIFIVE_SERIAL_RXDATA_EMPTY_SHIFT; | |
387 | ||
388 | ch = (v & SIFIVE_SERIAL_RXDATA_DATA_MASK) >> | |
389 | SIFIVE_SERIAL_RXDATA_DATA_SHIFT; | |
390 | ||
391 | return ch; | |
392 | } | |
393 | ||
394 | /** | |
395 | * __ssp_receive_chars() - receive multiple bytes from the UART | |
396 | * @ssp: pointer to a struct sifive_serial_port | |
397 | * | |
398 | * Receive up to an RX FIFO's worth of bytes from the SiFive UART referred | |
399 | * to by @ssp and pass them up to the Linux serial layer. | |
400 | * | |
401 | * Context: Expects ssp->port.lock to be held by caller. | |
402 | */ | |
403 | static void __ssp_receive_chars(struct sifive_serial_port *ssp) | |
404 | { | |
405 | unsigned char ch; | |
406 | char is_empty; | |
407 | int c; | |
408 | ||
409 | for (c = SIFIVE_RX_FIFO_DEPTH; c > 0; --c) { | |
410 | ch = __ssp_receive_char(ssp, &is_empty); | |
411 | if (is_empty) | |
412 | break; | |
413 | ||
414 | ssp->port.icount.rx++; | |
415 | uart_insert_char(&ssp->port, 0, 0, ch, TTY_NORMAL); | |
416 | } | |
417 | ||
45c054d0 | 418 | tty_flip_buffer_push(&ssp->port.state->port); |
45c054d0 PW |
419 | } |
420 | ||
421 | /** | |
422 | * __ssp_update_div() - calculate the divisor setting by the line rate | |
423 | * @ssp: pointer to a struct sifive_serial_port | |
424 | * | |
425 | * Calculate the appropriate value of the clock divisor for the UART | |
426 | * and target line rate referred to by @ssp and write it into the | |
427 | * hardware. | |
428 | */ | |
429 | static void __ssp_update_div(struct sifive_serial_port *ssp) | |
430 | { | |
431 | u16 div; | |
432 | ||
4487cd3e | 433 | div = DIV_ROUND_UP(ssp->port.uartclk, ssp->baud_rate) - 1; |
45c054d0 PW |
434 | |
435 | __ssp_writel(div, SIFIVE_SERIAL_DIV_OFFS, ssp); | |
436 | } | |
437 | ||
438 | /** | |
439 | * __ssp_update_baud_rate() - set the UART "baud rate" | |
440 | * @ssp: pointer to a struct sifive_serial_port | |
441 | * @rate: new target bit rate | |
442 | * | |
443 | * Calculate the UART divisor value for the target bit rate @rate for the | |
444 | * SiFive UART described by @ssp and program it into the UART. There may | |
445 | * be some error between the target bit rate and the actual bit rate implemented | |
446 | * by the UART due to clock ratio granularity. | |
447 | */ | |
448 | static void __ssp_update_baud_rate(struct sifive_serial_port *ssp, | |
449 | unsigned int rate) | |
450 | { | |
451 | if (ssp->baud_rate == rate) | |
452 | return; | |
453 | ||
454 | ssp->baud_rate = rate; | |
455 | __ssp_update_div(ssp); | |
456 | } | |
457 | ||
458 | /** | |
459 | * __ssp_set_stop_bits() - set the number of stop bits | |
460 | * @ssp: pointer to a struct sifive_serial_port | |
461 | * @nstop: 1 or 2 (stop bits) | |
462 | * | |
463 | * Program the SiFive UART referred to by @ssp to use @nstop stop bits. | |
464 | */ | |
465 | static void __ssp_set_stop_bits(struct sifive_serial_port *ssp, char nstop) | |
466 | { | |
467 | u32 v; | |
468 | ||
469 | if (nstop < 1 || nstop > 2) { | |
470 | WARN_ON(1); | |
471 | return; | |
472 | } | |
473 | ||
474 | v = __ssp_readl(ssp, SIFIVE_SERIAL_TXCTRL_OFFS); | |
475 | v &= ~SIFIVE_SERIAL_TXCTRL_NSTOP_MASK; | |
476 | v |= (nstop - 1) << SIFIVE_SERIAL_TXCTRL_NSTOP_SHIFT; | |
477 | __ssp_writel(v, SIFIVE_SERIAL_TXCTRL_OFFS, ssp); | |
478 | } | |
479 | ||
480 | /** | |
481 | * __ssp_wait_for_xmitr() - wait for an empty slot on the TX FIFO | |
482 | * @ssp: pointer to a struct sifive_serial_port | |
483 | * | |
484 | * Delay while the UART TX FIFO referred to by @ssp is marked as full. | |
485 | * | |
486 | * Context: Any context. | |
487 | */ | |
488 | static void __maybe_unused __ssp_wait_for_xmitr(struct sifive_serial_port *ssp) | |
489 | { | |
490 | while (sifive_serial_is_txfifo_full(ssp)) | |
491 | udelay(1); /* XXX Could probably be more intelligent here */ | |
492 | } | |
493 | ||
494 | /* | |
495 | * Linux serial API functions | |
496 | */ | |
497 | ||
498 | static void sifive_serial_stop_tx(struct uart_port *port) | |
499 | { | |
500 | struct sifive_serial_port *ssp = port_to_sifive_serial_port(port); | |
501 | ||
502 | __ssp_disable_txwm(ssp); | |
503 | } | |
504 | ||
505 | static void sifive_serial_stop_rx(struct uart_port *port) | |
506 | { | |
507 | struct sifive_serial_port *ssp = port_to_sifive_serial_port(port); | |
508 | ||
509 | __ssp_disable_rxwm(ssp); | |
510 | } | |
511 | ||
512 | static void sifive_serial_start_tx(struct uart_port *port) | |
513 | { | |
514 | struct sifive_serial_port *ssp = port_to_sifive_serial_port(port); | |
515 | ||
516 | __ssp_enable_txwm(ssp); | |
517 | } | |
518 | ||
519 | static irqreturn_t sifive_serial_irq(int irq, void *dev_id) | |
520 | { | |
521 | struct sifive_serial_port *ssp = dev_id; | |
522 | u32 ip; | |
523 | ||
524 | spin_lock(&ssp->port.lock); | |
525 | ||
526 | ip = __ssp_readl(ssp, SIFIVE_SERIAL_IP_OFFS); | |
527 | if (!ip) { | |
528 | spin_unlock(&ssp->port.lock); | |
529 | return IRQ_NONE; | |
530 | } | |
531 | ||
532 | if (ip & SIFIVE_SERIAL_IP_RXWM_MASK) | |
533 | __ssp_receive_chars(ssp); | |
534 | if (ip & SIFIVE_SERIAL_IP_TXWM_MASK) | |
535 | __ssp_transmit_chars(ssp); | |
536 | ||
537 | spin_unlock(&ssp->port.lock); | |
538 | ||
539 | return IRQ_HANDLED; | |
540 | } | |
541 | ||
542 | static unsigned int sifive_serial_tx_empty(struct uart_port *port) | |
543 | { | |
544 | return TIOCSER_TEMT; | |
545 | } | |
546 | ||
547 | static unsigned int sifive_serial_get_mctrl(struct uart_port *port) | |
548 | { | |
549 | return TIOCM_CAR | TIOCM_CTS | TIOCM_DSR; | |
550 | } | |
551 | ||
552 | static void sifive_serial_set_mctrl(struct uart_port *port, unsigned int mctrl) | |
553 | { | |
554 | /* IP block does not support these signals */ | |
555 | } | |
556 | ||
557 | static void sifive_serial_break_ctl(struct uart_port *port, int break_state) | |
558 | { | |
559 | /* IP block does not support sending a break */ | |
560 | } | |
561 | ||
562 | static int sifive_serial_startup(struct uart_port *port) | |
563 | { | |
564 | struct sifive_serial_port *ssp = port_to_sifive_serial_port(port); | |
565 | ||
566 | __ssp_enable_rxwm(ssp); | |
567 | ||
568 | return 0; | |
569 | } | |
570 | ||
571 | static void sifive_serial_shutdown(struct uart_port *port) | |
572 | { | |
573 | struct sifive_serial_port *ssp = port_to_sifive_serial_port(port); | |
574 | ||
575 | __ssp_disable_rxwm(ssp); | |
576 | __ssp_disable_txwm(ssp); | |
577 | } | |
578 | ||
579 | /** | |
580 | * sifive_serial_clk_notifier() - clock post-rate-change notifier | |
581 | * @nb: pointer to the struct notifier_block, from the notifier code | |
582 | * @event: event mask from the notifier code | |
583 | * @data: pointer to the struct clk_notifier_data from the notifier code | |
584 | * | |
585 | * On the V0 SoC, the UART IP block is derived from the CPU clock source | |
586 | * after a synchronous divide-by-two divider, so any CPU clock rate change | |
4cbd7814 PD |
587 | * requires the UART baud rate to be updated. This presumably corrupts any |
588 | * serial word currently being transmitted or received. In order to avoid | |
589 | * corrupting the output data stream, we drain the transmit queue before | |
590 | * allowing the clock's rate to be changed. | |
45c054d0 PW |
591 | */ |
592 | static int sifive_serial_clk_notifier(struct notifier_block *nb, | |
593 | unsigned long event, void *data) | |
594 | { | |
595 | struct clk_notifier_data *cnd = data; | |
596 | struct sifive_serial_port *ssp = notifier_to_sifive_serial_port(nb); | |
597 | ||
4cbd7814 PD |
598 | if (event == PRE_RATE_CHANGE) { |
599 | /* | |
600 | * The TX watermark is always set to 1 by this driver, which | |
601 | * means that the TX busy bit will lower when there are 0 bytes | |
602 | * left in the TX queue -- in other words, when the TX FIFO is | |
603 | * empty. | |
604 | */ | |
605 | __ssp_wait_for_xmitr(ssp); | |
606 | /* | |
607 | * On the cycle the TX FIFO goes empty there is still a full | |
608 | * UART frame left to be transmitted in the shift register. | |
609 | * The UART provides no way for software to directly determine | |
610 | * when that last frame has been transmitted, so we just sleep | |
611 | * here instead. As we're not tracking the number of stop bits | |
612 | * they're just worst cased here. The rest of the serial | |
613 | * framing parameters aren't configurable by software. | |
614 | */ | |
615 | udelay(DIV_ROUND_UP(12 * 1000 * 1000, ssp->baud_rate)); | |
616 | } | |
617 | ||
4487cd3e MR |
618 | if (event == POST_RATE_CHANGE && ssp->port.uartclk != cnd->new_rate) { |
619 | ssp->port.uartclk = cnd->new_rate; | |
45c054d0 PW |
620 | __ssp_update_div(ssp); |
621 | } | |
622 | ||
623 | return NOTIFY_OK; | |
624 | } | |
625 | ||
626 | static void sifive_serial_set_termios(struct uart_port *port, | |
627 | struct ktermios *termios, | |
bec5b814 | 628 | const struct ktermios *old) |
45c054d0 PW |
629 | { |
630 | struct sifive_serial_port *ssp = port_to_sifive_serial_port(port); | |
631 | unsigned long flags; | |
632 | u32 v, old_v; | |
633 | int rate; | |
634 | char nstop; | |
635 | ||
c069d275 | 636 | if ((termios->c_cflag & CSIZE) != CS8) { |
45c054d0 | 637 | dev_err_once(ssp->port.dev, "only 8-bit words supported\n"); |
c069d275 IJ |
638 | termios->c_cflag &= ~CSIZE; |
639 | termios->c_cflag |= CS8; | |
640 | } | |
45c054d0 PW |
641 | if (termios->c_iflag & (INPCK | PARMRK)) |
642 | dev_err_once(ssp->port.dev, "parity checking not supported\n"); | |
643 | if (termios->c_iflag & BRKINT) | |
644 | dev_err_once(ssp->port.dev, "BREAK detection not supported\n"); | |
c069d275 | 645 | termios->c_iflag &= ~(INPCK|PARMRK|BRKINT); |
45c054d0 PW |
646 | |
647 | /* Set number of stop bits */ | |
648 | nstop = (termios->c_cflag & CSTOPB) ? 2 : 1; | |
649 | __ssp_set_stop_bits(ssp, nstop); | |
650 | ||
651 | /* Set line rate */ | |
4487cd3e MR |
652 | rate = uart_get_baud_rate(port, termios, old, 0, |
653 | ssp->port.uartclk / 16); | |
45c054d0 PW |
654 | __ssp_update_baud_rate(ssp, rate); |
655 | ||
656 | spin_lock_irqsave(&ssp->port.lock, flags); | |
657 | ||
658 | /* Update the per-port timeout */ | |
659 | uart_update_timeout(port, termios->c_cflag, rate); | |
660 | ||
661 | ssp->port.read_status_mask = 0; | |
662 | ||
663 | /* Ignore all characters if CREAD is not set */ | |
664 | v = __ssp_readl(ssp, SIFIVE_SERIAL_RXCTRL_OFFS); | |
665 | old_v = v; | |
666 | if ((termios->c_cflag & CREAD) == 0) | |
667 | v &= SIFIVE_SERIAL_RXCTRL_RXEN_MASK; | |
668 | else | |
669 | v |= SIFIVE_SERIAL_RXCTRL_RXEN_MASK; | |
670 | if (v != old_v) | |
671 | __ssp_writel(v, SIFIVE_SERIAL_RXCTRL_OFFS, ssp); | |
672 | ||
673 | spin_unlock_irqrestore(&ssp->port.lock, flags); | |
674 | } | |
675 | ||
676 | static void sifive_serial_release_port(struct uart_port *port) | |
677 | { | |
678 | } | |
679 | ||
680 | static int sifive_serial_request_port(struct uart_port *port) | |
681 | { | |
682 | return 0; | |
683 | } | |
684 | ||
685 | static void sifive_serial_config_port(struct uart_port *port, int flags) | |
686 | { | |
687 | struct sifive_serial_port *ssp = port_to_sifive_serial_port(port); | |
688 | ||
689 | ssp->port.type = PORT_SIFIVE_V0; | |
690 | } | |
691 | ||
692 | static int sifive_serial_verify_port(struct uart_port *port, | |
693 | struct serial_struct *ser) | |
694 | { | |
695 | return -EINVAL; | |
696 | } | |
697 | ||
698 | static const char *sifive_serial_type(struct uart_port *port) | |
699 | { | |
700 | return port->type == PORT_SIFIVE_V0 ? "SiFive UART v0" : NULL; | |
701 | } | |
702 | ||
630db5cb VC |
703 | #ifdef CONFIG_CONSOLE_POLL |
704 | static int sifive_serial_poll_get_char(struct uart_port *port) | |
705 | { | |
706 | struct sifive_serial_port *ssp = port_to_sifive_serial_port(port); | |
707 | char is_empty, ch; | |
708 | ||
709 | ch = __ssp_receive_char(ssp, &is_empty); | |
710 | if (is_empty) | |
711 | return NO_POLL_CHAR; | |
712 | ||
713 | return ch; | |
714 | } | |
715 | ||
716 | static void sifive_serial_poll_put_char(struct uart_port *port, | |
717 | unsigned char c) | |
718 | { | |
719 | struct sifive_serial_port *ssp = port_to_sifive_serial_port(port); | |
720 | ||
721 | __ssp_wait_for_xmitr(ssp); | |
722 | __ssp_transmit_char(ssp, c); | |
723 | } | |
724 | #endif /* CONFIG_CONSOLE_POLL */ | |
725 | ||
45c054d0 PW |
726 | /* |
727 | * Early console support | |
728 | */ | |
729 | ||
730 | #ifdef CONFIG_SERIAL_EARLYCON | |
3f8bab17 | 731 | static void early_sifive_serial_putc(struct uart_port *port, unsigned char c) |
45c054d0 PW |
732 | { |
733 | while (__ssp_early_readl(port, SIFIVE_SERIAL_TXDATA_OFFS) & | |
734 | SIFIVE_SERIAL_TXDATA_FULL_MASK) | |
735 | cpu_relax(); | |
736 | ||
737 | __ssp_early_writel(c, SIFIVE_SERIAL_TXDATA_OFFS, port); | |
738 | } | |
739 | ||
740 | static void early_sifive_serial_write(struct console *con, const char *s, | |
741 | unsigned int n) | |
742 | { | |
743 | struct earlycon_device *dev = con->data; | |
744 | struct uart_port *port = &dev->port; | |
745 | ||
746 | uart_console_write(port, s, n, early_sifive_serial_putc); | |
747 | } | |
748 | ||
749 | static int __init early_sifive_serial_setup(struct earlycon_device *dev, | |
750 | const char *options) | |
751 | { | |
752 | struct uart_port *port = &dev->port; | |
753 | ||
754 | if (!port->membase) | |
755 | return -ENODEV; | |
756 | ||
757 | dev->con->write = early_sifive_serial_write; | |
758 | ||
759 | return 0; | |
760 | } | |
761 | ||
762 | OF_EARLYCON_DECLARE(sifive, "sifive,uart0", early_sifive_serial_setup); | |
763 | OF_EARLYCON_DECLARE(sifive, "sifive,fu540-c000-uart0", | |
764 | early_sifive_serial_setup); | |
765 | #endif /* CONFIG_SERIAL_EARLYCON */ | |
766 | ||
767 | /* | |
768 | * Linux console interface | |
769 | */ | |
770 | ||
771 | #ifdef CONFIG_SERIAL_SIFIVE_CONSOLE | |
772 | ||
773 | static struct sifive_serial_port *sifive_serial_console_ports[SIFIVE_SERIAL_MAX_PORTS]; | |
774 | ||
3f8bab17 | 775 | static void sifive_serial_console_putchar(struct uart_port *port, unsigned char ch) |
45c054d0 PW |
776 | { |
777 | struct sifive_serial_port *ssp = port_to_sifive_serial_port(port); | |
778 | ||
779 | __ssp_wait_for_xmitr(ssp); | |
780 | __ssp_transmit_char(ssp, ch); | |
781 | } | |
782 | ||
783 | static void sifive_serial_console_write(struct console *co, const char *s, | |
784 | unsigned int count) | |
785 | { | |
786 | struct sifive_serial_port *ssp = sifive_serial_console_ports[co->index]; | |
787 | unsigned long flags; | |
788 | unsigned int ier; | |
789 | int locked = 1; | |
790 | ||
791 | if (!ssp) | |
792 | return; | |
793 | ||
794 | local_irq_save(flags); | |
795 | if (ssp->port.sysrq) | |
796 | locked = 0; | |
797 | else if (oops_in_progress) | |
798 | locked = spin_trylock(&ssp->port.lock); | |
799 | else | |
800 | spin_lock(&ssp->port.lock); | |
801 | ||
802 | ier = __ssp_readl(ssp, SIFIVE_SERIAL_IE_OFFS); | |
803 | __ssp_writel(0, SIFIVE_SERIAL_IE_OFFS, ssp); | |
804 | ||
805 | uart_console_write(&ssp->port, s, count, sifive_serial_console_putchar); | |
806 | ||
807 | __ssp_writel(ier, SIFIVE_SERIAL_IE_OFFS, ssp); | |
808 | ||
809 | if (locked) | |
810 | spin_unlock(&ssp->port.lock); | |
811 | local_irq_restore(flags); | |
812 | } | |
813 | ||
9b8fef63 | 814 | static int sifive_serial_console_setup(struct console *co, char *options) |
45c054d0 PW |
815 | { |
816 | struct sifive_serial_port *ssp; | |
817 | int baud = SIFIVE_DEFAULT_BAUD_RATE; | |
818 | int bits = 8; | |
819 | int parity = 'n'; | |
820 | int flow = 'n'; | |
821 | ||
822 | if (co->index < 0 || co->index >= SIFIVE_SERIAL_MAX_PORTS) | |
823 | return -ENODEV; | |
824 | ||
825 | ssp = sifive_serial_console_ports[co->index]; | |
826 | if (!ssp) | |
827 | return -ENODEV; | |
828 | ||
829 | if (options) | |
830 | uart_parse_options(options, &baud, &parity, &bits, &flow); | |
831 | ||
832 | return uart_set_options(&ssp->port, co, baud, parity, bits, flow); | |
833 | } | |
834 | ||
835 | static struct uart_driver sifive_serial_uart_driver; | |
836 | ||
837 | static struct console sifive_serial_console = { | |
838 | .name = SIFIVE_TTY_PREFIX, | |
839 | .write = sifive_serial_console_write, | |
840 | .device = uart_console_device, | |
841 | .setup = sifive_serial_console_setup, | |
842 | .flags = CON_PRINTBUFFER, | |
843 | .index = -1, | |
844 | .data = &sifive_serial_uart_driver, | |
845 | }; | |
846 | ||
847 | static int __init sifive_console_init(void) | |
848 | { | |
849 | register_console(&sifive_serial_console); | |
850 | return 0; | |
851 | } | |
852 | ||
853 | console_initcall(sifive_console_init); | |
854 | ||
855 | static void __ssp_add_console_port(struct sifive_serial_port *ssp) | |
856 | { | |
857 | sifive_serial_console_ports[ssp->port.line] = ssp; | |
858 | } | |
859 | ||
860 | static void __ssp_remove_console_port(struct sifive_serial_port *ssp) | |
861 | { | |
27e8c8b4 | 862 | sifive_serial_console_ports[ssp->port.line] = NULL; |
45c054d0 PW |
863 | } |
864 | ||
865 | #define SIFIVE_SERIAL_CONSOLE (&sifive_serial_console) | |
866 | ||
867 | #else | |
868 | ||
869 | #define SIFIVE_SERIAL_CONSOLE NULL | |
870 | ||
871 | static void __ssp_add_console_port(struct sifive_serial_port *ssp) | |
872 | {} | |
873 | static void __ssp_remove_console_port(struct sifive_serial_port *ssp) | |
874 | {} | |
875 | ||
876 | #endif | |
877 | ||
878 | static const struct uart_ops sifive_serial_uops = { | |
879 | .tx_empty = sifive_serial_tx_empty, | |
880 | .set_mctrl = sifive_serial_set_mctrl, | |
881 | .get_mctrl = sifive_serial_get_mctrl, | |
882 | .stop_tx = sifive_serial_stop_tx, | |
883 | .start_tx = sifive_serial_start_tx, | |
884 | .stop_rx = sifive_serial_stop_rx, | |
885 | .break_ctl = sifive_serial_break_ctl, | |
886 | .startup = sifive_serial_startup, | |
887 | .shutdown = sifive_serial_shutdown, | |
888 | .set_termios = sifive_serial_set_termios, | |
889 | .type = sifive_serial_type, | |
890 | .release_port = sifive_serial_release_port, | |
891 | .request_port = sifive_serial_request_port, | |
892 | .config_port = sifive_serial_config_port, | |
893 | .verify_port = sifive_serial_verify_port, | |
630db5cb VC |
894 | #ifdef CONFIG_CONSOLE_POLL |
895 | .poll_get_char = sifive_serial_poll_get_char, | |
896 | .poll_put_char = sifive_serial_poll_put_char, | |
897 | #endif | |
45c054d0 PW |
898 | }; |
899 | ||
900 | static struct uart_driver sifive_serial_uart_driver = { | |
901 | .owner = THIS_MODULE, | |
902 | .driver_name = SIFIVE_SERIAL_NAME, | |
903 | .dev_name = SIFIVE_TTY_PREFIX, | |
904 | .nr = SIFIVE_SERIAL_MAX_PORTS, | |
905 | .cons = SIFIVE_SERIAL_CONSOLE, | |
906 | }; | |
907 | ||
908 | static int sifive_serial_probe(struct platform_device *pdev) | |
909 | { | |
910 | struct sifive_serial_port *ssp; | |
911 | struct resource *mem; | |
912 | struct clk *clk; | |
913 | void __iomem *base; | |
914 | int irq, id, r; | |
915 | ||
916 | irq = platform_get_irq(pdev, 0); | |
1df21786 | 917 | if (irq < 0) |
45c054d0 | 918 | return -EPROBE_DEFER; |
45c054d0 PW |
919 | |
920 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
921 | base = devm_ioremap_resource(&pdev->dev, mem); | |
922 | if (IS_ERR(base)) { | |
923 | dev_err(&pdev->dev, "could not acquire device memory\n"); | |
924 | return PTR_ERR(base); | |
925 | } | |
926 | ||
64379204 | 927 | clk = devm_clk_get_enabled(&pdev->dev, NULL); |
45c054d0 PW |
928 | if (IS_ERR(clk)) { |
929 | dev_err(&pdev->dev, "unable to find controller clock\n"); | |
930 | return PTR_ERR(clk); | |
931 | } | |
932 | ||
933 | id = of_alias_get_id(pdev->dev.of_node, "serial"); | |
934 | if (id < 0) { | |
935 | dev_err(&pdev->dev, "missing aliases entry\n"); | |
936 | return id; | |
937 | } | |
938 | ||
939 | #ifdef CONFIG_SERIAL_SIFIVE_CONSOLE | |
940 | if (id > SIFIVE_SERIAL_MAX_PORTS) { | |
941 | dev_err(&pdev->dev, "too many UARTs (%d)\n", id); | |
942 | return -EINVAL; | |
943 | } | |
944 | #endif | |
945 | ||
946 | ssp = devm_kzalloc(&pdev->dev, sizeof(*ssp), GFP_KERNEL); | |
947 | if (!ssp) | |
948 | return -ENOMEM; | |
949 | ||
950 | ssp->port.dev = &pdev->dev; | |
951 | ssp->port.type = PORT_SIFIVE_V0; | |
952 | ssp->port.iotype = UPIO_MEM; | |
953 | ssp->port.irq = irq; | |
954 | ssp->port.fifosize = SIFIVE_TX_FIFO_DEPTH; | |
955 | ssp->port.ops = &sifive_serial_uops; | |
956 | ssp->port.line = id; | |
957 | ssp->port.mapbase = mem->start; | |
958 | ssp->port.membase = base; | |
959 | ssp->dev = &pdev->dev; | |
960 | ssp->clk = clk; | |
961 | ssp->clk_notifier.notifier_call = sifive_serial_clk_notifier; | |
962 | ||
963 | r = clk_notifier_register(ssp->clk, &ssp->clk_notifier); | |
964 | if (r) { | |
965 | dev_err(&pdev->dev, "could not register clock notifier: %d\n", | |
966 | r); | |
967 | goto probe_out1; | |
968 | } | |
969 | ||
970 | /* Set up clock divider */ | |
4487cd3e | 971 | ssp->port.uartclk = clk_get_rate(ssp->clk); |
45c054d0 PW |
972 | ssp->baud_rate = SIFIVE_DEFAULT_BAUD_RATE; |
973 | __ssp_update_div(ssp); | |
974 | ||
975 | platform_set_drvdata(pdev, ssp); | |
976 | ||
977 | /* Enable transmits and set the watermark level to 1 */ | |
978 | __ssp_writel((1 << SIFIVE_SERIAL_TXCTRL_TXCNT_SHIFT) | | |
979 | SIFIVE_SERIAL_TXCTRL_TXEN_MASK, | |
980 | SIFIVE_SERIAL_TXCTRL_OFFS, ssp); | |
981 | ||
982 | /* Enable receives and set the watermark level to 0 */ | |
983 | __ssp_writel((0 << SIFIVE_SERIAL_RXCTRL_RXCNT_SHIFT) | | |
984 | SIFIVE_SERIAL_RXCTRL_RXEN_MASK, | |
985 | SIFIVE_SERIAL_RXCTRL_OFFS, ssp); | |
986 | ||
987 | r = request_irq(ssp->port.irq, sifive_serial_irq, ssp->port.irqflags, | |
988 | dev_name(&pdev->dev), ssp); | |
989 | if (r) { | |
990 | dev_err(&pdev->dev, "could not attach interrupt: %d\n", r); | |
991 | goto probe_out2; | |
992 | } | |
993 | ||
994 | __ssp_add_console_port(ssp); | |
995 | ||
996 | r = uart_add_one_port(&sifive_serial_uart_driver, &ssp->port); | |
997 | if (r != 0) { | |
998 | dev_err(&pdev->dev, "could not add uart: %d\n", r); | |
999 | goto probe_out3; | |
1000 | } | |
1001 | ||
1002 | return 0; | |
1003 | ||
1004 | probe_out3: | |
1005 | __ssp_remove_console_port(ssp); | |
1006 | free_irq(ssp->port.irq, ssp); | |
1007 | probe_out2: | |
1008 | clk_notifier_unregister(ssp->clk, &ssp->clk_notifier); | |
1009 | probe_out1: | |
1010 | return r; | |
1011 | } | |
1012 | ||
1013 | static int sifive_serial_remove(struct platform_device *dev) | |
1014 | { | |
1015 | struct sifive_serial_port *ssp = platform_get_drvdata(dev); | |
1016 | ||
1017 | __ssp_remove_console_port(ssp); | |
1018 | uart_remove_one_port(&sifive_serial_uart_driver, &ssp->port); | |
1019 | free_irq(ssp->port.irq, ssp); | |
1020 | clk_notifier_unregister(ssp->clk, &ssp->clk_notifier); | |
1021 | ||
1022 | return 0; | |
1023 | } | |
1024 | ||
1025 | static const struct of_device_id sifive_serial_of_match[] = { | |
1026 | { .compatible = "sifive,fu540-c000-uart0" }, | |
1027 | { .compatible = "sifive,uart0" }, | |
1028 | {}, | |
1029 | }; | |
1030 | MODULE_DEVICE_TABLE(of, sifive_serial_of_match); | |
1031 | ||
1032 | static struct platform_driver sifive_serial_platform_driver = { | |
1033 | .probe = sifive_serial_probe, | |
1034 | .remove = sifive_serial_remove, | |
1035 | .driver = { | |
1036 | .name = SIFIVE_SERIAL_NAME, | |
1037 | .of_match_table = of_match_ptr(sifive_serial_of_match), | |
1038 | }, | |
1039 | }; | |
1040 | ||
1041 | static int __init sifive_serial_init(void) | |
1042 | { | |
1043 | int r; | |
1044 | ||
1045 | r = uart_register_driver(&sifive_serial_uart_driver); | |
1046 | if (r) | |
1047 | goto init_out1; | |
1048 | ||
1049 | r = platform_driver_register(&sifive_serial_platform_driver); | |
1050 | if (r) | |
1051 | goto init_out2; | |
1052 | ||
1053 | return 0; | |
1054 | ||
1055 | init_out2: | |
1056 | uart_unregister_driver(&sifive_serial_uart_driver); | |
1057 | init_out1: | |
1058 | return r; | |
1059 | } | |
1060 | ||
1061 | static void __exit sifive_serial_exit(void) | |
1062 | { | |
1063 | platform_driver_unregister(&sifive_serial_platform_driver); | |
1064 | uart_unregister_driver(&sifive_serial_uart_driver); | |
1065 | } | |
1066 | ||
1067 | module_init(sifive_serial_init); | |
1068 | module_exit(sifive_serial_exit); | |
1069 | ||
1070 | MODULE_DESCRIPTION("SiFive UART serial driver"); | |
1071 | MODULE_LICENSE("GPL"); | |
1072 | MODULE_AUTHOR("Paul Walmsley <paul@pwsan.com>"); |