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tty: serial: imx: add pinctrl sleep/default mode switch for suspend
[linux-block.git] / drivers / tty / serial / sh-sci.c
CommitLineData
e3b3d0f5 1// SPDX-License-Identifier: GPL-2.0
1da177e4 2/*
1da177e4
LT		 3 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
4 *
f43dc23d 5 * Copyright (C) 2002 - 2011 Paul Mundt
f4998e55 6 * Copyright (C) 2015 Glider bvba
3ea6bc3d 7 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
1da177e4
LT		 8 *
9 * based off of the old drivers/char/sh-sci.c by:
10 *
11 * Copyright (C) 1999, 2000 Niibe Yutaka
12 * Copyright (C) 2000 Sugioka Toshinobu
13 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
14 * Modified to support SecureEdge. David McCullough (2002)
15 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
d89ddd1c 16 * Removed SH7300 support (Jul 2007).
1da177e4 17 */
0b3d4ef6
PM		 18#if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
19#define SUPPORT_SYSRQ
20#endif
1da177e4
LT		 21
22#undef DEBUG
23
8fb9631c
LP		 24#include <linux/clk.h>
25#include <linux/console.h>
26#include <linux/ctype.h>
27#include <linux/cpufreq.h>
28#include <linux/delay.h>
29#include <linux/dmaengine.h>
30#include <linux/dma-mapping.h>
31#include <linux/err.h>
1da177e4 32#include <linux/errno.h>
8fb9631c 33#include <linux/init.h>
1da177e4 34#include <linux/interrupt.h>
1da177e4 35#include <linux/ioport.h>
b96408b4 36#include <linux/ktime.h>
8fb9631c
LP		 37#include <linux/major.h>
38#include <linux/module.h>
1da177e4 39#include <linux/mm.h>
20bdcab8 40#include <linux/of.h>
6e605a01 41#include <linux/of_device.h>
8fb9631c 42#include <linux/platform_device.h>
5e50d2d6 43#include <linux/pm_runtime.h>
73a19e4c 44#include <linux/scatterlist.h>
8fb9631c
LP		 45#include <linux/serial.h>
46#include <linux/serial_sci.h>
47#include <linux/sh_dma.h>
5a0e3ad6 48#include <linux/slab.h>
8fb9631c
LP		 49#include <linux/string.h>
50#include <linux/sysrq.h>
51#include <linux/timer.h>
52#include <linux/tty.h>
53#include <linux/tty_flip.h>
85f094ec
PM		 54
55#ifdef CONFIG_SUPERH
1da177e4
LT		 56#include <asm/sh_bios.h>
57#endif
58
f907c9ea 59#include "serial_mctrl_gpio.h"
1da177e4
LT		 60#include "sh-sci.h"
61
89b5c1ab
LP		 62/* Offsets into the sci_port->irqs array */
63enum {
64 SCIx_ERI_IRQ,
65 SCIx_RXI_IRQ,
66 SCIx_TXI_IRQ,
67 SCIx_BRI_IRQ,
628c534a
CB		 68 SCIx_DRI_IRQ,
69 SCIx_TEI_IRQ,
89b5c1ab
LP		 70 SCIx_NR_IRQS,
71
72 SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */
73};
74
75#define SCIx_IRQ_IS_MUXED(port) \
76 ((port)->irqs[SCIx_ERI_IRQ] == \
77 (port)->irqs[SCIx_RXI_IRQ]) || \
78 ((port)->irqs[SCIx_ERI_IRQ] && \
79 ((port)->irqs[SCIx_RXI_IRQ] < 0))
80
f4998e55
GU		 81enum SCI_CLKS {
82 SCI_FCK, /* Functional Clock */
6af27bf2 83 SCI_SCK, /* Optional External Clock */
1270f865
GU		 84 SCI_BRG_INT, /* Optional BRG Internal Clock Source */
85 SCI_SCIF_CLK, /* Optional BRG External Clock Source */
f4998e55
GU		 86 SCI_NUM_CLKS
87};
88
69eee8e9
GU		 89/* Bit x set means sampling rate x + 1 is supported */
90#define SCI_SR(x) BIT((x) - 1)
91#define SCI_SR_RANGE(x, y) GENMASK((y) - 1, (x) - 1)
92
92a05748
GU		 93#define SCI_SR_SCIFAB SCI_SR(5) | SCI_SR(7) | SCI_SR(11) | \
94 SCI_SR(13) | SCI_SR(16) | SCI_SR(17) | \
95 SCI_SR(19) | SCI_SR(27)
96
69eee8e9
GU		 97#define min_sr(_port) ffs((_port)->sampling_rate_mask)
98#define max_sr(_port) fls((_port)->sampling_rate_mask)
99
100/* Iterate over all supported sampling rates, from high to low */
101#define for_each_sr(_sr, _port) \
102 for ((_sr) = max_sr(_port); (_sr) >= min_sr(_port); (_sr)--) \
103 if ((_port)->sampling_rate_mask & SCI_SR((_sr)))
104
e095ee6b
LP		 105struct plat_sci_reg {
106 u8 offset, size;
107};
108
109struct sci_port_params {
110 const struct plat_sci_reg regs[SCIx_NR_REGS];
b2f20ed9
LP		 111 unsigned int fifosize;
112 unsigned int overrun_reg;
113 unsigned int overrun_mask;
114 unsigned int sampling_rate_mask;
115 unsigned int error_mask;
116 unsigned int error_clear;
e095ee6b
LP		 117};
118
e108b2ca
PM		 119struct sci_port {
120 struct uart_port port;
121
ce6738b6 122 /* Platform configuration */
e095ee6b 123 const struct sci_port_params *params;
daf5a895 124 const struct plat_sci_port *cfg;
69eee8e9 125 unsigned int sampling_rate_mask;
e4d6f911 126 resource_size_t reg_size;
f907c9ea 127 struct mctrl_gpios *gpios;
e108b2ca 128
f4998e55
GU		 129 /* Clocks */
130 struct clk *clks[SCI_NUM_CLKS];
131 unsigned long clk_rates[SCI_NUM_CLKS];
edad1f20 132
1fcc91a6 133 int irqs[SCIx_NR_IRQS];
9174fc8f
PM		 134 char *irqstr[SCIx_NR_IRQS];
135
73a19e4c
GL		 136 struct dma_chan *chan_tx;
137 struct dma_chan *chan_rx;
f43dc23d 138
73a19e4c 139#ifdef CONFIG_SERIAL_SH_SCI_DMA
2c4ee235
GU		 140 struct dma_chan *chan_tx_saved;
141 struct dma_chan *chan_rx_saved;
73a19e4c
GL		 142 dma_cookie_t cookie_tx;
143 dma_cookie_t cookie_rx[2];
144 dma_cookie_t active_rx;
79904420
GU		 145 dma_addr_t tx_dma_addr;
146 unsigned int tx_dma_len;
73a19e4c 147 struct scatterlist sg_rx[2];
7b39d901 148 void *rx_buf[2];
73a19e4c 149 size_t buf_len_rx;
73a19e4c 150 struct work_struct work_tx;
b96408b4
UH		 151 struct hrtimer rx_timer;
152 unsigned int rx_timeout; /* microseconds */
73a19e4c 153#endif
03940376 154 unsigned int rx_frame;
18e8cf15 155 int rx_trigger;
03940376
UH		 156 struct timer_list rx_fifo_timer;
157 int rx_fifo_timeout;
fa2abb03 158 u16 hscif_tot;
33f50ffc 159
97ed9790 160 bool has_rtscts;
33f50ffc 161 bool autorts;
e108b2ca
PM		 162};
163
e108b2ca 164#define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
b7a76e4b 165
e108b2ca 166static struct sci_port sci_ports[SCI_NPORTS];
7678f4c2 167static unsigned long sci_ports_in_use;
e108b2ca 168static struct uart_driver sci_uart_driver;
1da177e4 169
e7c98dc7
MT		 170static inline struct sci_port *
171to_sci_port(struct uart_port *uart)
172{
173 return container_of(uart, struct sci_port, port);
174}
175
e095ee6b 176static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = {
61a6976b
PM		 177 /*
178 * Common SCI definitions, dependent on the port's regshift
179 * value.
180 */
181 [SCIx_SCI_REGTYPE] = {
e095ee6b
LP		 182 .regs = {
183 [SCSMR] = { 0x00, 8 },
184 [SCBRR] = { 0x01, 8 },
185 [SCSCR] = { 0x02, 8 },
186 [SCxTDR] = { 0x03, 8 },
187 [SCxSR] = { 0x04, 8 },
188 [SCxRDR] = { 0x05, 8 },
189 },
b2f20ed9
LP		 190 .fifosize = 1,
191 .overrun_reg = SCxSR,
192 .overrun_mask = SCI_ORER,
193 .sampling_rate_mask = SCI_SR(32),
194 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER,
195 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER,
61a6976b
PM		 196 },
197
198 /*
a752ba18 199 * Common definitions for legacy IrDA ports.
61a6976b
PM		 200 */
201 [SCIx_IRDA_REGTYPE] = {
e095ee6b
LP		 202 .regs = {
203 [SCSMR] = { 0x00, 8 },
204 [SCBRR] = { 0x02, 8 },
205 [SCSCR] = { 0x04, 8 },
206 [SCxTDR] = { 0x06, 8 },
207 [SCxSR] = { 0x08, 16 },
208 [SCxRDR] = { 0x0a, 8 },
209 [SCFCR] = { 0x0c, 8 },
210 [SCFDR] = { 0x0e, 16 },
211 },
b2f20ed9
LP		 212 .fifosize = 1,
213 .overrun_reg = SCxSR,
214 .overrun_mask = SCI_ORER,
215 .sampling_rate_mask = SCI_SR(32),
216 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER,
217 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER,
61a6976b
PM		 218 },
219
220 /*
221 * Common SCIFA definitions.
222 */
223 [SCIx_SCIFA_REGTYPE] = {
e095ee6b
LP		 224 .regs = {
225 [SCSMR] = { 0x00, 16 },
226 [SCBRR] = { 0x04, 8 },
227 [SCSCR] = { 0x08, 16 },
228 [SCxTDR] = { 0x20, 8 },
229 [SCxSR] = { 0x14, 16 },
230 [SCxRDR] = { 0x24, 8 },
231 [SCFCR] = { 0x18, 16 },
232 [SCFDR] = { 0x1c, 16 },
233 [SCPCR] = { 0x30, 16 },
234 [SCPDR] = { 0x34, 16 },
235 },
b2f20ed9
LP		 236 .fifosize = 64,
237 .overrun_reg = SCxSR,
238 .overrun_mask = SCIFA_ORER,
239 .sampling_rate_mask = SCI_SR_SCIFAB,
240 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
241 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
61a6976b
PM		 242 },
243
244 /*
245 * Common SCIFB definitions.
246 */
247 [SCIx_SCIFB_REGTYPE] = {
e095ee6b
LP		 248 .regs = {
249 [SCSMR] = { 0x00, 16 },
250 [SCBRR] = { 0x04, 8 },
251 [SCSCR] = { 0x08, 16 },
252 [SCxTDR] = { 0x40, 8 },
253 [SCxSR] = { 0x14, 16 },
254 [SCxRDR] = { 0x60, 8 },
255 [SCFCR] = { 0x18, 16 },
256 [SCTFDR] = { 0x38, 16 },
257 [SCRFDR] = { 0x3c, 16 },
258 [SCPCR] = { 0x30, 16 },
259 [SCPDR] = { 0x34, 16 },
260 },
b2f20ed9
LP		 261 .fifosize = 256,
262 .overrun_reg = SCxSR,
263 .overrun_mask = SCIFA_ORER,
264 .sampling_rate_mask = SCI_SR_SCIFAB,
265 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
266 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
61a6976b
PM		 267 },
268
3af1f8a4
PE		 269 /*
270 * Common SH-2(A) SCIF definitions for ports with FIFO data
271 * count registers.
272 */
273 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = {
e095ee6b
LP		 274 .regs = {
275 [SCSMR] = { 0x00, 16 },
276 [SCBRR] = { 0x04, 8 },
277 [SCSCR] = { 0x08, 16 },
278 [SCxTDR] = { 0x0c, 8 },
279 [SCxSR] = { 0x10, 16 },
280 [SCxRDR] = { 0x14, 8 },
281 [SCFCR] = { 0x18, 16 },
282 [SCFDR] = { 0x1c, 16 },
283 [SCSPTR] = { 0x20, 16 },
284 [SCLSR] = { 0x24, 16 },
285 },
b2f20ed9
LP		 286 .fifosize = 16,
287 .overrun_reg = SCLSR,
288 .overrun_mask = SCLSR_ORER,
289 .sampling_rate_mask = SCI_SR(32),
290 .error_mask = SCIF_DEFAULT_ERROR_MASK,
291 .error_clear = SCIF_ERROR_CLEAR,
3af1f8a4
PE		 292 },
293
61a6976b
PM		 294 /*
295 * Common SH-3 SCIF definitions.
296 */
297 [SCIx_SH3_SCIF_REGTYPE] = {
e095ee6b
LP		 298 .regs = {
299 [SCSMR] = { 0x00, 8 },
300 [SCBRR] = { 0x02, 8 },
301 [SCSCR] = { 0x04, 8 },
302 [SCxTDR] = { 0x06, 8 },
303 [SCxSR] = { 0x08, 16 },
304 [SCxRDR] = { 0x0a, 8 },
305 [SCFCR] = { 0x0c, 8 },
306 [SCFDR] = { 0x0e, 16 },
307 },
b2f20ed9
LP		 308 .fifosize = 16,
309 .overrun_reg = SCLSR,
310 .overrun_mask = SCLSR_ORER,
311 .sampling_rate_mask = SCI_SR(32),
312 .error_mask = SCIF_DEFAULT_ERROR_MASK,
313 .error_clear = SCIF_ERROR_CLEAR,
61a6976b
PM		 314 },
315
316 /*
317 * Common SH-4(A) SCIF(B) definitions.
318 */
319 [SCIx_SH4_SCIF_REGTYPE] = {
e095ee6b
LP		 320 .regs = {
321 [SCSMR] = { 0x00, 16 },
2d4dd0da
CB		 322 [SCBRR] = { 0x02, 8 },
323 [SCSCR] = { 0x04, 16 },
324 [SCxTDR] = { 0x06, 8 },
325 [SCxSR] = { 0x08, 16 },
326 [SCxRDR] = { 0x0a, 8 },
327 [SCFCR] = { 0x0c, 16 },
328 [SCFDR] = { 0x0e, 16 },
329 [SCSPTR] = { 0x10, 16 },
330 [SCLSR] = { 0x12, 16 },
e095ee6b 331 },
b2f20ed9
LP		 332 .fifosize = 16,
333 .overrun_reg = SCLSR,
334 .overrun_mask = SCLSR_ORER,
335 .sampling_rate_mask = SCI_SR(32),
336 .error_mask = SCIF_DEFAULT_ERROR_MASK,
337 .error_clear = SCIF_ERROR_CLEAR,
b8bbd6b2
GU		 338 },
339
340 /*
341 * Common SCIF definitions for ports with a Baud Rate Generator for
342 * External Clock (BRG).
343 */
344 [SCIx_SH4_SCIF_BRG_REGTYPE] = {
e095ee6b
LP		 345 .regs = {
346 [SCSMR] = { 0x00, 16 },
347 [SCBRR] = { 0x04, 8 },
348 [SCSCR] = { 0x08, 16 },
349 [SCxTDR] = { 0x0c, 8 },
350 [SCxSR] = { 0x10, 16 },
351 [SCxRDR] = { 0x14, 8 },
352 [SCFCR] = { 0x18, 16 },
353 [SCFDR] = { 0x1c, 16 },
354 [SCSPTR] = { 0x20, 16 },
355 [SCLSR] = { 0x24, 16 },
356 [SCDL] = { 0x30, 16 },
357 [SCCKS] = { 0x34, 16 },
358 },
b2f20ed9
LP		 359 .fifosize = 16,
360 .overrun_reg = SCLSR,
361 .overrun_mask = SCLSR_ORER,
362 .sampling_rate_mask = SCI_SR(32),
363 .error_mask = SCIF_DEFAULT_ERROR_MASK,
364 .error_clear = SCIF_ERROR_CLEAR,
f303b364
UH		 365 },
366
367 /*
368 * Common HSCIF definitions.
369 */
370 [SCIx_HSCIF_REGTYPE] = {
e095ee6b
LP		 371 .regs = {
372 [SCSMR] = { 0x00, 16 },
373 [SCBRR] = { 0x04, 8 },
374 [SCSCR] = { 0x08, 16 },
375 [SCxTDR] = { 0x0c, 8 },
376 [SCxSR] = { 0x10, 16 },
377 [SCxRDR] = { 0x14, 8 },
378 [SCFCR] = { 0x18, 16 },
379 [SCFDR] = { 0x1c, 16 },
380 [SCSPTR] = { 0x20, 16 },
381 [SCLSR] = { 0x24, 16 },
382 [HSSRR] = { 0x40, 16 },
383 [SCDL] = { 0x30, 16 },
384 [SCCKS] = { 0x34, 16 },
54e14ae2
UH		 385 [HSRTRGR] = { 0x54, 16 },
386 [HSTTRGR] = { 0x58, 16 },
e095ee6b 387 },
b2f20ed9
LP		 388 .fifosize = 128,
389 .overrun_reg = SCLSR,
390 .overrun_mask = SCLSR_ORER,
391 .sampling_rate_mask = SCI_SR_RANGE(8, 32),
392 .error_mask = SCIF_DEFAULT_ERROR_MASK,
393 .error_clear = SCIF_ERROR_CLEAR,
61a6976b
PM		 394 },
395
396 /*
397 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR
398 * register.
399 */
400 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = {
e095ee6b
LP		 401 .regs = {
402 [SCSMR] = { 0x00, 16 },
403 [SCBRR] = { 0x04, 8 },
404 [SCSCR] = { 0x08, 16 },
405 [SCxTDR] = { 0x0c, 8 },
406 [SCxSR] = { 0x10, 16 },
407 [SCxRDR] = { 0x14, 8 },
408 [SCFCR] = { 0x18, 16 },
409 [SCFDR] = { 0x1c, 16 },
410 [SCLSR] = { 0x24, 16 },
411 },
b2f20ed9
LP		 412 .fifosize = 16,
413 .overrun_reg = SCLSR,
414 .overrun_mask = SCLSR_ORER,
415 .sampling_rate_mask = SCI_SR(32),
416 .error_mask = SCIF_DEFAULT_ERROR_MASK,
417 .error_clear = SCIF_ERROR_CLEAR,
61a6976b
PM		 418 },
419
420 /*
421 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data
422 * count registers.
423 */
424 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = {
e095ee6b
LP		 425 .regs = {
426 [SCSMR] = { 0x00, 16 },
427 [SCBRR] = { 0x04, 8 },
428 [SCSCR] = { 0x08, 16 },
429 [SCxTDR] = { 0x0c, 8 },
430 [SCxSR] = { 0x10, 16 },
431 [SCxRDR] = { 0x14, 8 },
432 [SCFCR] = { 0x18, 16 },
433 [SCFDR] = { 0x1c, 16 },
434 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */
435 [SCRFDR] = { 0x20, 16 },
436 [SCSPTR] = { 0x24, 16 },
437 [SCLSR] = { 0x28, 16 },
438 },
b2f20ed9
LP		 439 .fifosize = 16,
440 .overrun_reg = SCLSR,
441 .overrun_mask = SCLSR_ORER,
442 .sampling_rate_mask = SCI_SR(32),
443 .error_mask = SCIF_DEFAULT_ERROR_MASK,
444 .error_clear = SCIF_ERROR_CLEAR,
61a6976b
PM		 445 },
446
447 /*
448 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR
449 * registers.
450 */
451 [SCIx_SH7705_SCIF_REGTYPE] = {
e095ee6b
LP		 452 .regs = {
453 [SCSMR] = { 0x00, 16 },
454 [SCBRR] = { 0x04, 8 },
455 [SCSCR] = { 0x08, 16 },
456 [SCxTDR] = { 0x20, 8 },
457 [SCxSR] = { 0x14, 16 },
458 [SCxRDR] = { 0x24, 8 },
459 [SCFCR] = { 0x18, 16 },
460 [SCFDR] = { 0x1c, 16 },
461 },
18e8cf15 462 .fifosize = 64,
b2f20ed9
LP		 463 .overrun_reg = SCxSR,
464 .overrun_mask = SCIFA_ORER,
465 .sampling_rate_mask = SCI_SR(16),
466 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
467 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
61a6976b
PM		 468 },
469};
470
e095ee6b 471#define sci_getreg(up, offset) (&to_sci_port(up)->params->regs[offset])
72b294cf 472
61a6976b
PM		 473/*
474 * The "offset" here is rather misleading, in that it refers to an enum
475 * value relative to the port mapping rather than the fixed offset
476 * itself, which needs to be manually retrieved from the platform's
477 * register map for the given port.
478 */
479static unsigned int sci_serial_in(struct uart_port *p, int offset)
480{
d3184e68 481 const struct plat_sci_reg *reg = sci_getreg(p, offset);
61a6976b
PM		 482
483 if (reg->size == 8)
484 return ioread8(p->membase + (reg->offset << p->regshift));
485 else if (reg->size == 16)
486 return ioread16(p->membase + (reg->offset << p->regshift));
487 else
488 WARN(1, "Invalid register access\n");
489
490 return 0;
491}
492
493static void sci_serial_out(struct uart_port *p, int offset, int value)
494{
d3184e68 495 const struct plat_sci_reg *reg = sci_getreg(p, offset);
61a6976b
PM		 496
497 if (reg->size == 8)
498 iowrite8(value, p->membase + (reg->offset << p->regshift));
499 else if (reg->size == 16)
500 iowrite16(value, p->membase + (reg->offset << p->regshift));
501 else
502 WARN(1, "Invalid register access\n");
503}
504
23241d43
PM		 505static void sci_port_enable(struct sci_port *sci_port)
506{
f4998e55
GU		 507 unsigned int i;
508
23241d43
PM		 509 if (!sci_port->port.dev)
510 return;
511
512 pm_runtime_get_sync(sci_port->port.dev);
513
f4998e55
GU		 514 for (i = 0; i < SCI_NUM_CLKS; i++) {
515 clk_prepare_enable(sci_port->clks[i]);
516 sci_port->clk_rates[i] = clk_get_rate(sci_port->clks[i]);
517 }
518 sci_port->port.uartclk = sci_port->clk_rates[SCI_FCK];
23241d43
PM		 519}
520
521static void sci_port_disable(struct sci_port *sci_port)
522{
f4998e55
GU		 523 unsigned int i;
524
23241d43
PM		 525 if (!sci_port->port.dev)
526 return;
527
f4998e55
GU		 528 for (i = SCI_NUM_CLKS; i-- > 0; )
529 clk_disable_unprepare(sci_port->clks[i]);
23241d43
PM		 530
531 pm_runtime_put_sync(sci_port->port.dev);
532}
533
e1910fcd
GU		 534static inline unsigned long port_rx_irq_mask(struct uart_port *port)
535{
536 /*
537 * Not all ports (such as SCIFA) will support REIE. Rather than
538 * special-casing the port type, we check the port initialization
539 * IRQ enable mask to see whether the IRQ is desired at all. If
540 * it's unset, it's logically inferred that there's no point in
541 * testing for it.
542 */
543 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE);
544}
545
546static void sci_start_tx(struct uart_port *port)
547{
548 struct sci_port *s = to_sci_port(port);
549 unsigned short ctrl;
550
551#ifdef CONFIG_SERIAL_SH_SCI_DMA
552 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
553 u16 new, scr = serial_port_in(port, SCSCR);
554 if (s->chan_tx)
555 new = scr | SCSCR_TDRQE;
556 else
557 new = scr & ~SCSCR_TDRQE;
558 if (new != scr)
559 serial_port_out(port, SCSCR, new);
560 }
561
562 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) &&
563 dma_submit_error(s->cookie_tx)) {
564 s->cookie_tx = 0;
565 schedule_work(&s->work_tx);
566 }
567#endif
568
569 if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
570 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
571 ctrl = serial_port_in(port, SCSCR);
572 serial_port_out(port, SCSCR, ctrl | SCSCR_TIE);
573 }
574}
575
576static void sci_stop_tx(struct uart_port *port)
577{
578 unsigned short ctrl;
579
580 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
581 ctrl = serial_port_in(port, SCSCR);
582
583 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
584 ctrl &= ~SCSCR_TDRQE;
585
586 ctrl &= ~SCSCR_TIE;
587
588 serial_port_out(port, SCSCR, ctrl);
589}
590
591static void sci_start_rx(struct uart_port *port)
592{
593 unsigned short ctrl;
594
595 ctrl = serial_port_in(port, SCSCR) | port_rx_irq_mask(port);
596
597 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
598 ctrl &= ~SCSCR_RDRQE;
599
600 serial_port_out(port, SCSCR, ctrl);
601}
602
603static void sci_stop_rx(struct uart_port *port)
604{
605 unsigned short ctrl;
606
607 ctrl = serial_port_in(port, SCSCR);
608
609 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
610 ctrl &= ~SCSCR_RDRQE;
611
612 ctrl &= ~port_rx_irq_mask(port);
613
614 serial_port_out(port, SCSCR, ctrl);
615}
616
a1b5b43f
GU		 617static void sci_clear_SCxSR(struct uart_port *port, unsigned int mask)
618{
619 if (port->type == PORT_SCI) {
620 /* Just store the mask */
621 serial_port_out(port, SCxSR, mask);
b2f20ed9 622 } else if (to_sci_port(port)->params->overrun_mask == SCIFA_ORER) {
a1b5b43f
GU		 623 /* SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721 */
624 /* Only clear the status bits we want to clear */
625 serial_port_out(port, SCxSR,
626 serial_port_in(port, SCxSR) & mask);
627 } else {
628 /* Store the mask, clear parity/framing errors */
629 serial_port_out(port, SCxSR, mask & ~(SCIF_FERC | SCIF_PERC));
630 }
631}
632
0b0cced1
YS		 633#if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \
634 defined(CONFIG_SERIAL_SH_SCI_EARLYCON)
1f6fd5c9
PM		 635
636#ifdef CONFIG_CONSOLE_POLL
07d2a1a1 637static int sci_poll_get_char(struct uart_port *port)
1da177e4 638{
1da177e4
LT		 639 unsigned short status;
640 int c;
641
e108b2ca 642 do {
b12bb29f 643 status = serial_port_in(port, SCxSR);
1da177e4 644 if (status & SCxSR_ERRORS(port)) {
a1b5b43f 645 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
1da177e4
LT		 646 continue;
647 }
3f255eb3
JW		 648 break;
649 } while (1);
650
651 if (!(status & SCxSR_RDxF(port)))
652 return NO_POLL_CHAR;
07d2a1a1 653
b12bb29f 654 c = serial_port_in(port, SCxRDR);
07d2a1a1 655
e7c98dc7 656 /* Dummy read */
b12bb29f 657 serial_port_in(port, SCxSR);
a1b5b43f 658 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1da177e4
LT		 659
660 return c;
661}
1f6fd5c9 662#endif
1da177e4 663
07d2a1a1 664static void sci_poll_put_char(struct uart_port *port, unsigned char c)
1da177e4 665{
1da177e4
LT		 666 unsigned short status;
667
1da177e4 668 do {
b12bb29f 669 status = serial_port_in(port, SCxSR);
1da177e4
LT		 670 } while (!(status & SCxSR_TDxE(port)));
671
b12bb29f 672 serial_port_out(port, SCxTDR, c);
a1b5b43f 673 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
1da177e4 674}
0b0cced1
YS		 675#endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE ||
676 CONFIG_SERIAL_SH_SCI_EARLYCON */
1da177e4 677
61a6976b 678static void sci_init_pins(struct uart_port *port, unsigned int cflag)
1da177e4 679{
61a6976b 680 struct sci_port *s = to_sci_port(port);
1da177e4 681
61a6976b
PM		 682 /*
683 * Use port-specific handler if provided.
684 */
685 if (s->cfg->ops && s->cfg->ops->init_pins) {
686 s->cfg->ops->init_pins(port, cflag);
687 return;
1da177e4 688 }
41504c39 689
e9d7a45a 690 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
cfa6eb23 691 u16 data = serial_port_in(port, SCPDR);
e9d7a45a
GU		 692 u16 ctrl = serial_port_in(port, SCPCR);
693
694 /* Enable RXD and TXD pin functions */
695 ctrl &= ~(SCPCR_RXDC | SCPCR_TXDC);
97ed9790 696 if (to_sci_port(port)->has_rtscts) {
cfa6eb23
GU		 697 /* RTS# is output, active low, unless autorts */
698 if (!(port->mctrl & TIOCM_RTS)) {
699 ctrl |= SCPCR_RTSC;
700 data |= SCPDR_RTSD;
701 } else if (!s->autorts) {
702 ctrl |= SCPCR_RTSC;
703 data &= ~SCPDR_RTSD;
704 } else {
705 /* Enable RTS# pin function */
706 ctrl &= ~SCPCR_RTSC;
707 }
e9d7a45a
GU		 708 /* Enable CTS# pin function */
709 ctrl &= ~SCPCR_CTSC;
710 }
cfa6eb23 711 serial_port_out(port, SCPDR, data);
e9d7a45a
GU		 712 serial_port_out(port, SCPCR, ctrl);
713 } else if (sci_getreg(port, SCSPTR)->size) {
d2b9775d
GU		 714 u16 status = serial_port_in(port, SCSPTR);
715
cfa6eb23
GU		 716 /* RTS# is always output; and active low, unless autorts */
717 status |= SCSPTR_RTSIO;
718 if (!(port->mctrl & TIOCM_RTS))
719 status |= SCSPTR_RTSDT;
720 else if (!s->autorts)
721 status &= ~SCSPTR_RTSDT;
d2b9775d
GU		 722 /* CTS# and SCK are inputs */
723 status &= ~(SCSPTR_CTSIO | SCSPTR_SCKIO);
724 serial_port_out(port, SCSPTR, status);
faf02f8f 725 }
d5701647 726}
e108b2ca 727
72b294cf 728static int sci_txfill(struct uart_port *port)
e108b2ca 729{
b2f20ed9
LP		 730 struct sci_port *s = to_sci_port(port);
731 unsigned int fifo_mask = (s->params->fifosize << 1) - 1;
d3184e68 732 const struct plat_sci_reg *reg;
e108b2ca 733
72b294cf
PM		 734 reg = sci_getreg(port, SCTFDR);
735 if (reg->size)
b2f20ed9 736 return serial_port_in(port, SCTFDR) & fifo_mask;
c63847a3 737
72b294cf
PM		 738 reg = sci_getreg(port, SCFDR);
739 if (reg->size)
b12bb29f 740 return serial_port_in(port, SCFDR) >> 8;
d1d4b10c 741
b12bb29f 742 return !(serial_port_in(port, SCxSR) & SCI_TDRE);
e108b2ca
PM		 743}
744
73a19e4c
GL		 745static int sci_txroom(struct uart_port *port)
746{
72b294cf 747 return port->fifosize - sci_txfill(port);
73a19e4c
GL		 748}
749
750static int sci_rxfill(struct uart_port *port)
e108b2ca 751{
b2f20ed9
LP		 752 struct sci_port *s = to_sci_port(port);
753 unsigned int fifo_mask = (s->params->fifosize << 1) - 1;
d3184e68 754 const struct plat_sci_reg *reg;
72b294cf
PM		 755
756 reg = sci_getreg(port, SCRFDR);
757 if (reg->size)
b2f20ed9 758 return serial_port_in(port, SCRFDR) & fifo_mask;
72b294cf
PM		 759
760 reg = sci_getreg(port, SCFDR);
761 if (reg->size)
b2f20ed9 762 return serial_port_in(port, SCFDR) & fifo_mask;
72b294cf 763
b12bb29f 764 return (serial_port_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
e108b2ca
PM		 765}
766
1da177e4
LT		 767/* ********************************************************************** *
768 * the interrupt related routines *
769 * ********************************************************************** */
770
771static void sci_transmit_chars(struct uart_port *port)
772{
ebd2c8f6 773 struct circ_buf *xmit = &port->state->xmit;
1da177e4 774 unsigned int stopped = uart_tx_stopped(port);
1da177e4
LT		 775 unsigned short status;
776 unsigned short ctrl;
e108b2ca 777 int count;
1da177e4 778
b12bb29f 779 status = serial_port_in(port, SCxSR);
1da177e4 780 if (!(status & SCxSR_TDxE(port))) {
b12bb29f 781 ctrl = serial_port_in(port, SCSCR);
e7c98dc7 782 if (uart_circ_empty(xmit))
8e698614 783 ctrl &= ~SCSCR_TIE;
e7c98dc7 784 else
8e698614 785 ctrl |= SCSCR_TIE;
b12bb29f 786 serial_port_out(port, SCSCR, ctrl);
1da177e4
LT		 787 return;
788 }
789
72b294cf 790 count = sci_txroom(port);
1da177e4
LT		 791
792 do {
793 unsigned char c;
794
795 if (port->x_char) {
796 c = port->x_char;
797 port->x_char = 0;
798 } else if (!uart_circ_empty(xmit) && !stopped) {
799 c = xmit->buf[xmit->tail];
800 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
801 } else {
802 break;
803 }
804
b12bb29f 805 serial_port_out(port, SCxTDR, c);
1da177e4
LT		 806
807 port->icount.tx++;
808 } while (--count > 0);
809
a1b5b43f 810 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
1da177e4
LT		 811
812 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
813 uart_write_wakeup(port);
814 if (uart_circ_empty(xmit)) {
b129a8cc 815 sci_stop_tx(port);
1da177e4 816 } else {
b12bb29f 817 ctrl = serial_port_in(port, SCSCR);
1da177e4 818
1a22f08d 819 if (port->type != PORT_SCI) {
b12bb29f 820 serial_port_in(port, SCxSR); /* Dummy read */
a1b5b43f 821 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
1da177e4 822 }
1da177e4 823
8e698614 824 ctrl |= SCSCR_TIE;
b12bb29f 825 serial_port_out(port, SCSCR, ctrl);
1da177e4
LT		 826 }
827}
828
829/* On SH3, SCIF may read end-of-break as a space->mark char */
e7c98dc7 830#define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); })
1da177e4 831
94c8b6db 832static void sci_receive_chars(struct uart_port *port)
1da177e4 833{
227434f8 834 struct tty_port *tport = &port->state->port;
1da177e4
LT		 835 int i, count, copied = 0;
836 unsigned short status;
33f0f88f 837 unsigned char flag;
1da177e4 838
b12bb29f 839 status = serial_port_in(port, SCxSR);
1da177e4
LT		 840 if (!(status & SCxSR_RDxF(port)))
841 return;
842
843 while (1) {
1da177e4 844 /* Don't copy more bytes than there is room for in the buffer */
227434f8 845 count = tty_buffer_request_room(tport, sci_rxfill(port));
1da177e4
LT		 846
847 /* If for any reason we can't copy more data, we're done! */
848 if (count == 0)
849 break;
850
851 if (port->type == PORT_SCI) {
b12bb29f 852 char c = serial_port_in(port, SCxRDR);
d5cb1319 853 if (uart_handle_sysrq_char(port, c))
1da177e4 854 count = 0;
e7c98dc7 855 else
92a19f9c 856 tty_insert_flip_char(tport, c, TTY_NORMAL);
1da177e4 857 } else {
e7c98dc7 858 for (i = 0; i < count; i++) {
b12bb29f 859 char c = serial_port_in(port, SCxRDR);
d97fbbed 860
b12bb29f 861 status = serial_port_in(port, SCxSR);
7d12e780 862 if (uart_handle_sysrq_char(port, c)) {
1da177e4
LT		 863 count--; i--;
864 continue;
865 }
866
867 /* Store data and status */
73a19e4c 868 if (status & SCxSR_FER(port)) {
33f0f88f 869 flag = TTY_FRAME;
d97fbbed 870 port->icount.frame++;
762c69e3 871 dev_notice(port->dev, "frame error\n");
73a19e4c 872 } else if (status & SCxSR_PER(port)) {
33f0f88f 873 flag = TTY_PARITY;
d97fbbed 874 port->icount.parity++;
762c69e3 875 dev_notice(port->dev, "parity error\n");
33f0f88f
AC		 876 } else
877 flag = TTY_NORMAL;
762c69e3 878
92a19f9c 879 tty_insert_flip_char(tport, c, flag);
1da177e4
LT		 880 }
881 }
882
b12bb29f 883 serial_port_in(port, SCxSR); /* dummy read */
a1b5b43f 884 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1da177e4 885
1da177e4
LT		 886 copied += count;
887 port->icount.rx += count;
888 }
889
890 if (copied) {
891 /* Tell the rest of the system the news. New characters! */
2e124b4a 892 tty_flip_buffer_push(tport);
1da177e4 893 } else {
7842055b
UH		 894 /* TTY buffers full; read from RX reg to prevent lockup */
895 serial_port_in(port, SCxRDR);
b12bb29f 896 serial_port_in(port, SCxSR); /* dummy read */
a1b5b43f 897 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1da177e4
LT		 898 }
899}
900
94c8b6db 901static int sci_handle_errors(struct uart_port *port)
1da177e4
LT		 902{
903 int copied = 0;
b12bb29f 904 unsigned short status = serial_port_in(port, SCxSR);
92a19f9c 905 struct tty_port *tport = &port->state->port;
debf9507 906 struct sci_port *s = to_sci_port(port);
1da177e4 907
3ae988d9 908 /* Handle overruns */
b2f20ed9 909 if (status & s->params->overrun_mask) {
3ae988d9 910 port->icount.overrun++;
d97fbbed 911
3ae988d9
LP		 912 /* overrun error */
913 if (tty_insert_flip_char(tport, 0, TTY_OVERRUN))
914 copied++;
762c69e3 915
9b971cd2 916 dev_notice(port->dev, "overrun error\n");
1da177e4
LT		 917 }
918
e108b2ca 919 if (status & SCxSR_FER(port)) {
d5cb1319
LP		 920 /* frame error */
921 port->icount.frame++;
d97fbbed 922
d5cb1319
LP		 923 if (tty_insert_flip_char(tport, 0, TTY_FRAME))
924 copied++;
762c69e3 925
d5cb1319 926 dev_notice(port->dev, "frame error\n");
1da177e4
LT		 927 }
928
e108b2ca 929 if (status & SCxSR_PER(port)) {
1da177e4 930 /* parity error */
d97fbbed
PM		 931 port->icount.parity++;
932
92a19f9c 933 if (tty_insert_flip_char(tport, 0, TTY_PARITY))
e108b2ca 934 copied++;
762c69e3 935
9b971cd2 936 dev_notice(port->dev, "parity error\n");
1da177e4
LT		 937 }
938
33f0f88f 939 if (copied)
2e124b4a 940 tty_flip_buffer_push(tport);
1da177e4
LT		 941
942 return copied;
943}
944
94c8b6db 945static int sci_handle_fifo_overrun(struct uart_port *port)
d830fa45 946{
92a19f9c 947 struct tty_port *tport = &port->state->port;
debf9507 948 struct sci_port *s = to_sci_port(port);
d3184e68 949 const struct plat_sci_reg *reg;
2e0842a1 950 int copied = 0;
75c249fd 951 u16 status;
d830fa45 952
b2f20ed9 953 reg = sci_getreg(port, s->params->overrun_reg);
4b8c59a3 954 if (!reg->size)
d830fa45
PM		 955 return 0;
956
b2f20ed9
LP		 957 status = serial_port_in(port, s->params->overrun_reg);
958 if (status & s->params->overrun_mask) {
959 status &= ~s->params->overrun_mask;
960 serial_port_out(port, s->params->overrun_reg, status);
d830fa45 961
d97fbbed
PM		 962 port->icount.overrun++;
963
92a19f9c 964 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
2e124b4a 965 tty_flip_buffer_push(tport);
d830fa45 966
51b31f1c 967 dev_dbg(port->dev, "overrun error\n");
d830fa45
PM		 968 copied++;
969 }
970
971 return copied;
972}
973
94c8b6db 974static int sci_handle_breaks(struct uart_port *port)
1da177e4
LT		 975{
976 int copied = 0;
b12bb29f 977 unsigned short status = serial_port_in(port, SCxSR);
92a19f9c 978 struct tty_port *tport = &port->state->port;
1da177e4 979
0b3d4ef6
PM		 980 if (uart_handle_break(port))
981 return 0;
982
d5cb1319 983 if (status & SCxSR_BRK(port)) {
d97fbbed
PM		 984 port->icount.brk++;
985
1da177e4 986 /* Notify of BREAK */
92a19f9c 987 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
33f0f88f 988 copied++;
762c69e3
PM		 989
990 dev_dbg(port->dev, "BREAK detected\n");
1da177e4
LT		 991 }
992
33f0f88f 993 if (copied)
2e124b4a 994 tty_flip_buffer_push(tport);
e108b2ca 995
d830fa45
PM		 996 copied += sci_handle_fifo_overrun(port);
997
1da177e4
LT		 998 return copied;
999}
1000
a380ed46
UH		 1001static int scif_set_rtrg(struct uart_port *port, int rx_trig)
1002{
1003 unsigned int bits;
1004
1005 if (rx_trig < 1)
1006 rx_trig = 1;
1007 if (rx_trig >= port->fifosize)
1008 rx_trig = port->fifosize;
1009
1010 /* HSCIF can be set to an arbitrary level. */
1011 if (sci_getreg(port, HSRTRGR)->size) {
1012 serial_port_out(port, HSRTRGR, rx_trig);
1013 return rx_trig;
1014 }
1015
1016 switch (port->type) {
1017 case PORT_SCIF:
1018 if (rx_trig < 4) {
1019 bits = 0;
1020 rx_trig = 1;
1021 } else if (rx_trig < 8) {
1022 bits = SCFCR_RTRG0;
1023 rx_trig = 4;
1024 } else if (rx_trig < 14) {
1025 bits = SCFCR_RTRG1;
1026 rx_trig = 8;
1027 } else {
1028 bits = SCFCR_RTRG0 | SCFCR_RTRG1;
1029 rx_trig = 14;
1030 }
1031 break;
1032 case PORT_SCIFA:
1033 case PORT_SCIFB:
1034 if (rx_trig < 16) {
1035 bits = 0;
1036 rx_trig = 1;
1037 } else if (rx_trig < 32) {
1038 bits = SCFCR_RTRG0;
1039 rx_trig = 16;
1040 } else if (rx_trig < 48) {
1041 bits = SCFCR_RTRG1;
1042 rx_trig = 32;
1043 } else {
1044 bits = SCFCR_RTRG0 | SCFCR_RTRG1;
1045 rx_trig = 48;
1046 }
1047 break;
1048 default:
1049 WARN(1, "unknown FIFO configuration");
1050 return 1;
1051 }
1052
1053 serial_port_out(port, SCFCR,
1054 (serial_port_in(port, SCFCR) &
1055 ~(SCFCR_RTRG1 | SCFCR_RTRG0)) | bits);
1056
1057 return rx_trig;
1058}
1059
03940376
UH		 1060static int scif_rtrg_enabled(struct uart_port *port)
1061{
1062 if (sci_getreg(port, HSRTRGR)->size)
1063 return serial_port_in(port, HSRTRGR) != 0;
1064 else
1065 return (serial_port_in(port, SCFCR) &
1066 (SCFCR_RTRG0 | SCFCR_RTRG1)) != 0;
1067}
1068
e99e88a9 1069static void rx_fifo_timer_fn(struct timer_list *t)
03940376 1070{
e99e88a9 1071 struct sci_port *s = from_timer(s, t, rx_fifo_timer);
03940376
UH		 1072 struct uart_port *port = &s->port;
1073
1074 dev_dbg(port->dev, "Rx timed out\n");
1075 scif_set_rtrg(port, 1);
1076}
1077
5d23188a
UH		 1078static ssize_t rx_trigger_show(struct device *dev,
1079 struct device_attribute *attr,
1080 char *buf)
1081{
1082 struct uart_port *port = dev_get_drvdata(dev);
1083 struct sci_port *sci = to_sci_port(port);
1084
1085 return sprintf(buf, "%d\n", sci->rx_trigger);
1086}
1087
1088static ssize_t rx_trigger_store(struct device *dev,
1089 struct device_attribute *attr,
1090 const char *buf,
1091 size_t count)
1092{
1093 struct uart_port *port = dev_get_drvdata(dev);
1094 struct sci_port *sci = to_sci_port(port);
4ab3c51e 1095 int ret;
5d23188a
UH		 1096 long r;
1097
4ab3c51e
DC		 1098 ret = kstrtol(buf, 0, &r);
1099 if (ret)
1100 return ret;
90afa525 1101
5d23188a 1102 sci->rx_trigger = scif_set_rtrg(port, r);
90afa525
UH		 1103 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1104 scif_set_rtrg(port, 1);
1105
5d23188a
UH		 1106 return count;
1107}
1108
1109static DEVICE_ATTR(rx_fifo_trigger, 0644, rx_trigger_show, rx_trigger_store);
1110
1111static ssize_t rx_fifo_timeout_show(struct device *dev,
1112 struct device_attribute *attr,
1113 char *buf)
1114{
1115 struct uart_port *port = dev_get_drvdata(dev);
1116 struct sci_port *sci = to_sci_port(port);
fa2abb03 1117 int v;
5d23188a 1118
fa2abb03
UH		 1119 if (port->type == PORT_HSCIF)
1120 v = sci->hscif_tot >> HSSCR_TOT_SHIFT;
1121 else
1122 v = sci->rx_fifo_timeout;
1123
1124 return sprintf(buf, "%d\n", v);
5d23188a
UH		 1125}
1126
1127static ssize_t rx_fifo_timeout_store(struct device *dev,
1128 struct device_attribute *attr,
1129 const char *buf,
1130 size_t count)
1131{
1132 struct uart_port *port = dev_get_drvdata(dev);
1133 struct sci_port *sci = to_sci_port(port);
4ab3c51e 1134 int ret;
5d23188a
UH		 1135 long r;
1136
4ab3c51e
DC		 1137 ret = kstrtol(buf, 0, &r);
1138 if (ret)
1139 return ret;
fa2abb03
UH		 1140
1141 if (port->type == PORT_HSCIF) {
1142 if (r < 0 || r > 3)
1143 return -EINVAL;
1144 sci->hscif_tot = r << HSSCR_TOT_SHIFT;
1145 } else {
1146 sci->rx_fifo_timeout = r;
1147 scif_set_rtrg(port, 1);
1148 if (r > 0)
e99e88a9 1149 timer_setup(&sci->rx_fifo_timer, rx_fifo_timer_fn, 0);
fa2abb03
UH		 1150 }
1151
5d23188a
UH		 1152 return count;
1153}
1154
b6b996b6 1155static DEVICE_ATTR_RW(rx_fifo_timeout);
5d23188a
UH		 1156
1157
73a19e4c 1158#ifdef CONFIG_SERIAL_SH_SCI_DMA
e1910fcd
GU		 1159static void sci_dma_tx_complete(void *arg)
1160{
1161 struct sci_port *s = arg;
1162 struct uart_port *port = &s->port;
1163 struct circ_buf *xmit = &port->state->xmit;
1164 unsigned long flags;
73a19e4c 1165
e1910fcd 1166 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
73a19e4c 1167
e1910fcd 1168 spin_lock_irqsave(&port->lock, flags);
73a19e4c 1169
e1910fcd
GU		 1170 xmit->tail += s->tx_dma_len;
1171 xmit->tail &= UART_XMIT_SIZE - 1;
73a19e4c 1172
e1910fcd 1173 port->icount.tx += s->tx_dma_len;
1da177e4 1174
e1910fcd
GU		 1175 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1176 uart_write_wakeup(port);
1da177e4 1177
e1910fcd
GU		 1178 if (!uart_circ_empty(xmit)) {
1179 s->cookie_tx = 0;
1180 schedule_work(&s->work_tx);
1181 } else {
1182 s->cookie_tx = -EINVAL;
1183 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1184 u16 ctrl = serial_port_in(port, SCSCR);
1185 serial_port_out(port, SCSCR, ctrl & ~SCSCR_TIE);
1186 }
1187 }
1da177e4 1188
fd78a76a 1189 spin_unlock_irqrestore(&port->lock, flags);
1da177e4
LT		 1190}
1191
e1910fcd
GU		 1192/* Locking: called with port lock held */
1193static int sci_dma_rx_push(struct sci_port *s, void *buf, size_t count)
1da177e4 1194{
e1910fcd
GU		 1195 struct uart_port *port = &s->port;
1196 struct tty_port *tport = &port->state->port;
1197 int copied;
1da177e4 1198
e1910fcd 1199 copied = tty_insert_flip_string(tport, buf, count);
6fc5a520 1200 if (copied < count)
e1910fcd 1201 port->icount.buf_overrun++;
1da177e4 1202
e1910fcd 1203 port->icount.rx += copied;
1da177e4 1204
e1910fcd 1205 return copied;
1da177e4
LT		 1206}
1207
e1910fcd 1208static int sci_dma_rx_find_active(struct sci_port *s)
1da177e4 1209{
e1910fcd 1210 unsigned int i;
1da177e4 1211
e1910fcd
GU		 1212 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++)
1213 if (s->active_rx == s->cookie_rx[i])
1214 return i;
1da177e4 1215
e1910fcd 1216 return -1;
1da177e4
LT		 1217}
1218
2c4ee235 1219static void sci_rx_dma_release(struct sci_port *s)
f43dc23d 1220{
2c4ee235 1221 struct dma_chan *chan = s->chan_rx_saved;
e1910fcd 1222
2c4ee235 1223 s->chan_rx_saved = s->chan_rx = NULL;
e1910fcd 1224 s->cookie_rx[0] = s->cookie_rx[1] = -EINVAL;
6eefc68d 1225 dmaengine_terminate_sync(chan);
e1910fcd
GU		 1226 dma_free_coherent(chan->device->dev, s->buf_len_rx * 2, s->rx_buf[0],
1227 sg_dma_address(&s->sg_rx[0]));
1228 dma_release_channel(chan);
f43dc23d
PM		 1229}
1230
b96408b4
UH		 1231static void start_hrtimer_us(struct hrtimer *hrt, unsigned long usec)
1232{
1233 long sec = usec / 1000000;
1234 long nsec = (usec % 1000000) * 1000;
1235 ktime_t t = ktime_set(sec, nsec);
1236
1237 hrtimer_start(hrt, t, HRTIMER_MODE_REL);
1238}
1239
e1910fcd 1240static void sci_dma_rx_complete(void *arg)
1da177e4 1241{
e1910fcd 1242 struct sci_port *s = arg;
1d3db608 1243 struct dma_chan *chan = s->chan_rx;
e1910fcd 1244 struct uart_port *port = &s->port;
67f462b0 1245 struct dma_async_tx_descriptor *desc;
e1910fcd
GU		 1246 unsigned long flags;
1247 int active, count = 0;
1da177e4 1248
e1910fcd
GU		 1249 dev_dbg(port->dev, "%s(%d) active cookie %d\n", __func__, port->line,
1250 s->active_rx);
cb772fe7 1251
e1910fcd 1252 spin_lock_irqsave(&port->lock, flags);
1da177e4 1253
e1910fcd
GU		 1254 active = sci_dma_rx_find_active(s);
1255 if (active >= 0)
1256 count = sci_dma_rx_push(s, s->rx_buf[active], s->buf_len_rx);
f43dc23d 1257
b96408b4 1258 start_hrtimer_us(&s->rx_timer, s->rx_timeout);
f43dc23d 1259
e1910fcd
GU		 1260 if (count)
1261 tty_flip_buffer_push(&port->state->port);
8b6ff84c 1262
67f462b0
GU		 1263 desc = dmaengine_prep_slave_sg(s->chan_rx, &s->sg_rx[active], 1,
1264 DMA_DEV_TO_MEM,
1265 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1266 if (!desc)
1267 goto fail;
1268
1269 desc->callback = sci_dma_rx_complete;
1270 desc->callback_param = s;
1271 s->cookie_rx[active] = dmaengine_submit(desc);
1272 if (dma_submit_error(s->cookie_rx[active]))
1273 goto fail;
1274
1275 s->active_rx = s->cookie_rx[!active];
1276
1d3db608
MHF		 1277 dma_async_issue_pending(chan);
1278
6fc5a520 1279 spin_unlock_irqrestore(&port->lock, flags);
67f462b0
GU		 1280 dev_dbg(port->dev, "%s: cookie %d #%d, new active cookie %d\n",
1281 __func__, s->cookie_rx[active], active, s->active_rx);
67f462b0
GU		 1282 return;
1283
1284fail:
1285 spin_unlock_irqrestore(&port->lock, flags);
1286 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
2c4ee235
GU		 1287 /* Switch to PIO */
1288 spin_lock_irqsave(&port->lock, flags);
1289 s->chan_rx = NULL;
1290 sci_start_rx(port);
1291 spin_unlock_irqrestore(&port->lock, flags);
1da177e4
LT		 1292}
1293
2c4ee235 1294static void sci_tx_dma_release(struct sci_port *s)
1da177e4 1295{
2c4ee235 1296 struct dma_chan *chan = s->chan_tx_saved;
1da177e4 1297
f6611317 1298 cancel_work_sync(&s->work_tx);
2c4ee235 1299 s->chan_tx_saved = s->chan_tx = NULL;
e1910fcd 1300 s->cookie_tx = -EINVAL;
6eefc68d 1301 dmaengine_terminate_sync(chan);
e1910fcd
GU		 1302 dma_unmap_single(chan->device->dev, s->tx_dma_addr, UART_XMIT_SIZE,
1303 DMA_TO_DEVICE);
1304 dma_release_channel(chan);
e1910fcd 1305}
d535a230 1306
e1910fcd
GU		 1307static void sci_submit_rx(struct sci_port *s)
1308{
1309 struct dma_chan *chan = s->chan_rx;
2c4ee235
GU		 1310 struct uart_port *port = &s->port;
1311 unsigned long flags;
e1910fcd 1312 int i;
073e84c9 1313
e1910fcd
GU		 1314 for (i = 0; i < 2; i++) {
1315 struct scatterlist *sg = &s->sg_rx[i];
1316 struct dma_async_tx_descriptor *desc;
1da177e4 1317
e1910fcd
GU		 1318 desc = dmaengine_prep_slave_sg(chan,
1319 sg, 1, DMA_DEV_TO_MEM,
1320 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1321 if (!desc)
1322 goto fail;
501b825d 1323
e1910fcd
GU		 1324 desc->callback = sci_dma_rx_complete;
1325 desc->callback_param = s;
1326 s->cookie_rx[i] = dmaengine_submit(desc);
1327 if (dma_submit_error(s->cookie_rx[i]))
1328 goto fail;
9174fc8f 1329
e1910fcd 1330 }
9174fc8f 1331
e1910fcd 1332 s->active_rx = s->cookie_rx[0];
9174fc8f 1333
e1910fcd
GU		 1334 dma_async_issue_pending(chan);
1335 return;
9174fc8f 1336
e1910fcd
GU		 1337fail:
1338 if (i)
6eefc68d 1339 dmaengine_terminate_async(chan);
e1910fcd
GU		 1340 for (i = 0; i < 2; i++)
1341 s->cookie_rx[i] = -EINVAL;
1342 s->active_rx = -EINVAL;
2c4ee235
GU		 1343 /* Switch to PIO */
1344 spin_lock_irqsave(&port->lock, flags);
1345 s->chan_rx = NULL;
1346 sci_start_rx(port);
1347 spin_unlock_irqrestore(&port->lock, flags);
e1910fcd 1348}
9174fc8f 1349
e1910fcd 1350static void work_fn_tx(struct work_struct *work)
1da177e4 1351{
e1910fcd
GU		 1352 struct sci_port *s = container_of(work, struct sci_port, work_tx);
1353 struct dma_async_tx_descriptor *desc;
1354 struct dma_chan *chan = s->chan_tx;
1355 struct uart_port *port = &s->port;
1356 struct circ_buf *xmit = &port->state->xmit;
2c4ee235 1357 unsigned long flags;
e1910fcd 1358 dma_addr_t buf;
1da177e4 1359
9174fc8f 1360 /*
e1910fcd
GU		 1361 * DMA is idle now.
1362 * Port xmit buffer is already mapped, and it is one page... Just adjust
1363 * offsets and lengths. Since it is a circular buffer, we have to
1364 * transmit till the end, and then the rest. Take the port lock to get a
1365 * consistent xmit buffer state.
9174fc8f 1366 */
e1910fcd
GU		 1367 spin_lock_irq(&port->lock);
1368 buf = s->tx_dma_addr + (xmit->tail & (UART_XMIT_SIZE - 1));
1369 s->tx_dma_len = min_t(unsigned int,
1370 CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE),
1371 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE));
1372 spin_unlock_irq(&port->lock);
0e8963de 1373
e1910fcd
GU		 1374 desc = dmaengine_prep_slave_single(chan, buf, s->tx_dma_len,
1375 DMA_MEM_TO_DEV,
1376 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1377 if (!desc) {
1378 dev_warn(port->dev, "Failed preparing Tx DMA descriptor\n");
2c4ee235 1379 goto switch_to_pio;
e1910fcd 1380 }
0e8963de 1381
e1910fcd
GU		 1382 dma_sync_single_for_device(chan->device->dev, buf, s->tx_dma_len,
1383 DMA_TO_DEVICE);
1da177e4 1384
e1910fcd
GU		 1385 spin_lock_irq(&port->lock);
1386 desc->callback = sci_dma_tx_complete;
1387 desc->callback_param = s;
1388 spin_unlock_irq(&port->lock);
1389 s->cookie_tx = dmaengine_submit(desc);
1390 if (dma_submit_error(s->cookie_tx)) {
1391 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
2c4ee235 1392 goto switch_to_pio;
1da177e4 1393 }
1da177e4 1394
e1910fcd
GU		 1395 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n",
1396 __func__, xmit->buf, xmit->tail, xmit->head, s->cookie_tx);
73a19e4c 1397
e1910fcd 1398 dma_async_issue_pending(chan);
2c4ee235
GU		 1399 return;
1400
1401switch_to_pio:
1402 spin_lock_irqsave(&port->lock, flags);
1403 s->chan_tx = NULL;
1404 sci_start_tx(port);
1405 spin_unlock_irqrestore(&port->lock, flags);
1406 return;
1da177e4
LT		 1407}
1408
b96408b4 1409static enum hrtimer_restart rx_timer_fn(struct hrtimer *t)
1da177e4 1410{
b96408b4 1411 struct sci_port *s = container_of(t, struct sci_port, rx_timer);
e7327c09 1412 struct dma_chan *chan = s->chan_rx;
e1910fcd 1413 struct uart_port *port = &s->port;
67f462b0
GU		 1414 struct dma_tx_state state;
1415 enum dma_status status;
1416 unsigned long flags;
1417 unsigned int read;
1418 int active, count;
1419 u16 scr;
1420
67f462b0 1421 dev_dbg(port->dev, "DMA Rx timed out\n");
67f462b0 1422
6fc5a520
TA		 1423 spin_lock_irqsave(&port->lock, flags);
1424
67f462b0
GU		 1425 active = sci_dma_rx_find_active(s);
1426 if (active < 0) {
1427 spin_unlock_irqrestore(&port->lock, flags);
b96408b4 1428 return HRTIMER_NORESTART;
67f462b0
GU		 1429 }
1430
1431 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
3b963042 1432 if (status == DMA_COMPLETE) {
6fc5a520 1433 spin_unlock_irqrestore(&port->lock, flags);
67f462b0
GU		 1434 dev_dbg(port->dev, "Cookie %d #%d has already completed\n",
1435 s->active_rx, active);
3b963042
MHF		 1436
1437 /* Let packet complete handler take care of the packet */
b96408b4 1438 return HRTIMER_NORESTART;
3b963042 1439 }
67f462b0 1440
e7327c09
MHF		 1441 dmaengine_pause(chan);
1442
1443 /*
1444 * sometimes DMA transfer doesn't stop even if it is stopped and
1445 * data keeps on coming until transaction is complete so check
1446 * for DMA_COMPLETE again
1447 * Let packet complete handler take care of the packet
1448 */
1449 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
1450 if (status == DMA_COMPLETE) {
1451 spin_unlock_irqrestore(&port->lock, flags);
1452 dev_dbg(port->dev, "Transaction complete after DMA engine was stopped");
b96408b4 1453 return HRTIMER_NORESTART;
e7327c09
MHF		 1454 }
1455
67f462b0 1456 /* Handle incomplete DMA receive */
6eefc68d 1457 dmaengine_terminate_async(s->chan_rx);
67f462b0 1458 read = sg_dma_len(&s->sg_rx[active]) - state.residue;
67f462b0
GU		 1459
1460 if (read) {
1461 count = sci_dma_rx_push(s, s->rx_buf[active], read);
1462 if (count)
1463 tty_flip_buffer_push(&port->state->port);
1464 }
1465
756981be
GU		 1466 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1467 sci_submit_rx(s);
371cfed3
MHF		 1468
1469 /* Direct new serial port interrupts back to CPU */
1470 scr = serial_port_in(port, SCSCR);
1471 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1472 scr &= ~SCSCR_RDRQE;
1473 enable_irq(s->irqs[SCIx_RXI_IRQ]);
1474 }
1475 serial_port_out(port, SCSCR, scr | SCSCR_RIE);
1476
1477 spin_unlock_irqrestore(&port->lock, flags);
b96408b4
UH		 1478
1479 return HRTIMER_NORESTART;
1da177e4
LT		 1480}
1481
ff441129 1482static struct dma_chan *sci_request_dma_chan(struct uart_port *port,
219fb0c1 1483 enum dma_transfer_direction dir)
ff441129 1484{
ff441129
GU		 1485 struct dma_chan *chan;
1486 struct dma_slave_config cfg;
1487 int ret;
1488
219fb0c1
LP		 1489 chan = dma_request_slave_channel(port->dev,
1490 dir == DMA_MEM_TO_DEV ? "tx" : "rx");
ff441129 1491 if (!chan) {
9b7becf1 1492 dev_warn(port->dev, "dma_request_slave_channel failed\n");
ff441129
GU		 1493 return NULL;
1494 }
1495
1496 memset(&cfg, 0, sizeof(cfg));
1497 cfg.direction = dir;
1498 if (dir == DMA_MEM_TO_DEV) {
1499 cfg.dst_addr = port->mapbase +
1500 (sci_getreg(port, SCxTDR)->offset << port->regshift);
1501 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1502 } else {
1503 cfg.src_addr = port->mapbase +
1504 (sci_getreg(port, SCxRDR)->offset << port->regshift);
1505 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1506 }
1507
1508 ret = dmaengine_slave_config(chan, &cfg);
1509 if (ret) {
1510 dev_warn(port->dev, "dmaengine_slave_config failed %d\n", ret);
1511 dma_release_channel(chan);
1512 return NULL;
1513 }
1514
1515 return chan;
1516}
1517
e1910fcd 1518static void sci_request_dma(struct uart_port *port)
73a19e4c 1519{
e1910fcd 1520 struct sci_port *s = to_sci_port(port);
e1910fcd 1521 struct dma_chan *chan;
73a19e4c 1522
e1910fcd 1523 dev_dbg(port->dev, "%s: port %d\n", __func__, port->line);
73a19e4c 1524
219fb0c1 1525 if (!port->dev->of_node)
e1910fcd 1526 return;
73a19e4c 1527
e1910fcd 1528 s->cookie_tx = -EINVAL;
7464779f
AL		 1529
1530 /*
1531 * Don't request a dma channel if no channel was specified
1532 * in the device tree.
1533 */
1534 if (!of_find_property(port->dev->of_node, "dmas", NULL))
1535 return;
1536
219fb0c1 1537 chan = sci_request_dma_chan(port, DMA_MEM_TO_DEV);
e1910fcd
GU		 1538 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
1539 if (chan) {
e1910fcd
GU		 1540 /* UART circular tx buffer is an aligned page. */
1541 s->tx_dma_addr = dma_map_single(chan->device->dev,
1542 port->state->xmit.buf,
1543 UART_XMIT_SIZE,
1544 DMA_TO_DEVICE);
1545 if (dma_mapping_error(chan->device->dev, s->tx_dma_addr)) {
1546 dev_warn(port->dev, "Failed mapping Tx DMA descriptor\n");
1547 dma_release_channel(chan);
e1910fcd
GU		 1548 } else {
1549 dev_dbg(port->dev, "%s: mapped %lu@%p to %pad\n",
1550 __func__, UART_XMIT_SIZE,
1551 port->state->xmit.buf, &s->tx_dma_addr);
2c4ee235 1552
f6611317 1553 INIT_WORK(&s->work_tx, work_fn_tx);
2c4ee235 1554 s->chan_tx_saved = s->chan_tx = chan;
49d4bcad 1555 }
3089f381
GL		 1556 }
1557
219fb0c1 1558 chan = sci_request_dma_chan(port, DMA_DEV_TO_MEM);
e1910fcd
GU		 1559 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan);
1560 if (chan) {
1561 unsigned int i;
1562 dma_addr_t dma;
1563 void *buf;
73a19e4c 1564
e1910fcd
GU		 1565 s->buf_len_rx = 2 * max_t(size_t, 16, port->fifosize);
1566 buf = dma_alloc_coherent(chan->device->dev, s->buf_len_rx * 2,
1567 &dma, GFP_KERNEL);
1568 if (!buf) {
1569 dev_warn(port->dev,
1570 "Failed to allocate Rx dma buffer, using PIO\n");
1571 dma_release_channel(chan);
e1910fcd
GU		 1572 return;
1573 }
73a19e4c 1574
e1910fcd
GU		 1575 for (i = 0; i < 2; i++) {
1576 struct scatterlist *sg = &s->sg_rx[i];
0533502d 1577
e1910fcd
GU		 1578 sg_init_table(sg, 1);
1579 s->rx_buf[i] = buf;
1580 sg_dma_address(sg) = dma;
d09959e7 1581 sg_dma_len(sg) = s->buf_len_rx;
0533502d 1582
e1910fcd
GU		 1583 buf += s->buf_len_rx;
1584 dma += s->buf_len_rx;
1585 }
1586
b96408b4
UH		 1587 hrtimer_init(&s->rx_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
1588 s->rx_timer.function = rx_timer_fn;
e1910fcd 1589
756981be
GU		 1590 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1591 sci_submit_rx(s);
2c4ee235
GU		 1592
1593 s->chan_rx_saved = s->chan_rx = chan;
e1910fcd 1594 }
0533502d
GU		 1595}
1596
e1910fcd 1597static void sci_free_dma(struct uart_port *port)
73a19e4c 1598{
e1910fcd 1599 struct sci_port *s = to_sci_port(port);
73a19e4c 1600
2c4ee235
GU		 1601 if (s->chan_tx_saved)
1602 sci_tx_dma_release(s);
1603 if (s->chan_rx_saved)
1604 sci_rx_dma_release(s);
e1910fcd 1605}
1cf4a7ef
GU		 1606
1607static void sci_flush_buffer(struct uart_port *port)
1608{
1609 /*
1610 * In uart_flush_buffer(), the xmit circular buffer has just been
1611 * cleared, so we have to reset tx_dma_len accordingly.
1612 */
1613 to_sci_port(port)->tx_dma_len = 0;
1614}
1615#else /* !CONFIG_SERIAL_SH_SCI_DMA */
e1910fcd
GU		 1616static inline void sci_request_dma(struct uart_port *port)
1617{
1618}
73a19e4c 1619
e1910fcd
GU		 1620static inline void sci_free_dma(struct uart_port *port)
1621{
1622}
1cf4a7ef
GU		 1623
1624#define sci_flush_buffer NULL
1625#endif /* !CONFIG_SERIAL_SH_SCI_DMA */
73a19e4c 1626
e1910fcd
GU		 1627static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
1628{
e1910fcd
GU		 1629 struct uart_port *port = ptr;
1630 struct sci_port *s = to_sci_port(port);
73a19e4c 1631
03940376 1632#ifdef CONFIG_SERIAL_SH_SCI_DMA
e1910fcd
GU		 1633 if (s->chan_rx) {
1634 u16 scr = serial_port_in(port, SCSCR);
1635 u16 ssr = serial_port_in(port, SCxSR);
73a19e4c 1636
e1910fcd
GU		 1637 /* Disable future Rx interrupts */
1638 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1639 disable_irq_nosync(irq);
1640 scr |= SCSCR_RDRQE;
1641 } else {
1642 scr &= ~SCSCR_RIE;
756981be 1643 sci_submit_rx(s);
e1910fcd
GU		 1644 }
1645 serial_port_out(port, SCSCR, scr);
1646 /* Clear current interrupt */
1647 serial_port_out(port, SCxSR,
1648 ssr & ~(SCIF_DR | SCxSR_RDxF(port)));
b96408b4 1649 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u us\n",
e1910fcd 1650 jiffies, s->rx_timeout);
b96408b4 1651 start_hrtimer_us(&s->rx_timer, s->rx_timeout);
73a19e4c 1652
e1910fcd
GU		 1653 return IRQ_HANDLED;
1654 }
1655#endif
73a19e4c 1656
03940376
UH		 1657 if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0) {
1658 if (!scif_rtrg_enabled(port))
1659 scif_set_rtrg(port, s->rx_trigger);
1660
1661 mod_timer(&s->rx_fifo_timer, jiffies + DIV_ROUND_UP(
b96408b4 1662 s->rx_frame * HZ * s->rx_fifo_timeout, 1000000));
03940376
UH		 1663 }
1664
e1910fcd
GU		 1665 /* I think sci_receive_chars has to be called irrespective
1666 * of whether the I_IXOFF is set, otherwise, how is the interrupt
1667 * to be disabled?
1668 */
1669 sci_receive_chars(ptr);
1670
1671 return IRQ_HANDLED;
73a19e4c
GL		 1672}
1673
e1910fcd 1674static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
73a19e4c 1675{
e1910fcd 1676 struct uart_port *port = ptr;
04928b79 1677 unsigned long flags;
73a19e4c 1678
04928b79 1679 spin_lock_irqsave(&port->lock, flags);
e1910fcd 1680 sci_transmit_chars(port);
04928b79 1681 spin_unlock_irqrestore(&port->lock, flags);
e1910fcd
GU		 1682
1683 return IRQ_HANDLED;
73a19e4c
GL		 1684}
1685
628c534a
CB		 1686static irqreturn_t sci_br_interrupt(int irq, void *ptr)
1687{
1688 struct uart_port *port = ptr;
1689
1690 /* Handle BREAKs */
1691 sci_handle_breaks(port);
1692 sci_clear_SCxSR(port, SCxSR_BREAK_CLEAR(port));
1693
1694 return IRQ_HANDLED;
1695}
8b0bbd95 1696
e1910fcd 1697static irqreturn_t sci_er_interrupt(int irq, void *ptr)
73a19e4c 1698{
e1910fcd
GU		 1699 struct uart_port *port = ptr;
1700 struct sci_port *s = to_sci_port(port);
73a19e4c 1701
628c534a 1702 if (s->irqs[SCIx_ERI_IRQ] == s->irqs[SCIx_BRI_IRQ]) {
8b0bbd95
CB		 1703 /* Break and Error interrupts are muxed */
1704 unsigned short ssr_status = serial_port_in(port, SCxSR);
1705
1706 /* Break Interrupt */
1707 if (ssr_status & SCxSR_BRK(port))
1708 sci_br_interrupt(irq, ptr);
1709
1710 /* Break only? */
1711 if (!(ssr_status & SCxSR_ERRORS(port)))
1712 return IRQ_HANDLED;
1713 }
1714
e1910fcd
GU		 1715 /* Handle errors */
1716 if (port->type == PORT_SCI) {
1717 if (sci_handle_errors(port)) {
1718 /* discard character in rx buffer */
1719 serial_port_in(port, SCxSR);
1720 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1721 }
1722 } else {
1723 sci_handle_fifo_overrun(port);
1724 if (!s->chan_rx)
1725 sci_receive_chars(ptr);
1726 }
1727
1728 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
1729
1730 /* Kick the transmission */
1731 if (!s->chan_tx)
1732 sci_tx_interrupt(irq, ptr);
1733
1734 return IRQ_HANDLED;
73a19e4c
GL		 1735}
1736
e1910fcd
GU		 1737static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
1738{
1739 unsigned short ssr_status, scr_status, err_enabled, orer_status = 0;
1740 struct uart_port *port = ptr;
1741 struct sci_port *s = to_sci_port(port);
1742 irqreturn_t ret = IRQ_NONE;
73a19e4c 1743
e1910fcd
GU		 1744 ssr_status = serial_port_in(port, SCxSR);
1745 scr_status = serial_port_in(port, SCSCR);
b2f20ed9 1746 if (s->params->overrun_reg == SCxSR)
e1910fcd 1747 orer_status = ssr_status;
b2f20ed9
LP		 1748 else if (sci_getreg(port, s->params->overrun_reg)->size)
1749 orer_status = serial_port_in(port, s->params->overrun_reg);
73a19e4c 1750
e1910fcd 1751 err_enabled = scr_status & port_rx_irq_mask(port);
73a19e4c 1752
e1910fcd
GU		 1753 /* Tx Interrupt */
1754 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) &&
1755 !s->chan_tx)
1756 ret = sci_tx_interrupt(irq, ptr);
658daa95 1757
e1910fcd
GU		 1758 /*
1759 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF /
1760 * DR flags
1761 */
1762 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&
1763 (scr_status & SCSCR_RIE))
1764 ret = sci_rx_interrupt(irq, ptr);
73a19e4c 1765
e1910fcd
GU		 1766 /* Error Interrupt */
1767 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
1768 ret = sci_er_interrupt(irq, ptr);
73a19e4c 1769
e1910fcd
GU		 1770 /* Break Interrupt */
1771 if ((ssr_status & SCxSR_BRK(port)) && err_enabled)
1772 ret = sci_br_interrupt(irq, ptr);
1773
1774 /* Overrun Interrupt */
b2f20ed9 1775 if (orer_status & s->params->overrun_mask) {
e1910fcd
GU		 1776 sci_handle_fifo_overrun(port);
1777 ret = IRQ_HANDLED;
73a19e4c 1778 }
73a19e4c 1779
e1910fcd
GU		 1780 return ret;
1781}
73a19e4c 1782
e1910fcd
GU		 1783static const struct sci_irq_desc {
1784 const char *desc;
1785 irq_handler_t handler;
1786} sci_irq_desc[] = {
1787 /*
1788 * Split out handlers, the default case.
1789 */
1790 [SCIx_ERI_IRQ] = {
1791 .desc = "rx err",
1792 .handler = sci_er_interrupt,
1793 },
3089f381 1794
e1910fcd
GU		 1795 [SCIx_RXI_IRQ] = {
1796 .desc = "rx full",
1797 .handler = sci_rx_interrupt,
1798 },
47aceb92 1799
e1910fcd
GU		 1800 [SCIx_TXI_IRQ] = {
1801 .desc = "tx empty",
1802 .handler = sci_tx_interrupt,
1803 },
73a19e4c 1804
e1910fcd
GU		 1805 [SCIx_BRI_IRQ] = {
1806 .desc = "break",
1807 .handler = sci_br_interrupt,
1808 },
73a19e4c 1809
628c534a
CB		 1810 [SCIx_DRI_IRQ] = {
1811 .desc = "rx ready",
1812 .handler = sci_rx_interrupt,
1813 },
1814
1815 [SCIx_TEI_IRQ] = {
1816 .desc = "tx end",
1817 .handler = sci_tx_interrupt,
1818 },
1819
73a19e4c 1820 /*
e1910fcd 1821 * Special muxed handler.
73a19e4c 1822 */
e1910fcd
GU		 1823 [SCIx_MUX_IRQ] = {
1824 .desc = "mux",
1825 .handler = sci_mpxed_interrupt,
1826 },
1827};
73a19e4c 1828
e1910fcd
GU		 1829static int sci_request_irq(struct sci_port *port)
1830{
1831 struct uart_port *up = &port->port;
628c534a 1832 int i, j, w, ret = 0;
73a19e4c 1833
e1910fcd
GU		 1834 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) {
1835 const struct sci_irq_desc *desc;
1836 int irq;
73a19e4c 1837
628c534a
CB		 1838 /* Check if already registered (muxed) */
1839 for (w = 0; w < i; w++)
1840 if (port->irqs[w] == port->irqs[i])
1841 w = i + 1;
1842 if (w > i)
1843 continue;
1844
e1910fcd
GU		 1845 if (SCIx_IRQ_IS_MUXED(port)) {
1846 i = SCIx_MUX_IRQ;
1847 irq = up->irq;
1848 } else {
1849 irq = port->irqs[i];
1850
1851 /*
1852 * Certain port types won't support all of the
1853 * available interrupt sources.
1854 */
1855 if (unlikely(irq < 0))
1856 continue;
1857 }
1858
1859 desc = sci_irq_desc + i;
628c534a
CB		 1860 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s",
1861 dev_name(up->dev), desc->desc);
623ac1d4
PB		 1862 if (!port->irqstr[j]) {
1863 ret = -ENOMEM;
e1910fcd 1864 goto out_nomem;
623ac1d4 1865 }
e1910fcd
GU		 1866
1867 ret = request_irq(irq, desc->handler, up->irqflags,
1868 port->irqstr[j], port);
1869 if (unlikely(ret)) {
1870 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc);
1871 goto out_noirq;
1872 }
73a19e4c
GL		 1873 }
1874
e1910fcd 1875 return 0;
1da177e4 1876
e1910fcd
GU		 1877out_noirq:
1878 while (--i >= 0)
1879 free_irq(port->irqs[i], port);
f43dc23d 1880
e1910fcd
GU		 1881out_nomem:
1882 while (--j >= 0)
1883 kfree(port->irqstr[j]);
f43dc23d 1884
e1910fcd 1885 return ret;
1da177e4
LT		 1886}
1887
e1910fcd 1888static void sci_free_irq(struct sci_port *port)
1da177e4 1889{
e1910fcd 1890 int i;
1da177e4 1891
e1910fcd
GU		 1892 /*
1893 * Intentionally in reverse order so we iterate over the muxed
1894 * IRQ first.
1895 */
1896 for (i = 0; i < SCIx_NR_IRQS; i++) {
1897 int irq = port->irqs[i];
f43dc23d 1898
e1910fcd
GU		 1899 /*
1900 * Certain port types won't support all of the available
1901 * interrupt sources.
1902 */
1903 if (unlikely(irq < 0))
1904 continue;
f43dc23d 1905
e1910fcd
GU		 1906 free_irq(port->irqs[i], port);
1907 kfree(port->irqstr[i]);
f43dc23d 1908
e1910fcd
GU		 1909 if (SCIx_IRQ_IS_MUXED(port)) {
1910 /* If there's only one IRQ, we're done. */
1911 return;
1912 }
1913 }
1da177e4
LT		 1914}
1915
e1910fcd 1916static unsigned int sci_tx_empty(struct uart_port *port)
1da177e4 1917{
e1910fcd
GU		 1918 unsigned short status = serial_port_in(port, SCxSR);
1919 unsigned short in_tx_fifo = sci_txfill(port);
f43dc23d 1920
e1910fcd 1921 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
1da177e4
LT		 1922}
1923
33f50ffc
GU		 1924static void sci_set_rts(struct uart_port *port, bool state)
1925{
1926 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1927 u16 data = serial_port_in(port, SCPDR);
1928
1929 /* Active low */
1930 if (state)
1931 data &= ~SCPDR_RTSD;
1932 else
1933 data |= SCPDR_RTSD;
1934 serial_port_out(port, SCPDR, data);
1935
1936 /* RTS# is output */
1937 serial_port_out(port, SCPCR,
1938 serial_port_in(port, SCPCR) | SCPCR_RTSC);
1939 } else if (sci_getreg(port, SCSPTR)->size) {
1940 u16 ctrl = serial_port_in(port, SCSPTR);
1941
1942 /* Active low */
1943 if (state)
1944 ctrl &= ~SCSPTR_RTSDT;
1945 else
1946 ctrl |= SCSPTR_RTSDT;
1947 serial_port_out(port, SCSPTR, ctrl);
1948 }
1949}
1950
1951static bool sci_get_cts(struct uart_port *port)
1952{
1953 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1954 /* Active low */
1955 return !(serial_port_in(port, SCPDR) & SCPDR_CTSD);
1956 } else if (sci_getreg(port, SCSPTR)->size) {
1957 /* Active low */
1958 return !(serial_port_in(port, SCSPTR) & SCSPTR_CTSDT);
1959 }
1960
1961 return true;
1962}
1963
e1910fcd
GU		 1964/*
1965 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally
1966 * CTS/RTS is supported in hardware by at least one port and controlled
1967 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently
1968 * handled via the ->init_pins() op, which is a bit of a one-way street,
1969 * lacking any ability to defer pin control -- this will later be
1970 * converted over to the GPIO framework).
1971 *
1972 * Other modes (such as loopback) are supported generically on certain
1973 * port types, but not others. For these it's sufficient to test for the
1974 * existence of the support register and simply ignore the port type.
1975 */
1976static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
1da177e4 1977{
f907c9ea
GU		 1978 struct sci_port *s = to_sci_port(port);
1979
e1910fcd
GU		 1980 if (mctrl & TIOCM_LOOP) {
1981 const struct plat_sci_reg *reg;
f43dc23d 1982
e1910fcd
GU		 1983 /*
1984 * Standard loopback mode for SCFCR ports.
1985 */
1986 reg = sci_getreg(port, SCFCR);
1987 if (reg->size)
1988 serial_port_out(port, SCFCR,
1989 serial_port_in(port, SCFCR) |
1990 SCFCR_LOOP);
1991 }
f907c9ea
GU		 1992
1993 mctrl_gpio_set(s->gpios, mctrl);
33f50ffc 1994
97ed9790 1995 if (!s->has_rtscts)
33f50ffc
GU		 1996 return;
1997
1998 if (!(mctrl & TIOCM_RTS)) {
1999 /* Disable Auto RTS */
2000 serial_port_out(port, SCFCR,
2001 serial_port_in(port, SCFCR) & ~SCFCR_MCE);
2002
2003 /* Clear RTS */
2004 sci_set_rts(port, 0);
2005 } else if (s->autorts) {
2006 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
2007 /* Enable RTS# pin function */
2008 serial_port_out(port, SCPCR,
2009 serial_port_in(port, SCPCR) & ~SCPCR_RTSC);
2010 }
2011
2012 /* Enable Auto RTS */
2013 serial_port_out(port, SCFCR,
2014 serial_port_in(port, SCFCR) | SCFCR_MCE);
2015 } else {
2016 /* Set RTS */
2017 sci_set_rts(port, 1);
2018 }
e1910fcd 2019}
f43dc23d 2020
e1910fcd
GU		 2021static unsigned int sci_get_mctrl(struct uart_port *port)
2022{
f907c9ea
GU		 2023 struct sci_port *s = to_sci_port(port);
2024 struct mctrl_gpios *gpios = s->gpios;
2025 unsigned int mctrl = 0;
2026
2027 mctrl_gpio_get(gpios, &mctrl);
2028
e1910fcd
GU		 2029 /*
2030 * CTS/RTS is handled in hardware when supported, while nothing
33f50ffc 2031 * else is wired up.
e1910fcd 2032 */
33f50ffc
GU		 2033 if (s->autorts) {
2034 if (sci_get_cts(port))
2035 mctrl |= TIOCM_CTS;
2036 } else if (IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(gpios, UART_GPIO_CTS))) {
f907c9ea 2037 mctrl |= TIOCM_CTS;
33f50ffc 2038 }
f907c9ea
GU		 2039 if (IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(gpios, UART_GPIO_DSR)))
2040 mctrl |= TIOCM_DSR;
2041 if (IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(gpios, UART_GPIO_DCD)))
2042 mctrl |= TIOCM_CAR;
2043
2044 return mctrl;
2045}
2046
2047static void sci_enable_ms(struct uart_port *port)
2048{
2049 mctrl_gpio_enable_ms(to_sci_port(port)->gpios);
1da177e4
LT		 2050}
2051
1da177e4
LT		 2052static void sci_break_ctl(struct uart_port *port, int break_state)
2053{
bbb4ce50 2054 unsigned short scscr, scsptr;
1be22663 2055 unsigned long flags;
bbb4ce50 2056
a4e02f6d 2057 /* check wheter the port has SCSPTR */
abbf121f 2058 if (!sci_getreg(port, SCSPTR)->size) {
bbb4ce50
SY		 2059 /*
2060 * Not supported by hardware. Most parts couple break and rx
2061 * interrupts together, with break detection always enabled.
2062 */
a4e02f6d 2063 return;
bbb4ce50 2064 }
a4e02f6d 2065
1be22663 2066 spin_lock_irqsave(&port->lock, flags);
a4e02f6d
SY		 2067 scsptr = serial_port_in(port, SCSPTR);
2068 scscr = serial_port_in(port, SCSCR);
2069
2070 if (break_state == -1) {
2071 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT;
2072 scscr &= ~SCSCR_TE;
2073 } else {
2074 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO;
2075 scscr |= SCSCR_TE;
2076 }
2077
2078 serial_port_out(port, SCSPTR, scsptr);
2079 serial_port_out(port, SCSCR, scscr);
1be22663 2080 spin_unlock_irqrestore(&port->lock, flags);
1da177e4
LT		 2081}
2082
2083static int sci_startup(struct uart_port *port)
2084{
a5660ada 2085 struct sci_port *s = to_sci_port(port);
073e84c9 2086 int ret;
1da177e4 2087
73a19e4c
GL		 2088 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
2089
3c910176
TA		 2090 sci_request_dma(port);
2091
073e84c9 2092 ret = sci_request_irq(s);
3c910176
TA		 2093 if (unlikely(ret < 0)) {
2094 sci_free_dma(port);
073e84c9 2095 return ret;
3c910176 2096 }
073e84c9 2097
1da177e4
LT		 2098 return 0;
2099}
2100
2101static void sci_shutdown(struct uart_port *port)
2102{
a5660ada 2103 struct sci_port *s = to_sci_port(port);
33b48e16 2104 unsigned long flags;
5fd2b6ee 2105 u16 scr;
1da177e4 2106
73a19e4c
GL		 2107 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
2108
33f50ffc 2109 s->autorts = false;
f907c9ea
GU		 2110 mctrl_gpio_disable_ms(to_sci_port(port)->gpios);
2111
33b48e16 2112 spin_lock_irqsave(&port->lock, flags);
1da177e4 2113 sci_stop_rx(port);
b129a8cc 2114 sci_stop_tx(port);
fa2abb03
UH		 2115 /*
2116 * Stop RX and TX, disable related interrupts, keep clock source
2117 * and HSCIF TOT bits
2118 */
5fd2b6ee 2119 scr = serial_port_in(port, SCSCR);
fa2abb03
UH		 2120 serial_port_out(port, SCSCR, scr &
2121 (SCSCR_CKE1 | SCSCR_CKE0 | s->hscif_tot));
33b48e16 2122 spin_unlock_irqrestore(&port->lock, flags);
073e84c9 2123
9ab76556 2124#ifdef CONFIG_SERIAL_SH_SCI_DMA
2c4ee235 2125 if (s->chan_rx_saved) {
9ab76556
AM		 2126 dev_dbg(port->dev, "%s(%d) deleting rx_timer\n", __func__,
2127 port->line);
b96408b4 2128 hrtimer_cancel(&s->rx_timer);
9ab76556
AM		 2129 }
2130#endif
2131
c5a9262f
GU		 2132 if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0)
2133 del_timer_sync(&s->rx_fifo_timer);
1da177e4 2134 sci_free_irq(s);
3c910176 2135 sci_free_dma(port);
1da177e4
LT		 2136}
2137
6af27bf2
GU		 2138static int sci_sck_calc(struct sci_port *s, unsigned int bps,
2139 unsigned int *srr)
26c92f37 2140{
6af27bf2 2141 unsigned long freq = s->clk_rates[SCI_SCK];
6af27bf2 2142 int err, min_err = INT_MAX;
69eee8e9 2143 unsigned int sr;
6af27bf2 2144
7b5c0c08
GU		 2145 if (s->port.type != PORT_HSCIF)
2146 freq *= 2;
6af27bf2 2147
69eee8e9 2148 for_each_sr(sr, s) {
6af27bf2
GU		 2149 err = DIV_ROUND_CLOSEST(freq, sr) - bps;
2150 if (abs(err) >= abs(min_err))
2151 continue;
2152
2153 min_err = err;
2154 *srr = sr - 1;
ec09c5eb 2155
6af27bf2
GU		 2156 if (!err)
2157 break;
2158 }
e8183a6c 2159
6af27bf2
GU		 2160 dev_dbg(s->port.dev, "SCK: %u%+d bps using SR %u\n", bps, min_err,
2161 *srr + 1);
2162 return min_err;
26c92f37
PM		 2163}
2164
1270f865
GU		 2165static int sci_brg_calc(struct sci_port *s, unsigned int bps,
2166 unsigned long freq, unsigned int *dlr,
2167 unsigned int *srr)
730c4e78 2168{
1270f865 2169 int err, min_err = INT_MAX;
69eee8e9 2170 unsigned int sr, dl;
730c4e78 2171
7b5c0c08
GU		 2172 if (s->port.type != PORT_HSCIF)
2173 freq *= 2;
730c4e78 2174
69eee8e9 2175 for_each_sr(sr, s) {
1270f865
GU		 2176 dl = DIV_ROUND_CLOSEST(freq, sr * bps);
2177 dl = clamp(dl, 1U, 65535U);
2178
2179 err = DIV_ROUND_CLOSEST(freq, sr * dl) - bps;
2180 if (abs(err) >= abs(min_err))
2181 continue;
2182
2183 min_err = err;
2184 *dlr = dl;
2185 *srr = sr - 1;
2186
2187 if (!err)
2188 break;
2189 }
730c4e78 2190
1270f865
GU		 2191 dev_dbg(s->port.dev, "BRG: %u%+d bps using DL %u SR %u\n", bps,
2192 min_err, *dlr, *srr + 1);
2193 return min_err;
2194}
730c4e78 2195
b4a5c459 2196/* calculate sample rate, BRR, and clock select */
f4998e55
GU		 2197static int sci_scbrr_calc(struct sci_port *s, unsigned int bps,
2198 unsigned int *brr, unsigned int *srr,
2199 unsigned int *cks)
f303b364 2200{
f4998e55 2201 unsigned long freq = s->clk_rates[SCI_FCK];
69eee8e9 2202 unsigned int sr, br, prediv, scrate, c;
6c51332d 2203 int err, min_err = INT_MAX;
f303b364 2204
7b5c0c08
GU		 2205 if (s->port.type != PORT_HSCIF)
2206 freq *= 2;
b4a5c459 2207
6c51332d
GU		 2208 /*
2209 * Find the combination of sample rate and clock select with the
2210 * smallest deviation from the desired baud rate.
2211 * Prefer high sample rates to maximise the receive margin.
2212 *
2213 * M: Receive margin (%)
2214 * N: Ratio of bit rate to clock (N = sampling rate)
2215 * D: Clock duty (D = 0 to 1.0)
2216 * L: Frame length (L = 9 to 12)
2217 * F: Absolute value of clock frequency deviation
2218 *
2219 * M = |(0.5 - 1 / 2 * N) - ((L - 0.5) * F) -
2220 * (|D - 0.5| / N * (1 + F))|
2221 * NOTE: Usually, treat D for 0.5, F is 0 by this calculation.
2222 */
69eee8e9 2223 for_each_sr(sr, s) {
f303b364
UH		 2224 for (c = 0; c <= 3; c++) {
2225 /* integerized formulas from HSCIF documentation */
7b5c0c08 2226 prediv = sr * (1 << (2 * c + 1));
de01e6cd
GU		 2227
2228 /*
2229 * We need to calculate:
2230 *
2231 * br = freq / (prediv * bps) clamped to [1..256]
881a7489 2232 * err = freq / (br * prediv) - bps
730c4e78 2233 *
de01e6cd
GU		 2234 * Watch out for overflow when calculating the desired
2235 * sampling clock rate!
730c4e78 2236 */
de01e6cd
GU		 2237 if (bps > UINT_MAX / prediv)
2238 break;
2239
2240 scrate = prediv * bps;
2241 br = DIV_ROUND_CLOSEST(freq, scrate);
95a2703e 2242 br = clamp(br, 1U, 256U);
6c51332d 2243
881a7489 2244 err = DIV_ROUND_CLOSEST(freq, br * prediv) - bps;
6c51332d 2245 if (abs(err) >= abs(min_err))
730c4e78
NI		 2246 continue;
2247
6c51332d 2248 min_err = err;
95a2703e 2249 *brr = br - 1;
730c4e78
NI		 2250 *srr = sr - 1;
2251 *cks = c;
6c51332d
GU		 2252
2253 if (!err)
2254 goto found;
f303b364
UH		 2255 }
2256 }
2257
6c51332d 2258found:
881a7489
GU		 2259 dev_dbg(s->port.dev, "BRR: %u%+d bps using N %u SR %u cks %u\n", bps,
2260 min_err, *brr, *srr + 1, *cks);
f4998e55 2261 return min_err;
f303b364
UH		 2262}
2263
1ba76220
MD		 2264static void sci_reset(struct uart_port *port)
2265{
d3184e68 2266 const struct plat_sci_reg *reg;
1ba76220 2267 unsigned int status;
18e8cf15 2268 struct sci_port *s = to_sci_port(port);
1ba76220 2269
fa2abb03 2270 serial_port_out(port, SCSCR, s->hscif_tot); /* TE=0, RE=0, CKE1=0 */
1ba76220 2271
0979e0e6
PM		 2272 reg = sci_getreg(port, SCFCR);
2273 if (reg->size)
b12bb29f 2274 serial_port_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
2768cf42
GU		 2275
2276 sci_clear_SCxSR(port,
2277 SCxSR_RDxF_CLEAR(port) & SCxSR_ERROR_CLEAR(port) &
2278 SCxSR_BREAK_CLEAR(port));
fc2af334
GU		 2279 if (sci_getreg(port, SCLSR)->size) {
2280 status = serial_port_in(port, SCLSR);
2281 status &= ~(SCLSR_TO | SCLSR_ORER);
2282 serial_port_out(port, SCLSR, status);
2283 }
18e8cf15 2284
03940376
UH		 2285 if (s->rx_trigger > 1) {
2286 if (s->rx_fifo_timeout) {
2287 scif_set_rtrg(port, 1);
e99e88a9 2288 timer_setup(&s->rx_fifo_timer, rx_fifo_timer_fn, 0);
03940376 2289 } else {
90afa525
UH		 2290 if (port->type == PORT_SCIFA ||
2291 port->type == PORT_SCIFB)
2292 scif_set_rtrg(port, 1);
2293 else
2294 scif_set_rtrg(port, s->rx_trigger);
03940376
UH		 2295 }
2296 }
1ba76220
MD		 2297}
2298
606d099c
AC		 2299static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
2300 struct ktermios *old)
1da177e4 2301{
03940376 2302 unsigned int baud, smr_val = SCSMR_ASYNC, scr_val = 0, i, bits;
1270f865
GU		 2303 unsigned int brr = 255, cks = 0, srr = 15, dl = 0, sccks = 0;
2304 unsigned int brr1 = 255, cks1 = 0, srr1 = 15, dl1 = 0;
00b9de9c 2305 struct sci_port *s = to_sci_port(port);
d3184e68 2306 const struct plat_sci_reg *reg;
f4998e55
GU		 2307 int min_err = INT_MAX, err;
2308 unsigned long max_freq = 0;
2309 int best_clk = -1;
1be22663 2310 unsigned long flags;
1da177e4 2311
730c4e78
NI		 2312 if ((termios->c_cflag & CSIZE) == CS7)
2313 smr_val |= SCSMR_CHR;
2314 if (termios->c_cflag & PARENB)
2315 smr_val |= SCSMR_PE;
2316 if (termios->c_cflag & PARODD)
2317 smr_val |= SCSMR_PE | SCSMR_ODD;
2318 if (termios->c_cflag & CSTOPB)
2319 smr_val |= SCSMR_STOP;
2320
154280fd
MD		 2321 /*
2322 * earlyprintk comes here early on with port->uartclk set to zero.
2323 * the clock framework is not up and running at this point so here
2324 * we assume that 115200 is the maximum baud rate. please note that
2325 * the baud rate is not programmed during earlyprintk - it is assumed
2326 * that the previous boot loader has enabled required clocks and
2327 * setup the baud rate generator hardware for us already.
2328 */
f4998e55
GU		 2329 if (!port->uartclk) {
2330 baud = uart_get_baud_rate(port, termios, old, 0, 115200);
2331 goto done;
2332 }
1da177e4 2333
f4998e55
GU		 2334 for (i = 0; i < SCI_NUM_CLKS; i++)
2335 max_freq = max(max_freq, s->clk_rates[i]);
2336
69eee8e9 2337 baud = uart_get_baud_rate(port, termios, old, 0, max_freq / min_sr(s));
f4998e55
GU		 2338 if (!baud)
2339 goto done;
2340
2341 /*
2342 * There can be multiple sources for the sampling clock. Find the one
2343 * that gives us the smallest deviation from the desired baud rate.
2344 */
2345
6af27bf2
GU		 2346 /* Optional Undivided External Clock */
2347 if (s->clk_rates[SCI_SCK] && port->type != PORT_SCIFA &&
2348 port->type != PORT_SCIFB) {
2349 err = sci_sck_calc(s, baud, &srr1);
2350 if (abs(err) < abs(min_err)) {
2351 best_clk = SCI_SCK;
2352 scr_val = SCSCR_CKE1;
2353 sccks = SCCKS_CKS;
2354 min_err = err;
2355 srr = srr1;
2356 if (!err)
2357 goto done;
2358 }
2359 }
2360
1270f865
GU		 2361 /* Optional BRG Frequency Divided External Clock */
2362 if (s->clk_rates[SCI_SCIF_CLK] && sci_getreg(port, SCDL)->size) {
2363 err = sci_brg_calc(s, baud, s->clk_rates[SCI_SCIF_CLK], &dl1,
2364 &srr1);
2365 if (abs(err) < abs(min_err)) {
2366 best_clk = SCI_SCIF_CLK;
2367 scr_val = SCSCR_CKE1;
2368 sccks = 0;
2369 min_err = err;
2370 dl = dl1;
2371 srr = srr1;
2372 if (!err)
2373 goto done;
2374 }
2375 }
2376
2377 /* Optional BRG Frequency Divided Internal Clock */
2378 if (s->clk_rates[SCI_BRG_INT] && sci_getreg(port, SCDL)->size) {
2379 err = sci_brg_calc(s, baud, s->clk_rates[SCI_BRG_INT], &dl1,
2380 &srr1);
2381 if (abs(err) < abs(min_err)) {
2382 best_clk = SCI_BRG_INT;
2383 scr_val = SCSCR_CKE1;
2384 sccks = SCCKS_XIN;
2385 min_err = err;
2386 dl = dl1;
2387 srr = srr1;
2388 if (!min_err)
2389 goto done;
f303b364
UH		 2390 }
2391 }
e108b2ca 2392
f4998e55
GU		 2393 /* Divided Functional Clock using standard Bit Rate Register */
2394 err = sci_scbrr_calc(s, baud, &brr1, &srr1, &cks1);
2395 if (abs(err) < abs(min_err)) {
2396 best_clk = SCI_FCK;
6af27bf2 2397 scr_val = 0;
f4998e55
GU		 2398 min_err = err;
2399 brr = brr1;
2400 srr = srr1;
2401 cks = cks1;
2402 }
2403
2404done:
2405 if (best_clk >= 0)
2406 dev_dbg(port->dev, "Using clk %pC for %u%+d bps\n",
2407 s->clks[best_clk], baud, min_err);
e108b2ca 2408
23241d43 2409 sci_port_enable(s);
36003386 2410
6af27bf2
GU		 2411 /*
2412 * Program the optional External Baud Rate Generator (BRG) first.
2413 * It controls the mux to select (H)SCK or frequency divided clock.
2414 */
1270f865
GU		 2415 if (best_clk >= 0 && sci_getreg(port, SCCKS)->size) {
2416 serial_port_out(port, SCDL, dl);
6af27bf2 2417 serial_port_out(port, SCCKS, sccks);
1270f865 2418 }
1da177e4 2419
1be22663
TA		 2420 spin_lock_irqsave(&port->lock, flags);
2421
1ba76220 2422 sci_reset(port);
1da177e4
LT		 2423
2424 uart_update_timeout(port, termios->c_cflag, baud);
2425
63ba1e00
UH		 2426 /* byte size and parity */
2427 switch (termios->c_cflag & CSIZE) {
2428 case CS5:
2429 bits = 7;
2430 break;
2431 case CS6:
2432 bits = 8;
2433 break;
2434 case CS7:
2435 bits = 9;
2436 break;
2437 default:
2438 bits = 10;
2439 break;
2440 }
2441
2442 if (termios->c_cflag & CSTOPB)
2443 bits++;
2444 if (termios->c_cflag & PARENB)
2445 bits++;
2446
f4998e55 2447 if (best_clk >= 0) {
92a05748
GU		 2448 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
2449 switch (srr + 1) {
2450 case 5: smr_val |= SCSMR_SRC_5; break;
2451 case 7: smr_val |= SCSMR_SRC_7; break;
2452 case 11: smr_val |= SCSMR_SRC_11; break;
2453 case 13: smr_val |= SCSMR_SRC_13; break;
2454 case 16: smr_val |= SCSMR_SRC_16; break;
2455 case 17: smr_val |= SCSMR_SRC_17; break;
2456 case 19: smr_val |= SCSMR_SRC_19; break;
2457 case 27: smr_val |= SCSMR_SRC_27; break;
2458 }
f4998e55 2459 smr_val |= cks;
fa2abb03 2460 serial_port_out(port, SCSCR, scr_val | s->hscif_tot);
f4998e55
GU		 2461 serial_port_out(port, SCSMR, smr_val);
2462 serial_port_out(port, SCBRR, brr);
63ba1e00
UH		 2463 if (sci_getreg(port, HSSRR)->size) {
2464 unsigned int hssrr = srr | HSCIF_SRE;
2465 /* Calculate deviation from intended rate at the
2466 * center of the last stop bit in sampling clocks.
2467 */
2468 int last_stop = bits * 2 - 1;
2469 int deviation = min_err * srr * last_stop / 2 / baud;
2470
2471 if (abs(deviation) >= 2) {
2472 /* At least two sampling clocks off at the
2473 * last stop bit; we can increase the error
2474 * margin by shifting the sampling point.
2475 */
2476 int shift = min(-8, max(7, deviation / 2));
2477
2478 hssrr |= (shift << HSCIF_SRHP_SHIFT) &
2479 HSCIF_SRHP_MASK;
2480 hssrr |= HSCIF_SRDE;
2481 }
2482 serial_port_out(port, HSSRR, hssrr);
2483 }
f4998e55
GU		 2484
2485 /* Wait one bit interval */
2486 udelay((1000000 + (baud - 1)) / baud);
2487 } else {
2488 /* Don't touch the bit rate configuration */
2489 scr_val = s->cfg->scscr & (SCSCR_CKE1 | SCSCR_CKE0);
3a964abe
GU		 2490 smr_val |= serial_port_in(port, SCSMR) &
2491 (SCSMR_CKEDG | SCSMR_SRC_MASK | SCSMR_CKS);
fa2abb03 2492 serial_port_out(port, SCSCR, scr_val | s->hscif_tot);
9d482cc3 2493 serial_port_out(port, SCSMR, smr_val);
f4998e55 2494 }
1da177e4 2495
d5701647 2496 sci_init_pins(port, termios->c_cflag);
0979e0e6 2497
33f50ffc
GU		 2498 port->status &= ~UPSTAT_AUTOCTS;
2499 s->autorts = false;
73c3d53f
PM		 2500 reg = sci_getreg(port, SCFCR);
2501 if (reg->size) {
b12bb29f 2502 unsigned short ctrl = serial_port_in(port, SCFCR);
0979e0e6 2503
33f50ffc
GU		 2504 if ((port->flags & UPF_HARD_FLOW) &&
2505 (termios->c_cflag & CRTSCTS)) {
2506 /* There is no CTS interrupt to restart the hardware */
2507 port->status |= UPSTAT_AUTOCTS;
2508 /* MCE is enabled when RTS is raised */
2509 s->autorts = true;
faf02f8f 2510 }
73c3d53f
PM		 2511
2512 /*
2513 * As we've done a sci_reset() above, ensure we don't
2514 * interfere with the FIFOs while toggling MCE. As the
2515 * reset values could still be set, simply mask them out.
2516 */
2517 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST);
2518
b12bb29f 2519 serial_port_out(port, SCFCR, ctrl);
0979e0e6 2520 }
5f76895e
GU		 2521 if (port->flags & UPF_HARD_FLOW) {
2522 /* Refresh (Auto) RTS */
2523 sci_set_mctrl(port, port->mctrl);
2524 }
b7a76e4b 2525
9f8325b3
LP		 2526 scr_val |= SCSCR_RE | SCSCR_TE |
2527 (s->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0));
fa2abb03 2528 serial_port_out(port, SCSCR, scr_val | s->hscif_tot);
92a05748
GU		 2529 if ((srr + 1 == 5) &&
2530 (port->type == PORT_SCIFA || port->type == PORT_SCIFB)) {
2531 /*
2532 * In asynchronous mode, when the sampling rate is 1/5, first
2533 * received data may become invalid on some SCIFA and SCIFB.
2534 * To avoid this problem wait more than 1 serial data time (1
2535 * bit time x serial data number) after setting SCSCR.RE = 1.
2536 */
2537 udelay(DIV_ROUND_UP(10 * 1000000, baud));
2538 }
1da177e4 2539
3089f381 2540 /*
5f6d8515 2541 * Calculate delay for 2 DMA buffers (4 FIFO).
f5835c1d
GU		 2542 * See serial_core.c::uart_update_timeout().
2543 * With 10 bits (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above
2544 * function calculates 1 jiffie for the data plus 5 jiffies for the
2545 * "slop(e)." Then below we calculate 5 jiffies (20ms) for 2 DMA
2546 * buffers (4 FIFO sizes), but when performing a faster transfer, the
2547 * value obtained by this formula is too small. Therefore, if the value
2548 * is smaller than 20ms, use 20ms as the timeout value for DMA.
3089f381 2549 */
b96408b4 2550 s->rx_frame = (10000 * bits) / (baud / 100);
03940376 2551#ifdef CONFIG_SERIAL_SH_SCI_DMA
b96408b4
UH		 2552 s->rx_timeout = s->buf_len_rx * 2 * s->rx_frame;
2553 if (s->rx_timeout < 20)
2554 s->rx_timeout = 20;
3089f381
GL		 2555#endif
2556
1da177e4 2557 if ((termios->c_cflag & CREAD) != 0)
73a19e4c 2558 sci_start_rx(port);
36003386 2559
1be22663
TA		 2560 spin_unlock_irqrestore(&port->lock, flags);
2561
23241d43 2562 sci_port_disable(s);
f907c9ea
GU		 2563
2564 if (UART_ENABLE_MS(port, termios->c_cflag))
2565 sci_enable_ms(port);
1da177e4
LT		 2566}
2567
0174e5ca
TK		 2568static void sci_pm(struct uart_port *port, unsigned int state,
2569 unsigned int oldstate)
2570{
2571 struct sci_port *sci_port = to_sci_port(port);
2572
2573 switch (state) {
d3dfe5d9 2574 case UART_PM_STATE_OFF:
0174e5ca
TK		 2575 sci_port_disable(sci_port);
2576 break;
2577 default:
2578 sci_port_enable(sci_port);
2579 break;
2580 }
2581}
2582
1da177e4
LT		 2583static const char *sci_type(struct uart_port *port)
2584{
2585 switch (port->type) {
e7c98dc7
MT		 2586 case PORT_IRDA:
2587 return "irda";
2588 case PORT_SCI:
2589 return "sci";
2590 case PORT_SCIF:
2591 return "scif";
2592 case PORT_SCIFA:
2593 return "scifa";
d1d4b10c
GL		 2594 case PORT_SCIFB:
2595 return "scifb";
f303b364
UH		 2596 case PORT_HSCIF:
2597 return "hscif";
1da177e4
LT		 2598 }
2599
fa43972f 2600 return NULL;
1da177e4
LT		 2601}
2602
f6e9495d
PM		 2603static int sci_remap_port(struct uart_port *port)
2604{
e4d6f911 2605 struct sci_port *sport = to_sci_port(port);
f6e9495d
PM		 2606
2607 /*
2608 * Nothing to do if there's already an established membase.
2609 */
2610 if (port->membase)
2611 return 0;
2612
3d73f32b 2613 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) {
e4d6f911 2614 port->membase = ioremap_nocache(port->mapbase, sport->reg_size);
f6e9495d
PM		 2615 if (unlikely(!port->membase)) {
2616 dev_err(port->dev, "can't remap port#%d\n", port->line);
2617 return -ENXIO;
2618 }
2619 } else {
2620 /*
2621 * For the simple (and majority of) cases where we don't
2622 * need to do any remapping, just cast the cookie
2623 * directly.
2624 */
3af4e960 2625 port->membase = (void __iomem *)(uintptr_t)port->mapbase;
f6e9495d
PM		 2626 }
2627
2628 return 0;
2629}
2630
e2651647 2631static void sci_release_port(struct uart_port *port)
1da177e4 2632{
e4d6f911
YS		 2633 struct sci_port *sport = to_sci_port(port);
2634
3d73f32b 2635 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) {
e2651647
PM		 2636 iounmap(port->membase);
2637 port->membase = NULL;
2638 }
2639
e4d6f911 2640 release_mem_region(port->mapbase, sport->reg_size);
1da177e4
LT		 2641}
2642
e2651647 2643static int sci_request_port(struct uart_port *port)
1da177e4 2644{
e2651647 2645 struct resource *res;
e4d6f911 2646 struct sci_port *sport = to_sci_port(port);
f6e9495d 2647 int ret;
1da177e4 2648
e4d6f911
YS		 2649 res = request_mem_region(port->mapbase, sport->reg_size,
2650 dev_name(port->dev));
2651 if (unlikely(res == NULL)) {
2652 dev_err(port->dev, "request_mem_region failed.");
e2651647 2653 return -EBUSY;
e4d6f911 2654 }
1da177e4 2655
f6e9495d
PM		 2656 ret = sci_remap_port(port);
2657 if (unlikely(ret != 0)) {
2658 release_resource(res);
2659 return ret;
7ff731ae 2660 }
e2651647
PM		 2661
2662 return 0;
2663}
2664
2665static void sci_config_port(struct uart_port *port, int flags)
2666{
2667 if (flags & UART_CONFIG_TYPE) {
2668 struct sci_port *sport = to_sci_port(port);
2669
2670 port->type = sport->cfg->type;
2671 sci_request_port(port);
2672 }
1da177e4
LT		 2673}
2674
2675static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
2676{
1da177e4
LT		 2677 if (ser->baud_base < 2400)
2678 /* No paper tape reader for Mitch.. */
2679 return -EINVAL;
2680
2681 return 0;
2682}
2683
069a47e5 2684static const struct uart_ops sci_uart_ops = {
1da177e4
LT		 2685 .tx_empty = sci_tx_empty,
2686 .set_mctrl = sci_set_mctrl,
2687 .get_mctrl = sci_get_mctrl,
2688 .start_tx = sci_start_tx,
2689 .stop_tx = sci_stop_tx,
2690 .stop_rx = sci_stop_rx,
f907c9ea 2691 .enable_ms = sci_enable_ms,
1da177e4
LT		 2692 .break_ctl = sci_break_ctl,
2693 .startup = sci_startup,
2694 .shutdown = sci_shutdown,
1cf4a7ef 2695 .flush_buffer = sci_flush_buffer,
1da177e4 2696 .set_termios = sci_set_termios,
0174e5ca 2697 .pm = sci_pm,
1da177e4
LT		 2698 .type = sci_type,
2699 .release_port = sci_release_port,
2700 .request_port = sci_request_port,
2701 .config_port = sci_config_port,
2702 .verify_port = sci_verify_port,
07d2a1a1
PM		 2703#ifdef CONFIG_CONSOLE_POLL
2704 .poll_get_char = sci_poll_get_char,
2705 .poll_put_char = sci_poll_put_char,
2706#endif
1da177e4
LT		 2707};
2708
a9ec81f4
LP		 2709static int sci_init_clocks(struct sci_port *sci_port, struct device *dev)
2710{
f4998e55
GU		 2711 const char *clk_names[] = {
2712 [SCI_FCK] = "fck",
6af27bf2 2713 [SCI_SCK] = "sck",
1270f865
GU		 2714 [SCI_BRG_INT] = "brg_int",
2715 [SCI_SCIF_CLK] = "scif_clk",
f4998e55
GU		 2716 };
2717 struct clk *clk;
2718 unsigned int i;
a9ec81f4 2719
6af27bf2
GU		 2720 if (sci_port->cfg->type == PORT_HSCIF)
2721 clk_names[SCI_SCK] = "hsck";
2722
f4998e55
GU		 2723 for (i = 0; i < SCI_NUM_CLKS; i++) {
2724 clk = devm_clk_get(dev, clk_names[i]);
2725 if (PTR_ERR(clk) == -EPROBE_DEFER)
2726 return -EPROBE_DEFER;
a9ec81f4 2727
f4998e55
GU		 2728 if (IS_ERR(clk) && i == SCI_FCK) {
2729 /*
2730 * "fck" used to be called "sci_ick", and we need to
2731 * maintain DT backward compatibility.
2732 */
2733 clk = devm_clk_get(dev, "sci_ick");
2734 if (PTR_ERR(clk) == -EPROBE_DEFER)
2735 return -EPROBE_DEFER;
a9ec81f4 2736
f4998e55
GU		 2737 if (!IS_ERR(clk))
2738 goto found;
a9ec81f4 2739
f4998e55
GU		 2740 /*
2741 * Not all SH platforms declare a clock lookup entry
2742 * for SCI devices, in which case we need to get the
2743 * global "peripheral_clk" clock.
2744 */
2745 clk = devm_clk_get(dev, "peripheral_clk");
2746 if (!IS_ERR(clk))
2747 goto found;
2748
2749 dev_err(dev, "failed to get %s (%ld)\n", clk_names[i],
2750 PTR_ERR(clk));
2751 return PTR_ERR(clk);
2752 }
2753
2754found:
2755 if (IS_ERR(clk))
2756 dev_dbg(dev, "failed to get %s (%ld)\n", clk_names[i],
2757 PTR_ERR(clk));
2758 else
d63c16f8
GU		 2759 dev_dbg(dev, "clk %s is %pC rate %lu\n", clk_names[i],
2760 clk, clk_get_rate(clk));
f4998e55
GU		 2761 sci_port->clks[i] = IS_ERR(clk) ? NULL : clk;
2762 }
2763 return 0;
a9ec81f4
LP		 2764}
2765
daf5a895
LP		 2766static const struct sci_port_params *
2767sci_probe_regmap(const struct plat_sci_port *cfg)
2768{
2769 unsigned int regtype;
2770
2771 if (cfg->regtype != SCIx_PROBE_REGTYPE)
2772 return &sci_port_params[cfg->regtype];
2773
2774 switch (cfg->type) {
2775 case PORT_SCI:
2776 regtype = SCIx_SCI_REGTYPE;
2777 break;
2778 case PORT_IRDA:
2779 regtype = SCIx_IRDA_REGTYPE;
2780 break;
2781 case PORT_SCIFA:
2782 regtype = SCIx_SCIFA_REGTYPE;
2783 break;
2784 case PORT_SCIFB:
2785 regtype = SCIx_SCIFB_REGTYPE;
2786 break;
2787 case PORT_SCIF:
2788 /*
2789 * The SH-4 is a bit of a misnomer here, although that's
2790 * where this particular port layout originated. This
2791 * configuration (or some slight variation thereof)
2792 * remains the dominant model for all SCIFs.
2793 */
2794 regtype = SCIx_SH4_SCIF_REGTYPE;
2795 break;
2796 case PORT_HSCIF:
2797 regtype = SCIx_HSCIF_REGTYPE;
2798 break;
2799 default:
2800 pr_err("Can't probe register map for given port\n");
2801 return NULL;
2802 }
2803
2804 return &sci_port_params[regtype];
2805}
2806
9671f099 2807static int sci_init_single(struct platform_device *dev,
1fcc91a6 2808 struct sci_port *sci_port, unsigned int index,
daf5a895 2809 const struct plat_sci_port *p, bool early)
e108b2ca 2810{
73a19e4c 2811 struct uart_port *port = &sci_port->port;
1fcc91a6 2812 const struct resource *res;
2d4dd0da 2813 unsigned int i, regtype;
3127c6b2 2814 int ret;
e108b2ca 2815
50f0959a
PM		 2816 sci_port->cfg = p;
2817
73a19e4c
GL		 2818 port->ops = &sci_uart_ops;
2819 port->iotype = UPIO_MEM;
2820 port->line = index;
75136d48 2821
89b5c1ab
LP		 2822 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
2823 if (res == NULL)
2824 return -ENOMEM;
1fcc91a6 2825
89b5c1ab 2826 port->mapbase = res->start;
e4d6f911 2827 sci_port->reg_size = resource_size(res);
1fcc91a6 2828
89b5c1ab
LP		 2829 for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i)
2830 sci_port->irqs[i] = platform_get_irq(dev, i);
1fcc91a6 2831
89b5c1ab
LP		 2832 /* The SCI generates several interrupts. They can be muxed together or
2833 * connected to different interrupt lines. In the muxed case only one
628c534a
CB		 2834 * interrupt resource is specified as there is only one interrupt ID.
2835 * In the non-muxed case, up to 6 interrupt signals might be generated
2836 * from the SCI, however those signals might have their own individual
2837 * interrupt ID numbers, or muxed together with another interrupt.
89b5c1ab
LP		 2838 */
2839 if (sci_port->irqs[0] < 0)
2840 return -ENXIO;
1fcc91a6 2841
628c534a
CB		 2842 if (sci_port->irqs[1] < 0)
2843 for (i = 1; i < ARRAY_SIZE(sci_port->irqs); i++)
2844 sci_port->irqs[i] = sci_port->irqs[0];
1fcc91a6 2845
daf5a895
LP		 2846 sci_port->params = sci_probe_regmap(p);
2847 if (unlikely(sci_port->params == NULL))
2848 return -EINVAL;
e095ee6b 2849
2d4dd0da 2850 regtype = sci_port->params - sci_port_params;
18e8cf15
UH		 2851 switch (p->type) {
2852 case PORT_SCIFB:
2853 sci_port->rx_trigger = 48;
2854 break;
2855 case PORT_HSCIF:
2856 sci_port->rx_trigger = 64;
2857 break;
2858 case PORT_SCIFA:
2859 sci_port->rx_trigger = 32;
2860 break;
2861 case PORT_SCIF:
2862 if (p->regtype == SCIx_SH7705_SCIF_REGTYPE)
2863 /* RX triggering not implemented for this IP */
2864 sci_port->rx_trigger = 1;
2865 else
2866 sci_port->rx_trigger = 8;
2867 break;
2868 default:
2869 sci_port->rx_trigger = 1;
2870 break;
2871 }
2872
03940376 2873 sci_port->rx_fifo_timeout = 0;
fa2abb03 2874 sci_port->hscif_tot = 0;
03940376 2875
878fbb91
LP		 2876 /* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't
2877 * match the SoC datasheet, this should be investigated. Let platform
2878 * data override the sampling rate for now.
ec09c5eb 2879 */
b2f20ed9
LP		 2880 sci_port->sampling_rate_mask = p->sampling_rate
2881 ? SCI_SR(p->sampling_rate)
2882 : sci_port->params->sampling_rate_mask;
ec09c5eb 2883
1fcc91a6 2884 if (!early) {
a9ec81f4
LP		 2885 ret = sci_init_clocks(sci_port, &dev->dev);
2886 if (ret < 0)
2887 return ret;
c7ed1ab3 2888
73a19e4c 2889 port->dev = &dev->dev;
5e50d2d6
MD		 2890
2891 pm_runtime_enable(&dev->dev);
7b6fd3bf 2892 }
e108b2ca 2893
ce6738b6 2894 port->type = p->type;
3d73f32b 2895 port->flags = UPF_FIXED_PORT | UPF_BOOT_AUTOCONF | p->flags;
b2f20ed9 2896 port->fifosize = sci_port->params->fifosize;
73a19e4c 2897
dfc80387
LP		 2898 if (port->type == PORT_SCI) {
2899 if (sci_port->reg_size >= 0x20)
2900 port->regshift = 2;
2901 else
2902 port->regshift = 1;
2903 }
2904
2d4dd0da
CB		 2905 if (regtype == SCIx_SH4_SCIF_REGTYPE)
2906 if (sci_port->reg_size >= 0x20)
2907 port->regshift = 1;
2908
ce6738b6 2909 /*
61a6976b 2910 * The UART port needs an IRQ value, so we peg this to the RX IRQ
ce6738b6
PM		 2911 * for the multi-IRQ ports, which is where we are primarily
2912 * concerned with the shutdown path synchronization.
2913 *
2914 * For the muxed case there's nothing more to do.
2915 */
1fcc91a6 2916 port->irq = sci_port->irqs[SCIx_RXI_IRQ];
9cfb5c05 2917 port->irqflags = 0;
73a19e4c 2918
61a6976b
PM		 2919 port->serial_in = sci_serial_in;
2920 port->serial_out = sci_serial_out;
2921
c7ed1ab3 2922 return 0;
e108b2ca
PM		 2923}
2924
6dae1421
LP		 2925static void sci_cleanup_single(struct sci_port *port)
2926{
6dae1421
LP		 2927 pm_runtime_disable(port->port.dev);
2928}
2929
0b0cced1
YS		 2930#if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \
2931 defined(CONFIG_SERIAL_SH_SCI_EARLYCON)
dc8e6f5b
MD		 2932static void serial_console_putchar(struct uart_port *port, int ch)
2933{
2934 sci_poll_put_char(port, ch);
2935}
2936
1da177e4
LT		 2937/*
2938 * Print a string to the serial port trying not to disturb
2939 * any possible real use of the port...
2940 */
2941static void serial_console_write(struct console *co, const char *s,
2942 unsigned count)
2943{
906b17dc
PM		 2944 struct sci_port *sci_port = &sci_ports[co->index];
2945 struct uart_port *port = &sci_port->port;
a67969b5 2946 unsigned short bits, ctrl, ctrl_temp;
40f70c03
SK		 2947 unsigned long flags;
2948 int locked = 1;
2949
0b0cced1 2950#if defined(SUPPORT_SYSRQ)
40f70c03
SK		 2951 if (port->sysrq)
2952 locked = 0;
0b0cced1
YS		 2953 else
2954#endif
2955 if (oops_in_progress)
8afb1d2c 2956 locked = spin_trylock_irqsave(&port->lock, flags);
40f70c03 2957 else
8afb1d2c 2958 spin_lock_irqsave(&port->lock, flags);
40f70c03 2959
a67969b5 2960 /* first save SCSCR then disable interrupts, keep clock source */
40f70c03 2961 ctrl = serial_port_in(port, SCSCR);
9f8325b3
LP		 2962 ctrl_temp = SCSCR_RE | SCSCR_TE |
2963 (sci_port->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)) |
a67969b5 2964 (ctrl & (SCSCR_CKE1 | SCSCR_CKE0));
fa2abb03 2965 serial_port_out(port, SCSCR, ctrl_temp | sci_port->hscif_tot);
07d2a1a1 2966
501b825d 2967 uart_console_write(port, s, count, serial_console_putchar);
973e5d52
MD		 2968
2969 /* wait until fifo is empty and last bit has been transmitted */
2970 bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
b12bb29f 2971 while ((serial_port_in(port, SCxSR) & bits) != bits)
973e5d52 2972 cpu_relax();
40f70c03
SK		 2973
2974 /* restore the SCSCR */
2975 serial_port_out(port, SCSCR, ctrl);
2976
2977 if (locked)
8afb1d2c 2978 spin_unlock_irqrestore(&port->lock, flags);
1da177e4
LT		 2979}
2980
9671f099 2981static int serial_console_setup(struct console *co, char *options)
1da177e4 2982{
dc8e6f5b 2983 struct sci_port *sci_port;
1da177e4
LT		 2984 struct uart_port *port;
2985 int baud = 115200;
2986 int bits = 8;
2987 int parity = 'n';
2988 int flow = 'n';
2989 int ret;
2990
e108b2ca 2991 /*
906b17dc 2992 * Refuse to handle any bogus ports.
1da177e4 2993 */
906b17dc 2994 if (co->index < 0 || co->index >= SCI_NPORTS)
e108b2ca 2995 return -ENODEV;
e108b2ca 2996
906b17dc
PM		 2997 sci_port = &sci_ports[co->index];
2998 port = &sci_port->port;
2999
b2267a6b
AC		 3000 /*
3001 * Refuse to handle uninitialized ports.
3002 */
3003 if (!port->ops)
3004 return -ENODEV;
3005
f6e9495d
PM		 3006 ret = sci_remap_port(port);
3007 if (unlikely(ret != 0))
3008 return ret;
e108b2ca 3009
1da177e4
LT		 3010 if (options)
3011 uart_parse_options(options, &baud, &parity, &bits, &flow);
3012
ab7cfb55 3013 return uart_set_options(port, co, baud, parity, bits, flow);
1da177e4
LT		 3014}
3015
3016static struct console serial_console = {
3017 .name = "ttySC",
906b17dc 3018 .device = uart_console_device,
1da177e4
LT		 3019 .write = serial_console_write,
3020 .setup = serial_console_setup,
fa5da2f7 3021 .flags = CON_PRINTBUFFER,
1da177e4 3022 .index = -1,
906b17dc 3023 .data = &sci_uart_driver,
1da177e4
LT		 3024};
3025
7b6fd3bf
MD		 3026static struct console early_serial_console = {
3027 .name = "early_ttySC",
3028 .write = serial_console_write,
3029 .flags = CON_PRINTBUFFER,
906b17dc 3030 .index = -1,
7b6fd3bf 3031};
ecdf8a46 3032
7b6fd3bf
MD		 3033static char early_serial_buf[32];
3034
9671f099 3035static int sci_probe_earlyprintk(struct platform_device *pdev)
ecdf8a46 3036{
daf5a895 3037 const struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev);
ecdf8a46
PM		 3038
3039 if (early_serial_console.data)
3040 return -EEXIST;
3041
3042 early_serial_console.index = pdev->id;
ecdf8a46 3043
1fcc91a6 3044 sci_init_single(pdev, &sci_ports[pdev->id], pdev->id, cfg, true);
ecdf8a46
PM		 3045
3046 serial_console_setup(&early_serial_console, early_serial_buf);
3047
3048 if (!strstr(early_serial_buf, "keep"))
3049 early_serial_console.flags |= CON_BOOT;
3050
3051 register_console(&early_serial_console);
3052 return 0;
3053}
6a8c9799
NI		 3054
3055#define SCI_CONSOLE (&serial_console)
3056
ecdf8a46 3057#else
9671f099 3058static inline int sci_probe_earlyprintk(struct platform_device *pdev)
ecdf8a46
PM		 3059{
3060 return -EINVAL;
3061}
1da177e4 3062
6a8c9799
NI		 3063#define SCI_CONSOLE NULL
3064
0b0cced1 3065#endif /* CONFIG_SERIAL_SH_SCI_CONSOLE || CONFIG_SERIAL_SH_SCI_EARLYCON */
1da177e4 3066
6c13d5d2 3067static const char banner[] __initconst = "SuperH (H)SCI(F) driver initialized";
1da177e4 3068
352b9266 3069static DEFINE_MUTEX(sci_uart_registration_lock);
1da177e4
LT		 3070static struct uart_driver sci_uart_driver = {
3071 .owner = THIS_MODULE,
3072 .driver_name = "sci",
1da177e4
LT		 3073 .dev_name = "ttySC",
3074 .major = SCI_MAJOR,
3075 .minor = SCI_MINOR_START,
e108b2ca 3076 .nr = SCI_NPORTS,
1da177e4
LT		 3077 .cons = SCI_CONSOLE,
3078};
3079
54507f6e 3080static int sci_remove(struct platform_device *dev)
e552de24 3081{
d535a230 3082 struct sci_port *port = platform_get_drvdata(dev);
e552de24 3083
7678f4c2 3084 sci_ports_in_use &= ~BIT(port->port.line);
d535a230
PM		 3085 uart_remove_one_port(&sci_uart_driver, &port->port);
3086
6dae1421 3087 sci_cleanup_single(port);
e552de24 3088
5d23188a
UH		 3089 if (port->port.fifosize > 1) {
3090 sysfs_remove_file(&dev->dev.kobj,
3091 &dev_attr_rx_fifo_trigger.attr);
3092 }
fa2abb03
UH		 3093 if (port->port.type == PORT_SCIFA || port->port.type == PORT_SCIFB ||
3094 port->port.type == PORT_HSCIF) {
5d23188a
UH		 3095 sysfs_remove_file(&dev->dev.kobj,
3096 &dev_attr_rx_fifo_timeout.attr);
3097 }
3098
e552de24
MD		 3099 return 0;
3100}
3101
bd2238fb
GU		 3102
3103#define SCI_OF_DATA(type, regtype) (void *)((type) << 16 | (regtype))
3104#define SCI_OF_TYPE(data) ((unsigned long)(data) >> 16)
3105#define SCI_OF_REGTYPE(data) ((unsigned long)(data) & 0xffff)
20bdcab8
BH		 3106
3107static const struct of_device_id of_sci_match[] = {
f443ff80
GU		 3108 /* SoC-specific types */
3109 {
3110 .compatible = "renesas,scif-r7s72100",
3111 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH2_SCIF_FIFODATA_REGTYPE),
3112 },
9ed44bb2
GU		 3113 /* Family-specific types */
3114 {
3115 .compatible = "renesas,rcar-gen1-scif",
3116 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
3117 }, {
3118 .compatible = "renesas,rcar-gen2-scif",
3119 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
3120 }, {
3121 .compatible = "renesas,rcar-gen3-scif",
3122 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
3123 },
f443ff80 3124 /* Generic types */
20bdcab8
BH		 3125 {
3126 .compatible = "renesas,scif",
bd2238fb 3127 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_REGTYPE),
20bdcab8
BH		 3128 }, {
3129 .compatible = "renesas,scifa",
bd2238fb 3130 .data = SCI_OF_DATA(PORT_SCIFA, SCIx_SCIFA_REGTYPE),
20bdcab8
BH		 3131 }, {
3132 .compatible = "renesas,scifb",
bd2238fb 3133 .data = SCI_OF_DATA(PORT_SCIFB, SCIx_SCIFB_REGTYPE),
20bdcab8
BH		 3134 }, {
3135 .compatible = "renesas,hscif",
bd2238fb 3136 .data = SCI_OF_DATA(PORT_HSCIF, SCIx_HSCIF_REGTYPE),
e1d0be61
YS		 3137 }, {
3138 .compatible = "renesas,sci",
bd2238fb 3139 .data = SCI_OF_DATA(PORT_SCI, SCIx_SCI_REGTYPE),
20bdcab8
BH		 3140 }, {
3141 /* Terminator */
3142 },
3143};
3144MODULE_DEVICE_TABLE(of, of_sci_match);
3145
54b12c48
GU		 3146static struct plat_sci_port *sci_parse_dt(struct platform_device *pdev,
3147 unsigned int *dev_id)
20bdcab8
BH		 3148{
3149 struct device_node *np = pdev->dev.of_node;
20bdcab8 3150 struct plat_sci_port *p;
97ed9790 3151 struct sci_port *sp;
6e605a01 3152 const void *data;
20bdcab8
BH		 3153 int id;
3154
3155 if (!IS_ENABLED(CONFIG_OF) || !np)
3156 return NULL;
3157
6e605a01 3158 data = of_device_get_match_data(&pdev->dev);
20bdcab8 3159
20bdcab8 3160 p = devm_kzalloc(&pdev->dev, sizeof(struct plat_sci_port), GFP_KERNEL);
4205463c 3161 if (!p)
20bdcab8 3162 return NULL;
20bdcab8 3163
2095fc76 3164 /* Get the line number from the aliases node. */
20bdcab8 3165 id = of_alias_get_id(np, "serial");
7678f4c2
GU		 3166 if (id < 0 && ~sci_ports_in_use)
3167 id = ffz(sci_ports_in_use);
20bdcab8
BH		 3168 if (id < 0) {
3169 dev_err(&pdev->dev, "failed to get alias id (%d)\n", id);
3170 return NULL;
3171 }
090fa4b0
GU		 3172 if (id >= ARRAY_SIZE(sci_ports)) {
3173 dev_err(&pdev->dev, "serial%d out of range\n", id);
3174 return NULL;
3175 }
20bdcab8 3176
97ed9790 3177 sp = &sci_ports[id];
20bdcab8
BH		 3178 *dev_id = id;
3179
6e605a01
GU		 3180 p->type = SCI_OF_TYPE(data);
3181 p->regtype = SCI_OF_REGTYPE(data);
20bdcab8 3182
43c61286 3183 sp->has_rtscts = of_property_read_bool(np, "uart-has-rtscts");
861a70ab 3184
20bdcab8
BH		 3185 return p;
3186}
3187
9671f099 3188static int sci_probe_single(struct platform_device *dev,
0ee70712
MD		 3189 unsigned int index,
3190 struct plat_sci_port *p,
3191 struct sci_port *sciport)
3192{
0ee70712
MD		 3193 int ret;
3194
3195 /* Sanity check */
3196 if (unlikely(index >= SCI_NPORTS)) {
9b971cd2 3197 dev_notice(&dev->dev, "Attempting to register port %d when only %d are available\n",
0ee70712 3198 index+1, SCI_NPORTS);
9b971cd2 3199 dev_notice(&dev->dev, "Consider bumping CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
b6c5ef6f 3200 return -EINVAL;
0ee70712 3201 }
7678f4c2
GU		 3202 BUILD_BUG_ON(SCI_NPORTS > sizeof(sci_ports_in_use) * 8);
3203 if (sci_ports_in_use & BIT(index))
3204 return -EBUSY;
0ee70712 3205
352b9266
SS		 3206 mutex_lock(&sci_uart_registration_lock);
3207 if (!sci_uart_driver.state) {
3208 ret = uart_register_driver(&sci_uart_driver);
3209 if (ret) {
3210 mutex_unlock(&sci_uart_registration_lock);
3211 return ret;
3212 }
3213 }
3214 mutex_unlock(&sci_uart_registration_lock);
3215
1fcc91a6 3216 ret = sci_init_single(dev, sciport, index, p, false);
c7ed1ab3
PM		 3217 if (ret)
3218 return ret;
0ee70712 3219
f907c9ea
GU		 3220 sciport->gpios = mctrl_gpio_init(&sciport->port, 0);
3221 if (IS_ERR(sciport->gpios) && PTR_ERR(sciport->gpios) != -ENOSYS)
3222 return PTR_ERR(sciport->gpios);
3223
97ed9790 3224 if (sciport->has_rtscts) {
f907c9ea
GU		 3225 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(sciport->gpios,
3226 UART_GPIO_CTS)) ||
3227 !IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(sciport->gpios,
3228 UART_GPIO_RTS))) {
3229 dev_err(&dev->dev, "Conflicting RTS/CTS config\n");
3230 return -EINVAL;
3231 }
33f50ffc 3232 sciport->port.flags |= UPF_HARD_FLOW;
f907c9ea
GU		 3233 }
3234
6dae1421
LP		 3235 ret = uart_add_one_port(&sci_uart_driver, &sciport->port);
3236 if (ret) {
3237 sci_cleanup_single(sciport);
3238 return ret;
3239 }
3240
3241 return 0;
0ee70712
MD		 3242}
3243
9671f099 3244static int sci_probe(struct platform_device *dev)
1da177e4 3245{
20bdcab8
BH		 3246 struct plat_sci_port *p;
3247 struct sci_port *sp;
3248 unsigned int dev_id;
ecdf8a46 3249 int ret;
d535a230 3250
ecdf8a46
PM		 3251 /*
3252 * If we've come here via earlyprintk initialization, head off to
3253 * the special early probe. We don't have sufficient device state
3254 * to make it beyond this yet.
3255 */
3256 if (is_early_platform_device(dev))
3257 return sci_probe_earlyprintk(dev);
7b6fd3bf 3258
20bdcab8
BH		 3259 if (dev->dev.of_node) {
3260 p = sci_parse_dt(dev, &dev_id);
3261 if (p == NULL)
3262 return -EINVAL;
3263 } else {
3264 p = dev->dev.platform_data;
3265 if (p == NULL) {
3266 dev_err(&dev->dev, "no platform data supplied\n");
3267 return -EINVAL;
3268 }
3269
3270 dev_id = dev->id;
3271 }
3272
3273 sp = &sci_ports[dev_id];
d535a230 3274 platform_set_drvdata(dev, sp);
e552de24 3275
20bdcab8 3276 ret = sci_probe_single(dev, dev_id, p, sp);
d535a230 3277 if (ret)
6dae1421 3278 return ret;
e552de24 3279
5d23188a
UH		 3280 if (sp->port.fifosize > 1) {
3281 ret = sysfs_create_file(&dev->dev.kobj,
3282 &dev_attr_rx_fifo_trigger.attr);
3283 if (ret)
3284 return ret;
3285 }
fa2abb03
UH		 3286 if (sp->port.type == PORT_SCIFA || sp->port.type == PORT_SCIFB ||
3287 sp->port.type == PORT_HSCIF) {
5d23188a
UH		 3288 ret = sysfs_create_file(&dev->dev.kobj,
3289 &dev_attr_rx_fifo_timeout.attr);
3290 if (ret) {
3291 if (sp->port.fifosize > 1) {
3292 sysfs_remove_file(&dev->dev.kobj,
3293 &dev_attr_rx_fifo_trigger.attr);
3294 }
3295 return ret;
3296 }
3297 }
3298
1da177e4
LT		 3299#ifdef CONFIG_SH_STANDARD_BIOS
3300 sh_bios_gdb_detach();
3301#endif
3302
7678f4c2 3303 sci_ports_in_use |= BIT(dev_id);
e108b2ca 3304 return 0;
1da177e4
LT		 3305}
3306
cb876341 3307static __maybe_unused int sci_suspend(struct device *dev)
1da177e4 3308{
d535a230 3309 struct sci_port *sport = dev_get_drvdata(dev);
e108b2ca 3310
d535a230
PM		 3311 if (sport)
3312 uart_suspend_port(&sci_uart_driver, &sport->port);
1da177e4 3313
e108b2ca
PM		 3314 return 0;
3315}
1da177e4 3316
cb876341 3317static __maybe_unused int sci_resume(struct device *dev)
e108b2ca 3318{
d535a230 3319 struct sci_port *sport = dev_get_drvdata(dev);
e108b2ca 3320
d535a230
PM		 3321 if (sport)
3322 uart_resume_port(&sci_uart_driver, &sport->port);
e108b2ca
PM		 3323
3324 return 0;
3325}
3326
cb876341 3327static SIMPLE_DEV_PM_OPS(sci_dev_pm_ops, sci_suspend, sci_resume);
6daa79b3 3328
e108b2ca
PM		 3329static struct platform_driver sci_driver = {
3330 .probe = sci_probe,
b9e39c89 3331 .remove = sci_remove,
e108b2ca
PM		 3332 .driver = {
3333 .name = "sh-sci",
6daa79b3 3334 .pm = &sci_dev_pm_ops,
20bdcab8 3335 .of_match_table = of_match_ptr(of_sci_match),
e108b2ca
PM		 3336 },
3337};
3338
3339static int __init sci_init(void)
3340{
6c13d5d2 3341 pr_info("%s\n", banner);
e108b2ca 3342
352b9266 3343 return platform_driver_register(&sci_driver);
e108b2ca
PM		 3344}
3345
3346static void __exit sci_exit(void)
3347{
3348 platform_driver_unregister(&sci_driver);
352b9266
SS		 3349
3350 if (sci_uart_driver.state)
3351 uart_unregister_driver(&sci_uart_driver);
1da177e4
LT		 3352}
3353
7b6fd3bf
MD		 3354#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
3355early_platform_init_buffer("earlyprintk", &sci_driver,
3356 early_serial_buf, ARRAY_SIZE(early_serial_buf));
3357#endif
0b0cced1 3358#ifdef CONFIG_SERIAL_SH_SCI_EARLYCON
dd076cff 3359static struct plat_sci_port port_cfg __initdata;
0b0cced1
YS		 3360
3361static int __init early_console_setup(struct earlycon_device *device,
3362 int type)
3363{
3364 if (!device->port.membase)
3365 return -ENODEV;
3366
3367 device->port.serial_in = sci_serial_in;
3368 device->port.serial_out = sci_serial_out;
3369 device->port.type = type;
3370 memcpy(&sci_ports[0].port, &device->port, sizeof(struct uart_port));
daf5a895 3371 port_cfg.type = type;
0b0cced1 3372 sci_ports[0].cfg = &port_cfg;
daf5a895 3373 sci_ports[0].params = sci_probe_regmap(&port_cfg);
9f8325b3
LP		 3374 port_cfg.scscr = sci_serial_in(&sci_ports[0].port, SCSCR);
3375 sci_serial_out(&sci_ports[0].port, SCSCR,
3376 SCSCR_RE | SCSCR_TE | port_cfg.scscr);
0b0cced1
YS		 3377
3378 device->con->write = serial_console_write;
3379 return 0;
3380}
3381static int __init sci_early_console_setup(struct earlycon_device *device,
3382 const char *opt)
3383{
3384 return early_console_setup(device, PORT_SCI);
3385}
3386static int __init scif_early_console_setup(struct earlycon_device *device,
3387 const char *opt)
3388{
3389 return early_console_setup(device, PORT_SCIF);
3390}
3391static int __init scifa_early_console_setup(struct earlycon_device *device,
3392 const char *opt)
3393{
3394 return early_console_setup(device, PORT_SCIFA);
3395}
3396static int __init scifb_early_console_setup(struct earlycon_device *device,
3397 const char *opt)
3398{
3399 return early_console_setup(device, PORT_SCIFB);
3400}
3401static int __init hscif_early_console_setup(struct earlycon_device *device,
3402 const char *opt)
3403{
3404 return early_console_setup(device, PORT_HSCIF);
3405}
3406
0b0cced1 3407OF_EARLYCON_DECLARE(sci, "renesas,sci", sci_early_console_setup);
0b0cced1 3408OF_EARLYCON_DECLARE(scif, "renesas,scif", scif_early_console_setup);
0b0cced1 3409OF_EARLYCON_DECLARE(scifa, "renesas,scifa", scifa_early_console_setup);
0b0cced1 3410OF_EARLYCON_DECLARE(scifb, "renesas,scifb", scifb_early_console_setup);
0b0cced1
YS		 3411OF_EARLYCON_DECLARE(hscif, "renesas,hscif", hscif_early_console_setup);
3412#endif /* CONFIG_SERIAL_SH_SCI_EARLYCON */
3413
1da177e4
LT		 3414module_init(sci_init);
3415module_exit(sci_exit);
3416
e108b2ca 3417MODULE_LICENSE("GPL");
e169c139 3418MODULE_ALIAS("platform:sh-sci");
7f405f9c 3419MODULE_AUTHOR("Paul Mundt");
f303b364 3420MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver");
Linux 6.x block layer and io_uring tree(s)