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clk: h8300: fix error handling in h8s2678_pll_clk_setup()
[linux-block.git] / drivers / tty / serial / sh-sci.c
CommitLineData
1da177e4 1/*
1da177e4
LT		 2 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
3 *
f43dc23d 4 * Copyright (C) 2002 - 2011 Paul Mundt
3ea6bc3d 5 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
1da177e4
LT		 6 *
7 * based off of the old drivers/char/sh-sci.c by:
8 *
9 * Copyright (C) 1999, 2000 Niibe Yutaka
10 * Copyright (C) 2000 Sugioka Toshinobu
11 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
12 * Modified to support SecureEdge. David McCullough (2002)
13 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
d89ddd1c 14 * Removed SH7300 support (Jul 2007).
1da177e4
LT		 15 *
16 * This file is subject to the terms and conditions of the GNU General Public
17 * License. See the file "COPYING" in the main directory of this archive
18 * for more details.
19 */
0b3d4ef6
PM		 20#if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
21#define SUPPORT_SYSRQ
22#endif
1da177e4
LT		 23
24#undef DEBUG
25
8fb9631c
LP		 26#include <linux/clk.h>
27#include <linux/console.h>
28#include <linux/ctype.h>
29#include <linux/cpufreq.h>
30#include <linux/delay.h>
31#include <linux/dmaengine.h>
32#include <linux/dma-mapping.h>
33#include <linux/err.h>
1da177e4 34#include <linux/errno.h>
8fb9631c 35#include <linux/init.h>
1da177e4 36#include <linux/interrupt.h>
1da177e4 37#include <linux/ioport.h>
8fb9631c
LP		 38#include <linux/major.h>
39#include <linux/module.h>
1da177e4 40#include <linux/mm.h>
1da177e4 41#include <linux/notifier.h>
20bdcab8 42#include <linux/of.h>
8fb9631c 43#include <linux/platform_device.h>
5e50d2d6 44#include <linux/pm_runtime.h>
73a19e4c 45#include <linux/scatterlist.h>
8fb9631c
LP		 46#include <linux/serial.h>
47#include <linux/serial_sci.h>
48#include <linux/sh_dma.h>
5a0e3ad6 49#include <linux/slab.h>
8fb9631c
LP		 50#include <linux/string.h>
51#include <linux/sysrq.h>
52#include <linux/timer.h>
53#include <linux/tty.h>
54#include <linux/tty_flip.h>
85f094ec
PM		 55
56#ifdef CONFIG_SUPERH
1da177e4
LT		 57#include <asm/sh_bios.h>
58#endif
59
1da177e4
LT		 60#include "sh-sci.h"
61
89b5c1ab
LP		 62/* Offsets into the sci_port->irqs array */
63enum {
64 SCIx_ERI_IRQ,
65 SCIx_RXI_IRQ,
66 SCIx_TXI_IRQ,
67 SCIx_BRI_IRQ,
68 SCIx_NR_IRQS,
69
70 SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */
71};
72
73#define SCIx_IRQ_IS_MUXED(port) \
74 ((port)->irqs[SCIx_ERI_IRQ] == \
75 (port)->irqs[SCIx_RXI_IRQ]) || \
76 ((port)->irqs[SCIx_ERI_IRQ] && \
77 ((port)->irqs[SCIx_RXI_IRQ] < 0))
78
e108b2ca
PM		 79struct sci_port {
80 struct uart_port port;
81
ce6738b6
PM		 82 /* Platform configuration */
83 struct plat_sci_port *cfg;
3ae988d9
LP		 84 int overrun_bit;
85 unsigned int error_mask;
ec09c5eb 86 unsigned int sampling_rate;
3ae988d9 87
e108b2ca 88
e108b2ca
PM		 89 /* Break timer */
90 struct timer_list break_timer;
91 int break_flag;
1534a3b3 92
501b825d
MD		 93 /* Interface clock */
94 struct clk *iclk;
c7ed1ab3
PM		 95 /* Function clock */
96 struct clk *fclk;
edad1f20 97
1fcc91a6 98 int irqs[SCIx_NR_IRQS];
9174fc8f
PM		 99 char *irqstr[SCIx_NR_IRQS];
100
73a19e4c
GL		 101 struct dma_chan *chan_tx;
102 struct dma_chan *chan_rx;
f43dc23d 103
73a19e4c 104#ifdef CONFIG_SERIAL_SH_SCI_DMA
73a19e4c
GL		 105 struct dma_async_tx_descriptor *desc_tx;
106 struct dma_async_tx_descriptor *desc_rx[2];
107 dma_cookie_t cookie_tx;
108 dma_cookie_t cookie_rx[2];
109 dma_cookie_t active_rx;
110 struct scatterlist sg_tx;
111 unsigned int sg_len_tx;
112 struct scatterlist sg_rx[2];
113 size_t buf_len_rx;
114 struct sh_dmae_slave param_tx;
115 struct sh_dmae_slave param_rx;
116 struct work_struct work_tx;
117 struct work_struct work_rx;
118 struct timer_list rx_timer;
3089f381 119 unsigned int rx_timeout;
73a19e4c 120#endif
e552de24 121
d535a230 122 struct notifier_block freq_transition;
e108b2ca
PM		 123};
124
1da177e4 125/* Function prototypes */
d535a230 126static void sci_start_tx(struct uart_port *port);
b129a8cc 127static void sci_stop_tx(struct uart_port *port);
d535a230 128static void sci_start_rx(struct uart_port *port);
1da177e4 129
e108b2ca 130#define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
b7a76e4b 131
e108b2ca
PM		 132static struct sci_port sci_ports[SCI_NPORTS];
133static struct uart_driver sci_uart_driver;
1da177e4 134
e7c98dc7
MT		 135static inline struct sci_port *
136to_sci_port(struct uart_port *uart)
137{
138 return container_of(uart, struct sci_port, port);
139}
140
61a6976b
PM		 141struct plat_sci_reg {
142 u8 offset, size;
143};
144
145/* Helper for invalidating specific entries of an inherited map. */
146#define sci_reg_invalid { .offset = 0, .size = 0 }
147
148static struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = {
149 [SCIx_PROBE_REGTYPE] = {
150 [0 ... SCIx_NR_REGS - 1] = sci_reg_invalid,
151 },
152
153 /*
154 * Common SCI definitions, dependent on the port's regshift
155 * value.
156 */
157 [SCIx_SCI_REGTYPE] = {
158 [SCSMR] = { 0x00, 8 },
159 [SCBRR] = { 0x01, 8 },
160 [SCSCR] = { 0x02, 8 },
161 [SCxTDR] = { 0x03, 8 },
162 [SCxSR] = { 0x04, 8 },
163 [SCxRDR] = { 0x05, 8 },
164 [SCFCR] = sci_reg_invalid,
165 [SCFDR] = sci_reg_invalid,
166 [SCTFDR] = sci_reg_invalid,
167 [SCRFDR] = sci_reg_invalid,
168 [SCSPTR] = sci_reg_invalid,
169 [SCLSR] = sci_reg_invalid,
f303b364 170 [HSSRR] = sci_reg_invalid,
61a6976b
PM		 171 },
172
173 /*
174 * Common definitions for legacy IrDA ports, dependent on
175 * regshift value.
176 */
177 [SCIx_IRDA_REGTYPE] = {
178 [SCSMR] = { 0x00, 8 },
179 [SCBRR] = { 0x01, 8 },
180 [SCSCR] = { 0x02, 8 },
181 [SCxTDR] = { 0x03, 8 },
182 [SCxSR] = { 0x04, 8 },
183 [SCxRDR] = { 0x05, 8 },
184 [SCFCR] = { 0x06, 8 },
185 [SCFDR] = { 0x07, 16 },
186 [SCTFDR] = sci_reg_invalid,
187 [SCRFDR] = sci_reg_invalid,
188 [SCSPTR] = sci_reg_invalid,
189 [SCLSR] = sci_reg_invalid,
f303b364 190 [HSSRR] = sci_reg_invalid,
61a6976b
PM		 191 },
192
193 /*
194 * Common SCIFA definitions.
195 */
196 [SCIx_SCIFA_REGTYPE] = {
197 [SCSMR] = { 0x00, 16 },
198 [SCBRR] = { 0x04, 8 },
199 [SCSCR] = { 0x08, 16 },
200 [SCxTDR] = { 0x20, 8 },
201 [SCxSR] = { 0x14, 16 },
202 [SCxRDR] = { 0x24, 8 },
203 [SCFCR] = { 0x18, 16 },
204 [SCFDR] = { 0x1c, 16 },
205 [SCTFDR] = sci_reg_invalid,
206 [SCRFDR] = sci_reg_invalid,
207 [SCSPTR] = sci_reg_invalid,
208 [SCLSR] = sci_reg_invalid,
f303b364 209 [HSSRR] = sci_reg_invalid,
61a6976b
PM		 210 },
211
212 /*
213 * Common SCIFB definitions.
214 */
215 [SCIx_SCIFB_REGTYPE] = {
216 [SCSMR] = { 0x00, 16 },
217 [SCBRR] = { 0x04, 8 },
218 [SCSCR] = { 0x08, 16 },
219 [SCxTDR] = { 0x40, 8 },
220 [SCxSR] = { 0x14, 16 },
221 [SCxRDR] = { 0x60, 8 },
222 [SCFCR] = { 0x18, 16 },
8c66d6d2
TY		 223 [SCFDR] = sci_reg_invalid,
224 [SCTFDR] = { 0x38, 16 },
225 [SCRFDR] = { 0x3c, 16 },
61a6976b
PM		 226 [SCSPTR] = sci_reg_invalid,
227 [SCLSR] = sci_reg_invalid,
f303b364 228 [HSSRR] = sci_reg_invalid,
61a6976b
PM		 229 },
230
3af1f8a4
PE		 231 /*
232 * Common SH-2(A) SCIF definitions for ports with FIFO data
233 * count registers.
234 */
235 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = {
236 [SCSMR] = { 0x00, 16 },
237 [SCBRR] = { 0x04, 8 },
238 [SCSCR] = { 0x08, 16 },
239 [SCxTDR] = { 0x0c, 8 },
240 [SCxSR] = { 0x10, 16 },
241 [SCxRDR] = { 0x14, 8 },
242 [SCFCR] = { 0x18, 16 },
243 [SCFDR] = { 0x1c, 16 },
244 [SCTFDR] = sci_reg_invalid,
245 [SCRFDR] = sci_reg_invalid,
246 [SCSPTR] = { 0x20, 16 },
247 [SCLSR] = { 0x24, 16 },
f303b364 248 [HSSRR] = sci_reg_invalid,
3af1f8a4
PE		 249 },
250
61a6976b
PM		 251 /*
252 * Common SH-3 SCIF definitions.
253 */
254 [SCIx_SH3_SCIF_REGTYPE] = {
255 [SCSMR] = { 0x00, 8 },
256 [SCBRR] = { 0x02, 8 },
257 [SCSCR] = { 0x04, 8 },
258 [SCxTDR] = { 0x06, 8 },
259 [SCxSR] = { 0x08, 16 },
260 [SCxRDR] = { 0x0a, 8 },
261 [SCFCR] = { 0x0c, 8 },
262 [SCFDR] = { 0x0e, 16 },
263 [SCTFDR] = sci_reg_invalid,
264 [SCRFDR] = sci_reg_invalid,
265 [SCSPTR] = sci_reg_invalid,
266 [SCLSR] = sci_reg_invalid,
f303b364 267 [HSSRR] = sci_reg_invalid,
61a6976b
PM		 268 },
269
270 /*
271 * Common SH-4(A) SCIF(B) definitions.
272 */
273 [SCIx_SH4_SCIF_REGTYPE] = {
274 [SCSMR] = { 0x00, 16 },
275 [SCBRR] = { 0x04, 8 },
276 [SCSCR] = { 0x08, 16 },
277 [SCxTDR] = { 0x0c, 8 },
278 [SCxSR] = { 0x10, 16 },
279 [SCxRDR] = { 0x14, 8 },
280 [SCFCR] = { 0x18, 16 },
281 [SCFDR] = { 0x1c, 16 },
282 [SCTFDR] = sci_reg_invalid,
283 [SCRFDR] = sci_reg_invalid,
284 [SCSPTR] = { 0x20, 16 },
285 [SCLSR] = { 0x24, 16 },
f303b364
UH		 286 [HSSRR] = sci_reg_invalid,
287 },
288
289 /*
290 * Common HSCIF definitions.
291 */
292 [SCIx_HSCIF_REGTYPE] = {
293 [SCSMR] = { 0x00, 16 },
294 [SCBRR] = { 0x04, 8 },
295 [SCSCR] = { 0x08, 16 },
296 [SCxTDR] = { 0x0c, 8 },
297 [SCxSR] = { 0x10, 16 },
298 [SCxRDR] = { 0x14, 8 },
299 [SCFCR] = { 0x18, 16 },
300 [SCFDR] = { 0x1c, 16 },
301 [SCTFDR] = sci_reg_invalid,
302 [SCRFDR] = sci_reg_invalid,
303 [SCSPTR] = { 0x20, 16 },
304 [SCLSR] = { 0x24, 16 },
305 [HSSRR] = { 0x40, 16 },
61a6976b
PM		 306 },
307
308 /*
309 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR
310 * register.
311 */
312 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = {
313 [SCSMR] = { 0x00, 16 },
314 [SCBRR] = { 0x04, 8 },
315 [SCSCR] = { 0x08, 16 },
316 [SCxTDR] = { 0x0c, 8 },
317 [SCxSR] = { 0x10, 16 },
318 [SCxRDR] = { 0x14, 8 },
319 [SCFCR] = { 0x18, 16 },
320 [SCFDR] = { 0x1c, 16 },
321 [SCTFDR] = sci_reg_invalid,
322 [SCRFDR] = sci_reg_invalid,
323 [SCSPTR] = sci_reg_invalid,
324 [SCLSR] = { 0x24, 16 },
f303b364 325 [HSSRR] = sci_reg_invalid,
61a6976b
PM		 326 },
327
328 /*
329 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data
330 * count registers.
331 */
332 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = {
333 [SCSMR] = { 0x00, 16 },
334 [SCBRR] = { 0x04, 8 },
335 [SCSCR] = { 0x08, 16 },
336 [SCxTDR] = { 0x0c, 8 },
337 [SCxSR] = { 0x10, 16 },
338 [SCxRDR] = { 0x14, 8 },
339 [SCFCR] = { 0x18, 16 },
340 [SCFDR] = { 0x1c, 16 },
341 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */
342 [SCRFDR] = { 0x20, 16 },
343 [SCSPTR] = { 0x24, 16 },
344 [SCLSR] = { 0x28, 16 },
f303b364 345 [HSSRR] = sci_reg_invalid,
61a6976b
PM		 346 },
347
348 /*
349 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR
350 * registers.
351 */
352 [SCIx_SH7705_SCIF_REGTYPE] = {
353 [SCSMR] = { 0x00, 16 },
354 [SCBRR] = { 0x04, 8 },
355 [SCSCR] = { 0x08, 16 },
356 [SCxTDR] = { 0x20, 8 },
357 [SCxSR] = { 0x14, 16 },
358 [SCxRDR] = { 0x24, 8 },
359 [SCFCR] = { 0x18, 16 },
360 [SCFDR] = { 0x1c, 16 },
361 [SCTFDR] = sci_reg_invalid,
362 [SCRFDR] = sci_reg_invalid,
363 [SCSPTR] = sci_reg_invalid,
364 [SCLSR] = sci_reg_invalid,
f303b364 365 [HSSRR] = sci_reg_invalid,
61a6976b
PM		 366 },
367};
368
72b294cf
PM		 369#define sci_getreg(up, offset) (sci_regmap[to_sci_port(up)->cfg->regtype] + offset)
370
61a6976b
PM		 371/*
372 * The "offset" here is rather misleading, in that it refers to an enum
373 * value relative to the port mapping rather than the fixed offset
374 * itself, which needs to be manually retrieved from the platform's
375 * register map for the given port.
376 */
377static unsigned int sci_serial_in(struct uart_port *p, int offset)
378{
72b294cf 379 struct plat_sci_reg *reg = sci_getreg(p, offset);
61a6976b
PM		 380
381 if (reg->size == 8)
382 return ioread8(p->membase + (reg->offset << p->regshift));
383 else if (reg->size == 16)
384 return ioread16(p->membase + (reg->offset << p->regshift));
385 else
386 WARN(1, "Invalid register access\n");
387
388 return 0;
389}
390
391static void sci_serial_out(struct uart_port *p, int offset, int value)
392{
72b294cf 393 struct plat_sci_reg *reg = sci_getreg(p, offset);
61a6976b
PM		 394
395 if (reg->size == 8)
396 iowrite8(value, p->membase + (reg->offset << p->regshift));
397 else if (reg->size == 16)
398 iowrite16(value, p->membase + (reg->offset << p->regshift));
399 else
400 WARN(1, "Invalid register access\n");
401}
402
61a6976b
PM		 403static int sci_probe_regmap(struct plat_sci_port *cfg)
404{
405 switch (cfg->type) {
406 case PORT_SCI:
407 cfg->regtype = SCIx_SCI_REGTYPE;
408 break;
409 case PORT_IRDA:
410 cfg->regtype = SCIx_IRDA_REGTYPE;
411 break;
412 case PORT_SCIFA:
413 cfg->regtype = SCIx_SCIFA_REGTYPE;
414 break;
415 case PORT_SCIFB:
416 cfg->regtype = SCIx_SCIFB_REGTYPE;
417 break;
418 case PORT_SCIF:
419 /*
420 * The SH-4 is a bit of a misnomer here, although that's
421 * where this particular port layout originated. This
422 * configuration (or some slight variation thereof)
423 * remains the dominant model for all SCIFs.
424 */
425 cfg->regtype = SCIx_SH4_SCIF_REGTYPE;
426 break;
f303b364
UH		 427 case PORT_HSCIF:
428 cfg->regtype = SCIx_HSCIF_REGTYPE;
429 break;
61a6976b 430 default:
6c13d5d2 431 pr_err("Can't probe register map for given port\n");
61a6976b
PM		 432 return -EINVAL;
433 }
434
435 return 0;
436}
437
23241d43
PM		 438static void sci_port_enable(struct sci_port *sci_port)
439{
440 if (!sci_port->port.dev)
441 return;
442
443 pm_runtime_get_sync(sci_port->port.dev);
444
b016b646 445 clk_prepare_enable(sci_port->iclk);
23241d43 446 sci_port->port.uartclk = clk_get_rate(sci_port->iclk);
b016b646 447 clk_prepare_enable(sci_port->fclk);
23241d43
PM		 448}
449
450static void sci_port_disable(struct sci_port *sci_port)
451{
452 if (!sci_port->port.dev)
453 return;
454
caec7038
LP		 455 /* Cancel the break timer to ensure that the timer handler will not try
456 * to access the hardware with clocks and power disabled. Reset the
457 * break flag to make the break debouncing state machine ready for the
458 * next break.
459 */
460 del_timer_sync(&sci_port->break_timer);
461 sci_port->break_flag = 0;
462
b016b646
LP		 463 clk_disable_unprepare(sci_port->fclk);
464 clk_disable_unprepare(sci_port->iclk);
23241d43
PM		 465
466 pm_runtime_put_sync(sci_port->port.dev);
467}
468
07d2a1a1 469#if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
1f6fd5c9
PM		 470
471#ifdef CONFIG_CONSOLE_POLL
07d2a1a1 472static int sci_poll_get_char(struct uart_port *port)
1da177e4 473{
1da177e4
LT		 474 unsigned short status;
475 int c;
476
e108b2ca 477 do {
b12bb29f 478 status = serial_port_in(port, SCxSR);
1da177e4 479 if (status & SCxSR_ERRORS(port)) {
b12bb29f 480 serial_port_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
1da177e4
LT		 481 continue;
482 }
3f255eb3
JW		 483 break;
484 } while (1);
485
486 if (!(status & SCxSR_RDxF(port)))
487 return NO_POLL_CHAR;
07d2a1a1 488
b12bb29f 489 c = serial_port_in(port, SCxRDR);
07d2a1a1 490
e7c98dc7 491 /* Dummy read */
b12bb29f
PM		 492 serial_port_in(port, SCxSR);
493 serial_port_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
1da177e4
LT		 494
495 return c;
496}
1f6fd5c9 497#endif
1da177e4 498
07d2a1a1 499static void sci_poll_put_char(struct uart_port *port, unsigned char c)
1da177e4 500{
1da177e4
LT		 501 unsigned short status;
502
1da177e4 503 do {
b12bb29f 504 status = serial_port_in(port, SCxSR);
1da177e4
LT		 505 } while (!(status & SCxSR_TDxE(port)));
506
b12bb29f
PM		 507 serial_port_out(port, SCxTDR, c);
508 serial_port_out(port, SCxSR, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
1da177e4 509}
07d2a1a1 510#endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE */
1da177e4 511
61a6976b 512static void sci_init_pins(struct uart_port *port, unsigned int cflag)
1da177e4 513{
61a6976b
PM		 514 struct sci_port *s = to_sci_port(port);
515 struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR;
1da177e4 516
61a6976b
PM		 517 /*
518 * Use port-specific handler if provided.
519 */
520 if (s->cfg->ops && s->cfg->ops->init_pins) {
521 s->cfg->ops->init_pins(port, cflag);
522 return;
1da177e4 523 }
41504c39 524
61a6976b
PM		 525 /*
526 * For the generic path SCSPTR is necessary. Bail out if that's
527 * unavailable, too.
528 */
529 if (!reg->size)
530 return;
41504c39 531
faf02f8f
PM		 532 if ((s->cfg->capabilities & SCIx_HAVE_RTSCTS) &&
533 ((!(cflag & CRTSCTS)))) {
534 unsigned short status;
535
b12bb29f 536 status = serial_port_in(port, SCSPTR);
faf02f8f
PM		 537 status &= ~SCSPTR_CTSIO;
538 status |= SCSPTR_RTSIO;
b12bb29f 539 serial_port_out(port, SCSPTR, status); /* Set RTS = 1 */
faf02f8f 540 }
d5701647 541}
e108b2ca 542
72b294cf 543static int sci_txfill(struct uart_port *port)
e108b2ca 544{
72b294cf 545 struct plat_sci_reg *reg;
e108b2ca 546
72b294cf
PM		 547 reg = sci_getreg(port, SCTFDR);
548 if (reg->size)
63f7ad11 549 return serial_port_in(port, SCTFDR) & ((port->fifosize << 1) - 1);
c63847a3 550
72b294cf
PM		 551 reg = sci_getreg(port, SCFDR);
552 if (reg->size)
b12bb29f 553 return serial_port_in(port, SCFDR) >> 8;
d1d4b10c 554
b12bb29f 555 return !(serial_port_in(port, SCxSR) & SCI_TDRE);
e108b2ca
PM		 556}
557
73a19e4c
GL		 558static int sci_txroom(struct uart_port *port)
559{
72b294cf 560 return port->fifosize - sci_txfill(port);
73a19e4c
GL		 561}
562
563static int sci_rxfill(struct uart_port *port)
e108b2ca 564{
72b294cf
PM		 565 struct plat_sci_reg *reg;
566
567 reg = sci_getreg(port, SCRFDR);
568 if (reg->size)
63f7ad11 569 return serial_port_in(port, SCRFDR) & ((port->fifosize << 1) - 1);
72b294cf
PM		 570
571 reg = sci_getreg(port, SCFDR);
572 if (reg->size)
b12bb29f 573 return serial_port_in(port, SCFDR) & ((port->fifosize << 1) - 1);
72b294cf 574
b12bb29f 575 return (serial_port_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
e108b2ca
PM		 576}
577
514820eb
PM		 578/*
579 * SCI helper for checking the state of the muxed port/RXD pins.
580 */
581static inline int sci_rxd_in(struct uart_port *port)
582{
583 struct sci_port *s = to_sci_port(port);
584
585 if (s->cfg->port_reg <= 0)
586 return 1;
587
0dd4d5cb 588 /* Cast for ARM damage */
e2afca69 589 return !!__raw_readb((void __iomem *)(uintptr_t)s->cfg->port_reg);
514820eb
PM		 590}
591
1da177e4
LT		 592/* ********************************************************************** *
593 * the interrupt related routines *
594 * ********************************************************************** */
595
596static void sci_transmit_chars(struct uart_port *port)
597{
ebd2c8f6 598 struct circ_buf *xmit = &port->state->xmit;
1da177e4 599 unsigned int stopped = uart_tx_stopped(port);
1da177e4
LT		 600 unsigned short status;
601 unsigned short ctrl;
e108b2ca 602 int count;
1da177e4 603
b12bb29f 604 status = serial_port_in(port, SCxSR);
1da177e4 605 if (!(status & SCxSR_TDxE(port))) {
b12bb29f 606 ctrl = serial_port_in(port, SCSCR);
e7c98dc7 607 if (uart_circ_empty(xmit))
8e698614 608 ctrl &= ~SCSCR_TIE;
e7c98dc7 609 else
8e698614 610 ctrl |= SCSCR_TIE;
b12bb29f 611 serial_port_out(port, SCSCR, ctrl);
1da177e4
LT		 612 return;
613 }
614
72b294cf 615 count = sci_txroom(port);
1da177e4
LT		 616
617 do {
618 unsigned char c;
619
620 if (port->x_char) {
621 c = port->x_char;
622 port->x_char = 0;
623 } else if (!uart_circ_empty(xmit) && !stopped) {
624 c = xmit->buf[xmit->tail];
625 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
626 } else {
627 break;
628 }
629
b12bb29f 630 serial_port_out(port, SCxTDR, c);
1da177e4
LT		 631
632 port->icount.tx++;
633 } while (--count > 0);
634
b12bb29f 635 serial_port_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
1da177e4
LT		 636
637 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
638 uart_write_wakeup(port);
639 if (uart_circ_empty(xmit)) {
b129a8cc 640 sci_stop_tx(port);
1da177e4 641 } else {
b12bb29f 642 ctrl = serial_port_in(port, SCSCR);
1da177e4 643
1a22f08d 644 if (port->type != PORT_SCI) {
b12bb29f
PM		 645 serial_port_in(port, SCxSR); /* Dummy read */
646 serial_port_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
1da177e4 647 }
1da177e4 648
8e698614 649 ctrl |= SCSCR_TIE;
b12bb29f 650 serial_port_out(port, SCSCR, ctrl);
1da177e4
LT		 651 }
652}
653
654/* On SH3, SCIF may read end-of-break as a space->mark char */
e7c98dc7 655#define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); })
1da177e4 656
94c8b6db 657static void sci_receive_chars(struct uart_port *port)
1da177e4 658{
e7c98dc7 659 struct sci_port *sci_port = to_sci_port(port);
227434f8 660 struct tty_port *tport = &port->state->port;
1da177e4
LT		 661 int i, count, copied = 0;
662 unsigned short status;
33f0f88f 663 unsigned char flag;
1da177e4 664
b12bb29f 665 status = serial_port_in(port, SCxSR);
1da177e4
LT		 666 if (!(status & SCxSR_RDxF(port)))
667 return;
668
669 while (1) {
1da177e4 670 /* Don't copy more bytes than there is room for in the buffer */
227434f8 671 count = tty_buffer_request_room(tport, sci_rxfill(port));
1da177e4
LT		 672
673 /* If for any reason we can't copy more data, we're done! */
674 if (count == 0)
675 break;
676
677 if (port->type == PORT_SCI) {
b12bb29f 678 char c = serial_port_in(port, SCxRDR);
e7c98dc7
MT		 679 if (uart_handle_sysrq_char(port, c) ||
680 sci_port->break_flag)
1da177e4 681 count = 0;
e7c98dc7 682 else
92a19f9c 683 tty_insert_flip_char(tport, c, TTY_NORMAL);
1da177e4 684 } else {
e7c98dc7 685 for (i = 0; i < count; i++) {
b12bb29f 686 char c = serial_port_in(port, SCxRDR);
d97fbbed 687
b12bb29f 688 status = serial_port_in(port, SCxSR);
1da177e4
LT		 689#if defined(CONFIG_CPU_SH3)
690 /* Skip "chars" during break */
e108b2ca 691 if (sci_port->break_flag) {
1da177e4
LT		 692 if ((c == 0) &&
693 (status & SCxSR_FER(port))) {
694 count--; i--;
695 continue;
696 }
e108b2ca 697
1da177e4 698 /* Nonzero => end-of-break */
762c69e3 699 dev_dbg(port->dev, "debounce<%02x>\n", c);
e108b2ca
PM		 700 sci_port->break_flag = 0;
701
1da177e4
LT		 702 if (STEPFN(c)) {
703 count--; i--;
704 continue;
705 }
706 }
707#endif /* CONFIG_CPU_SH3 */
7d12e780 708 if (uart_handle_sysrq_char(port, c)) {
1da177e4
LT		 709 count--; i--;
710 continue;
711 }
712
713 /* Store data and status */
73a19e4c 714 if (status & SCxSR_FER(port)) {
33f0f88f 715 flag = TTY_FRAME;
d97fbbed 716 port->icount.frame++;
762c69e3 717 dev_notice(port->dev, "frame error\n");
73a19e4c 718 } else if (status & SCxSR_PER(port)) {
33f0f88f 719 flag = TTY_PARITY;
d97fbbed 720 port->icount.parity++;
762c69e3 721 dev_notice(port->dev, "parity error\n");
33f0f88f
AC		 722 } else
723 flag = TTY_NORMAL;
762c69e3 724
92a19f9c 725 tty_insert_flip_char(tport, c, flag);
1da177e4
LT		 726 }
727 }
728
b12bb29f
PM		 729 serial_port_in(port, SCxSR); /* dummy read */
730 serial_port_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
1da177e4 731
1da177e4
LT		 732 copied += count;
733 port->icount.rx += count;
734 }
735
736 if (copied) {
737 /* Tell the rest of the system the news. New characters! */
2e124b4a 738 tty_flip_buffer_push(tport);
1da177e4 739 } else {
b12bb29f
PM		 740 serial_port_in(port, SCxSR); /* dummy read */
741 serial_port_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
1da177e4
LT		 742 }
743}
744
745#define SCI_BREAK_JIFFIES (HZ/20)
94c8b6db
PM		 746
747/*
748 * The sci generates interrupts during the break,
1da177e4
LT		 749 * 1 per millisecond or so during the break period, for 9600 baud.
750 * So dont bother disabling interrupts.
751 * But dont want more than 1 break event.
752 * Use a kernel timer to periodically poll the rx line until
753 * the break is finished.
754 */
94c8b6db 755static inline void sci_schedule_break_timer(struct sci_port *port)
1da177e4 756{
bc9b3f5c 757 mod_timer(&port->break_timer, jiffies + SCI_BREAK_JIFFIES);
1da177e4 758}
94c8b6db 759
1da177e4
LT		 760/* Ensure that two consecutive samples find the break over. */
761static void sci_break_timer(unsigned long data)
762{
e108b2ca
PM		 763 struct sci_port *port = (struct sci_port *)data;
764
765 if (sci_rxd_in(&port->port) == 0) {
1da177e4 766 port->break_flag = 1;
e108b2ca
PM		 767 sci_schedule_break_timer(port);
768 } else if (port->break_flag == 1) {
1da177e4
LT		 769 /* break is over. */
770 port->break_flag = 2;
e108b2ca
PM		 771 sci_schedule_break_timer(port);
772 } else
773 port->break_flag = 0;
1da177e4
LT		 774}
775
94c8b6db 776static int sci_handle_errors(struct uart_port *port)
1da177e4
LT		 777{
778 int copied = 0;
b12bb29f 779 unsigned short status = serial_port_in(port, SCxSR);
92a19f9c 780 struct tty_port *tport = &port->state->port;
debf9507 781 struct sci_port *s = to_sci_port(port);
1da177e4 782
3ae988d9
LP		 783 /* Handle overruns */
784 if (status & (1 << s->overrun_bit)) {
785 port->icount.overrun++;
d97fbbed 786
3ae988d9
LP		 787 /* overrun error */
788 if (tty_insert_flip_char(tport, 0, TTY_OVERRUN))
789 copied++;
762c69e3 790
9b971cd2 791 dev_notice(port->dev, "overrun error\n");
1da177e4
LT		 792 }
793
e108b2ca 794 if (status & SCxSR_FER(port)) {
1da177e4
LT		 795 if (sci_rxd_in(port) == 0) {
796 /* Notify of BREAK */
e7c98dc7 797 struct sci_port *sci_port = to_sci_port(port);
e108b2ca
PM		 798
799 if (!sci_port->break_flag) {
d97fbbed
PM		 800 port->icount.brk++;
801
e108b2ca
PM		 802 sci_port->break_flag = 1;
803 sci_schedule_break_timer(sci_port);
804
1da177e4 805 /* Do sysrq handling. */
e108b2ca 806 if (uart_handle_break(port))
1da177e4 807 return 0;
762c69e3
PM		 808
809 dev_dbg(port->dev, "BREAK detected\n");
810
92a19f9c 811 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
e7c98dc7
MT		 812 copied++;
813 }
814
e108b2ca 815 } else {
1da177e4 816 /* frame error */
d97fbbed
PM		 817 port->icount.frame++;
818
92a19f9c 819 if (tty_insert_flip_char(tport, 0, TTY_FRAME))
33f0f88f 820 copied++;
762c69e3
PM		 821
822 dev_notice(port->dev, "frame error\n");
1da177e4
LT		 823 }
824 }
825
e108b2ca 826 if (status & SCxSR_PER(port)) {
1da177e4 827 /* parity error */
d97fbbed
PM		 828 port->icount.parity++;
829
92a19f9c 830 if (tty_insert_flip_char(tport, 0, TTY_PARITY))
e108b2ca 831 copied++;
762c69e3 832
9b971cd2 833 dev_notice(port->dev, "parity error\n");
1da177e4
LT		 834 }
835
33f0f88f 836 if (copied)
2e124b4a 837 tty_flip_buffer_push(tport);
1da177e4
LT		 838
839 return copied;
840}
841
94c8b6db 842static int sci_handle_fifo_overrun(struct uart_port *port)
d830fa45 843{
92a19f9c 844 struct tty_port *tport = &port->state->port;
debf9507 845 struct sci_port *s = to_sci_port(port);
4b8c59a3 846 struct plat_sci_reg *reg;
cb772fe7
NI		 847 int copied = 0, offset;
848 u16 status, bit;
849
850 switch (port->type) {
851 case PORT_SCIF:
852 case PORT_HSCIF:
853 offset = SCLSR;
854 break;
855 case PORT_SCIFA:
856 case PORT_SCIFB:
857 offset = SCxSR;
858 break;
859 default:
860 return 0;
861 }
d830fa45 862
cb772fe7 863 reg = sci_getreg(port, offset);
4b8c59a3 864 if (!reg->size)
d830fa45
PM		 865 return 0;
866
cb772fe7
NI		 867 status = serial_port_in(port, offset);
868 bit = 1 << s->overrun_bit;
869
870 if (status & bit) {
871 status &= ~bit;
872 serial_port_out(port, offset, status);
d830fa45 873
d97fbbed
PM		 874 port->icount.overrun++;
875
92a19f9c 876 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
2e124b4a 877 tty_flip_buffer_push(tport);
d830fa45 878
51b31f1c 879 dev_dbg(port->dev, "overrun error\n");
d830fa45
PM		 880 copied++;
881 }
882
883 return copied;
884}
885
94c8b6db 886static int sci_handle_breaks(struct uart_port *port)
1da177e4
LT		 887{
888 int copied = 0;
b12bb29f 889 unsigned short status = serial_port_in(port, SCxSR);
92a19f9c 890 struct tty_port *tport = &port->state->port;
a5660ada 891 struct sci_port *s = to_sci_port(port);
1da177e4 892
0b3d4ef6
PM		 893 if (uart_handle_break(port))
894 return 0;
895
b7a76e4b 896 if (!s->break_flag && status & SCxSR_BRK(port)) {
1da177e4
LT		 897#if defined(CONFIG_CPU_SH3)
898 /* Debounce break */
899 s->break_flag = 1;
900#endif
d97fbbed
PM		 901
902 port->icount.brk++;
903
1da177e4 904 /* Notify of BREAK */
92a19f9c 905 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
33f0f88f 906 copied++;
762c69e3
PM		 907
908 dev_dbg(port->dev, "BREAK detected\n");
1da177e4
LT		 909 }
910
33f0f88f 911 if (copied)
2e124b4a 912 tty_flip_buffer_push(tport);
e108b2ca 913
d830fa45
PM		 914 copied += sci_handle_fifo_overrun(port);
915
1da177e4
LT		 916 return copied;
917}
918
73a19e4c 919static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
1da177e4 920{
73a19e4c
GL		 921#ifdef CONFIG_SERIAL_SH_SCI_DMA
922 struct uart_port *port = ptr;
923 struct sci_port *s = to_sci_port(port);
924
925 if (s->chan_rx) {
b12bb29f
PM		 926 u16 scr = serial_port_in(port, SCSCR);
927 u16 ssr = serial_port_in(port, SCxSR);
73a19e4c
GL		 928
929 /* Disable future Rx interrupts */
d1d4b10c 930 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
3089f381 931 disable_irq_nosync(irq);
26de4f1b 932 scr |= SCSCR_RDRQE;
3089f381 933 } else {
f43dc23d 934 scr &= ~SCSCR_RIE;
3089f381 935 }
b12bb29f 936 serial_port_out(port, SCSCR, scr);
73a19e4c 937 /* Clear current interrupt */
b12bb29f 938 serial_port_out(port, SCxSR, ssr & ~(1 | SCxSR_RDxF(port)));
3089f381
GL		 939 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u jiffies\n",
940 jiffies, s->rx_timeout);
941 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
73a19e4c
GL		 942
943 return IRQ_HANDLED;
944 }
945#endif
946
1da177e4
LT		 947 /* I think sci_receive_chars has to be called irrespective
948 * of whether the I_IXOFF is set, otherwise, how is the interrupt
949 * to be disabled?
950 */
73a19e4c 951 sci_receive_chars(ptr);
1da177e4
LT		 952
953 return IRQ_HANDLED;
954}
955
7d12e780 956static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
1da177e4
LT		 957{
958 struct uart_port *port = ptr;
fd78a76a 959 unsigned long flags;
1da177e4 960
fd78a76a 961 spin_lock_irqsave(&port->lock, flags);
1da177e4 962 sci_transmit_chars(port);
fd78a76a 963 spin_unlock_irqrestore(&port->lock, flags);
1da177e4
LT		 964
965 return IRQ_HANDLED;
966}
967
7d12e780 968static irqreturn_t sci_er_interrupt(int irq, void *ptr)
1da177e4
LT		 969{
970 struct uart_port *port = ptr;
971
972 /* Handle errors */
973 if (port->type == PORT_SCI) {
974 if (sci_handle_errors(port)) {
975 /* discard character in rx buffer */
b12bb29f
PM		 976 serial_port_in(port, SCxSR);
977 serial_port_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
1da177e4
LT		 978 }
979 } else {
d830fa45 980 sci_handle_fifo_overrun(port);
7d12e780 981 sci_rx_interrupt(irq, ptr);
1da177e4
LT		 982 }
983
b12bb29f 984 serial_port_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
1da177e4
LT		 985
986 /* Kick the transmission */
7d12e780 987 sci_tx_interrupt(irq, ptr);
1da177e4
LT		 988
989 return IRQ_HANDLED;
990}
991
7d12e780 992static irqreturn_t sci_br_interrupt(int irq, void *ptr)
1da177e4
LT		 993{
994 struct uart_port *port = ptr;
995
996 /* Handle BREAKs */
997 sci_handle_breaks(port);
b12bb29f 998 serial_port_out(port, SCxSR, SCxSR_BREAK_CLEAR(port));
1da177e4
LT		 999
1000 return IRQ_HANDLED;
1001}
1002
f43dc23d
PM		 1003static inline unsigned long port_rx_irq_mask(struct uart_port *port)
1004{
1005 /*
1006 * Not all ports (such as SCIFA) will support REIE. Rather than
1007 * special-casing the port type, we check the port initialization
1008 * IRQ enable mask to see whether the IRQ is desired at all. If
1009 * it's unset, it's logically inferred that there's no point in
1010 * testing for it.
1011 */
ce6738b6 1012 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE);
f43dc23d
PM		 1013}
1014
7d12e780 1015static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
1da177e4 1016{
cb772fe7 1017 unsigned short ssr_status, scr_status, err_enabled, orer_status = 0;
a8884e34 1018 struct uart_port *port = ptr;
73a19e4c 1019 struct sci_port *s = to_sci_port(port);
a8884e34 1020 irqreturn_t ret = IRQ_NONE;
1da177e4 1021
b12bb29f
PM		 1022 ssr_status = serial_port_in(port, SCxSR);
1023 scr_status = serial_port_in(port, SCSCR);
cb772fe7
NI		 1024 switch (port->type) {
1025 case PORT_SCIF:
1026 case PORT_HSCIF:
1027 orer_status = serial_port_in(port, SCLSR);
1028 break;
1029 case PORT_SCIFA:
1030 case PORT_SCIFB:
1031 orer_status = ssr_status;
1032 break;
1033 }
1034
f43dc23d 1035 err_enabled = scr_status & port_rx_irq_mask(port);
1da177e4
LT		 1036
1037 /* Tx Interrupt */
f43dc23d 1038 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) &&
73a19e4c 1039 !s->chan_tx)
a8884e34 1040 ret = sci_tx_interrupt(irq, ptr);
f43dc23d 1041
73a19e4c
GL		 1042 /*
1043 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF /
1044 * DR flags
1045 */
1046 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&
8b6ff84c
HN		 1047 (scr_status & SCSCR_RIE)) {
1048 if (port->type == PORT_SCIF || port->type == PORT_HSCIF)
1049 sci_handle_fifo_overrun(port);
a8884e34 1050 ret = sci_rx_interrupt(irq, ptr);
8b6ff84c 1051 }
f43dc23d 1052
1da177e4 1053 /* Error Interrupt */
dd4da3a5 1054 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
a8884e34 1055 ret = sci_er_interrupt(irq, ptr);
f43dc23d 1056
1da177e4 1057 /* Break Interrupt */
dd4da3a5 1058 if ((ssr_status & SCxSR_BRK(port)) && err_enabled)
a8884e34 1059 ret = sci_br_interrupt(irq, ptr);
1da177e4 1060
8b6ff84c 1061 /* Overrun Interrupt */
cb772fe7
NI		 1062 if (orer_status & (1 << s->overrun_bit))
1063 sci_handle_fifo_overrun(port);
8b6ff84c 1064
a8884e34 1065 return ret;
1da177e4
LT		 1066}
1067
1da177e4 1068/*
25985edc 1069 * Here we define a transition notifier so that we can update all of our
1da177e4
LT		 1070 * ports' baud rate when the peripheral clock changes.
1071 */
e108b2ca
PM		 1072static int sci_notifier(struct notifier_block *self,
1073 unsigned long phase, void *p)
1da177e4 1074{
e552de24
MD		 1075 struct sci_port *sci_port;
1076 unsigned long flags;
1da177e4 1077
d535a230
PM		 1078 sci_port = container_of(self, struct sci_port, freq_transition);
1079
0b443ead 1080 if (phase == CPUFREQ_POSTCHANGE) {
d535a230 1081 struct uart_port *port = &sci_port->port;
073e84c9 1082
d535a230
PM		 1083 spin_lock_irqsave(&port->lock, flags);
1084 port->uartclk = clk_get_rate(sci_port->iclk);
1085 spin_unlock_irqrestore(&port->lock, flags);
e552de24 1086 }
1da177e4 1087
1da177e4
LT		 1088 return NOTIFY_OK;
1089}
501b825d 1090
9174fc8f
PM		 1091static struct sci_irq_desc {
1092 const char *desc;
1093 irq_handler_t handler;
1094} sci_irq_desc[] = {
1095 /*
1096 * Split out handlers, the default case.
1097 */
1098 [SCIx_ERI_IRQ] = {
1099 .desc = "rx err",
1100 .handler = sci_er_interrupt,
1101 },
1102
1103 [SCIx_RXI_IRQ] = {
1104 .desc = "rx full",
1105 .handler = sci_rx_interrupt,
1106 },
1107
1108 [SCIx_TXI_IRQ] = {
1109 .desc = "tx empty",
1110 .handler = sci_tx_interrupt,
1111 },
1112
1113 [SCIx_BRI_IRQ] = {
1114 .desc = "break",
1115 .handler = sci_br_interrupt,
1116 },
1117
1118 /*
1119 * Special muxed handler.
1120 */
1121 [SCIx_MUX_IRQ] = {
1122 .desc = "mux",
1123 .handler = sci_mpxed_interrupt,
1124 },
1125};
1126
1da177e4
LT		 1127static int sci_request_irq(struct sci_port *port)
1128{
9174fc8f
PM		 1129 struct uart_port *up = &port->port;
1130 int i, j, ret = 0;
1131
1132 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) {
1133 struct sci_irq_desc *desc;
1fcc91a6 1134 int irq;
9174fc8f
PM		 1135
1136 if (SCIx_IRQ_IS_MUXED(port)) {
1137 i = SCIx_MUX_IRQ;
1138 irq = up->irq;
0e8963de 1139 } else {
1fcc91a6 1140 irq = port->irqs[i];
9174fc8f 1141
0e8963de
PM		 1142 /*
1143 * Certain port types won't support all of the
1144 * available interrupt sources.
1145 */
1fcc91a6 1146 if (unlikely(irq < 0))
0e8963de
PM		 1147 continue;
1148 }
1149
9174fc8f
PM		 1150 desc = sci_irq_desc + i;
1151 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s",
1152 dev_name(up->dev), desc->desc);
1153 if (!port->irqstr[j]) {
1154 dev_err(up->dev, "Failed to allocate %s IRQ string\n",
1155 desc->desc);
1156 goto out_nomem;
1da177e4 1157 }
9174fc8f
PM		 1158
1159 ret = request_irq(irq, desc->handler, up->irqflags,
1160 port->irqstr[j], port);
1161 if (unlikely(ret)) {
1162 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc);
1163 goto out_noirq;
1da177e4
LT		 1164 }
1165 }
1166
1167 return 0;
9174fc8f
PM		 1168
1169out_noirq:
1170 while (--i >= 0)
1fcc91a6 1171 free_irq(port->irqs[i], port);
9174fc8f
PM		 1172
1173out_nomem:
1174 while (--j >= 0)
1175 kfree(port->irqstr[j]);
1176
1177 return ret;
1da177e4
LT		 1178}
1179
1180static void sci_free_irq(struct sci_port *port)
1181{
1182 int i;
1183
9174fc8f
PM		 1184 /*
1185 * Intentionally in reverse order so we iterate over the muxed
1186 * IRQ first.
1187 */
1188 for (i = 0; i < SCIx_NR_IRQS; i++) {
1fcc91a6 1189 int irq = port->irqs[i];
0e8963de
PM		 1190
1191 /*
1192 * Certain port types won't support all of the available
1193 * interrupt sources.
1194 */
1fcc91a6 1195 if (unlikely(irq < 0))
0e8963de
PM		 1196 continue;
1197
1fcc91a6 1198 free_irq(port->irqs[i], port);
9174fc8f 1199 kfree(port->irqstr[i]);
1da177e4 1200
9174fc8f
PM		 1201 if (SCIx_IRQ_IS_MUXED(port)) {
1202 /* If there's only one IRQ, we're done. */
1203 return;
1da177e4
LT		 1204 }
1205 }
1206}
1207
1208static unsigned int sci_tx_empty(struct uart_port *port)
1209{
b12bb29f 1210 unsigned short status = serial_port_in(port, SCxSR);
72b294cf 1211 unsigned short in_tx_fifo = sci_txfill(port);
73a19e4c
GL		 1212
1213 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
1da177e4
LT		 1214}
1215
cdf7c42f
PM		 1216/*
1217 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally
1218 * CTS/RTS is supported in hardware by at least one port and controlled
1219 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently
1220 * handled via the ->init_pins() op, which is a bit of a one-way street,
1221 * lacking any ability to defer pin control -- this will later be
1222 * converted over to the GPIO framework).
dc7e3ef7
PM		 1223 *
1224 * Other modes (such as loopback) are supported generically on certain
1225 * port types, but not others. For these it's sufficient to test for the
1226 * existence of the support register and simply ignore the port type.
cdf7c42f 1227 */
1da177e4
LT		 1228static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
1229{
dc7e3ef7
PM		 1230 if (mctrl & TIOCM_LOOP) {
1231 struct plat_sci_reg *reg;
1232
1233 /*
1234 * Standard loopback mode for SCFCR ports.
1235 */
1236 reg = sci_getreg(port, SCFCR);
1237 if (reg->size)
26de4f1b
GU		 1238 serial_port_out(port, SCFCR,
1239 serial_port_in(port, SCFCR) |
1240 SCFCR_LOOP);
dc7e3ef7 1241 }
1da177e4
LT		 1242}
1243
1244static unsigned int sci_get_mctrl(struct uart_port *port)
1245{
cdf7c42f
PM		 1246 /*
1247 * CTS/RTS is handled in hardware when supported, while nothing
1248 * else is wired up. Keep it simple and simply assert DSR/CAR.
1249 */
1250 return TIOCM_DSR | TIOCM_CAR;
1da177e4
LT		 1251}
1252
73a19e4c
GL		 1253#ifdef CONFIG_SERIAL_SH_SCI_DMA
1254static void sci_dma_tx_complete(void *arg)
1255{
1256 struct sci_port *s = arg;
1257 struct uart_port *port = &s->port;
1258 struct circ_buf *xmit = &port->state->xmit;
1259 unsigned long flags;
1260
1261 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1262
1263 spin_lock_irqsave(&port->lock, flags);
1264
f354a381 1265 xmit->tail += sg_dma_len(&s->sg_tx);
73a19e4c
GL		 1266 xmit->tail &= UART_XMIT_SIZE - 1;
1267
f354a381 1268 port->icount.tx += sg_dma_len(&s->sg_tx);
73a19e4c
GL		 1269
1270 async_tx_ack(s->desc_tx);
73a19e4c
GL		 1271 s->desc_tx = NULL;
1272
73a19e4c
GL		 1273 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1274 uart_write_wakeup(port);
1275
3089f381 1276 if (!uart_circ_empty(xmit)) {
49d4bcad 1277 s->cookie_tx = 0;
73a19e4c 1278 schedule_work(&s->work_tx);
49d4bcad
YT		 1279 } else {
1280 s->cookie_tx = -EINVAL;
1281 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
b12bb29f
PM		 1282 u16 ctrl = serial_port_in(port, SCSCR);
1283 serial_port_out(port, SCSCR, ctrl & ~SCSCR_TIE);
49d4bcad 1284 }
3089f381
GL		 1285 }
1286
1287 spin_unlock_irqrestore(&port->lock, flags);
73a19e4c
GL		 1288}
1289
1290/* Locking: called with port lock held */
92a19f9c 1291static int sci_dma_rx_push(struct sci_port *s, size_t count)
73a19e4c
GL		 1292{
1293 struct uart_port *port = &s->port;
227434f8 1294 struct tty_port *tport = &port->state->port;
73a19e4c
GL		 1295 int i, active, room;
1296
227434f8 1297 room = tty_buffer_request_room(tport, count);
73a19e4c
GL		 1298
1299 if (s->active_rx == s->cookie_rx[0]) {
1300 active = 0;
1301 } else if (s->active_rx == s->cookie_rx[1]) {
1302 active = 1;
1303 } else {
1304 dev_err(port->dev, "cookie %d not found!\n", s->active_rx);
1305 return 0;
1306 }
1307
1308 if (room < count)
e2afca69 1309 dev_warn(port->dev, "Rx overrun: dropping %zu bytes\n",
73a19e4c
GL		 1310 count - room);
1311 if (!room)
1312 return room;
1313
1314 for (i = 0; i < room; i++)
92a19f9c 1315 tty_insert_flip_char(tport, ((u8 *)sg_virt(&s->sg_rx[active]))[i],
73a19e4c
GL		 1316 TTY_NORMAL);
1317
1318 port->icount.rx += room;
1319
1320 return room;
1321}
1322
1323static void sci_dma_rx_complete(void *arg)
1324{
1325 struct sci_port *s = arg;
1326 struct uart_port *port = &s->port;
73a19e4c
GL		 1327 unsigned long flags;
1328 int count;
1329
9b971cd2
JP		 1330 dev_dbg(port->dev, "%s(%d) active #%d\n",
1331 __func__, port->line, s->active_rx);
73a19e4c
GL		 1332
1333 spin_lock_irqsave(&port->lock, flags);
1334
92a19f9c 1335 count = sci_dma_rx_push(s, s->buf_len_rx);
73a19e4c 1336
3089f381 1337 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
73a19e4c
GL		 1338
1339 spin_unlock_irqrestore(&port->lock, flags);
1340
1341 if (count)
2e124b4a 1342 tty_flip_buffer_push(&port->state->port);
73a19e4c
GL		 1343
1344 schedule_work(&s->work_rx);
1345}
1346
73a19e4c
GL		 1347static void sci_rx_dma_release(struct sci_port *s, bool enable_pio)
1348{
1349 struct dma_chan *chan = s->chan_rx;
1350 struct uart_port *port = &s->port;
73a19e4c
GL		 1351
1352 s->chan_rx = NULL;
1353 s->cookie_rx[0] = s->cookie_rx[1] = -EINVAL;
1354 dma_release_channel(chan);
85b8e3ff
GL		 1355 if (sg_dma_address(&s->sg_rx[0]))
1356 dma_free_coherent(port->dev, s->buf_len_rx * 2,
1357 sg_virt(&s->sg_rx[0]), sg_dma_address(&s->sg_rx[0]));
73a19e4c
GL		 1358 if (enable_pio)
1359 sci_start_rx(port);
1360}
1361
1362static void sci_tx_dma_release(struct sci_port *s, bool enable_pio)
1363{
1364 struct dma_chan *chan = s->chan_tx;
1365 struct uart_port *port = &s->port;
73a19e4c
GL		 1366
1367 s->chan_tx = NULL;
1368 s->cookie_tx = -EINVAL;
1369 dma_release_channel(chan);
1370 if (enable_pio)
1371 sci_start_tx(port);
1372}
1373
1374static void sci_submit_rx(struct sci_port *s)
1375{
1376 struct dma_chan *chan = s->chan_rx;
1377 int i;
1378
1379 for (i = 0; i < 2; i++) {
1380 struct scatterlist *sg = &s->sg_rx[i];
1381 struct dma_async_tx_descriptor *desc;
1382
16052827 1383 desc = dmaengine_prep_slave_sg(chan,
a485df4b 1384 sg, 1, DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
73a19e4c
GL		 1385
1386 if (desc) {
1387 s->desc_rx[i] = desc;
1388 desc->callback = sci_dma_rx_complete;
1389 desc->callback_param = s;
1390 s->cookie_rx[i] = desc->tx_submit(desc);
1391 }
1392
1393 if (!desc || s->cookie_rx[i] < 0) {
1394 if (i) {
1395 async_tx_ack(s->desc_rx[0]);
1396 s->cookie_rx[0] = -EINVAL;
1397 }
1398 if (desc) {
1399 async_tx_ack(desc);
1400 s->cookie_rx[i] = -EINVAL;
1401 }
1402 dev_warn(s->port.dev,
1403 "failed to re-start DMA, using PIO\n");
1404 sci_rx_dma_release(s, true);
1405 return;
1406 }
9b971cd2
JP		 1407 dev_dbg(s->port.dev, "%s(): cookie %d to #%d\n",
1408 __func__, s->cookie_rx[i], i);
73a19e4c
GL		 1409 }
1410
1411 s->active_rx = s->cookie_rx[0];
1412
1413 dma_async_issue_pending(chan);
1414}
1415
1416static void work_fn_rx(struct work_struct *work)
1417{
1418 struct sci_port *s = container_of(work, struct sci_port, work_rx);
1419 struct uart_port *port = &s->port;
1420 struct dma_async_tx_descriptor *desc;
1421 int new;
1422
1423 if (s->active_rx == s->cookie_rx[0]) {
1424 new = 0;
1425 } else if (s->active_rx == s->cookie_rx[1]) {
1426 new = 1;
1427 } else {
1428 dev_err(port->dev, "cookie %d not found!\n", s->active_rx);
1429 return;
1430 }
1431 desc = s->desc_rx[new];
1432
1433 if (dma_async_is_tx_complete(s->chan_rx, s->active_rx, NULL, NULL) !=
0b3d7d39 1434 DMA_COMPLETE) {
73a19e4c 1435 /* Handle incomplete DMA receive */
73a19e4c 1436 struct dma_chan *chan = s->chan_rx;
4dc4c516
GL		 1437 struct shdma_desc *sh_desc = container_of(desc,
1438 struct shdma_desc, async_tx);
73a19e4c
GL		 1439 unsigned long flags;
1440 int count;
1441
2bcd90d5 1442 dmaengine_terminate_all(chan);
e2afca69 1443 dev_dbg(port->dev, "Read %zu bytes with cookie %d\n",
73a19e4c
GL		 1444 sh_desc->partial, sh_desc->cookie);
1445
1446 spin_lock_irqsave(&port->lock, flags);
92a19f9c 1447 count = sci_dma_rx_push(s, sh_desc->partial);
73a19e4c
GL		 1448 spin_unlock_irqrestore(&port->lock, flags);
1449
1450 if (count)
2e124b4a 1451 tty_flip_buffer_push(&port->state->port);
73a19e4c
GL		 1452
1453 sci_submit_rx(s);
1454
1455 return;
1456 }
1457
1458 s->cookie_rx[new] = desc->tx_submit(desc);
1459 if (s->cookie_rx[new] < 0) {
1460 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
1461 sci_rx_dma_release(s, true);
1462 return;
1463 }
1464
73a19e4c 1465 s->active_rx = s->cookie_rx[!new];
3089f381 1466
9b971cd2
JP		 1467 dev_dbg(port->dev, "%s: cookie %d #%d, new active #%d\n",
1468 __func__, s->cookie_rx[new], new, s->active_rx);
73a19e4c
GL		 1469}
1470
1471static void work_fn_tx(struct work_struct *work)
1472{
1473 struct sci_port *s = container_of(work, struct sci_port, work_tx);
1474 struct dma_async_tx_descriptor *desc;
1475 struct dma_chan *chan = s->chan_tx;
1476 struct uart_port *port = &s->port;
1477 struct circ_buf *xmit = &port->state->xmit;
1478 struct scatterlist *sg = &s->sg_tx;
1479
1480 /*
1481 * DMA is idle now.
1482 * Port xmit buffer is already mapped, and it is one page... Just adjust
1483 * offsets and lengths. Since it is a circular buffer, we have to
1484 * transmit till the end, and then the rest. Take the port lock to get a
1485 * consistent xmit buffer state.
1486 */
1487 spin_lock_irq(&port->lock);
1488 sg->offset = xmit->tail & (UART_XMIT_SIZE - 1);
f354a381 1489 sg_dma_address(sg) = (sg_dma_address(sg) & ~(UART_XMIT_SIZE - 1)) +
73a19e4c 1490 sg->offset;
f354a381 1491 sg_dma_len(sg) = min((int)CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE),
73a19e4c 1492 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE));
73a19e4c
GL		 1493 spin_unlock_irq(&port->lock);
1494
f354a381 1495 BUG_ON(!sg_dma_len(sg));
73a19e4c 1496
16052827 1497 desc = dmaengine_prep_slave_sg(chan,
a485df4b 1498 sg, s->sg_len_tx, DMA_MEM_TO_DEV,
73a19e4c
GL		 1499 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1500 if (!desc) {
1501 /* switch to PIO */
1502 sci_tx_dma_release(s, true);
1503 return;
1504 }
1505
1506 dma_sync_sg_for_device(port->dev, sg, 1, DMA_TO_DEVICE);
1507
1508 spin_lock_irq(&port->lock);
1509 s->desc_tx = desc;
1510 desc->callback = sci_dma_tx_complete;
1511 desc->callback_param = s;
1512 spin_unlock_irq(&port->lock);
1513 s->cookie_tx = desc->tx_submit(desc);
1514 if (s->cookie_tx < 0) {
1515 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
1516 /* switch to PIO */
1517 sci_tx_dma_release(s, true);
1518 return;
1519 }
1520
9b971cd2
JP		 1521 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n",
1522 __func__, xmit->buf, xmit->tail, xmit->head, s->cookie_tx);
73a19e4c
GL		 1523
1524 dma_async_issue_pending(chan);
1525}
1526#endif
1527
b129a8cc 1528static void sci_start_tx(struct uart_port *port)
1da177e4 1529{
3089f381 1530 struct sci_port *s = to_sci_port(port);
e108b2ca 1531 unsigned short ctrl;
1da177e4 1532
73a19e4c 1533#ifdef CONFIG_SERIAL_SH_SCI_DMA
d1d4b10c 1534 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
b12bb29f 1535 u16 new, scr = serial_port_in(port, SCSCR);
3089f381 1536 if (s->chan_tx)
26de4f1b 1537 new = scr | SCSCR_TDRQE;
3089f381 1538 else
26de4f1b 1539 new = scr & ~SCSCR_TDRQE;
3089f381 1540 if (new != scr)
b12bb29f 1541 serial_port_out(port, SCSCR, new);
73a19e4c 1542 }
f43dc23d 1543
3089f381 1544 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) &&
49d4bcad
YT		 1545 s->cookie_tx < 0) {
1546 s->cookie_tx = 0;
3089f381 1547 schedule_work(&s->work_tx);
49d4bcad 1548 }
73a19e4c 1549#endif
f43dc23d 1550
d1d4b10c 1551 if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
3089f381 1552 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
b12bb29f
PM		 1553 ctrl = serial_port_in(port, SCSCR);
1554 serial_port_out(port, SCSCR, ctrl | SCSCR_TIE);
3089f381 1555 }
1da177e4
LT		 1556}
1557
b129a8cc 1558static void sci_stop_tx(struct uart_port *port)
1da177e4 1559{
1da177e4
LT		 1560 unsigned short ctrl;
1561
1562 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
b12bb29f 1563 ctrl = serial_port_in(port, SCSCR);
f43dc23d 1564
d1d4b10c 1565 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
26de4f1b 1566 ctrl &= ~SCSCR_TDRQE;
f43dc23d 1567
8e698614 1568 ctrl &= ~SCSCR_TIE;
f43dc23d 1569
b12bb29f 1570 serial_port_out(port, SCSCR, ctrl);
1da177e4
LT		 1571}
1572
73a19e4c 1573static void sci_start_rx(struct uart_port *port)
1da177e4 1574{
1da177e4
LT		 1575 unsigned short ctrl;
1576
b12bb29f 1577 ctrl = serial_port_in(port, SCSCR) | port_rx_irq_mask(port);
1da177e4 1578
d1d4b10c 1579 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
26de4f1b 1580 ctrl &= ~SCSCR_RDRQE;
f43dc23d 1581
b12bb29f 1582 serial_port_out(port, SCSCR, ctrl);
1da177e4
LT		 1583}
1584
1585static void sci_stop_rx(struct uart_port *port)
1586{
1da177e4
LT		 1587 unsigned short ctrl;
1588
b12bb29f 1589 ctrl = serial_port_in(port, SCSCR);
f43dc23d 1590
d1d4b10c 1591 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
26de4f1b 1592 ctrl &= ~SCSCR_RDRQE;
f43dc23d
PM		 1593
1594 ctrl &= ~port_rx_irq_mask(port);
1595
b12bb29f 1596 serial_port_out(port, SCSCR, ctrl);
1da177e4
LT		 1597}
1598
1da177e4
LT		 1599static void sci_break_ctl(struct uart_port *port, int break_state)
1600{
bbb4ce50 1601 struct sci_port *s = to_sci_port(port);
a4e02f6d 1602 struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR;
bbb4ce50
SY		 1603 unsigned short scscr, scsptr;
1604
a4e02f6d
SY		 1605 /* check wheter the port has SCSPTR */
1606 if (!reg->size) {
bbb4ce50
SY		 1607 /*
1608 * Not supported by hardware. Most parts couple break and rx
1609 * interrupts together, with break detection always enabled.
1610 */
a4e02f6d 1611 return;
bbb4ce50 1612 }
a4e02f6d
SY		 1613
1614 scsptr = serial_port_in(port, SCSPTR);
1615 scscr = serial_port_in(port, SCSCR);
1616
1617 if (break_state == -1) {
1618 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT;
1619 scscr &= ~SCSCR_TE;
1620 } else {
1621 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO;
1622 scscr |= SCSCR_TE;
1623 }
1624
1625 serial_port_out(port, SCSPTR, scsptr);
1626 serial_port_out(port, SCSCR, scscr);
1da177e4
LT		 1627}
1628
73a19e4c
GL		 1629#ifdef CONFIG_SERIAL_SH_SCI_DMA
1630static bool filter(struct dma_chan *chan, void *slave)
1631{
1632 struct sh_dmae_slave *param = slave;
1633
9b971cd2
JP		 1634 dev_dbg(chan->device->dev, "%s: slave ID %d\n",
1635 __func__, param->shdma_slave.slave_id);
73a19e4c 1636
d6fa5a4e 1637 chan->private = &param->shdma_slave;
937bb6e4 1638 return true;
73a19e4c
GL		 1639}
1640
1641static void rx_timer_fn(unsigned long arg)
1642{
1643 struct sci_port *s = (struct sci_port *)arg;
1644 struct uart_port *port = &s->port;
b12bb29f 1645 u16 scr = serial_port_in(port, SCSCR);
3089f381 1646
d1d4b10c 1647 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
26de4f1b 1648 scr &= ~SCSCR_RDRQE;
1fcc91a6 1649 enable_irq(s->irqs[SCIx_RXI_IRQ]);
3089f381 1650 }
b12bb29f 1651 serial_port_out(port, SCSCR, scr | SCSCR_RIE);
73a19e4c
GL		 1652 dev_dbg(port->dev, "DMA Rx timed out\n");
1653 schedule_work(&s->work_rx);
1654}
1655
1656static void sci_request_dma(struct uart_port *port)
1657{
1658 struct sci_port *s = to_sci_port(port);
1659 struct sh_dmae_slave *param;
1660 struct dma_chan *chan;
1661 dma_cap_mask_t mask;
1662 int nent;
1663
9b971cd2 1664 dev_dbg(port->dev, "%s: port %d\n", __func__, port->line);
73a19e4c 1665
937bb6e4 1666 if (s->cfg->dma_slave_tx <= 0 || s->cfg->dma_slave_rx <= 0)
73a19e4c
GL		 1667 return;
1668
1669 dma_cap_zero(mask);
1670 dma_cap_set(DMA_SLAVE, mask);
1671
1672 param = &s->param_tx;
1673
1674 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_TX */
d6fa5a4e 1675 param->shdma_slave.slave_id = s->cfg->dma_slave_tx;
73a19e4c
GL		 1676
1677 s->cookie_tx = -EINVAL;
1678 chan = dma_request_channel(mask, filter, param);
1679 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
1680 if (chan) {
1681 s->chan_tx = chan;
1682 sg_init_table(&s->sg_tx, 1);
1683 /* UART circular tx buffer is an aligned page. */
e2afca69 1684 BUG_ON((uintptr_t)port->state->xmit.buf & ~PAGE_MASK);
73a19e4c 1685 sg_set_page(&s->sg_tx, virt_to_page(port->state->xmit.buf),
e2afca69
LP		 1686 UART_XMIT_SIZE,
1687 (uintptr_t)port->state->xmit.buf & ~PAGE_MASK);
73a19e4c
GL		 1688 nent = dma_map_sg(port->dev, &s->sg_tx, 1, DMA_TO_DEVICE);
1689 if (!nent)
1690 sci_tx_dma_release(s, false);
1691 else
9b971cd2
JP		 1692 dev_dbg(port->dev, "%s: mapped %d@%p to %pad\n",
1693 __func__,
e2afca69
LP		 1694 sg_dma_len(&s->sg_tx), port->state->xmit.buf,
1695 &sg_dma_address(&s->sg_tx));
73a19e4c
GL		 1696
1697 s->sg_len_tx = nent;
1698
1699 INIT_WORK(&s->work_tx, work_fn_tx);
1700 }
1701
1702 param = &s->param_rx;
1703
1704 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_RX */
d6fa5a4e 1705 param->shdma_slave.slave_id = s->cfg->dma_slave_rx;
73a19e4c
GL		 1706
1707 chan = dma_request_channel(mask, filter, param);
1708 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan);
1709 if (chan) {
1710 dma_addr_t dma[2];
1711 void *buf[2];
1712 int i;
1713
1714 s->chan_rx = chan;
1715
1716 s->buf_len_rx = 2 * max(16, (int)port->fifosize);
1717 buf[0] = dma_alloc_coherent(port->dev, s->buf_len_rx * 2,
1718 &dma[0], GFP_KERNEL);
1719
1720 if (!buf[0]) {
1721 dev_warn(port->dev,
1722 "failed to allocate dma buffer, using PIO\n");
1723 sci_rx_dma_release(s, true);
1724 return;
1725 }
1726
1727 buf[1] = buf[0] + s->buf_len_rx;
1728 dma[1] = dma[0] + s->buf_len_rx;
1729
1730 for (i = 0; i < 2; i++) {
1731 struct scatterlist *sg = &s->sg_rx[i];
1732
1733 sg_init_table(sg, 1);
1734 sg_set_page(sg, virt_to_page(buf[i]), s->buf_len_rx,
e2afca69 1735 (uintptr_t)buf[i] & ~PAGE_MASK);
f354a381 1736 sg_dma_address(sg) = dma[i];
73a19e4c
GL		 1737 }
1738
1739 INIT_WORK(&s->work_rx, work_fn_rx);
1740 setup_timer(&s->rx_timer, rx_timer_fn, (unsigned long)s);
1741
1742 sci_submit_rx(s);
1743 }
1744}
1745
1746static void sci_free_dma(struct uart_port *port)
1747{
1748 struct sci_port *s = to_sci_port(port);
1749
73a19e4c
GL		 1750 if (s->chan_tx)
1751 sci_tx_dma_release(s, false);
1752 if (s->chan_rx)
1753 sci_rx_dma_release(s, false);
1754}
27bd1075
PM		 1755#else
1756static inline void sci_request_dma(struct uart_port *port)
1757{
1758}
1759
1760static inline void sci_free_dma(struct uart_port *port)
1761{
1762}
73a19e4c
GL		 1763#endif
1764
1da177e4
LT		 1765static int sci_startup(struct uart_port *port)
1766{
a5660ada 1767 struct sci_port *s = to_sci_port(port);
33b48e16 1768 unsigned long flags;
073e84c9 1769 int ret;
1da177e4 1770
73a19e4c
GL		 1771 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1772
073e84c9
PM		 1773 ret = sci_request_irq(s);
1774 if (unlikely(ret < 0))
1775 return ret;
1776
73a19e4c 1777 sci_request_dma(port);
073e84c9 1778
33b48e16 1779 spin_lock_irqsave(&port->lock, flags);
d656901b 1780 sci_start_tx(port);
73a19e4c 1781 sci_start_rx(port);
33b48e16 1782 spin_unlock_irqrestore(&port->lock, flags);
1da177e4
LT		 1783
1784 return 0;
1785}
1786
1787static void sci_shutdown(struct uart_port *port)
1788{
a5660ada 1789 struct sci_port *s = to_sci_port(port);
33b48e16 1790 unsigned long flags;
1da177e4 1791
73a19e4c
GL		 1792 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1793
33b48e16 1794 spin_lock_irqsave(&port->lock, flags);
1da177e4 1795 sci_stop_rx(port);
b129a8cc 1796 sci_stop_tx(port);
33b48e16 1797 spin_unlock_irqrestore(&port->lock, flags);
073e84c9 1798
73a19e4c 1799 sci_free_dma(port);
1da177e4 1800 sci_free_irq(s);
1da177e4
LT		 1801}
1802
ec09c5eb 1803static unsigned int sci_scbrr_calc(struct sci_port *s, unsigned int bps,
26c92f37
PM		 1804 unsigned long freq)
1805{
ec09c5eb
LP		 1806 if (s->sampling_rate)
1807 return DIV_ROUND_CLOSEST(freq, s->sampling_rate * bps) - 1;
1808
26c92f37
PM		 1809 /* Warn, but use a safe default */
1810 WARN_ON(1);
e8183a6c 1811
26c92f37
PM		 1812 return ((freq + 16 * bps) / (32 * bps) - 1);
1813}
1814
730c4e78
NI		 1815/* calculate frame length from SMR */
1816static int sci_baud_calc_frame_len(unsigned int smr_val)
1817{
1818 int len = 10;
1819
1820 if (smr_val & SCSMR_CHR)
1821 len--;
1822 if (smr_val & SCSMR_PE)
1823 len++;
1824 if (smr_val & SCSMR_STOP)
1825 len++;
1826
1827 return len;
1828}
1829
1830
f303b364
UH		 1831/* calculate sample rate, BRR, and clock select for HSCIF */
1832static void sci_baud_calc_hscif(unsigned int bps, unsigned long freq,
1833 int *brr, unsigned int *srr,
730c4e78 1834 unsigned int *cks, int frame_len)
f303b364 1835{
730c4e78 1836 int sr, c, br, err, recv_margin;
f303b364 1837 int min_err = 1000; /* 100% */
730c4e78 1838 int recv_max_margin = 0;
f303b364
UH		 1839
1840 /* Find the combination of sample rate and clock select with the
1841 smallest deviation from the desired baud rate. */
1842 for (sr = 8; sr <= 32; sr++) {
1843 for (c = 0; c <= 3; c++) {
1844 /* integerized formulas from HSCIF documentation */
b7d66397
NI		 1845 br = DIV_ROUND_CLOSEST(freq, (sr *
1846 (1 << (2 * c + 1)) * bps)) - 1;
bcb9973a 1847 br = clamp(br, 0, 255);
b7d66397
NI		 1848 err = DIV_ROUND_CLOSEST(freq, ((br + 1) * bps * sr *
1849 (1 << (2 * c + 1)) / 1000)) -
1850 1000;
730c4e78
NI		 1851 /* Calc recv margin
1852 * M: Receive margin (%)
1853 * N: Ratio of bit rate to clock (N = sampling rate)
1854 * D: Clock duty (D = 0 to 1.0)
1855 * L: Frame length (L = 9 to 12)
1856 * F: Absolute value of clock frequency deviation
1857 *
1858 * M = |(0.5 - 1 / 2 * N) - ((L - 0.5) * F) -
1859 * (|D - 0.5| / N * (1 + F))|
1860 * NOTE: Usually, treat D for 0.5, F is 0 by this
1861 * calculation.
1862 */
1863 recv_margin = abs((500 -
1864 DIV_ROUND_CLOSEST(1000, sr << 1)) / 10);
f53297fb 1865 if (abs(min_err) > abs(err)) {
f303b364 1866 min_err = err;
730c4e78
NI		 1867 recv_max_margin = recv_margin;
1868 } else if ((min_err == err) &&
1869 (recv_margin > recv_max_margin))
1870 recv_max_margin = recv_margin;
1871 else
1872 continue;
1873
1874 *brr = br;
1875 *srr = sr - 1;
1876 *cks = c;
f303b364
UH		 1877 }
1878 }
1879
1880 if (min_err == 1000) {
1881 WARN_ON(1);
1882 /* use defaults */
1883 *brr = 255;
1884 *srr = 15;
1885 *cks = 0;
1886 }
1887}
1888
1ba76220
MD		 1889static void sci_reset(struct uart_port *port)
1890{
0979e0e6 1891 struct plat_sci_reg *reg;
1ba76220
MD		 1892 unsigned int status;
1893
1894 do {
b12bb29f 1895 status = serial_port_in(port, SCxSR);
1ba76220
MD		 1896 } while (!(status & SCxSR_TEND(port)));
1897
b12bb29f 1898 serial_port_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */
1ba76220 1899
0979e0e6
PM		 1900 reg = sci_getreg(port, SCFCR);
1901 if (reg->size)
b12bb29f 1902 serial_port_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
1ba76220
MD		 1903}
1904
606d099c
AC		 1905static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
1906 struct ktermios *old)
1da177e4 1907{
00b9de9c 1908 struct sci_port *s = to_sci_port(port);
0979e0e6 1909 struct plat_sci_reg *reg;
730c4e78 1910 unsigned int baud, smr_val = 0, max_baud, cks = 0;
a2159b52 1911 int t = -1;
d4759ded 1912 unsigned int srr = 15;
1da177e4 1913
730c4e78
NI		 1914 if ((termios->c_cflag & CSIZE) == CS7)
1915 smr_val |= SCSMR_CHR;
1916 if (termios->c_cflag & PARENB)
1917 smr_val |= SCSMR_PE;
1918 if (termios->c_cflag & PARODD)
1919 smr_val |= SCSMR_PE | SCSMR_ODD;
1920 if (termios->c_cflag & CSTOPB)
1921 smr_val |= SCSMR_STOP;
1922
154280fd
MD		 1923 /*
1924 * earlyprintk comes here early on with port->uartclk set to zero.
1925 * the clock framework is not up and running at this point so here
1926 * we assume that 115200 is the maximum baud rate. please note that
1927 * the baud rate is not programmed during earlyprintk - it is assumed
1928 * that the previous boot loader has enabled required clocks and
1929 * setup the baud rate generator hardware for us already.
1930 */
1931 max_baud = port->uartclk ? port->uartclk / 16 : 115200;
1da177e4 1932
154280fd 1933 baud = uart_get_baud_rate(port, termios, old, 0, max_baud);
f303b364 1934 if (likely(baud && port->uartclk)) {
ec09c5eb 1935 if (s->cfg->type == PORT_HSCIF) {
730c4e78 1936 int frame_len = sci_baud_calc_frame_len(smr_val);
f303b364 1937 sci_baud_calc_hscif(baud, port->uartclk, &t, &srr,
730c4e78 1938 &cks, frame_len);
f303b364 1939 } else {
ec09c5eb 1940 t = sci_scbrr_calc(s, baud, port->uartclk);
f303b364
UH		 1941 for (cks = 0; t >= 256 && cks <= 3; cks++)
1942 t >>= 2;
1943 }
1944 }
e108b2ca 1945
23241d43 1946 sci_port_enable(s);
36003386 1947
1ba76220 1948 sci_reset(port);
1da177e4 1949
730c4e78 1950 smr_val |= serial_port_in(port, SCSMR) & 3;
1da177e4
LT		 1951
1952 uart_update_timeout(port, termios->c_cflag, baud);
1953
9d482cc3
TY		 1954 dev_dbg(port->dev, "%s: SMR %x, cks %x, t %x, SCSCR %x\n",
1955 __func__, smr_val, cks, t, s->cfg->scscr);
73a19e4c 1956
4ffc3cdb 1957 if (t >= 0) {
26de4f1b 1958 serial_port_out(port, SCSMR, (smr_val & ~SCSMR_CKS) | cks);
b12bb29f 1959 serial_port_out(port, SCBRR, t);
f303b364
UH		 1960 reg = sci_getreg(port, HSSRR);
1961 if (reg->size)
1962 serial_port_out(port, HSSRR, srr | HSCIF_SRE);
1da177e4 1963 udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */
9d482cc3
TY		 1964 } else
1965 serial_port_out(port, SCSMR, smr_val);
1da177e4 1966
d5701647 1967 sci_init_pins(port, termios->c_cflag);
0979e0e6 1968
73c3d53f
PM		 1969 reg = sci_getreg(port, SCFCR);
1970 if (reg->size) {
b12bb29f 1971 unsigned short ctrl = serial_port_in(port, SCFCR);
0979e0e6 1972
73c3d53f 1973 if (s->cfg->capabilities & SCIx_HAVE_RTSCTS) {
faf02f8f
PM		 1974 if (termios->c_cflag & CRTSCTS)
1975 ctrl |= SCFCR_MCE;
1976 else
1977 ctrl &= ~SCFCR_MCE;
faf02f8f 1978 }
73c3d53f
PM		 1979
1980 /*
1981 * As we've done a sci_reset() above, ensure we don't
1982 * interfere with the FIFOs while toggling MCE. As the
1983 * reset values could still be set, simply mask them out.
1984 */
1985 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST);
1986
b12bb29f 1987 serial_port_out(port, SCFCR, ctrl);
0979e0e6 1988 }
b7a76e4b 1989
b12bb29f 1990 serial_port_out(port, SCSCR, s->cfg->scscr);
1da177e4 1991
3089f381
GL		 1992#ifdef CONFIG_SERIAL_SH_SCI_DMA
1993 /*
5f6d8515
NI		 1994 * Calculate delay for 2 DMA buffers (4 FIFO).
1995 * See drivers/serial/serial_core.c::uart_update_timeout(). With 10
1996 * bits (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above function
3089f381 1997 * calculates 1 jiffie for the data plus 5 jiffies for the "slop(e)."
5f6d8515
NI		 1998 * Then below we calculate 5 jiffies (20ms) for 2 DMA buffers (4 FIFO
1999 * sizes), but when performing a faster transfer, value obtained by
2000 * this formula is may not enough. Therefore, if value is smaller than
2001 * 20msec, this sets 20msec as timeout of DMA.
3089f381
GL		 2002 */
2003 if (s->chan_rx) {
5f6d8515
NI		 2004 unsigned int bits;
2005
2006 /* byte size and parity */
2007 switch (termios->c_cflag & CSIZE) {
2008 case CS5:
2009 bits = 7;
2010 break;
2011 case CS6:
2012 bits = 8;
2013 break;
2014 case CS7:
2015 bits = 9;
2016 break;
2017 default:
2018 bits = 10;
2019 break;
2020 }
2021
2022 if (termios->c_cflag & CSTOPB)
2023 bits++;
2024 if (termios->c_cflag & PARENB)
2025 bits++;
2026 s->rx_timeout = DIV_ROUND_UP((s->buf_len_rx * 2 * bits * HZ) /
2027 (baud / 10), 10);
9b971cd2 2028 dev_dbg(port->dev, "DMA Rx t-out %ums, tty t-out %u jiffies\n",
3089f381
GL		 2029 s->rx_timeout * 1000 / HZ, port->timeout);
2030 if (s->rx_timeout < msecs_to_jiffies(20))
2031 s->rx_timeout = msecs_to_jiffies(20);
2032 }
2033#endif
2034
1da177e4 2035 if ((termios->c_cflag & CREAD) != 0)
73a19e4c 2036 sci_start_rx(port);
36003386 2037
23241d43 2038 sci_port_disable(s);
1da177e4
LT		 2039}
2040
0174e5ca
TK		 2041static void sci_pm(struct uart_port *port, unsigned int state,
2042 unsigned int oldstate)
2043{
2044 struct sci_port *sci_port = to_sci_port(port);
2045
2046 switch (state) {
d3dfe5d9 2047 case UART_PM_STATE_OFF:
0174e5ca
TK		 2048 sci_port_disable(sci_port);
2049 break;
2050 default:
2051 sci_port_enable(sci_port);
2052 break;
2053 }
2054}
2055
1da177e4
LT		 2056static const char *sci_type(struct uart_port *port)
2057{
2058 switch (port->type) {
e7c98dc7
MT		 2059 case PORT_IRDA:
2060 return "irda";
2061 case PORT_SCI:
2062 return "sci";
2063 case PORT_SCIF:
2064 return "scif";
2065 case PORT_SCIFA:
2066 return "scifa";
d1d4b10c
GL		 2067 case PORT_SCIFB:
2068 return "scifb";
f303b364
UH		 2069 case PORT_HSCIF:
2070 return "hscif";
1da177e4
LT		 2071 }
2072
fa43972f 2073 return NULL;
1da177e4
LT		 2074}
2075
e2651647 2076static inline unsigned long sci_port_size(struct uart_port *port)
1da177e4 2077{
e2651647
PM		 2078 /*
2079 * Pick an arbitrary size that encapsulates all of the base
2080 * registers by default. This can be optimized later, or derived
2081 * from platform resource data at such a time that ports begin to
2082 * behave more erratically.
2083 */
f303b364
UH		 2084 if (port->type == PORT_HSCIF)
2085 return 96;
2086 else
2087 return 64;
1da177e4
LT		 2088}
2089
f6e9495d
PM		 2090static int sci_remap_port(struct uart_port *port)
2091{
2092 unsigned long size = sci_port_size(port);
2093
2094 /*
2095 * Nothing to do if there's already an established membase.
2096 */
2097 if (port->membase)
2098 return 0;
2099
2100 if (port->flags & UPF_IOREMAP) {
2101 port->membase = ioremap_nocache(port->mapbase, size);
2102 if (unlikely(!port->membase)) {
2103 dev_err(port->dev, "can't remap port#%d\n", port->line);
2104 return -ENXIO;
2105 }
2106 } else {
2107 /*
2108 * For the simple (and majority of) cases where we don't
2109 * need to do any remapping, just cast the cookie
2110 * directly.
2111 */
3af4e960 2112 port->membase = (void __iomem *)(uintptr_t)port->mapbase;
f6e9495d
PM		 2113 }
2114
2115 return 0;
2116}
2117
e2651647 2118static void sci_release_port(struct uart_port *port)
1da177e4 2119{
e2651647
PM		 2120 if (port->flags & UPF_IOREMAP) {
2121 iounmap(port->membase);
2122 port->membase = NULL;
2123 }
2124
2125 release_mem_region(port->mapbase, sci_port_size(port));
1da177e4
LT		 2126}
2127
e2651647 2128static int sci_request_port(struct uart_port *port)
1da177e4 2129{
e2651647
PM		 2130 unsigned long size = sci_port_size(port);
2131 struct resource *res;
f6e9495d 2132 int ret;
1da177e4 2133
1020520e 2134 res = request_mem_region(port->mapbase, size, dev_name(port->dev));
e2651647
PM		 2135 if (unlikely(res == NULL))
2136 return -EBUSY;
1da177e4 2137
f6e9495d
PM		 2138 ret = sci_remap_port(port);
2139 if (unlikely(ret != 0)) {
2140 release_resource(res);
2141 return ret;
7ff731ae 2142 }
e2651647
PM		 2143
2144 return 0;
2145}
2146
2147static void sci_config_port(struct uart_port *port, int flags)
2148{
2149 if (flags & UART_CONFIG_TYPE) {
2150 struct sci_port *sport = to_sci_port(port);
2151
2152 port->type = sport->cfg->type;
2153 sci_request_port(port);
2154 }
1da177e4
LT		 2155}
2156
2157static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
2158{
1da177e4
LT		 2159 if (ser->baud_base < 2400)
2160 /* No paper tape reader for Mitch.. */
2161 return -EINVAL;
2162
2163 return 0;
2164}
2165
2166static struct uart_ops sci_uart_ops = {
2167 .tx_empty = sci_tx_empty,
2168 .set_mctrl = sci_set_mctrl,
2169 .get_mctrl = sci_get_mctrl,
2170 .start_tx = sci_start_tx,
2171 .stop_tx = sci_stop_tx,
2172 .stop_rx = sci_stop_rx,
1da177e4
LT		 2173 .break_ctl = sci_break_ctl,
2174 .startup = sci_startup,
2175 .shutdown = sci_shutdown,
2176 .set_termios = sci_set_termios,
0174e5ca 2177 .pm = sci_pm,
1da177e4
LT		 2178 .type = sci_type,
2179 .release_port = sci_release_port,
2180 .request_port = sci_request_port,
2181 .config_port = sci_config_port,
2182 .verify_port = sci_verify_port,
07d2a1a1
PM		 2183#ifdef CONFIG_CONSOLE_POLL
2184 .poll_get_char = sci_poll_get_char,
2185 .poll_put_char = sci_poll_put_char,
2186#endif
1da177e4
LT		 2187};
2188
9671f099 2189static int sci_init_single(struct platform_device *dev,
1fcc91a6
LP		 2190 struct sci_port *sci_port, unsigned int index,
2191 struct plat_sci_port *p, bool early)
e108b2ca 2192{
73a19e4c 2193 struct uart_port *port = &sci_port->port;
1fcc91a6 2194 const struct resource *res;
ec09c5eb 2195 unsigned int sampling_rate;
1fcc91a6 2196 unsigned int i;
3127c6b2 2197 int ret;
e108b2ca 2198
50f0959a
PM		 2199 sci_port->cfg = p;
2200
73a19e4c
GL		 2201 port->ops = &sci_uart_ops;
2202 port->iotype = UPIO_MEM;
2203 port->line = index;
75136d48 2204
89b5c1ab
LP		 2205 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
2206 if (res == NULL)
2207 return -ENOMEM;
1fcc91a6 2208
89b5c1ab 2209 port->mapbase = res->start;
1fcc91a6 2210
89b5c1ab
LP		 2211 for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i)
2212 sci_port->irqs[i] = platform_get_irq(dev, i);
1fcc91a6 2213
89b5c1ab
LP		 2214 /* The SCI generates several interrupts. They can be muxed together or
2215 * connected to different interrupt lines. In the muxed case only one
2216 * interrupt resource is specified. In the non-muxed case three or four
2217 * interrupt resources are specified, as the BRI interrupt is optional.
2218 */
2219 if (sci_port->irqs[0] < 0)
2220 return -ENXIO;
1fcc91a6 2221
89b5c1ab
LP		 2222 if (sci_port->irqs[1] < 0) {
2223 sci_port->irqs[1] = sci_port->irqs[0];
2224 sci_port->irqs[2] = sci_port->irqs[0];
2225 sci_port->irqs[3] = sci_port->irqs[0];
1fcc91a6
LP		 2226 }
2227
b545e4f4
LP		 2228 if (p->regtype == SCIx_PROBE_REGTYPE) {
2229 ret = sci_probe_regmap(p);
2230 if (unlikely(ret))
2231 return ret;
2232 }
2233
75136d48 2234 switch (p->type) {
d1d4b10c
GL		 2235 case PORT_SCIFB:
2236 port->fifosize = 256;
b545e4f4 2237 sci_port->overrun_bit = 9;
ec09c5eb 2238 sampling_rate = 16;
d1d4b10c 2239 break;
f303b364
UH		 2240 case PORT_HSCIF:
2241 port->fifosize = 128;
ec09c5eb 2242 sampling_rate = 0;
b545e4f4 2243 sci_port->overrun_bit = 0;
f303b364 2244 break;
75136d48 2245 case PORT_SCIFA:
73a19e4c 2246 port->fifosize = 64;
b545e4f4 2247 sci_port->overrun_bit = 9;
ec09c5eb 2248 sampling_rate = 16;
75136d48
MP		 2249 break;
2250 case PORT_SCIF:
73a19e4c 2251 port->fifosize = 16;
ec09c5eb 2252 if (p->regtype == SCIx_SH7705_SCIF_REGTYPE) {
b545e4f4 2253 sci_port->overrun_bit = 9;
ec09c5eb
LP		 2254 sampling_rate = 16;
2255 } else {
b545e4f4 2256 sci_port->overrun_bit = 0;
ec09c5eb
LP		 2257 sampling_rate = 32;
2258 }
75136d48
MP		 2259 break;
2260 default:
73a19e4c 2261 port->fifosize = 1;
b545e4f4 2262 sci_port->overrun_bit = 5;
ec09c5eb 2263 sampling_rate = 32;
75136d48
MP		 2264 break;
2265 }
7b6fd3bf 2266
878fbb91
LP		 2267 /* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't
2268 * match the SoC datasheet, this should be investigated. Let platform
2269 * data override the sampling rate for now.
ec09c5eb 2270 */
878fbb91
LP		 2271 sci_port->sampling_rate = p->sampling_rate ? p->sampling_rate
2272 : sampling_rate;
ec09c5eb 2273
1fcc91a6 2274 if (!early) {
c7ed1ab3
PM		 2275 sci_port->iclk = clk_get(&dev->dev, "sci_ick");
2276 if (IS_ERR(sci_port->iclk)) {
2277 sci_port->iclk = clk_get(&dev->dev, "peripheral_clk");
2278 if (IS_ERR(sci_port->iclk)) {
2279 dev_err(&dev->dev, "can't get iclk\n");
2280 return PTR_ERR(sci_port->iclk);
2281 }
2282 }
2283
2284 /*
2285 * The function clock is optional, ignore it if we can't
2286 * find it.
2287 */
2288 sci_port->fclk = clk_get(&dev->dev, "sci_fck");
2289 if (IS_ERR(sci_port->fclk))
2290 sci_port->fclk = NULL;
2291
73a19e4c 2292 port->dev = &dev->dev;
5e50d2d6
MD		 2293
2294 pm_runtime_enable(&dev->dev);
7b6fd3bf 2295 }
e108b2ca 2296
7ed7e071
MD		 2297 sci_port->break_timer.data = (unsigned long)sci_port;
2298 sci_port->break_timer.function = sci_break_timer;
2299 init_timer(&sci_port->break_timer);
2300
debf9507
PM		 2301 /*
2302 * Establish some sensible defaults for the error detection.
2303 */
3ae988d9 2304 sci_port->error_mask = (p->type == PORT_SCI) ?
debf9507
PM		 2305 SCI_DEFAULT_ERROR_MASK : SCIF_DEFAULT_ERROR_MASK;
2306
2307 /*
2308 * Establish sensible defaults for the overrun detection, unless
2309 * the part has explicitly disabled support for it.
2310 */
debf9507 2311
3ae988d9
LP		 2312 /*
2313 * Make the error mask inclusive of overrun detection, if
2314 * supported.
2315 */
2316 sci_port->error_mask |= 1 << sci_port->overrun_bit;
debf9507 2317
ce6738b6 2318 port->type = p->type;
b6e4a3f1 2319 port->flags = UPF_FIXED_PORT | p->flags;
61a6976b 2320 port->regshift = p->regshift;
73a19e4c 2321
ce6738b6 2322 /*
61a6976b 2323 * The UART port needs an IRQ value, so we peg this to the RX IRQ
ce6738b6
PM		 2324 * for the multi-IRQ ports, which is where we are primarily
2325 * concerned with the shutdown path synchronization.
2326 *
2327 * For the muxed case there's nothing more to do.
2328 */
1fcc91a6 2329 port->irq = sci_port->irqs[SCIx_RXI_IRQ];
9cfb5c05 2330 port->irqflags = 0;
73a19e4c 2331
61a6976b
PM		 2332 port->serial_in = sci_serial_in;
2333 port->serial_out = sci_serial_out;
2334
937bb6e4
GL		 2335 if (p->dma_slave_tx > 0 && p->dma_slave_rx > 0)
2336 dev_dbg(port->dev, "DMA tx %d, rx %d\n",
2337 p->dma_slave_tx, p->dma_slave_rx);
7ed7e071 2338
c7ed1ab3 2339 return 0;
e108b2ca
PM		 2340}
2341
6dae1421
LP		 2342static void sci_cleanup_single(struct sci_port *port)
2343{
6dae1421
LP		 2344 clk_put(port->iclk);
2345 clk_put(port->fclk);
2346
2347 pm_runtime_disable(port->port.dev);
2348}
2349
1da177e4 2350#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
dc8e6f5b
MD		 2351static void serial_console_putchar(struct uart_port *port, int ch)
2352{
2353 sci_poll_put_char(port, ch);
2354}
2355
1da177e4
LT		 2356/*
2357 * Print a string to the serial port trying not to disturb
2358 * any possible real use of the port...
2359 */
2360static void serial_console_write(struct console *co, const char *s,
2361 unsigned count)
2362{
906b17dc
PM		 2363 struct sci_port *sci_port = &sci_ports[co->index];
2364 struct uart_port *port = &sci_port->port;
40f70c03
SK		 2365 unsigned short bits, ctrl;
2366 unsigned long flags;
2367 int locked = 1;
2368
2369 local_irq_save(flags);
2370 if (port->sysrq)
2371 locked = 0;
2372 else if (oops_in_progress)
2373 locked = spin_trylock(&port->lock);
2374 else
2375 spin_lock(&port->lock);
2376
2377 /* first save the SCSCR then disable the interrupts */
2378 ctrl = serial_port_in(port, SCSCR);
2379 serial_port_out(port, SCSCR, sci_port->cfg->scscr);
07d2a1a1 2380
501b825d 2381 uart_console_write(port, s, count, serial_console_putchar);
973e5d52
MD		 2382
2383 /* wait until fifo is empty and last bit has been transmitted */
2384 bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
b12bb29f 2385 while ((serial_port_in(port, SCxSR) & bits) != bits)
973e5d52 2386 cpu_relax();
40f70c03
SK		 2387
2388 /* restore the SCSCR */
2389 serial_port_out(port, SCSCR, ctrl);
2390
2391 if (locked)
2392 spin_unlock(&port->lock);
2393 local_irq_restore(flags);
1da177e4
LT		 2394}
2395
9671f099 2396static int serial_console_setup(struct console *co, char *options)
1da177e4 2397{
dc8e6f5b 2398 struct sci_port *sci_port;
1da177e4
LT		 2399 struct uart_port *port;
2400 int baud = 115200;
2401 int bits = 8;
2402 int parity = 'n';
2403 int flow = 'n';
2404 int ret;
2405
e108b2ca 2406 /*
906b17dc 2407 * Refuse to handle any bogus ports.
1da177e4 2408 */
906b17dc 2409 if (co->index < 0 || co->index >= SCI_NPORTS)
e108b2ca 2410 return -ENODEV;
e108b2ca 2411
906b17dc
PM		 2412 sci_port = &sci_ports[co->index];
2413 port = &sci_port->port;
2414
b2267a6b
AC		 2415 /*
2416 * Refuse to handle uninitialized ports.
2417 */
2418 if (!port->ops)
2419 return -ENODEV;
2420
f6e9495d
PM		 2421 ret = sci_remap_port(port);
2422 if (unlikely(ret != 0))
2423 return ret;
e108b2ca 2424
1da177e4
LT		 2425 if (options)
2426 uart_parse_options(options, &baud, &parity, &bits, &flow);
2427
ab7cfb55 2428 return uart_set_options(port, co, baud, parity, bits, flow);
1da177e4
LT		 2429}
2430
2431static struct console serial_console = {
2432 .name = "ttySC",
906b17dc 2433 .device = uart_console_device,
1da177e4
LT		 2434 .write = serial_console_write,
2435 .setup = serial_console_setup,
fa5da2f7 2436 .flags = CON_PRINTBUFFER,
1da177e4 2437 .index = -1,
906b17dc 2438 .data = &sci_uart_driver,
1da177e4
LT		 2439};
2440
7b6fd3bf
MD		 2441static struct console early_serial_console = {
2442 .name = "early_ttySC",
2443 .write = serial_console_write,
2444 .flags = CON_PRINTBUFFER,
906b17dc 2445 .index = -1,
7b6fd3bf 2446};
ecdf8a46 2447
7b6fd3bf
MD		 2448static char early_serial_buf[32];
2449
9671f099 2450static int sci_probe_earlyprintk(struct platform_device *pdev)
ecdf8a46 2451{
574de559 2452 struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev);
ecdf8a46
PM		 2453
2454 if (early_serial_console.data)
2455 return -EEXIST;
2456
2457 early_serial_console.index = pdev->id;
ecdf8a46 2458
1fcc91a6 2459 sci_init_single(pdev, &sci_ports[pdev->id], pdev->id, cfg, true);
ecdf8a46
PM		 2460
2461 serial_console_setup(&early_serial_console, early_serial_buf);
2462
2463 if (!strstr(early_serial_buf, "keep"))
2464 early_serial_console.flags |= CON_BOOT;
2465
2466 register_console(&early_serial_console);
2467 return 0;
2468}
6a8c9799
NI		 2469
2470#define SCI_CONSOLE (&serial_console)
2471
ecdf8a46 2472#else
9671f099 2473static inline int sci_probe_earlyprintk(struct platform_device *pdev)
ecdf8a46
PM		 2474{
2475 return -EINVAL;
2476}
1da177e4 2477
6a8c9799
NI		 2478#define SCI_CONSOLE NULL
2479
2480#endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
1da177e4 2481
6c13d5d2 2482static const char banner[] __initconst = "SuperH (H)SCI(F) driver initialized";
1da177e4
LT		 2483
2484static struct uart_driver sci_uart_driver = {
2485 .owner = THIS_MODULE,
2486 .driver_name = "sci",
1da177e4
LT		 2487 .dev_name = "ttySC",
2488 .major = SCI_MAJOR,
2489 .minor = SCI_MINOR_START,
e108b2ca 2490 .nr = SCI_NPORTS,
1da177e4
LT		 2491 .cons = SCI_CONSOLE,
2492};
2493
54507f6e 2494static int sci_remove(struct platform_device *dev)
e552de24 2495{
d535a230 2496 struct sci_port *port = platform_get_drvdata(dev);
e552de24 2497
d535a230
PM		 2498 cpufreq_unregister_notifier(&port->freq_transition,
2499 CPUFREQ_TRANSITION_NOTIFIER);
e552de24 2500
d535a230
PM		 2501 uart_remove_one_port(&sci_uart_driver, &port->port);
2502
6dae1421 2503 sci_cleanup_single(port);
e552de24 2504
e552de24
MD		 2505 return 0;
2506}
2507
20bdcab8
BH		 2508struct sci_port_info {
2509 unsigned int type;
2510 unsigned int regtype;
2511};
2512
2513static const struct of_device_id of_sci_match[] = {
2514 {
2515 .compatible = "renesas,scif",
ff43da00 2516 .data = &(const struct sci_port_info) {
20bdcab8
BH		 2517 .type = PORT_SCIF,
2518 .regtype = SCIx_SH4_SCIF_REGTYPE,
2519 },
2520 }, {
2521 .compatible = "renesas,scifa",
ff43da00 2522 .data = &(const struct sci_port_info) {
20bdcab8
BH		 2523 .type = PORT_SCIFA,
2524 .regtype = SCIx_SCIFA_REGTYPE,
2525 },
2526 }, {
2527 .compatible = "renesas,scifb",
ff43da00 2528 .data = &(const struct sci_port_info) {
20bdcab8
BH		 2529 .type = PORT_SCIFB,
2530 .regtype = SCIx_SCIFB_REGTYPE,
2531 },
2532 }, {
2533 .compatible = "renesas,hscif",
ff43da00 2534 .data = &(const struct sci_port_info) {
20bdcab8
BH		 2535 .type = PORT_HSCIF,
2536 .regtype = SCIx_HSCIF_REGTYPE,
2537 },
e1d0be61
YS		 2538 }, {
2539 .compatible = "renesas,sci",
2540 .data = &(const struct sci_port_info) {
2541 .type = PORT_SCI,
2542 .regtype = SCIx_SCI_REGTYPE,
2543 },
20bdcab8
BH		 2544 }, {
2545 /* Terminator */
2546 },
2547};
2548MODULE_DEVICE_TABLE(of, of_sci_match);
2549
2550static struct plat_sci_port *
2551sci_parse_dt(struct platform_device *pdev, unsigned int *dev_id)
2552{
2553 struct device_node *np = pdev->dev.of_node;
2554 const struct of_device_id *match;
2555 const struct sci_port_info *info;
2556 struct plat_sci_port *p;
2557 int id;
2558
2559 if (!IS_ENABLED(CONFIG_OF) || !np)
2560 return NULL;
2561
2562 match = of_match_node(of_sci_match, pdev->dev.of_node);
2563 if (!match)
2564 return NULL;
2565
2566 info = match->data;
2567
2568 p = devm_kzalloc(&pdev->dev, sizeof(struct plat_sci_port), GFP_KERNEL);
2569 if (!p) {
2570 dev_err(&pdev->dev, "failed to allocate DT config data\n");
2571 return NULL;
2572 }
2573
2574 /* Get the line number for the aliases node. */
2575 id = of_alias_get_id(np, "serial");
2576 if (id < 0) {
2577 dev_err(&pdev->dev, "failed to get alias id (%d)\n", id);
2578 return NULL;
2579 }
2580
2581 *dev_id = id;
2582
2583 p->flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF;
2584 p->type = info->type;
2585 p->regtype = info->regtype;
2586 p->scscr = SCSCR_RE | SCSCR_TE;
2587
2588 return p;
2589}
2590
9671f099 2591static int sci_probe_single(struct platform_device *dev,
0ee70712
MD		 2592 unsigned int index,
2593 struct plat_sci_port *p,
2594 struct sci_port *sciport)
2595{
0ee70712
MD		 2596 int ret;
2597
2598 /* Sanity check */
2599 if (unlikely(index >= SCI_NPORTS)) {
9b971cd2 2600 dev_notice(&dev->dev, "Attempting to register port %d when only %d are available\n",
0ee70712 2601 index+1, SCI_NPORTS);
9b971cd2 2602 dev_notice(&dev->dev, "Consider bumping CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
b6c5ef6f 2603 return -EINVAL;
0ee70712
MD		 2604 }
2605
1fcc91a6 2606 ret = sci_init_single(dev, sciport, index, p, false);
c7ed1ab3
PM		 2607 if (ret)
2608 return ret;
0ee70712 2609
6dae1421
LP		 2610 ret = uart_add_one_port(&sci_uart_driver, &sciport->port);
2611 if (ret) {
2612 sci_cleanup_single(sciport);
2613 return ret;
2614 }
2615
2616 return 0;
0ee70712
MD		 2617}
2618
9671f099 2619static int sci_probe(struct platform_device *dev)
1da177e4 2620{
20bdcab8
BH		 2621 struct plat_sci_port *p;
2622 struct sci_port *sp;
2623 unsigned int dev_id;
ecdf8a46 2624 int ret;
d535a230 2625
ecdf8a46
PM		 2626 /*
2627 * If we've come here via earlyprintk initialization, head off to
2628 * the special early probe. We don't have sufficient device state
2629 * to make it beyond this yet.
2630 */
2631 if (is_early_platform_device(dev))
2632 return sci_probe_earlyprintk(dev);
7b6fd3bf 2633
20bdcab8
BH		 2634 if (dev->dev.of_node) {
2635 p = sci_parse_dt(dev, &dev_id);
2636 if (p == NULL)
2637 return -EINVAL;
2638 } else {
2639 p = dev->dev.platform_data;
2640 if (p == NULL) {
2641 dev_err(&dev->dev, "no platform data supplied\n");
2642 return -EINVAL;
2643 }
2644
2645 dev_id = dev->id;
2646 }
2647
2648 sp = &sci_ports[dev_id];
d535a230 2649 platform_set_drvdata(dev, sp);
e552de24 2650
20bdcab8 2651 ret = sci_probe_single(dev, dev_id, p, sp);
d535a230 2652 if (ret)
6dae1421 2653 return ret;
e552de24 2654
d535a230 2655 sp->freq_transition.notifier_call = sci_notifier;
1da177e4 2656
d535a230
PM		 2657 ret = cpufreq_register_notifier(&sp->freq_transition,
2658 CPUFREQ_TRANSITION_NOTIFIER);
6dae1421 2659 if (unlikely(ret < 0)) {
bf13c9a8 2660 uart_remove_one_port(&sci_uart_driver, &sp->port);
6dae1421
LP		 2661 sci_cleanup_single(sp);
2662 return ret;
2663 }
1da177e4
LT		 2664
2665#ifdef CONFIG_SH_STANDARD_BIOS
2666 sh_bios_gdb_detach();
2667#endif
2668
e108b2ca 2669 return 0;
1da177e4
LT		 2670}
2671
cb876341 2672static __maybe_unused int sci_suspend(struct device *dev)
1da177e4 2673{
d535a230 2674 struct sci_port *sport = dev_get_drvdata(dev);
e108b2ca 2675
d535a230
PM		 2676 if (sport)
2677 uart_suspend_port(&sci_uart_driver, &sport->port);
1da177e4 2678
e108b2ca
PM		 2679 return 0;
2680}
1da177e4 2681
cb876341 2682static __maybe_unused int sci_resume(struct device *dev)
e108b2ca 2683{
d535a230 2684 struct sci_port *sport = dev_get_drvdata(dev);
e108b2ca 2685
d535a230
PM		 2686 if (sport)
2687 uart_resume_port(&sci_uart_driver, &sport->port);
e108b2ca
PM		 2688
2689 return 0;
2690}
2691
cb876341 2692static SIMPLE_DEV_PM_OPS(sci_dev_pm_ops, sci_suspend, sci_resume);
6daa79b3 2693
e108b2ca
PM		 2694static struct platform_driver sci_driver = {
2695 .probe = sci_probe,
b9e39c89 2696 .remove = sci_remove,
e108b2ca
PM		 2697 .driver = {
2698 .name = "sh-sci",
6daa79b3 2699 .pm = &sci_dev_pm_ops,
20bdcab8 2700 .of_match_table = of_match_ptr(of_sci_match),
e108b2ca
PM		 2701 },
2702};
2703
2704static int __init sci_init(void)
2705{
2706 int ret;
2707
6c13d5d2 2708 pr_info("%s\n", banner);
e108b2ca 2709
e108b2ca
PM		 2710 ret = uart_register_driver(&sci_uart_driver);
2711 if (likely(ret == 0)) {
2712 ret = platform_driver_register(&sci_driver);
2713 if (unlikely(ret))
2714 uart_unregister_driver(&sci_uart_driver);
2715 }
2716
2717 return ret;
2718}
2719
2720static void __exit sci_exit(void)
2721{
2722 platform_driver_unregister(&sci_driver);
1da177e4
LT		 2723 uart_unregister_driver(&sci_uart_driver);
2724}
2725
7b6fd3bf
MD		 2726#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
2727early_platform_init_buffer("earlyprintk", &sci_driver,
2728 early_serial_buf, ARRAY_SIZE(early_serial_buf));
2729#endif
1da177e4
LT		 2730module_init(sci_init);
2731module_exit(sci_exit);
2732
e108b2ca 2733MODULE_LICENSE("GPL");
e169c139 2734MODULE_ALIAS("platform:sh-sci");
7f405f9c 2735MODULE_AUTHOR("Paul Mundt");
f303b364 2736MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver");
Linux 6.x block layer and io_uring tree(s)