projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
serial: sh-sci: Add support for loopback mode.
[linux-2.6-block.git] / drivers / tty / serial / sh-sci.c
CommitLineData
1da177e4 1/*
1da177e4
LT		 2 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
3 *
f43dc23d 4 * Copyright (C) 2002 - 2011 Paul Mundt
3ea6bc3d 5 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
1da177e4
LT		 6 *
7 * based off of the old drivers/char/sh-sci.c by:
8 *
9 * Copyright (C) 1999, 2000 Niibe Yutaka
10 * Copyright (C) 2000 Sugioka Toshinobu
11 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
12 * Modified to support SecureEdge. David McCullough (2002)
13 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
d89ddd1c 14 * Removed SH7300 support (Jul 2007).
1da177e4
LT		 15 *
16 * This file is subject to the terms and conditions of the GNU General Public
17 * License. See the file "COPYING" in the main directory of this archive
18 * for more details.
19 */
0b3d4ef6
PM		 20#if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
21#define SUPPORT_SYSRQ
22#endif
1da177e4
LT		 23
24#undef DEBUG
25
1da177e4
LT		 26#include <linux/module.h>
27#include <linux/errno.h>
1da177e4
LT		 28#include <linux/timer.h>
29#include <linux/interrupt.h>
30#include <linux/tty.h>
31#include <linux/tty_flip.h>
32#include <linux/serial.h>
33#include <linux/major.h>
34#include <linux/string.h>
35#include <linux/sysrq.h>
1da177e4
LT		 36#include <linux/ioport.h>
37#include <linux/mm.h>
1da177e4
LT		 38#include <linux/init.h>
39#include <linux/delay.h>
40#include <linux/console.h>
e108b2ca 41#include <linux/platform_device.h>
96de1a8f 42#include <linux/serial_sci.h>
1da177e4 43#include <linux/notifier.h>
5e50d2d6 44#include <linux/pm_runtime.h>
1da177e4 45#include <linux/cpufreq.h>
85f094ec 46#include <linux/clk.h>
fa5da2f7 47#include <linux/ctype.h>
7ff731ae 48#include <linux/err.h>
73a19e4c 49#include <linux/dmaengine.h>
5beabc7f 50#include <linux/dma-mapping.h>
73a19e4c 51#include <linux/scatterlist.h>
5a0e3ad6 52#include <linux/slab.h>
85f094ec
PM		 53
54#ifdef CONFIG_SUPERH
1da177e4
LT		 55#include <asm/sh_bios.h>
56#endif
57
1da177e4
LT		 58#include "sh-sci.h"
59
e108b2ca
PM		 60struct sci_port {
61 struct uart_port port;
62
ce6738b6
PM		 63 /* Platform configuration */
64 struct plat_sci_port *cfg;
e108b2ca 65
e108b2ca
PM		 66 /* Break timer */
67 struct timer_list break_timer;
68 int break_flag;
1534a3b3 69
501b825d
MD		 70 /* Interface clock */
71 struct clk *iclk;
c7ed1ab3
PM		 72 /* Function clock */
73 struct clk *fclk;
edad1f20 74
9174fc8f
PM		 75 char *irqstr[SCIx_NR_IRQS];
76
73a19e4c
GL		 77 struct dma_chan *chan_tx;
78 struct dma_chan *chan_rx;
f43dc23d 79
73a19e4c 80#ifdef CONFIG_SERIAL_SH_SCI_DMA
73a19e4c
GL		 81 struct dma_async_tx_descriptor *desc_tx;
82 struct dma_async_tx_descriptor *desc_rx[2];
83 dma_cookie_t cookie_tx;
84 dma_cookie_t cookie_rx[2];
85 dma_cookie_t active_rx;
86 struct scatterlist sg_tx;
87 unsigned int sg_len_tx;
88 struct scatterlist sg_rx[2];
89 size_t buf_len_rx;
90 struct sh_dmae_slave param_tx;
91 struct sh_dmae_slave param_rx;
92 struct work_struct work_tx;
93 struct work_struct work_rx;
94 struct timer_list rx_timer;
3089f381 95 unsigned int rx_timeout;
73a19e4c 96#endif
e552de24 97
d535a230 98 struct notifier_block freq_transition;
1ba76220
MD		 99
100#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
101 unsigned short saved_smr;
102 unsigned short saved_fcr;
103 unsigned char saved_brr;
104#endif
e108b2ca
PM		 105};
106
1da177e4 107/* Function prototypes */
d535a230 108static void sci_start_tx(struct uart_port *port);
b129a8cc 109static void sci_stop_tx(struct uart_port *port);
d535a230 110static void sci_start_rx(struct uart_port *port);
1da177e4 111
e108b2ca 112#define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
b7a76e4b 113
e108b2ca
PM		 114static struct sci_port sci_ports[SCI_NPORTS];
115static struct uart_driver sci_uart_driver;
1da177e4 116
e7c98dc7
MT		 117static inline struct sci_port *
118to_sci_port(struct uart_port *uart)
119{
120 return container_of(uart, struct sci_port, port);
121}
122
61a6976b
PM		 123struct plat_sci_reg {
124 u8 offset, size;
125};
126
127/* Helper for invalidating specific entries of an inherited map. */
128#define sci_reg_invalid { .offset = 0, .size = 0 }
129
130static struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = {
131 [SCIx_PROBE_REGTYPE] = {
132 [0 ... SCIx_NR_REGS - 1] = sci_reg_invalid,
133 },
134
135 /*
136 * Common SCI definitions, dependent on the port's regshift
137 * value.
138 */
139 [SCIx_SCI_REGTYPE] = {
140 [SCSMR] = { 0x00, 8 },
141 [SCBRR] = { 0x01, 8 },
142 [SCSCR] = { 0x02, 8 },
143 [SCxTDR] = { 0x03, 8 },
144 [SCxSR] = { 0x04, 8 },
145 [SCxRDR] = { 0x05, 8 },
146 [SCFCR] = sci_reg_invalid,
147 [SCFDR] = sci_reg_invalid,
148 [SCTFDR] = sci_reg_invalid,
149 [SCRFDR] = sci_reg_invalid,
150 [SCSPTR] = sci_reg_invalid,
151 [SCLSR] = sci_reg_invalid,
152 },
153
154 /*
155 * Common definitions for legacy IrDA ports, dependent on
156 * regshift value.
157 */
158 [SCIx_IRDA_REGTYPE] = {
159 [SCSMR] = { 0x00, 8 },
160 [SCBRR] = { 0x01, 8 },
161 [SCSCR] = { 0x02, 8 },
162 [SCxTDR] = { 0x03, 8 },
163 [SCxSR] = { 0x04, 8 },
164 [SCxRDR] = { 0x05, 8 },
165 [SCFCR] = { 0x06, 8 },
166 [SCFDR] = { 0x07, 16 },
167 [SCTFDR] = sci_reg_invalid,
168 [SCRFDR] = sci_reg_invalid,
169 [SCSPTR] = sci_reg_invalid,
170 [SCLSR] = sci_reg_invalid,
171 },
172
173 /*
174 * Common SCIFA definitions.
175 */
176 [SCIx_SCIFA_REGTYPE] = {
177 [SCSMR] = { 0x00, 16 },
178 [SCBRR] = { 0x04, 8 },
179 [SCSCR] = { 0x08, 16 },
180 [SCxTDR] = { 0x20, 8 },
181 [SCxSR] = { 0x14, 16 },
182 [SCxRDR] = { 0x24, 8 },
183 [SCFCR] = { 0x18, 16 },
184 [SCFDR] = { 0x1c, 16 },
185 [SCTFDR] = sci_reg_invalid,
186 [SCRFDR] = sci_reg_invalid,
187 [SCSPTR] = sci_reg_invalid,
188 [SCLSR] = sci_reg_invalid,
189 },
190
191 /*
192 * Common SCIFB definitions.
193 */
194 [SCIx_SCIFB_REGTYPE] = {
195 [SCSMR] = { 0x00, 16 },
196 [SCBRR] = { 0x04, 8 },
197 [SCSCR] = { 0x08, 16 },
198 [SCxTDR] = { 0x40, 8 },
199 [SCxSR] = { 0x14, 16 },
200 [SCxRDR] = { 0x60, 8 },
201 [SCFCR] = { 0x18, 16 },
202 [SCFDR] = { 0x1c, 16 },
203 [SCTFDR] = sci_reg_invalid,
204 [SCRFDR] = sci_reg_invalid,
205 [SCSPTR] = sci_reg_invalid,
206 [SCLSR] = sci_reg_invalid,
207 },
208
3af1f8a4
PE		 209 /*
210 * Common SH-2(A) SCIF definitions for ports with FIFO data
211 * count registers.
212 */
213 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = {
214 [SCSMR] = { 0x00, 16 },
215 [SCBRR] = { 0x04, 8 },
216 [SCSCR] = { 0x08, 16 },
217 [SCxTDR] = { 0x0c, 8 },
218 [SCxSR] = { 0x10, 16 },
219 [SCxRDR] = { 0x14, 8 },
220 [SCFCR] = { 0x18, 16 },
221 [SCFDR] = { 0x1c, 16 },
222 [SCTFDR] = sci_reg_invalid,
223 [SCRFDR] = sci_reg_invalid,
224 [SCSPTR] = { 0x20, 16 },
225 [SCLSR] = { 0x24, 16 },
226 },
227
61a6976b
PM		 228 /*
229 * Common SH-3 SCIF definitions.
230 */
231 [SCIx_SH3_SCIF_REGTYPE] = {
232 [SCSMR] = { 0x00, 8 },
233 [SCBRR] = { 0x02, 8 },
234 [SCSCR] = { 0x04, 8 },
235 [SCxTDR] = { 0x06, 8 },
236 [SCxSR] = { 0x08, 16 },
237 [SCxRDR] = { 0x0a, 8 },
238 [SCFCR] = { 0x0c, 8 },
239 [SCFDR] = { 0x0e, 16 },
240 [SCTFDR] = sci_reg_invalid,
241 [SCRFDR] = sci_reg_invalid,
242 [SCSPTR] = sci_reg_invalid,
243 [SCLSR] = sci_reg_invalid,
244 },
245
246 /*
247 * Common SH-4(A) SCIF(B) definitions.
248 */
249 [SCIx_SH4_SCIF_REGTYPE] = {
250 [SCSMR] = { 0x00, 16 },
251 [SCBRR] = { 0x04, 8 },
252 [SCSCR] = { 0x08, 16 },
253 [SCxTDR] = { 0x0c, 8 },
254 [SCxSR] = { 0x10, 16 },
255 [SCxRDR] = { 0x14, 8 },
256 [SCFCR] = { 0x18, 16 },
257 [SCFDR] = { 0x1c, 16 },
258 [SCTFDR] = sci_reg_invalid,
259 [SCRFDR] = sci_reg_invalid,
260 [SCSPTR] = { 0x20, 16 },
261 [SCLSR] = { 0x24, 16 },
262 },
263
264 /*
265 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR
266 * register.
267 */
268 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = {
269 [SCSMR] = { 0x00, 16 },
270 [SCBRR] = { 0x04, 8 },
271 [SCSCR] = { 0x08, 16 },
272 [SCxTDR] = { 0x0c, 8 },
273 [SCxSR] = { 0x10, 16 },
274 [SCxRDR] = { 0x14, 8 },
275 [SCFCR] = { 0x18, 16 },
276 [SCFDR] = { 0x1c, 16 },
277 [SCTFDR] = sci_reg_invalid,
278 [SCRFDR] = sci_reg_invalid,
279 [SCSPTR] = sci_reg_invalid,
280 [SCLSR] = { 0x24, 16 },
281 },
282
283 /*
284 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data
285 * count registers.
286 */
287 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = {
288 [SCSMR] = { 0x00, 16 },
289 [SCBRR] = { 0x04, 8 },
290 [SCSCR] = { 0x08, 16 },
291 [SCxTDR] = { 0x0c, 8 },
292 [SCxSR] = { 0x10, 16 },
293 [SCxRDR] = { 0x14, 8 },
294 [SCFCR] = { 0x18, 16 },
295 [SCFDR] = { 0x1c, 16 },
296 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */
297 [SCRFDR] = { 0x20, 16 },
298 [SCSPTR] = { 0x24, 16 },
299 [SCLSR] = { 0x28, 16 },
300 },
301
302 /*
303 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR
304 * registers.
305 */
306 [SCIx_SH7705_SCIF_REGTYPE] = {
307 [SCSMR] = { 0x00, 16 },
308 [SCBRR] = { 0x04, 8 },
309 [SCSCR] = { 0x08, 16 },
310 [SCxTDR] = { 0x20, 8 },
311 [SCxSR] = { 0x14, 16 },
312 [SCxRDR] = { 0x24, 8 },
313 [SCFCR] = { 0x18, 16 },
314 [SCFDR] = { 0x1c, 16 },
315 [SCTFDR] = sci_reg_invalid,
316 [SCRFDR] = sci_reg_invalid,
317 [SCSPTR] = sci_reg_invalid,
318 [SCLSR] = sci_reg_invalid,
319 },
320};
321
72b294cf
PM		 322#define sci_getreg(up, offset) (sci_regmap[to_sci_port(up)->cfg->regtype] + offset)
323
61a6976b
PM		 324/*
325 * The "offset" here is rather misleading, in that it refers to an enum
326 * value relative to the port mapping rather than the fixed offset
327 * itself, which needs to be manually retrieved from the platform's
328 * register map for the given port.
329 */
330static unsigned int sci_serial_in(struct uart_port *p, int offset)
331{
72b294cf 332 struct plat_sci_reg *reg = sci_getreg(p, offset);
61a6976b
PM		 333
334 if (reg->size == 8)
335 return ioread8(p->membase + (reg->offset << p->regshift));
336 else if (reg->size == 16)
337 return ioread16(p->membase + (reg->offset << p->regshift));
338 else
339 WARN(1, "Invalid register access\n");
340
341 return 0;
342}
343
344static void sci_serial_out(struct uart_port *p, int offset, int value)
345{
72b294cf 346 struct plat_sci_reg *reg = sci_getreg(p, offset);
61a6976b
PM		 347
348 if (reg->size == 8)
349 iowrite8(value, p->membase + (reg->offset << p->regshift));
350 else if (reg->size == 16)
351 iowrite16(value, p->membase + (reg->offset << p->regshift));
352 else
353 WARN(1, "Invalid register access\n");
354}
355
356#define sci_in(up, offset) (up->serial_in(up, offset))
357#define sci_out(up, offset, value) (up->serial_out(up, offset, value))
358
359static int sci_probe_regmap(struct plat_sci_port *cfg)
360{
361 switch (cfg->type) {
362 case PORT_SCI:
363 cfg->regtype = SCIx_SCI_REGTYPE;
364 break;
365 case PORT_IRDA:
366 cfg->regtype = SCIx_IRDA_REGTYPE;
367 break;
368 case PORT_SCIFA:
369 cfg->regtype = SCIx_SCIFA_REGTYPE;
370 break;
371 case PORT_SCIFB:
372 cfg->regtype = SCIx_SCIFB_REGTYPE;
373 break;
374 case PORT_SCIF:
375 /*
376 * The SH-4 is a bit of a misnomer here, although that's
377 * where this particular port layout originated. This
378 * configuration (or some slight variation thereof)
379 * remains the dominant model for all SCIFs.
380 */
381 cfg->regtype = SCIx_SH4_SCIF_REGTYPE;
382 break;
383 default:
384 printk(KERN_ERR "Can't probe register map for given port\n");
385 return -EINVAL;
386 }
387
388 return 0;
389}
390
23241d43
PM		 391static void sci_port_enable(struct sci_port *sci_port)
392{
393 if (!sci_port->port.dev)
394 return;
395
396 pm_runtime_get_sync(sci_port->port.dev);
397
398 clk_enable(sci_port->iclk);
399 sci_port->port.uartclk = clk_get_rate(sci_port->iclk);
400 clk_enable(sci_port->fclk);
401}
402
403static void sci_port_disable(struct sci_port *sci_port)
404{
405 if (!sci_port->port.dev)
406 return;
407
408 clk_disable(sci_port->fclk);
409 clk_disable(sci_port->iclk);
410
411 pm_runtime_put_sync(sci_port->port.dev);
412}
413
07d2a1a1 414#if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
1f6fd5c9
PM		 415
416#ifdef CONFIG_CONSOLE_POLL
07d2a1a1 417static int sci_poll_get_char(struct uart_port *port)
1da177e4 418{
1da177e4
LT		 419 unsigned short status;
420 int c;
421
e108b2ca 422 do {
1da177e4
LT		 423 status = sci_in(port, SCxSR);
424 if (status & SCxSR_ERRORS(port)) {
94c8b6db 425 sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
1da177e4
LT		 426 continue;
427 }
3f255eb3
JW		 428 break;
429 } while (1);
430
431 if (!(status & SCxSR_RDxF(port)))
432 return NO_POLL_CHAR;
07d2a1a1 433
1da177e4 434 c = sci_in(port, SCxRDR);
07d2a1a1 435
e7c98dc7
MT		 436 /* Dummy read */
437 sci_in(port, SCxSR);
1da177e4 438 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
1da177e4
LT		 439
440 return c;
441}
1f6fd5c9 442#endif
1da177e4 443
07d2a1a1 444static void sci_poll_put_char(struct uart_port *port, unsigned char c)
1da177e4 445{
1da177e4
LT		 446 unsigned short status;
447
1da177e4
LT		 448 do {
449 status = sci_in(port, SCxSR);
450 } while (!(status & SCxSR_TDxE(port)));
451
272966c0 452 sci_out(port, SCxTDR, c);
dd0a3e77 453 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
1da177e4 454}
07d2a1a1 455#endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE */
1da177e4 456
61a6976b 457static void sci_init_pins(struct uart_port *port, unsigned int cflag)
1da177e4 458{
61a6976b
PM		 459 struct sci_port *s = to_sci_port(port);
460 struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR;
1da177e4 461
61a6976b
PM		 462 /*
463 * Use port-specific handler if provided.
464 */
465 if (s->cfg->ops && s->cfg->ops->init_pins) {
466 s->cfg->ops->init_pins(port, cflag);
467 return;
1da177e4 468 }
41504c39 469
61a6976b
PM		 470 /*
471 * For the generic path SCSPTR is necessary. Bail out if that's
472 * unavailable, too.
473 */
474 if (!reg->size)
475 return;
41504c39 476
d5701647 477 if (!(cflag & CRTSCTS))
61a6976b 478 sci_out(port, SCSPTR, 0x0080); /* Set RTS = 1 */
d5701647 479}
e108b2ca 480
72b294cf 481static int sci_txfill(struct uart_port *port)
e108b2ca 482{
72b294cf 483 struct plat_sci_reg *reg;
e108b2ca 484
72b294cf
PM		 485 reg = sci_getreg(port, SCTFDR);
486 if (reg->size)
73a19e4c 487 return sci_in(port, SCTFDR) & 0xff;
c63847a3 488
72b294cf
PM		 489 reg = sci_getreg(port, SCFDR);
490 if (reg->size)
d1d4b10c 491 return sci_in(port, SCFDR) >> 8;
d1d4b10c 492
73a19e4c 493 return !(sci_in(port, SCxSR) & SCI_TDRE);
e108b2ca
PM		 494}
495
73a19e4c
GL		 496static int sci_txroom(struct uart_port *port)
497{
72b294cf 498 return port->fifosize - sci_txfill(port);
73a19e4c
GL		 499}
500
501static int sci_rxfill(struct uart_port *port)
e108b2ca 502{
72b294cf
PM		 503 struct plat_sci_reg *reg;
504
505 reg = sci_getreg(port, SCRFDR);
506 if (reg->size)
507 return sci_in(port, SCRFDR) & 0xff;
508
509 reg = sci_getreg(port, SCFDR);
510 if (reg->size)
511 return sci_in(port, SCFDR) & ((port->fifosize << 1) - 1);
512
e7c98dc7 513 return (sci_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
e108b2ca
PM		 514}
515
514820eb
PM		 516/*
517 * SCI helper for checking the state of the muxed port/RXD pins.
518 */
519static inline int sci_rxd_in(struct uart_port *port)
520{
521 struct sci_port *s = to_sci_port(port);
522
523 if (s->cfg->port_reg <= 0)
524 return 1;
525
526 return !!__raw_readb(s->cfg->port_reg);
527}
528
1da177e4
LT		 529/* ********************************************************************** *
530 * the interrupt related routines *
531 * ********************************************************************** */
532
533static void sci_transmit_chars(struct uart_port *port)
534{
ebd2c8f6 535 struct circ_buf *xmit = &port->state->xmit;
1da177e4 536 unsigned int stopped = uart_tx_stopped(port);
1da177e4
LT		 537 unsigned short status;
538 unsigned short ctrl;
e108b2ca 539 int count;
1da177e4
LT		 540
541 status = sci_in(port, SCxSR);
542 if (!(status & SCxSR_TDxE(port))) {
1da177e4 543 ctrl = sci_in(port, SCSCR);
e7c98dc7 544 if (uart_circ_empty(xmit))
8e698614 545 ctrl &= ~SCSCR_TIE;
e7c98dc7 546 else
8e698614 547 ctrl |= SCSCR_TIE;
1da177e4 548 sci_out(port, SCSCR, ctrl);
1da177e4
LT		 549 return;
550 }
551
72b294cf 552 count = sci_txroom(port);
1da177e4
LT		 553
554 do {
555 unsigned char c;
556
557 if (port->x_char) {
558 c = port->x_char;
559 port->x_char = 0;
560 } else if (!uart_circ_empty(xmit) && !stopped) {
561 c = xmit->buf[xmit->tail];
562 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
563 } else {
564 break;
565 }
566
567 sci_out(port, SCxTDR, c);
568
569 port->icount.tx++;
570 } while (--count > 0);
571
572 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
573
574 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
575 uart_write_wakeup(port);
576 if (uart_circ_empty(xmit)) {
b129a8cc 577 sci_stop_tx(port);
1da177e4 578 } else {
1da177e4
LT		 579 ctrl = sci_in(port, SCSCR);
580
1a22f08d 581 if (port->type != PORT_SCI) {
1da177e4
LT		 582 sci_in(port, SCxSR); /* Dummy read */
583 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
584 }
1da177e4 585
8e698614 586 ctrl |= SCSCR_TIE;
1da177e4 587 sci_out(port, SCSCR, ctrl);
1da177e4
LT		 588 }
589}
590
591/* On SH3, SCIF may read end-of-break as a space->mark char */
e7c98dc7 592#define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); })
1da177e4 593
94c8b6db 594static void sci_receive_chars(struct uart_port *port)
1da177e4 595{
e7c98dc7 596 struct sci_port *sci_port = to_sci_port(port);
ebd2c8f6 597 struct tty_struct *tty = port->state->port.tty;
1da177e4
LT		 598 int i, count, copied = 0;
599 unsigned short status;
33f0f88f 600 unsigned char flag;
1da177e4
LT		 601
602 status = sci_in(port, SCxSR);
603 if (!(status & SCxSR_RDxF(port)))
604 return;
605
606 while (1) {
1da177e4 607 /* Don't copy more bytes than there is room for in the buffer */
72b294cf 608 count = tty_buffer_request_room(tty, sci_rxfill(port));
1da177e4
LT		 609
610 /* If for any reason we can't copy more data, we're done! */
611 if (count == 0)
612 break;
613
614 if (port->type == PORT_SCI) {
615 char c = sci_in(port, SCxRDR);
e7c98dc7
MT		 616 if (uart_handle_sysrq_char(port, c) ||
617 sci_port->break_flag)
1da177e4 618 count = 0;
e7c98dc7 619 else
e108b2ca 620 tty_insert_flip_char(tty, c, TTY_NORMAL);
1da177e4 621 } else {
e7c98dc7 622 for (i = 0; i < count; i++) {
1da177e4 623 char c = sci_in(port, SCxRDR);
d97fbbed 624
1da177e4
LT		 625 status = sci_in(port, SCxSR);
626#if defined(CONFIG_CPU_SH3)
627 /* Skip "chars" during break */
e108b2ca 628 if (sci_port->break_flag) {
1da177e4
LT		 629 if ((c == 0) &&
630 (status & SCxSR_FER(port))) {
631 count--; i--;
632 continue;
633 }
e108b2ca 634
1da177e4 635 /* Nonzero => end-of-break */
762c69e3 636 dev_dbg(port->dev, "debounce<%02x>\n", c);
e108b2ca
PM		 637 sci_port->break_flag = 0;
638
1da177e4
LT		 639 if (STEPFN(c)) {
640 count--; i--;
641 continue;
642 }
643 }
644#endif /* CONFIG_CPU_SH3 */
7d12e780 645 if (uart_handle_sysrq_char(port, c)) {
1da177e4
LT		 646 count--; i--;
647 continue;
648 }
649
650 /* Store data and status */
73a19e4c 651 if (status & SCxSR_FER(port)) {
33f0f88f 652 flag = TTY_FRAME;
d97fbbed 653 port->icount.frame++;
762c69e3 654 dev_notice(port->dev, "frame error\n");
73a19e4c 655 } else if (status & SCxSR_PER(port)) {
33f0f88f 656 flag = TTY_PARITY;
d97fbbed 657 port->icount.parity++;
762c69e3 658 dev_notice(port->dev, "parity error\n");
33f0f88f
AC		 659 } else
660 flag = TTY_NORMAL;
762c69e3 661
33f0f88f 662 tty_insert_flip_char(tty, c, flag);
1da177e4
LT		 663 }
664 }
665
666 sci_in(port, SCxSR); /* dummy read */
667 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
668
1da177e4
LT		 669 copied += count;
670 port->icount.rx += count;
671 }
672
673 if (copied) {
674 /* Tell the rest of the system the news. New characters! */
675 tty_flip_buffer_push(tty);
676 } else {
677 sci_in(port, SCxSR); /* dummy read */
678 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
679 }
680}
681
682#define SCI_BREAK_JIFFIES (HZ/20)
94c8b6db
PM		 683
684/*
685 * The sci generates interrupts during the break,
1da177e4
LT		 686 * 1 per millisecond or so during the break period, for 9600 baud.
687 * So dont bother disabling interrupts.
688 * But dont want more than 1 break event.
689 * Use a kernel timer to periodically poll the rx line until
690 * the break is finished.
691 */
94c8b6db 692static inline void sci_schedule_break_timer(struct sci_port *port)
1da177e4 693{
bc9b3f5c 694 mod_timer(&port->break_timer, jiffies + SCI_BREAK_JIFFIES);
1da177e4 695}
94c8b6db 696
1da177e4
LT		 697/* Ensure that two consecutive samples find the break over. */
698static void sci_break_timer(unsigned long data)
699{
e108b2ca
PM		 700 struct sci_port *port = (struct sci_port *)data;
701
23241d43 702 sci_port_enable(port);
5e50d2d6 703
e108b2ca 704 if (sci_rxd_in(&port->port) == 0) {
1da177e4 705 port->break_flag = 1;
e108b2ca
PM		 706 sci_schedule_break_timer(port);
707 } else if (port->break_flag == 1) {
1da177e4
LT		 708 /* break is over. */
709 port->break_flag = 2;
e108b2ca
PM		 710 sci_schedule_break_timer(port);
711 } else
712 port->break_flag = 0;
5e50d2d6 713
23241d43 714 sci_port_disable(port);
1da177e4
LT		 715}
716
94c8b6db 717static int sci_handle_errors(struct uart_port *port)
1da177e4
LT		 718{
719 int copied = 0;
720 unsigned short status = sci_in(port, SCxSR);
ebd2c8f6 721 struct tty_struct *tty = port->state->port.tty;
debf9507 722 struct sci_port *s = to_sci_port(port);
1da177e4 723
debf9507
PM		 724 /*
725 * Handle overruns, if supported.
726 */
727 if (s->cfg->overrun_bit != SCIx_NOT_SUPPORTED) {
728 if (status & (1 << s->cfg->overrun_bit)) {
d97fbbed
PM		 729 port->icount.overrun++;
730
debf9507
PM		 731 /* overrun error */
732 if (tty_insert_flip_char(tty, 0, TTY_OVERRUN))
733 copied++;
762c69e3 734
debf9507
PM		 735 dev_notice(port->dev, "overrun error");
736 }
1da177e4
LT		 737 }
738
e108b2ca 739 if (status & SCxSR_FER(port)) {
1da177e4
LT		 740 if (sci_rxd_in(port) == 0) {
741 /* Notify of BREAK */
e7c98dc7 742 struct sci_port *sci_port = to_sci_port(port);
e108b2ca
PM		 743
744 if (!sci_port->break_flag) {
d97fbbed
PM		 745 port->icount.brk++;
746
e108b2ca
PM		 747 sci_port->break_flag = 1;
748 sci_schedule_break_timer(sci_port);
749
1da177e4 750 /* Do sysrq handling. */
e108b2ca 751 if (uart_handle_break(port))
1da177e4 752 return 0;
762c69e3
PM		 753
754 dev_dbg(port->dev, "BREAK detected\n");
755
e108b2ca 756 if (tty_insert_flip_char(tty, 0, TTY_BREAK))
e7c98dc7
MT		 757 copied++;
758 }
759
e108b2ca 760 } else {
1da177e4 761 /* frame error */
d97fbbed
PM		 762 port->icount.frame++;
763
e108b2ca 764 if (tty_insert_flip_char(tty, 0, TTY_FRAME))
33f0f88f 765 copied++;
762c69e3
PM		 766
767 dev_notice(port->dev, "frame error\n");
1da177e4
LT		 768 }
769 }
770
e108b2ca 771 if (status & SCxSR_PER(port)) {
1da177e4 772 /* parity error */
d97fbbed
PM		 773 port->icount.parity++;
774
e108b2ca
PM		 775 if (tty_insert_flip_char(tty, 0, TTY_PARITY))
776 copied++;
762c69e3
PM		 777
778 dev_notice(port->dev, "parity error");
1da177e4
LT		 779 }
780
33f0f88f 781 if (copied)
1da177e4 782 tty_flip_buffer_push(tty);
1da177e4
LT		 783
784 return copied;
785}
786
94c8b6db 787static int sci_handle_fifo_overrun(struct uart_port *port)
d830fa45 788{
ebd2c8f6 789 struct tty_struct *tty = port->state->port.tty;
debf9507 790 struct sci_port *s = to_sci_port(port);
4b8c59a3 791 struct plat_sci_reg *reg;
d830fa45
PM		 792 int copied = 0;
793
4b8c59a3
PM		 794 reg = sci_getreg(port, SCLSR);
795 if (!reg->size)
d830fa45
PM		 796 return 0;
797
debf9507 798 if ((sci_in(port, SCLSR) & (1 << s->cfg->overrun_bit))) {
d830fa45
PM		 799 sci_out(port, SCLSR, 0);
800
d97fbbed
PM		 801 port->icount.overrun++;
802
d830fa45
PM		 803 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
804 tty_flip_buffer_push(tty);
805
806 dev_notice(port->dev, "overrun error\n");
807 copied++;
808 }
809
810 return copied;
811}
812
94c8b6db 813static int sci_handle_breaks(struct uart_port *port)
1da177e4
LT		 814{
815 int copied = 0;
816 unsigned short status = sci_in(port, SCxSR);
ebd2c8f6 817 struct tty_struct *tty = port->state->port.tty;
a5660ada 818 struct sci_port *s = to_sci_port(port);
1da177e4 819
0b3d4ef6
PM		 820 if (uart_handle_break(port))
821 return 0;
822
b7a76e4b 823 if (!s->break_flag && status & SCxSR_BRK(port)) {
1da177e4
LT		 824#if defined(CONFIG_CPU_SH3)
825 /* Debounce break */
826 s->break_flag = 1;
827#endif
d97fbbed
PM		 828
829 port->icount.brk++;
830
1da177e4 831 /* Notify of BREAK */
e108b2ca 832 if (tty_insert_flip_char(tty, 0, TTY_BREAK))
33f0f88f 833 copied++;
762c69e3
PM		 834
835 dev_dbg(port->dev, "BREAK detected\n");
1da177e4
LT		 836 }
837
33f0f88f 838 if (copied)
1da177e4 839 tty_flip_buffer_push(tty);
e108b2ca 840
d830fa45
PM		 841 copied += sci_handle_fifo_overrun(port);
842
1da177e4
LT		 843 return copied;
844}
845
73a19e4c 846static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
1da177e4 847{
73a19e4c
GL		 848#ifdef CONFIG_SERIAL_SH_SCI_DMA
849 struct uart_port *port = ptr;
850 struct sci_port *s = to_sci_port(port);
851
852 if (s->chan_rx) {
73a19e4c
GL		 853 u16 scr = sci_in(port, SCSCR);
854 u16 ssr = sci_in(port, SCxSR);
855
856 /* Disable future Rx interrupts */
d1d4b10c 857 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
3089f381
GL		 858 disable_irq_nosync(irq);
859 scr |= 0x4000;
860 } else {
f43dc23d 861 scr &= ~SCSCR_RIE;
3089f381
GL		 862 }
863 sci_out(port, SCSCR, scr);
73a19e4c
GL		 864 /* Clear current interrupt */
865 sci_out(port, SCxSR, ssr & ~(1 | SCxSR_RDxF(port)));
3089f381
GL		 866 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u jiffies\n",
867 jiffies, s->rx_timeout);
868 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
73a19e4c
GL		 869
870 return IRQ_HANDLED;
871 }
872#endif
873
1da177e4
LT		 874 /* I think sci_receive_chars has to be called irrespective
875 * of whether the I_IXOFF is set, otherwise, how is the interrupt
876 * to be disabled?
877 */
73a19e4c 878 sci_receive_chars(ptr);
1da177e4
LT		 879
880 return IRQ_HANDLED;
881}
882
7d12e780 883static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
1da177e4
LT		 884{
885 struct uart_port *port = ptr;
fd78a76a 886 unsigned long flags;
1da177e4 887
fd78a76a 888 spin_lock_irqsave(&port->lock, flags);
1da177e4 889 sci_transmit_chars(port);
fd78a76a 890 spin_unlock_irqrestore(&port->lock, flags);
1da177e4
LT		 891
892 return IRQ_HANDLED;
893}
894
7d12e780 895static irqreturn_t sci_er_interrupt(int irq, void *ptr)
1da177e4
LT		 896{
897 struct uart_port *port = ptr;
898
899 /* Handle errors */
900 if (port->type == PORT_SCI) {
901 if (sci_handle_errors(port)) {
902 /* discard character in rx buffer */
903 sci_in(port, SCxSR);
904 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
905 }
906 } else {
d830fa45 907 sci_handle_fifo_overrun(port);
7d12e780 908 sci_rx_interrupt(irq, ptr);
1da177e4
LT		 909 }
910
911 sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
912
913 /* Kick the transmission */
7d12e780 914 sci_tx_interrupt(irq, ptr);
1da177e4
LT		 915
916 return IRQ_HANDLED;
917}
918
7d12e780 919static irqreturn_t sci_br_interrupt(int irq, void *ptr)
1da177e4
LT		 920{
921 struct uart_port *port = ptr;
922
923 /* Handle BREAKs */
924 sci_handle_breaks(port);
925 sci_out(port, SCxSR, SCxSR_BREAK_CLEAR(port));
926
927 return IRQ_HANDLED;
928}
929
f43dc23d
PM		 930static inline unsigned long port_rx_irq_mask(struct uart_port *port)
931{
932 /*
933 * Not all ports (such as SCIFA) will support REIE. Rather than
934 * special-casing the port type, we check the port initialization
935 * IRQ enable mask to see whether the IRQ is desired at all. If
936 * it's unset, it's logically inferred that there's no point in
937 * testing for it.
938 */
ce6738b6 939 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE);
f43dc23d
PM		 940}
941
7d12e780 942static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
1da177e4 943{
44e18e9e 944 unsigned short ssr_status, scr_status, err_enabled;
a8884e34 945 struct uart_port *port = ptr;
73a19e4c 946 struct sci_port *s = to_sci_port(port);
a8884e34 947 irqreturn_t ret = IRQ_NONE;
1da177e4 948
e7c98dc7
MT		 949 ssr_status = sci_in(port, SCxSR);
950 scr_status = sci_in(port, SCSCR);
f43dc23d 951 err_enabled = scr_status & port_rx_irq_mask(port);
1da177e4
LT		 952
953 /* Tx Interrupt */
f43dc23d 954 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) &&
73a19e4c 955 !s->chan_tx)
a8884e34 956 ret = sci_tx_interrupt(irq, ptr);
f43dc23d 957
73a19e4c
GL		 958 /*
959 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF /
960 * DR flags
961 */
962 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&
f43dc23d 963 (scr_status & SCSCR_RIE))
a8884e34 964 ret = sci_rx_interrupt(irq, ptr);
f43dc23d 965
1da177e4 966 /* Error Interrupt */
dd4da3a5 967 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
a8884e34 968 ret = sci_er_interrupt(irq, ptr);
f43dc23d 969
1da177e4 970 /* Break Interrupt */
dd4da3a5 971 if ((ssr_status & SCxSR_BRK(port)) && err_enabled)
a8884e34 972 ret = sci_br_interrupt(irq, ptr);
1da177e4 973
a8884e34 974 return ret;
1da177e4
LT		 975}
976
1da177e4 977/*
25985edc 978 * Here we define a transition notifier so that we can update all of our
1da177e4
LT		 979 * ports' baud rate when the peripheral clock changes.
980 */
e108b2ca
PM		 981static int sci_notifier(struct notifier_block *self,
982 unsigned long phase, void *p)
1da177e4 983{
e552de24
MD		 984 struct sci_port *sci_port;
985 unsigned long flags;
1da177e4 986
d535a230
PM		 987 sci_port = container_of(self, struct sci_port, freq_transition);
988
1da177e4 989 if ((phase == CPUFREQ_POSTCHANGE) ||
e552de24 990 (phase == CPUFREQ_RESUMECHANGE)) {
d535a230 991 struct uart_port *port = &sci_port->port;
073e84c9 992
d535a230
PM		 993 spin_lock_irqsave(&port->lock, flags);
994 port->uartclk = clk_get_rate(sci_port->iclk);
995 spin_unlock_irqrestore(&port->lock, flags);
e552de24 996 }
1da177e4 997
1da177e4
LT		 998 return NOTIFY_OK;
999}
501b825d 1000
9174fc8f
PM		 1001static struct sci_irq_desc {
1002 const char *desc;
1003 irq_handler_t handler;
1004} sci_irq_desc[] = {
1005 /*
1006 * Split out handlers, the default case.
1007 */
1008 [SCIx_ERI_IRQ] = {
1009 .desc = "rx err",
1010 .handler = sci_er_interrupt,
1011 },
1012
1013 [SCIx_RXI_IRQ] = {
1014 .desc = "rx full",
1015 .handler = sci_rx_interrupt,
1016 },
1017
1018 [SCIx_TXI_IRQ] = {
1019 .desc = "tx empty",
1020 .handler = sci_tx_interrupt,
1021 },
1022
1023 [SCIx_BRI_IRQ] = {
1024 .desc = "break",
1025 .handler = sci_br_interrupt,
1026 },
1027
1028 /*
1029 * Special muxed handler.
1030 */
1031 [SCIx_MUX_IRQ] = {
1032 .desc = "mux",
1033 .handler = sci_mpxed_interrupt,
1034 },
1035};
1036
1da177e4
LT		 1037static int sci_request_irq(struct sci_port *port)
1038{
9174fc8f
PM		 1039 struct uart_port *up = &port->port;
1040 int i, j, ret = 0;
1041
1042 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) {
1043 struct sci_irq_desc *desc;
1044 unsigned int irq;
1045
1046 if (SCIx_IRQ_IS_MUXED(port)) {
1047 i = SCIx_MUX_IRQ;
1048 irq = up->irq;
1049 } else
1050 irq = port->cfg->irqs[i];
1051
1052 desc = sci_irq_desc + i;
1053 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s",
1054 dev_name(up->dev), desc->desc);
1055 if (!port->irqstr[j]) {
1056 dev_err(up->dev, "Failed to allocate %s IRQ string\n",
1057 desc->desc);
1058 goto out_nomem;
1da177e4 1059 }
9174fc8f
PM		 1060
1061 ret = request_irq(irq, desc->handler, up->irqflags,
1062 port->irqstr[j], port);
1063 if (unlikely(ret)) {
1064 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc);
1065 goto out_noirq;
1da177e4
LT		 1066 }
1067 }
1068
1069 return 0;
9174fc8f
PM		 1070
1071out_noirq:
1072 while (--i >= 0)
1073 free_irq(port->cfg->irqs[i], port);
1074
1075out_nomem:
1076 while (--j >= 0)
1077 kfree(port->irqstr[j]);
1078
1079 return ret;
1da177e4
LT		 1080}
1081
1082static void sci_free_irq(struct sci_port *port)
1083{
1084 int i;
1085
9174fc8f
PM		 1086 /*
1087 * Intentionally in reverse order so we iterate over the muxed
1088 * IRQ first.
1089 */
1090 for (i = 0; i < SCIx_NR_IRQS; i++) {
1091 free_irq(port->cfg->irqs[i], port);
1092 kfree(port->irqstr[i]);
1da177e4 1093
9174fc8f
PM		 1094 if (SCIx_IRQ_IS_MUXED(port)) {
1095 /* If there's only one IRQ, we're done. */
1096 return;
1da177e4
LT		 1097 }
1098 }
1099}
1100
1101static unsigned int sci_tx_empty(struct uart_port *port)
1102{
b1516803 1103 unsigned short status = sci_in(port, SCxSR);
72b294cf 1104 unsigned short in_tx_fifo = sci_txfill(port);
73a19e4c
GL		 1105
1106 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
1da177e4
LT		 1107}
1108
cdf7c42f
PM		 1109/*
1110 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally
1111 * CTS/RTS is supported in hardware by at least one port and controlled
1112 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently
1113 * handled via the ->init_pins() op, which is a bit of a one-way street,
1114 * lacking any ability to defer pin control -- this will later be
1115 * converted over to the GPIO framework).
dc7e3ef7
PM		 1116 *
1117 * Other modes (such as loopback) are supported generically on certain
1118 * port types, but not others. For these it's sufficient to test for the
1119 * existence of the support register and simply ignore the port type.
cdf7c42f 1120 */
1da177e4
LT		 1121static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
1122{
dc7e3ef7
PM		 1123 if (mctrl & TIOCM_LOOP) {
1124 struct plat_sci_reg *reg;
1125
1126 /*
1127 * Standard loopback mode for SCFCR ports.
1128 */
1129 reg = sci_getreg(port, SCFCR);
1130 if (reg->size)
1131 sci_out(port, SCFCR, sci_in(port, SCFCR) | 1);
1132 }
1da177e4
LT		 1133}
1134
1135static unsigned int sci_get_mctrl(struct uart_port *port)
1136{
cdf7c42f
PM		 1137 /*
1138 * CTS/RTS is handled in hardware when supported, while nothing
1139 * else is wired up. Keep it simple and simply assert DSR/CAR.
1140 */
1141 return TIOCM_DSR | TIOCM_CAR;
1da177e4
LT		 1142}
1143
73a19e4c
GL		 1144#ifdef CONFIG_SERIAL_SH_SCI_DMA
1145static void sci_dma_tx_complete(void *arg)
1146{
1147 struct sci_port *s = arg;
1148 struct uart_port *port = &s->port;
1149 struct circ_buf *xmit = &port->state->xmit;
1150 unsigned long flags;
1151
1152 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1153
1154 spin_lock_irqsave(&port->lock, flags);
1155
f354a381 1156 xmit->tail += sg_dma_len(&s->sg_tx);
73a19e4c
GL		 1157 xmit->tail &= UART_XMIT_SIZE - 1;
1158
f354a381 1159 port->icount.tx += sg_dma_len(&s->sg_tx);
73a19e4c
GL		 1160
1161 async_tx_ack(s->desc_tx);
1162 s->cookie_tx = -EINVAL;
1163 s->desc_tx = NULL;
1164
73a19e4c
GL		 1165 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1166 uart_write_wakeup(port);
1167
3089f381 1168 if (!uart_circ_empty(xmit)) {
73a19e4c 1169 schedule_work(&s->work_tx);
d1d4b10c 1170 } else if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
3089f381 1171 u16 ctrl = sci_in(port, SCSCR);
f43dc23d 1172 sci_out(port, SCSCR, ctrl & ~SCSCR_TIE);
3089f381
GL		 1173 }
1174
1175 spin_unlock_irqrestore(&port->lock, flags);
73a19e4c
GL		 1176}
1177
1178/* Locking: called with port lock held */
1179static int sci_dma_rx_push(struct sci_port *s, struct tty_struct *tty,
1180 size_t count)
1181{
1182 struct uart_port *port = &s->port;
1183 int i, active, room;
1184
1185 room = tty_buffer_request_room(tty, count);
1186
1187 if (s->active_rx == s->cookie_rx[0]) {
1188 active = 0;
1189 } else if (s->active_rx == s->cookie_rx[1]) {
1190 active = 1;
1191 } else {
1192 dev_err(port->dev, "cookie %d not found!\n", s->active_rx);
1193 return 0;
1194 }
1195
1196 if (room < count)
1197 dev_warn(port->dev, "Rx overrun: dropping %u bytes\n",
1198 count - room);
1199 if (!room)
1200 return room;
1201
1202 for (i = 0; i < room; i++)
1203 tty_insert_flip_char(tty, ((u8 *)sg_virt(&s->sg_rx[active]))[i],
1204 TTY_NORMAL);
1205
1206 port->icount.rx += room;
1207
1208 return room;
1209}
1210
1211static void sci_dma_rx_complete(void *arg)
1212{
1213 struct sci_port *s = arg;
1214 struct uart_port *port = &s->port;
1215 struct tty_struct *tty = port->state->port.tty;
1216 unsigned long flags;
1217 int count;
1218
3089f381 1219 dev_dbg(port->dev, "%s(%d) active #%d\n", __func__, port->line, s->active_rx);
73a19e4c
GL		 1220
1221 spin_lock_irqsave(&port->lock, flags);
1222
1223 count = sci_dma_rx_push(s, tty, s->buf_len_rx);
1224
3089f381 1225 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
73a19e4c
GL		 1226
1227 spin_unlock_irqrestore(&port->lock, flags);
1228
1229 if (count)
1230 tty_flip_buffer_push(tty);
1231
1232 schedule_work(&s->work_rx);
1233}
1234
73a19e4c
GL		 1235static void sci_rx_dma_release(struct sci_port *s, bool enable_pio)
1236{
1237 struct dma_chan *chan = s->chan_rx;
1238 struct uart_port *port = &s->port;
73a19e4c
GL		 1239
1240 s->chan_rx = NULL;
1241 s->cookie_rx[0] = s->cookie_rx[1] = -EINVAL;
1242 dma_release_channel(chan);
85b8e3ff
GL		 1243 if (sg_dma_address(&s->sg_rx[0]))
1244 dma_free_coherent(port->dev, s->buf_len_rx * 2,
1245 sg_virt(&s->sg_rx[0]), sg_dma_address(&s->sg_rx[0]));
73a19e4c
GL		 1246 if (enable_pio)
1247 sci_start_rx(port);
1248}
1249
1250static void sci_tx_dma_release(struct sci_port *s, bool enable_pio)
1251{
1252 struct dma_chan *chan = s->chan_tx;
1253 struct uart_port *port = &s->port;
73a19e4c
GL		 1254
1255 s->chan_tx = NULL;
1256 s->cookie_tx = -EINVAL;
1257 dma_release_channel(chan);
1258 if (enable_pio)
1259 sci_start_tx(port);
1260}
1261
1262static void sci_submit_rx(struct sci_port *s)
1263{
1264 struct dma_chan *chan = s->chan_rx;
1265 int i;
1266
1267 for (i = 0; i < 2; i++) {
1268 struct scatterlist *sg = &s->sg_rx[i];
1269 struct dma_async_tx_descriptor *desc;
1270
1271 desc = chan->device->device_prep_slave_sg(chan,
1272 sg, 1, DMA_FROM_DEVICE, DMA_PREP_INTERRUPT);
1273
1274 if (desc) {
1275 s->desc_rx[i] = desc;
1276 desc->callback = sci_dma_rx_complete;
1277 desc->callback_param = s;
1278 s->cookie_rx[i] = desc->tx_submit(desc);
1279 }
1280
1281 if (!desc || s->cookie_rx[i] < 0) {
1282 if (i) {
1283 async_tx_ack(s->desc_rx[0]);
1284 s->cookie_rx[0] = -EINVAL;
1285 }
1286 if (desc) {
1287 async_tx_ack(desc);
1288 s->cookie_rx[i] = -EINVAL;
1289 }
1290 dev_warn(s->port.dev,
1291 "failed to re-start DMA, using PIO\n");
1292 sci_rx_dma_release(s, true);
1293 return;
1294 }
3089f381
GL		 1295 dev_dbg(s->port.dev, "%s(): cookie %d to #%d\n", __func__,
1296 s->cookie_rx[i], i);
73a19e4c
GL		 1297 }
1298
1299 s->active_rx = s->cookie_rx[0];
1300
1301 dma_async_issue_pending(chan);
1302}
1303
1304static void work_fn_rx(struct work_struct *work)
1305{
1306 struct sci_port *s = container_of(work, struct sci_port, work_rx);
1307 struct uart_port *port = &s->port;
1308 struct dma_async_tx_descriptor *desc;
1309 int new;
1310
1311 if (s->active_rx == s->cookie_rx[0]) {
1312 new = 0;
1313 } else if (s->active_rx == s->cookie_rx[1]) {
1314 new = 1;
1315 } else {
1316 dev_err(port->dev, "cookie %d not found!\n", s->active_rx);
1317 return;
1318 }
1319 desc = s->desc_rx[new];
1320
1321 if (dma_async_is_tx_complete(s->chan_rx, s->active_rx, NULL, NULL) !=
1322 DMA_SUCCESS) {
1323 /* Handle incomplete DMA receive */
1324 struct tty_struct *tty = port->state->port.tty;
1325 struct dma_chan *chan = s->chan_rx;
1326 struct sh_desc *sh_desc = container_of(desc, struct sh_desc,
1327 async_tx);
1328 unsigned long flags;
1329 int count;
1330
05827630 1331 chan->device->device_control(chan, DMA_TERMINATE_ALL, 0);
73a19e4c
GL		 1332 dev_dbg(port->dev, "Read %u bytes with cookie %d\n",
1333 sh_desc->partial, sh_desc->cookie);
1334
1335 spin_lock_irqsave(&port->lock, flags);
1336 count = sci_dma_rx_push(s, tty, sh_desc->partial);
1337 spin_unlock_irqrestore(&port->lock, flags);
1338
1339 if (count)
1340 tty_flip_buffer_push(tty);
1341
1342 sci_submit_rx(s);
1343
1344 return;
1345 }
1346
1347 s->cookie_rx[new] = desc->tx_submit(desc);
1348 if (s->cookie_rx[new] < 0) {
1349 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
1350 sci_rx_dma_release(s, true);
1351 return;
1352 }
1353
73a19e4c 1354 s->active_rx = s->cookie_rx[!new];
3089f381
GL		 1355
1356 dev_dbg(port->dev, "%s: cookie %d #%d, new active #%d\n", __func__,
1357 s->cookie_rx[new], new, s->active_rx);
73a19e4c
GL		 1358}
1359
1360static void work_fn_tx(struct work_struct *work)
1361{
1362 struct sci_port *s = container_of(work, struct sci_port, work_tx);
1363 struct dma_async_tx_descriptor *desc;
1364 struct dma_chan *chan = s->chan_tx;
1365 struct uart_port *port = &s->port;
1366 struct circ_buf *xmit = &port->state->xmit;
1367 struct scatterlist *sg = &s->sg_tx;
1368
1369 /*
1370 * DMA is idle now.
1371 * Port xmit buffer is already mapped, and it is one page... Just adjust
1372 * offsets and lengths. Since it is a circular buffer, we have to
1373 * transmit till the end, and then the rest. Take the port lock to get a
1374 * consistent xmit buffer state.
1375 */
1376 spin_lock_irq(&port->lock);
1377 sg->offset = xmit->tail & (UART_XMIT_SIZE - 1);
f354a381 1378 sg_dma_address(sg) = (sg_dma_address(sg) & ~(UART_XMIT_SIZE - 1)) +
73a19e4c 1379 sg->offset;
f354a381 1380 sg_dma_len(sg) = min((int)CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE),
73a19e4c 1381 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE));
73a19e4c
GL		 1382 spin_unlock_irq(&port->lock);
1383
f354a381 1384 BUG_ON(!sg_dma_len(sg));
73a19e4c
GL		 1385
1386 desc = chan->device->device_prep_slave_sg(chan,
1387 sg, s->sg_len_tx, DMA_TO_DEVICE,
1388 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1389 if (!desc) {
1390 /* switch to PIO */
1391 sci_tx_dma_release(s, true);
1392 return;
1393 }
1394
1395 dma_sync_sg_for_device(port->dev, sg, 1, DMA_TO_DEVICE);
1396
1397 spin_lock_irq(&port->lock);
1398 s->desc_tx = desc;
1399 desc->callback = sci_dma_tx_complete;
1400 desc->callback_param = s;
1401 spin_unlock_irq(&port->lock);
1402 s->cookie_tx = desc->tx_submit(desc);
1403 if (s->cookie_tx < 0) {
1404 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
1405 /* switch to PIO */
1406 sci_tx_dma_release(s, true);
1407 return;
1408 }
1409
1410 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n", __func__,
1411 xmit->buf, xmit->tail, xmit->head, s->cookie_tx);
1412
1413 dma_async_issue_pending(chan);
1414}
1415#endif
1416
b129a8cc 1417static void sci_start_tx(struct uart_port *port)
1da177e4 1418{
3089f381 1419 struct sci_port *s = to_sci_port(port);
e108b2ca 1420 unsigned short ctrl;
1da177e4 1421
73a19e4c 1422#ifdef CONFIG_SERIAL_SH_SCI_DMA
d1d4b10c 1423 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
3089f381
GL		 1424 u16 new, scr = sci_in(port, SCSCR);
1425 if (s->chan_tx)
1426 new = scr | 0x8000;
1427 else
1428 new = scr & ~0x8000;
1429 if (new != scr)
1430 sci_out(port, SCSCR, new);
73a19e4c 1431 }
f43dc23d 1432
3089f381
GL		 1433 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) &&
1434 s->cookie_tx < 0)
1435 schedule_work(&s->work_tx);
73a19e4c 1436#endif
f43dc23d 1437
d1d4b10c 1438 if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
3089f381
GL		 1439 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
1440 ctrl = sci_in(port, SCSCR);
f43dc23d 1441 sci_out(port, SCSCR, ctrl | SCSCR_TIE);
3089f381 1442 }
1da177e4
LT		 1443}
1444
b129a8cc 1445static void sci_stop_tx(struct uart_port *port)
1da177e4 1446{
1da177e4
LT		 1447 unsigned short ctrl;
1448
1449 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
1da177e4 1450 ctrl = sci_in(port, SCSCR);
f43dc23d 1451
d1d4b10c 1452 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
3089f381 1453 ctrl &= ~0x8000;
f43dc23d 1454
8e698614 1455 ctrl &= ~SCSCR_TIE;
f43dc23d 1456
1da177e4 1457 sci_out(port, SCSCR, ctrl);
1da177e4
LT		 1458}
1459
73a19e4c 1460static void sci_start_rx(struct uart_port *port)
1da177e4 1461{
1da177e4
LT		 1462 unsigned short ctrl;
1463
f43dc23d 1464 ctrl = sci_in(port, SCSCR) | port_rx_irq_mask(port);
1da177e4 1465
d1d4b10c 1466 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
3089f381 1467 ctrl &= ~0x4000;
f43dc23d 1468
1da177e4 1469 sci_out(port, SCSCR, ctrl);
1da177e4
LT		 1470}
1471
1472static void sci_stop_rx(struct uart_port *port)
1473{
1da177e4
LT		 1474 unsigned short ctrl;
1475
1da177e4 1476 ctrl = sci_in(port, SCSCR);
f43dc23d 1477
d1d4b10c 1478 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
3089f381 1479 ctrl &= ~0x4000;
f43dc23d
PM		 1480
1481 ctrl &= ~port_rx_irq_mask(port);
1482
1da177e4 1483 sci_out(port, SCSCR, ctrl);
1da177e4
LT		 1484}
1485
1486static void sci_enable_ms(struct uart_port *port)
1487{
d39ec6ce
PM		 1488 /*
1489 * Not supported by hardware, always a nop.
1490 */
1da177e4
LT		 1491}
1492
1493static void sci_break_ctl(struct uart_port *port, int break_state)
1494{
d39ec6ce
PM		 1495 /*
1496 * Not supported by hardware. Most parts couple break and rx
1497 * interrupts together, with break detection always enabled.
1498 */
1da177e4
LT		 1499}
1500
73a19e4c
GL		 1501#ifdef CONFIG_SERIAL_SH_SCI_DMA
1502static bool filter(struct dma_chan *chan, void *slave)
1503{
1504 struct sh_dmae_slave *param = slave;
1505
1506 dev_dbg(chan->device->dev, "%s: slave ID %d\n", __func__,
1507 param->slave_id);
1508
937bb6e4
GL		 1509 chan->private = param;
1510 return true;
73a19e4c
GL		 1511}
1512
1513static void rx_timer_fn(unsigned long arg)
1514{
1515 struct sci_port *s = (struct sci_port *)arg;
1516 struct uart_port *port = &s->port;
73a19e4c 1517 u16 scr = sci_in(port, SCSCR);
3089f381 1518
d1d4b10c 1519 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
3089f381 1520 scr &= ~0x4000;
ce6738b6 1521 enable_irq(s->cfg->irqs[1]);
3089f381 1522 }
f43dc23d 1523 sci_out(port, SCSCR, scr | SCSCR_RIE);
73a19e4c
GL		 1524 dev_dbg(port->dev, "DMA Rx timed out\n");
1525 schedule_work(&s->work_rx);
1526}
1527
1528static void sci_request_dma(struct uart_port *port)
1529{
1530 struct sci_port *s = to_sci_port(port);
1531 struct sh_dmae_slave *param;
1532 struct dma_chan *chan;
1533 dma_cap_mask_t mask;
1534 int nent;
1535
937bb6e4
GL		 1536 dev_dbg(port->dev, "%s: port %d\n", __func__,
1537 port->line);
73a19e4c 1538
937bb6e4 1539 if (s->cfg->dma_slave_tx <= 0 || s->cfg->dma_slave_rx <= 0)
73a19e4c
GL		 1540 return;
1541
1542 dma_cap_zero(mask);
1543 dma_cap_set(DMA_SLAVE, mask);
1544
1545 param = &s->param_tx;
1546
1547 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_TX */
ce6738b6 1548 param->slave_id = s->cfg->dma_slave_tx;
73a19e4c
GL		 1549
1550 s->cookie_tx = -EINVAL;
1551 chan = dma_request_channel(mask, filter, param);
1552 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
1553 if (chan) {
1554 s->chan_tx = chan;
1555 sg_init_table(&s->sg_tx, 1);
1556 /* UART circular tx buffer is an aligned page. */
1557 BUG_ON((int)port->state->xmit.buf & ~PAGE_MASK);
1558 sg_set_page(&s->sg_tx, virt_to_page(port->state->xmit.buf),
1559 UART_XMIT_SIZE, (int)port->state->xmit.buf & ~PAGE_MASK);
1560 nent = dma_map_sg(port->dev, &s->sg_tx, 1, DMA_TO_DEVICE);
1561 if (!nent)
1562 sci_tx_dma_release(s, false);
1563 else
1564 dev_dbg(port->dev, "%s: mapped %d@%p to %x\n", __func__,
1565 sg_dma_len(&s->sg_tx),
1566 port->state->xmit.buf, sg_dma_address(&s->sg_tx));
1567
1568 s->sg_len_tx = nent;
1569
1570 INIT_WORK(&s->work_tx, work_fn_tx);
1571 }
1572
1573 param = &s->param_rx;
1574
1575 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_RX */
ce6738b6 1576 param->slave_id = s->cfg->dma_slave_rx;
73a19e4c
GL		 1577
1578 chan = dma_request_channel(mask, filter, param);
1579 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan);
1580 if (chan) {
1581 dma_addr_t dma[2];
1582 void *buf[2];
1583 int i;
1584
1585 s->chan_rx = chan;
1586
1587 s->buf_len_rx = 2 * max(16, (int)port->fifosize);
1588 buf[0] = dma_alloc_coherent(port->dev, s->buf_len_rx * 2,
1589 &dma[0], GFP_KERNEL);
1590
1591 if (!buf[0]) {
1592 dev_warn(port->dev,
1593 "failed to allocate dma buffer, using PIO\n");
1594 sci_rx_dma_release(s, true);
1595 return;
1596 }
1597
1598 buf[1] = buf[0] + s->buf_len_rx;
1599 dma[1] = dma[0] + s->buf_len_rx;
1600
1601 for (i = 0; i < 2; i++) {
1602 struct scatterlist *sg = &s->sg_rx[i];
1603
1604 sg_init_table(sg, 1);
1605 sg_set_page(sg, virt_to_page(buf[i]), s->buf_len_rx,
1606 (int)buf[i] & ~PAGE_MASK);
f354a381 1607 sg_dma_address(sg) = dma[i];
73a19e4c
GL		 1608 }
1609
1610 INIT_WORK(&s->work_rx, work_fn_rx);
1611 setup_timer(&s->rx_timer, rx_timer_fn, (unsigned long)s);
1612
1613 sci_submit_rx(s);
1614 }
1615}
1616
1617static void sci_free_dma(struct uart_port *port)
1618{
1619 struct sci_port *s = to_sci_port(port);
1620
73a19e4c
GL		 1621 if (s->chan_tx)
1622 sci_tx_dma_release(s, false);
1623 if (s->chan_rx)
1624 sci_rx_dma_release(s, false);
1625}
27bd1075
PM		 1626#else
1627static inline void sci_request_dma(struct uart_port *port)
1628{
1629}
1630
1631static inline void sci_free_dma(struct uart_port *port)
1632{
1633}
73a19e4c
GL		 1634#endif
1635
1da177e4
LT		 1636static int sci_startup(struct uart_port *port)
1637{
a5660ada 1638 struct sci_port *s = to_sci_port(port);
073e84c9 1639 int ret;
1da177e4 1640
73a19e4c
GL		 1641 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1642
23241d43 1643 sci_port_enable(s);
1da177e4 1644
073e84c9
PM		 1645 ret = sci_request_irq(s);
1646 if (unlikely(ret < 0))
1647 return ret;
1648
73a19e4c 1649 sci_request_dma(port);
073e84c9 1650
d656901b 1651 sci_start_tx(port);
73a19e4c 1652 sci_start_rx(port);
1da177e4
LT		 1653
1654 return 0;
1655}
1656
1657static void sci_shutdown(struct uart_port *port)
1658{
a5660ada 1659 struct sci_port *s = to_sci_port(port);
1da177e4 1660
73a19e4c
GL		 1661 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1662
1da177e4 1663 sci_stop_rx(port);
b129a8cc 1664 sci_stop_tx(port);
073e84c9 1665
73a19e4c 1666 sci_free_dma(port);
1da177e4
LT		 1667 sci_free_irq(s);
1668
23241d43 1669 sci_port_disable(s);
1da177e4
LT		 1670}
1671
26c92f37
PM		 1672static unsigned int sci_scbrr_calc(unsigned int algo_id, unsigned int bps,
1673 unsigned long freq)
1674{
1675 switch (algo_id) {
1676 case SCBRR_ALGO_1:
1677 return ((freq + 16 * bps) / (16 * bps) - 1);
1678 case SCBRR_ALGO_2:
1679 return ((freq + 16 * bps) / (32 * bps) - 1);
1680 case SCBRR_ALGO_3:
1681 return (((freq * 2) + 16 * bps) / (16 * bps) - 1);
1682 case SCBRR_ALGO_4:
1683 return (((freq * 2) + 16 * bps) / (32 * bps) - 1);
1684 case SCBRR_ALGO_5:
1685 return (((freq * 1000 / 32) / bps) - 1);
1686 }
1687
1688 /* Warn, but use a safe default */
1689 WARN_ON(1);
e8183a6c 1690
26c92f37
PM		 1691 return ((freq + 16 * bps) / (32 * bps) - 1);
1692}
1693
1ba76220
MD		 1694static void sci_reset(struct uart_port *port)
1695{
0979e0e6 1696 struct plat_sci_reg *reg;
1ba76220
MD		 1697 unsigned int status;
1698
1699 do {
1700 status = sci_in(port, SCxSR);
1701 } while (!(status & SCxSR_TEND(port)));
1702
1703 sci_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */
1704
0979e0e6
PM		 1705 reg = sci_getreg(port, SCFCR);
1706 if (reg->size)
1ba76220
MD		 1707 sci_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
1708}
1709
606d099c
AC		 1710static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
1711 struct ktermios *old)
1da177e4 1712{
00b9de9c 1713 struct sci_port *s = to_sci_port(port);
0979e0e6 1714 struct plat_sci_reg *reg;
1ba76220 1715 unsigned int baud, smr_val, max_baud;
a2159b52 1716 int t = -1;
1da177e4 1717
154280fd
MD		 1718 /*
1719 * earlyprintk comes here early on with port->uartclk set to zero.
1720 * the clock framework is not up and running at this point so here
1721 * we assume that 115200 is the maximum baud rate. please note that
1722 * the baud rate is not programmed during earlyprintk - it is assumed
1723 * that the previous boot loader has enabled required clocks and
1724 * setup the baud rate generator hardware for us already.
1725 */
1726 max_baud = port->uartclk ? port->uartclk / 16 : 115200;
1da177e4 1727
154280fd
MD		 1728 baud = uart_get_baud_rate(port, termios, old, 0, max_baud);
1729 if (likely(baud && port->uartclk))
ce6738b6 1730 t = sci_scbrr_calc(s->cfg->scbrr_algo_id, baud, port->uartclk);
e108b2ca 1731
23241d43 1732 sci_port_enable(s);
36003386 1733
1ba76220 1734 sci_reset(port);
1da177e4
LT		 1735
1736 smr_val = sci_in(port, SCSMR) & 3;
e8183a6c 1737
1da177e4
LT		 1738 if ((termios->c_cflag & CSIZE) == CS7)
1739 smr_val |= 0x40;
1740 if (termios->c_cflag & PARENB)
1741 smr_val |= 0x20;
1742 if (termios->c_cflag & PARODD)
1743 smr_val |= 0x30;
1744 if (termios->c_cflag & CSTOPB)
1745 smr_val |= 0x08;
1746
1747 uart_update_timeout(port, termios->c_cflag, baud);
1748
1749 sci_out(port, SCSMR, smr_val);
1750
73a19e4c 1751 dev_dbg(port->dev, "%s: SMR %x, t %x, SCSCR %x\n", __func__, smr_val, t,
ce6738b6 1752 s->cfg->scscr);
73a19e4c 1753
1da177e4 1754 if (t > 0) {
e7c98dc7 1755 if (t >= 256) {
1da177e4
LT		 1756 sci_out(port, SCSMR, (sci_in(port, SCSMR) & ~3) | 1);
1757 t >>= 2;
e7c98dc7 1758 } else
1da177e4 1759 sci_out(port, SCSMR, sci_in(port, SCSMR) & ~3);
e7c98dc7 1760
1da177e4
LT		 1761 sci_out(port, SCBRR, t);
1762 udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */
1763 }
1764
d5701647 1765 sci_init_pins(port, termios->c_cflag);
0979e0e6
PM		 1766
1767 reg = sci_getreg(port, SCFCR);
1768 if (reg->size) {
1769 unsigned short ctrl;
1770
1771 ctrl = sci_in(port, SCFCR);
1772 if (termios->c_cflag & CRTSCTS)
1773 ctrl |= SCFCR_MCE;
1774 else
1775 ctrl &= ~SCFCR_MCE;
1776 sci_out(port, SCFCR, ctrl);
1777 }
b7a76e4b 1778
ce6738b6 1779 sci_out(port, SCSCR, s->cfg->scscr);
1da177e4 1780
3089f381
GL		 1781#ifdef CONFIG_SERIAL_SH_SCI_DMA
1782 /*
1783 * Calculate delay for 1.5 DMA buffers: see
1784 * drivers/serial/serial_core.c::uart_update_timeout(). With 10 bits
1785 * (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above function
1786 * calculates 1 jiffie for the data plus 5 jiffies for the "slop(e)."
1787 * Then below we calculate 3 jiffies (12ms) for 1.5 DMA buffers (3 FIFO
1788 * sizes), but it has been found out experimentally, that this is not
1789 * enough: the driver too often needlessly runs on a DMA timeout. 20ms
1790 * as a minimum seem to work perfectly.
1791 */
1792 if (s->chan_rx) {
1793 s->rx_timeout = (port->timeout - HZ / 50) * s->buf_len_rx * 3 /
1794 port->fifosize / 2;
1795 dev_dbg(port->dev,
1796 "DMA Rx t-out %ums, tty t-out %u jiffies\n",
1797 s->rx_timeout * 1000 / HZ, port->timeout);
1798 if (s->rx_timeout < msecs_to_jiffies(20))
1799 s->rx_timeout = msecs_to_jiffies(20);
1800 }
1801#endif
1802
1da177e4 1803 if ((termios->c_cflag & CREAD) != 0)
73a19e4c 1804 sci_start_rx(port);
36003386 1805
23241d43 1806 sci_port_disable(s);
1da177e4
LT		 1807}
1808
1809static const char *sci_type(struct uart_port *port)
1810{
1811 switch (port->type) {
e7c98dc7
MT		 1812 case PORT_IRDA:
1813 return "irda";
1814 case PORT_SCI:
1815 return "sci";
1816 case PORT_SCIF:
1817 return "scif";
1818 case PORT_SCIFA:
1819 return "scifa";
d1d4b10c
GL		 1820 case PORT_SCIFB:
1821 return "scifb";
1da177e4
LT		 1822 }
1823
fa43972f 1824 return NULL;
1da177e4
LT		 1825}
1826
e2651647 1827static inline unsigned long sci_port_size(struct uart_port *port)
1da177e4 1828{
e2651647
PM		 1829 /*
1830 * Pick an arbitrary size that encapsulates all of the base
1831 * registers by default. This can be optimized later, or derived
1832 * from platform resource data at such a time that ports begin to
1833 * behave more erratically.
1834 */
1835 return 64;
1da177e4
LT		 1836}
1837
f6e9495d
PM		 1838static int sci_remap_port(struct uart_port *port)
1839{
1840 unsigned long size = sci_port_size(port);
1841
1842 /*
1843 * Nothing to do if there's already an established membase.
1844 */
1845 if (port->membase)
1846 return 0;
1847
1848 if (port->flags & UPF_IOREMAP) {
1849 port->membase = ioremap_nocache(port->mapbase, size);
1850 if (unlikely(!port->membase)) {
1851 dev_err(port->dev, "can't remap port#%d\n", port->line);
1852 return -ENXIO;
1853 }
1854 } else {
1855 /*
1856 * For the simple (and majority of) cases where we don't
1857 * need to do any remapping, just cast the cookie
1858 * directly.
1859 */
1860 port->membase = (void __iomem *)port->mapbase;
1861 }
1862
1863 return 0;
1864}
1865
e2651647 1866static void sci_release_port(struct uart_port *port)
1da177e4 1867{
e2651647
PM		 1868 if (port->flags & UPF_IOREMAP) {
1869 iounmap(port->membase);
1870 port->membase = NULL;
1871 }
1872
1873 release_mem_region(port->mapbase, sci_port_size(port));
1da177e4
LT		 1874}
1875
e2651647 1876static int sci_request_port(struct uart_port *port)
1da177e4 1877{
e2651647
PM		 1878 unsigned long size = sci_port_size(port);
1879 struct resource *res;
f6e9495d 1880 int ret;
1da177e4 1881
1020520e 1882 res = request_mem_region(port->mapbase, size, dev_name(port->dev));
e2651647
PM		 1883 if (unlikely(res == NULL))
1884 return -EBUSY;
1da177e4 1885
f6e9495d
PM		 1886 ret = sci_remap_port(port);
1887 if (unlikely(ret != 0)) {
1888 release_resource(res);
1889 return ret;
7ff731ae 1890 }
e2651647
PM		 1891
1892 return 0;
1893}
1894
1895static void sci_config_port(struct uart_port *port, int flags)
1896{
1897 if (flags & UART_CONFIG_TYPE) {
1898 struct sci_port *sport = to_sci_port(port);
1899
1900 port->type = sport->cfg->type;
1901 sci_request_port(port);
1902 }
1da177e4
LT		 1903}
1904
1905static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
1906{
a5660ada 1907 struct sci_port *s = to_sci_port(port);
1da177e4 1908
ce6738b6 1909 if (ser->irq != s->cfg->irqs[SCIx_TXI_IRQ] || ser->irq > nr_irqs)
1da177e4
LT		 1910 return -EINVAL;
1911 if (ser->baud_base < 2400)
1912 /* No paper tape reader for Mitch.. */
1913 return -EINVAL;
1914
1915 return 0;
1916}
1917
1918static struct uart_ops sci_uart_ops = {
1919 .tx_empty = sci_tx_empty,
1920 .set_mctrl = sci_set_mctrl,
1921 .get_mctrl = sci_get_mctrl,
1922 .start_tx = sci_start_tx,
1923 .stop_tx = sci_stop_tx,
1924 .stop_rx = sci_stop_rx,
1925 .enable_ms = sci_enable_ms,
1926 .break_ctl = sci_break_ctl,
1927 .startup = sci_startup,
1928 .shutdown = sci_shutdown,
1929 .set_termios = sci_set_termios,
1930 .type = sci_type,
1931 .release_port = sci_release_port,
1932 .request_port = sci_request_port,
1933 .config_port = sci_config_port,
1934 .verify_port = sci_verify_port,
07d2a1a1
PM		 1935#ifdef CONFIG_CONSOLE_POLL
1936 .poll_get_char = sci_poll_get_char,
1937 .poll_put_char = sci_poll_put_char,
1938#endif
1da177e4
LT		 1939};
1940
c7ed1ab3
PM		 1941static int __devinit sci_init_single(struct platform_device *dev,
1942 struct sci_port *sci_port,
1943 unsigned int index,
1944 struct plat_sci_port *p)
e108b2ca 1945{
73a19e4c 1946 struct uart_port *port = &sci_port->port;
3127c6b2 1947 int ret;
e108b2ca 1948
73a19e4c
GL		 1949 port->ops = &sci_uart_ops;
1950 port->iotype = UPIO_MEM;
1951 port->line = index;
75136d48
MP		 1952
1953 switch (p->type) {
d1d4b10c
GL		 1954 case PORT_SCIFB:
1955 port->fifosize = 256;
1956 break;
75136d48 1957 case PORT_SCIFA:
73a19e4c 1958 port->fifosize = 64;
75136d48
MP		 1959 break;
1960 case PORT_SCIF:
73a19e4c 1961 port->fifosize = 16;
75136d48
MP		 1962 break;
1963 default:
73a19e4c 1964 port->fifosize = 1;
75136d48
MP		 1965 break;
1966 }
7b6fd3bf 1967
3127c6b2
PM		 1968 if (p->regtype == SCIx_PROBE_REGTYPE) {
1969 ret = sci_probe_regmap(p);
fc97114b 1970 if (unlikely(ret))
3127c6b2
PM		 1971 return ret;
1972 }
61a6976b 1973
7b6fd3bf 1974 if (dev) {
c7ed1ab3
PM		 1975 sci_port->iclk = clk_get(&dev->dev, "sci_ick");
1976 if (IS_ERR(sci_port->iclk)) {
1977 sci_port->iclk = clk_get(&dev->dev, "peripheral_clk");
1978 if (IS_ERR(sci_port->iclk)) {
1979 dev_err(&dev->dev, "can't get iclk\n");
1980 return PTR_ERR(sci_port->iclk);
1981 }
1982 }
1983
1984 /*
1985 * The function clock is optional, ignore it if we can't
1986 * find it.
1987 */
1988 sci_port->fclk = clk_get(&dev->dev, "sci_fck");
1989 if (IS_ERR(sci_port->fclk))
1990 sci_port->fclk = NULL;
1991
73a19e4c 1992 port->dev = &dev->dev;
5e50d2d6 1993
5a50a01b 1994 pm_runtime_irq_safe(&dev->dev);
5e50d2d6 1995 pm_runtime_enable(&dev->dev);
7b6fd3bf 1996 }
e108b2ca 1997
7ed7e071
MD		 1998 sci_port->break_timer.data = (unsigned long)sci_port;
1999 sci_port->break_timer.function = sci_break_timer;
2000 init_timer(&sci_port->break_timer);
2001
debf9507
PM		 2002 /*
2003 * Establish some sensible defaults for the error detection.
2004 */
2005 if (!p->error_mask)
2006 p->error_mask = (p->type == PORT_SCI) ?
2007 SCI_DEFAULT_ERROR_MASK : SCIF_DEFAULT_ERROR_MASK;
2008
2009 /*
2010 * Establish sensible defaults for the overrun detection, unless
2011 * the part has explicitly disabled support for it.
2012 */
2013 if (p->overrun_bit != SCIx_NOT_SUPPORTED) {
2014 if (p->type == PORT_SCI)
2015 p->overrun_bit = 5;
2016 else if (p->scbrr_algo_id == SCBRR_ALGO_4)
2017 p->overrun_bit = 9;
2018 else
2019 p->overrun_bit = 0;
2020
2021 /*
2022 * Make the error mask inclusive of overrun detection, if
2023 * supported.
2024 */
2025 p->error_mask |= (1 << p->overrun_bit);
2026 }
2027
ce6738b6 2028 sci_port->cfg = p;
7ed7e071 2029
ce6738b6
PM		 2030 port->mapbase = p->mapbase;
2031 port->type = p->type;
f43dc23d 2032 port->flags = p->flags;
61a6976b 2033 port->regshift = p->regshift;
73a19e4c 2034
ce6738b6 2035 /*
61a6976b 2036 * The UART port needs an IRQ value, so we peg this to the RX IRQ
ce6738b6
PM		 2037 * for the multi-IRQ ports, which is where we are primarily
2038 * concerned with the shutdown path synchronization.
2039 *
2040 * For the muxed case there's nothing more to do.
2041 */
54aa89ea 2042 port->irq = p->irqs[SCIx_RXI_IRQ];
9cfb5c05 2043 port->irqflags = 0;
73a19e4c 2044
61a6976b
PM		 2045 port->serial_in = sci_serial_in;
2046 port->serial_out = sci_serial_out;
2047
937bb6e4
GL		 2048 if (p->dma_slave_tx > 0 && p->dma_slave_rx > 0)
2049 dev_dbg(port->dev, "DMA tx %d, rx %d\n",
2050 p->dma_slave_tx, p->dma_slave_rx);
7ed7e071 2051
c7ed1ab3 2052 return 0;
e108b2ca
PM		 2053}
2054
1da177e4 2055#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
dc8e6f5b
MD		 2056static void serial_console_putchar(struct uart_port *port, int ch)
2057{
2058 sci_poll_put_char(port, ch);
2059}
2060
1da177e4
LT		 2061/*
2062 * Print a string to the serial port trying not to disturb
2063 * any possible real use of the port...
2064 */
2065static void serial_console_write(struct console *co, const char *s,
2066 unsigned count)
2067{
906b17dc
PM		 2068 struct sci_port *sci_port = &sci_ports[co->index];
2069 struct uart_port *port = &sci_port->port;
973e5d52 2070 unsigned short bits;
07d2a1a1 2071
23241d43 2072 sci_port_enable(sci_port);
501b825d
MD		 2073
2074 uart_console_write(port, s, count, serial_console_putchar);
973e5d52
MD		 2075
2076 /* wait until fifo is empty and last bit has been transmitted */
2077 bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
2078 while ((sci_in(port, SCxSR) & bits) != bits)
2079 cpu_relax();
501b825d 2080
23241d43 2081 sci_port_disable(sci_port);
1da177e4
LT		 2082}
2083
7b6fd3bf 2084static int __devinit serial_console_setup(struct console *co, char *options)
1da177e4 2085{
dc8e6f5b 2086 struct sci_port *sci_port;
1da177e4
LT		 2087 struct uart_port *port;
2088 int baud = 115200;
2089 int bits = 8;
2090 int parity = 'n';
2091 int flow = 'n';
2092 int ret;
2093
e108b2ca 2094 /*
906b17dc 2095 * Refuse to handle any bogus ports.
1da177e4 2096 */
906b17dc 2097 if (co->index < 0 || co->index >= SCI_NPORTS)
e108b2ca 2098 return -ENODEV;
e108b2ca 2099
906b17dc
PM		 2100 sci_port = &sci_ports[co->index];
2101 port = &sci_port->port;
2102
b2267a6b
AC		 2103 /*
2104 * Refuse to handle uninitialized ports.
2105 */
2106 if (!port->ops)
2107 return -ENODEV;
2108
f6e9495d
PM		 2109 ret = sci_remap_port(port);
2110 if (unlikely(ret != 0))
2111 return ret;
e108b2ca 2112
23241d43 2113 sci_port_enable(sci_port);
b7a76e4b 2114
1da177e4
LT		 2115 if (options)
2116 uart_parse_options(options, &baud, &parity, &bits, &flow);
2117
1ba76220
MD		 2118 sci_port_disable(sci_port);
2119
ab7cfb55 2120 return uart_set_options(port, co, baud, parity, bits, flow);
1da177e4
LT		 2121}
2122
2123static struct console serial_console = {
2124 .name = "ttySC",
906b17dc 2125 .device = uart_console_device,
1da177e4
LT		 2126 .write = serial_console_write,
2127 .setup = serial_console_setup,
fa5da2f7 2128 .flags = CON_PRINTBUFFER,
1da177e4 2129 .index = -1,
906b17dc 2130 .data = &sci_uart_driver,
1da177e4
LT		 2131};
2132
7b6fd3bf
MD		 2133static struct console early_serial_console = {
2134 .name = "early_ttySC",
2135 .write = serial_console_write,
2136 .flags = CON_PRINTBUFFER,
906b17dc 2137 .index = -1,
7b6fd3bf 2138};
ecdf8a46 2139
7b6fd3bf
MD		 2140static char early_serial_buf[32];
2141
ecdf8a46
PM		 2142static int __devinit sci_probe_earlyprintk(struct platform_device *pdev)
2143{
2144 struct plat_sci_port *cfg = pdev->dev.platform_data;
2145
2146 if (early_serial_console.data)
2147 return -EEXIST;
2148
2149 early_serial_console.index = pdev->id;
ecdf8a46 2150
906b17dc 2151 sci_init_single(NULL, &sci_ports[pdev->id], pdev->id, cfg);
ecdf8a46
PM		 2152
2153 serial_console_setup(&early_serial_console, early_serial_buf);
2154
2155 if (!strstr(early_serial_buf, "keep"))
2156 early_serial_console.flags |= CON_BOOT;
2157
2158 register_console(&early_serial_console);
2159 return 0;
2160}
6a8c9799 2161
1ba76220
MD		 2162#define uart_console(port) ((port)->cons->index == (port)->line)
2163
2164static int sci_runtime_suspend(struct device *dev)
2165{
2166 struct sci_port *sci_port = dev_get_drvdata(dev);
2167 struct uart_port *port = &sci_port->port;
2168
2169 if (uart_console(port)) {
0979e0e6
PM		 2170 struct plat_sci_reg *reg;
2171
1ba76220
MD		 2172 sci_port->saved_smr = sci_in(port, SCSMR);
2173 sci_port->saved_brr = sci_in(port, SCBRR);
0979e0e6
PM		 2174
2175 reg = sci_getreg(port, SCFCR);
2176 if (reg->size)
2177 sci_port->saved_fcr = sci_in(port, SCFCR);
2178 else
2179 sci_port->saved_fcr = 0;
1ba76220
MD		 2180 }
2181 return 0;
2182}
2183
2184static int sci_runtime_resume(struct device *dev)
2185{
2186 struct sci_port *sci_port = dev_get_drvdata(dev);
2187 struct uart_port *port = &sci_port->port;
2188
2189 if (uart_console(port)) {
2190 sci_reset(port);
2191 sci_out(port, SCSMR, sci_port->saved_smr);
2192 sci_out(port, SCBRR, sci_port->saved_brr);
0979e0e6
PM		 2193
2194 if (sci_port->saved_fcr)
2195 sci_out(port, SCFCR, sci_port->saved_fcr);
2196
1ba76220
MD		 2197 sci_out(port, SCSCR, sci_port->cfg->scscr);
2198 }
2199 return 0;
2200}
2201
6a8c9799
NI		 2202#define SCI_CONSOLE (&serial_console)
2203
ecdf8a46
PM		 2204#else
2205static inline int __devinit sci_probe_earlyprintk(struct platform_device *pdev)
2206{
2207 return -EINVAL;
2208}
1da177e4 2209
6a8c9799 2210#define SCI_CONSOLE NULL
1ba76220
MD		 2211#define sci_runtime_suspend NULL
2212#define sci_runtime_resume NULL
6a8c9799
NI		 2213
2214#endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
1da177e4
LT		 2215
2216static char banner[] __initdata =
2217 KERN_INFO "SuperH SCI(F) driver initialized\n";
2218
2219static struct uart_driver sci_uart_driver = {
2220 .owner = THIS_MODULE,
2221 .driver_name = "sci",
1da177e4
LT		 2222 .dev_name = "ttySC",
2223 .major = SCI_MAJOR,
2224 .minor = SCI_MINOR_START,
e108b2ca 2225 .nr = SCI_NPORTS,
1da177e4
LT		 2226 .cons = SCI_CONSOLE,
2227};
2228
54507f6e 2229static int sci_remove(struct platform_device *dev)
e552de24 2230{
d535a230 2231 struct sci_port *port = platform_get_drvdata(dev);
e552de24 2232
d535a230
PM		 2233 cpufreq_unregister_notifier(&port->freq_transition,
2234 CPUFREQ_TRANSITION_NOTIFIER);
e552de24 2235
d535a230
PM		 2236 uart_remove_one_port(&sci_uart_driver, &port->port);
2237
2238 clk_put(port->iclk);
2239 clk_put(port->fclk);
e552de24 2240
5e50d2d6 2241 pm_runtime_disable(&dev->dev);
e552de24
MD		 2242 return 0;
2243}
2244
0ee70712
MD		 2245static int __devinit sci_probe_single(struct platform_device *dev,
2246 unsigned int index,
2247 struct plat_sci_port *p,
2248 struct sci_port *sciport)
2249{
0ee70712
MD		 2250 int ret;
2251
2252 /* Sanity check */
2253 if (unlikely(index >= SCI_NPORTS)) {
2254 dev_notice(&dev->dev, "Attempting to register port "
2255 "%d when only %d are available.\n",
2256 index+1, SCI_NPORTS);
2257 dev_notice(&dev->dev, "Consider bumping "
2258 "CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
2259 return 0;
2260 }
2261
c7ed1ab3
PM		 2262 ret = sci_init_single(dev, sciport, index, p);
2263 if (ret)
2264 return ret;
0ee70712 2265
d535a230 2266 return uart_add_one_port(&sci_uart_driver, &sciport->port);
0ee70712
MD		 2267}
2268
e108b2ca 2269static int __devinit sci_probe(struct platform_device *dev)
1da177e4 2270{
e108b2ca 2271 struct plat_sci_port *p = dev->dev.platform_data;
d535a230 2272 struct sci_port *sp = &sci_ports[dev->id];
ecdf8a46 2273 int ret;
d535a230 2274
ecdf8a46
PM		 2275 /*
2276 * If we've come here via earlyprintk initialization, head off to
2277 * the special early probe. We don't have sufficient device state
2278 * to make it beyond this yet.
2279 */
2280 if (is_early_platform_device(dev))
2281 return sci_probe_earlyprintk(dev);
7b6fd3bf 2282
d535a230 2283 platform_set_drvdata(dev, sp);
e552de24 2284
906b17dc 2285 ret = sci_probe_single(dev, dev->id, p, sp);
d535a230
PM		 2286 if (ret)
2287 goto err_unreg;
e552de24 2288
d535a230 2289 sp->freq_transition.notifier_call = sci_notifier;
1da177e4 2290
d535a230
PM		 2291 ret = cpufreq_register_notifier(&sp->freq_transition,
2292 CPUFREQ_TRANSITION_NOTIFIER);
2293 if (unlikely(ret < 0))
2294 goto err_unreg;
1da177e4
LT		 2295
2296#ifdef CONFIG_SH_STANDARD_BIOS
2297 sh_bios_gdb_detach();
2298#endif
2299
e108b2ca 2300 return 0;
7ff731ae
PM		 2301
2302err_unreg:
e552de24 2303 sci_remove(dev);
7ff731ae 2304 return ret;
1da177e4
LT		 2305}
2306
6daa79b3 2307static int sci_suspend(struct device *dev)
1da177e4 2308{
d535a230 2309 struct sci_port *sport = dev_get_drvdata(dev);
e108b2ca 2310
d535a230
PM		 2311 if (sport)
2312 uart_suspend_port(&sci_uart_driver, &sport->port);
1da177e4 2313
e108b2ca
PM		 2314 return 0;
2315}
1da177e4 2316
6daa79b3 2317static int sci_resume(struct device *dev)
e108b2ca 2318{
d535a230 2319 struct sci_port *sport = dev_get_drvdata(dev);
e108b2ca 2320
d535a230
PM		 2321 if (sport)
2322 uart_resume_port(&sci_uart_driver, &sport->port);
e108b2ca
PM		 2323
2324 return 0;
2325}
2326
47145210 2327static const struct dev_pm_ops sci_dev_pm_ops = {
1ba76220
MD		 2328 .runtime_suspend = sci_runtime_suspend,
2329 .runtime_resume = sci_runtime_resume,
6daa79b3
PM		 2330 .suspend = sci_suspend,
2331 .resume = sci_resume,
2332};
2333
e108b2ca
PM		 2334static struct platform_driver sci_driver = {
2335 .probe = sci_probe,
b9e39c89 2336 .remove = sci_remove,
e108b2ca
PM		 2337 .driver = {
2338 .name = "sh-sci",
2339 .owner = THIS_MODULE,
6daa79b3 2340 .pm = &sci_dev_pm_ops,
e108b2ca
PM		 2341 },
2342};
2343
2344static int __init sci_init(void)
2345{
2346 int ret;
2347
2348 printk(banner);
2349
e108b2ca
PM		 2350 ret = uart_register_driver(&sci_uart_driver);
2351 if (likely(ret == 0)) {
2352 ret = platform_driver_register(&sci_driver);
2353 if (unlikely(ret))
2354 uart_unregister_driver(&sci_uart_driver);
2355 }
2356
2357 return ret;
2358}
2359
2360static void __exit sci_exit(void)
2361{
2362 platform_driver_unregister(&sci_driver);
1da177e4
LT		 2363 uart_unregister_driver(&sci_uart_driver);
2364}
2365
7b6fd3bf
MD		 2366#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
2367early_platform_init_buffer("earlyprintk", &sci_driver,
2368 early_serial_buf, ARRAY_SIZE(early_serial_buf));
2369#endif
1da177e4
LT		 2370module_init(sci_init);
2371module_exit(sci_exit);
2372
e108b2ca 2373MODULE_LICENSE("GPL");
e169c139 2374MODULE_ALIAS("platform:sh-sci");
7f405f9c
PM		 2375MODULE_AUTHOR("Paul Mundt");
2376MODULE_DESCRIPTION("SuperH SCI(F) serial driver");
Linux 6.x block layer and io_uring tree(s)