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serial: sh-sci: Remove manual break debouncing
[linux-block.git] / drivers / tty / serial / sh-sci.c
CommitLineData
1da177e4 1/*
1da177e4
LT		 2 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
3 *
f43dc23d 4 * Copyright (C) 2002 - 2011 Paul Mundt
f4998e55 5 * Copyright (C) 2015 Glider bvba
3ea6bc3d 6 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
1da177e4
LT		 7 *
8 * based off of the old drivers/char/sh-sci.c by:
9 *
10 * Copyright (C) 1999, 2000 Niibe Yutaka
11 * Copyright (C) 2000 Sugioka Toshinobu
12 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
13 * Modified to support SecureEdge. David McCullough (2002)
14 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
d89ddd1c 15 * Removed SH7300 support (Jul 2007).
1da177e4
LT		 16 *
17 * This file is subject to the terms and conditions of the GNU General Public
18 * License. See the file "COPYING" in the main directory of this archive
19 * for more details.
20 */
0b3d4ef6
PM		 21#if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
22#define SUPPORT_SYSRQ
23#endif
1da177e4
LT		 24
25#undef DEBUG
26
8fb9631c
LP		 27#include <linux/clk.h>
28#include <linux/console.h>
29#include <linux/ctype.h>
30#include <linux/cpufreq.h>
31#include <linux/delay.h>
32#include <linux/dmaengine.h>
33#include <linux/dma-mapping.h>
34#include <linux/err.h>
1da177e4 35#include <linux/errno.h>
8fb9631c 36#include <linux/init.h>
1da177e4 37#include <linux/interrupt.h>
1da177e4 38#include <linux/ioport.h>
8fb9631c
LP		 39#include <linux/major.h>
40#include <linux/module.h>
1da177e4 41#include <linux/mm.h>
20bdcab8 42#include <linux/of.h>
8fb9631c 43#include <linux/platform_device.h>
5e50d2d6 44#include <linux/pm_runtime.h>
73a19e4c 45#include <linux/scatterlist.h>
8fb9631c
LP		 46#include <linux/serial.h>
47#include <linux/serial_sci.h>
48#include <linux/sh_dma.h>
5a0e3ad6 49#include <linux/slab.h>
8fb9631c
LP		 50#include <linux/string.h>
51#include <linux/sysrq.h>
52#include <linux/timer.h>
53#include <linux/tty.h>
54#include <linux/tty_flip.h>
85f094ec
PM		 55
56#ifdef CONFIG_SUPERH
1da177e4
LT		 57#include <asm/sh_bios.h>
58#endif
59
f907c9ea 60#include "serial_mctrl_gpio.h"
1da177e4
LT		 61#include "sh-sci.h"
62
89b5c1ab
LP		 63/* Offsets into the sci_port->irqs array */
64enum {
65 SCIx_ERI_IRQ,
66 SCIx_RXI_IRQ,
67 SCIx_TXI_IRQ,
68 SCIx_BRI_IRQ,
69 SCIx_NR_IRQS,
70
71 SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */
72};
73
74#define SCIx_IRQ_IS_MUXED(port) \
75 ((port)->irqs[SCIx_ERI_IRQ] == \
76 (port)->irqs[SCIx_RXI_IRQ]) || \
77 ((port)->irqs[SCIx_ERI_IRQ] && \
78 ((port)->irqs[SCIx_RXI_IRQ] < 0))
79
f4998e55
GU		 80enum SCI_CLKS {
81 SCI_FCK, /* Functional Clock */
6af27bf2 82 SCI_SCK, /* Optional External Clock */
1270f865
GU		 83 SCI_BRG_INT, /* Optional BRG Internal Clock Source */
84 SCI_SCIF_CLK, /* Optional BRG External Clock Source */
f4998e55
GU		 85 SCI_NUM_CLKS
86};
87
69eee8e9
GU		 88/* Bit x set means sampling rate x + 1 is supported */
89#define SCI_SR(x) BIT((x) - 1)
90#define SCI_SR_RANGE(x, y) GENMASK((y) - 1, (x) - 1)
91
92a05748
GU		 92#define SCI_SR_SCIFAB SCI_SR(5) | SCI_SR(7) | SCI_SR(11) | \
93 SCI_SR(13) | SCI_SR(16) | SCI_SR(17) | \
94 SCI_SR(19) | SCI_SR(27)
95
69eee8e9
GU		 96#define min_sr(_port) ffs((_port)->sampling_rate_mask)
97#define max_sr(_port) fls((_port)->sampling_rate_mask)
98
99/* Iterate over all supported sampling rates, from high to low */
100#define for_each_sr(_sr, _port) \
101 for ((_sr) = max_sr(_port); (_sr) >= min_sr(_port); (_sr)--) \
102 if ((_port)->sampling_rate_mask & SCI_SR((_sr)))
103
e095ee6b
LP		 104struct plat_sci_reg {
105 u8 offset, size;
106};
107
108struct sci_port_params {
109 const struct plat_sci_reg regs[SCIx_NR_REGS];
b2f20ed9
LP		 110 unsigned int fifosize;
111 unsigned int overrun_reg;
112 unsigned int overrun_mask;
113 unsigned int sampling_rate_mask;
114 unsigned int error_mask;
115 unsigned int error_clear;
e095ee6b
LP		 116};
117
e108b2ca
PM		 118struct sci_port {
119 struct uart_port port;
120
ce6738b6 121 /* Platform configuration */
e095ee6b 122 const struct sci_port_params *params;
daf5a895 123 const struct plat_sci_port *cfg;
69eee8e9 124 unsigned int sampling_rate_mask;
e4d6f911 125 resource_size_t reg_size;
f907c9ea 126 struct mctrl_gpios *gpios;
e108b2ca 127
f4998e55
GU		 128 /* Clocks */
129 struct clk *clks[SCI_NUM_CLKS];
130 unsigned long clk_rates[SCI_NUM_CLKS];
edad1f20 131
1fcc91a6 132 int irqs[SCIx_NR_IRQS];
9174fc8f
PM		 133 char *irqstr[SCIx_NR_IRQS];
134
73a19e4c
GL		 135 struct dma_chan *chan_tx;
136 struct dma_chan *chan_rx;
f43dc23d 137
73a19e4c 138#ifdef CONFIG_SERIAL_SH_SCI_DMA
73a19e4c
GL		 139 dma_cookie_t cookie_tx;
140 dma_cookie_t cookie_rx[2];
141 dma_cookie_t active_rx;
79904420
GU		 142 dma_addr_t tx_dma_addr;
143 unsigned int tx_dma_len;
73a19e4c 144 struct scatterlist sg_rx[2];
7b39d901 145 void *rx_buf[2];
73a19e4c 146 size_t buf_len_rx;
73a19e4c 147 struct work_struct work_tx;
73a19e4c 148 struct timer_list rx_timer;
3089f381 149 unsigned int rx_timeout;
73a19e4c 150#endif
33f50ffc
GU		 151
152 bool autorts;
e108b2ca
PM		 153};
154
e108b2ca 155#define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
b7a76e4b 156
e108b2ca
PM		 157static struct sci_port sci_ports[SCI_NPORTS];
158static struct uart_driver sci_uart_driver;
1da177e4 159
e7c98dc7
MT		 160static inline struct sci_port *
161to_sci_port(struct uart_port *uart)
162{
163 return container_of(uart, struct sci_port, port);
164}
165
e095ee6b 166static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = {
61a6976b
PM		 167 /*
168 * Common SCI definitions, dependent on the port's regshift
169 * value.
170 */
171 [SCIx_SCI_REGTYPE] = {
e095ee6b
LP		 172 .regs = {
173 [SCSMR] = { 0x00, 8 },
174 [SCBRR] = { 0x01, 8 },
175 [SCSCR] = { 0x02, 8 },
176 [SCxTDR] = { 0x03, 8 },
177 [SCxSR] = { 0x04, 8 },
178 [SCxRDR] = { 0x05, 8 },
179 },
b2f20ed9
LP		 180 .fifosize = 1,
181 .overrun_reg = SCxSR,
182 .overrun_mask = SCI_ORER,
183 .sampling_rate_mask = SCI_SR(32),
184 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER,
185 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER,
61a6976b
PM		 186 },
187
188 /*
a752ba18 189 * Common definitions for legacy IrDA ports.
61a6976b
PM		 190 */
191 [SCIx_IRDA_REGTYPE] = {
e095ee6b
LP		 192 .regs = {
193 [SCSMR] = { 0x00, 8 },
194 [SCBRR] = { 0x02, 8 },
195 [SCSCR] = { 0x04, 8 },
196 [SCxTDR] = { 0x06, 8 },
197 [SCxSR] = { 0x08, 16 },
198 [SCxRDR] = { 0x0a, 8 },
199 [SCFCR] = { 0x0c, 8 },
200 [SCFDR] = { 0x0e, 16 },
201 },
b2f20ed9
LP		 202 .fifosize = 1,
203 .overrun_reg = SCxSR,
204 .overrun_mask = SCI_ORER,
205 .sampling_rate_mask = SCI_SR(32),
206 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER,
207 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER,
61a6976b
PM		 208 },
209
210 /*
211 * Common SCIFA definitions.
212 */
213 [SCIx_SCIFA_REGTYPE] = {
e095ee6b
LP		 214 .regs = {
215 [SCSMR] = { 0x00, 16 },
216 [SCBRR] = { 0x04, 8 },
217 [SCSCR] = { 0x08, 16 },
218 [SCxTDR] = { 0x20, 8 },
219 [SCxSR] = { 0x14, 16 },
220 [SCxRDR] = { 0x24, 8 },
221 [SCFCR] = { 0x18, 16 },
222 [SCFDR] = { 0x1c, 16 },
223 [SCPCR] = { 0x30, 16 },
224 [SCPDR] = { 0x34, 16 },
225 },
b2f20ed9
LP		 226 .fifosize = 64,
227 .overrun_reg = SCxSR,
228 .overrun_mask = SCIFA_ORER,
229 .sampling_rate_mask = SCI_SR_SCIFAB,
230 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
231 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
61a6976b
PM		 232 },
233
234 /*
235 * Common SCIFB definitions.
236 */
237 [SCIx_SCIFB_REGTYPE] = {
e095ee6b
LP		 238 .regs = {
239 [SCSMR] = { 0x00, 16 },
240 [SCBRR] = { 0x04, 8 },
241 [SCSCR] = { 0x08, 16 },
242 [SCxTDR] = { 0x40, 8 },
243 [SCxSR] = { 0x14, 16 },
244 [SCxRDR] = { 0x60, 8 },
245 [SCFCR] = { 0x18, 16 },
246 [SCTFDR] = { 0x38, 16 },
247 [SCRFDR] = { 0x3c, 16 },
248 [SCPCR] = { 0x30, 16 },
249 [SCPDR] = { 0x34, 16 },
250 },
b2f20ed9
LP		 251 .fifosize = 256,
252 .overrun_reg = SCxSR,
253 .overrun_mask = SCIFA_ORER,
254 .sampling_rate_mask = SCI_SR_SCIFAB,
255 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
256 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
61a6976b
PM		 257 },
258
3af1f8a4
PE		 259 /*
260 * Common SH-2(A) SCIF definitions for ports with FIFO data
261 * count registers.
262 */
263 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = {
e095ee6b
LP		 264 .regs = {
265 [SCSMR] = { 0x00, 16 },
266 [SCBRR] = { 0x04, 8 },
267 [SCSCR] = { 0x08, 16 },
268 [SCxTDR] = { 0x0c, 8 },
269 [SCxSR] = { 0x10, 16 },
270 [SCxRDR] = { 0x14, 8 },
271 [SCFCR] = { 0x18, 16 },
272 [SCFDR] = { 0x1c, 16 },
273 [SCSPTR] = { 0x20, 16 },
274 [SCLSR] = { 0x24, 16 },
275 },
b2f20ed9
LP		 276 .fifosize = 16,
277 .overrun_reg = SCLSR,
278 .overrun_mask = SCLSR_ORER,
279 .sampling_rate_mask = SCI_SR(32),
280 .error_mask = SCIF_DEFAULT_ERROR_MASK,
281 .error_clear = SCIF_ERROR_CLEAR,
3af1f8a4
PE		 282 },
283
61a6976b
PM		 284 /*
285 * Common SH-3 SCIF definitions.
286 */
287 [SCIx_SH3_SCIF_REGTYPE] = {
e095ee6b
LP		 288 .regs = {
289 [SCSMR] = { 0x00, 8 },
290 [SCBRR] = { 0x02, 8 },
291 [SCSCR] = { 0x04, 8 },
292 [SCxTDR] = { 0x06, 8 },
293 [SCxSR] = { 0x08, 16 },
294 [SCxRDR] = { 0x0a, 8 },
295 [SCFCR] = { 0x0c, 8 },
296 [SCFDR] = { 0x0e, 16 },
297 },
b2f20ed9
LP		 298 .fifosize = 16,
299 .overrun_reg = SCLSR,
300 .overrun_mask = SCLSR_ORER,
301 .sampling_rate_mask = SCI_SR(32),
302 .error_mask = SCIF_DEFAULT_ERROR_MASK,
303 .error_clear = SCIF_ERROR_CLEAR,
61a6976b
PM		 304 },
305
306 /*
307 * Common SH-4(A) SCIF(B) definitions.
308 */
309 [SCIx_SH4_SCIF_REGTYPE] = {
e095ee6b
LP		 310 .regs = {
311 [SCSMR] = { 0x00, 16 },
312 [SCBRR] = { 0x04, 8 },
313 [SCSCR] = { 0x08, 16 },
314 [SCxTDR] = { 0x0c, 8 },
315 [SCxSR] = { 0x10, 16 },
316 [SCxRDR] = { 0x14, 8 },
317 [SCFCR] = { 0x18, 16 },
318 [SCFDR] = { 0x1c, 16 },
319 [SCSPTR] = { 0x20, 16 },
320 [SCLSR] = { 0x24, 16 },
321 },
b2f20ed9
LP		 322 .fifosize = 16,
323 .overrun_reg = SCLSR,
324 .overrun_mask = SCLSR_ORER,
325 .sampling_rate_mask = SCI_SR(32),
326 .error_mask = SCIF_DEFAULT_ERROR_MASK,
327 .error_clear = SCIF_ERROR_CLEAR,
b8bbd6b2
GU		 328 },
329
330 /*
331 * Common SCIF definitions for ports with a Baud Rate Generator for
332 * External Clock (BRG).
333 */
334 [SCIx_SH4_SCIF_BRG_REGTYPE] = {
e095ee6b
LP		 335 .regs = {
336 [SCSMR] = { 0x00, 16 },
337 [SCBRR] = { 0x04, 8 },
338 [SCSCR] = { 0x08, 16 },
339 [SCxTDR] = { 0x0c, 8 },
340 [SCxSR] = { 0x10, 16 },
341 [SCxRDR] = { 0x14, 8 },
342 [SCFCR] = { 0x18, 16 },
343 [SCFDR] = { 0x1c, 16 },
344 [SCSPTR] = { 0x20, 16 },
345 [SCLSR] = { 0x24, 16 },
346 [SCDL] = { 0x30, 16 },
347 [SCCKS] = { 0x34, 16 },
348 },
b2f20ed9
LP		 349 .fifosize = 16,
350 .overrun_reg = SCLSR,
351 .overrun_mask = SCLSR_ORER,
352 .sampling_rate_mask = SCI_SR(32),
353 .error_mask = SCIF_DEFAULT_ERROR_MASK,
354 .error_clear = SCIF_ERROR_CLEAR,
f303b364
UH		 355 },
356
357 /*
358 * Common HSCIF definitions.
359 */
360 [SCIx_HSCIF_REGTYPE] = {
e095ee6b
LP		 361 .regs = {
362 [SCSMR] = { 0x00, 16 },
363 [SCBRR] = { 0x04, 8 },
364 [SCSCR] = { 0x08, 16 },
365 [SCxTDR] = { 0x0c, 8 },
366 [SCxSR] = { 0x10, 16 },
367 [SCxRDR] = { 0x14, 8 },
368 [SCFCR] = { 0x18, 16 },
369 [SCFDR] = { 0x1c, 16 },
370 [SCSPTR] = { 0x20, 16 },
371 [SCLSR] = { 0x24, 16 },
372 [HSSRR] = { 0x40, 16 },
373 [SCDL] = { 0x30, 16 },
374 [SCCKS] = { 0x34, 16 },
375 },
b2f20ed9
LP		 376 .fifosize = 128,
377 .overrun_reg = SCLSR,
378 .overrun_mask = SCLSR_ORER,
379 .sampling_rate_mask = SCI_SR_RANGE(8, 32),
380 .error_mask = SCIF_DEFAULT_ERROR_MASK,
381 .error_clear = SCIF_ERROR_CLEAR,
61a6976b
PM		 382 },
383
384 /*
385 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR
386 * register.
387 */
388 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = {
e095ee6b
LP		 389 .regs = {
390 [SCSMR] = { 0x00, 16 },
391 [SCBRR] = { 0x04, 8 },
392 [SCSCR] = { 0x08, 16 },
393 [SCxTDR] = { 0x0c, 8 },
394 [SCxSR] = { 0x10, 16 },
395 [SCxRDR] = { 0x14, 8 },
396 [SCFCR] = { 0x18, 16 },
397 [SCFDR] = { 0x1c, 16 },
398 [SCLSR] = { 0x24, 16 },
399 },
b2f20ed9
LP		 400 .fifosize = 16,
401 .overrun_reg = SCLSR,
402 .overrun_mask = SCLSR_ORER,
403 .sampling_rate_mask = SCI_SR(32),
404 .error_mask = SCIF_DEFAULT_ERROR_MASK,
405 .error_clear = SCIF_ERROR_CLEAR,
61a6976b
PM		 406 },
407
408 /*
409 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data
410 * count registers.
411 */
412 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = {
e095ee6b
LP		 413 .regs = {
414 [SCSMR] = { 0x00, 16 },
415 [SCBRR] = { 0x04, 8 },
416 [SCSCR] = { 0x08, 16 },
417 [SCxTDR] = { 0x0c, 8 },
418 [SCxSR] = { 0x10, 16 },
419 [SCxRDR] = { 0x14, 8 },
420 [SCFCR] = { 0x18, 16 },
421 [SCFDR] = { 0x1c, 16 },
422 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */
423 [SCRFDR] = { 0x20, 16 },
424 [SCSPTR] = { 0x24, 16 },
425 [SCLSR] = { 0x28, 16 },
426 },
b2f20ed9
LP		 427 .fifosize = 16,
428 .overrun_reg = SCLSR,
429 .overrun_mask = SCLSR_ORER,
430 .sampling_rate_mask = SCI_SR(32),
431 .error_mask = SCIF_DEFAULT_ERROR_MASK,
432 .error_clear = SCIF_ERROR_CLEAR,
61a6976b
PM		 433 },
434
435 /*
436 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR
437 * registers.
438 */
439 [SCIx_SH7705_SCIF_REGTYPE] = {
e095ee6b
LP		 440 .regs = {
441 [SCSMR] = { 0x00, 16 },
442 [SCBRR] = { 0x04, 8 },
443 [SCSCR] = { 0x08, 16 },
444 [SCxTDR] = { 0x20, 8 },
445 [SCxSR] = { 0x14, 16 },
446 [SCxRDR] = { 0x24, 8 },
447 [SCFCR] = { 0x18, 16 },
448 [SCFDR] = { 0x1c, 16 },
449 },
b2f20ed9
LP		 450 .fifosize = 16,
451 .overrun_reg = SCxSR,
452 .overrun_mask = SCIFA_ORER,
453 .sampling_rate_mask = SCI_SR(16),
454 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
455 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
61a6976b
PM		 456 },
457};
458
e095ee6b 459#define sci_getreg(up, offset) (&to_sci_port(up)->params->regs[offset])
72b294cf 460
61a6976b
PM		 461/*
462 * The "offset" here is rather misleading, in that it refers to an enum
463 * value relative to the port mapping rather than the fixed offset
464 * itself, which needs to be manually retrieved from the platform's
465 * register map for the given port.
466 */
467static unsigned int sci_serial_in(struct uart_port *p, int offset)
468{
d3184e68 469 const struct plat_sci_reg *reg = sci_getreg(p, offset);
61a6976b
PM		 470
471 if (reg->size == 8)
472 return ioread8(p->membase + (reg->offset << p->regshift));
473 else if (reg->size == 16)
474 return ioread16(p->membase + (reg->offset << p->regshift));
475 else
476 WARN(1, "Invalid register access\n");
477
478 return 0;
479}
480
481static void sci_serial_out(struct uart_port *p, int offset, int value)
482{
d3184e68 483 const struct plat_sci_reg *reg = sci_getreg(p, offset);
61a6976b
PM		 484
485 if (reg->size == 8)
486 iowrite8(value, p->membase + (reg->offset << p->regshift));
487 else if (reg->size == 16)
488 iowrite16(value, p->membase + (reg->offset << p->regshift));
489 else
490 WARN(1, "Invalid register access\n");
491}
492
23241d43
PM		 493static void sci_port_enable(struct sci_port *sci_port)
494{
f4998e55
GU		 495 unsigned int i;
496
23241d43
PM		 497 if (!sci_port->port.dev)
498 return;
499
500 pm_runtime_get_sync(sci_port->port.dev);
501
f4998e55
GU		 502 for (i = 0; i < SCI_NUM_CLKS; i++) {
503 clk_prepare_enable(sci_port->clks[i]);
504 sci_port->clk_rates[i] = clk_get_rate(sci_port->clks[i]);
505 }
506 sci_port->port.uartclk = sci_port->clk_rates[SCI_FCK];
23241d43
PM		 507}
508
509static void sci_port_disable(struct sci_port *sci_port)
510{
f4998e55
GU		 511 unsigned int i;
512
23241d43
PM		 513 if (!sci_port->port.dev)
514 return;
515
f4998e55
GU		 516 for (i = SCI_NUM_CLKS; i-- > 0; )
517 clk_disable_unprepare(sci_port->clks[i]);
23241d43
PM		 518
519 pm_runtime_put_sync(sci_port->port.dev);
520}
521
e1910fcd
GU		 522static inline unsigned long port_rx_irq_mask(struct uart_port *port)
523{
524 /*
525 * Not all ports (such as SCIFA) will support REIE. Rather than
526 * special-casing the port type, we check the port initialization
527 * IRQ enable mask to see whether the IRQ is desired at all. If
528 * it's unset, it's logically inferred that there's no point in
529 * testing for it.
530 */
531 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE);
532}
533
534static void sci_start_tx(struct uart_port *port)
535{
536 struct sci_port *s = to_sci_port(port);
537 unsigned short ctrl;
538
539#ifdef CONFIG_SERIAL_SH_SCI_DMA
540 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
541 u16 new, scr = serial_port_in(port, SCSCR);
542 if (s->chan_tx)
543 new = scr | SCSCR_TDRQE;
544 else
545 new = scr & ~SCSCR_TDRQE;
546 if (new != scr)
547 serial_port_out(port, SCSCR, new);
548 }
549
550 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) &&
551 dma_submit_error(s->cookie_tx)) {
552 s->cookie_tx = 0;
553 schedule_work(&s->work_tx);
554 }
555#endif
556
557 if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
558 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
559 ctrl = serial_port_in(port, SCSCR);
560 serial_port_out(port, SCSCR, ctrl | SCSCR_TIE);
561 }
562}
563
564static void sci_stop_tx(struct uart_port *port)
565{
566 unsigned short ctrl;
567
568 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
569 ctrl = serial_port_in(port, SCSCR);
570
571 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
572 ctrl &= ~SCSCR_TDRQE;
573
574 ctrl &= ~SCSCR_TIE;
575
576 serial_port_out(port, SCSCR, ctrl);
577}
578
579static void sci_start_rx(struct uart_port *port)
580{
581 unsigned short ctrl;
582
583 ctrl = serial_port_in(port, SCSCR) | port_rx_irq_mask(port);
584
585 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
586 ctrl &= ~SCSCR_RDRQE;
587
588 serial_port_out(port, SCSCR, ctrl);
589}
590
591static void sci_stop_rx(struct uart_port *port)
592{
593 unsigned short ctrl;
594
595 ctrl = serial_port_in(port, SCSCR);
596
597 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
598 ctrl &= ~SCSCR_RDRQE;
599
600 ctrl &= ~port_rx_irq_mask(port);
601
602 serial_port_out(port, SCSCR, ctrl);
603}
604
a1b5b43f
GU		 605static void sci_clear_SCxSR(struct uart_port *port, unsigned int mask)
606{
607 if (port->type == PORT_SCI) {
608 /* Just store the mask */
609 serial_port_out(port, SCxSR, mask);
b2f20ed9 610 } else if (to_sci_port(port)->params->overrun_mask == SCIFA_ORER) {
a1b5b43f
GU		 611 /* SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721 */
612 /* Only clear the status bits we want to clear */
613 serial_port_out(port, SCxSR,
614 serial_port_in(port, SCxSR) & mask);
615 } else {
616 /* Store the mask, clear parity/framing errors */
617 serial_port_out(port, SCxSR, mask & ~(SCIF_FERC | SCIF_PERC));
618 }
619}
620
0b0cced1
YS		 621#if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \
622 defined(CONFIG_SERIAL_SH_SCI_EARLYCON)
1f6fd5c9
PM		 623
624#ifdef CONFIG_CONSOLE_POLL
07d2a1a1 625static int sci_poll_get_char(struct uart_port *port)
1da177e4 626{
1da177e4
LT		 627 unsigned short status;
628 int c;
629
e108b2ca 630 do {
b12bb29f 631 status = serial_port_in(port, SCxSR);
1da177e4 632 if (status & SCxSR_ERRORS(port)) {
a1b5b43f 633 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
1da177e4
LT		 634 continue;
635 }
3f255eb3
JW		 636 break;
637 } while (1);
638
639 if (!(status & SCxSR_RDxF(port)))
640 return NO_POLL_CHAR;
07d2a1a1 641
b12bb29f 642 c = serial_port_in(port, SCxRDR);
07d2a1a1 643
e7c98dc7 644 /* Dummy read */
b12bb29f 645 serial_port_in(port, SCxSR);
a1b5b43f 646 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1da177e4
LT		 647
648 return c;
649}
1f6fd5c9 650#endif
1da177e4 651
07d2a1a1 652static void sci_poll_put_char(struct uart_port *port, unsigned char c)
1da177e4 653{
1da177e4
LT		 654 unsigned short status;
655
1da177e4 656 do {
b12bb29f 657 status = serial_port_in(port, SCxSR);
1da177e4
LT		 658 } while (!(status & SCxSR_TDxE(port)));
659
b12bb29f 660 serial_port_out(port, SCxTDR, c);
a1b5b43f 661 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
1da177e4 662}
0b0cced1
YS		 663#endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE ||
664 CONFIG_SERIAL_SH_SCI_EARLYCON */
1da177e4 665
61a6976b 666static void sci_init_pins(struct uart_port *port, unsigned int cflag)
1da177e4 667{
61a6976b 668 struct sci_port *s = to_sci_port(port);
1da177e4 669
61a6976b
PM		 670 /*
671 * Use port-specific handler if provided.
672 */
673 if (s->cfg->ops && s->cfg->ops->init_pins) {
674 s->cfg->ops->init_pins(port, cflag);
675 return;
1da177e4 676 }
41504c39 677
e9d7a45a
GU		 678 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
679 u16 ctrl = serial_port_in(port, SCPCR);
680
681 /* Enable RXD and TXD pin functions */
682 ctrl &= ~(SCPCR_RXDC | SCPCR_TXDC);
683 if (to_sci_port(port)->cfg->capabilities & SCIx_HAVE_RTSCTS) {
684 /* RTS# is output, driven 1 */
685 ctrl |= SCPCR_RTSC;
686 serial_port_out(port, SCPDR,
687 serial_port_in(port, SCPDR) | SCPDR_RTSD);
688 /* Enable CTS# pin function */
689 ctrl &= ~SCPCR_CTSC;
690 }
691 serial_port_out(port, SCPCR, ctrl);
692 } else if (sci_getreg(port, SCSPTR)->size) {
d2b9775d
GU		 693 u16 status = serial_port_in(port, SCSPTR);
694
695 /* RTS# is output, driven 1 */
696 status |= SCSPTR_RTSIO | SCSPTR_RTSDT;
697 /* CTS# and SCK are inputs */
698 status &= ~(SCSPTR_CTSIO | SCSPTR_SCKIO);
699 serial_port_out(port, SCSPTR, status);
faf02f8f 700 }
d5701647 701}
e108b2ca 702
72b294cf 703static int sci_txfill(struct uart_port *port)
e108b2ca 704{
b2f20ed9
LP		 705 struct sci_port *s = to_sci_port(port);
706 unsigned int fifo_mask = (s->params->fifosize << 1) - 1;
d3184e68 707 const struct plat_sci_reg *reg;
e108b2ca 708
72b294cf
PM		 709 reg = sci_getreg(port, SCTFDR);
710 if (reg->size)
b2f20ed9 711 return serial_port_in(port, SCTFDR) & fifo_mask;
c63847a3 712
72b294cf
PM		 713 reg = sci_getreg(port, SCFDR);
714 if (reg->size)
b12bb29f 715 return serial_port_in(port, SCFDR) >> 8;
d1d4b10c 716
b12bb29f 717 return !(serial_port_in(port, SCxSR) & SCI_TDRE);
e108b2ca
PM		 718}
719
73a19e4c
GL		 720static int sci_txroom(struct uart_port *port)
721{
72b294cf 722 return port->fifosize - sci_txfill(port);
73a19e4c
GL		 723}
724
725static int sci_rxfill(struct uart_port *port)
e108b2ca 726{
b2f20ed9
LP		 727 struct sci_port *s = to_sci_port(port);
728 unsigned int fifo_mask = (s->params->fifosize << 1) - 1;
d3184e68 729 const struct plat_sci_reg *reg;
72b294cf
PM		 730
731 reg = sci_getreg(port, SCRFDR);
732 if (reg->size)
b2f20ed9 733 return serial_port_in(port, SCRFDR) & fifo_mask;
72b294cf
PM		 734
735 reg = sci_getreg(port, SCFDR);
736 if (reg->size)
b2f20ed9 737 return serial_port_in(port, SCFDR) & fifo_mask;
72b294cf 738
b12bb29f 739 return (serial_port_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
e108b2ca
PM		 740}
741
1da177e4
LT		 742/* ********************************************************************** *
743 * the interrupt related routines *
744 * ********************************************************************** */
745
746static void sci_transmit_chars(struct uart_port *port)
747{
ebd2c8f6 748 struct circ_buf *xmit = &port->state->xmit;
1da177e4 749 unsigned int stopped = uart_tx_stopped(port);
1da177e4
LT		 750 unsigned short status;
751 unsigned short ctrl;
e108b2ca 752 int count;
1da177e4 753
b12bb29f 754 status = serial_port_in(port, SCxSR);
1da177e4 755 if (!(status & SCxSR_TDxE(port))) {
b12bb29f 756 ctrl = serial_port_in(port, SCSCR);
e7c98dc7 757 if (uart_circ_empty(xmit))
8e698614 758 ctrl &= ~SCSCR_TIE;
e7c98dc7 759 else
8e698614 760 ctrl |= SCSCR_TIE;
b12bb29f 761 serial_port_out(port, SCSCR, ctrl);
1da177e4
LT		 762 return;
763 }
764
72b294cf 765 count = sci_txroom(port);
1da177e4
LT		 766
767 do {
768 unsigned char c;
769
770 if (port->x_char) {
771 c = port->x_char;
772 port->x_char = 0;
773 } else if (!uart_circ_empty(xmit) && !stopped) {
774 c = xmit->buf[xmit->tail];
775 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
776 } else {
777 break;
778 }
779
b12bb29f 780 serial_port_out(port, SCxTDR, c);
1da177e4
LT		 781
782 port->icount.tx++;
783 } while (--count > 0);
784
a1b5b43f 785 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
1da177e4
LT		 786
787 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
788 uart_write_wakeup(port);
789 if (uart_circ_empty(xmit)) {
b129a8cc 790 sci_stop_tx(port);
1da177e4 791 } else {
b12bb29f 792 ctrl = serial_port_in(port, SCSCR);
1da177e4 793
1a22f08d 794 if (port->type != PORT_SCI) {
b12bb29f 795 serial_port_in(port, SCxSR); /* Dummy read */
a1b5b43f 796 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
1da177e4 797 }
1da177e4 798
8e698614 799 ctrl |= SCSCR_TIE;
b12bb29f 800 serial_port_out(port, SCSCR, ctrl);
1da177e4
LT		 801 }
802}
803
804/* On SH3, SCIF may read end-of-break as a space->mark char */
e7c98dc7 805#define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); })
1da177e4 806
94c8b6db 807static void sci_receive_chars(struct uart_port *port)
1da177e4 808{
227434f8 809 struct tty_port *tport = &port->state->port;
1da177e4
LT		 810 int i, count, copied = 0;
811 unsigned short status;
33f0f88f 812 unsigned char flag;
1da177e4 813
b12bb29f 814 status = serial_port_in(port, SCxSR);
1da177e4
LT		 815 if (!(status & SCxSR_RDxF(port)))
816 return;
817
818 while (1) {
1da177e4 819 /* Don't copy more bytes than there is room for in the buffer */
227434f8 820 count = tty_buffer_request_room(tport, sci_rxfill(port));
1da177e4
LT		 821
822 /* If for any reason we can't copy more data, we're done! */
823 if (count == 0)
824 break;
825
826 if (port->type == PORT_SCI) {
b12bb29f 827 char c = serial_port_in(port, SCxRDR);
d5cb1319 828 if (uart_handle_sysrq_char(port, c))
1da177e4 829 count = 0;
e7c98dc7 830 else
92a19f9c 831 tty_insert_flip_char(tport, c, TTY_NORMAL);
1da177e4 832 } else {
e7c98dc7 833 for (i = 0; i < count; i++) {
b12bb29f 834 char c = serial_port_in(port, SCxRDR);
d97fbbed 835
b12bb29f 836 status = serial_port_in(port, SCxSR);
7d12e780 837 if (uart_handle_sysrq_char(port, c)) {
1da177e4
LT		 838 count--; i--;
839 continue;
840 }
841
842 /* Store data and status */
73a19e4c 843 if (status & SCxSR_FER(port)) {
33f0f88f 844 flag = TTY_FRAME;
d97fbbed 845 port->icount.frame++;
762c69e3 846 dev_notice(port->dev, "frame error\n");
73a19e4c 847 } else if (status & SCxSR_PER(port)) {
33f0f88f 848 flag = TTY_PARITY;
d97fbbed 849 port->icount.parity++;
762c69e3 850 dev_notice(port->dev, "parity error\n");
33f0f88f
AC		 851 } else
852 flag = TTY_NORMAL;
762c69e3 853
92a19f9c 854 tty_insert_flip_char(tport, c, flag);
1da177e4
LT		 855 }
856 }
857
b12bb29f 858 serial_port_in(port, SCxSR); /* dummy read */
a1b5b43f 859 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1da177e4 860
1da177e4
LT		 861 copied += count;
862 port->icount.rx += count;
863 }
864
865 if (copied) {
866 /* Tell the rest of the system the news. New characters! */
2e124b4a 867 tty_flip_buffer_push(tport);
1da177e4 868 } else {
b12bb29f 869 serial_port_in(port, SCxSR); /* dummy read */
a1b5b43f 870 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1da177e4
LT		 871 }
872}
873
94c8b6db 874static int sci_handle_errors(struct uart_port *port)
1da177e4
LT		 875{
876 int copied = 0;
b12bb29f 877 unsigned short status = serial_port_in(port, SCxSR);
92a19f9c 878 struct tty_port *tport = &port->state->port;
debf9507 879 struct sci_port *s = to_sci_port(port);
1da177e4 880
3ae988d9 881 /* Handle overruns */
b2f20ed9 882 if (status & s->params->overrun_mask) {
3ae988d9 883 port->icount.overrun++;
d97fbbed 884
3ae988d9
LP		 885 /* overrun error */
886 if (tty_insert_flip_char(tport, 0, TTY_OVERRUN))
887 copied++;
762c69e3 888
9b971cd2 889 dev_notice(port->dev, "overrun error\n");
1da177e4
LT		 890 }
891
e108b2ca 892 if (status & SCxSR_FER(port)) {
d5cb1319
LP		 893 /* frame error */
894 port->icount.frame++;
d97fbbed 895
d5cb1319
LP		 896 if (tty_insert_flip_char(tport, 0, TTY_FRAME))
897 copied++;
762c69e3 898
d5cb1319 899 dev_notice(port->dev, "frame error\n");
1da177e4
LT		 900 }
901
e108b2ca 902 if (status & SCxSR_PER(port)) {
1da177e4 903 /* parity error */
d97fbbed
PM		 904 port->icount.parity++;
905
92a19f9c 906 if (tty_insert_flip_char(tport, 0, TTY_PARITY))
e108b2ca 907 copied++;
762c69e3 908
9b971cd2 909 dev_notice(port->dev, "parity error\n");
1da177e4
LT		 910 }
911
33f0f88f 912 if (copied)
2e124b4a 913 tty_flip_buffer_push(tport);
1da177e4
LT		 914
915 return copied;
916}
917
94c8b6db 918static int sci_handle_fifo_overrun(struct uart_port *port)
d830fa45 919{
92a19f9c 920 struct tty_port *tport = &port->state->port;
debf9507 921 struct sci_port *s = to_sci_port(port);
d3184e68 922 const struct plat_sci_reg *reg;
2e0842a1 923 int copied = 0;
75c249fd 924 u16 status;
d830fa45 925
b2f20ed9 926 reg = sci_getreg(port, s->params->overrun_reg);
4b8c59a3 927 if (!reg->size)
d830fa45
PM		 928 return 0;
929
b2f20ed9
LP		 930 status = serial_port_in(port, s->params->overrun_reg);
931 if (status & s->params->overrun_mask) {
932 status &= ~s->params->overrun_mask;
933 serial_port_out(port, s->params->overrun_reg, status);
d830fa45 934
d97fbbed
PM		 935 port->icount.overrun++;
936
92a19f9c 937 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
2e124b4a 938 tty_flip_buffer_push(tport);
d830fa45 939
51b31f1c 940 dev_dbg(port->dev, "overrun error\n");
d830fa45
PM		 941 copied++;
942 }
943
944 return copied;
945}
946
94c8b6db 947static int sci_handle_breaks(struct uart_port *port)
1da177e4
LT		 948{
949 int copied = 0;
b12bb29f 950 unsigned short status = serial_port_in(port, SCxSR);
92a19f9c 951 struct tty_port *tport = &port->state->port;
1da177e4 952
0b3d4ef6
PM		 953 if (uart_handle_break(port))
954 return 0;
955
d5cb1319 956 if (status & SCxSR_BRK(port)) {
d97fbbed
PM		 957 port->icount.brk++;
958
1da177e4 959 /* Notify of BREAK */
92a19f9c 960 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
33f0f88f 961 copied++;
762c69e3
PM		 962
963 dev_dbg(port->dev, "BREAK detected\n");
1da177e4
LT		 964 }
965
33f0f88f 966 if (copied)
2e124b4a 967 tty_flip_buffer_push(tport);
e108b2ca 968
d830fa45
PM		 969 copied += sci_handle_fifo_overrun(port);
970
1da177e4
LT		 971 return copied;
972}
973
73a19e4c 974#ifdef CONFIG_SERIAL_SH_SCI_DMA
e1910fcd
GU		 975static void sci_dma_tx_complete(void *arg)
976{
977 struct sci_port *s = arg;
978 struct uart_port *port = &s->port;
979 struct circ_buf *xmit = &port->state->xmit;
980 unsigned long flags;
73a19e4c 981
e1910fcd 982 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
73a19e4c 983
e1910fcd 984 spin_lock_irqsave(&port->lock, flags);
73a19e4c 985
e1910fcd
GU		 986 xmit->tail += s->tx_dma_len;
987 xmit->tail &= UART_XMIT_SIZE - 1;
73a19e4c 988
e1910fcd 989 port->icount.tx += s->tx_dma_len;
1da177e4 990
e1910fcd
GU		 991 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
992 uart_write_wakeup(port);
1da177e4 993
e1910fcd
GU		 994 if (!uart_circ_empty(xmit)) {
995 s->cookie_tx = 0;
996 schedule_work(&s->work_tx);
997 } else {
998 s->cookie_tx = -EINVAL;
999 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1000 u16 ctrl = serial_port_in(port, SCSCR);
1001 serial_port_out(port, SCSCR, ctrl & ~SCSCR_TIE);
1002 }
1003 }
1da177e4 1004
fd78a76a 1005 spin_unlock_irqrestore(&port->lock, flags);
1da177e4
LT		 1006}
1007
e1910fcd
GU		 1008/* Locking: called with port lock held */
1009static int sci_dma_rx_push(struct sci_port *s, void *buf, size_t count)
1da177e4 1010{
e1910fcd
GU		 1011 struct uart_port *port = &s->port;
1012 struct tty_port *tport = &port->state->port;
1013 int copied;
1da177e4 1014
e1910fcd 1015 copied = tty_insert_flip_string(tport, buf, count);
6fc5a520 1016 if (copied < count)
e1910fcd 1017 port->icount.buf_overrun++;
1da177e4 1018
e1910fcd 1019 port->icount.rx += copied;
1da177e4 1020
e1910fcd 1021 return copied;
1da177e4
LT		 1022}
1023
e1910fcd 1024static int sci_dma_rx_find_active(struct sci_port *s)
1da177e4 1025{
e1910fcd 1026 unsigned int i;
1da177e4 1027
e1910fcd
GU		 1028 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++)
1029 if (s->active_rx == s->cookie_rx[i])
1030 return i;
1da177e4 1031
e1910fcd 1032 return -1;
1da177e4
LT		 1033}
1034
e1910fcd 1035static void sci_rx_dma_release(struct sci_port *s, bool enable_pio)
f43dc23d 1036{
e1910fcd
GU		 1037 struct dma_chan *chan = s->chan_rx;
1038 struct uart_port *port = &s->port;
1039 unsigned long flags;
1040
1041 spin_lock_irqsave(&port->lock, flags);
1042 s->chan_rx = NULL;
1043 s->cookie_rx[0] = s->cookie_rx[1] = -EINVAL;
1044 spin_unlock_irqrestore(&port->lock, flags);
1045 dmaengine_terminate_all(chan);
1046 dma_free_coherent(chan->device->dev, s->buf_len_rx * 2, s->rx_buf[0],
1047 sg_dma_address(&s->sg_rx[0]));
1048 dma_release_channel(chan);
1049 if (enable_pio)
1050 sci_start_rx(port);
f43dc23d
PM		 1051}
1052
e1910fcd 1053static void sci_dma_rx_complete(void *arg)
1da177e4 1054{
e1910fcd 1055 struct sci_port *s = arg;
1d3db608 1056 struct dma_chan *chan = s->chan_rx;
e1910fcd 1057 struct uart_port *port = &s->port;
67f462b0 1058 struct dma_async_tx_descriptor *desc;
e1910fcd
GU		 1059 unsigned long flags;
1060 int active, count = 0;
1da177e4 1061
e1910fcd
GU		 1062 dev_dbg(port->dev, "%s(%d) active cookie %d\n", __func__, port->line,
1063 s->active_rx);
cb772fe7 1064
e1910fcd 1065 spin_lock_irqsave(&port->lock, flags);
1da177e4 1066
e1910fcd
GU		 1067 active = sci_dma_rx_find_active(s);
1068 if (active >= 0)
1069 count = sci_dma_rx_push(s, s->rx_buf[active], s->buf_len_rx);
f43dc23d 1070
e1910fcd 1071 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
f43dc23d 1072
e1910fcd
GU		 1073 if (count)
1074 tty_flip_buffer_push(&port->state->port);
8b6ff84c 1075
67f462b0
GU		 1076 desc = dmaengine_prep_slave_sg(s->chan_rx, &s->sg_rx[active], 1,
1077 DMA_DEV_TO_MEM,
1078 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1079 if (!desc)
1080 goto fail;
1081
1082 desc->callback = sci_dma_rx_complete;
1083 desc->callback_param = s;
1084 s->cookie_rx[active] = dmaengine_submit(desc);
1085 if (dma_submit_error(s->cookie_rx[active]))
1086 goto fail;
1087
1088 s->active_rx = s->cookie_rx[!active];
1089
1d3db608
MHF		 1090 dma_async_issue_pending(chan);
1091
6fc5a520 1092 spin_unlock_irqrestore(&port->lock, flags);
67f462b0
GU		 1093 dev_dbg(port->dev, "%s: cookie %d #%d, new active cookie %d\n",
1094 __func__, s->cookie_rx[active], active, s->active_rx);
67f462b0
GU		 1095 return;
1096
1097fail:
1098 spin_unlock_irqrestore(&port->lock, flags);
1099 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
1100 sci_rx_dma_release(s, true);
1da177e4
LT		 1101}
1102
e1910fcd 1103static void sci_tx_dma_release(struct sci_port *s, bool enable_pio)
1da177e4 1104{
e1910fcd
GU		 1105 struct dma_chan *chan = s->chan_tx;
1106 struct uart_port *port = &s->port;
e552de24 1107 unsigned long flags;
1da177e4 1108
e1910fcd
GU		 1109 spin_lock_irqsave(&port->lock, flags);
1110 s->chan_tx = NULL;
1111 s->cookie_tx = -EINVAL;
1112 spin_unlock_irqrestore(&port->lock, flags);
1113 dmaengine_terminate_all(chan);
1114 dma_unmap_single(chan->device->dev, s->tx_dma_addr, UART_XMIT_SIZE,
1115 DMA_TO_DEVICE);
1116 dma_release_channel(chan);
1117 if (enable_pio)
1118 sci_start_tx(port);
1119}
d535a230 1120
e1910fcd
GU		 1121static void sci_submit_rx(struct sci_port *s)
1122{
1123 struct dma_chan *chan = s->chan_rx;
1124 int i;
073e84c9 1125
e1910fcd
GU		 1126 for (i = 0; i < 2; i++) {
1127 struct scatterlist *sg = &s->sg_rx[i];
1128 struct dma_async_tx_descriptor *desc;
1da177e4 1129
e1910fcd
GU		 1130 desc = dmaengine_prep_slave_sg(chan,
1131 sg, 1, DMA_DEV_TO_MEM,
1132 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1133 if (!desc)
1134 goto fail;
501b825d 1135
e1910fcd
GU		 1136 desc->callback = sci_dma_rx_complete;
1137 desc->callback_param = s;
1138 s->cookie_rx[i] = dmaengine_submit(desc);
1139 if (dma_submit_error(s->cookie_rx[i]))
1140 goto fail;
9174fc8f 1141
e1910fcd 1142 }
9174fc8f 1143
e1910fcd 1144 s->active_rx = s->cookie_rx[0];
9174fc8f 1145
e1910fcd
GU		 1146 dma_async_issue_pending(chan);
1147 return;
9174fc8f 1148
e1910fcd
GU		 1149fail:
1150 if (i)
1151 dmaengine_terminate_all(chan);
1152 for (i = 0; i < 2; i++)
1153 s->cookie_rx[i] = -EINVAL;
1154 s->active_rx = -EINVAL;
e1910fcd
GU		 1155 sci_rx_dma_release(s, true);
1156}
9174fc8f 1157
e1910fcd 1158static void work_fn_tx(struct work_struct *work)
1da177e4 1159{
e1910fcd
GU		 1160 struct sci_port *s = container_of(work, struct sci_port, work_tx);
1161 struct dma_async_tx_descriptor *desc;
1162 struct dma_chan *chan = s->chan_tx;
1163 struct uart_port *port = &s->port;
1164 struct circ_buf *xmit = &port->state->xmit;
1165 dma_addr_t buf;
1da177e4 1166
9174fc8f 1167 /*
e1910fcd
GU		 1168 * DMA is idle now.
1169 * Port xmit buffer is already mapped, and it is one page... Just adjust
1170 * offsets and lengths. Since it is a circular buffer, we have to
1171 * transmit till the end, and then the rest. Take the port lock to get a
1172 * consistent xmit buffer state.
9174fc8f 1173 */
e1910fcd
GU		 1174 spin_lock_irq(&port->lock);
1175 buf = s->tx_dma_addr + (xmit->tail & (UART_XMIT_SIZE - 1));
1176 s->tx_dma_len = min_t(unsigned int,
1177 CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE),
1178 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE));
1179 spin_unlock_irq(&port->lock);
0e8963de 1180
e1910fcd
GU		 1181 desc = dmaengine_prep_slave_single(chan, buf, s->tx_dma_len,
1182 DMA_MEM_TO_DEV,
1183 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1184 if (!desc) {
1185 dev_warn(port->dev, "Failed preparing Tx DMA descriptor\n");
1186 /* switch to PIO */
1187 sci_tx_dma_release(s, true);
1188 return;
1189 }
0e8963de 1190
e1910fcd
GU		 1191 dma_sync_single_for_device(chan->device->dev, buf, s->tx_dma_len,
1192 DMA_TO_DEVICE);
1da177e4 1193
e1910fcd
GU		 1194 spin_lock_irq(&port->lock);
1195 desc->callback = sci_dma_tx_complete;
1196 desc->callback_param = s;
1197 spin_unlock_irq(&port->lock);
1198 s->cookie_tx = dmaengine_submit(desc);
1199 if (dma_submit_error(s->cookie_tx)) {
1200 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
1201 /* switch to PIO */
1202 sci_tx_dma_release(s, true);
1203 return;
1da177e4 1204 }
1da177e4 1205
e1910fcd
GU		 1206 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n",
1207 __func__, xmit->buf, xmit->tail, xmit->head, s->cookie_tx);
73a19e4c 1208
e1910fcd 1209 dma_async_issue_pending(chan);
1da177e4
LT		 1210}
1211
e1910fcd 1212static void rx_timer_fn(unsigned long arg)
1da177e4 1213{
e1910fcd 1214 struct sci_port *s = (struct sci_port *)arg;
e7327c09 1215 struct dma_chan *chan = s->chan_rx;
e1910fcd 1216 struct uart_port *port = &s->port;
67f462b0
GU		 1217 struct dma_tx_state state;
1218 enum dma_status status;
1219 unsigned long flags;
1220 unsigned int read;
1221 int active, count;
1222 u16 scr;
1223
67f462b0 1224 dev_dbg(port->dev, "DMA Rx timed out\n");
67f462b0 1225
6fc5a520
TA		 1226 spin_lock_irqsave(&port->lock, flags);
1227
67f462b0
GU		 1228 active = sci_dma_rx_find_active(s);
1229 if (active < 0) {
1230 spin_unlock_irqrestore(&port->lock, flags);
1231 return;
1232 }
1233
1234 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
3b963042 1235 if (status == DMA_COMPLETE) {
6fc5a520 1236 spin_unlock_irqrestore(&port->lock, flags);
67f462b0
GU		 1237 dev_dbg(port->dev, "Cookie %d #%d has already completed\n",
1238 s->active_rx, active);
3b963042
MHF		 1239
1240 /* Let packet complete handler take care of the packet */
1241 return;
1242 }
67f462b0 1243
e7327c09
MHF		 1244 dmaengine_pause(chan);
1245
1246 /*
1247 * sometimes DMA transfer doesn't stop even if it is stopped and
1248 * data keeps on coming until transaction is complete so check
1249 * for DMA_COMPLETE again
1250 * Let packet complete handler take care of the packet
1251 */
1252 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
1253 if (status == DMA_COMPLETE) {
1254 spin_unlock_irqrestore(&port->lock, flags);
1255 dev_dbg(port->dev, "Transaction complete after DMA engine was stopped");
1256 return;
1257 }
1258
67f462b0
GU		 1259 /* Handle incomplete DMA receive */
1260 dmaengine_terminate_all(s->chan_rx);
1261 read = sg_dma_len(&s->sg_rx[active]) - state.residue;
67f462b0
GU		 1262
1263 if (read) {
1264 count = sci_dma_rx_push(s, s->rx_buf[active], read);
1265 if (count)
1266 tty_flip_buffer_push(&port->state->port);
1267 }
1268
756981be
GU		 1269 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1270 sci_submit_rx(s);
371cfed3
MHF		 1271
1272 /* Direct new serial port interrupts back to CPU */
1273 scr = serial_port_in(port, SCSCR);
1274 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1275 scr &= ~SCSCR_RDRQE;
1276 enable_irq(s->irqs[SCIx_RXI_IRQ]);
1277 }
1278 serial_port_out(port, SCSCR, scr | SCSCR_RIE);
1279
1280 spin_unlock_irqrestore(&port->lock, flags);
1da177e4
LT		 1281}
1282
ff441129 1283static struct dma_chan *sci_request_dma_chan(struct uart_port *port,
219fb0c1 1284 enum dma_transfer_direction dir)
ff441129 1285{
ff441129
GU		 1286 struct dma_chan *chan;
1287 struct dma_slave_config cfg;
1288 int ret;
1289
219fb0c1
LP		 1290 chan = dma_request_slave_channel(port->dev,
1291 dir == DMA_MEM_TO_DEV ? "tx" : "rx");
ff441129
GU		 1292 if (!chan) {
1293 dev_warn(port->dev,
1294 "dma_request_slave_channel_compat failed\n");
1295 return NULL;
1296 }
1297
1298 memset(&cfg, 0, sizeof(cfg));
1299 cfg.direction = dir;
1300 if (dir == DMA_MEM_TO_DEV) {
1301 cfg.dst_addr = port->mapbase +
1302 (sci_getreg(port, SCxTDR)->offset << port->regshift);
1303 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1304 } else {
1305 cfg.src_addr = port->mapbase +
1306 (sci_getreg(port, SCxRDR)->offset << port->regshift);
1307 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1308 }
1309
1310 ret = dmaengine_slave_config(chan, &cfg);
1311 if (ret) {
1312 dev_warn(port->dev, "dmaengine_slave_config failed %d\n", ret);
1313 dma_release_channel(chan);
1314 return NULL;
1315 }
1316
1317 return chan;
1318}
1319
e1910fcd 1320static void sci_request_dma(struct uart_port *port)
73a19e4c 1321{
e1910fcd 1322 struct sci_port *s = to_sci_port(port);
e1910fcd 1323 struct dma_chan *chan;
73a19e4c 1324
e1910fcd 1325 dev_dbg(port->dev, "%s: port %d\n", __func__, port->line);
73a19e4c 1326
219fb0c1 1327 if (!port->dev->of_node)
e1910fcd 1328 return;
73a19e4c 1329
e1910fcd 1330 s->cookie_tx = -EINVAL;
219fb0c1 1331 chan = sci_request_dma_chan(port, DMA_MEM_TO_DEV);
e1910fcd
GU		 1332 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
1333 if (chan) {
1334 s->chan_tx = chan;
1335 /* UART circular tx buffer is an aligned page. */
1336 s->tx_dma_addr = dma_map_single(chan->device->dev,
1337 port->state->xmit.buf,
1338 UART_XMIT_SIZE,
1339 DMA_TO_DEVICE);
1340 if (dma_mapping_error(chan->device->dev, s->tx_dma_addr)) {
1341 dev_warn(port->dev, "Failed mapping Tx DMA descriptor\n");
1342 dma_release_channel(chan);
1343 s->chan_tx = NULL;
1344 } else {
1345 dev_dbg(port->dev, "%s: mapped %lu@%p to %pad\n",
1346 __func__, UART_XMIT_SIZE,
1347 port->state->xmit.buf, &s->tx_dma_addr);
49d4bcad 1348 }
e1910fcd
GU		 1349
1350 INIT_WORK(&s->work_tx, work_fn_tx);
3089f381
GL		 1351 }
1352
219fb0c1 1353 chan = sci_request_dma_chan(port, DMA_DEV_TO_MEM);
e1910fcd
GU		 1354 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan);
1355 if (chan) {
1356 unsigned int i;
1357 dma_addr_t dma;
1358 void *buf;
73a19e4c 1359
e1910fcd 1360 s->chan_rx = chan;
73a19e4c 1361
e1910fcd
GU		 1362 s->buf_len_rx = 2 * max_t(size_t, 16, port->fifosize);
1363 buf = dma_alloc_coherent(chan->device->dev, s->buf_len_rx * 2,
1364 &dma, GFP_KERNEL);
1365 if (!buf) {
1366 dev_warn(port->dev,
1367 "Failed to allocate Rx dma buffer, using PIO\n");
1368 dma_release_channel(chan);
1369 s->chan_rx = NULL;
e1910fcd
GU		 1370 return;
1371 }
73a19e4c 1372
e1910fcd
GU		 1373 for (i = 0; i < 2; i++) {
1374 struct scatterlist *sg = &s->sg_rx[i];
0533502d 1375
e1910fcd
GU		 1376 sg_init_table(sg, 1);
1377 s->rx_buf[i] = buf;
1378 sg_dma_address(sg) = dma;
d09959e7 1379 sg_dma_len(sg) = s->buf_len_rx;
0533502d 1380
e1910fcd
GU		 1381 buf += s->buf_len_rx;
1382 dma += s->buf_len_rx;
1383 }
1384
e1910fcd
GU		 1385 setup_timer(&s->rx_timer, rx_timer_fn, (unsigned long)s);
1386
756981be
GU		 1387 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1388 sci_submit_rx(s);
e1910fcd 1389 }
0533502d
GU		 1390}
1391
e1910fcd 1392static void sci_free_dma(struct uart_port *port)
73a19e4c 1393{
e1910fcd 1394 struct sci_port *s = to_sci_port(port);
73a19e4c 1395
e1910fcd
GU		 1396 if (s->chan_tx)
1397 sci_tx_dma_release(s, false);
1398 if (s->chan_rx)
1399 sci_rx_dma_release(s, false);
1400}
1401#else
1402static inline void sci_request_dma(struct uart_port *port)
1403{
1404}
73a19e4c 1405
e1910fcd
GU		 1406static inline void sci_free_dma(struct uart_port *port)
1407{
1408}
1409#endif
73a19e4c 1410
e1910fcd
GU		 1411static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
1412{
1413#ifdef CONFIG_SERIAL_SH_SCI_DMA
1414 struct uart_port *port = ptr;
1415 struct sci_port *s = to_sci_port(port);
73a19e4c 1416
e1910fcd
GU		 1417 if (s->chan_rx) {
1418 u16 scr = serial_port_in(port, SCSCR);
1419 u16 ssr = serial_port_in(port, SCxSR);
73a19e4c 1420
e1910fcd
GU		 1421 /* Disable future Rx interrupts */
1422 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1423 disable_irq_nosync(irq);
1424 scr |= SCSCR_RDRQE;
1425 } else {
1426 scr &= ~SCSCR_RIE;
756981be 1427 sci_submit_rx(s);
e1910fcd
GU		 1428 }
1429 serial_port_out(port, SCSCR, scr);
1430 /* Clear current interrupt */
1431 serial_port_out(port, SCxSR,
1432 ssr & ~(SCIF_DR | SCxSR_RDxF(port)));
1433 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u jiffies\n",
1434 jiffies, s->rx_timeout);
1435 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
73a19e4c 1436
e1910fcd
GU		 1437 return IRQ_HANDLED;
1438 }
1439#endif
73a19e4c 1440
e1910fcd
GU		 1441 /* I think sci_receive_chars has to be called irrespective
1442 * of whether the I_IXOFF is set, otherwise, how is the interrupt
1443 * to be disabled?
1444 */
1445 sci_receive_chars(ptr);
1446
1447 return IRQ_HANDLED;
73a19e4c
GL		 1448}
1449
e1910fcd 1450static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
73a19e4c 1451{
e1910fcd 1452 struct uart_port *port = ptr;
04928b79 1453 unsigned long flags;
73a19e4c 1454
04928b79 1455 spin_lock_irqsave(&port->lock, flags);
e1910fcd 1456 sci_transmit_chars(port);
04928b79 1457 spin_unlock_irqrestore(&port->lock, flags);
e1910fcd
GU		 1458
1459 return IRQ_HANDLED;
73a19e4c
GL		 1460}
1461
e1910fcd 1462static irqreturn_t sci_er_interrupt(int irq, void *ptr)
73a19e4c 1463{
e1910fcd
GU		 1464 struct uart_port *port = ptr;
1465 struct sci_port *s = to_sci_port(port);
73a19e4c 1466
e1910fcd
GU		 1467 /* Handle errors */
1468 if (port->type == PORT_SCI) {
1469 if (sci_handle_errors(port)) {
1470 /* discard character in rx buffer */
1471 serial_port_in(port, SCxSR);
1472 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1473 }
1474 } else {
1475 sci_handle_fifo_overrun(port);
1476 if (!s->chan_rx)
1477 sci_receive_chars(ptr);
1478 }
1479
1480 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
1481
1482 /* Kick the transmission */
1483 if (!s->chan_tx)
1484 sci_tx_interrupt(irq, ptr);
1485
1486 return IRQ_HANDLED;
73a19e4c
GL		 1487}
1488
e1910fcd 1489static irqreturn_t sci_br_interrupt(int irq, void *ptr)
73a19e4c 1490{
e1910fcd 1491 struct uart_port *port = ptr;
73a19e4c 1492
e1910fcd
GU		 1493 /* Handle BREAKs */
1494 sci_handle_breaks(port);
1495 sci_clear_SCxSR(port, SCxSR_BREAK_CLEAR(port));
73a19e4c 1496
e1910fcd
GU		 1497 return IRQ_HANDLED;
1498}
73a19e4c 1499
e1910fcd
GU		 1500static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
1501{
1502 unsigned short ssr_status, scr_status, err_enabled, orer_status = 0;
1503 struct uart_port *port = ptr;
1504 struct sci_port *s = to_sci_port(port);
1505 irqreturn_t ret = IRQ_NONE;
73a19e4c 1506
e1910fcd
GU		 1507 ssr_status = serial_port_in(port, SCxSR);
1508 scr_status = serial_port_in(port, SCSCR);
b2f20ed9 1509 if (s->params->overrun_reg == SCxSR)
e1910fcd 1510 orer_status = ssr_status;
b2f20ed9
LP		 1511 else if (sci_getreg(port, s->params->overrun_reg)->size)
1512 orer_status = serial_port_in(port, s->params->overrun_reg);
73a19e4c 1513
e1910fcd 1514 err_enabled = scr_status & port_rx_irq_mask(port);
73a19e4c 1515
e1910fcd
GU		 1516 /* Tx Interrupt */
1517 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) &&
1518 !s->chan_tx)
1519 ret = sci_tx_interrupt(irq, ptr);
658daa95 1520
e1910fcd
GU		 1521 /*
1522 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF /
1523 * DR flags
1524 */
1525 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&
1526 (scr_status & SCSCR_RIE))
1527 ret = sci_rx_interrupt(irq, ptr);
73a19e4c 1528
e1910fcd
GU		 1529 /* Error Interrupt */
1530 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
1531 ret = sci_er_interrupt(irq, ptr);
73a19e4c 1532
e1910fcd
GU		 1533 /* Break Interrupt */
1534 if ((ssr_status & SCxSR_BRK(port)) && err_enabled)
1535 ret = sci_br_interrupt(irq, ptr);
1536
1537 /* Overrun Interrupt */
b2f20ed9 1538 if (orer_status & s->params->overrun_mask) {
e1910fcd
GU		 1539 sci_handle_fifo_overrun(port);
1540 ret = IRQ_HANDLED;
73a19e4c 1541 }
73a19e4c 1542
e1910fcd
GU		 1543 return ret;
1544}
73a19e4c 1545
e1910fcd
GU		 1546static const struct sci_irq_desc {
1547 const char *desc;
1548 irq_handler_t handler;
1549} sci_irq_desc[] = {
1550 /*
1551 * Split out handlers, the default case.
1552 */
1553 [SCIx_ERI_IRQ] = {
1554 .desc = "rx err",
1555 .handler = sci_er_interrupt,
1556 },
3089f381 1557
e1910fcd
GU		 1558 [SCIx_RXI_IRQ] = {
1559 .desc = "rx full",
1560 .handler = sci_rx_interrupt,
1561 },
47aceb92 1562
e1910fcd
GU		 1563 [SCIx_TXI_IRQ] = {
1564 .desc = "tx empty",
1565 .handler = sci_tx_interrupt,
1566 },
73a19e4c 1567
e1910fcd
GU		 1568 [SCIx_BRI_IRQ] = {
1569 .desc = "break",
1570 .handler = sci_br_interrupt,
1571 },
73a19e4c
GL		 1572
1573 /*
e1910fcd 1574 * Special muxed handler.
73a19e4c 1575 */
e1910fcd
GU		 1576 [SCIx_MUX_IRQ] = {
1577 .desc = "mux",
1578 .handler = sci_mpxed_interrupt,
1579 },
1580};
73a19e4c 1581
e1910fcd
GU		 1582static int sci_request_irq(struct sci_port *port)
1583{
1584 struct uart_port *up = &port->port;
1585 int i, j, ret = 0;
73a19e4c 1586
e1910fcd
GU		 1587 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) {
1588 const struct sci_irq_desc *desc;
1589 int irq;
73a19e4c 1590
e1910fcd
GU		 1591 if (SCIx_IRQ_IS_MUXED(port)) {
1592 i = SCIx_MUX_IRQ;
1593 irq = up->irq;
1594 } else {
1595 irq = port->irqs[i];
1596
1597 /*
1598 * Certain port types won't support all of the
1599 * available interrupt sources.
1600 */
1601 if (unlikely(irq < 0))
1602 continue;
1603 }
1604
1605 desc = sci_irq_desc + i;
1606 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s",
1607 dev_name(up->dev), desc->desc);
623ac1d4
PB		 1608 if (!port->irqstr[j]) {
1609 ret = -ENOMEM;
e1910fcd 1610 goto out_nomem;
623ac1d4 1611 }
e1910fcd
GU		 1612
1613 ret = request_irq(irq, desc->handler, up->irqflags,
1614 port->irqstr[j], port);
1615 if (unlikely(ret)) {
1616 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc);
1617 goto out_noirq;
1618 }
73a19e4c
GL		 1619 }
1620
e1910fcd 1621 return 0;
1da177e4 1622
e1910fcd
GU		 1623out_noirq:
1624 while (--i >= 0)
1625 free_irq(port->irqs[i], port);
f43dc23d 1626
e1910fcd
GU		 1627out_nomem:
1628 while (--j >= 0)
1629 kfree(port->irqstr[j]);
f43dc23d 1630
e1910fcd 1631 return ret;
1da177e4
LT		 1632}
1633
e1910fcd 1634static void sci_free_irq(struct sci_port *port)
1da177e4 1635{
e1910fcd 1636 int i;
1da177e4 1637
e1910fcd
GU		 1638 /*
1639 * Intentionally in reverse order so we iterate over the muxed
1640 * IRQ first.
1641 */
1642 for (i = 0; i < SCIx_NR_IRQS; i++) {
1643 int irq = port->irqs[i];
f43dc23d 1644
e1910fcd
GU		 1645 /*
1646 * Certain port types won't support all of the available
1647 * interrupt sources.
1648 */
1649 if (unlikely(irq < 0))
1650 continue;
f43dc23d 1651
e1910fcd
GU		 1652 free_irq(port->irqs[i], port);
1653 kfree(port->irqstr[i]);
f43dc23d 1654
e1910fcd
GU		 1655 if (SCIx_IRQ_IS_MUXED(port)) {
1656 /* If there's only one IRQ, we're done. */
1657 return;
1658 }
1659 }
1da177e4
LT		 1660}
1661
e1910fcd 1662static unsigned int sci_tx_empty(struct uart_port *port)
1da177e4 1663{
e1910fcd
GU		 1664 unsigned short status = serial_port_in(port, SCxSR);
1665 unsigned short in_tx_fifo = sci_txfill(port);
f43dc23d 1666
e1910fcd 1667 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
1da177e4
LT		 1668}
1669
33f50ffc
GU		 1670static void sci_set_rts(struct uart_port *port, bool state)
1671{
1672 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1673 u16 data = serial_port_in(port, SCPDR);
1674
1675 /* Active low */
1676 if (state)
1677 data &= ~SCPDR_RTSD;
1678 else
1679 data |= SCPDR_RTSD;
1680 serial_port_out(port, SCPDR, data);
1681
1682 /* RTS# is output */
1683 serial_port_out(port, SCPCR,
1684 serial_port_in(port, SCPCR) | SCPCR_RTSC);
1685 } else if (sci_getreg(port, SCSPTR)->size) {
1686 u16 ctrl = serial_port_in(port, SCSPTR);
1687
1688 /* Active low */
1689 if (state)
1690 ctrl &= ~SCSPTR_RTSDT;
1691 else
1692 ctrl |= SCSPTR_RTSDT;
1693 serial_port_out(port, SCSPTR, ctrl);
1694 }
1695}
1696
1697static bool sci_get_cts(struct uart_port *port)
1698{
1699 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1700 /* Active low */
1701 return !(serial_port_in(port, SCPDR) & SCPDR_CTSD);
1702 } else if (sci_getreg(port, SCSPTR)->size) {
1703 /* Active low */
1704 return !(serial_port_in(port, SCSPTR) & SCSPTR_CTSDT);
1705 }
1706
1707 return true;
1708}
1709
e1910fcd
GU		 1710/*
1711 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally
1712 * CTS/RTS is supported in hardware by at least one port and controlled
1713 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently
1714 * handled via the ->init_pins() op, which is a bit of a one-way street,
1715 * lacking any ability to defer pin control -- this will later be
1716 * converted over to the GPIO framework).
1717 *
1718 * Other modes (such as loopback) are supported generically on certain
1719 * port types, but not others. For these it's sufficient to test for the
1720 * existence of the support register and simply ignore the port type.
1721 */
1722static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
1da177e4 1723{
f907c9ea
GU		 1724 struct sci_port *s = to_sci_port(port);
1725
e1910fcd
GU		 1726 if (mctrl & TIOCM_LOOP) {
1727 const struct plat_sci_reg *reg;
f43dc23d 1728
e1910fcd
GU		 1729 /*
1730 * Standard loopback mode for SCFCR ports.
1731 */
1732 reg = sci_getreg(port, SCFCR);
1733 if (reg->size)
1734 serial_port_out(port, SCFCR,
1735 serial_port_in(port, SCFCR) |
1736 SCFCR_LOOP);
1737 }
f907c9ea
GU		 1738
1739 mctrl_gpio_set(s->gpios, mctrl);
33f50ffc
GU		 1740
1741 if (!(s->cfg->capabilities & SCIx_HAVE_RTSCTS))
1742 return;
1743
1744 if (!(mctrl & TIOCM_RTS)) {
1745 /* Disable Auto RTS */
1746 serial_port_out(port, SCFCR,
1747 serial_port_in(port, SCFCR) & ~SCFCR_MCE);
1748
1749 /* Clear RTS */
1750 sci_set_rts(port, 0);
1751 } else if (s->autorts) {
1752 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1753 /* Enable RTS# pin function */
1754 serial_port_out(port, SCPCR,
1755 serial_port_in(port, SCPCR) & ~SCPCR_RTSC);
1756 }
1757
1758 /* Enable Auto RTS */
1759 serial_port_out(port, SCFCR,
1760 serial_port_in(port, SCFCR) | SCFCR_MCE);
1761 } else {
1762 /* Set RTS */
1763 sci_set_rts(port, 1);
1764 }
e1910fcd 1765}
f43dc23d 1766
e1910fcd
GU		 1767static unsigned int sci_get_mctrl(struct uart_port *port)
1768{
f907c9ea
GU		 1769 struct sci_port *s = to_sci_port(port);
1770 struct mctrl_gpios *gpios = s->gpios;
1771 unsigned int mctrl = 0;
1772
1773 mctrl_gpio_get(gpios, &mctrl);
1774
e1910fcd
GU		 1775 /*
1776 * CTS/RTS is handled in hardware when supported, while nothing
33f50ffc 1777 * else is wired up.
e1910fcd 1778 */
33f50ffc
GU		 1779 if (s->autorts) {
1780 if (sci_get_cts(port))
1781 mctrl |= TIOCM_CTS;
1782 } else if (IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(gpios, UART_GPIO_CTS))) {
f907c9ea 1783 mctrl |= TIOCM_CTS;
33f50ffc 1784 }
f907c9ea
GU		 1785 if (IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(gpios, UART_GPIO_DSR)))
1786 mctrl |= TIOCM_DSR;
1787 if (IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(gpios, UART_GPIO_DCD)))
1788 mctrl |= TIOCM_CAR;
1789
1790 return mctrl;
1791}
1792
1793static void sci_enable_ms(struct uart_port *port)
1794{
1795 mctrl_gpio_enable_ms(to_sci_port(port)->gpios);
1da177e4
LT		 1796}
1797
1da177e4
LT		 1798static void sci_break_ctl(struct uart_port *port, int break_state)
1799{
bbb4ce50
SY		 1800 unsigned short scscr, scsptr;
1801
a4e02f6d 1802 /* check wheter the port has SCSPTR */
abbf121f 1803 if (!sci_getreg(port, SCSPTR)->size) {
bbb4ce50
SY		 1804 /*
1805 * Not supported by hardware. Most parts couple break and rx
1806 * interrupts together, with break detection always enabled.
1807 */
a4e02f6d 1808 return;
bbb4ce50 1809 }
a4e02f6d
SY		 1810
1811 scsptr = serial_port_in(port, SCSPTR);
1812 scscr = serial_port_in(port, SCSCR);
1813
1814 if (break_state == -1) {
1815 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT;
1816 scscr &= ~SCSCR_TE;
1817 } else {
1818 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO;
1819 scscr |= SCSCR_TE;
1820 }
1821
1822 serial_port_out(port, SCSPTR, scsptr);
1823 serial_port_out(port, SCSCR, scscr);
1da177e4
LT		 1824}
1825
1826static int sci_startup(struct uart_port *port)
1827{
a5660ada 1828 struct sci_port *s = to_sci_port(port);
073e84c9 1829 int ret;
1da177e4 1830
73a19e4c
GL		 1831 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1832
073e84c9
PM		 1833 ret = sci_request_irq(s);
1834 if (unlikely(ret < 0))
1835 return ret;
1836
73a19e4c 1837 sci_request_dma(port);
073e84c9 1838
1da177e4
LT		 1839 return 0;
1840}
1841
1842static void sci_shutdown(struct uart_port *port)
1843{
a5660ada 1844 struct sci_port *s = to_sci_port(port);
33b48e16 1845 unsigned long flags;
5fd2b6ee 1846 u16 scr;
1da177e4 1847
73a19e4c
GL		 1848 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1849
33f50ffc 1850 s->autorts = false;
f907c9ea
GU		 1851 mctrl_gpio_disable_ms(to_sci_port(port)->gpios);
1852
33b48e16 1853 spin_lock_irqsave(&port->lock, flags);
1da177e4 1854 sci_stop_rx(port);
b129a8cc 1855 sci_stop_tx(port);
5fd2b6ee
GU		 1856 /* Stop RX and TX, disable related interrupts, keep clock source */
1857 scr = serial_port_in(port, SCSCR);
1858 serial_port_out(port, SCSCR, scr & (SCSCR_CKE1 | SCSCR_CKE0));
33b48e16 1859 spin_unlock_irqrestore(&port->lock, flags);
073e84c9 1860
9ab76556
AM		 1861#ifdef CONFIG_SERIAL_SH_SCI_DMA
1862 if (s->chan_rx) {
1863 dev_dbg(port->dev, "%s(%d) deleting rx_timer\n", __func__,
1864 port->line);
1865 del_timer_sync(&s->rx_timer);
1866 }
1867#endif
1868
73a19e4c 1869 sci_free_dma(port);
1da177e4 1870 sci_free_irq(s);
1da177e4
LT		 1871}
1872
6af27bf2
GU		 1873static int sci_sck_calc(struct sci_port *s, unsigned int bps,
1874 unsigned int *srr)
26c92f37 1875{
6af27bf2 1876 unsigned long freq = s->clk_rates[SCI_SCK];
6af27bf2 1877 int err, min_err = INT_MAX;
69eee8e9 1878 unsigned int sr;
6af27bf2 1879
7b5c0c08
GU		 1880 if (s->port.type != PORT_HSCIF)
1881 freq *= 2;
6af27bf2 1882
69eee8e9 1883 for_each_sr(sr, s) {
6af27bf2
GU		 1884 err = DIV_ROUND_CLOSEST(freq, sr) - bps;
1885 if (abs(err) >= abs(min_err))
1886 continue;
1887
1888 min_err = err;
1889 *srr = sr - 1;
ec09c5eb 1890
6af27bf2
GU		 1891 if (!err)
1892 break;
1893 }
e8183a6c 1894
6af27bf2
GU		 1895 dev_dbg(s->port.dev, "SCK: %u%+d bps using SR %u\n", bps, min_err,
1896 *srr + 1);
1897 return min_err;
26c92f37
PM		 1898}
1899
1270f865
GU		 1900static int sci_brg_calc(struct sci_port *s, unsigned int bps,
1901 unsigned long freq, unsigned int *dlr,
1902 unsigned int *srr)
730c4e78 1903{
1270f865 1904 int err, min_err = INT_MAX;
69eee8e9 1905 unsigned int sr, dl;
730c4e78 1906
7b5c0c08
GU		 1907 if (s->port.type != PORT_HSCIF)
1908 freq *= 2;
730c4e78 1909
69eee8e9 1910 for_each_sr(sr, s) {
1270f865
GU		 1911 dl = DIV_ROUND_CLOSEST(freq, sr * bps);
1912 dl = clamp(dl, 1U, 65535U);
1913
1914 err = DIV_ROUND_CLOSEST(freq, sr * dl) - bps;
1915 if (abs(err) >= abs(min_err))
1916 continue;
1917
1918 min_err = err;
1919 *dlr = dl;
1920 *srr = sr - 1;
1921
1922 if (!err)
1923 break;
1924 }
730c4e78 1925
1270f865
GU		 1926 dev_dbg(s->port.dev, "BRG: %u%+d bps using DL %u SR %u\n", bps,
1927 min_err, *dlr, *srr + 1);
1928 return min_err;
1929}
730c4e78 1930
b4a5c459 1931/* calculate sample rate, BRR, and clock select */
f4998e55
GU		 1932static int sci_scbrr_calc(struct sci_port *s, unsigned int bps,
1933 unsigned int *brr, unsigned int *srr,
1934 unsigned int *cks)
f303b364 1935{
f4998e55 1936 unsigned long freq = s->clk_rates[SCI_FCK];
69eee8e9 1937 unsigned int sr, br, prediv, scrate, c;
6c51332d 1938 int err, min_err = INT_MAX;
f303b364 1939
7b5c0c08
GU		 1940 if (s->port.type != PORT_HSCIF)
1941 freq *= 2;
b4a5c459 1942
6c51332d
GU		 1943 /*
1944 * Find the combination of sample rate and clock select with the
1945 * smallest deviation from the desired baud rate.
1946 * Prefer high sample rates to maximise the receive margin.
1947 *
1948 * M: Receive margin (%)
1949 * N: Ratio of bit rate to clock (N = sampling rate)
1950 * D: Clock duty (D = 0 to 1.0)
1951 * L: Frame length (L = 9 to 12)
1952 * F: Absolute value of clock frequency deviation
1953 *
1954 * M = |(0.5 - 1 / 2 * N) - ((L - 0.5) * F) -
1955 * (|D - 0.5| / N * (1 + F))|
1956 * NOTE: Usually, treat D for 0.5, F is 0 by this calculation.
1957 */
69eee8e9 1958 for_each_sr(sr, s) {
f303b364
UH		 1959 for (c = 0; c <= 3; c++) {
1960 /* integerized formulas from HSCIF documentation */
7b5c0c08 1961 prediv = sr * (1 << (2 * c + 1));
de01e6cd
GU		 1962
1963 /*
1964 * We need to calculate:
1965 *
1966 * br = freq / (prediv * bps) clamped to [1..256]
881a7489 1967 * err = freq / (br * prediv) - bps
730c4e78 1968 *
de01e6cd
GU		 1969 * Watch out for overflow when calculating the desired
1970 * sampling clock rate!
730c4e78 1971 */
de01e6cd
GU		 1972 if (bps > UINT_MAX / prediv)
1973 break;
1974
1975 scrate = prediv * bps;
1976 br = DIV_ROUND_CLOSEST(freq, scrate);
95a2703e 1977 br = clamp(br, 1U, 256U);
6c51332d 1978
881a7489 1979 err = DIV_ROUND_CLOSEST(freq, br * prediv) - bps;
6c51332d 1980 if (abs(err) >= abs(min_err))
730c4e78
NI		 1981 continue;
1982
6c51332d 1983 min_err = err;
95a2703e 1984 *brr = br - 1;
730c4e78
NI		 1985 *srr = sr - 1;
1986 *cks = c;
6c51332d
GU		 1987
1988 if (!err)
1989 goto found;
f303b364
UH		 1990 }
1991 }
1992
6c51332d 1993found:
881a7489
GU		 1994 dev_dbg(s->port.dev, "BRR: %u%+d bps using N %u SR %u cks %u\n", bps,
1995 min_err, *brr, *srr + 1, *cks);
f4998e55 1996 return min_err;
f303b364
UH		 1997}
1998
1ba76220
MD		 1999static void sci_reset(struct uart_port *port)
2000{
d3184e68 2001 const struct plat_sci_reg *reg;
1ba76220
MD		 2002 unsigned int status;
2003
2004 do {
b12bb29f 2005 status = serial_port_in(port, SCxSR);
1ba76220
MD		 2006 } while (!(status & SCxSR_TEND(port)));
2007
b12bb29f 2008 serial_port_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */
1ba76220 2009
0979e0e6
PM		 2010 reg = sci_getreg(port, SCFCR);
2011 if (reg->size)
b12bb29f 2012 serial_port_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
2768cf42
GU		 2013
2014 sci_clear_SCxSR(port,
2015 SCxSR_RDxF_CLEAR(port) & SCxSR_ERROR_CLEAR(port) &
2016 SCxSR_BREAK_CLEAR(port));
fc2af334
GU		 2017 if (sci_getreg(port, SCLSR)->size) {
2018 status = serial_port_in(port, SCLSR);
2019 status &= ~(SCLSR_TO | SCLSR_ORER);
2020 serial_port_out(port, SCLSR, status);
2021 }
1ba76220
MD		 2022}
2023
606d099c
AC		 2024static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
2025 struct ktermios *old)
1da177e4 2026{
95ee05c7 2027 unsigned int baud, smr_val = SCSMR_ASYNC, scr_val = 0, i;
1270f865
GU		 2028 unsigned int brr = 255, cks = 0, srr = 15, dl = 0, sccks = 0;
2029 unsigned int brr1 = 255, cks1 = 0, srr1 = 15, dl1 = 0;
00b9de9c 2030 struct sci_port *s = to_sci_port(port);
d3184e68 2031 const struct plat_sci_reg *reg;
f4998e55
GU		 2032 int min_err = INT_MAX, err;
2033 unsigned long max_freq = 0;
2034 int best_clk = -1;
1da177e4 2035
730c4e78
NI		 2036 if ((termios->c_cflag & CSIZE) == CS7)
2037 smr_val |= SCSMR_CHR;
2038 if (termios->c_cflag & PARENB)
2039 smr_val |= SCSMR_PE;
2040 if (termios->c_cflag & PARODD)
2041 smr_val |= SCSMR_PE | SCSMR_ODD;
2042 if (termios->c_cflag & CSTOPB)
2043 smr_val |= SCSMR_STOP;
2044
154280fd
MD		 2045 /*
2046 * earlyprintk comes here early on with port->uartclk set to zero.
2047 * the clock framework is not up and running at this point so here
2048 * we assume that 115200 is the maximum baud rate. please note that
2049 * the baud rate is not programmed during earlyprintk - it is assumed
2050 * that the previous boot loader has enabled required clocks and
2051 * setup the baud rate generator hardware for us already.
2052 */
f4998e55
GU		 2053 if (!port->uartclk) {
2054 baud = uart_get_baud_rate(port, termios, old, 0, 115200);
2055 goto done;
2056 }
1da177e4 2057
f4998e55
GU		 2058 for (i = 0; i < SCI_NUM_CLKS; i++)
2059 max_freq = max(max_freq, s->clk_rates[i]);
2060
69eee8e9 2061 baud = uart_get_baud_rate(port, termios, old, 0, max_freq / min_sr(s));
f4998e55
GU		 2062 if (!baud)
2063 goto done;
2064
2065 /*
2066 * There can be multiple sources for the sampling clock. Find the one
2067 * that gives us the smallest deviation from the desired baud rate.
2068 */
2069
6af27bf2
GU		 2070 /* Optional Undivided External Clock */
2071 if (s->clk_rates[SCI_SCK] && port->type != PORT_SCIFA &&
2072 port->type != PORT_SCIFB) {
2073 err = sci_sck_calc(s, baud, &srr1);
2074 if (abs(err) < abs(min_err)) {
2075 best_clk = SCI_SCK;
2076 scr_val = SCSCR_CKE1;
2077 sccks = SCCKS_CKS;
2078 min_err = err;
2079 srr = srr1;
2080 if (!err)
2081 goto done;
2082 }
2083 }
2084
1270f865
GU		 2085 /* Optional BRG Frequency Divided External Clock */
2086 if (s->clk_rates[SCI_SCIF_CLK] && sci_getreg(port, SCDL)->size) {
2087 err = sci_brg_calc(s, baud, s->clk_rates[SCI_SCIF_CLK], &dl1,
2088 &srr1);
2089 if (abs(err) < abs(min_err)) {
2090 best_clk = SCI_SCIF_CLK;
2091 scr_val = SCSCR_CKE1;
2092 sccks = 0;
2093 min_err = err;
2094 dl = dl1;
2095 srr = srr1;
2096 if (!err)
2097 goto done;
2098 }
2099 }
2100
2101 /* Optional BRG Frequency Divided Internal Clock */
2102 if (s->clk_rates[SCI_BRG_INT] && sci_getreg(port, SCDL)->size) {
2103 err = sci_brg_calc(s, baud, s->clk_rates[SCI_BRG_INT], &dl1,
2104 &srr1);
2105 if (abs(err) < abs(min_err)) {
2106 best_clk = SCI_BRG_INT;
2107 scr_val = SCSCR_CKE1;
2108 sccks = SCCKS_XIN;
2109 min_err = err;
2110 dl = dl1;
2111 srr = srr1;
2112 if (!min_err)
2113 goto done;
f303b364
UH		 2114 }
2115 }
e108b2ca 2116
f4998e55
GU		 2117 /* Divided Functional Clock using standard Bit Rate Register */
2118 err = sci_scbrr_calc(s, baud, &brr1, &srr1, &cks1);
2119 if (abs(err) < abs(min_err)) {
2120 best_clk = SCI_FCK;
6af27bf2 2121 scr_val = 0;
f4998e55
GU		 2122 min_err = err;
2123 brr = brr1;
2124 srr = srr1;
2125 cks = cks1;
2126 }
2127
2128done:
2129 if (best_clk >= 0)
2130 dev_dbg(port->dev, "Using clk %pC for %u%+d bps\n",
2131 s->clks[best_clk], baud, min_err);
e108b2ca 2132
23241d43 2133 sci_port_enable(s);
36003386 2134
6af27bf2
GU		 2135 /*
2136 * Program the optional External Baud Rate Generator (BRG) first.
2137 * It controls the mux to select (H)SCK or frequency divided clock.
2138 */
1270f865
GU		 2139 if (best_clk >= 0 && sci_getreg(port, SCCKS)->size) {
2140 serial_port_out(port, SCDL, dl);
6af27bf2 2141 serial_port_out(port, SCCKS, sccks);
1270f865 2142 }
1da177e4 2143
1ba76220 2144 sci_reset(port);
1da177e4
LT		 2145
2146 uart_update_timeout(port, termios->c_cflag, baud);
2147
f4998e55 2148 if (best_clk >= 0) {
92a05748
GU		 2149 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
2150 switch (srr + 1) {
2151 case 5: smr_val |= SCSMR_SRC_5; break;
2152 case 7: smr_val |= SCSMR_SRC_7; break;
2153 case 11: smr_val |= SCSMR_SRC_11; break;
2154 case 13: smr_val |= SCSMR_SRC_13; break;
2155 case 16: smr_val |= SCSMR_SRC_16; break;
2156 case 17: smr_val |= SCSMR_SRC_17; break;
2157 case 19: smr_val |= SCSMR_SRC_19; break;
2158 case 27: smr_val |= SCSMR_SRC_27; break;
2159 }
f4998e55 2160 smr_val |= cks;
6af27bf2 2161 dev_dbg(port->dev,
1270f865
GU		 2162 "SCR 0x%x SMR 0x%x BRR %u CKS 0x%x DL %u SRR %u\n",
2163 scr_val, smr_val, brr, sccks, dl, srr);
6af27bf2 2164 serial_port_out(port, SCSCR, scr_val);
f4998e55
GU		 2165 serial_port_out(port, SCSMR, smr_val);
2166 serial_port_out(port, SCBRR, brr);
2167 if (sci_getreg(port, HSSRR)->size)
f303b364 2168 serial_port_out(port, HSSRR, srr | HSCIF_SRE);
f4998e55
GU		 2169
2170 /* Wait one bit interval */
2171 udelay((1000000 + (baud - 1)) / baud);
2172 } else {
2173 /* Don't touch the bit rate configuration */
2174 scr_val = s->cfg->scscr & (SCSCR_CKE1 | SCSCR_CKE0);
3a964abe
GU		 2175 smr_val |= serial_port_in(port, SCSMR) &
2176 (SCSMR_CKEDG | SCSMR_SRC_MASK | SCSMR_CKS);
f4998e55
GU		 2177 dev_dbg(port->dev, "SCR 0x%x SMR 0x%x\n", scr_val, smr_val);
2178 serial_port_out(port, SCSCR, scr_val);
9d482cc3 2179 serial_port_out(port, SCSMR, smr_val);
f4998e55 2180 }
1da177e4 2181
d5701647 2182 sci_init_pins(port, termios->c_cflag);
0979e0e6 2183
33f50ffc
GU		 2184 port->status &= ~UPSTAT_AUTOCTS;
2185 s->autorts = false;
73c3d53f
PM		 2186 reg = sci_getreg(port, SCFCR);
2187 if (reg->size) {
b12bb29f 2188 unsigned short ctrl = serial_port_in(port, SCFCR);
0979e0e6 2189
33f50ffc
GU		 2190 if ((port->flags & UPF_HARD_FLOW) &&
2191 (termios->c_cflag & CRTSCTS)) {
2192 /* There is no CTS interrupt to restart the hardware */
2193 port->status |= UPSTAT_AUTOCTS;
2194 /* MCE is enabled when RTS is raised */
2195 s->autorts = true;
faf02f8f 2196 }
73c3d53f
PM		 2197
2198 /*
2199 * As we've done a sci_reset() above, ensure we don't
2200 * interfere with the FIFOs while toggling MCE. As the
2201 * reset values could still be set, simply mask them out.
2202 */
2203 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST);
2204
b12bb29f 2205 serial_port_out(port, SCFCR, ctrl);
0979e0e6 2206 }
b7a76e4b 2207
9f8325b3
LP		 2208 scr_val |= SCSCR_RE | SCSCR_TE |
2209 (s->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0));
f4998e55
GU		 2210 dev_dbg(port->dev, "SCSCR 0x%x\n", scr_val);
2211 serial_port_out(port, SCSCR, scr_val);
92a05748
GU		 2212 if ((srr + 1 == 5) &&
2213 (port->type == PORT_SCIFA || port->type == PORT_SCIFB)) {
2214 /*
2215 * In asynchronous mode, when the sampling rate is 1/5, first
2216 * received data may become invalid on some SCIFA and SCIFB.
2217 * To avoid this problem wait more than 1 serial data time (1
2218 * bit time x serial data number) after setting SCSCR.RE = 1.
2219 */
2220 udelay(DIV_ROUND_UP(10 * 1000000, baud));
2221 }
1da177e4 2222
3089f381
GL		 2223#ifdef CONFIG_SERIAL_SH_SCI_DMA
2224 /*
5f6d8515 2225 * Calculate delay for 2 DMA buffers (4 FIFO).
f5835c1d
GU		 2226 * See serial_core.c::uart_update_timeout().
2227 * With 10 bits (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above
2228 * function calculates 1 jiffie for the data plus 5 jiffies for the
2229 * "slop(e)." Then below we calculate 5 jiffies (20ms) for 2 DMA
2230 * buffers (4 FIFO sizes), but when performing a faster transfer, the
2231 * value obtained by this formula is too small. Therefore, if the value
2232 * is smaller than 20ms, use 20ms as the timeout value for DMA.
3089f381
GL		 2233 */
2234 if (s->chan_rx) {
5f6d8515
NI		 2235 unsigned int bits;
2236
2237 /* byte size and parity */
2238 switch (termios->c_cflag & CSIZE) {
2239 case CS5:
2240 bits = 7;
2241 break;
2242 case CS6:
2243 bits = 8;
2244 break;
2245 case CS7:
2246 bits = 9;
2247 break;
2248 default:
2249 bits = 10;
2250 break;
2251 }
2252
2253 if (termios->c_cflag & CSTOPB)
2254 bits++;
2255 if (termios->c_cflag & PARENB)
2256 bits++;
2257 s->rx_timeout = DIV_ROUND_UP((s->buf_len_rx * 2 * bits * HZ) /
2258 (baud / 10), 10);
9b971cd2 2259 dev_dbg(port->dev, "DMA Rx t-out %ums, tty t-out %u jiffies\n",
3089f381
GL		 2260 s->rx_timeout * 1000 / HZ, port->timeout);
2261 if (s->rx_timeout < msecs_to_jiffies(20))
2262 s->rx_timeout = msecs_to_jiffies(20);
2263 }
2264#endif
2265
1da177e4 2266 if ((termios->c_cflag & CREAD) != 0)
73a19e4c 2267 sci_start_rx(port);
36003386 2268
23241d43 2269 sci_port_disable(s);
f907c9ea
GU		 2270
2271 if (UART_ENABLE_MS(port, termios->c_cflag))
2272 sci_enable_ms(port);
1da177e4
LT		 2273}
2274
0174e5ca
TK		 2275static void sci_pm(struct uart_port *port, unsigned int state,
2276 unsigned int oldstate)
2277{
2278 struct sci_port *sci_port = to_sci_port(port);
2279
2280 switch (state) {
d3dfe5d9 2281 case UART_PM_STATE_OFF:
0174e5ca
TK		 2282 sci_port_disable(sci_port);
2283 break;
2284 default:
2285 sci_port_enable(sci_port);
2286 break;
2287 }
2288}
2289
1da177e4
LT		 2290static const char *sci_type(struct uart_port *port)
2291{
2292 switch (port->type) {
e7c98dc7
MT		 2293 case PORT_IRDA:
2294 return "irda";
2295 case PORT_SCI:
2296 return "sci";
2297 case PORT_SCIF:
2298 return "scif";
2299 case PORT_SCIFA:
2300 return "scifa";
d1d4b10c
GL		 2301 case PORT_SCIFB:
2302 return "scifb";
f303b364
UH		 2303 case PORT_HSCIF:
2304 return "hscif";
1da177e4
LT		 2305 }
2306
fa43972f 2307 return NULL;
1da177e4
LT		 2308}
2309
f6e9495d
PM		 2310static int sci_remap_port(struct uart_port *port)
2311{
e4d6f911 2312 struct sci_port *sport = to_sci_port(port);
f6e9495d
PM		 2313
2314 /*
2315 * Nothing to do if there's already an established membase.
2316 */
2317 if (port->membase)
2318 return 0;
2319
3d73f32b 2320 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) {
e4d6f911 2321 port->membase = ioremap_nocache(port->mapbase, sport->reg_size);
f6e9495d
PM		 2322 if (unlikely(!port->membase)) {
2323 dev_err(port->dev, "can't remap port#%d\n", port->line);
2324 return -ENXIO;
2325 }
2326 } else {
2327 /*
2328 * For the simple (and majority of) cases where we don't
2329 * need to do any remapping, just cast the cookie
2330 * directly.
2331 */
3af4e960 2332 port->membase = (void __iomem *)(uintptr_t)port->mapbase;
f6e9495d
PM		 2333 }
2334
2335 return 0;
2336}
2337
e2651647 2338static void sci_release_port(struct uart_port *port)
1da177e4 2339{
e4d6f911
YS		 2340 struct sci_port *sport = to_sci_port(port);
2341
3d73f32b 2342 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) {
e2651647
PM		 2343 iounmap(port->membase);
2344 port->membase = NULL;
2345 }
2346
e4d6f911 2347 release_mem_region(port->mapbase, sport->reg_size);
1da177e4
LT		 2348}
2349
e2651647 2350static int sci_request_port(struct uart_port *port)
1da177e4 2351{
e2651647 2352 struct resource *res;
e4d6f911 2353 struct sci_port *sport = to_sci_port(port);
f6e9495d 2354 int ret;
1da177e4 2355
e4d6f911
YS		 2356 res = request_mem_region(port->mapbase, sport->reg_size,
2357 dev_name(port->dev));
2358 if (unlikely(res == NULL)) {
2359 dev_err(port->dev, "request_mem_region failed.");
e2651647 2360 return -EBUSY;
e4d6f911 2361 }
1da177e4 2362
f6e9495d
PM		 2363 ret = sci_remap_port(port);
2364 if (unlikely(ret != 0)) {
2365 release_resource(res);
2366 return ret;
7ff731ae 2367 }
e2651647
PM		 2368
2369 return 0;
2370}
2371
2372static void sci_config_port(struct uart_port *port, int flags)
2373{
2374 if (flags & UART_CONFIG_TYPE) {
2375 struct sci_port *sport = to_sci_port(port);
2376
2377 port->type = sport->cfg->type;
2378 sci_request_port(port);
2379 }
1da177e4
LT		 2380}
2381
2382static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
2383{
1da177e4
LT		 2384 if (ser->baud_base < 2400)
2385 /* No paper tape reader for Mitch.. */
2386 return -EINVAL;
2387
2388 return 0;
2389}
2390
069a47e5 2391static const struct uart_ops sci_uart_ops = {
1da177e4
LT		 2392 .tx_empty = sci_tx_empty,
2393 .set_mctrl = sci_set_mctrl,
2394 .get_mctrl = sci_get_mctrl,
2395 .start_tx = sci_start_tx,
2396 .stop_tx = sci_stop_tx,
2397 .stop_rx = sci_stop_rx,
f907c9ea 2398 .enable_ms = sci_enable_ms,
1da177e4
LT		 2399 .break_ctl = sci_break_ctl,
2400 .startup = sci_startup,
2401 .shutdown = sci_shutdown,
2402 .set_termios = sci_set_termios,
0174e5ca 2403 .pm = sci_pm,
1da177e4
LT		 2404 .type = sci_type,
2405 .release_port = sci_release_port,
2406 .request_port = sci_request_port,
2407 .config_port = sci_config_port,
2408 .verify_port = sci_verify_port,
07d2a1a1
PM		 2409#ifdef CONFIG_CONSOLE_POLL
2410 .poll_get_char = sci_poll_get_char,
2411 .poll_put_char = sci_poll_put_char,
2412#endif
1da177e4
LT		 2413};
2414
a9ec81f4
LP		 2415static int sci_init_clocks(struct sci_port *sci_port, struct device *dev)
2416{
f4998e55
GU		 2417 const char *clk_names[] = {
2418 [SCI_FCK] = "fck",
6af27bf2 2419 [SCI_SCK] = "sck",
1270f865
GU		 2420 [SCI_BRG_INT] = "brg_int",
2421 [SCI_SCIF_CLK] = "scif_clk",
f4998e55
GU		 2422 };
2423 struct clk *clk;
2424 unsigned int i;
a9ec81f4 2425
6af27bf2
GU		 2426 if (sci_port->cfg->type == PORT_HSCIF)
2427 clk_names[SCI_SCK] = "hsck";
2428
f4998e55
GU		 2429 for (i = 0; i < SCI_NUM_CLKS; i++) {
2430 clk = devm_clk_get(dev, clk_names[i]);
2431 if (PTR_ERR(clk) == -EPROBE_DEFER)
2432 return -EPROBE_DEFER;
a9ec81f4 2433
f4998e55
GU		 2434 if (IS_ERR(clk) && i == SCI_FCK) {
2435 /*
2436 * "fck" used to be called "sci_ick", and we need to
2437 * maintain DT backward compatibility.
2438 */
2439 clk = devm_clk_get(dev, "sci_ick");
2440 if (PTR_ERR(clk) == -EPROBE_DEFER)
2441 return -EPROBE_DEFER;
a9ec81f4 2442
f4998e55
GU		 2443 if (!IS_ERR(clk))
2444 goto found;
a9ec81f4 2445
f4998e55
GU		 2446 /*
2447 * Not all SH platforms declare a clock lookup entry
2448 * for SCI devices, in which case we need to get the
2449 * global "peripheral_clk" clock.
2450 */
2451 clk = devm_clk_get(dev, "peripheral_clk");
2452 if (!IS_ERR(clk))
2453 goto found;
2454
2455 dev_err(dev, "failed to get %s (%ld)\n", clk_names[i],
2456 PTR_ERR(clk));
2457 return PTR_ERR(clk);
2458 }
2459
2460found:
2461 if (IS_ERR(clk))
2462 dev_dbg(dev, "failed to get %s (%ld)\n", clk_names[i],
2463 PTR_ERR(clk));
2464 else
2465 dev_dbg(dev, "clk %s is %pC rate %pCr\n", clk_names[i],
2466 clk, clk);
2467 sci_port->clks[i] = IS_ERR(clk) ? NULL : clk;
2468 }
2469 return 0;
a9ec81f4
LP		 2470}
2471
daf5a895
LP		 2472static const struct sci_port_params *
2473sci_probe_regmap(const struct plat_sci_port *cfg)
2474{
2475 unsigned int regtype;
2476
2477 if (cfg->regtype != SCIx_PROBE_REGTYPE)
2478 return &sci_port_params[cfg->regtype];
2479
2480 switch (cfg->type) {
2481 case PORT_SCI:
2482 regtype = SCIx_SCI_REGTYPE;
2483 break;
2484 case PORT_IRDA:
2485 regtype = SCIx_IRDA_REGTYPE;
2486 break;
2487 case PORT_SCIFA:
2488 regtype = SCIx_SCIFA_REGTYPE;
2489 break;
2490 case PORT_SCIFB:
2491 regtype = SCIx_SCIFB_REGTYPE;
2492 break;
2493 case PORT_SCIF:
2494 /*
2495 * The SH-4 is a bit of a misnomer here, although that's
2496 * where this particular port layout originated. This
2497 * configuration (or some slight variation thereof)
2498 * remains the dominant model for all SCIFs.
2499 */
2500 regtype = SCIx_SH4_SCIF_REGTYPE;
2501 break;
2502 case PORT_HSCIF:
2503 regtype = SCIx_HSCIF_REGTYPE;
2504 break;
2505 default:
2506 pr_err("Can't probe register map for given port\n");
2507 return NULL;
2508 }
2509
2510 return &sci_port_params[regtype];
2511}
2512
9671f099 2513static int sci_init_single(struct platform_device *dev,
1fcc91a6 2514 struct sci_port *sci_port, unsigned int index,
daf5a895 2515 const struct plat_sci_port *p, bool early)
e108b2ca 2516{
73a19e4c 2517 struct uart_port *port = &sci_port->port;
1fcc91a6
LP		 2518 const struct resource *res;
2519 unsigned int i;
3127c6b2 2520 int ret;
e108b2ca 2521
50f0959a
PM		 2522 sci_port->cfg = p;
2523
73a19e4c
GL		 2524 port->ops = &sci_uart_ops;
2525 port->iotype = UPIO_MEM;
2526 port->line = index;
75136d48 2527
89b5c1ab
LP		 2528 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
2529 if (res == NULL)
2530 return -ENOMEM;
1fcc91a6 2531
89b5c1ab 2532 port->mapbase = res->start;
e4d6f911 2533 sci_port->reg_size = resource_size(res);
1fcc91a6 2534
89b5c1ab
LP		 2535 for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i)
2536 sci_port->irqs[i] = platform_get_irq(dev, i);
1fcc91a6 2537
89b5c1ab
LP		 2538 /* The SCI generates several interrupts. They can be muxed together or
2539 * connected to different interrupt lines. In the muxed case only one
2540 * interrupt resource is specified. In the non-muxed case three or four
2541 * interrupt resources are specified, as the BRI interrupt is optional.
2542 */
2543 if (sci_port->irqs[0] < 0)
2544 return -ENXIO;
1fcc91a6 2545
89b5c1ab
LP		 2546 if (sci_port->irqs[1] < 0) {
2547 sci_port->irqs[1] = sci_port->irqs[0];
2548 sci_port->irqs[2] = sci_port->irqs[0];
2549 sci_port->irqs[3] = sci_port->irqs[0];
1fcc91a6
LP		 2550 }
2551
daf5a895
LP		 2552 sci_port->params = sci_probe_regmap(p);
2553 if (unlikely(sci_port->params == NULL))
2554 return -EINVAL;
e095ee6b 2555
878fbb91
LP		 2556 /* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't
2557 * match the SoC datasheet, this should be investigated. Let platform
2558 * data override the sampling rate for now.
ec09c5eb 2559 */
b2f20ed9
LP		 2560 sci_port->sampling_rate_mask = p->sampling_rate
2561 ? SCI_SR(p->sampling_rate)
2562 : sci_port->params->sampling_rate_mask;
ec09c5eb 2563
1fcc91a6 2564 if (!early) {
a9ec81f4
LP		 2565 ret = sci_init_clocks(sci_port, &dev->dev);
2566 if (ret < 0)
2567 return ret;
c7ed1ab3 2568
73a19e4c 2569 port->dev = &dev->dev;
5e50d2d6
MD		 2570
2571 pm_runtime_enable(&dev->dev);
7b6fd3bf 2572 }
e108b2ca 2573
ce6738b6 2574 port->type = p->type;
3d73f32b 2575 port->flags = UPF_FIXED_PORT | UPF_BOOT_AUTOCONF | p->flags;
61a6976b 2576 port->regshift = p->regshift;
b2f20ed9 2577 port->fifosize = sci_port->params->fifosize;
73a19e4c 2578
ce6738b6 2579 /*
61a6976b 2580 * The UART port needs an IRQ value, so we peg this to the RX IRQ
ce6738b6
PM		 2581 * for the multi-IRQ ports, which is where we are primarily
2582 * concerned with the shutdown path synchronization.
2583 *
2584 * For the muxed case there's nothing more to do.
2585 */
1fcc91a6 2586 port->irq = sci_port->irqs[SCIx_RXI_IRQ];
9cfb5c05 2587 port->irqflags = 0;
73a19e4c 2588
61a6976b
PM		 2589 port->serial_in = sci_serial_in;
2590 port->serial_out = sci_serial_out;
2591
c7ed1ab3 2592 return 0;
e108b2ca
PM		 2593}
2594
6dae1421
LP		 2595static void sci_cleanup_single(struct sci_port *port)
2596{
6dae1421
LP		 2597 pm_runtime_disable(port->port.dev);
2598}
2599
0b0cced1
YS		 2600#if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \
2601 defined(CONFIG_SERIAL_SH_SCI_EARLYCON)
dc8e6f5b
MD		 2602static void serial_console_putchar(struct uart_port *port, int ch)
2603{
2604 sci_poll_put_char(port, ch);
2605}
2606
1da177e4
LT		 2607/*
2608 * Print a string to the serial port trying not to disturb
2609 * any possible real use of the port...
2610 */
2611static void serial_console_write(struct console *co, const char *s,
2612 unsigned count)
2613{
906b17dc
PM		 2614 struct sci_port *sci_port = &sci_ports[co->index];
2615 struct uart_port *port = &sci_port->port;
a67969b5 2616 unsigned short bits, ctrl, ctrl_temp;
40f70c03
SK		 2617 unsigned long flags;
2618 int locked = 1;
2619
2620 local_irq_save(flags);
0b0cced1 2621#if defined(SUPPORT_SYSRQ)
40f70c03
SK		 2622 if (port->sysrq)
2623 locked = 0;
0b0cced1
YS		 2624 else
2625#endif
2626 if (oops_in_progress)
40f70c03
SK		 2627 locked = spin_trylock(&port->lock);
2628 else
2629 spin_lock(&port->lock);
2630
a67969b5 2631 /* first save SCSCR then disable interrupts, keep clock source */
40f70c03 2632 ctrl = serial_port_in(port, SCSCR);
9f8325b3
LP		 2633 ctrl_temp = SCSCR_RE | SCSCR_TE |
2634 (sci_port->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)) |
a67969b5
GU		 2635 (ctrl & (SCSCR_CKE1 | SCSCR_CKE0));
2636 serial_port_out(port, SCSCR, ctrl_temp);
07d2a1a1 2637
501b825d 2638 uart_console_write(port, s, count, serial_console_putchar);
973e5d52
MD		 2639
2640 /* wait until fifo is empty and last bit has been transmitted */
2641 bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
b12bb29f 2642 while ((serial_port_in(port, SCxSR) & bits) != bits)
973e5d52 2643 cpu_relax();
40f70c03
SK		 2644
2645 /* restore the SCSCR */
2646 serial_port_out(port, SCSCR, ctrl);
2647
2648 if (locked)
2649 spin_unlock(&port->lock);
2650 local_irq_restore(flags);
1da177e4
LT		 2651}
2652
9671f099 2653static int serial_console_setup(struct console *co, char *options)
1da177e4 2654{
dc8e6f5b 2655 struct sci_port *sci_port;
1da177e4
LT		 2656 struct uart_port *port;
2657 int baud = 115200;
2658 int bits = 8;
2659 int parity = 'n';
2660 int flow = 'n';
2661 int ret;
2662
e108b2ca 2663 /*
906b17dc 2664 * Refuse to handle any bogus ports.
1da177e4 2665 */
906b17dc 2666 if (co->index < 0 || co->index >= SCI_NPORTS)
e108b2ca 2667 return -ENODEV;
e108b2ca 2668
906b17dc
PM		 2669 sci_port = &sci_ports[co->index];
2670 port = &sci_port->port;
2671
b2267a6b
AC		 2672 /*
2673 * Refuse to handle uninitialized ports.
2674 */
2675 if (!port->ops)
2676 return -ENODEV;
2677
f6e9495d
PM		 2678 ret = sci_remap_port(port);
2679 if (unlikely(ret != 0))
2680 return ret;
e108b2ca 2681
1da177e4
LT		 2682 if (options)
2683 uart_parse_options(options, &baud, &parity, &bits, &flow);
2684
ab7cfb55 2685 return uart_set_options(port, co, baud, parity, bits, flow);
1da177e4
LT		 2686}
2687
2688static struct console serial_console = {
2689 .name = "ttySC",
906b17dc 2690 .device = uart_console_device,
1da177e4
LT		 2691 .write = serial_console_write,
2692 .setup = serial_console_setup,
fa5da2f7 2693 .flags = CON_PRINTBUFFER,
1da177e4 2694 .index = -1,
906b17dc 2695 .data = &sci_uart_driver,
1da177e4
LT		 2696};
2697
7b6fd3bf
MD		 2698static struct console early_serial_console = {
2699 .name = "early_ttySC",
2700 .write = serial_console_write,
2701 .flags = CON_PRINTBUFFER,
906b17dc 2702 .index = -1,
7b6fd3bf 2703};
ecdf8a46 2704
7b6fd3bf
MD		 2705static char early_serial_buf[32];
2706
9671f099 2707static int sci_probe_earlyprintk(struct platform_device *pdev)
ecdf8a46 2708{
daf5a895 2709 const struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev);
ecdf8a46
PM		 2710
2711 if (early_serial_console.data)
2712 return -EEXIST;
2713
2714 early_serial_console.index = pdev->id;
ecdf8a46 2715
1fcc91a6 2716 sci_init_single(pdev, &sci_ports[pdev->id], pdev->id, cfg, true);
ecdf8a46
PM		 2717
2718 serial_console_setup(&early_serial_console, early_serial_buf);
2719
2720 if (!strstr(early_serial_buf, "keep"))
2721 early_serial_console.flags |= CON_BOOT;
2722
2723 register_console(&early_serial_console);
2724 return 0;
2725}
6a8c9799
NI		 2726
2727#define SCI_CONSOLE (&serial_console)
2728
ecdf8a46 2729#else
9671f099 2730static inline int sci_probe_earlyprintk(struct platform_device *pdev)
ecdf8a46
PM		 2731{
2732 return -EINVAL;
2733}
1da177e4 2734
6a8c9799
NI		 2735#define SCI_CONSOLE NULL
2736
0b0cced1 2737#endif /* CONFIG_SERIAL_SH_SCI_CONSOLE || CONFIG_SERIAL_SH_SCI_EARLYCON */
1da177e4 2738
6c13d5d2 2739static const char banner[] __initconst = "SuperH (H)SCI(F) driver initialized";
1da177e4
LT		 2740
2741static struct uart_driver sci_uart_driver = {
2742 .owner = THIS_MODULE,
2743 .driver_name = "sci",
1da177e4
LT		 2744 .dev_name = "ttySC",
2745 .major = SCI_MAJOR,
2746 .minor = SCI_MINOR_START,
e108b2ca 2747 .nr = SCI_NPORTS,
1da177e4
LT		 2748 .cons = SCI_CONSOLE,
2749};
2750
54507f6e 2751static int sci_remove(struct platform_device *dev)
e552de24 2752{
d535a230 2753 struct sci_port *port = platform_get_drvdata(dev);
e552de24 2754
d535a230
PM		 2755 uart_remove_one_port(&sci_uart_driver, &port->port);
2756
6dae1421 2757 sci_cleanup_single(port);
e552de24 2758
e552de24
MD		 2759 return 0;
2760}
2761
bd2238fb
GU		 2762
2763#define SCI_OF_DATA(type, regtype) (void *)((type) << 16 | (regtype))
2764#define SCI_OF_TYPE(data) ((unsigned long)(data) >> 16)
2765#define SCI_OF_REGTYPE(data) ((unsigned long)(data) & 0xffff)
20bdcab8
BH		 2766
2767static const struct of_device_id of_sci_match[] = {
f443ff80
GU		 2768 /* SoC-specific types */
2769 {
2770 .compatible = "renesas,scif-r7s72100",
2771 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH2_SCIF_FIFODATA_REGTYPE),
2772 },
9ed44bb2
GU		 2773 /* Family-specific types */
2774 {
2775 .compatible = "renesas,rcar-gen1-scif",
2776 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
2777 }, {
2778 .compatible = "renesas,rcar-gen2-scif",
2779 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
2780 }, {
2781 .compatible = "renesas,rcar-gen3-scif",
2782 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
2783 },
f443ff80 2784 /* Generic types */
20bdcab8
BH		 2785 {
2786 .compatible = "renesas,scif",
bd2238fb 2787 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_REGTYPE),
20bdcab8
BH		 2788 }, {
2789 .compatible = "renesas,scifa",
bd2238fb 2790 .data = SCI_OF_DATA(PORT_SCIFA, SCIx_SCIFA_REGTYPE),
20bdcab8
BH		 2791 }, {
2792 .compatible = "renesas,scifb",
bd2238fb 2793 .data = SCI_OF_DATA(PORT_SCIFB, SCIx_SCIFB_REGTYPE),
20bdcab8
BH		 2794 }, {
2795 .compatible = "renesas,hscif",
bd2238fb 2796 .data = SCI_OF_DATA(PORT_HSCIF, SCIx_HSCIF_REGTYPE),
e1d0be61
YS		 2797 }, {
2798 .compatible = "renesas,sci",
bd2238fb 2799 .data = SCI_OF_DATA(PORT_SCI, SCIx_SCI_REGTYPE),
20bdcab8
BH		 2800 }, {
2801 /* Terminator */
2802 },
2803};
2804MODULE_DEVICE_TABLE(of, of_sci_match);
2805
2806static struct plat_sci_port *
2807sci_parse_dt(struct platform_device *pdev, unsigned int *dev_id)
2808{
2809 struct device_node *np = pdev->dev.of_node;
2810 const struct of_device_id *match;
20bdcab8
BH		 2811 struct plat_sci_port *p;
2812 int id;
2813
2814 if (!IS_ENABLED(CONFIG_OF) || !np)
2815 return NULL;
2816
495bb47c 2817 match = of_match_node(of_sci_match, np);
20bdcab8
BH		 2818 if (!match)
2819 return NULL;
2820
20bdcab8 2821 p = devm_kzalloc(&pdev->dev, sizeof(struct plat_sci_port), GFP_KERNEL);
4205463c 2822 if (!p)
20bdcab8 2823 return NULL;
20bdcab8 2824
2095fc76 2825 /* Get the line number from the aliases node. */
20bdcab8
BH		 2826 id = of_alias_get_id(np, "serial");
2827 if (id < 0) {
2828 dev_err(&pdev->dev, "failed to get alias id (%d)\n", id);
2829 return NULL;
2830 }
2831
2832 *dev_id = id;
2833
bd2238fb
GU		 2834 p->type = SCI_OF_TYPE(match->data);
2835 p->regtype = SCI_OF_REGTYPE(match->data);
20bdcab8 2836
861a70ab
GU		 2837 if (of_find_property(np, "uart-has-rtscts", NULL))
2838 p->capabilities |= SCIx_HAVE_RTSCTS;
2839
20bdcab8
BH		 2840 return p;
2841}
2842
9671f099 2843static int sci_probe_single(struct platform_device *dev,
0ee70712
MD		 2844 unsigned int index,
2845 struct plat_sci_port *p,
2846 struct sci_port *sciport)
2847{
0ee70712
MD		 2848 int ret;
2849
2850 /* Sanity check */
2851 if (unlikely(index >= SCI_NPORTS)) {
9b971cd2 2852 dev_notice(&dev->dev, "Attempting to register port %d when only %d are available\n",
0ee70712 2853 index+1, SCI_NPORTS);
9b971cd2 2854 dev_notice(&dev->dev, "Consider bumping CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
b6c5ef6f 2855 return -EINVAL;
0ee70712
MD		 2856 }
2857
1fcc91a6 2858 ret = sci_init_single(dev, sciport, index, p, false);
c7ed1ab3
PM		 2859 if (ret)
2860 return ret;
0ee70712 2861
f907c9ea
GU		 2862 sciport->gpios = mctrl_gpio_init(&sciport->port, 0);
2863 if (IS_ERR(sciport->gpios) && PTR_ERR(sciport->gpios) != -ENOSYS)
2864 return PTR_ERR(sciport->gpios);
2865
2866 if (p->capabilities & SCIx_HAVE_RTSCTS) {
2867 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(sciport->gpios,
2868 UART_GPIO_CTS)) ||
2869 !IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(sciport->gpios,
2870 UART_GPIO_RTS))) {
2871 dev_err(&dev->dev, "Conflicting RTS/CTS config\n");
2872 return -EINVAL;
2873 }
33f50ffc 2874 sciport->port.flags |= UPF_HARD_FLOW;
f907c9ea
GU		 2875 }
2876
6dae1421
LP		 2877 ret = uart_add_one_port(&sci_uart_driver, &sciport->port);
2878 if (ret) {
2879 sci_cleanup_single(sciport);
2880 return ret;
2881 }
2882
2883 return 0;
0ee70712
MD		 2884}
2885
9671f099 2886static int sci_probe(struct platform_device *dev)
1da177e4 2887{
20bdcab8
BH		 2888 struct plat_sci_port *p;
2889 struct sci_port *sp;
2890 unsigned int dev_id;
ecdf8a46 2891 int ret;
d535a230 2892
ecdf8a46
PM		 2893 /*
2894 * If we've come here via earlyprintk initialization, head off to
2895 * the special early probe. We don't have sufficient device state
2896 * to make it beyond this yet.
2897 */
2898 if (is_early_platform_device(dev))
2899 return sci_probe_earlyprintk(dev);
7b6fd3bf 2900
20bdcab8
BH		 2901 if (dev->dev.of_node) {
2902 p = sci_parse_dt(dev, &dev_id);
2903 if (p == NULL)
2904 return -EINVAL;
2905 } else {
2906 p = dev->dev.platform_data;
2907 if (p == NULL) {
2908 dev_err(&dev->dev, "no platform data supplied\n");
2909 return -EINVAL;
2910 }
2911
2912 dev_id = dev->id;
2913 }
2914
2915 sp = &sci_ports[dev_id];
d535a230 2916 platform_set_drvdata(dev, sp);
e552de24 2917
20bdcab8 2918 ret = sci_probe_single(dev, dev_id, p, sp);
d535a230 2919 if (ret)
6dae1421 2920 return ret;
e552de24 2921
1da177e4
LT		 2922#ifdef CONFIG_SH_STANDARD_BIOS
2923 sh_bios_gdb_detach();
2924#endif
2925
e108b2ca 2926 return 0;
1da177e4
LT		 2927}
2928
cb876341 2929static __maybe_unused int sci_suspend(struct device *dev)
1da177e4 2930{
d535a230 2931 struct sci_port *sport = dev_get_drvdata(dev);
e108b2ca 2932
d535a230
PM		 2933 if (sport)
2934 uart_suspend_port(&sci_uart_driver, &sport->port);
1da177e4 2935
e108b2ca
PM		 2936 return 0;
2937}
1da177e4 2938
cb876341 2939static __maybe_unused int sci_resume(struct device *dev)
e108b2ca 2940{
d535a230 2941 struct sci_port *sport = dev_get_drvdata(dev);
e108b2ca 2942
d535a230
PM		 2943 if (sport)
2944 uart_resume_port(&sci_uart_driver, &sport->port);
e108b2ca
PM		 2945
2946 return 0;
2947}
2948
cb876341 2949static SIMPLE_DEV_PM_OPS(sci_dev_pm_ops, sci_suspend, sci_resume);
6daa79b3 2950
e108b2ca
PM		 2951static struct platform_driver sci_driver = {
2952 .probe = sci_probe,
b9e39c89 2953 .remove = sci_remove,
e108b2ca
PM		 2954 .driver = {
2955 .name = "sh-sci",
6daa79b3 2956 .pm = &sci_dev_pm_ops,
20bdcab8 2957 .of_match_table = of_match_ptr(of_sci_match),
e108b2ca
PM		 2958 },
2959};
2960
2961static int __init sci_init(void)
2962{
2963 int ret;
2964
6c13d5d2 2965 pr_info("%s\n", banner);
e108b2ca 2966
e108b2ca
PM		 2967 ret = uart_register_driver(&sci_uart_driver);
2968 if (likely(ret == 0)) {
2969 ret = platform_driver_register(&sci_driver);
2970 if (unlikely(ret))
2971 uart_unregister_driver(&sci_uart_driver);
2972 }
2973
2974 return ret;
2975}
2976
2977static void __exit sci_exit(void)
2978{
2979 platform_driver_unregister(&sci_driver);
1da177e4
LT		 2980 uart_unregister_driver(&sci_uart_driver);
2981}
2982
7b6fd3bf
MD		 2983#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
2984early_platform_init_buffer("earlyprintk", &sci_driver,
2985 early_serial_buf, ARRAY_SIZE(early_serial_buf));
2986#endif
0b0cced1
YS		 2987#ifdef CONFIG_SERIAL_SH_SCI_EARLYCON
2988static struct __init plat_sci_port port_cfg;
2989
2990static int __init early_console_setup(struct earlycon_device *device,
2991 int type)
2992{
2993 if (!device->port.membase)
2994 return -ENODEV;
2995
2996 device->port.serial_in = sci_serial_in;
2997 device->port.serial_out = sci_serial_out;
2998 device->port.type = type;
2999 memcpy(&sci_ports[0].port, &device->port, sizeof(struct uart_port));
daf5a895 3000 port_cfg.type = type;
0b0cced1 3001 sci_ports[0].cfg = &port_cfg;
daf5a895 3002 sci_ports[0].params = sci_probe_regmap(&port_cfg);
9f8325b3
LP		 3003 port_cfg.scscr = sci_serial_in(&sci_ports[0].port, SCSCR);
3004 sci_serial_out(&sci_ports[0].port, SCSCR,
3005 SCSCR_RE | SCSCR_TE | port_cfg.scscr);
0b0cced1
YS		 3006
3007 device->con->write = serial_console_write;
3008 return 0;
3009}
3010static int __init sci_early_console_setup(struct earlycon_device *device,
3011 const char *opt)
3012{
3013 return early_console_setup(device, PORT_SCI);
3014}
3015static int __init scif_early_console_setup(struct earlycon_device *device,
3016 const char *opt)
3017{
3018 return early_console_setup(device, PORT_SCIF);
3019}
3020static int __init scifa_early_console_setup(struct earlycon_device *device,
3021 const char *opt)
3022{
3023 return early_console_setup(device, PORT_SCIFA);
3024}
3025static int __init scifb_early_console_setup(struct earlycon_device *device,
3026 const char *opt)
3027{
3028 return early_console_setup(device, PORT_SCIFB);
3029}
3030static int __init hscif_early_console_setup(struct earlycon_device *device,
3031 const char *opt)
3032{
3033 return early_console_setup(device, PORT_HSCIF);
3034}
3035
0b0cced1 3036OF_EARLYCON_DECLARE(sci, "renesas,sci", sci_early_console_setup);
0b0cced1 3037OF_EARLYCON_DECLARE(scif, "renesas,scif", scif_early_console_setup);
0b0cced1 3038OF_EARLYCON_DECLARE(scifa, "renesas,scifa", scifa_early_console_setup);
0b0cced1 3039OF_EARLYCON_DECLARE(scifb, "renesas,scifb", scifb_early_console_setup);
0b0cced1
YS		 3040OF_EARLYCON_DECLARE(hscif, "renesas,hscif", hscif_early_console_setup);
3041#endif /* CONFIG_SERIAL_SH_SCI_EARLYCON */
3042
1da177e4
LT		 3043module_init(sci_init);
3044module_exit(sci_exit);
3045
e108b2ca 3046MODULE_LICENSE("GPL");
e169c139 3047MODULE_ALIAS("platform:sh-sci");
7f405f9c 3048MODULE_AUTHOR("Paul Mundt");
f303b364 3049MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver");
Linux 6.x block layer and io_uring tree(s)