projects / linux-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
treewide: init_timer() -> setup_timer()
[linux-block.git] / drivers / tty / serial / sh-sci.c
CommitLineData
e3b3d0f5 1// SPDX-License-Identifier: GPL-2.0
1da177e4 2/*
1da177e4
LT		 3 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
4 *
f43dc23d 5 * Copyright (C) 2002 - 2011 Paul Mundt
f4998e55 6 * Copyright (C) 2015 Glider bvba
3ea6bc3d 7 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
1da177e4
LT		 8 *
9 * based off of the old drivers/char/sh-sci.c by:
10 *
11 * Copyright (C) 1999, 2000 Niibe Yutaka
12 * Copyright (C) 2000 Sugioka Toshinobu
13 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
14 * Modified to support SecureEdge. David McCullough (2002)
15 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
d89ddd1c 16 * Removed SH7300 support (Jul 2007).
1da177e4 17 */
0b3d4ef6
PM		 18#if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
19#define SUPPORT_SYSRQ
20#endif
1da177e4
LT		 21
22#undef DEBUG
23
8fb9631c
LP		 24#include <linux/clk.h>
25#include <linux/console.h>
26#include <linux/ctype.h>
27#include <linux/cpufreq.h>
28#include <linux/delay.h>
29#include <linux/dmaengine.h>
30#include <linux/dma-mapping.h>
31#include <linux/err.h>
1da177e4 32#include <linux/errno.h>
8fb9631c 33#include <linux/init.h>
1da177e4 34#include <linux/interrupt.h>
1da177e4 35#include <linux/ioport.h>
8fb9631c
LP		 36#include <linux/major.h>
37#include <linux/module.h>
1da177e4 38#include <linux/mm.h>
20bdcab8 39#include <linux/of.h>
6e605a01 40#include <linux/of_device.h>
8fb9631c 41#include <linux/platform_device.h>
5e50d2d6 42#include <linux/pm_runtime.h>
73a19e4c 43#include <linux/scatterlist.h>
8fb9631c
LP		 44#include <linux/serial.h>
45#include <linux/serial_sci.h>
46#include <linux/sh_dma.h>
5a0e3ad6 47#include <linux/slab.h>
8fb9631c
LP		 48#include <linux/string.h>
49#include <linux/sysrq.h>
50#include <linux/timer.h>
51#include <linux/tty.h>
52#include <linux/tty_flip.h>
85f094ec
PM		 53
54#ifdef CONFIG_SUPERH
1da177e4
LT		 55#include <asm/sh_bios.h>
56#endif
57
f907c9ea 58#include "serial_mctrl_gpio.h"
1da177e4
LT		 59#include "sh-sci.h"
60
89b5c1ab
LP		 61/* Offsets into the sci_port->irqs array */
62enum {
63 SCIx_ERI_IRQ,
64 SCIx_RXI_IRQ,
65 SCIx_TXI_IRQ,
66 SCIx_BRI_IRQ,
67 SCIx_NR_IRQS,
68
69 SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */
70};
71
72#define SCIx_IRQ_IS_MUXED(port) \
73 ((port)->irqs[SCIx_ERI_IRQ] == \
74 (port)->irqs[SCIx_RXI_IRQ]) || \
75 ((port)->irqs[SCIx_ERI_IRQ] && \
76 ((port)->irqs[SCIx_RXI_IRQ] < 0))
77
f4998e55
GU		 78enum SCI_CLKS {
79 SCI_FCK, /* Functional Clock */
6af27bf2 80 SCI_SCK, /* Optional External Clock */
1270f865
GU		 81 SCI_BRG_INT, /* Optional BRG Internal Clock Source */
82 SCI_SCIF_CLK, /* Optional BRG External Clock Source */
f4998e55
GU		 83 SCI_NUM_CLKS
84};
85
69eee8e9
GU		 86/* Bit x set means sampling rate x + 1 is supported */
87#define SCI_SR(x) BIT((x) - 1)
88#define SCI_SR_RANGE(x, y) GENMASK((y) - 1, (x) - 1)
89
92a05748
GU		 90#define SCI_SR_SCIFAB SCI_SR(5) | SCI_SR(7) | SCI_SR(11) | \
91 SCI_SR(13) | SCI_SR(16) | SCI_SR(17) | \
92 SCI_SR(19) | SCI_SR(27)
93
69eee8e9
GU		 94#define min_sr(_port) ffs((_port)->sampling_rate_mask)
95#define max_sr(_port) fls((_port)->sampling_rate_mask)
96
97/* Iterate over all supported sampling rates, from high to low */
98#define for_each_sr(_sr, _port) \
99 for ((_sr) = max_sr(_port); (_sr) >= min_sr(_port); (_sr)--) \
100 if ((_port)->sampling_rate_mask & SCI_SR((_sr)))
101
e095ee6b
LP		 102struct plat_sci_reg {
103 u8 offset, size;
104};
105
106struct sci_port_params {
107 const struct plat_sci_reg regs[SCIx_NR_REGS];
b2f20ed9
LP		 108 unsigned int fifosize;
109 unsigned int overrun_reg;
110 unsigned int overrun_mask;
111 unsigned int sampling_rate_mask;
112 unsigned int error_mask;
113 unsigned int error_clear;
e095ee6b
LP		 114};
115
e108b2ca
PM		 116struct sci_port {
117 struct uart_port port;
118
ce6738b6 119 /* Platform configuration */
e095ee6b 120 const struct sci_port_params *params;
daf5a895 121 const struct plat_sci_port *cfg;
69eee8e9 122 unsigned int sampling_rate_mask;
e4d6f911 123 resource_size_t reg_size;
f907c9ea 124 struct mctrl_gpios *gpios;
e108b2ca 125
f4998e55
GU		 126 /* Clocks */
127 struct clk *clks[SCI_NUM_CLKS];
128 unsigned long clk_rates[SCI_NUM_CLKS];
edad1f20 129
1fcc91a6 130 int irqs[SCIx_NR_IRQS];
9174fc8f
PM		 131 char *irqstr[SCIx_NR_IRQS];
132
73a19e4c
GL		 133 struct dma_chan *chan_tx;
134 struct dma_chan *chan_rx;
f43dc23d 135
73a19e4c 136#ifdef CONFIG_SERIAL_SH_SCI_DMA
73a19e4c
GL		 137 dma_cookie_t cookie_tx;
138 dma_cookie_t cookie_rx[2];
139 dma_cookie_t active_rx;
79904420
GU		 140 dma_addr_t tx_dma_addr;
141 unsigned int tx_dma_len;
73a19e4c 142 struct scatterlist sg_rx[2];
7b39d901 143 void *rx_buf[2];
73a19e4c 144 size_t buf_len_rx;
73a19e4c 145 struct work_struct work_tx;
73a19e4c 146 struct timer_list rx_timer;
3089f381 147 unsigned int rx_timeout;
73a19e4c 148#endif
03940376 149 unsigned int rx_frame;
18e8cf15 150 int rx_trigger;
03940376
UH		 151 struct timer_list rx_fifo_timer;
152 int rx_fifo_timeout;
fa2abb03 153 u16 hscif_tot;
33f50ffc 154
97ed9790 155 bool has_rtscts;
33f50ffc 156 bool autorts;
e108b2ca
PM		 157};
158
e108b2ca 159#define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
b7a76e4b 160
e108b2ca
PM		 161static struct sci_port sci_ports[SCI_NPORTS];
162static struct uart_driver sci_uart_driver;
1da177e4 163
e7c98dc7
MT		 164static inline struct sci_port *
165to_sci_port(struct uart_port *uart)
166{
167 return container_of(uart, struct sci_port, port);
168}
169
e095ee6b 170static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = {
61a6976b
PM		 171 /*
172 * Common SCI definitions, dependent on the port's regshift
173 * value.
174 */
175 [SCIx_SCI_REGTYPE] = {
e095ee6b
LP		 176 .regs = {
177 [SCSMR] = { 0x00, 8 },
178 [SCBRR] = { 0x01, 8 },
179 [SCSCR] = { 0x02, 8 },
180 [SCxTDR] = { 0x03, 8 },
181 [SCxSR] = { 0x04, 8 },
182 [SCxRDR] = { 0x05, 8 },
183 },
b2f20ed9
LP		 184 .fifosize = 1,
185 .overrun_reg = SCxSR,
186 .overrun_mask = SCI_ORER,
187 .sampling_rate_mask = SCI_SR(32),
188 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER,
189 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER,
61a6976b
PM		 190 },
191
192 /*
a752ba18 193 * Common definitions for legacy IrDA ports.
61a6976b
PM		 194 */
195 [SCIx_IRDA_REGTYPE] = {
e095ee6b
LP		 196 .regs = {
197 [SCSMR] = { 0x00, 8 },
198 [SCBRR] = { 0x02, 8 },
199 [SCSCR] = { 0x04, 8 },
200 [SCxTDR] = { 0x06, 8 },
201 [SCxSR] = { 0x08, 16 },
202 [SCxRDR] = { 0x0a, 8 },
203 [SCFCR] = { 0x0c, 8 },
204 [SCFDR] = { 0x0e, 16 },
205 },
b2f20ed9
LP		 206 .fifosize = 1,
207 .overrun_reg = SCxSR,
208 .overrun_mask = SCI_ORER,
209 .sampling_rate_mask = SCI_SR(32),
210 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER,
211 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER,
61a6976b
PM		 212 },
213
214 /*
215 * Common SCIFA definitions.
216 */
217 [SCIx_SCIFA_REGTYPE] = {
e095ee6b
LP		 218 .regs = {
219 [SCSMR] = { 0x00, 16 },
220 [SCBRR] = { 0x04, 8 },
221 [SCSCR] = { 0x08, 16 },
222 [SCxTDR] = { 0x20, 8 },
223 [SCxSR] = { 0x14, 16 },
224 [SCxRDR] = { 0x24, 8 },
225 [SCFCR] = { 0x18, 16 },
226 [SCFDR] = { 0x1c, 16 },
227 [SCPCR] = { 0x30, 16 },
228 [SCPDR] = { 0x34, 16 },
229 },
b2f20ed9
LP		 230 .fifosize = 64,
231 .overrun_reg = SCxSR,
232 .overrun_mask = SCIFA_ORER,
233 .sampling_rate_mask = SCI_SR_SCIFAB,
234 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
235 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
61a6976b
PM		 236 },
237
238 /*
239 * Common SCIFB definitions.
240 */
241 [SCIx_SCIFB_REGTYPE] = {
e095ee6b
LP		 242 .regs = {
243 [SCSMR] = { 0x00, 16 },
244 [SCBRR] = { 0x04, 8 },
245 [SCSCR] = { 0x08, 16 },
246 [SCxTDR] = { 0x40, 8 },
247 [SCxSR] = { 0x14, 16 },
248 [SCxRDR] = { 0x60, 8 },
249 [SCFCR] = { 0x18, 16 },
250 [SCTFDR] = { 0x38, 16 },
251 [SCRFDR] = { 0x3c, 16 },
252 [SCPCR] = { 0x30, 16 },
253 [SCPDR] = { 0x34, 16 },
254 },
b2f20ed9
LP		 255 .fifosize = 256,
256 .overrun_reg = SCxSR,
257 .overrun_mask = SCIFA_ORER,
258 .sampling_rate_mask = SCI_SR_SCIFAB,
259 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
260 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
61a6976b
PM		 261 },
262
3af1f8a4
PE		 263 /*
264 * Common SH-2(A) SCIF definitions for ports with FIFO data
265 * count registers.
266 */
267 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = {
e095ee6b
LP		 268 .regs = {
269 [SCSMR] = { 0x00, 16 },
270 [SCBRR] = { 0x04, 8 },
271 [SCSCR] = { 0x08, 16 },
272 [SCxTDR] = { 0x0c, 8 },
273 [SCxSR] = { 0x10, 16 },
274 [SCxRDR] = { 0x14, 8 },
275 [SCFCR] = { 0x18, 16 },
276 [SCFDR] = { 0x1c, 16 },
277 [SCSPTR] = { 0x20, 16 },
278 [SCLSR] = { 0x24, 16 },
279 },
b2f20ed9
LP		 280 .fifosize = 16,
281 .overrun_reg = SCLSR,
282 .overrun_mask = SCLSR_ORER,
283 .sampling_rate_mask = SCI_SR(32),
284 .error_mask = SCIF_DEFAULT_ERROR_MASK,
285 .error_clear = SCIF_ERROR_CLEAR,
3af1f8a4
PE		 286 },
287
61a6976b
PM		 288 /*
289 * Common SH-3 SCIF definitions.
290 */
291 [SCIx_SH3_SCIF_REGTYPE] = {
e095ee6b
LP		 292 .regs = {
293 [SCSMR] = { 0x00, 8 },
294 [SCBRR] = { 0x02, 8 },
295 [SCSCR] = { 0x04, 8 },
296 [SCxTDR] = { 0x06, 8 },
297 [SCxSR] = { 0x08, 16 },
298 [SCxRDR] = { 0x0a, 8 },
299 [SCFCR] = { 0x0c, 8 },
300 [SCFDR] = { 0x0e, 16 },
301 },
b2f20ed9
LP		 302 .fifosize = 16,
303 .overrun_reg = SCLSR,
304 .overrun_mask = SCLSR_ORER,
305 .sampling_rate_mask = SCI_SR(32),
306 .error_mask = SCIF_DEFAULT_ERROR_MASK,
307 .error_clear = SCIF_ERROR_CLEAR,
61a6976b
PM		 308 },
309
310 /*
311 * Common SH-4(A) SCIF(B) definitions.
312 */
313 [SCIx_SH4_SCIF_REGTYPE] = {
e095ee6b
LP		 314 .regs = {
315 [SCSMR] = { 0x00, 16 },
316 [SCBRR] = { 0x04, 8 },
317 [SCSCR] = { 0x08, 16 },
318 [SCxTDR] = { 0x0c, 8 },
319 [SCxSR] = { 0x10, 16 },
320 [SCxRDR] = { 0x14, 8 },
321 [SCFCR] = { 0x18, 16 },
322 [SCFDR] = { 0x1c, 16 },
323 [SCSPTR] = { 0x20, 16 },
324 [SCLSR] = { 0x24, 16 },
325 },
b2f20ed9
LP		 326 .fifosize = 16,
327 .overrun_reg = SCLSR,
328 .overrun_mask = SCLSR_ORER,
329 .sampling_rate_mask = SCI_SR(32),
330 .error_mask = SCIF_DEFAULT_ERROR_MASK,
331 .error_clear = SCIF_ERROR_CLEAR,
b8bbd6b2
GU		 332 },
333
334 /*
335 * Common SCIF definitions for ports with a Baud Rate Generator for
336 * External Clock (BRG).
337 */
338 [SCIx_SH4_SCIF_BRG_REGTYPE] = {
e095ee6b
LP		 339 .regs = {
340 [SCSMR] = { 0x00, 16 },
341 [SCBRR] = { 0x04, 8 },
342 [SCSCR] = { 0x08, 16 },
343 [SCxTDR] = { 0x0c, 8 },
344 [SCxSR] = { 0x10, 16 },
345 [SCxRDR] = { 0x14, 8 },
346 [SCFCR] = { 0x18, 16 },
347 [SCFDR] = { 0x1c, 16 },
348 [SCSPTR] = { 0x20, 16 },
349 [SCLSR] = { 0x24, 16 },
350 [SCDL] = { 0x30, 16 },
351 [SCCKS] = { 0x34, 16 },
352 },
b2f20ed9
LP		 353 .fifosize = 16,
354 .overrun_reg = SCLSR,
355 .overrun_mask = SCLSR_ORER,
356 .sampling_rate_mask = SCI_SR(32),
357 .error_mask = SCIF_DEFAULT_ERROR_MASK,
358 .error_clear = SCIF_ERROR_CLEAR,
f303b364
UH		 359 },
360
361 /*
362 * Common HSCIF definitions.
363 */
364 [SCIx_HSCIF_REGTYPE] = {
e095ee6b
LP		 365 .regs = {
366 [SCSMR] = { 0x00, 16 },
367 [SCBRR] = { 0x04, 8 },
368 [SCSCR] = { 0x08, 16 },
369 [SCxTDR] = { 0x0c, 8 },
370 [SCxSR] = { 0x10, 16 },
371 [SCxRDR] = { 0x14, 8 },
372 [SCFCR] = { 0x18, 16 },
373 [SCFDR] = { 0x1c, 16 },
374 [SCSPTR] = { 0x20, 16 },
375 [SCLSR] = { 0x24, 16 },
376 [HSSRR] = { 0x40, 16 },
377 [SCDL] = { 0x30, 16 },
378 [SCCKS] = { 0x34, 16 },
54e14ae2
UH		 379 [HSRTRGR] = { 0x54, 16 },
380 [HSTTRGR] = { 0x58, 16 },
e095ee6b 381 },
b2f20ed9
LP		 382 .fifosize = 128,
383 .overrun_reg = SCLSR,
384 .overrun_mask = SCLSR_ORER,
385 .sampling_rate_mask = SCI_SR_RANGE(8, 32),
386 .error_mask = SCIF_DEFAULT_ERROR_MASK,
387 .error_clear = SCIF_ERROR_CLEAR,
61a6976b
PM		 388 },
389
390 /*
391 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR
392 * register.
393 */
394 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = {
e095ee6b
LP		 395 .regs = {
396 [SCSMR] = { 0x00, 16 },
397 [SCBRR] = { 0x04, 8 },
398 [SCSCR] = { 0x08, 16 },
399 [SCxTDR] = { 0x0c, 8 },
400 [SCxSR] = { 0x10, 16 },
401 [SCxRDR] = { 0x14, 8 },
402 [SCFCR] = { 0x18, 16 },
403 [SCFDR] = { 0x1c, 16 },
404 [SCLSR] = { 0x24, 16 },
405 },
b2f20ed9
LP		 406 .fifosize = 16,
407 .overrun_reg = SCLSR,
408 .overrun_mask = SCLSR_ORER,
409 .sampling_rate_mask = SCI_SR(32),
410 .error_mask = SCIF_DEFAULT_ERROR_MASK,
411 .error_clear = SCIF_ERROR_CLEAR,
61a6976b
PM		 412 },
413
414 /*
415 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data
416 * count registers.
417 */
418 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = {
e095ee6b
LP		 419 .regs = {
420 [SCSMR] = { 0x00, 16 },
421 [SCBRR] = { 0x04, 8 },
422 [SCSCR] = { 0x08, 16 },
423 [SCxTDR] = { 0x0c, 8 },
424 [SCxSR] = { 0x10, 16 },
425 [SCxRDR] = { 0x14, 8 },
426 [SCFCR] = { 0x18, 16 },
427 [SCFDR] = { 0x1c, 16 },
428 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */
429 [SCRFDR] = { 0x20, 16 },
430 [SCSPTR] = { 0x24, 16 },
431 [SCLSR] = { 0x28, 16 },
432 },
b2f20ed9
LP		 433 .fifosize = 16,
434 .overrun_reg = SCLSR,
435 .overrun_mask = SCLSR_ORER,
436 .sampling_rate_mask = SCI_SR(32),
437 .error_mask = SCIF_DEFAULT_ERROR_MASK,
438 .error_clear = SCIF_ERROR_CLEAR,
61a6976b
PM		 439 },
440
441 /*
442 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR
443 * registers.
444 */
445 [SCIx_SH7705_SCIF_REGTYPE] = {
e095ee6b
LP		 446 .regs = {
447 [SCSMR] = { 0x00, 16 },
448 [SCBRR] = { 0x04, 8 },
449 [SCSCR] = { 0x08, 16 },
450 [SCxTDR] = { 0x20, 8 },
451 [SCxSR] = { 0x14, 16 },
452 [SCxRDR] = { 0x24, 8 },
453 [SCFCR] = { 0x18, 16 },
454 [SCFDR] = { 0x1c, 16 },
455 },
18e8cf15 456 .fifosize = 64,
b2f20ed9
LP		 457 .overrun_reg = SCxSR,
458 .overrun_mask = SCIFA_ORER,
459 .sampling_rate_mask = SCI_SR(16),
460 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
461 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
61a6976b
PM		 462 },
463};
464
e095ee6b 465#define sci_getreg(up, offset) (&to_sci_port(up)->params->regs[offset])
72b294cf 466
61a6976b
PM		 467/*
468 * The "offset" here is rather misleading, in that it refers to an enum
469 * value relative to the port mapping rather than the fixed offset
470 * itself, which needs to be manually retrieved from the platform's
471 * register map for the given port.
472 */
473static unsigned int sci_serial_in(struct uart_port *p, int offset)
474{
d3184e68 475 const struct plat_sci_reg *reg = sci_getreg(p, offset);
61a6976b
PM		 476
477 if (reg->size == 8)
478 return ioread8(p->membase + (reg->offset << p->regshift));
479 else if (reg->size == 16)
480 return ioread16(p->membase + (reg->offset << p->regshift));
481 else
482 WARN(1, "Invalid register access\n");
483
484 return 0;
485}
486
487static void sci_serial_out(struct uart_port *p, int offset, int value)
488{
d3184e68 489 const struct plat_sci_reg *reg = sci_getreg(p, offset);
61a6976b
PM		 490
491 if (reg->size == 8)
492 iowrite8(value, p->membase + (reg->offset << p->regshift));
493 else if (reg->size == 16)
494 iowrite16(value, p->membase + (reg->offset << p->regshift));
495 else
496 WARN(1, "Invalid register access\n");
497}
498
23241d43
PM		 499static void sci_port_enable(struct sci_port *sci_port)
500{
f4998e55
GU		 501 unsigned int i;
502
23241d43
PM		 503 if (!sci_port->port.dev)
504 return;
505
506 pm_runtime_get_sync(sci_port->port.dev);
507
f4998e55
GU		 508 for (i = 0; i < SCI_NUM_CLKS; i++) {
509 clk_prepare_enable(sci_port->clks[i]);
510 sci_port->clk_rates[i] = clk_get_rate(sci_port->clks[i]);
511 }
512 sci_port->port.uartclk = sci_port->clk_rates[SCI_FCK];
23241d43
PM		 513}
514
515static void sci_port_disable(struct sci_port *sci_port)
516{
f4998e55
GU		 517 unsigned int i;
518
23241d43
PM		 519 if (!sci_port->port.dev)
520 return;
521
f4998e55
GU		 522 for (i = SCI_NUM_CLKS; i-- > 0; )
523 clk_disable_unprepare(sci_port->clks[i]);
23241d43
PM		 524
525 pm_runtime_put_sync(sci_port->port.dev);
526}
527
e1910fcd
GU		 528static inline unsigned long port_rx_irq_mask(struct uart_port *port)
529{
530 /*
531 * Not all ports (such as SCIFA) will support REIE. Rather than
532 * special-casing the port type, we check the port initialization
533 * IRQ enable mask to see whether the IRQ is desired at all. If
534 * it's unset, it's logically inferred that there's no point in
535 * testing for it.
536 */
537 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE);
538}
539
540static void sci_start_tx(struct uart_port *port)
541{
542 struct sci_port *s = to_sci_port(port);
543 unsigned short ctrl;
544
545#ifdef CONFIG_SERIAL_SH_SCI_DMA
546 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
547 u16 new, scr = serial_port_in(port, SCSCR);
548 if (s->chan_tx)
549 new = scr | SCSCR_TDRQE;
550 else
551 new = scr & ~SCSCR_TDRQE;
552 if (new != scr)
553 serial_port_out(port, SCSCR, new);
554 }
555
556 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) &&
557 dma_submit_error(s->cookie_tx)) {
558 s->cookie_tx = 0;
559 schedule_work(&s->work_tx);
560 }
561#endif
562
563 if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
564 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
565 ctrl = serial_port_in(port, SCSCR);
566 serial_port_out(port, SCSCR, ctrl | SCSCR_TIE);
567 }
568}
569
570static void sci_stop_tx(struct uart_port *port)
571{
572 unsigned short ctrl;
573
574 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
575 ctrl = serial_port_in(port, SCSCR);
576
577 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
578 ctrl &= ~SCSCR_TDRQE;
579
580 ctrl &= ~SCSCR_TIE;
581
582 serial_port_out(port, SCSCR, ctrl);
583}
584
585static void sci_start_rx(struct uart_port *port)
586{
587 unsigned short ctrl;
588
589 ctrl = serial_port_in(port, SCSCR) | port_rx_irq_mask(port);
590
591 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
592 ctrl &= ~SCSCR_RDRQE;
593
594 serial_port_out(port, SCSCR, ctrl);
595}
596
597static void sci_stop_rx(struct uart_port *port)
598{
599 unsigned short ctrl;
600
601 ctrl = serial_port_in(port, SCSCR);
602
603 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
604 ctrl &= ~SCSCR_RDRQE;
605
606 ctrl &= ~port_rx_irq_mask(port);
607
608 serial_port_out(port, SCSCR, ctrl);
609}
610
a1b5b43f
GU		 611static void sci_clear_SCxSR(struct uart_port *port, unsigned int mask)
612{
613 if (port->type == PORT_SCI) {
614 /* Just store the mask */
615 serial_port_out(port, SCxSR, mask);
b2f20ed9 616 } else if (to_sci_port(port)->params->overrun_mask == SCIFA_ORER) {
a1b5b43f
GU		 617 /* SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721 */
618 /* Only clear the status bits we want to clear */
619 serial_port_out(port, SCxSR,
620 serial_port_in(port, SCxSR) & mask);
621 } else {
622 /* Store the mask, clear parity/framing errors */
623 serial_port_out(port, SCxSR, mask & ~(SCIF_FERC | SCIF_PERC));
624 }
625}
626
0b0cced1
YS		 627#if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \
628 defined(CONFIG_SERIAL_SH_SCI_EARLYCON)
1f6fd5c9
PM		 629
630#ifdef CONFIG_CONSOLE_POLL
07d2a1a1 631static int sci_poll_get_char(struct uart_port *port)
1da177e4 632{
1da177e4
LT		 633 unsigned short status;
634 int c;
635
e108b2ca 636 do {
b12bb29f 637 status = serial_port_in(port, SCxSR);
1da177e4 638 if (status & SCxSR_ERRORS(port)) {
a1b5b43f 639 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
1da177e4
LT		 640 continue;
641 }
3f255eb3
JW		 642 break;
643 } while (1);
644
645 if (!(status & SCxSR_RDxF(port)))
646 return NO_POLL_CHAR;
07d2a1a1 647
b12bb29f 648 c = serial_port_in(port, SCxRDR);
07d2a1a1 649
e7c98dc7 650 /* Dummy read */
b12bb29f 651 serial_port_in(port, SCxSR);
a1b5b43f 652 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1da177e4
LT		 653
654 return c;
655}
1f6fd5c9 656#endif
1da177e4 657
07d2a1a1 658static void sci_poll_put_char(struct uart_port *port, unsigned char c)
1da177e4 659{
1da177e4
LT		 660 unsigned short status;
661
1da177e4 662 do {
b12bb29f 663 status = serial_port_in(port, SCxSR);
1da177e4
LT		 664 } while (!(status & SCxSR_TDxE(port)));
665
b12bb29f 666 serial_port_out(port, SCxTDR, c);
a1b5b43f 667 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
1da177e4 668}
0b0cced1
YS		 669#endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE ||
670 CONFIG_SERIAL_SH_SCI_EARLYCON */
1da177e4 671
61a6976b 672static void sci_init_pins(struct uart_port *port, unsigned int cflag)
1da177e4 673{
61a6976b 674 struct sci_port *s = to_sci_port(port);
1da177e4 675
61a6976b
PM		 676 /*
677 * Use port-specific handler if provided.
678 */
679 if (s->cfg->ops && s->cfg->ops->init_pins) {
680 s->cfg->ops->init_pins(port, cflag);
681 return;
1da177e4 682 }
41504c39 683
e9d7a45a 684 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
cfa6eb23 685 u16 data = serial_port_in(port, SCPDR);
e9d7a45a
GU		 686 u16 ctrl = serial_port_in(port, SCPCR);
687
688 /* Enable RXD and TXD pin functions */
689 ctrl &= ~(SCPCR_RXDC | SCPCR_TXDC);
97ed9790 690 if (to_sci_port(port)->has_rtscts) {
cfa6eb23
GU		 691 /* RTS# is output, active low, unless autorts */
692 if (!(port->mctrl & TIOCM_RTS)) {
693 ctrl |= SCPCR_RTSC;
694 data |= SCPDR_RTSD;
695 } else if (!s->autorts) {
696 ctrl |= SCPCR_RTSC;
697 data &= ~SCPDR_RTSD;
698 } else {
699 /* Enable RTS# pin function */
700 ctrl &= ~SCPCR_RTSC;
701 }
e9d7a45a
GU		 702 /* Enable CTS# pin function */
703 ctrl &= ~SCPCR_CTSC;
704 }
cfa6eb23 705 serial_port_out(port, SCPDR, data);
e9d7a45a
GU		 706 serial_port_out(port, SCPCR, ctrl);
707 } else if (sci_getreg(port, SCSPTR)->size) {
d2b9775d
GU		 708 u16 status = serial_port_in(port, SCSPTR);
709
cfa6eb23
GU		 710 /* RTS# is always output; and active low, unless autorts */
711 status |= SCSPTR_RTSIO;
712 if (!(port->mctrl & TIOCM_RTS))
713 status |= SCSPTR_RTSDT;
714 else if (!s->autorts)
715 status &= ~SCSPTR_RTSDT;
d2b9775d
GU		 716 /* CTS# and SCK are inputs */
717 status &= ~(SCSPTR_CTSIO | SCSPTR_SCKIO);
718 serial_port_out(port, SCSPTR, status);
faf02f8f 719 }
d5701647 720}
e108b2ca 721
72b294cf 722static int sci_txfill(struct uart_port *port)
e108b2ca 723{
b2f20ed9
LP		 724 struct sci_port *s = to_sci_port(port);
725 unsigned int fifo_mask = (s->params->fifosize << 1) - 1;
d3184e68 726 const struct plat_sci_reg *reg;
e108b2ca 727
72b294cf
PM		 728 reg = sci_getreg(port, SCTFDR);
729 if (reg->size)
b2f20ed9 730 return serial_port_in(port, SCTFDR) & fifo_mask;
c63847a3 731
72b294cf
PM		 732 reg = sci_getreg(port, SCFDR);
733 if (reg->size)
b12bb29f 734 return serial_port_in(port, SCFDR) >> 8;
d1d4b10c 735
b12bb29f 736 return !(serial_port_in(port, SCxSR) & SCI_TDRE);
e108b2ca
PM		 737}
738
73a19e4c
GL		 739static int sci_txroom(struct uart_port *port)
740{
72b294cf 741 return port->fifosize - sci_txfill(port);
73a19e4c
GL		 742}
743
744static int sci_rxfill(struct uart_port *port)
e108b2ca 745{
b2f20ed9
LP		 746 struct sci_port *s = to_sci_port(port);
747 unsigned int fifo_mask = (s->params->fifosize << 1) - 1;
d3184e68 748 const struct plat_sci_reg *reg;
72b294cf
PM		 749
750 reg = sci_getreg(port, SCRFDR);
751 if (reg->size)
b2f20ed9 752 return serial_port_in(port, SCRFDR) & fifo_mask;
72b294cf
PM		 753
754 reg = sci_getreg(port, SCFDR);
755 if (reg->size)
b2f20ed9 756 return serial_port_in(port, SCFDR) & fifo_mask;
72b294cf 757
b12bb29f 758 return (serial_port_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
e108b2ca
PM		 759}
760
1da177e4
LT		 761/* ********************************************************************** *
762 * the interrupt related routines *
763 * ********************************************************************** */
764
765static void sci_transmit_chars(struct uart_port *port)
766{
ebd2c8f6 767 struct circ_buf *xmit = &port->state->xmit;
1da177e4 768 unsigned int stopped = uart_tx_stopped(port);
1da177e4
LT		 769 unsigned short status;
770 unsigned short ctrl;
e108b2ca 771 int count;
1da177e4 772
b12bb29f 773 status = serial_port_in(port, SCxSR);
1da177e4 774 if (!(status & SCxSR_TDxE(port))) {
b12bb29f 775 ctrl = serial_port_in(port, SCSCR);
e7c98dc7 776 if (uart_circ_empty(xmit))
8e698614 777 ctrl &= ~SCSCR_TIE;
e7c98dc7 778 else
8e698614 779 ctrl |= SCSCR_TIE;
b12bb29f 780 serial_port_out(port, SCSCR, ctrl);
1da177e4
LT		 781 return;
782 }
783
72b294cf 784 count = sci_txroom(port);
1da177e4
LT		 785
786 do {
787 unsigned char c;
788
789 if (port->x_char) {
790 c = port->x_char;
791 port->x_char = 0;
792 } else if (!uart_circ_empty(xmit) && !stopped) {
793 c = xmit->buf[xmit->tail];
794 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
795 } else {
796 break;
797 }
798
b12bb29f 799 serial_port_out(port, SCxTDR, c);
1da177e4
LT		 800
801 port->icount.tx++;
802 } while (--count > 0);
803
a1b5b43f 804 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
1da177e4
LT		 805
806 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
807 uart_write_wakeup(port);
808 if (uart_circ_empty(xmit)) {
b129a8cc 809 sci_stop_tx(port);
1da177e4 810 } else {
b12bb29f 811 ctrl = serial_port_in(port, SCSCR);
1da177e4 812
1a22f08d 813 if (port->type != PORT_SCI) {
b12bb29f 814 serial_port_in(port, SCxSR); /* Dummy read */
a1b5b43f 815 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
1da177e4 816 }
1da177e4 817
8e698614 818 ctrl |= SCSCR_TIE;
b12bb29f 819 serial_port_out(port, SCSCR, ctrl);
1da177e4
LT		 820 }
821}
822
823/* On SH3, SCIF may read end-of-break as a space->mark char */
e7c98dc7 824#define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); })
1da177e4 825
94c8b6db 826static void sci_receive_chars(struct uart_port *port)
1da177e4 827{
227434f8 828 struct tty_port *tport = &port->state->port;
1da177e4
LT		 829 int i, count, copied = 0;
830 unsigned short status;
33f0f88f 831 unsigned char flag;
1da177e4 832
b12bb29f 833 status = serial_port_in(port, SCxSR);
1da177e4
LT		 834 if (!(status & SCxSR_RDxF(port)))
835 return;
836
837 while (1) {
1da177e4 838 /* Don't copy more bytes than there is room for in the buffer */
227434f8 839 count = tty_buffer_request_room(tport, sci_rxfill(port));
1da177e4
LT		 840
841 /* If for any reason we can't copy more data, we're done! */
842 if (count == 0)
843 break;
844
845 if (port->type == PORT_SCI) {
b12bb29f 846 char c = serial_port_in(port, SCxRDR);
d5cb1319 847 if (uart_handle_sysrq_char(port, c))
1da177e4 848 count = 0;
e7c98dc7 849 else
92a19f9c 850 tty_insert_flip_char(tport, c, TTY_NORMAL);
1da177e4 851 } else {
e7c98dc7 852 for (i = 0; i < count; i++) {
b12bb29f 853 char c = serial_port_in(port, SCxRDR);
d97fbbed 854
b12bb29f 855 status = serial_port_in(port, SCxSR);
7d12e780 856 if (uart_handle_sysrq_char(port, c)) {
1da177e4
LT		 857 count--; i--;
858 continue;
859 }
860
861 /* Store data and status */
73a19e4c 862 if (status & SCxSR_FER(port)) {
33f0f88f 863 flag = TTY_FRAME;
d97fbbed 864 port->icount.frame++;
762c69e3 865 dev_notice(port->dev, "frame error\n");
73a19e4c 866 } else if (status & SCxSR_PER(port)) {
33f0f88f 867 flag = TTY_PARITY;
d97fbbed 868 port->icount.parity++;
762c69e3 869 dev_notice(port->dev, "parity error\n");
33f0f88f
AC		 870 } else
871 flag = TTY_NORMAL;
762c69e3 872
92a19f9c 873 tty_insert_flip_char(tport, c, flag);
1da177e4
LT		 874 }
875 }
876
b12bb29f 877 serial_port_in(port, SCxSR); /* dummy read */
a1b5b43f 878 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1da177e4 879
1da177e4
LT		 880 copied += count;
881 port->icount.rx += count;
882 }
883
884 if (copied) {
885 /* Tell the rest of the system the news. New characters! */
2e124b4a 886 tty_flip_buffer_push(tport);
1da177e4 887 } else {
b12bb29f 888 serial_port_in(port, SCxSR); /* dummy read */
a1b5b43f 889 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1da177e4
LT		 890 }
891}
892
94c8b6db 893static int sci_handle_errors(struct uart_port *port)
1da177e4
LT		 894{
895 int copied = 0;
b12bb29f 896 unsigned short status = serial_port_in(port, SCxSR);
92a19f9c 897 struct tty_port *tport = &port->state->port;
debf9507 898 struct sci_port *s = to_sci_port(port);
1da177e4 899
3ae988d9 900 /* Handle overruns */
b2f20ed9 901 if (status & s->params->overrun_mask) {
3ae988d9 902 port->icount.overrun++;
d97fbbed 903
3ae988d9
LP		 904 /* overrun error */
905 if (tty_insert_flip_char(tport, 0, TTY_OVERRUN))
906 copied++;
762c69e3 907
9b971cd2 908 dev_notice(port->dev, "overrun error\n");
1da177e4
LT		 909 }
910
e108b2ca 911 if (status & SCxSR_FER(port)) {
d5cb1319
LP		 912 /* frame error */
913 port->icount.frame++;
d97fbbed 914
d5cb1319
LP		 915 if (tty_insert_flip_char(tport, 0, TTY_FRAME))
916 copied++;
762c69e3 917
d5cb1319 918 dev_notice(port->dev, "frame error\n");
1da177e4
LT		 919 }
920
e108b2ca 921 if (status & SCxSR_PER(port)) {
1da177e4 922 /* parity error */
d97fbbed
PM		 923 port->icount.parity++;
924
92a19f9c 925 if (tty_insert_flip_char(tport, 0, TTY_PARITY))
e108b2ca 926 copied++;
762c69e3 927
9b971cd2 928 dev_notice(port->dev, "parity error\n");
1da177e4
LT		 929 }
930
33f0f88f 931 if (copied)
2e124b4a 932 tty_flip_buffer_push(tport);
1da177e4
LT		 933
934 return copied;
935}
936
94c8b6db 937static int sci_handle_fifo_overrun(struct uart_port *port)
d830fa45 938{
92a19f9c 939 struct tty_port *tport = &port->state->port;
debf9507 940 struct sci_port *s = to_sci_port(port);
d3184e68 941 const struct plat_sci_reg *reg;
2e0842a1 942 int copied = 0;
75c249fd 943 u16 status;
d830fa45 944
b2f20ed9 945 reg = sci_getreg(port, s->params->overrun_reg);
4b8c59a3 946 if (!reg->size)
d830fa45
PM		 947 return 0;
948
b2f20ed9
LP		 949 status = serial_port_in(port, s->params->overrun_reg);
950 if (status & s->params->overrun_mask) {
951 status &= ~s->params->overrun_mask;
952 serial_port_out(port, s->params->overrun_reg, status);
d830fa45 953
d97fbbed
PM		 954 port->icount.overrun++;
955
92a19f9c 956 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
2e124b4a 957 tty_flip_buffer_push(tport);
d830fa45 958
51b31f1c 959 dev_dbg(port->dev, "overrun error\n");
d830fa45
PM		 960 copied++;
961 }
962
963 return copied;
964}
965
94c8b6db 966static int sci_handle_breaks(struct uart_port *port)
1da177e4
LT		 967{
968 int copied = 0;
b12bb29f 969 unsigned short status = serial_port_in(port, SCxSR);
92a19f9c 970 struct tty_port *tport = &port->state->port;
1da177e4 971
0b3d4ef6
PM		 972 if (uart_handle_break(port))
973 return 0;
974
d5cb1319 975 if (status & SCxSR_BRK(port)) {
d97fbbed
PM		 976 port->icount.brk++;
977
1da177e4 978 /* Notify of BREAK */
92a19f9c 979 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
33f0f88f 980 copied++;
762c69e3
PM		 981
982 dev_dbg(port->dev, "BREAK detected\n");
1da177e4
LT		 983 }
984
33f0f88f 985 if (copied)
2e124b4a 986 tty_flip_buffer_push(tport);
e108b2ca 987
d830fa45
PM		 988 copied += sci_handle_fifo_overrun(port);
989
1da177e4
LT		 990 return copied;
991}
992
a380ed46
UH		 993static int scif_set_rtrg(struct uart_port *port, int rx_trig)
994{
995 unsigned int bits;
996
997 if (rx_trig < 1)
998 rx_trig = 1;
999 if (rx_trig >= port->fifosize)
1000 rx_trig = port->fifosize;
1001
1002 /* HSCIF can be set to an arbitrary level. */
1003 if (sci_getreg(port, HSRTRGR)->size) {
1004 serial_port_out(port, HSRTRGR, rx_trig);
1005 return rx_trig;
1006 }
1007
1008 switch (port->type) {
1009 case PORT_SCIF:
1010 if (rx_trig < 4) {
1011 bits = 0;
1012 rx_trig = 1;
1013 } else if (rx_trig < 8) {
1014 bits = SCFCR_RTRG0;
1015 rx_trig = 4;
1016 } else if (rx_trig < 14) {
1017 bits = SCFCR_RTRG1;
1018 rx_trig = 8;
1019 } else {
1020 bits = SCFCR_RTRG0 | SCFCR_RTRG1;
1021 rx_trig = 14;
1022 }
1023 break;
1024 case PORT_SCIFA:
1025 case PORT_SCIFB:
1026 if (rx_trig < 16) {
1027 bits = 0;
1028 rx_trig = 1;
1029 } else if (rx_trig < 32) {
1030 bits = SCFCR_RTRG0;
1031 rx_trig = 16;
1032 } else if (rx_trig < 48) {
1033 bits = SCFCR_RTRG1;
1034 rx_trig = 32;
1035 } else {
1036 bits = SCFCR_RTRG0 | SCFCR_RTRG1;
1037 rx_trig = 48;
1038 }
1039 break;
1040 default:
1041 WARN(1, "unknown FIFO configuration");
1042 return 1;
1043 }
1044
1045 serial_port_out(port, SCFCR,
1046 (serial_port_in(port, SCFCR) &
1047 ~(SCFCR_RTRG1 | SCFCR_RTRG0)) | bits);
1048
1049 return rx_trig;
1050}
1051
03940376
UH		 1052static int scif_rtrg_enabled(struct uart_port *port)
1053{
1054 if (sci_getreg(port, HSRTRGR)->size)
1055 return serial_port_in(port, HSRTRGR) != 0;
1056 else
1057 return (serial_port_in(port, SCFCR) &
1058 (SCFCR_RTRG0 | SCFCR_RTRG1)) != 0;
1059}
1060
1061static void rx_fifo_timer_fn(unsigned long arg)
1062{
1063 struct sci_port *s = (struct sci_port *)arg;
1064 struct uart_port *port = &s->port;
1065
1066 dev_dbg(port->dev, "Rx timed out\n");
1067 scif_set_rtrg(port, 1);
1068}
1069
5d23188a
UH		 1070static ssize_t rx_trigger_show(struct device *dev,
1071 struct device_attribute *attr,
1072 char *buf)
1073{
1074 struct uart_port *port = dev_get_drvdata(dev);
1075 struct sci_port *sci = to_sci_port(port);
1076
1077 return sprintf(buf, "%d\n", sci->rx_trigger);
1078}
1079
1080static ssize_t rx_trigger_store(struct device *dev,
1081 struct device_attribute *attr,
1082 const char *buf,
1083 size_t count)
1084{
1085 struct uart_port *port = dev_get_drvdata(dev);
1086 struct sci_port *sci = to_sci_port(port);
4ab3c51e 1087 int ret;
5d23188a
UH		 1088 long r;
1089
4ab3c51e
DC		 1090 ret = kstrtol(buf, 0, &r);
1091 if (ret)
1092 return ret;
90afa525 1093
5d23188a 1094 sci->rx_trigger = scif_set_rtrg(port, r);
90afa525
UH		 1095 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1096 scif_set_rtrg(port, 1);
1097
5d23188a
UH		 1098 return count;
1099}
1100
1101static DEVICE_ATTR(rx_fifo_trigger, 0644, rx_trigger_show, rx_trigger_store);
1102
1103static ssize_t rx_fifo_timeout_show(struct device *dev,
1104 struct device_attribute *attr,
1105 char *buf)
1106{
1107 struct uart_port *port = dev_get_drvdata(dev);
1108 struct sci_port *sci = to_sci_port(port);
fa2abb03 1109 int v;
5d23188a 1110
fa2abb03
UH		 1111 if (port->type == PORT_HSCIF)
1112 v = sci->hscif_tot >> HSSCR_TOT_SHIFT;
1113 else
1114 v = sci->rx_fifo_timeout;
1115
1116 return sprintf(buf, "%d\n", v);
5d23188a
UH		 1117}
1118
1119static ssize_t rx_fifo_timeout_store(struct device *dev,
1120 struct device_attribute *attr,
1121 const char *buf,
1122 size_t count)
1123{
1124 struct uart_port *port = dev_get_drvdata(dev);
1125 struct sci_port *sci = to_sci_port(port);
4ab3c51e 1126 int ret;
5d23188a
UH		 1127 long r;
1128
4ab3c51e
DC		 1129 ret = kstrtol(buf, 0, &r);
1130 if (ret)
1131 return ret;
fa2abb03
UH		 1132
1133 if (port->type == PORT_HSCIF) {
1134 if (r < 0 || r > 3)
1135 return -EINVAL;
1136 sci->hscif_tot = r << HSSCR_TOT_SHIFT;
1137 } else {
1138 sci->rx_fifo_timeout = r;
1139 scif_set_rtrg(port, 1);
1140 if (r > 0)
1141 setup_timer(&sci->rx_fifo_timer, rx_fifo_timer_fn,
1142 (unsigned long)sci);
1143 }
1144
5d23188a
UH		 1145 return count;
1146}
1147
1148static DEVICE_ATTR(rx_fifo_timeout, 0644, rx_fifo_timeout_show, rx_fifo_timeout_store);
1149
1150
73a19e4c 1151#ifdef CONFIG_SERIAL_SH_SCI_DMA
e1910fcd
GU		 1152static void sci_dma_tx_complete(void *arg)
1153{
1154 struct sci_port *s = arg;
1155 struct uart_port *port = &s->port;
1156 struct circ_buf *xmit = &port->state->xmit;
1157 unsigned long flags;
73a19e4c 1158
e1910fcd 1159 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
73a19e4c 1160
e1910fcd 1161 spin_lock_irqsave(&port->lock, flags);
73a19e4c 1162
e1910fcd
GU		 1163 xmit->tail += s->tx_dma_len;
1164 xmit->tail &= UART_XMIT_SIZE - 1;
73a19e4c 1165
e1910fcd 1166 port->icount.tx += s->tx_dma_len;
1da177e4 1167
e1910fcd
GU		 1168 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1169 uart_write_wakeup(port);
1da177e4 1170
e1910fcd
GU		 1171 if (!uart_circ_empty(xmit)) {
1172 s->cookie_tx = 0;
1173 schedule_work(&s->work_tx);
1174 } else {
1175 s->cookie_tx = -EINVAL;
1176 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1177 u16 ctrl = serial_port_in(port, SCSCR);
1178 serial_port_out(port, SCSCR, ctrl & ~SCSCR_TIE);
1179 }
1180 }
1da177e4 1181
fd78a76a 1182 spin_unlock_irqrestore(&port->lock, flags);
1da177e4
LT		 1183}
1184
e1910fcd
GU		 1185/* Locking: called with port lock held */
1186static int sci_dma_rx_push(struct sci_port *s, void *buf, size_t count)
1da177e4 1187{
e1910fcd
GU		 1188 struct uart_port *port = &s->port;
1189 struct tty_port *tport = &port->state->port;
1190 int copied;
1da177e4 1191
e1910fcd 1192 copied = tty_insert_flip_string(tport, buf, count);
6fc5a520 1193 if (copied < count)
e1910fcd 1194 port->icount.buf_overrun++;
1da177e4 1195
e1910fcd 1196 port->icount.rx += copied;
1da177e4 1197
e1910fcd 1198 return copied;
1da177e4
LT		 1199}
1200
e1910fcd 1201static int sci_dma_rx_find_active(struct sci_port *s)
1da177e4 1202{
e1910fcd 1203 unsigned int i;
1da177e4 1204
e1910fcd
GU		 1205 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++)
1206 if (s->active_rx == s->cookie_rx[i])
1207 return i;
1da177e4 1208
e1910fcd 1209 return -1;
1da177e4
LT		 1210}
1211
e1910fcd 1212static void sci_rx_dma_release(struct sci_port *s, bool enable_pio)
f43dc23d 1213{
e1910fcd
GU		 1214 struct dma_chan *chan = s->chan_rx;
1215 struct uart_port *port = &s->port;
1216 unsigned long flags;
1217
1218 spin_lock_irqsave(&port->lock, flags);
1219 s->chan_rx = NULL;
1220 s->cookie_rx[0] = s->cookie_rx[1] = -EINVAL;
1221 spin_unlock_irqrestore(&port->lock, flags);
1222 dmaengine_terminate_all(chan);
1223 dma_free_coherent(chan->device->dev, s->buf_len_rx * 2, s->rx_buf[0],
1224 sg_dma_address(&s->sg_rx[0]));
1225 dma_release_channel(chan);
1be22663
TA		 1226 if (enable_pio) {
1227 spin_lock_irqsave(&port->lock, flags);
e1910fcd 1228 sci_start_rx(port);
1be22663
TA		 1229 spin_unlock_irqrestore(&port->lock, flags);
1230 }
f43dc23d
PM		 1231}
1232
e1910fcd 1233static void sci_dma_rx_complete(void *arg)
1da177e4 1234{
e1910fcd 1235 struct sci_port *s = arg;
1d3db608 1236 struct dma_chan *chan = s->chan_rx;
e1910fcd 1237 struct uart_port *port = &s->port;
67f462b0 1238 struct dma_async_tx_descriptor *desc;
e1910fcd
GU		 1239 unsigned long flags;
1240 int active, count = 0;
1da177e4 1241
e1910fcd
GU		 1242 dev_dbg(port->dev, "%s(%d) active cookie %d\n", __func__, port->line,
1243 s->active_rx);
cb772fe7 1244
e1910fcd 1245 spin_lock_irqsave(&port->lock, flags);
1da177e4 1246
e1910fcd
GU		 1247 active = sci_dma_rx_find_active(s);
1248 if (active >= 0)
1249 count = sci_dma_rx_push(s, s->rx_buf[active], s->buf_len_rx);
f43dc23d 1250
e1910fcd 1251 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
f43dc23d 1252
e1910fcd
GU		 1253 if (count)
1254 tty_flip_buffer_push(&port->state->port);
8b6ff84c 1255
67f462b0
GU		 1256 desc = dmaengine_prep_slave_sg(s->chan_rx, &s->sg_rx[active], 1,
1257 DMA_DEV_TO_MEM,
1258 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1259 if (!desc)
1260 goto fail;
1261
1262 desc->callback = sci_dma_rx_complete;
1263 desc->callback_param = s;
1264 s->cookie_rx[active] = dmaengine_submit(desc);
1265 if (dma_submit_error(s->cookie_rx[active]))
1266 goto fail;
1267
1268 s->active_rx = s->cookie_rx[!active];
1269
1d3db608
MHF		 1270 dma_async_issue_pending(chan);
1271
6fc5a520 1272 spin_unlock_irqrestore(&port->lock, flags);
67f462b0
GU		 1273 dev_dbg(port->dev, "%s: cookie %d #%d, new active cookie %d\n",
1274 __func__, s->cookie_rx[active], active, s->active_rx);
67f462b0
GU		 1275 return;
1276
1277fail:
1278 spin_unlock_irqrestore(&port->lock, flags);
1279 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
1280 sci_rx_dma_release(s, true);
1da177e4
LT		 1281}
1282
e1910fcd 1283static void sci_tx_dma_release(struct sci_port *s, bool enable_pio)
1da177e4 1284{
e1910fcd
GU		 1285 struct dma_chan *chan = s->chan_tx;
1286 struct uart_port *port = &s->port;
e552de24 1287 unsigned long flags;
1da177e4 1288
e1910fcd
GU		 1289 spin_lock_irqsave(&port->lock, flags);
1290 s->chan_tx = NULL;
1291 s->cookie_tx = -EINVAL;
1292 spin_unlock_irqrestore(&port->lock, flags);
1293 dmaengine_terminate_all(chan);
1294 dma_unmap_single(chan->device->dev, s->tx_dma_addr, UART_XMIT_SIZE,
1295 DMA_TO_DEVICE);
1296 dma_release_channel(chan);
1be22663
TA		 1297 if (enable_pio) {
1298 spin_lock_irqsave(&port->lock, flags);
e1910fcd 1299 sci_start_tx(port);
1be22663
TA		 1300 spin_unlock_irqrestore(&port->lock, flags);
1301 }
e1910fcd 1302}
d535a230 1303
e1910fcd
GU		 1304static void sci_submit_rx(struct sci_port *s)
1305{
1306 struct dma_chan *chan = s->chan_rx;
1307 int i;
073e84c9 1308
e1910fcd
GU		 1309 for (i = 0; i < 2; i++) {
1310 struct scatterlist *sg = &s->sg_rx[i];
1311 struct dma_async_tx_descriptor *desc;
1da177e4 1312
e1910fcd
GU		 1313 desc = dmaengine_prep_slave_sg(chan,
1314 sg, 1, DMA_DEV_TO_MEM,
1315 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1316 if (!desc)
1317 goto fail;
501b825d 1318
e1910fcd
GU		 1319 desc->callback = sci_dma_rx_complete;
1320 desc->callback_param = s;
1321 s->cookie_rx[i] = dmaengine_submit(desc);
1322 if (dma_submit_error(s->cookie_rx[i]))
1323 goto fail;
9174fc8f 1324
e1910fcd 1325 }
9174fc8f 1326
e1910fcd 1327 s->active_rx = s->cookie_rx[0];
9174fc8f 1328
e1910fcd
GU		 1329 dma_async_issue_pending(chan);
1330 return;
9174fc8f 1331
e1910fcd
GU		 1332fail:
1333 if (i)
1334 dmaengine_terminate_all(chan);
1335 for (i = 0; i < 2; i++)
1336 s->cookie_rx[i] = -EINVAL;
1337 s->active_rx = -EINVAL;
e1910fcd
GU		 1338 sci_rx_dma_release(s, true);
1339}
9174fc8f 1340
e1910fcd 1341static void work_fn_tx(struct work_struct *work)
1da177e4 1342{
e1910fcd
GU		 1343 struct sci_port *s = container_of(work, struct sci_port, work_tx);
1344 struct dma_async_tx_descriptor *desc;
1345 struct dma_chan *chan = s->chan_tx;
1346 struct uart_port *port = &s->port;
1347 struct circ_buf *xmit = &port->state->xmit;
1348 dma_addr_t buf;
1da177e4 1349
9174fc8f 1350 /*
e1910fcd
GU		 1351 * DMA is idle now.
1352 * Port xmit buffer is already mapped, and it is one page... Just adjust
1353 * offsets and lengths. Since it is a circular buffer, we have to
1354 * transmit till the end, and then the rest. Take the port lock to get a
1355 * consistent xmit buffer state.
9174fc8f 1356 */
e1910fcd
GU		 1357 spin_lock_irq(&port->lock);
1358 buf = s->tx_dma_addr + (xmit->tail & (UART_XMIT_SIZE - 1));
1359 s->tx_dma_len = min_t(unsigned int,
1360 CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE),
1361 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE));
1362 spin_unlock_irq(&port->lock);
0e8963de 1363
e1910fcd
GU		 1364 desc = dmaengine_prep_slave_single(chan, buf, s->tx_dma_len,
1365 DMA_MEM_TO_DEV,
1366 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1367 if (!desc) {
1368 dev_warn(port->dev, "Failed preparing Tx DMA descriptor\n");
1369 /* switch to PIO */
1370 sci_tx_dma_release(s, true);
1371 return;
1372 }
0e8963de 1373
e1910fcd
GU		 1374 dma_sync_single_for_device(chan->device->dev, buf, s->tx_dma_len,
1375 DMA_TO_DEVICE);
1da177e4 1376
e1910fcd
GU		 1377 spin_lock_irq(&port->lock);
1378 desc->callback = sci_dma_tx_complete;
1379 desc->callback_param = s;
1380 spin_unlock_irq(&port->lock);
1381 s->cookie_tx = dmaengine_submit(desc);
1382 if (dma_submit_error(s->cookie_tx)) {
1383 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
1384 /* switch to PIO */
1385 sci_tx_dma_release(s, true);
1386 return;
1da177e4 1387 }
1da177e4 1388
e1910fcd
GU		 1389 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n",
1390 __func__, xmit->buf, xmit->tail, xmit->head, s->cookie_tx);
73a19e4c 1391
e1910fcd 1392 dma_async_issue_pending(chan);
1da177e4
LT		 1393}
1394
e1910fcd 1395static void rx_timer_fn(unsigned long arg)
1da177e4 1396{
e1910fcd 1397 struct sci_port *s = (struct sci_port *)arg;
e7327c09 1398 struct dma_chan *chan = s->chan_rx;
e1910fcd 1399 struct uart_port *port = &s->port;
67f462b0
GU		 1400 struct dma_tx_state state;
1401 enum dma_status status;
1402 unsigned long flags;
1403 unsigned int read;
1404 int active, count;
1405 u16 scr;
1406
67f462b0 1407 dev_dbg(port->dev, "DMA Rx timed out\n");
67f462b0 1408
6fc5a520
TA		 1409 spin_lock_irqsave(&port->lock, flags);
1410
67f462b0
GU		 1411 active = sci_dma_rx_find_active(s);
1412 if (active < 0) {
1413 spin_unlock_irqrestore(&port->lock, flags);
1414 return;
1415 }
1416
1417 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
3b963042 1418 if (status == DMA_COMPLETE) {
6fc5a520 1419 spin_unlock_irqrestore(&port->lock, flags);
67f462b0
GU		 1420 dev_dbg(port->dev, "Cookie %d #%d has already completed\n",
1421 s->active_rx, active);
3b963042
MHF		 1422
1423 /* Let packet complete handler take care of the packet */
1424 return;
1425 }
67f462b0 1426
e7327c09
MHF		 1427 dmaengine_pause(chan);
1428
1429 /*
1430 * sometimes DMA transfer doesn't stop even if it is stopped and
1431 * data keeps on coming until transaction is complete so check
1432 * for DMA_COMPLETE again
1433 * Let packet complete handler take care of the packet
1434 */
1435 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
1436 if (status == DMA_COMPLETE) {
1437 spin_unlock_irqrestore(&port->lock, flags);
1438 dev_dbg(port->dev, "Transaction complete after DMA engine was stopped");
1439 return;
1440 }
1441
67f462b0
GU		 1442 /* Handle incomplete DMA receive */
1443 dmaengine_terminate_all(s->chan_rx);
1444 read = sg_dma_len(&s->sg_rx[active]) - state.residue;
67f462b0
GU		 1445
1446 if (read) {
1447 count = sci_dma_rx_push(s, s->rx_buf[active], read);
1448 if (count)
1449 tty_flip_buffer_push(&port->state->port);
1450 }
1451
756981be
GU		 1452 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1453 sci_submit_rx(s);
371cfed3
MHF		 1454
1455 /* Direct new serial port interrupts back to CPU */
1456 scr = serial_port_in(port, SCSCR);
1457 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1458 scr &= ~SCSCR_RDRQE;
1459 enable_irq(s->irqs[SCIx_RXI_IRQ]);
1460 }
1461 serial_port_out(port, SCSCR, scr | SCSCR_RIE);
1462
1463 spin_unlock_irqrestore(&port->lock, flags);
1da177e4
LT		 1464}
1465
ff441129 1466static struct dma_chan *sci_request_dma_chan(struct uart_port *port,
219fb0c1 1467 enum dma_transfer_direction dir)
ff441129 1468{
ff441129
GU		 1469 struct dma_chan *chan;
1470 struct dma_slave_config cfg;
1471 int ret;
1472
219fb0c1
LP		 1473 chan = dma_request_slave_channel(port->dev,
1474 dir == DMA_MEM_TO_DEV ? "tx" : "rx");
ff441129 1475 if (!chan) {
9b7becf1 1476 dev_warn(port->dev, "dma_request_slave_channel failed\n");
ff441129
GU		 1477 return NULL;
1478 }
1479
1480 memset(&cfg, 0, sizeof(cfg));
1481 cfg.direction = dir;
1482 if (dir == DMA_MEM_TO_DEV) {
1483 cfg.dst_addr = port->mapbase +
1484 (sci_getreg(port, SCxTDR)->offset << port->regshift);
1485 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1486 } else {
1487 cfg.src_addr = port->mapbase +
1488 (sci_getreg(port, SCxRDR)->offset << port->regshift);
1489 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1490 }
1491
1492 ret = dmaengine_slave_config(chan, &cfg);
1493 if (ret) {
1494 dev_warn(port->dev, "dmaengine_slave_config failed %d\n", ret);
1495 dma_release_channel(chan);
1496 return NULL;
1497 }
1498
1499 return chan;
1500}
1501
e1910fcd 1502static void sci_request_dma(struct uart_port *port)
73a19e4c 1503{
e1910fcd 1504 struct sci_port *s = to_sci_port(port);
e1910fcd 1505 struct dma_chan *chan;
73a19e4c 1506
e1910fcd 1507 dev_dbg(port->dev, "%s: port %d\n", __func__, port->line);
73a19e4c 1508
219fb0c1 1509 if (!port->dev->of_node)
e1910fcd 1510 return;
73a19e4c 1511
e1910fcd 1512 s->cookie_tx = -EINVAL;
7464779f
AL		 1513
1514 /*
1515 * Don't request a dma channel if no channel was specified
1516 * in the device tree.
1517 */
1518 if (!of_find_property(port->dev->of_node, "dmas", NULL))
1519 return;
1520
219fb0c1 1521 chan = sci_request_dma_chan(port, DMA_MEM_TO_DEV);
e1910fcd
GU		 1522 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
1523 if (chan) {
1524 s->chan_tx = chan;
1525 /* UART circular tx buffer is an aligned page. */
1526 s->tx_dma_addr = dma_map_single(chan->device->dev,
1527 port->state->xmit.buf,
1528 UART_XMIT_SIZE,
1529 DMA_TO_DEVICE);
1530 if (dma_mapping_error(chan->device->dev, s->tx_dma_addr)) {
1531 dev_warn(port->dev, "Failed mapping Tx DMA descriptor\n");
1532 dma_release_channel(chan);
1533 s->chan_tx = NULL;
1534 } else {
1535 dev_dbg(port->dev, "%s: mapped %lu@%p to %pad\n",
1536 __func__, UART_XMIT_SIZE,
1537 port->state->xmit.buf, &s->tx_dma_addr);
49d4bcad 1538 }
e1910fcd
GU		 1539
1540 INIT_WORK(&s->work_tx, work_fn_tx);
3089f381
GL		 1541 }
1542
219fb0c1 1543 chan = sci_request_dma_chan(port, DMA_DEV_TO_MEM);
e1910fcd
GU		 1544 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan);
1545 if (chan) {
1546 unsigned int i;
1547 dma_addr_t dma;
1548 void *buf;
73a19e4c 1549
e1910fcd 1550 s->chan_rx = chan;
73a19e4c 1551
e1910fcd
GU		 1552 s->buf_len_rx = 2 * max_t(size_t, 16, port->fifosize);
1553 buf = dma_alloc_coherent(chan->device->dev, s->buf_len_rx * 2,
1554 &dma, GFP_KERNEL);
1555 if (!buf) {
1556 dev_warn(port->dev,
1557 "Failed to allocate Rx dma buffer, using PIO\n");
1558 dma_release_channel(chan);
1559 s->chan_rx = NULL;
e1910fcd
GU		 1560 return;
1561 }
73a19e4c 1562
e1910fcd
GU		 1563 for (i = 0; i < 2; i++) {
1564 struct scatterlist *sg = &s->sg_rx[i];
0533502d 1565
e1910fcd
GU		 1566 sg_init_table(sg, 1);
1567 s->rx_buf[i] = buf;
1568 sg_dma_address(sg) = dma;
d09959e7 1569 sg_dma_len(sg) = s->buf_len_rx;
0533502d 1570
e1910fcd
GU		 1571 buf += s->buf_len_rx;
1572 dma += s->buf_len_rx;
1573 }
1574
e1910fcd
GU		 1575 setup_timer(&s->rx_timer, rx_timer_fn, (unsigned long)s);
1576
756981be
GU		 1577 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1578 sci_submit_rx(s);
e1910fcd 1579 }
0533502d
GU		 1580}
1581
e1910fcd 1582static void sci_free_dma(struct uart_port *port)
73a19e4c 1583{
e1910fcd 1584 struct sci_port *s = to_sci_port(port);
73a19e4c 1585
e1910fcd
GU		 1586 if (s->chan_tx)
1587 sci_tx_dma_release(s, false);
1588 if (s->chan_rx)
1589 sci_rx_dma_release(s, false);
1590}
1cf4a7ef
GU		 1591
1592static void sci_flush_buffer(struct uart_port *port)
1593{
1594 /*
1595 * In uart_flush_buffer(), the xmit circular buffer has just been
1596 * cleared, so we have to reset tx_dma_len accordingly.
1597 */
1598 to_sci_port(port)->tx_dma_len = 0;
1599}
1600#else /* !CONFIG_SERIAL_SH_SCI_DMA */
e1910fcd
GU		 1601static inline void sci_request_dma(struct uart_port *port)
1602{
1603}
73a19e4c 1604
e1910fcd
GU		 1605static inline void sci_free_dma(struct uart_port *port)
1606{
1607}
1cf4a7ef
GU		 1608
1609#define sci_flush_buffer NULL
1610#endif /* !CONFIG_SERIAL_SH_SCI_DMA */
73a19e4c 1611
e1910fcd
GU		 1612static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
1613{
e1910fcd
GU		 1614 struct uart_port *port = ptr;
1615 struct sci_port *s = to_sci_port(port);
73a19e4c 1616
03940376 1617#ifdef CONFIG_SERIAL_SH_SCI_DMA
e1910fcd
GU		 1618 if (s->chan_rx) {
1619 u16 scr = serial_port_in(port, SCSCR);
1620 u16 ssr = serial_port_in(port, SCxSR);
73a19e4c 1621
e1910fcd
GU		 1622 /* Disable future Rx interrupts */
1623 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1624 disable_irq_nosync(irq);
1625 scr |= SCSCR_RDRQE;
1626 } else {
1627 scr &= ~SCSCR_RIE;
756981be 1628 sci_submit_rx(s);
e1910fcd
GU		 1629 }
1630 serial_port_out(port, SCSCR, scr);
1631 /* Clear current interrupt */
1632 serial_port_out(port, SCxSR,
1633 ssr & ~(SCIF_DR | SCxSR_RDxF(port)));
1634 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u jiffies\n",
1635 jiffies, s->rx_timeout);
1636 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
73a19e4c 1637
e1910fcd
GU		 1638 return IRQ_HANDLED;
1639 }
1640#endif
73a19e4c 1641
03940376
UH		 1642 if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0) {
1643 if (!scif_rtrg_enabled(port))
1644 scif_set_rtrg(port, s->rx_trigger);
1645
1646 mod_timer(&s->rx_fifo_timer, jiffies + DIV_ROUND_UP(
1647 s->rx_frame * s->rx_fifo_timeout, 1000));
1648 }
1649
e1910fcd
GU		 1650 /* I think sci_receive_chars has to be called irrespective
1651 * of whether the I_IXOFF is set, otherwise, how is the interrupt
1652 * to be disabled?
1653 */
1654 sci_receive_chars(ptr);
1655
1656 return IRQ_HANDLED;
73a19e4c
GL		 1657}
1658
e1910fcd 1659static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
73a19e4c 1660{
e1910fcd 1661 struct uart_port *port = ptr;
04928b79 1662 unsigned long flags;
73a19e4c 1663
04928b79 1664 spin_lock_irqsave(&port->lock, flags);
e1910fcd 1665 sci_transmit_chars(port);
04928b79 1666 spin_unlock_irqrestore(&port->lock, flags);
e1910fcd
GU		 1667
1668 return IRQ_HANDLED;
73a19e4c
GL		 1669}
1670
e1910fcd 1671static irqreturn_t sci_er_interrupt(int irq, void *ptr)
73a19e4c 1672{
e1910fcd
GU		 1673 struct uart_port *port = ptr;
1674 struct sci_port *s = to_sci_port(port);
73a19e4c 1675
e1910fcd
GU		 1676 /* Handle errors */
1677 if (port->type == PORT_SCI) {
1678 if (sci_handle_errors(port)) {
1679 /* discard character in rx buffer */
1680 serial_port_in(port, SCxSR);
1681 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1682 }
1683 } else {
1684 sci_handle_fifo_overrun(port);
1685 if (!s->chan_rx)
1686 sci_receive_chars(ptr);
1687 }
1688
1689 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
1690
1691 /* Kick the transmission */
1692 if (!s->chan_tx)
1693 sci_tx_interrupt(irq, ptr);
1694
1695 return IRQ_HANDLED;
73a19e4c
GL		 1696}
1697
e1910fcd 1698static irqreturn_t sci_br_interrupt(int irq, void *ptr)
73a19e4c 1699{
e1910fcd 1700 struct uart_port *port = ptr;
73a19e4c 1701
e1910fcd
GU		 1702 /* Handle BREAKs */
1703 sci_handle_breaks(port);
1704 sci_clear_SCxSR(port, SCxSR_BREAK_CLEAR(port));
73a19e4c 1705
e1910fcd
GU		 1706 return IRQ_HANDLED;
1707}
73a19e4c 1708
e1910fcd
GU		 1709static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
1710{
1711 unsigned short ssr_status, scr_status, err_enabled, orer_status = 0;
1712 struct uart_port *port = ptr;
1713 struct sci_port *s = to_sci_port(port);
1714 irqreturn_t ret = IRQ_NONE;
73a19e4c 1715
e1910fcd
GU		 1716 ssr_status = serial_port_in(port, SCxSR);
1717 scr_status = serial_port_in(port, SCSCR);
b2f20ed9 1718 if (s->params->overrun_reg == SCxSR)
e1910fcd 1719 orer_status = ssr_status;
b2f20ed9
LP		 1720 else if (sci_getreg(port, s->params->overrun_reg)->size)
1721 orer_status = serial_port_in(port, s->params->overrun_reg);
73a19e4c 1722
e1910fcd 1723 err_enabled = scr_status & port_rx_irq_mask(port);
73a19e4c 1724
e1910fcd
GU		 1725 /* Tx Interrupt */
1726 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) &&
1727 !s->chan_tx)
1728 ret = sci_tx_interrupt(irq, ptr);
658daa95 1729
e1910fcd
GU		 1730 /*
1731 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF /
1732 * DR flags
1733 */
1734 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&
1735 (scr_status & SCSCR_RIE))
1736 ret = sci_rx_interrupt(irq, ptr);
73a19e4c 1737
e1910fcd
GU		 1738 /* Error Interrupt */
1739 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
1740 ret = sci_er_interrupt(irq, ptr);
73a19e4c 1741
e1910fcd
GU		 1742 /* Break Interrupt */
1743 if ((ssr_status & SCxSR_BRK(port)) && err_enabled)
1744 ret = sci_br_interrupt(irq, ptr);
1745
1746 /* Overrun Interrupt */
b2f20ed9 1747 if (orer_status & s->params->overrun_mask) {
e1910fcd
GU		 1748 sci_handle_fifo_overrun(port);
1749 ret = IRQ_HANDLED;
73a19e4c 1750 }
73a19e4c 1751
e1910fcd
GU		 1752 return ret;
1753}
73a19e4c 1754
e1910fcd
GU		 1755static const struct sci_irq_desc {
1756 const char *desc;
1757 irq_handler_t handler;
1758} sci_irq_desc[] = {
1759 /*
1760 * Split out handlers, the default case.
1761 */
1762 [SCIx_ERI_IRQ] = {
1763 .desc = "rx err",
1764 .handler = sci_er_interrupt,
1765 },
3089f381 1766
e1910fcd
GU		 1767 [SCIx_RXI_IRQ] = {
1768 .desc = "rx full",
1769 .handler = sci_rx_interrupt,
1770 },
47aceb92 1771
e1910fcd
GU		 1772 [SCIx_TXI_IRQ] = {
1773 .desc = "tx empty",
1774 .handler = sci_tx_interrupt,
1775 },
73a19e4c 1776
e1910fcd
GU		 1777 [SCIx_BRI_IRQ] = {
1778 .desc = "break",
1779 .handler = sci_br_interrupt,
1780 },
73a19e4c
GL		 1781
1782 /*
e1910fcd 1783 * Special muxed handler.
73a19e4c 1784 */
e1910fcd
GU		 1785 [SCIx_MUX_IRQ] = {
1786 .desc = "mux",
1787 .handler = sci_mpxed_interrupt,
1788 },
1789};
73a19e4c 1790
e1910fcd
GU		 1791static int sci_request_irq(struct sci_port *port)
1792{
1793 struct uart_port *up = &port->port;
1794 int i, j, ret = 0;
73a19e4c 1795
e1910fcd
GU		 1796 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) {
1797 const struct sci_irq_desc *desc;
1798 int irq;
73a19e4c 1799
e1910fcd
GU		 1800 if (SCIx_IRQ_IS_MUXED(port)) {
1801 i = SCIx_MUX_IRQ;
1802 irq = up->irq;
1803 } else {
1804 irq = port->irqs[i];
1805
1806 /*
1807 * Certain port types won't support all of the
1808 * available interrupt sources.
1809 */
1810 if (unlikely(irq < 0))
1811 continue;
1812 }
1813
1814 desc = sci_irq_desc + i;
1815 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s",
1816 dev_name(up->dev), desc->desc);
623ac1d4
PB		 1817 if (!port->irqstr[j]) {
1818 ret = -ENOMEM;
e1910fcd 1819 goto out_nomem;
623ac1d4 1820 }
e1910fcd
GU		 1821
1822 ret = request_irq(irq, desc->handler, up->irqflags,
1823 port->irqstr[j], port);
1824 if (unlikely(ret)) {
1825 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc);
1826 goto out_noirq;
1827 }
73a19e4c
GL		 1828 }
1829
e1910fcd 1830 return 0;
1da177e4 1831
e1910fcd
GU		 1832out_noirq:
1833 while (--i >= 0)
1834 free_irq(port->irqs[i], port);
f43dc23d 1835
e1910fcd
GU		 1836out_nomem:
1837 while (--j >= 0)
1838 kfree(port->irqstr[j]);
f43dc23d 1839
e1910fcd 1840 return ret;
1da177e4
LT		 1841}
1842
e1910fcd 1843static void sci_free_irq(struct sci_port *port)
1da177e4 1844{
e1910fcd 1845 int i;
1da177e4 1846
e1910fcd
GU		 1847 /*
1848 * Intentionally in reverse order so we iterate over the muxed
1849 * IRQ first.
1850 */
1851 for (i = 0; i < SCIx_NR_IRQS; i++) {
1852 int irq = port->irqs[i];
f43dc23d 1853
e1910fcd
GU		 1854 /*
1855 * Certain port types won't support all of the available
1856 * interrupt sources.
1857 */
1858 if (unlikely(irq < 0))
1859 continue;
f43dc23d 1860
e1910fcd
GU		 1861 free_irq(port->irqs[i], port);
1862 kfree(port->irqstr[i]);
f43dc23d 1863
e1910fcd
GU		 1864 if (SCIx_IRQ_IS_MUXED(port)) {
1865 /* If there's only one IRQ, we're done. */
1866 return;
1867 }
1868 }
1da177e4
LT		 1869}
1870
e1910fcd 1871static unsigned int sci_tx_empty(struct uart_port *port)
1da177e4 1872{
e1910fcd
GU		 1873 unsigned short status = serial_port_in(port, SCxSR);
1874 unsigned short in_tx_fifo = sci_txfill(port);
f43dc23d 1875
e1910fcd 1876 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
1da177e4
LT		 1877}
1878
33f50ffc
GU		 1879static void sci_set_rts(struct uart_port *port, bool state)
1880{
1881 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1882 u16 data = serial_port_in(port, SCPDR);
1883
1884 /* Active low */
1885 if (state)
1886 data &= ~SCPDR_RTSD;
1887 else
1888 data |= SCPDR_RTSD;
1889 serial_port_out(port, SCPDR, data);
1890
1891 /* RTS# is output */
1892 serial_port_out(port, SCPCR,
1893 serial_port_in(port, SCPCR) | SCPCR_RTSC);
1894 } else if (sci_getreg(port, SCSPTR)->size) {
1895 u16 ctrl = serial_port_in(port, SCSPTR);
1896
1897 /* Active low */
1898 if (state)
1899 ctrl &= ~SCSPTR_RTSDT;
1900 else
1901 ctrl |= SCSPTR_RTSDT;
1902 serial_port_out(port, SCSPTR, ctrl);
1903 }
1904}
1905
1906static bool sci_get_cts(struct uart_port *port)
1907{
1908 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1909 /* Active low */
1910 return !(serial_port_in(port, SCPDR) & SCPDR_CTSD);
1911 } else if (sci_getreg(port, SCSPTR)->size) {
1912 /* Active low */
1913 return !(serial_port_in(port, SCSPTR) & SCSPTR_CTSDT);
1914 }
1915
1916 return true;
1917}
1918
e1910fcd
GU		 1919/*
1920 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally
1921 * CTS/RTS is supported in hardware by at least one port and controlled
1922 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently
1923 * handled via the ->init_pins() op, which is a bit of a one-way street,
1924 * lacking any ability to defer pin control -- this will later be
1925 * converted over to the GPIO framework).
1926 *
1927 * Other modes (such as loopback) are supported generically on certain
1928 * port types, but not others. For these it's sufficient to test for the
1929 * existence of the support register and simply ignore the port type.
1930 */
1931static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
1da177e4 1932{
f907c9ea
GU		 1933 struct sci_port *s = to_sci_port(port);
1934
e1910fcd
GU		 1935 if (mctrl & TIOCM_LOOP) {
1936 const struct plat_sci_reg *reg;
f43dc23d 1937
e1910fcd
GU		 1938 /*
1939 * Standard loopback mode for SCFCR ports.
1940 */
1941 reg = sci_getreg(port, SCFCR);
1942 if (reg->size)
1943 serial_port_out(port, SCFCR,
1944 serial_port_in(port, SCFCR) |
1945 SCFCR_LOOP);
1946 }
f907c9ea
GU		 1947
1948 mctrl_gpio_set(s->gpios, mctrl);
33f50ffc 1949
97ed9790 1950 if (!s->has_rtscts)
33f50ffc
GU		 1951 return;
1952
1953 if (!(mctrl & TIOCM_RTS)) {
1954 /* Disable Auto RTS */
1955 serial_port_out(port, SCFCR,
1956 serial_port_in(port, SCFCR) & ~SCFCR_MCE);
1957
1958 /* Clear RTS */
1959 sci_set_rts(port, 0);
1960 } else if (s->autorts) {
1961 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1962 /* Enable RTS# pin function */
1963 serial_port_out(port, SCPCR,
1964 serial_port_in(port, SCPCR) & ~SCPCR_RTSC);
1965 }
1966
1967 /* Enable Auto RTS */
1968 serial_port_out(port, SCFCR,
1969 serial_port_in(port, SCFCR) | SCFCR_MCE);
1970 } else {
1971 /* Set RTS */
1972 sci_set_rts(port, 1);
1973 }
e1910fcd 1974}
f43dc23d 1975
e1910fcd
GU		 1976static unsigned int sci_get_mctrl(struct uart_port *port)
1977{
f907c9ea
GU		 1978 struct sci_port *s = to_sci_port(port);
1979 struct mctrl_gpios *gpios = s->gpios;
1980 unsigned int mctrl = 0;
1981
1982 mctrl_gpio_get(gpios, &mctrl);
1983
e1910fcd
GU		 1984 /*
1985 * CTS/RTS is handled in hardware when supported, while nothing
33f50ffc 1986 * else is wired up.
e1910fcd 1987 */
33f50ffc
GU		 1988 if (s->autorts) {
1989 if (sci_get_cts(port))
1990 mctrl |= TIOCM_CTS;
1991 } else if (IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(gpios, UART_GPIO_CTS))) {
f907c9ea 1992 mctrl |= TIOCM_CTS;
33f50ffc 1993 }
f907c9ea
GU		 1994 if (IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(gpios, UART_GPIO_DSR)))
1995 mctrl |= TIOCM_DSR;
1996 if (IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(gpios, UART_GPIO_DCD)))
1997 mctrl |= TIOCM_CAR;
1998
1999 return mctrl;
2000}
2001
2002static void sci_enable_ms(struct uart_port *port)
2003{
2004 mctrl_gpio_enable_ms(to_sci_port(port)->gpios);
1da177e4
LT		 2005}
2006
1da177e4
LT		 2007static void sci_break_ctl(struct uart_port *port, int break_state)
2008{
bbb4ce50 2009 unsigned short scscr, scsptr;
1be22663 2010 unsigned long flags;
bbb4ce50 2011
a4e02f6d 2012 /* check wheter the port has SCSPTR */
abbf121f 2013 if (!sci_getreg(port, SCSPTR)->size) {
bbb4ce50
SY		 2014 /*
2015 * Not supported by hardware. Most parts couple break and rx
2016 * interrupts together, with break detection always enabled.
2017 */
a4e02f6d 2018 return;
bbb4ce50 2019 }
a4e02f6d 2020
1be22663 2021 spin_lock_irqsave(&port->lock, flags);
a4e02f6d
SY		 2022 scsptr = serial_port_in(port, SCSPTR);
2023 scscr = serial_port_in(port, SCSCR);
2024
2025 if (break_state == -1) {
2026 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT;
2027 scscr &= ~SCSCR_TE;
2028 } else {
2029 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO;
2030 scscr |= SCSCR_TE;
2031 }
2032
2033 serial_port_out(port, SCSPTR, scsptr);
2034 serial_port_out(port, SCSCR, scscr);
1be22663 2035 spin_unlock_irqrestore(&port->lock, flags);
1da177e4
LT		 2036}
2037
2038static int sci_startup(struct uart_port *port)
2039{
a5660ada 2040 struct sci_port *s = to_sci_port(port);
073e84c9 2041 int ret;
1da177e4 2042
73a19e4c
GL		 2043 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
2044
3c910176
TA		 2045 sci_request_dma(port);
2046
073e84c9 2047 ret = sci_request_irq(s);
3c910176
TA		 2048 if (unlikely(ret < 0)) {
2049 sci_free_dma(port);
073e84c9 2050 return ret;
3c910176 2051 }
073e84c9 2052
1da177e4
LT		 2053 return 0;
2054}
2055
2056static void sci_shutdown(struct uart_port *port)
2057{
a5660ada 2058 struct sci_port *s = to_sci_port(port);
33b48e16 2059 unsigned long flags;
5fd2b6ee 2060 u16 scr;
1da177e4 2061
73a19e4c
GL		 2062 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
2063
33f50ffc 2064 s->autorts = false;
f907c9ea
GU		 2065 mctrl_gpio_disable_ms(to_sci_port(port)->gpios);
2066
33b48e16 2067 spin_lock_irqsave(&port->lock, flags);
1da177e4 2068 sci_stop_rx(port);
b129a8cc 2069 sci_stop_tx(port);
fa2abb03
UH		 2070 /*
2071 * Stop RX and TX, disable related interrupts, keep clock source
2072 * and HSCIF TOT bits
2073 */
5fd2b6ee 2074 scr = serial_port_in(port, SCSCR);
fa2abb03
UH		 2075 serial_port_out(port, SCSCR, scr &
2076 (SCSCR_CKE1 | SCSCR_CKE0 | s->hscif_tot));
33b48e16 2077 spin_unlock_irqrestore(&port->lock, flags);
073e84c9 2078
9ab76556
AM		 2079#ifdef CONFIG_SERIAL_SH_SCI_DMA
2080 if (s->chan_rx) {
2081 dev_dbg(port->dev, "%s(%d) deleting rx_timer\n", __func__,
2082 port->line);
2083 del_timer_sync(&s->rx_timer);
2084 }
2085#endif
2086
1da177e4 2087 sci_free_irq(s);
3c910176 2088 sci_free_dma(port);
1da177e4
LT		 2089}
2090
6af27bf2
GU		 2091static int sci_sck_calc(struct sci_port *s, unsigned int bps,
2092 unsigned int *srr)
26c92f37 2093{
6af27bf2 2094 unsigned long freq = s->clk_rates[SCI_SCK];
6af27bf2 2095 int err, min_err = INT_MAX;
69eee8e9 2096 unsigned int sr;
6af27bf2 2097
7b5c0c08
GU		 2098 if (s->port.type != PORT_HSCIF)
2099 freq *= 2;
6af27bf2 2100
69eee8e9 2101 for_each_sr(sr, s) {
6af27bf2
GU		 2102 err = DIV_ROUND_CLOSEST(freq, sr) - bps;
2103 if (abs(err) >= abs(min_err))
2104 continue;
2105
2106 min_err = err;
2107 *srr = sr - 1;
ec09c5eb 2108
6af27bf2
GU		 2109 if (!err)
2110 break;
2111 }
e8183a6c 2112
6af27bf2
GU		 2113 dev_dbg(s->port.dev, "SCK: %u%+d bps using SR %u\n", bps, min_err,
2114 *srr + 1);
2115 return min_err;
26c92f37
PM		 2116}
2117
1270f865
GU		 2118static int sci_brg_calc(struct sci_port *s, unsigned int bps,
2119 unsigned long freq, unsigned int *dlr,
2120 unsigned int *srr)
730c4e78 2121{
1270f865 2122 int err, min_err = INT_MAX;
69eee8e9 2123 unsigned int sr, dl;
730c4e78 2124
7b5c0c08
GU		 2125 if (s->port.type != PORT_HSCIF)
2126 freq *= 2;
730c4e78 2127
69eee8e9 2128 for_each_sr(sr, s) {
1270f865
GU		 2129 dl = DIV_ROUND_CLOSEST(freq, sr * bps);
2130 dl = clamp(dl, 1U, 65535U);
2131
2132 err = DIV_ROUND_CLOSEST(freq, sr * dl) - bps;
2133 if (abs(err) >= abs(min_err))
2134 continue;
2135
2136 min_err = err;
2137 *dlr = dl;
2138 *srr = sr - 1;
2139
2140 if (!err)
2141 break;
2142 }
730c4e78 2143
1270f865
GU		 2144 dev_dbg(s->port.dev, "BRG: %u%+d bps using DL %u SR %u\n", bps,
2145 min_err, *dlr, *srr + 1);
2146 return min_err;
2147}
730c4e78 2148
b4a5c459 2149/* calculate sample rate, BRR, and clock select */
f4998e55
GU		 2150static int sci_scbrr_calc(struct sci_port *s, unsigned int bps,
2151 unsigned int *brr, unsigned int *srr,
2152 unsigned int *cks)
f303b364 2153{
f4998e55 2154 unsigned long freq = s->clk_rates[SCI_FCK];
69eee8e9 2155 unsigned int sr, br, prediv, scrate, c;
6c51332d 2156 int err, min_err = INT_MAX;
f303b364 2157
7b5c0c08
GU		 2158 if (s->port.type != PORT_HSCIF)
2159 freq *= 2;
b4a5c459 2160
6c51332d
GU		 2161 /*
2162 * Find the combination of sample rate and clock select with the
2163 * smallest deviation from the desired baud rate.
2164 * Prefer high sample rates to maximise the receive margin.
2165 *
2166 * M: Receive margin (%)
2167 * N: Ratio of bit rate to clock (N = sampling rate)
2168 * D: Clock duty (D = 0 to 1.0)
2169 * L: Frame length (L = 9 to 12)
2170 * F: Absolute value of clock frequency deviation
2171 *
2172 * M = |(0.5 - 1 / 2 * N) - ((L - 0.5) * F) -
2173 * (|D - 0.5| / N * (1 + F))|
2174 * NOTE: Usually, treat D for 0.5, F is 0 by this calculation.
2175 */
69eee8e9 2176 for_each_sr(sr, s) {
f303b364
UH		 2177 for (c = 0; c <= 3; c++) {
2178 /* integerized formulas from HSCIF documentation */
7b5c0c08 2179 prediv = sr * (1 << (2 * c + 1));
de01e6cd
GU		 2180
2181 /*
2182 * We need to calculate:
2183 *
2184 * br = freq / (prediv * bps) clamped to [1..256]
881a7489 2185 * err = freq / (br * prediv) - bps
730c4e78 2186 *
de01e6cd
GU		 2187 * Watch out for overflow when calculating the desired
2188 * sampling clock rate!
730c4e78 2189 */
de01e6cd
GU		 2190 if (bps > UINT_MAX / prediv)
2191 break;
2192
2193 scrate = prediv * bps;
2194 br = DIV_ROUND_CLOSEST(freq, scrate);
95a2703e 2195 br = clamp(br, 1U, 256U);
6c51332d 2196
881a7489 2197 err = DIV_ROUND_CLOSEST(freq, br * prediv) - bps;
6c51332d 2198 if (abs(err) >= abs(min_err))
730c4e78
NI		 2199 continue;
2200
6c51332d 2201 min_err = err;
95a2703e 2202 *brr = br - 1;
730c4e78
NI		 2203 *srr = sr - 1;
2204 *cks = c;
6c51332d
GU		 2205
2206 if (!err)
2207 goto found;
f303b364
UH		 2208 }
2209 }
2210
6c51332d 2211found:
881a7489
GU		 2212 dev_dbg(s->port.dev, "BRR: %u%+d bps using N %u SR %u cks %u\n", bps,
2213 min_err, *brr, *srr + 1, *cks);
f4998e55 2214 return min_err;
f303b364
UH		 2215}
2216
1ba76220
MD		 2217static void sci_reset(struct uart_port *port)
2218{
d3184e68 2219 const struct plat_sci_reg *reg;
1ba76220 2220 unsigned int status;
18e8cf15 2221 struct sci_port *s = to_sci_port(port);
1ba76220 2222
fa2abb03 2223 serial_port_out(port, SCSCR, s->hscif_tot); /* TE=0, RE=0, CKE1=0 */
1ba76220 2224
0979e0e6
PM		 2225 reg = sci_getreg(port, SCFCR);
2226 if (reg->size)
b12bb29f 2227 serial_port_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
2768cf42
GU		 2228
2229 sci_clear_SCxSR(port,
2230 SCxSR_RDxF_CLEAR(port) & SCxSR_ERROR_CLEAR(port) &
2231 SCxSR_BREAK_CLEAR(port));
fc2af334
GU		 2232 if (sci_getreg(port, SCLSR)->size) {
2233 status = serial_port_in(port, SCLSR);
2234 status &= ~(SCLSR_TO | SCLSR_ORER);
2235 serial_port_out(port, SCLSR, status);
2236 }
18e8cf15 2237
03940376
UH		 2238 if (s->rx_trigger > 1) {
2239 if (s->rx_fifo_timeout) {
2240 scif_set_rtrg(port, 1);
2241 setup_timer(&s->rx_fifo_timer, rx_fifo_timer_fn,
2242 (unsigned long)s);
2243 } else {
90afa525
UH		 2244 if (port->type == PORT_SCIFA ||
2245 port->type == PORT_SCIFB)
2246 scif_set_rtrg(port, 1);
2247 else
2248 scif_set_rtrg(port, s->rx_trigger);
03940376
UH		 2249 }
2250 }
1ba76220
MD		 2251}
2252
606d099c
AC		 2253static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
2254 struct ktermios *old)
1da177e4 2255{
03940376 2256 unsigned int baud, smr_val = SCSMR_ASYNC, scr_val = 0, i, bits;
1270f865
GU		 2257 unsigned int brr = 255, cks = 0, srr = 15, dl = 0, sccks = 0;
2258 unsigned int brr1 = 255, cks1 = 0, srr1 = 15, dl1 = 0;
00b9de9c 2259 struct sci_port *s = to_sci_port(port);
d3184e68 2260 const struct plat_sci_reg *reg;
f4998e55
GU		 2261 int min_err = INT_MAX, err;
2262 unsigned long max_freq = 0;
2263 int best_clk = -1;
1be22663 2264 unsigned long flags;
1da177e4 2265
730c4e78
NI		 2266 if ((termios->c_cflag & CSIZE) == CS7)
2267 smr_val |= SCSMR_CHR;
2268 if (termios->c_cflag & PARENB)
2269 smr_val |= SCSMR_PE;
2270 if (termios->c_cflag & PARODD)
2271 smr_val |= SCSMR_PE | SCSMR_ODD;
2272 if (termios->c_cflag & CSTOPB)
2273 smr_val |= SCSMR_STOP;
2274
154280fd
MD		 2275 /*
2276 * earlyprintk comes here early on with port->uartclk set to zero.
2277 * the clock framework is not up and running at this point so here
2278 * we assume that 115200 is the maximum baud rate. please note that
2279 * the baud rate is not programmed during earlyprintk - it is assumed
2280 * that the previous boot loader has enabled required clocks and
2281 * setup the baud rate generator hardware for us already.
2282 */
f4998e55
GU		 2283 if (!port->uartclk) {
2284 baud = uart_get_baud_rate(port, termios, old, 0, 115200);
2285 goto done;
2286 }
1da177e4 2287
f4998e55
GU		 2288 for (i = 0; i < SCI_NUM_CLKS; i++)
2289 max_freq = max(max_freq, s->clk_rates[i]);
2290
69eee8e9 2291 baud = uart_get_baud_rate(port, termios, old, 0, max_freq / min_sr(s));
f4998e55
GU		 2292 if (!baud)
2293 goto done;
2294
2295 /*
2296 * There can be multiple sources for the sampling clock. Find the one
2297 * that gives us the smallest deviation from the desired baud rate.
2298 */
2299
6af27bf2
GU		 2300 /* Optional Undivided External Clock */
2301 if (s->clk_rates[SCI_SCK] && port->type != PORT_SCIFA &&
2302 port->type != PORT_SCIFB) {
2303 err = sci_sck_calc(s, baud, &srr1);
2304 if (abs(err) < abs(min_err)) {
2305 best_clk = SCI_SCK;
2306 scr_val = SCSCR_CKE1;
2307 sccks = SCCKS_CKS;
2308 min_err = err;
2309 srr = srr1;
2310 if (!err)
2311 goto done;
2312 }
2313 }
2314
1270f865
GU		 2315 /* Optional BRG Frequency Divided External Clock */
2316 if (s->clk_rates[SCI_SCIF_CLK] && sci_getreg(port, SCDL)->size) {
2317 err = sci_brg_calc(s, baud, s->clk_rates[SCI_SCIF_CLK], &dl1,
2318 &srr1);
2319 if (abs(err) < abs(min_err)) {
2320 best_clk = SCI_SCIF_CLK;
2321 scr_val = SCSCR_CKE1;
2322 sccks = 0;
2323 min_err = err;
2324 dl = dl1;
2325 srr = srr1;
2326 if (!err)
2327 goto done;
2328 }
2329 }
2330
2331 /* Optional BRG Frequency Divided Internal Clock */
2332 if (s->clk_rates[SCI_BRG_INT] && sci_getreg(port, SCDL)->size) {
2333 err = sci_brg_calc(s, baud, s->clk_rates[SCI_BRG_INT], &dl1,
2334 &srr1);
2335 if (abs(err) < abs(min_err)) {
2336 best_clk = SCI_BRG_INT;
2337 scr_val = SCSCR_CKE1;
2338 sccks = SCCKS_XIN;
2339 min_err = err;
2340 dl = dl1;
2341 srr = srr1;
2342 if (!min_err)
2343 goto done;
f303b364
UH		 2344 }
2345 }
e108b2ca 2346
f4998e55
GU		 2347 /* Divided Functional Clock using standard Bit Rate Register */
2348 err = sci_scbrr_calc(s, baud, &brr1, &srr1, &cks1);
2349 if (abs(err) < abs(min_err)) {
2350 best_clk = SCI_FCK;
6af27bf2 2351 scr_val = 0;
f4998e55
GU		 2352 min_err = err;
2353 brr = brr1;
2354 srr = srr1;
2355 cks = cks1;
2356 }
2357
2358done:
2359 if (best_clk >= 0)
2360 dev_dbg(port->dev, "Using clk %pC for %u%+d bps\n",
2361 s->clks[best_clk], baud, min_err);
e108b2ca 2362
23241d43 2363 sci_port_enable(s);
36003386 2364
6af27bf2
GU		 2365 /*
2366 * Program the optional External Baud Rate Generator (BRG) first.
2367 * It controls the mux to select (H)SCK or frequency divided clock.
2368 */
1270f865
GU		 2369 if (best_clk >= 0 && sci_getreg(port, SCCKS)->size) {
2370 serial_port_out(port, SCDL, dl);
6af27bf2 2371 serial_port_out(port, SCCKS, sccks);
1270f865 2372 }
1da177e4 2373
1be22663
TA		 2374 spin_lock_irqsave(&port->lock, flags);
2375
1ba76220 2376 sci_reset(port);
1da177e4
LT		 2377
2378 uart_update_timeout(port, termios->c_cflag, baud);
2379
f4998e55 2380 if (best_clk >= 0) {
92a05748
GU		 2381 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
2382 switch (srr + 1) {
2383 case 5: smr_val |= SCSMR_SRC_5; break;
2384 case 7: smr_val |= SCSMR_SRC_7; break;
2385 case 11: smr_val |= SCSMR_SRC_11; break;
2386 case 13: smr_val |= SCSMR_SRC_13; break;
2387 case 16: smr_val |= SCSMR_SRC_16; break;
2388 case 17: smr_val |= SCSMR_SRC_17; break;
2389 case 19: smr_val |= SCSMR_SRC_19; break;
2390 case 27: smr_val |= SCSMR_SRC_27; break;
2391 }
f4998e55 2392 smr_val |= cks;
fa2abb03 2393 serial_port_out(port, SCSCR, scr_val | s->hscif_tot);
f4998e55
GU		 2394 serial_port_out(port, SCSMR, smr_val);
2395 serial_port_out(port, SCBRR, brr);
2396 if (sci_getreg(port, HSSRR)->size)
f303b364 2397 serial_port_out(port, HSSRR, srr | HSCIF_SRE);
f4998e55
GU		 2398
2399 /* Wait one bit interval */
2400 udelay((1000000 + (baud - 1)) / baud);
2401 } else {
2402 /* Don't touch the bit rate configuration */
2403 scr_val = s->cfg->scscr & (SCSCR_CKE1 | SCSCR_CKE0);
3a964abe
GU		 2404 smr_val |= serial_port_in(port, SCSMR) &
2405 (SCSMR_CKEDG | SCSMR_SRC_MASK | SCSMR_CKS);
fa2abb03 2406 serial_port_out(port, SCSCR, scr_val | s->hscif_tot);
9d482cc3 2407 serial_port_out(port, SCSMR, smr_val);
f4998e55 2408 }
1da177e4 2409
d5701647 2410 sci_init_pins(port, termios->c_cflag);
0979e0e6 2411
33f50ffc
GU		 2412 port->status &= ~UPSTAT_AUTOCTS;
2413 s->autorts = false;
73c3d53f
PM		 2414 reg = sci_getreg(port, SCFCR);
2415 if (reg->size) {
b12bb29f 2416 unsigned short ctrl = serial_port_in(port, SCFCR);
0979e0e6 2417
33f50ffc
GU		 2418 if ((port->flags & UPF_HARD_FLOW) &&
2419 (termios->c_cflag & CRTSCTS)) {
2420 /* There is no CTS interrupt to restart the hardware */
2421 port->status |= UPSTAT_AUTOCTS;
2422 /* MCE is enabled when RTS is raised */
2423 s->autorts = true;
faf02f8f 2424 }
73c3d53f
PM		 2425
2426 /*
2427 * As we've done a sci_reset() above, ensure we don't
2428 * interfere with the FIFOs while toggling MCE. As the
2429 * reset values could still be set, simply mask them out.
2430 */
2431 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST);
2432
b12bb29f 2433 serial_port_out(port, SCFCR, ctrl);
0979e0e6 2434 }
5f76895e
GU		 2435 if (port->flags & UPF_HARD_FLOW) {
2436 /* Refresh (Auto) RTS */
2437 sci_set_mctrl(port, port->mctrl);
2438 }
b7a76e4b 2439
9f8325b3
LP		 2440 scr_val |= SCSCR_RE | SCSCR_TE |
2441 (s->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0));
fa2abb03 2442 serial_port_out(port, SCSCR, scr_val | s->hscif_tot);
92a05748
GU		 2443 if ((srr + 1 == 5) &&
2444 (port->type == PORT_SCIFA || port->type == PORT_SCIFB)) {
2445 /*
2446 * In asynchronous mode, when the sampling rate is 1/5, first
2447 * received data may become invalid on some SCIFA and SCIFB.
2448 * To avoid this problem wait more than 1 serial data time (1
2449 * bit time x serial data number) after setting SCSCR.RE = 1.
2450 */
2451 udelay(DIV_ROUND_UP(10 * 1000000, baud));
2452 }
1da177e4 2453
3089f381 2454 /*
5f6d8515 2455 * Calculate delay for 2 DMA buffers (4 FIFO).
f5835c1d
GU		 2456 * See serial_core.c::uart_update_timeout().
2457 * With 10 bits (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above
2458 * function calculates 1 jiffie for the data plus 5 jiffies for the
2459 * "slop(e)." Then below we calculate 5 jiffies (20ms) for 2 DMA
2460 * buffers (4 FIFO sizes), but when performing a faster transfer, the
2461 * value obtained by this formula is too small. Therefore, if the value
2462 * is smaller than 20ms, use 20ms as the timeout value for DMA.
3089f381 2463 */
03940376
UH		 2464 /* byte size and parity */
2465 switch (termios->c_cflag & CSIZE) {
2466 case CS5:
2467 bits = 7;
2468 break;
2469 case CS6:
2470 bits = 8;
2471 break;
2472 case CS7:
2473 bits = 9;
2474 break;
2475 default:
2476 bits = 10;
2477 break;
2478 }
5f6d8515 2479
03940376
UH		 2480 if (termios->c_cflag & CSTOPB)
2481 bits++;
2482 if (termios->c_cflag & PARENB)
2483 bits++;
5f6d8515 2484
03940376
UH		 2485 s->rx_frame = (100 * bits * HZ) / (baud / 10);
2486#ifdef CONFIG_SERIAL_SH_SCI_DMA
2487 s->rx_timeout = DIV_ROUND_UP(s->buf_len_rx * 2 * s->rx_frame, 1000);
03940376
UH		 2488 if (s->rx_timeout < msecs_to_jiffies(20))
2489 s->rx_timeout = msecs_to_jiffies(20);
3089f381
GL		 2490#endif
2491
1da177e4 2492 if ((termios->c_cflag & CREAD) != 0)
73a19e4c 2493 sci_start_rx(port);
36003386 2494
1be22663
TA		 2495 spin_unlock_irqrestore(&port->lock, flags);
2496
23241d43 2497 sci_port_disable(s);
f907c9ea
GU		 2498
2499 if (UART_ENABLE_MS(port, termios->c_cflag))
2500 sci_enable_ms(port);
1da177e4
LT		 2501}
2502
0174e5ca
TK		 2503static void sci_pm(struct uart_port *port, unsigned int state,
2504 unsigned int oldstate)
2505{
2506 struct sci_port *sci_port = to_sci_port(port);
2507
2508 switch (state) {
d3dfe5d9 2509 case UART_PM_STATE_OFF:
0174e5ca
TK		 2510 sci_port_disable(sci_port);
2511 break;
2512 default:
2513 sci_port_enable(sci_port);
2514 break;
2515 }
2516}
2517
1da177e4
LT		 2518static const char *sci_type(struct uart_port *port)
2519{
2520 switch (port->type) {
e7c98dc7
MT		 2521 case PORT_IRDA:
2522 return "irda";
2523 case PORT_SCI:
2524 return "sci";
2525 case PORT_SCIF:
2526 return "scif";
2527 case PORT_SCIFA:
2528 return "scifa";
d1d4b10c
GL		 2529 case PORT_SCIFB:
2530 return "scifb";
f303b364
UH		 2531 case PORT_HSCIF:
2532 return "hscif";
1da177e4
LT		 2533 }
2534
fa43972f 2535 return NULL;
1da177e4
LT		 2536}
2537
f6e9495d
PM		 2538static int sci_remap_port(struct uart_port *port)
2539{
e4d6f911 2540 struct sci_port *sport = to_sci_port(port);
f6e9495d
PM		 2541
2542 /*
2543 * Nothing to do if there's already an established membase.
2544 */
2545 if (port->membase)
2546 return 0;
2547
3d73f32b 2548 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) {
e4d6f911 2549 port->membase = ioremap_nocache(port->mapbase, sport->reg_size);
f6e9495d
PM		 2550 if (unlikely(!port->membase)) {
2551 dev_err(port->dev, "can't remap port#%d\n", port->line);
2552 return -ENXIO;
2553 }
2554 } else {
2555 /*
2556 * For the simple (and majority of) cases where we don't
2557 * need to do any remapping, just cast the cookie
2558 * directly.
2559 */
3af4e960 2560 port->membase = (void __iomem *)(uintptr_t)port->mapbase;
f6e9495d
PM		 2561 }
2562
2563 return 0;
2564}
2565
e2651647 2566static void sci_release_port(struct uart_port *port)
1da177e4 2567{
e4d6f911
YS		 2568 struct sci_port *sport = to_sci_port(port);
2569
3d73f32b 2570 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) {
e2651647
PM		 2571 iounmap(port->membase);
2572 port->membase = NULL;
2573 }
2574
e4d6f911 2575 release_mem_region(port->mapbase, sport->reg_size);
1da177e4
LT		 2576}
2577
e2651647 2578static int sci_request_port(struct uart_port *port)
1da177e4 2579{
e2651647 2580 struct resource *res;
e4d6f911 2581 struct sci_port *sport = to_sci_port(port);
f6e9495d 2582 int ret;
1da177e4 2583
e4d6f911
YS		 2584 res = request_mem_region(port->mapbase, sport->reg_size,
2585 dev_name(port->dev));
2586 if (unlikely(res == NULL)) {
2587 dev_err(port->dev, "request_mem_region failed.");
e2651647 2588 return -EBUSY;
e4d6f911 2589 }
1da177e4 2590
f6e9495d
PM		 2591 ret = sci_remap_port(port);
2592 if (unlikely(ret != 0)) {
2593 release_resource(res);
2594 return ret;
7ff731ae 2595 }
e2651647
PM		 2596
2597 return 0;
2598}
2599
2600static void sci_config_port(struct uart_port *port, int flags)
2601{
2602 if (flags & UART_CONFIG_TYPE) {
2603 struct sci_port *sport = to_sci_port(port);
2604
2605 port->type = sport->cfg->type;
2606 sci_request_port(port);
2607 }
1da177e4
LT		 2608}
2609
2610static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
2611{
1da177e4
LT		 2612 if (ser->baud_base < 2400)
2613 /* No paper tape reader for Mitch.. */
2614 return -EINVAL;
2615
2616 return 0;
2617}
2618
069a47e5 2619static const struct uart_ops sci_uart_ops = {
1da177e4
LT		 2620 .tx_empty = sci_tx_empty,
2621 .set_mctrl = sci_set_mctrl,
2622 .get_mctrl = sci_get_mctrl,
2623 .start_tx = sci_start_tx,
2624 .stop_tx = sci_stop_tx,
2625 .stop_rx = sci_stop_rx,
f907c9ea 2626 .enable_ms = sci_enable_ms,
1da177e4
LT		 2627 .break_ctl = sci_break_ctl,
2628 .startup = sci_startup,
2629 .shutdown = sci_shutdown,
1cf4a7ef 2630 .flush_buffer = sci_flush_buffer,
1da177e4 2631 .set_termios = sci_set_termios,
0174e5ca 2632 .pm = sci_pm,
1da177e4
LT		 2633 .type = sci_type,
2634 .release_port = sci_release_port,
2635 .request_port = sci_request_port,
2636 .config_port = sci_config_port,
2637 .verify_port = sci_verify_port,
07d2a1a1
PM		 2638#ifdef CONFIG_CONSOLE_POLL
2639 .poll_get_char = sci_poll_get_char,
2640 .poll_put_char = sci_poll_put_char,
2641#endif
1da177e4
LT		 2642};
2643
a9ec81f4
LP		 2644static int sci_init_clocks(struct sci_port *sci_port, struct device *dev)
2645{
f4998e55
GU		 2646 const char *clk_names[] = {
2647 [SCI_FCK] = "fck",
6af27bf2 2648 [SCI_SCK] = "sck",
1270f865
GU		 2649 [SCI_BRG_INT] = "brg_int",
2650 [SCI_SCIF_CLK] = "scif_clk",
f4998e55
GU		 2651 };
2652 struct clk *clk;
2653 unsigned int i;
a9ec81f4 2654
6af27bf2
GU		 2655 if (sci_port->cfg->type == PORT_HSCIF)
2656 clk_names[SCI_SCK] = "hsck";
2657
f4998e55
GU		 2658 for (i = 0; i < SCI_NUM_CLKS; i++) {
2659 clk = devm_clk_get(dev, clk_names[i]);
2660 if (PTR_ERR(clk) == -EPROBE_DEFER)
2661 return -EPROBE_DEFER;
a9ec81f4 2662
f4998e55
GU		 2663 if (IS_ERR(clk) && i == SCI_FCK) {
2664 /*
2665 * "fck" used to be called "sci_ick", and we need to
2666 * maintain DT backward compatibility.
2667 */
2668 clk = devm_clk_get(dev, "sci_ick");
2669 if (PTR_ERR(clk) == -EPROBE_DEFER)
2670 return -EPROBE_DEFER;
a9ec81f4 2671
f4998e55
GU		 2672 if (!IS_ERR(clk))
2673 goto found;
a9ec81f4 2674
f4998e55
GU		 2675 /*
2676 * Not all SH platforms declare a clock lookup entry
2677 * for SCI devices, in which case we need to get the
2678 * global "peripheral_clk" clock.
2679 */
2680 clk = devm_clk_get(dev, "peripheral_clk");
2681 if (!IS_ERR(clk))
2682 goto found;
2683
2684 dev_err(dev, "failed to get %s (%ld)\n", clk_names[i],
2685 PTR_ERR(clk));
2686 return PTR_ERR(clk);
2687 }
2688
2689found:
2690 if (IS_ERR(clk))
2691 dev_dbg(dev, "failed to get %s (%ld)\n", clk_names[i],
2692 PTR_ERR(clk));
2693 else
2694 dev_dbg(dev, "clk %s is %pC rate %pCr\n", clk_names[i],
2695 clk, clk);
2696 sci_port->clks[i] = IS_ERR(clk) ? NULL : clk;
2697 }
2698 return 0;
a9ec81f4
LP		 2699}
2700
daf5a895
LP		 2701static const struct sci_port_params *
2702sci_probe_regmap(const struct plat_sci_port *cfg)
2703{
2704 unsigned int regtype;
2705
2706 if (cfg->regtype != SCIx_PROBE_REGTYPE)
2707 return &sci_port_params[cfg->regtype];
2708
2709 switch (cfg->type) {
2710 case PORT_SCI:
2711 regtype = SCIx_SCI_REGTYPE;
2712 break;
2713 case PORT_IRDA:
2714 regtype = SCIx_IRDA_REGTYPE;
2715 break;
2716 case PORT_SCIFA:
2717 regtype = SCIx_SCIFA_REGTYPE;
2718 break;
2719 case PORT_SCIFB:
2720 regtype = SCIx_SCIFB_REGTYPE;
2721 break;
2722 case PORT_SCIF:
2723 /*
2724 * The SH-4 is a bit of a misnomer here, although that's
2725 * where this particular port layout originated. This
2726 * configuration (or some slight variation thereof)
2727 * remains the dominant model for all SCIFs.
2728 */
2729 regtype = SCIx_SH4_SCIF_REGTYPE;
2730 break;
2731 case PORT_HSCIF:
2732 regtype = SCIx_HSCIF_REGTYPE;
2733 break;
2734 default:
2735 pr_err("Can't probe register map for given port\n");
2736 return NULL;
2737 }
2738
2739 return &sci_port_params[regtype];
2740}
2741
9671f099 2742static int sci_init_single(struct platform_device *dev,
1fcc91a6 2743 struct sci_port *sci_port, unsigned int index,
daf5a895 2744 const struct plat_sci_port *p, bool early)
e108b2ca 2745{
73a19e4c 2746 struct uart_port *port = &sci_port->port;
1fcc91a6
LP		 2747 const struct resource *res;
2748 unsigned int i;
3127c6b2 2749 int ret;
e108b2ca 2750
50f0959a
PM		 2751 sci_port->cfg = p;
2752
73a19e4c
GL		 2753 port->ops = &sci_uart_ops;
2754 port->iotype = UPIO_MEM;
2755 port->line = index;
75136d48 2756
89b5c1ab
LP		 2757 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
2758 if (res == NULL)
2759 return -ENOMEM;
1fcc91a6 2760
89b5c1ab 2761 port->mapbase = res->start;
e4d6f911 2762 sci_port->reg_size = resource_size(res);
1fcc91a6 2763
89b5c1ab
LP		 2764 for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i)
2765 sci_port->irqs[i] = platform_get_irq(dev, i);
1fcc91a6 2766
89b5c1ab
LP		 2767 /* The SCI generates several interrupts. They can be muxed together or
2768 * connected to different interrupt lines. In the muxed case only one
2769 * interrupt resource is specified. In the non-muxed case three or four
2770 * interrupt resources are specified, as the BRI interrupt is optional.
2771 */
2772 if (sci_port->irqs[0] < 0)
2773 return -ENXIO;
1fcc91a6 2774
89b5c1ab
LP		 2775 if (sci_port->irqs[1] < 0) {
2776 sci_port->irqs[1] = sci_port->irqs[0];
2777 sci_port->irqs[2] = sci_port->irqs[0];
2778 sci_port->irqs[3] = sci_port->irqs[0];
1fcc91a6
LP		 2779 }
2780
daf5a895
LP		 2781 sci_port->params = sci_probe_regmap(p);
2782 if (unlikely(sci_port->params == NULL))
2783 return -EINVAL;
e095ee6b 2784
18e8cf15
UH		 2785 switch (p->type) {
2786 case PORT_SCIFB:
2787 sci_port->rx_trigger = 48;
2788 break;
2789 case PORT_HSCIF:
2790 sci_port->rx_trigger = 64;
2791 break;
2792 case PORT_SCIFA:
2793 sci_port->rx_trigger = 32;
2794 break;
2795 case PORT_SCIF:
2796 if (p->regtype == SCIx_SH7705_SCIF_REGTYPE)
2797 /* RX triggering not implemented for this IP */
2798 sci_port->rx_trigger = 1;
2799 else
2800 sci_port->rx_trigger = 8;
2801 break;
2802 default:
2803 sci_port->rx_trigger = 1;
2804 break;
2805 }
2806
03940376 2807 sci_port->rx_fifo_timeout = 0;
fa2abb03 2808 sci_port->hscif_tot = 0;
03940376 2809
878fbb91
LP		 2810 /* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't
2811 * match the SoC datasheet, this should be investigated. Let platform
2812 * data override the sampling rate for now.
ec09c5eb 2813 */
b2f20ed9
LP		 2814 sci_port->sampling_rate_mask = p->sampling_rate
2815 ? SCI_SR(p->sampling_rate)
2816 : sci_port->params->sampling_rate_mask;
ec09c5eb 2817
1fcc91a6 2818 if (!early) {
a9ec81f4
LP		 2819 ret = sci_init_clocks(sci_port, &dev->dev);
2820 if (ret < 0)
2821 return ret;
c7ed1ab3 2822
73a19e4c 2823 port->dev = &dev->dev;
5e50d2d6
MD		 2824
2825 pm_runtime_enable(&dev->dev);
7b6fd3bf 2826 }
e108b2ca 2827
ce6738b6 2828 port->type = p->type;
3d73f32b 2829 port->flags = UPF_FIXED_PORT | UPF_BOOT_AUTOCONF | p->flags;
b2f20ed9 2830 port->fifosize = sci_port->params->fifosize;
73a19e4c 2831
dfc80387
LP		 2832 if (port->type == PORT_SCI) {
2833 if (sci_port->reg_size >= 0x20)
2834 port->regshift = 2;
2835 else
2836 port->regshift = 1;
2837 }
2838
ce6738b6 2839 /*
61a6976b 2840 * The UART port needs an IRQ value, so we peg this to the RX IRQ
ce6738b6
PM		 2841 * for the multi-IRQ ports, which is where we are primarily
2842 * concerned with the shutdown path synchronization.
2843 *
2844 * For the muxed case there's nothing more to do.
2845 */
1fcc91a6 2846 port->irq = sci_port->irqs[SCIx_RXI_IRQ];
9cfb5c05 2847 port->irqflags = 0;
73a19e4c 2848
61a6976b
PM		 2849 port->serial_in = sci_serial_in;
2850 port->serial_out = sci_serial_out;
2851
c7ed1ab3 2852 return 0;
e108b2ca
PM		 2853}
2854
6dae1421
LP		 2855static void sci_cleanup_single(struct sci_port *port)
2856{
6dae1421
LP		 2857 pm_runtime_disable(port->port.dev);
2858}
2859
0b0cced1
YS		 2860#if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \
2861 defined(CONFIG_SERIAL_SH_SCI_EARLYCON)
dc8e6f5b
MD		 2862static void serial_console_putchar(struct uart_port *port, int ch)
2863{
2864 sci_poll_put_char(port, ch);
2865}
2866
1da177e4
LT		 2867/*
2868 * Print a string to the serial port trying not to disturb
2869 * any possible real use of the port...
2870 */
2871static void serial_console_write(struct console *co, const char *s,
2872 unsigned count)
2873{
906b17dc
PM		 2874 struct sci_port *sci_port = &sci_ports[co->index];
2875 struct uart_port *port = &sci_port->port;
a67969b5 2876 unsigned short bits, ctrl, ctrl_temp;
40f70c03
SK		 2877 unsigned long flags;
2878 int locked = 1;
2879
2880 local_irq_save(flags);
0b0cced1 2881#if defined(SUPPORT_SYSRQ)
40f70c03
SK		 2882 if (port->sysrq)
2883 locked = 0;
0b0cced1
YS		 2884 else
2885#endif
2886 if (oops_in_progress)
40f70c03
SK		 2887 locked = spin_trylock(&port->lock);
2888 else
2889 spin_lock(&port->lock);
2890
a67969b5 2891 /* first save SCSCR then disable interrupts, keep clock source */
40f70c03 2892 ctrl = serial_port_in(port, SCSCR);
9f8325b3
LP		 2893 ctrl_temp = SCSCR_RE | SCSCR_TE |
2894 (sci_port->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)) |
a67969b5 2895 (ctrl & (SCSCR_CKE1 | SCSCR_CKE0));
fa2abb03 2896 serial_port_out(port, SCSCR, ctrl_temp | sci_port->hscif_tot);
07d2a1a1 2897
501b825d 2898 uart_console_write(port, s, count, serial_console_putchar);
973e5d52
MD		 2899
2900 /* wait until fifo is empty and last bit has been transmitted */
2901 bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
b12bb29f 2902 while ((serial_port_in(port, SCxSR) & bits) != bits)
973e5d52 2903 cpu_relax();
40f70c03
SK		 2904
2905 /* restore the SCSCR */
2906 serial_port_out(port, SCSCR, ctrl);
2907
2908 if (locked)
2909 spin_unlock(&port->lock);
2910 local_irq_restore(flags);
1da177e4
LT		 2911}
2912
9671f099 2913static int serial_console_setup(struct console *co, char *options)
1da177e4 2914{
dc8e6f5b 2915 struct sci_port *sci_port;
1da177e4
LT		 2916 struct uart_port *port;
2917 int baud = 115200;
2918 int bits = 8;
2919 int parity = 'n';
2920 int flow = 'n';
2921 int ret;
2922
e108b2ca 2923 /*
906b17dc 2924 * Refuse to handle any bogus ports.
1da177e4 2925 */
906b17dc 2926 if (co->index < 0 || co->index >= SCI_NPORTS)
e108b2ca 2927 return -ENODEV;
e108b2ca 2928
906b17dc
PM		 2929 sci_port = &sci_ports[co->index];
2930 port = &sci_port->port;
2931
b2267a6b
AC		 2932 /*
2933 * Refuse to handle uninitialized ports.
2934 */
2935 if (!port->ops)
2936 return -ENODEV;
2937
f6e9495d
PM		 2938 ret = sci_remap_port(port);
2939 if (unlikely(ret != 0))
2940 return ret;
e108b2ca 2941
1da177e4
LT		 2942 if (options)
2943 uart_parse_options(options, &baud, &parity, &bits, &flow);
2944
ab7cfb55 2945 return uart_set_options(port, co, baud, parity, bits, flow);
1da177e4
LT		 2946}
2947
2948static struct console serial_console = {
2949 .name = "ttySC",
906b17dc 2950 .device = uart_console_device,
1da177e4
LT		 2951 .write = serial_console_write,
2952 .setup = serial_console_setup,
fa5da2f7 2953 .flags = CON_PRINTBUFFER,
1da177e4 2954 .index = -1,
906b17dc 2955 .data = &sci_uart_driver,
1da177e4
LT		 2956};
2957
7b6fd3bf
MD		 2958static struct console early_serial_console = {
2959 .name = "early_ttySC",
2960 .write = serial_console_write,
2961 .flags = CON_PRINTBUFFER,
906b17dc 2962 .index = -1,
7b6fd3bf 2963};
ecdf8a46 2964
7b6fd3bf
MD		 2965static char early_serial_buf[32];
2966
9671f099 2967static int sci_probe_earlyprintk(struct platform_device *pdev)
ecdf8a46 2968{
daf5a895 2969 const struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev);
ecdf8a46
PM		 2970
2971 if (early_serial_console.data)
2972 return -EEXIST;
2973
2974 early_serial_console.index = pdev->id;
ecdf8a46 2975
1fcc91a6 2976 sci_init_single(pdev, &sci_ports[pdev->id], pdev->id, cfg, true);
ecdf8a46
PM		 2977
2978 serial_console_setup(&early_serial_console, early_serial_buf);
2979
2980 if (!strstr(early_serial_buf, "keep"))
2981 early_serial_console.flags |= CON_BOOT;
2982
2983 register_console(&early_serial_console);
2984 return 0;
2985}
6a8c9799
NI		 2986
2987#define SCI_CONSOLE (&serial_console)
2988
ecdf8a46 2989#else
9671f099 2990static inline int sci_probe_earlyprintk(struct platform_device *pdev)
ecdf8a46
PM		 2991{
2992 return -EINVAL;
2993}
1da177e4 2994
6a8c9799
NI		 2995#define SCI_CONSOLE NULL
2996
0b0cced1 2997#endif /* CONFIG_SERIAL_SH_SCI_CONSOLE || CONFIG_SERIAL_SH_SCI_EARLYCON */
1da177e4 2998
6c13d5d2 2999static const char banner[] __initconst = "SuperH (H)SCI(F) driver initialized";
1da177e4 3000
352b9266 3001static DEFINE_MUTEX(sci_uart_registration_lock);
1da177e4
LT		 3002static struct uart_driver sci_uart_driver = {
3003 .owner = THIS_MODULE,
3004 .driver_name = "sci",
1da177e4
LT		 3005 .dev_name = "ttySC",
3006 .major = SCI_MAJOR,
3007 .minor = SCI_MINOR_START,
e108b2ca 3008 .nr = SCI_NPORTS,
1da177e4
LT		 3009 .cons = SCI_CONSOLE,
3010};
3011
54507f6e 3012static int sci_remove(struct platform_device *dev)
e552de24 3013{
d535a230 3014 struct sci_port *port = platform_get_drvdata(dev);
e552de24 3015
d535a230
PM		 3016 uart_remove_one_port(&sci_uart_driver, &port->port);
3017
6dae1421 3018 sci_cleanup_single(port);
e552de24 3019
5d23188a
UH		 3020 if (port->port.fifosize > 1) {
3021 sysfs_remove_file(&dev->dev.kobj,
3022 &dev_attr_rx_fifo_trigger.attr);
3023 }
fa2abb03
UH		 3024 if (port->port.type == PORT_SCIFA || port->port.type == PORT_SCIFB ||
3025 port->port.type == PORT_HSCIF) {
5d23188a
UH		 3026 sysfs_remove_file(&dev->dev.kobj,
3027 &dev_attr_rx_fifo_timeout.attr);
3028 }
3029
e552de24
MD		 3030 return 0;
3031}
3032
bd2238fb
GU		 3033
3034#define SCI_OF_DATA(type, regtype) (void *)((type) << 16 | (regtype))
3035#define SCI_OF_TYPE(data) ((unsigned long)(data) >> 16)
3036#define SCI_OF_REGTYPE(data) ((unsigned long)(data) & 0xffff)
20bdcab8
BH		 3037
3038static const struct of_device_id of_sci_match[] = {
f443ff80
GU		 3039 /* SoC-specific types */
3040 {
3041 .compatible = "renesas,scif-r7s72100",
3042 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH2_SCIF_FIFODATA_REGTYPE),
3043 },
9ed44bb2
GU		 3044 /* Family-specific types */
3045 {
3046 .compatible = "renesas,rcar-gen1-scif",
3047 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
3048 }, {
3049 .compatible = "renesas,rcar-gen2-scif",
3050 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
3051 }, {
3052 .compatible = "renesas,rcar-gen3-scif",
3053 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
3054 },
f443ff80 3055 /* Generic types */
20bdcab8
BH		 3056 {
3057 .compatible = "renesas,scif",
bd2238fb 3058 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_REGTYPE),
20bdcab8
BH		 3059 }, {
3060 .compatible = "renesas,scifa",
bd2238fb 3061 .data = SCI_OF_DATA(PORT_SCIFA, SCIx_SCIFA_REGTYPE),
20bdcab8
BH		 3062 }, {
3063 .compatible = "renesas,scifb",
bd2238fb 3064 .data = SCI_OF_DATA(PORT_SCIFB, SCIx_SCIFB_REGTYPE),
20bdcab8
BH		 3065 }, {
3066 .compatible = "renesas,hscif",
bd2238fb 3067 .data = SCI_OF_DATA(PORT_HSCIF, SCIx_HSCIF_REGTYPE),
e1d0be61
YS		 3068 }, {
3069 .compatible = "renesas,sci",
bd2238fb 3070 .data = SCI_OF_DATA(PORT_SCI, SCIx_SCI_REGTYPE),
20bdcab8
BH		 3071 }, {
3072 /* Terminator */
3073 },
3074};
3075MODULE_DEVICE_TABLE(of, of_sci_match);
3076
54b12c48
GU		 3077static struct plat_sci_port *sci_parse_dt(struct platform_device *pdev,
3078 unsigned int *dev_id)
20bdcab8
BH		 3079{
3080 struct device_node *np = pdev->dev.of_node;
20bdcab8 3081 struct plat_sci_port *p;
97ed9790 3082 struct sci_port *sp;
6e605a01 3083 const void *data;
20bdcab8
BH		 3084 int id;
3085
3086 if (!IS_ENABLED(CONFIG_OF) || !np)
3087 return NULL;
3088
6e605a01 3089 data = of_device_get_match_data(&pdev->dev);
20bdcab8 3090
20bdcab8 3091 p = devm_kzalloc(&pdev->dev, sizeof(struct plat_sci_port), GFP_KERNEL);
4205463c 3092 if (!p)
20bdcab8 3093 return NULL;
20bdcab8 3094
2095fc76 3095 /* Get the line number from the aliases node. */
20bdcab8
BH		 3096 id = of_alias_get_id(np, "serial");
3097 if (id < 0) {
3098 dev_err(&pdev->dev, "failed to get alias id (%d)\n", id);
3099 return NULL;
3100 }
3101
97ed9790 3102 sp = &sci_ports[id];
20bdcab8
BH		 3103 *dev_id = id;
3104
6e605a01
GU		 3105 p->type = SCI_OF_TYPE(data);
3106 p->regtype = SCI_OF_REGTYPE(data);
20bdcab8 3107
43c61286 3108 sp->has_rtscts = of_property_read_bool(np, "uart-has-rtscts");
861a70ab 3109
20bdcab8
BH		 3110 return p;
3111}
3112
9671f099 3113static int sci_probe_single(struct platform_device *dev,
0ee70712
MD		 3114 unsigned int index,
3115 struct plat_sci_port *p,
3116 struct sci_port *sciport)
3117{
0ee70712
MD		 3118 int ret;
3119
3120 /* Sanity check */
3121 if (unlikely(index >= SCI_NPORTS)) {
9b971cd2 3122 dev_notice(&dev->dev, "Attempting to register port %d when only %d are available\n",
0ee70712 3123 index+1, SCI_NPORTS);
9b971cd2 3124 dev_notice(&dev->dev, "Consider bumping CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
b6c5ef6f 3125 return -EINVAL;
0ee70712
MD		 3126 }
3127
352b9266
SS		 3128 mutex_lock(&sci_uart_registration_lock);
3129 if (!sci_uart_driver.state) {
3130 ret = uart_register_driver(&sci_uart_driver);
3131 if (ret) {
3132 mutex_unlock(&sci_uart_registration_lock);
3133 return ret;
3134 }
3135 }
3136 mutex_unlock(&sci_uart_registration_lock);
3137
1fcc91a6 3138 ret = sci_init_single(dev, sciport, index, p, false);
c7ed1ab3
PM		 3139 if (ret)
3140 return ret;
0ee70712 3141
f907c9ea
GU		 3142 sciport->gpios = mctrl_gpio_init(&sciport->port, 0);
3143 if (IS_ERR(sciport->gpios) && PTR_ERR(sciport->gpios) != -ENOSYS)
3144 return PTR_ERR(sciport->gpios);
3145
97ed9790 3146 if (sciport->has_rtscts) {
f907c9ea
GU		 3147 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(sciport->gpios,
3148 UART_GPIO_CTS)) ||
3149 !IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(sciport->gpios,
3150 UART_GPIO_RTS))) {
3151 dev_err(&dev->dev, "Conflicting RTS/CTS config\n");
3152 return -EINVAL;
3153 }
33f50ffc 3154 sciport->port.flags |= UPF_HARD_FLOW;
f907c9ea
GU		 3155 }
3156
6dae1421
LP		 3157 ret = uart_add_one_port(&sci_uart_driver, &sciport->port);
3158 if (ret) {
3159 sci_cleanup_single(sciport);
3160 return ret;
3161 }
3162
3163 return 0;
0ee70712
MD		 3164}
3165
9671f099 3166static int sci_probe(struct platform_device *dev)
1da177e4 3167{
20bdcab8
BH		 3168 struct plat_sci_port *p;
3169 struct sci_port *sp;
3170 unsigned int dev_id;
ecdf8a46 3171 int ret;
d535a230 3172
ecdf8a46
PM		 3173 /*
3174 * If we've come here via earlyprintk initialization, head off to
3175 * the special early probe. We don't have sufficient device state
3176 * to make it beyond this yet.
3177 */
3178 if (is_early_platform_device(dev))
3179 return sci_probe_earlyprintk(dev);
7b6fd3bf 3180
20bdcab8
BH		 3181 if (dev->dev.of_node) {
3182 p = sci_parse_dt(dev, &dev_id);
3183 if (p == NULL)
3184 return -EINVAL;
3185 } else {
3186 p = dev->dev.platform_data;
3187 if (p == NULL) {
3188 dev_err(&dev->dev, "no platform data supplied\n");
3189 return -EINVAL;
3190 }
3191
3192 dev_id = dev->id;
3193 }
3194
3195 sp = &sci_ports[dev_id];
d535a230 3196 platform_set_drvdata(dev, sp);
e552de24 3197
20bdcab8 3198 ret = sci_probe_single(dev, dev_id, p, sp);
d535a230 3199 if (ret)
6dae1421 3200 return ret;
e552de24 3201
5d23188a
UH		 3202 if (sp->port.fifosize > 1) {
3203 ret = sysfs_create_file(&dev->dev.kobj,
3204 &dev_attr_rx_fifo_trigger.attr);
3205 if (ret)
3206 return ret;
3207 }
fa2abb03
UH		 3208 if (sp->port.type == PORT_SCIFA || sp->port.type == PORT_SCIFB ||
3209 sp->port.type == PORT_HSCIF) {
5d23188a
UH		 3210 ret = sysfs_create_file(&dev->dev.kobj,
3211 &dev_attr_rx_fifo_timeout.attr);
3212 if (ret) {
3213 if (sp->port.fifosize > 1) {
3214 sysfs_remove_file(&dev->dev.kobj,
3215 &dev_attr_rx_fifo_trigger.attr);
3216 }
3217 return ret;
3218 }
3219 }
3220
1da177e4
LT		 3221#ifdef CONFIG_SH_STANDARD_BIOS
3222 sh_bios_gdb_detach();
3223#endif
3224
e108b2ca 3225 return 0;
1da177e4
LT		 3226}
3227
cb876341 3228static __maybe_unused int sci_suspend(struct device *dev)
1da177e4 3229{
d535a230 3230 struct sci_port *sport = dev_get_drvdata(dev);
e108b2ca 3231
d535a230
PM		 3232 if (sport)
3233 uart_suspend_port(&sci_uart_driver, &sport->port);
1da177e4 3234
e108b2ca
PM		 3235 return 0;
3236}
1da177e4 3237
cb876341 3238static __maybe_unused int sci_resume(struct device *dev)
e108b2ca 3239{
d535a230 3240 struct sci_port *sport = dev_get_drvdata(dev);
e108b2ca 3241
d535a230
PM		 3242 if (sport)
3243 uart_resume_port(&sci_uart_driver, &sport->port);
e108b2ca
PM		 3244
3245 return 0;
3246}
3247
cb876341 3248static SIMPLE_DEV_PM_OPS(sci_dev_pm_ops, sci_suspend, sci_resume);
6daa79b3 3249
e108b2ca
PM		 3250static struct platform_driver sci_driver = {
3251 .probe = sci_probe,
b9e39c89 3252 .remove = sci_remove,
e108b2ca
PM		 3253 .driver = {
3254 .name = "sh-sci",
6daa79b3 3255 .pm = &sci_dev_pm_ops,
20bdcab8 3256 .of_match_table = of_match_ptr(of_sci_match),
e108b2ca
PM		 3257 },
3258};
3259
3260static int __init sci_init(void)
3261{
6c13d5d2 3262 pr_info("%s\n", banner);
e108b2ca 3263
352b9266 3264 return platform_driver_register(&sci_driver);
e108b2ca
PM		 3265}
3266
3267static void __exit sci_exit(void)
3268{
3269 platform_driver_unregister(&sci_driver);
352b9266
SS		 3270
3271 if (sci_uart_driver.state)
3272 uart_unregister_driver(&sci_uart_driver);
1da177e4
LT		 3273}
3274
7b6fd3bf
MD		 3275#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
3276early_platform_init_buffer("earlyprintk", &sci_driver,
3277 early_serial_buf, ARRAY_SIZE(early_serial_buf));
3278#endif
0b0cced1 3279#ifdef CONFIG_SERIAL_SH_SCI_EARLYCON
dd076cff 3280static struct plat_sci_port port_cfg __initdata;
0b0cced1
YS		 3281
3282static int __init early_console_setup(struct earlycon_device *device,
3283 int type)
3284{
3285 if (!device->port.membase)
3286 return -ENODEV;
3287
3288 device->port.serial_in = sci_serial_in;
3289 device->port.serial_out = sci_serial_out;
3290 device->port.type = type;
3291 memcpy(&sci_ports[0].port, &device->port, sizeof(struct uart_port));
daf5a895 3292 port_cfg.type = type;
0b0cced1 3293 sci_ports[0].cfg = &port_cfg;
daf5a895 3294 sci_ports[0].params = sci_probe_regmap(&port_cfg);
9f8325b3
LP		 3295 port_cfg.scscr = sci_serial_in(&sci_ports[0].port, SCSCR);
3296 sci_serial_out(&sci_ports[0].port, SCSCR,
3297 SCSCR_RE | SCSCR_TE | port_cfg.scscr);
0b0cced1
YS		 3298
3299 device->con->write = serial_console_write;
3300 return 0;
3301}
3302static int __init sci_early_console_setup(struct earlycon_device *device,
3303 const char *opt)
3304{
3305 return early_console_setup(device, PORT_SCI);
3306}
3307static int __init scif_early_console_setup(struct earlycon_device *device,
3308 const char *opt)
3309{
3310 return early_console_setup(device, PORT_SCIF);
3311}
3312static int __init scifa_early_console_setup(struct earlycon_device *device,
3313 const char *opt)
3314{
3315 return early_console_setup(device, PORT_SCIFA);
3316}
3317static int __init scifb_early_console_setup(struct earlycon_device *device,
3318 const char *opt)
3319{
3320 return early_console_setup(device, PORT_SCIFB);
3321}
3322static int __init hscif_early_console_setup(struct earlycon_device *device,
3323 const char *opt)
3324{
3325 return early_console_setup(device, PORT_HSCIF);
3326}
3327
0b0cced1 3328OF_EARLYCON_DECLARE(sci, "renesas,sci", sci_early_console_setup);
0b0cced1 3329OF_EARLYCON_DECLARE(scif, "renesas,scif", scif_early_console_setup);
0b0cced1 3330OF_EARLYCON_DECLARE(scifa, "renesas,scifa", scifa_early_console_setup);
0b0cced1 3331OF_EARLYCON_DECLARE(scifb, "renesas,scifb", scifb_early_console_setup);
0b0cced1
YS		 3332OF_EARLYCON_DECLARE(hscif, "renesas,hscif", hscif_early_console_setup);
3333#endif /* CONFIG_SERIAL_SH_SCI_EARLYCON */
3334
1da177e4
LT		 3335module_init(sci_init);
3336module_exit(sci_exit);
3337
e108b2ca 3338MODULE_LICENSE("GPL");
e169c139 3339MODULE_ALIAS("platform:sh-sci");
7f405f9c 3340MODULE_AUTHOR("Paul Mundt");
f303b364 3341MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver");
Linux 6.x block layer and io_uring tree(s)