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serial: sh-sci: Add BRG register definitions
[linux-block.git] / drivers / tty / serial / sh-sci.c
CommitLineData
1da177e4 1/*
1da177e4
LT		 2 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
3 *
f43dc23d 4 * Copyright (C) 2002 - 2011 Paul Mundt
3ea6bc3d 5 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
1da177e4
LT		 6 *
7 * based off of the old drivers/char/sh-sci.c by:
8 *
9 * Copyright (C) 1999, 2000 Niibe Yutaka
10 * Copyright (C) 2000 Sugioka Toshinobu
11 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
12 * Modified to support SecureEdge. David McCullough (2002)
13 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
d89ddd1c 14 * Removed SH7300 support (Jul 2007).
1da177e4
LT		 15 *
16 * This file is subject to the terms and conditions of the GNU General Public
17 * License. See the file "COPYING" in the main directory of this archive
18 * for more details.
19 */
0b3d4ef6
PM		 20#if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
21#define SUPPORT_SYSRQ
22#endif
1da177e4
LT		 23
24#undef DEBUG
25
8fb9631c
LP		 26#include <linux/clk.h>
27#include <linux/console.h>
28#include <linux/ctype.h>
29#include <linux/cpufreq.h>
30#include <linux/delay.h>
31#include <linux/dmaengine.h>
32#include <linux/dma-mapping.h>
33#include <linux/err.h>
1da177e4 34#include <linux/errno.h>
8fb9631c 35#include <linux/init.h>
1da177e4 36#include <linux/interrupt.h>
1da177e4 37#include <linux/ioport.h>
8fb9631c
LP		 38#include <linux/major.h>
39#include <linux/module.h>
1da177e4 40#include <linux/mm.h>
1da177e4 41#include <linux/notifier.h>
20bdcab8 42#include <linux/of.h>
8fb9631c 43#include <linux/platform_device.h>
5e50d2d6 44#include <linux/pm_runtime.h>
73a19e4c 45#include <linux/scatterlist.h>
8fb9631c
LP		 46#include <linux/serial.h>
47#include <linux/serial_sci.h>
48#include <linux/sh_dma.h>
5a0e3ad6 49#include <linux/slab.h>
8fb9631c
LP		 50#include <linux/string.h>
51#include <linux/sysrq.h>
52#include <linux/timer.h>
53#include <linux/tty.h>
54#include <linux/tty_flip.h>
85f094ec
PM		 55
56#ifdef CONFIG_SUPERH
1da177e4
LT		 57#include <asm/sh_bios.h>
58#endif
59
1da177e4
LT		 60#include "sh-sci.h"
61
89b5c1ab
LP		 62/* Offsets into the sci_port->irqs array */
63enum {
64 SCIx_ERI_IRQ,
65 SCIx_RXI_IRQ,
66 SCIx_TXI_IRQ,
67 SCIx_BRI_IRQ,
68 SCIx_NR_IRQS,
69
70 SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */
71};
72
73#define SCIx_IRQ_IS_MUXED(port) \
74 ((port)->irqs[SCIx_ERI_IRQ] == \
75 (port)->irqs[SCIx_RXI_IRQ]) || \
76 ((port)->irqs[SCIx_ERI_IRQ] && \
77 ((port)->irqs[SCIx_RXI_IRQ] < 0))
78
e108b2ca
PM		 79struct sci_port {
80 struct uart_port port;
81
ce6738b6
PM		 82 /* Platform configuration */
83 struct plat_sci_port *cfg;
2e0842a1 84 unsigned int overrun_reg;
75c249fd 85 unsigned int overrun_mask;
3ae988d9 86 unsigned int error_mask;
5da0f468 87 unsigned int error_clear;
ec09c5eb 88 unsigned int sampling_rate;
e4d6f911 89 resource_size_t reg_size;
e108b2ca 90
e108b2ca
PM		 91 /* Break timer */
92 struct timer_list break_timer;
93 int break_flag;
1534a3b3 94
c7ed1ab3
PM		 95 /* Function clock */
96 struct clk *fclk;
edad1f20 97
1fcc91a6 98 int irqs[SCIx_NR_IRQS];
9174fc8f
PM		 99 char *irqstr[SCIx_NR_IRQS];
100
73a19e4c
GL		 101 struct dma_chan *chan_tx;
102 struct dma_chan *chan_rx;
f43dc23d 103
73a19e4c 104#ifdef CONFIG_SERIAL_SH_SCI_DMA
73a19e4c
GL		 105 dma_cookie_t cookie_tx;
106 dma_cookie_t cookie_rx[2];
107 dma_cookie_t active_rx;
79904420
GU		 108 dma_addr_t tx_dma_addr;
109 unsigned int tx_dma_len;
73a19e4c 110 struct scatterlist sg_rx[2];
7b39d901 111 void *rx_buf[2];
73a19e4c 112 size_t buf_len_rx;
73a19e4c 113 struct work_struct work_tx;
73a19e4c 114 struct timer_list rx_timer;
3089f381 115 unsigned int rx_timeout;
73a19e4c 116#endif
e552de24 117
d535a230 118 struct notifier_block freq_transition;
e108b2ca
PM		 119};
120
e108b2ca 121#define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
b7a76e4b 122
e108b2ca
PM		 123static struct sci_port sci_ports[SCI_NPORTS];
124static struct uart_driver sci_uart_driver;
1da177e4 125
e7c98dc7
MT		 126static inline struct sci_port *
127to_sci_port(struct uart_port *uart)
128{
129 return container_of(uart, struct sci_port, port);
130}
131
61a6976b
PM		 132struct plat_sci_reg {
133 u8 offset, size;
134};
135
136/* Helper for invalidating specific entries of an inherited map. */
137#define sci_reg_invalid { .offset = 0, .size = 0 }
138
d3184e68 139static const struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = {
61a6976b
PM		 140 [SCIx_PROBE_REGTYPE] = {
141 [0 ... SCIx_NR_REGS - 1] = sci_reg_invalid,
142 },
143
144 /*
145 * Common SCI definitions, dependent on the port's regshift
146 * value.
147 */
148 [SCIx_SCI_REGTYPE] = {
149 [SCSMR] = { 0x00, 8 },
150 [SCBRR] = { 0x01, 8 },
151 [SCSCR] = { 0x02, 8 },
152 [SCxTDR] = { 0x03, 8 },
153 [SCxSR] = { 0x04, 8 },
154 [SCxRDR] = { 0x05, 8 },
155 [SCFCR] = sci_reg_invalid,
156 [SCFDR] = sci_reg_invalid,
157 [SCTFDR] = sci_reg_invalid,
158 [SCRFDR] = sci_reg_invalid,
159 [SCSPTR] = sci_reg_invalid,
160 [SCLSR] = sci_reg_invalid,
f303b364 161 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 162 [SCPCR] = sci_reg_invalid,
163 [SCPDR] = sci_reg_invalid,
b8bbd6b2
GU		 164 [SCDL] = sci_reg_invalid,
165 [SCCKS] = sci_reg_invalid,
61a6976b
PM		 166 },
167
168 /*
169 * Common definitions for legacy IrDA ports, dependent on
170 * regshift value.
171 */
172 [SCIx_IRDA_REGTYPE] = {
173 [SCSMR] = { 0x00, 8 },
174 [SCBRR] = { 0x01, 8 },
175 [SCSCR] = { 0x02, 8 },
176 [SCxTDR] = { 0x03, 8 },
177 [SCxSR] = { 0x04, 8 },
178 [SCxRDR] = { 0x05, 8 },
179 [SCFCR] = { 0x06, 8 },
180 [SCFDR] = { 0x07, 16 },
181 [SCTFDR] = sci_reg_invalid,
182 [SCRFDR] = sci_reg_invalid,
183 [SCSPTR] = sci_reg_invalid,
184 [SCLSR] = sci_reg_invalid,
f303b364 185 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 186 [SCPCR] = sci_reg_invalid,
187 [SCPDR] = sci_reg_invalid,
b8bbd6b2
GU		 188 [SCDL] = sci_reg_invalid,
189 [SCCKS] = sci_reg_invalid,
61a6976b
PM		 190 },
191
192 /*
193 * Common SCIFA definitions.
194 */
195 [SCIx_SCIFA_REGTYPE] = {
196 [SCSMR] = { 0x00, 16 },
197 [SCBRR] = { 0x04, 8 },
198 [SCSCR] = { 0x08, 16 },
199 [SCxTDR] = { 0x20, 8 },
200 [SCxSR] = { 0x14, 16 },
201 [SCxRDR] = { 0x24, 8 },
202 [SCFCR] = { 0x18, 16 },
203 [SCFDR] = { 0x1c, 16 },
204 [SCTFDR] = sci_reg_invalid,
205 [SCRFDR] = sci_reg_invalid,
206 [SCSPTR] = sci_reg_invalid,
207 [SCLSR] = sci_reg_invalid,
f303b364 208 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 209 [SCPCR] = { 0x30, 16 },
210 [SCPDR] = { 0x34, 16 },
b8bbd6b2
GU		 211 [SCDL] = sci_reg_invalid,
212 [SCCKS] = sci_reg_invalid,
61a6976b
PM		 213 },
214
215 /*
216 * Common SCIFB definitions.
217 */
218 [SCIx_SCIFB_REGTYPE] = {
219 [SCSMR] = { 0x00, 16 },
220 [SCBRR] = { 0x04, 8 },
221 [SCSCR] = { 0x08, 16 },
222 [SCxTDR] = { 0x40, 8 },
223 [SCxSR] = { 0x14, 16 },
224 [SCxRDR] = { 0x60, 8 },
225 [SCFCR] = { 0x18, 16 },
8c66d6d2
TY		 226 [SCFDR] = sci_reg_invalid,
227 [SCTFDR] = { 0x38, 16 },
228 [SCRFDR] = { 0x3c, 16 },
61a6976b
PM		 229 [SCSPTR] = sci_reg_invalid,
230 [SCLSR] = sci_reg_invalid,
f303b364 231 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 232 [SCPCR] = { 0x30, 16 },
233 [SCPDR] = { 0x34, 16 },
b8bbd6b2
GU		 234 [SCDL] = sci_reg_invalid,
235 [SCCKS] = sci_reg_invalid,
61a6976b
PM		 236 },
237
3af1f8a4
PE		 238 /*
239 * Common SH-2(A) SCIF definitions for ports with FIFO data
240 * count registers.
241 */
242 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = {
243 [SCSMR] = { 0x00, 16 },
244 [SCBRR] = { 0x04, 8 },
245 [SCSCR] = { 0x08, 16 },
246 [SCxTDR] = { 0x0c, 8 },
247 [SCxSR] = { 0x10, 16 },
248 [SCxRDR] = { 0x14, 8 },
249 [SCFCR] = { 0x18, 16 },
250 [SCFDR] = { 0x1c, 16 },
251 [SCTFDR] = sci_reg_invalid,
252 [SCRFDR] = sci_reg_invalid,
253 [SCSPTR] = { 0x20, 16 },
254 [SCLSR] = { 0x24, 16 },
f303b364 255 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 256 [SCPCR] = sci_reg_invalid,
257 [SCPDR] = sci_reg_invalid,
b8bbd6b2
GU		 258 [SCDL] = sci_reg_invalid,
259 [SCCKS] = sci_reg_invalid,
3af1f8a4
PE		 260 },
261
61a6976b
PM		 262 /*
263 * Common SH-3 SCIF definitions.
264 */
265 [SCIx_SH3_SCIF_REGTYPE] = {
266 [SCSMR] = { 0x00, 8 },
267 [SCBRR] = { 0x02, 8 },
268 [SCSCR] = { 0x04, 8 },
269 [SCxTDR] = { 0x06, 8 },
270 [SCxSR] = { 0x08, 16 },
271 [SCxRDR] = { 0x0a, 8 },
272 [SCFCR] = { 0x0c, 8 },
273 [SCFDR] = { 0x0e, 16 },
274 [SCTFDR] = sci_reg_invalid,
275 [SCRFDR] = sci_reg_invalid,
276 [SCSPTR] = sci_reg_invalid,
277 [SCLSR] = sci_reg_invalid,
f303b364 278 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 279 [SCPCR] = sci_reg_invalid,
280 [SCPDR] = sci_reg_invalid,
b8bbd6b2
GU		 281 [SCDL] = sci_reg_invalid,
282 [SCCKS] = sci_reg_invalid,
61a6976b
PM		 283 },
284
285 /*
286 * Common SH-4(A) SCIF(B) definitions.
287 */
288 [SCIx_SH4_SCIF_REGTYPE] = {
289 [SCSMR] = { 0x00, 16 },
290 [SCBRR] = { 0x04, 8 },
291 [SCSCR] = { 0x08, 16 },
292 [SCxTDR] = { 0x0c, 8 },
293 [SCxSR] = { 0x10, 16 },
294 [SCxRDR] = { 0x14, 8 },
295 [SCFCR] = { 0x18, 16 },
296 [SCFDR] = { 0x1c, 16 },
297 [SCTFDR] = sci_reg_invalid,
298 [SCRFDR] = sci_reg_invalid,
299 [SCSPTR] = { 0x20, 16 },
300 [SCLSR] = { 0x24, 16 },
f303b364 301 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 302 [SCPCR] = sci_reg_invalid,
303 [SCPDR] = sci_reg_invalid,
b8bbd6b2
GU		 304 [SCDL] = sci_reg_invalid,
305 [SCCKS] = sci_reg_invalid,
306 },
307
308 /*
309 * Common SCIF definitions for ports with a Baud Rate Generator for
310 * External Clock (BRG).
311 */
312 [SCIx_SH4_SCIF_BRG_REGTYPE] = {
313 [SCSMR] = { 0x00, 16 },
314 [SCBRR] = { 0x04, 8 },
315 [SCSCR] = { 0x08, 16 },
316 [SCxTDR] = { 0x0c, 8 },
317 [SCxSR] = { 0x10, 16 },
318 [SCxRDR] = { 0x14, 8 },
319 [SCFCR] = { 0x18, 16 },
320 [SCFDR] = { 0x1c, 16 },
321 [SCTFDR] = sci_reg_invalid,
322 [SCRFDR] = sci_reg_invalid,
323 [SCSPTR] = { 0x20, 16 },
324 [SCLSR] = { 0x24, 16 },
325 [HSSRR] = sci_reg_invalid,
326 [SCPCR] = sci_reg_invalid,
327 [SCPDR] = sci_reg_invalid,
328 [SCDL] = { 0x30, 16 },
329 [SCCKS] = { 0x34, 16 },
f303b364
UH		 330 },
331
332 /*
333 * Common HSCIF definitions.
334 */
335 [SCIx_HSCIF_REGTYPE] = {
336 [SCSMR] = { 0x00, 16 },
337 [SCBRR] = { 0x04, 8 },
338 [SCSCR] = { 0x08, 16 },
339 [SCxTDR] = { 0x0c, 8 },
340 [SCxSR] = { 0x10, 16 },
341 [SCxRDR] = { 0x14, 8 },
342 [SCFCR] = { 0x18, 16 },
343 [SCFDR] = { 0x1c, 16 },
344 [SCTFDR] = sci_reg_invalid,
345 [SCRFDR] = sci_reg_invalid,
346 [SCSPTR] = { 0x20, 16 },
347 [SCLSR] = { 0x24, 16 },
348 [HSSRR] = { 0x40, 16 },
c097abc3
GU		 349 [SCPCR] = sci_reg_invalid,
350 [SCPDR] = sci_reg_invalid,
b8bbd6b2
GU		 351 [SCDL] = { 0x30, 16 },
352 [SCCKS] = { 0x34, 16 },
61a6976b
PM		 353 },
354
355 /*
356 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR
357 * register.
358 */
359 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = {
360 [SCSMR] = { 0x00, 16 },
361 [SCBRR] = { 0x04, 8 },
362 [SCSCR] = { 0x08, 16 },
363 [SCxTDR] = { 0x0c, 8 },
364 [SCxSR] = { 0x10, 16 },
365 [SCxRDR] = { 0x14, 8 },
366 [SCFCR] = { 0x18, 16 },
367 [SCFDR] = { 0x1c, 16 },
368 [SCTFDR] = sci_reg_invalid,
369 [SCRFDR] = sci_reg_invalid,
370 [SCSPTR] = sci_reg_invalid,
371 [SCLSR] = { 0x24, 16 },
f303b364 372 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 373 [SCPCR] = sci_reg_invalid,
374 [SCPDR] = sci_reg_invalid,
b8bbd6b2
GU		 375 [SCDL] = sci_reg_invalid,
376 [SCCKS] = sci_reg_invalid,
61a6976b
PM		 377 },
378
379 /*
380 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data
381 * count registers.
382 */
383 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = {
384 [SCSMR] = { 0x00, 16 },
385 [SCBRR] = { 0x04, 8 },
386 [SCSCR] = { 0x08, 16 },
387 [SCxTDR] = { 0x0c, 8 },
388 [SCxSR] = { 0x10, 16 },
389 [SCxRDR] = { 0x14, 8 },
390 [SCFCR] = { 0x18, 16 },
391 [SCFDR] = { 0x1c, 16 },
392 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */
393 [SCRFDR] = { 0x20, 16 },
394 [SCSPTR] = { 0x24, 16 },
395 [SCLSR] = { 0x28, 16 },
f303b364 396 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 397 [SCPCR] = sci_reg_invalid,
398 [SCPDR] = sci_reg_invalid,
b8bbd6b2
GU		 399 [SCDL] = sci_reg_invalid,
400 [SCCKS] = sci_reg_invalid,
61a6976b
PM		 401 },
402
403 /*
404 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR
405 * registers.
406 */
407 [SCIx_SH7705_SCIF_REGTYPE] = {
408 [SCSMR] = { 0x00, 16 },
409 [SCBRR] = { 0x04, 8 },
410 [SCSCR] = { 0x08, 16 },
411 [SCxTDR] = { 0x20, 8 },
412 [SCxSR] = { 0x14, 16 },
413 [SCxRDR] = { 0x24, 8 },
414 [SCFCR] = { 0x18, 16 },
415 [SCFDR] = { 0x1c, 16 },
416 [SCTFDR] = sci_reg_invalid,
417 [SCRFDR] = sci_reg_invalid,
418 [SCSPTR] = sci_reg_invalid,
419 [SCLSR] = sci_reg_invalid,
f303b364 420 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 421 [SCPCR] = sci_reg_invalid,
422 [SCPDR] = sci_reg_invalid,
b8bbd6b2
GU		 423 [SCDL] = sci_reg_invalid,
424 [SCCKS] = sci_reg_invalid,
61a6976b
PM		 425 },
426};
427
72b294cf
PM		 428#define sci_getreg(up, offset) (sci_regmap[to_sci_port(up)->cfg->regtype] + offset)
429
61a6976b
PM		 430/*
431 * The "offset" here is rather misleading, in that it refers to an enum
432 * value relative to the port mapping rather than the fixed offset
433 * itself, which needs to be manually retrieved from the platform's
434 * register map for the given port.
435 */
436static unsigned int sci_serial_in(struct uart_port *p, int offset)
437{
d3184e68 438 const struct plat_sci_reg *reg = sci_getreg(p, offset);
61a6976b
PM		 439
440 if (reg->size == 8)
441 return ioread8(p->membase + (reg->offset << p->regshift));
442 else if (reg->size == 16)
443 return ioread16(p->membase + (reg->offset << p->regshift));
444 else
445 WARN(1, "Invalid register access\n");
446
447 return 0;
448}
449
450static void sci_serial_out(struct uart_port *p, int offset, int value)
451{
d3184e68 452 const struct plat_sci_reg *reg = sci_getreg(p, offset);
61a6976b
PM		 453
454 if (reg->size == 8)
455 iowrite8(value, p->membase + (reg->offset << p->regshift));
456 else if (reg->size == 16)
457 iowrite16(value, p->membase + (reg->offset << p->regshift));
458 else
459 WARN(1, "Invalid register access\n");
460}
461
61a6976b
PM		 462static int sci_probe_regmap(struct plat_sci_port *cfg)
463{
464 switch (cfg->type) {
465 case PORT_SCI:
466 cfg->regtype = SCIx_SCI_REGTYPE;
467 break;
468 case PORT_IRDA:
469 cfg->regtype = SCIx_IRDA_REGTYPE;
470 break;
471 case PORT_SCIFA:
472 cfg->regtype = SCIx_SCIFA_REGTYPE;
473 break;
474 case PORT_SCIFB:
475 cfg->regtype = SCIx_SCIFB_REGTYPE;
476 break;
477 case PORT_SCIF:
478 /*
479 * The SH-4 is a bit of a misnomer here, although that's
480 * where this particular port layout originated. This
481 * configuration (or some slight variation thereof)
482 * remains the dominant model for all SCIFs.
483 */
484 cfg->regtype = SCIx_SH4_SCIF_REGTYPE;
485 break;
f303b364
UH		 486 case PORT_HSCIF:
487 cfg->regtype = SCIx_HSCIF_REGTYPE;
488 break;
61a6976b 489 default:
6c13d5d2 490 pr_err("Can't probe register map for given port\n");
61a6976b
PM		 491 return -EINVAL;
492 }
493
494 return 0;
495}
496
23241d43
PM		 497static void sci_port_enable(struct sci_port *sci_port)
498{
499 if (!sci_port->port.dev)
500 return;
501
502 pm_runtime_get_sync(sci_port->port.dev);
503
b016b646 504 clk_prepare_enable(sci_port->fclk);
a9ec81f4 505 sci_port->port.uartclk = clk_get_rate(sci_port->fclk);
23241d43
PM		 506}
507
508static void sci_port_disable(struct sci_port *sci_port)
509{
510 if (!sci_port->port.dev)
511 return;
512
caec7038
LP		 513 /* Cancel the break timer to ensure that the timer handler will not try
514 * to access the hardware with clocks and power disabled. Reset the
515 * break flag to make the break debouncing state machine ready for the
516 * next break.
517 */
518 del_timer_sync(&sci_port->break_timer);
519 sci_port->break_flag = 0;
520
b016b646 521 clk_disable_unprepare(sci_port->fclk);
23241d43
PM		 522
523 pm_runtime_put_sync(sci_port->port.dev);
524}
525
e1910fcd
GU		 526static inline unsigned long port_rx_irq_mask(struct uart_port *port)
527{
528 /*
529 * Not all ports (such as SCIFA) will support REIE. Rather than
530 * special-casing the port type, we check the port initialization
531 * IRQ enable mask to see whether the IRQ is desired at all. If
532 * it's unset, it's logically inferred that there's no point in
533 * testing for it.
534 */
535 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE);
536}
537
538static void sci_start_tx(struct uart_port *port)
539{
540 struct sci_port *s = to_sci_port(port);
541 unsigned short ctrl;
542
543#ifdef CONFIG_SERIAL_SH_SCI_DMA
544 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
545 u16 new, scr = serial_port_in(port, SCSCR);
546 if (s->chan_tx)
547 new = scr | SCSCR_TDRQE;
548 else
549 new = scr & ~SCSCR_TDRQE;
550 if (new != scr)
551 serial_port_out(port, SCSCR, new);
552 }
553
554 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) &&
555 dma_submit_error(s->cookie_tx)) {
556 s->cookie_tx = 0;
557 schedule_work(&s->work_tx);
558 }
559#endif
560
561 if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
562 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
563 ctrl = serial_port_in(port, SCSCR);
564 serial_port_out(port, SCSCR, ctrl | SCSCR_TIE);
565 }
566}
567
568static void sci_stop_tx(struct uart_port *port)
569{
570 unsigned short ctrl;
571
572 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
573 ctrl = serial_port_in(port, SCSCR);
574
575 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
576 ctrl &= ~SCSCR_TDRQE;
577
578 ctrl &= ~SCSCR_TIE;
579
580 serial_port_out(port, SCSCR, ctrl);
581}
582
583static void sci_start_rx(struct uart_port *port)
584{
585 unsigned short ctrl;
586
587 ctrl = serial_port_in(port, SCSCR) | port_rx_irq_mask(port);
588
589 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
590 ctrl &= ~SCSCR_RDRQE;
591
592 serial_port_out(port, SCSCR, ctrl);
593}
594
595static void sci_stop_rx(struct uart_port *port)
596{
597 unsigned short ctrl;
598
599 ctrl = serial_port_in(port, SCSCR);
600
601 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
602 ctrl &= ~SCSCR_RDRQE;
603
604 ctrl &= ~port_rx_irq_mask(port);
605
606 serial_port_out(port, SCSCR, ctrl);
607}
608
a1b5b43f
GU		 609static void sci_clear_SCxSR(struct uart_port *port, unsigned int mask)
610{
611 if (port->type == PORT_SCI) {
612 /* Just store the mask */
613 serial_port_out(port, SCxSR, mask);
614 } else if (to_sci_port(port)->overrun_mask == SCIFA_ORER) {
615 /* SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721 */
616 /* Only clear the status bits we want to clear */
617 serial_port_out(port, SCxSR,
618 serial_port_in(port, SCxSR) & mask);
619 } else {
620 /* Store the mask, clear parity/framing errors */
621 serial_port_out(port, SCxSR, mask & ~(SCIF_FERC | SCIF_PERC));
622 }
623}
624
07d2a1a1 625#if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
1f6fd5c9
PM		 626
627#ifdef CONFIG_CONSOLE_POLL
07d2a1a1 628static int sci_poll_get_char(struct uart_port *port)
1da177e4 629{
1da177e4
LT		 630 unsigned short status;
631 int c;
632
e108b2ca 633 do {
b12bb29f 634 status = serial_port_in(port, SCxSR);
1da177e4 635 if (status & SCxSR_ERRORS(port)) {
a1b5b43f 636 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
1da177e4
LT		 637 continue;
638 }
3f255eb3
JW		 639 break;
640 } while (1);
641
642 if (!(status & SCxSR_RDxF(port)))
643 return NO_POLL_CHAR;
07d2a1a1 644
b12bb29f 645 c = serial_port_in(port, SCxRDR);
07d2a1a1 646
e7c98dc7 647 /* Dummy read */
b12bb29f 648 serial_port_in(port, SCxSR);
a1b5b43f 649 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1da177e4
LT		 650
651 return c;
652}
1f6fd5c9 653#endif
1da177e4 654
07d2a1a1 655static void sci_poll_put_char(struct uart_port *port, unsigned char c)
1da177e4 656{
1da177e4
LT		 657 unsigned short status;
658
1da177e4 659 do {
b12bb29f 660 status = serial_port_in(port, SCxSR);
1da177e4
LT		 661 } while (!(status & SCxSR_TDxE(port)));
662
b12bb29f 663 serial_port_out(port, SCxTDR, c);
a1b5b43f 664 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
1da177e4 665}
07d2a1a1 666#endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE */
1da177e4 667
61a6976b 668static void sci_init_pins(struct uart_port *port, unsigned int cflag)
1da177e4 669{
61a6976b 670 struct sci_port *s = to_sci_port(port);
d3184e68 671 const struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR;
1da177e4 672
61a6976b
PM		 673 /*
674 * Use port-specific handler if provided.
675 */
676 if (s->cfg->ops && s->cfg->ops->init_pins) {
677 s->cfg->ops->init_pins(port, cflag);
678 return;
1da177e4 679 }
41504c39 680
61a6976b
PM		 681 /*
682 * For the generic path SCSPTR is necessary. Bail out if that's
683 * unavailable, too.
684 */
685 if (!reg->size)
686 return;
41504c39 687
faf02f8f
PM		 688 if ((s->cfg->capabilities & SCIx_HAVE_RTSCTS) &&
689 ((!(cflag & CRTSCTS)))) {
690 unsigned short status;
691
b12bb29f 692 status = serial_port_in(port, SCSPTR);
faf02f8f
PM		 693 status &= ~SCSPTR_CTSIO;
694 status |= SCSPTR_RTSIO;
b12bb29f 695 serial_port_out(port, SCSPTR, status); /* Set RTS = 1 */
faf02f8f 696 }
d5701647 697}
e108b2ca 698
72b294cf 699static int sci_txfill(struct uart_port *port)
e108b2ca 700{
d3184e68 701 const struct plat_sci_reg *reg;
e108b2ca 702
72b294cf
PM		 703 reg = sci_getreg(port, SCTFDR);
704 if (reg->size)
63f7ad11 705 return serial_port_in(port, SCTFDR) & ((port->fifosize << 1) - 1);
c63847a3 706
72b294cf
PM		 707 reg = sci_getreg(port, SCFDR);
708 if (reg->size)
b12bb29f 709 return serial_port_in(port, SCFDR) >> 8;
d1d4b10c 710
b12bb29f 711 return !(serial_port_in(port, SCxSR) & SCI_TDRE);
e108b2ca
PM		 712}
713
73a19e4c
GL		 714static int sci_txroom(struct uart_port *port)
715{
72b294cf 716 return port->fifosize - sci_txfill(port);
73a19e4c
GL		 717}
718
719static int sci_rxfill(struct uart_port *port)
e108b2ca 720{
d3184e68 721 const struct plat_sci_reg *reg;
72b294cf
PM		 722
723 reg = sci_getreg(port, SCRFDR);
724 if (reg->size)
63f7ad11 725 return serial_port_in(port, SCRFDR) & ((port->fifosize << 1) - 1);
72b294cf
PM		 726
727 reg = sci_getreg(port, SCFDR);
728 if (reg->size)
b12bb29f 729 return serial_port_in(port, SCFDR) & ((port->fifosize << 1) - 1);
72b294cf 730
b12bb29f 731 return (serial_port_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
e108b2ca
PM		 732}
733
514820eb
PM		 734/*
735 * SCI helper for checking the state of the muxed port/RXD pins.
736 */
737static inline int sci_rxd_in(struct uart_port *port)
738{
739 struct sci_port *s = to_sci_port(port);
740
741 if (s->cfg->port_reg <= 0)
742 return 1;
743
0dd4d5cb 744 /* Cast for ARM damage */
e2afca69 745 return !!__raw_readb((void __iomem *)(uintptr_t)s->cfg->port_reg);
514820eb
PM		 746}
747
1da177e4
LT		 748/* ********************************************************************** *
749 * the interrupt related routines *
750 * ********************************************************************** */
751
752static void sci_transmit_chars(struct uart_port *port)
753{
ebd2c8f6 754 struct circ_buf *xmit = &port->state->xmit;
1da177e4 755 unsigned int stopped = uart_tx_stopped(port);
1da177e4
LT		 756 unsigned short status;
757 unsigned short ctrl;
e108b2ca 758 int count;
1da177e4 759
b12bb29f 760 status = serial_port_in(port, SCxSR);
1da177e4 761 if (!(status & SCxSR_TDxE(port))) {
b12bb29f 762 ctrl = serial_port_in(port, SCSCR);
e7c98dc7 763 if (uart_circ_empty(xmit))
8e698614 764 ctrl &= ~SCSCR_TIE;
e7c98dc7 765 else
8e698614 766 ctrl |= SCSCR_TIE;
b12bb29f 767 serial_port_out(port, SCSCR, ctrl);
1da177e4
LT		 768 return;
769 }
770
72b294cf 771 count = sci_txroom(port);
1da177e4
LT		 772
773 do {
774 unsigned char c;
775
776 if (port->x_char) {
777 c = port->x_char;
778 port->x_char = 0;
779 } else if (!uart_circ_empty(xmit) && !stopped) {
780 c = xmit->buf[xmit->tail];
781 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
782 } else {
783 break;
784 }
785
b12bb29f 786 serial_port_out(port, SCxTDR, c);
1da177e4
LT		 787
788 port->icount.tx++;
789 } while (--count > 0);
790
a1b5b43f 791 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
1da177e4
LT		 792
793 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
794 uart_write_wakeup(port);
795 if (uart_circ_empty(xmit)) {
b129a8cc 796 sci_stop_tx(port);
1da177e4 797 } else {
b12bb29f 798 ctrl = serial_port_in(port, SCSCR);
1da177e4 799
1a22f08d 800 if (port->type != PORT_SCI) {
b12bb29f 801 serial_port_in(port, SCxSR); /* Dummy read */
a1b5b43f 802 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
1da177e4 803 }
1da177e4 804
8e698614 805 ctrl |= SCSCR_TIE;
b12bb29f 806 serial_port_out(port, SCSCR, ctrl);
1da177e4
LT		 807 }
808}
809
810/* On SH3, SCIF may read end-of-break as a space->mark char */
e7c98dc7 811#define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); })
1da177e4 812
94c8b6db 813static void sci_receive_chars(struct uart_port *port)
1da177e4 814{
e7c98dc7 815 struct sci_port *sci_port = to_sci_port(port);
227434f8 816 struct tty_port *tport = &port->state->port;
1da177e4
LT		 817 int i, count, copied = 0;
818 unsigned short status;
33f0f88f 819 unsigned char flag;
1da177e4 820
b12bb29f 821 status = serial_port_in(port, SCxSR);
1da177e4
LT		 822 if (!(status & SCxSR_RDxF(port)))
823 return;
824
825 while (1) {
1da177e4 826 /* Don't copy more bytes than there is room for in the buffer */
227434f8 827 count = tty_buffer_request_room(tport, sci_rxfill(port));
1da177e4
LT		 828
829 /* If for any reason we can't copy more data, we're done! */
830 if (count == 0)
831 break;
832
833 if (port->type == PORT_SCI) {
b12bb29f 834 char c = serial_port_in(port, SCxRDR);
e7c98dc7
MT		 835 if (uart_handle_sysrq_char(port, c) ||
836 sci_port->break_flag)
1da177e4 837 count = 0;
e7c98dc7 838 else
92a19f9c 839 tty_insert_flip_char(tport, c, TTY_NORMAL);
1da177e4 840 } else {
e7c98dc7 841 for (i = 0; i < count; i++) {
b12bb29f 842 char c = serial_port_in(port, SCxRDR);
d97fbbed 843
b12bb29f 844 status = serial_port_in(port, SCxSR);
1da177e4
LT		 845#if defined(CONFIG_CPU_SH3)
846 /* Skip "chars" during break */
e108b2ca 847 if (sci_port->break_flag) {
1da177e4
LT		 848 if ((c == 0) &&
849 (status & SCxSR_FER(port))) {
850 count--; i--;
851 continue;
852 }
e108b2ca 853
1da177e4 854 /* Nonzero => end-of-break */
762c69e3 855 dev_dbg(port->dev, "debounce<%02x>\n", c);
e108b2ca
PM		 856 sci_port->break_flag = 0;
857
1da177e4
LT		 858 if (STEPFN(c)) {
859 count--; i--;
860 continue;
861 }
862 }
863#endif /* CONFIG_CPU_SH3 */
7d12e780 864 if (uart_handle_sysrq_char(port, c)) {
1da177e4
LT		 865 count--; i--;
866 continue;
867 }
868
869 /* Store data and status */
73a19e4c 870 if (status & SCxSR_FER(port)) {
33f0f88f 871 flag = TTY_FRAME;
d97fbbed 872 port->icount.frame++;
762c69e3 873 dev_notice(port->dev, "frame error\n");
73a19e4c 874 } else if (status & SCxSR_PER(port)) {
33f0f88f 875 flag = TTY_PARITY;
d97fbbed 876 port->icount.parity++;
762c69e3 877 dev_notice(port->dev, "parity error\n");
33f0f88f
AC		 878 } else
879 flag = TTY_NORMAL;
762c69e3 880
92a19f9c 881 tty_insert_flip_char(tport, c, flag);
1da177e4
LT		 882 }
883 }
884
b12bb29f 885 serial_port_in(port, SCxSR); /* dummy read */
a1b5b43f 886 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1da177e4 887
1da177e4
LT		 888 copied += count;
889 port->icount.rx += count;
890 }
891
892 if (copied) {
893 /* Tell the rest of the system the news. New characters! */
2e124b4a 894 tty_flip_buffer_push(tport);
1da177e4 895 } else {
b12bb29f 896 serial_port_in(port, SCxSR); /* dummy read */
a1b5b43f 897 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1da177e4
LT		 898 }
899}
900
901#define SCI_BREAK_JIFFIES (HZ/20)
94c8b6db
PM		 902
903/*
904 * The sci generates interrupts during the break,
1da177e4
LT		 905 * 1 per millisecond or so during the break period, for 9600 baud.
906 * So dont bother disabling interrupts.
907 * But dont want more than 1 break event.
908 * Use a kernel timer to periodically poll the rx line until
909 * the break is finished.
910 */
94c8b6db 911static inline void sci_schedule_break_timer(struct sci_port *port)
1da177e4 912{
bc9b3f5c 913 mod_timer(&port->break_timer, jiffies + SCI_BREAK_JIFFIES);
1da177e4 914}
94c8b6db 915
1da177e4
LT		 916/* Ensure that two consecutive samples find the break over. */
917static void sci_break_timer(unsigned long data)
918{
e108b2ca
PM		 919 struct sci_port *port = (struct sci_port *)data;
920
921 if (sci_rxd_in(&port->port) == 0) {
1da177e4 922 port->break_flag = 1;
e108b2ca
PM		 923 sci_schedule_break_timer(port);
924 } else if (port->break_flag == 1) {
1da177e4
LT		 925 /* break is over. */
926 port->break_flag = 2;
e108b2ca
PM		 927 sci_schedule_break_timer(port);
928 } else
929 port->break_flag = 0;
1da177e4
LT		 930}
931
94c8b6db 932static int sci_handle_errors(struct uart_port *port)
1da177e4
LT		 933{
934 int copied = 0;
b12bb29f 935 unsigned short status = serial_port_in(port, SCxSR);
92a19f9c 936 struct tty_port *tport = &port->state->port;
debf9507 937 struct sci_port *s = to_sci_port(port);
1da177e4 938
3ae988d9 939 /* Handle overruns */
75c249fd 940 if (status & s->overrun_mask) {
3ae988d9 941 port->icount.overrun++;
d97fbbed 942
3ae988d9
LP		 943 /* overrun error */
944 if (tty_insert_flip_char(tport, 0, TTY_OVERRUN))
945 copied++;
762c69e3 946
9b971cd2 947 dev_notice(port->dev, "overrun error\n");
1da177e4
LT		 948 }
949
e108b2ca 950 if (status & SCxSR_FER(port)) {
1da177e4
LT		 951 if (sci_rxd_in(port) == 0) {
952 /* Notify of BREAK */
e7c98dc7 953 struct sci_port *sci_port = to_sci_port(port);
e108b2ca
PM		 954
955 if (!sci_port->break_flag) {
d97fbbed
PM		 956 port->icount.brk++;
957
e108b2ca
PM		 958 sci_port->break_flag = 1;
959 sci_schedule_break_timer(sci_port);
960
1da177e4 961 /* Do sysrq handling. */
e108b2ca 962 if (uart_handle_break(port))
1da177e4 963 return 0;
762c69e3
PM		 964
965 dev_dbg(port->dev, "BREAK detected\n");
966
92a19f9c 967 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
e7c98dc7
MT		 968 copied++;
969 }
970
e108b2ca 971 } else {
1da177e4 972 /* frame error */
d97fbbed
PM		 973 port->icount.frame++;
974
92a19f9c 975 if (tty_insert_flip_char(tport, 0, TTY_FRAME))
33f0f88f 976 copied++;
762c69e3
PM		 977
978 dev_notice(port->dev, "frame error\n");
1da177e4
LT		 979 }
980 }
981
e108b2ca 982 if (status & SCxSR_PER(port)) {
1da177e4 983 /* parity error */
d97fbbed
PM		 984 port->icount.parity++;
985
92a19f9c 986 if (tty_insert_flip_char(tport, 0, TTY_PARITY))
e108b2ca 987 copied++;
762c69e3 988
9b971cd2 989 dev_notice(port->dev, "parity error\n");
1da177e4
LT		 990 }
991
33f0f88f 992 if (copied)
2e124b4a 993 tty_flip_buffer_push(tport);
1da177e4
LT		 994
995 return copied;
996}
997
94c8b6db 998static int sci_handle_fifo_overrun(struct uart_port *port)
d830fa45 999{
92a19f9c 1000 struct tty_port *tport = &port->state->port;
debf9507 1001 struct sci_port *s = to_sci_port(port);
d3184e68 1002 const struct plat_sci_reg *reg;
2e0842a1 1003 int copied = 0;
75c249fd 1004 u16 status;
d830fa45 1005
2e0842a1 1006 reg = sci_getreg(port, s->overrun_reg);
4b8c59a3 1007 if (!reg->size)
d830fa45
PM		 1008 return 0;
1009
2e0842a1 1010 status = serial_port_in(port, s->overrun_reg);
75c249fd
GU		 1011 if (status & s->overrun_mask) {
1012 status &= ~s->overrun_mask;
2e0842a1 1013 serial_port_out(port, s->overrun_reg, status);
d830fa45 1014
d97fbbed
PM		 1015 port->icount.overrun++;
1016
92a19f9c 1017 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
2e124b4a 1018 tty_flip_buffer_push(tport);
d830fa45 1019
51b31f1c 1020 dev_dbg(port->dev, "overrun error\n");
d830fa45
PM		 1021 copied++;
1022 }
1023
1024 return copied;
1025}
1026
94c8b6db 1027static int sci_handle_breaks(struct uart_port *port)
1da177e4
LT		 1028{
1029 int copied = 0;
b12bb29f 1030 unsigned short status = serial_port_in(port, SCxSR);
92a19f9c 1031 struct tty_port *tport = &port->state->port;
a5660ada 1032 struct sci_port *s = to_sci_port(port);
1da177e4 1033
0b3d4ef6
PM		 1034 if (uart_handle_break(port))
1035 return 0;
1036
b7a76e4b 1037 if (!s->break_flag && status & SCxSR_BRK(port)) {
1da177e4
LT		 1038#if defined(CONFIG_CPU_SH3)
1039 /* Debounce break */
1040 s->break_flag = 1;
1041#endif
d97fbbed
PM		 1042
1043 port->icount.brk++;
1044
1da177e4 1045 /* Notify of BREAK */
92a19f9c 1046 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
33f0f88f 1047 copied++;
762c69e3
PM		 1048
1049 dev_dbg(port->dev, "BREAK detected\n");
1da177e4
LT		 1050 }
1051
33f0f88f 1052 if (copied)
2e124b4a 1053 tty_flip_buffer_push(tport);
e108b2ca 1054
d830fa45
PM		 1055 copied += sci_handle_fifo_overrun(port);
1056
1da177e4
LT		 1057 return copied;
1058}
1059
73a19e4c 1060#ifdef CONFIG_SERIAL_SH_SCI_DMA
e1910fcd
GU		 1061static void sci_dma_tx_complete(void *arg)
1062{
1063 struct sci_port *s = arg;
1064 struct uart_port *port = &s->port;
1065 struct circ_buf *xmit = &port->state->xmit;
1066 unsigned long flags;
73a19e4c 1067
e1910fcd 1068 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
73a19e4c 1069
e1910fcd 1070 spin_lock_irqsave(&port->lock, flags);
73a19e4c 1071
e1910fcd
GU		 1072 xmit->tail += s->tx_dma_len;
1073 xmit->tail &= UART_XMIT_SIZE - 1;
73a19e4c 1074
e1910fcd 1075 port->icount.tx += s->tx_dma_len;
1da177e4 1076
e1910fcd
GU		 1077 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1078 uart_write_wakeup(port);
1da177e4 1079
e1910fcd
GU		 1080 if (!uart_circ_empty(xmit)) {
1081 s->cookie_tx = 0;
1082 schedule_work(&s->work_tx);
1083 } else {
1084 s->cookie_tx = -EINVAL;
1085 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1086 u16 ctrl = serial_port_in(port, SCSCR);
1087 serial_port_out(port, SCSCR, ctrl & ~SCSCR_TIE);
1088 }
1089 }
1da177e4 1090
fd78a76a 1091 spin_unlock_irqrestore(&port->lock, flags);
1da177e4
LT		 1092}
1093
e1910fcd
GU		 1094/* Locking: called with port lock held */
1095static int sci_dma_rx_push(struct sci_port *s, void *buf, size_t count)
1da177e4 1096{
e1910fcd
GU		 1097 struct uart_port *port = &s->port;
1098 struct tty_port *tport = &port->state->port;
1099 int copied;
1da177e4 1100
e1910fcd
GU		 1101 copied = tty_insert_flip_string(tport, buf, count);
1102 if (copied < count) {
1103 dev_warn(port->dev, "Rx overrun: dropping %zu bytes\n",
1104 count - copied);
1105 port->icount.buf_overrun++;
1da177e4
LT		 1106 }
1107
e1910fcd 1108 port->icount.rx += copied;
1da177e4 1109
e1910fcd 1110 return copied;
1da177e4
LT		 1111}
1112
e1910fcd 1113static int sci_dma_rx_find_active(struct sci_port *s)
1da177e4 1114{
e1910fcd 1115 unsigned int i;
1da177e4 1116
e1910fcd
GU		 1117 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++)
1118 if (s->active_rx == s->cookie_rx[i])
1119 return i;
1da177e4 1120
e1910fcd
GU		 1121 dev_err(s->port.dev, "%s: Rx cookie %d not found!\n", __func__,
1122 s->active_rx);
1123 return -1;
1da177e4
LT		 1124}
1125
e1910fcd 1126static void sci_rx_dma_release(struct sci_port *s, bool enable_pio)
f43dc23d 1127{
e1910fcd
GU		 1128 struct dma_chan *chan = s->chan_rx;
1129 struct uart_port *port = &s->port;
1130 unsigned long flags;
1131
1132 spin_lock_irqsave(&port->lock, flags);
1133 s->chan_rx = NULL;
1134 s->cookie_rx[0] = s->cookie_rx[1] = -EINVAL;
1135 spin_unlock_irqrestore(&port->lock, flags);
1136 dmaengine_terminate_all(chan);
1137 dma_free_coherent(chan->device->dev, s->buf_len_rx * 2, s->rx_buf[0],
1138 sg_dma_address(&s->sg_rx[0]));
1139 dma_release_channel(chan);
1140 if (enable_pio)
1141 sci_start_rx(port);
f43dc23d
PM		 1142}
1143
e1910fcd 1144static void sci_dma_rx_complete(void *arg)
1da177e4 1145{
e1910fcd 1146 struct sci_port *s = arg;
1d3db608 1147 struct dma_chan *chan = s->chan_rx;
e1910fcd 1148 struct uart_port *port = &s->port;
67f462b0 1149 struct dma_async_tx_descriptor *desc;
e1910fcd
GU		 1150 unsigned long flags;
1151 int active, count = 0;
1da177e4 1152
e1910fcd
GU		 1153 dev_dbg(port->dev, "%s(%d) active cookie %d\n", __func__, port->line,
1154 s->active_rx);
cb772fe7 1155
e1910fcd 1156 spin_lock_irqsave(&port->lock, flags);
1da177e4 1157
e1910fcd
GU		 1158 active = sci_dma_rx_find_active(s);
1159 if (active >= 0)
1160 count = sci_dma_rx_push(s, s->rx_buf[active], s->buf_len_rx);
f43dc23d 1161
e1910fcd 1162 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
f43dc23d 1163
e1910fcd
GU		 1164 if (count)
1165 tty_flip_buffer_push(&port->state->port);
8b6ff84c 1166
67f462b0
GU		 1167 desc = dmaengine_prep_slave_sg(s->chan_rx, &s->sg_rx[active], 1,
1168 DMA_DEV_TO_MEM,
1169 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1170 if (!desc)
1171 goto fail;
1172
1173 desc->callback = sci_dma_rx_complete;
1174 desc->callback_param = s;
1175 s->cookie_rx[active] = dmaengine_submit(desc);
1176 if (dma_submit_error(s->cookie_rx[active]))
1177 goto fail;
1178
1179 s->active_rx = s->cookie_rx[!active];
1180
1d3db608
MHF		 1181 dma_async_issue_pending(chan);
1182
67f462b0
GU		 1183 dev_dbg(port->dev, "%s: cookie %d #%d, new active cookie %d\n",
1184 __func__, s->cookie_rx[active], active, s->active_rx);
1185 spin_unlock_irqrestore(&port->lock, flags);
1186 return;
1187
1188fail:
1189 spin_unlock_irqrestore(&port->lock, flags);
1190 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
1191 sci_rx_dma_release(s, true);
1da177e4
LT		 1192}
1193
e1910fcd 1194static void sci_tx_dma_release(struct sci_port *s, bool enable_pio)
1da177e4 1195{
e1910fcd
GU		 1196 struct dma_chan *chan = s->chan_tx;
1197 struct uart_port *port = &s->port;
e552de24 1198 unsigned long flags;
1da177e4 1199
e1910fcd
GU		 1200 spin_lock_irqsave(&port->lock, flags);
1201 s->chan_tx = NULL;
1202 s->cookie_tx = -EINVAL;
1203 spin_unlock_irqrestore(&port->lock, flags);
1204 dmaengine_terminate_all(chan);
1205 dma_unmap_single(chan->device->dev, s->tx_dma_addr, UART_XMIT_SIZE,
1206 DMA_TO_DEVICE);
1207 dma_release_channel(chan);
1208 if (enable_pio)
1209 sci_start_tx(port);
1210}
d535a230 1211
e1910fcd
GU		 1212static void sci_submit_rx(struct sci_port *s)
1213{
1214 struct dma_chan *chan = s->chan_rx;
1215 int i;
073e84c9 1216
e1910fcd
GU		 1217 for (i = 0; i < 2; i++) {
1218 struct scatterlist *sg = &s->sg_rx[i];
1219 struct dma_async_tx_descriptor *desc;
1da177e4 1220
e1910fcd
GU		 1221 desc = dmaengine_prep_slave_sg(chan,
1222 sg, 1, DMA_DEV_TO_MEM,
1223 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1224 if (!desc)
1225 goto fail;
501b825d 1226
e1910fcd
GU		 1227 desc->callback = sci_dma_rx_complete;
1228 desc->callback_param = s;
1229 s->cookie_rx[i] = dmaengine_submit(desc);
1230 if (dma_submit_error(s->cookie_rx[i]))
1231 goto fail;
9174fc8f 1232
e1910fcd
GU		 1233 dev_dbg(s->port.dev, "%s(): cookie %d to #%d\n", __func__,
1234 s->cookie_rx[i], i);
1235 }
9174fc8f 1236
e1910fcd 1237 s->active_rx = s->cookie_rx[0];
9174fc8f 1238
e1910fcd
GU		 1239 dma_async_issue_pending(chan);
1240 return;
9174fc8f 1241
e1910fcd
GU		 1242fail:
1243 if (i)
1244 dmaengine_terminate_all(chan);
1245 for (i = 0; i < 2; i++)
1246 s->cookie_rx[i] = -EINVAL;
1247 s->active_rx = -EINVAL;
1248 dev_warn(s->port.dev, "Failed to re-start Rx DMA, using PIO\n");
1249 sci_rx_dma_release(s, true);
1250}
9174fc8f 1251
e1910fcd 1252static void work_fn_tx(struct work_struct *work)
1da177e4 1253{
e1910fcd
GU		 1254 struct sci_port *s = container_of(work, struct sci_port, work_tx);
1255 struct dma_async_tx_descriptor *desc;
1256 struct dma_chan *chan = s->chan_tx;
1257 struct uart_port *port = &s->port;
1258 struct circ_buf *xmit = &port->state->xmit;
1259 dma_addr_t buf;
1da177e4 1260
9174fc8f 1261 /*
e1910fcd
GU		 1262 * DMA is idle now.
1263 * Port xmit buffer is already mapped, and it is one page... Just adjust
1264 * offsets and lengths. Since it is a circular buffer, we have to
1265 * transmit till the end, and then the rest. Take the port lock to get a
1266 * consistent xmit buffer state.
9174fc8f 1267 */
e1910fcd
GU		 1268 spin_lock_irq(&port->lock);
1269 buf = s->tx_dma_addr + (xmit->tail & (UART_XMIT_SIZE - 1));
1270 s->tx_dma_len = min_t(unsigned int,
1271 CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE),
1272 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE));
1273 spin_unlock_irq(&port->lock);
0e8963de 1274
e1910fcd
GU		 1275 desc = dmaengine_prep_slave_single(chan, buf, s->tx_dma_len,
1276 DMA_MEM_TO_DEV,
1277 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1278 if (!desc) {
1279 dev_warn(port->dev, "Failed preparing Tx DMA descriptor\n");
1280 /* switch to PIO */
1281 sci_tx_dma_release(s, true);
1282 return;
1283 }
0e8963de 1284
e1910fcd
GU		 1285 dma_sync_single_for_device(chan->device->dev, buf, s->tx_dma_len,
1286 DMA_TO_DEVICE);
1da177e4 1287
e1910fcd
GU		 1288 spin_lock_irq(&port->lock);
1289 desc->callback = sci_dma_tx_complete;
1290 desc->callback_param = s;
1291 spin_unlock_irq(&port->lock);
1292 s->cookie_tx = dmaengine_submit(desc);
1293 if (dma_submit_error(s->cookie_tx)) {
1294 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
1295 /* switch to PIO */
1296 sci_tx_dma_release(s, true);
1297 return;
1da177e4 1298 }
1da177e4 1299
e1910fcd
GU		 1300 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n",
1301 __func__, xmit->buf, xmit->tail, xmit->head, s->cookie_tx);
73a19e4c 1302
e1910fcd 1303 dma_async_issue_pending(chan);
1da177e4
LT		 1304}
1305
e1910fcd 1306static void rx_timer_fn(unsigned long arg)
1da177e4 1307{
e1910fcd 1308 struct sci_port *s = (struct sci_port *)arg;
e7327c09 1309 struct dma_chan *chan = s->chan_rx;
e1910fcd 1310 struct uart_port *port = &s->port;
67f462b0
GU		 1311 struct dma_tx_state state;
1312 enum dma_status status;
1313 unsigned long flags;
1314 unsigned int read;
1315 int active, count;
1316 u16 scr;
1317
1318 spin_lock_irqsave(&port->lock, flags);
e1910fcd 1319
67f462b0 1320 dev_dbg(port->dev, "DMA Rx timed out\n");
67f462b0
GU		 1321
1322 active = sci_dma_rx_find_active(s);
1323 if (active < 0) {
1324 spin_unlock_irqrestore(&port->lock, flags);
1325 return;
1326 }
1327
1328 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
3b963042 1329 if (status == DMA_COMPLETE) {
67f462b0
GU		 1330 dev_dbg(port->dev, "Cookie %d #%d has already completed\n",
1331 s->active_rx, active);
3b963042
MHF		 1332 spin_unlock_irqrestore(&port->lock, flags);
1333
1334 /* Let packet complete handler take care of the packet */
1335 return;
1336 }
67f462b0 1337
e7327c09
MHF		 1338 dmaengine_pause(chan);
1339
1340 /*
1341 * sometimes DMA transfer doesn't stop even if it is stopped and
1342 * data keeps on coming until transaction is complete so check
1343 * for DMA_COMPLETE again
1344 * Let packet complete handler take care of the packet
1345 */
1346 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
1347 if (status == DMA_COMPLETE) {
1348 spin_unlock_irqrestore(&port->lock, flags);
1349 dev_dbg(port->dev, "Transaction complete after DMA engine was stopped");
1350 return;
1351 }
1352
67f462b0
GU		 1353 /* Handle incomplete DMA receive */
1354 dmaengine_terminate_all(s->chan_rx);
1355 read = sg_dma_len(&s->sg_rx[active]) - state.residue;
1356 dev_dbg(port->dev, "Read %u bytes with cookie %d\n", read,
1357 s->active_rx);
1358
1359 if (read) {
1360 count = sci_dma_rx_push(s, s->rx_buf[active], read);
1361 if (count)
1362 tty_flip_buffer_push(&port->state->port);
1363 }
1364
756981be
GU		 1365 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1366 sci_submit_rx(s);
371cfed3
MHF		 1367
1368 /* Direct new serial port interrupts back to CPU */
1369 scr = serial_port_in(port, SCSCR);
1370 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1371 scr &= ~SCSCR_RDRQE;
1372 enable_irq(s->irqs[SCIx_RXI_IRQ]);
1373 }
1374 serial_port_out(port, SCSCR, scr | SCSCR_RIE);
1375
1376 spin_unlock_irqrestore(&port->lock, flags);
1da177e4
LT		 1377}
1378
ff441129
GU		 1379static struct dma_chan *sci_request_dma_chan(struct uart_port *port,
1380 enum dma_transfer_direction dir,
1381 unsigned int id)
1382{
1383 dma_cap_mask_t mask;
1384 struct dma_chan *chan;
1385 struct dma_slave_config cfg;
1386 int ret;
1387
1388 dma_cap_zero(mask);
1389 dma_cap_set(DMA_SLAVE, mask);
1390
1391 chan = dma_request_slave_channel_compat(mask, shdma_chan_filter,
1392 (void *)(unsigned long)id, port->dev,
1393 dir == DMA_MEM_TO_DEV ? "tx" : "rx");
1394 if (!chan) {
1395 dev_warn(port->dev,
1396 "dma_request_slave_channel_compat failed\n");
1397 return NULL;
1398 }
1399
1400 memset(&cfg, 0, sizeof(cfg));
1401 cfg.direction = dir;
1402 if (dir == DMA_MEM_TO_DEV) {
1403 cfg.dst_addr = port->mapbase +
1404 (sci_getreg(port, SCxTDR)->offset << port->regshift);
1405 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1406 } else {
1407 cfg.src_addr = port->mapbase +
1408 (sci_getreg(port, SCxRDR)->offset << port->regshift);
1409 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1410 }
1411
1412 ret = dmaengine_slave_config(chan, &cfg);
1413 if (ret) {
1414 dev_warn(port->dev, "dmaengine_slave_config failed %d\n", ret);
1415 dma_release_channel(chan);
1416 return NULL;
1417 }
1418
1419 return chan;
1420}
1421
e1910fcd 1422static void sci_request_dma(struct uart_port *port)
73a19e4c 1423{
e1910fcd 1424 struct sci_port *s = to_sci_port(port);
e1910fcd 1425 struct dma_chan *chan;
73a19e4c 1426
e1910fcd 1427 dev_dbg(port->dev, "%s: port %d\n", __func__, port->line);
73a19e4c 1428
ff441129
GU		 1429 if (!port->dev->of_node &&
1430 (s->cfg->dma_slave_tx <= 0 || s->cfg->dma_slave_rx <= 0))
e1910fcd 1431 return;
73a19e4c 1432
e1910fcd 1433 s->cookie_tx = -EINVAL;
ff441129 1434 chan = sci_request_dma_chan(port, DMA_MEM_TO_DEV, s->cfg->dma_slave_tx);
e1910fcd
GU		 1435 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
1436 if (chan) {
1437 s->chan_tx = chan;
1438 /* UART circular tx buffer is an aligned page. */
1439 s->tx_dma_addr = dma_map_single(chan->device->dev,
1440 port->state->xmit.buf,
1441 UART_XMIT_SIZE,
1442 DMA_TO_DEVICE);
1443 if (dma_mapping_error(chan->device->dev, s->tx_dma_addr)) {
1444 dev_warn(port->dev, "Failed mapping Tx DMA descriptor\n");
1445 dma_release_channel(chan);
1446 s->chan_tx = NULL;
1447 } else {
1448 dev_dbg(port->dev, "%s: mapped %lu@%p to %pad\n",
1449 __func__, UART_XMIT_SIZE,
1450 port->state->xmit.buf, &s->tx_dma_addr);
49d4bcad 1451 }
e1910fcd
GU		 1452
1453 INIT_WORK(&s->work_tx, work_fn_tx);
3089f381
GL		 1454 }
1455
ff441129 1456 chan = sci_request_dma_chan(port, DMA_DEV_TO_MEM, s->cfg->dma_slave_rx);
e1910fcd
GU		 1457 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan);
1458 if (chan) {
1459 unsigned int i;
1460 dma_addr_t dma;
1461 void *buf;
73a19e4c 1462
e1910fcd 1463 s->chan_rx = chan;
73a19e4c 1464
e1910fcd
GU		 1465 s->buf_len_rx = 2 * max_t(size_t, 16, port->fifosize);
1466 buf = dma_alloc_coherent(chan->device->dev, s->buf_len_rx * 2,
1467 &dma, GFP_KERNEL);
1468 if (!buf) {
1469 dev_warn(port->dev,
1470 "Failed to allocate Rx dma buffer, using PIO\n");
1471 dma_release_channel(chan);
1472 s->chan_rx = NULL;
e1910fcd
GU		 1473 return;
1474 }
73a19e4c 1475
e1910fcd
GU		 1476 for (i = 0; i < 2; i++) {
1477 struct scatterlist *sg = &s->sg_rx[i];
0533502d 1478
e1910fcd
GU		 1479 sg_init_table(sg, 1);
1480 s->rx_buf[i] = buf;
1481 sg_dma_address(sg) = dma;
1482 sg->length = s->buf_len_rx;
0533502d 1483
e1910fcd
GU		 1484 buf += s->buf_len_rx;
1485 dma += s->buf_len_rx;
1486 }
1487
e1910fcd
GU		 1488 setup_timer(&s->rx_timer, rx_timer_fn, (unsigned long)s);
1489
756981be
GU		 1490 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1491 sci_submit_rx(s);
e1910fcd 1492 }
0533502d
GU		 1493}
1494
e1910fcd 1495static void sci_free_dma(struct uart_port *port)
73a19e4c 1496{
e1910fcd 1497 struct sci_port *s = to_sci_port(port);
73a19e4c 1498
e1910fcd
GU		 1499 if (s->chan_tx)
1500 sci_tx_dma_release(s, false);
1501 if (s->chan_rx)
1502 sci_rx_dma_release(s, false);
1503}
1504#else
1505static inline void sci_request_dma(struct uart_port *port)
1506{
1507}
73a19e4c 1508
e1910fcd
GU		 1509static inline void sci_free_dma(struct uart_port *port)
1510{
1511}
1512#endif
73a19e4c 1513
e1910fcd
GU		 1514static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
1515{
1516#ifdef CONFIG_SERIAL_SH_SCI_DMA
1517 struct uart_port *port = ptr;
1518 struct sci_port *s = to_sci_port(port);
73a19e4c 1519
e1910fcd
GU		 1520 if (s->chan_rx) {
1521 u16 scr = serial_port_in(port, SCSCR);
1522 u16 ssr = serial_port_in(port, SCxSR);
73a19e4c 1523
e1910fcd
GU		 1524 /* Disable future Rx interrupts */
1525 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1526 disable_irq_nosync(irq);
1527 scr |= SCSCR_RDRQE;
1528 } else {
1529 scr &= ~SCSCR_RIE;
756981be 1530 sci_submit_rx(s);
e1910fcd
GU		 1531 }
1532 serial_port_out(port, SCSCR, scr);
1533 /* Clear current interrupt */
1534 serial_port_out(port, SCxSR,
1535 ssr & ~(SCIF_DR | SCxSR_RDxF(port)));
1536 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u jiffies\n",
1537 jiffies, s->rx_timeout);
1538 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
73a19e4c 1539
e1910fcd
GU		 1540 return IRQ_HANDLED;
1541 }
1542#endif
73a19e4c 1543
e1910fcd
GU		 1544 /* I think sci_receive_chars has to be called irrespective
1545 * of whether the I_IXOFF is set, otherwise, how is the interrupt
1546 * to be disabled?
1547 */
1548 sci_receive_chars(ptr);
1549
1550 return IRQ_HANDLED;
73a19e4c
GL		 1551}
1552
e1910fcd 1553static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
73a19e4c 1554{
e1910fcd 1555 struct uart_port *port = ptr;
04928b79 1556 unsigned long flags;
73a19e4c 1557
04928b79 1558 spin_lock_irqsave(&port->lock, flags);
e1910fcd 1559 sci_transmit_chars(port);
04928b79 1560 spin_unlock_irqrestore(&port->lock, flags);
e1910fcd
GU		 1561
1562 return IRQ_HANDLED;
73a19e4c
GL		 1563}
1564
e1910fcd 1565static irqreturn_t sci_er_interrupt(int irq, void *ptr)
73a19e4c 1566{
e1910fcd
GU		 1567 struct uart_port *port = ptr;
1568 struct sci_port *s = to_sci_port(port);
73a19e4c 1569
e1910fcd
GU		 1570 /* Handle errors */
1571 if (port->type == PORT_SCI) {
1572 if (sci_handle_errors(port)) {
1573 /* discard character in rx buffer */
1574 serial_port_in(port, SCxSR);
1575 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1576 }
1577 } else {
1578 sci_handle_fifo_overrun(port);
1579 if (!s->chan_rx)
1580 sci_receive_chars(ptr);
1581 }
1582
1583 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
1584
1585 /* Kick the transmission */
1586 if (!s->chan_tx)
1587 sci_tx_interrupt(irq, ptr);
1588
1589 return IRQ_HANDLED;
73a19e4c
GL		 1590}
1591
e1910fcd 1592static irqreturn_t sci_br_interrupt(int irq, void *ptr)
73a19e4c 1593{
e1910fcd 1594 struct uart_port *port = ptr;
73a19e4c 1595
e1910fcd
GU		 1596 /* Handle BREAKs */
1597 sci_handle_breaks(port);
1598 sci_clear_SCxSR(port, SCxSR_BREAK_CLEAR(port));
73a19e4c 1599
e1910fcd
GU		 1600 return IRQ_HANDLED;
1601}
73a19e4c 1602
e1910fcd
GU		 1603static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
1604{
1605 unsigned short ssr_status, scr_status, err_enabled, orer_status = 0;
1606 struct uart_port *port = ptr;
1607 struct sci_port *s = to_sci_port(port);
1608 irqreturn_t ret = IRQ_NONE;
73a19e4c 1609
e1910fcd
GU		 1610 ssr_status = serial_port_in(port, SCxSR);
1611 scr_status = serial_port_in(port, SCSCR);
1612 if (s->overrun_reg == SCxSR)
1613 orer_status = ssr_status;
1614 else {
1615 if (sci_getreg(port, s->overrun_reg)->size)
1616 orer_status = serial_port_in(port, s->overrun_reg);
73a19e4c
GL		 1617 }
1618
e1910fcd 1619 err_enabled = scr_status & port_rx_irq_mask(port);
73a19e4c 1620
e1910fcd
GU		 1621 /* Tx Interrupt */
1622 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) &&
1623 !s->chan_tx)
1624 ret = sci_tx_interrupt(irq, ptr);
658daa95 1625
e1910fcd
GU		 1626 /*
1627 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF /
1628 * DR flags
1629 */
1630 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&
1631 (scr_status & SCSCR_RIE))
1632 ret = sci_rx_interrupt(irq, ptr);
73a19e4c 1633
e1910fcd
GU		 1634 /* Error Interrupt */
1635 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
1636 ret = sci_er_interrupt(irq, ptr);
73a19e4c 1637
e1910fcd
GU		 1638 /* Break Interrupt */
1639 if ((ssr_status & SCxSR_BRK(port)) && err_enabled)
1640 ret = sci_br_interrupt(irq, ptr);
1641
1642 /* Overrun Interrupt */
1643 if (orer_status & s->overrun_mask) {
1644 sci_handle_fifo_overrun(port);
1645 ret = IRQ_HANDLED;
73a19e4c 1646 }
73a19e4c 1647
e1910fcd
GU		 1648 return ret;
1649}
73a19e4c 1650
e1910fcd
GU		 1651/*
1652 * Here we define a transition notifier so that we can update all of our
1653 * ports' baud rate when the peripheral clock changes.
1654 */
1655static int sci_notifier(struct notifier_block *self,
1656 unsigned long phase, void *p)
1657{
1658 struct sci_port *sci_port;
1659 unsigned long flags;
73a19e4c 1660
e1910fcd 1661 sci_port = container_of(self, struct sci_port, freq_transition);
73a19e4c 1662
e1910fcd
GU		 1663 if (phase == CPUFREQ_POSTCHANGE) {
1664 struct uart_port *port = &sci_port->port;
73a19e4c 1665
e1910fcd 1666 spin_lock_irqsave(&port->lock, flags);
a9ec81f4 1667 port->uartclk = clk_get_rate(sci_port->fclk);
e1910fcd 1668 spin_unlock_irqrestore(&port->lock, flags);
73a19e4c
GL		 1669 }
1670
e1910fcd
GU		 1671 return NOTIFY_OK;
1672}
73a19e4c 1673
e1910fcd
GU		 1674static const struct sci_irq_desc {
1675 const char *desc;
1676 irq_handler_t handler;
1677} sci_irq_desc[] = {
1678 /*
1679 * Split out handlers, the default case.
1680 */
1681 [SCIx_ERI_IRQ] = {
1682 .desc = "rx err",
1683 .handler = sci_er_interrupt,
1684 },
3089f381 1685
e1910fcd
GU		 1686 [SCIx_RXI_IRQ] = {
1687 .desc = "rx full",
1688 .handler = sci_rx_interrupt,
1689 },
47aceb92 1690
e1910fcd
GU		 1691 [SCIx_TXI_IRQ] = {
1692 .desc = "tx empty",
1693 .handler = sci_tx_interrupt,
1694 },
73a19e4c 1695
e1910fcd
GU		 1696 [SCIx_BRI_IRQ] = {
1697 .desc = "break",
1698 .handler = sci_br_interrupt,
1699 },
73a19e4c
GL		 1700
1701 /*
e1910fcd 1702 * Special muxed handler.
73a19e4c 1703 */
e1910fcd
GU		 1704 [SCIx_MUX_IRQ] = {
1705 .desc = "mux",
1706 .handler = sci_mpxed_interrupt,
1707 },
1708};
73a19e4c 1709
e1910fcd
GU		 1710static int sci_request_irq(struct sci_port *port)
1711{
1712 struct uart_port *up = &port->port;
1713 int i, j, ret = 0;
73a19e4c 1714
e1910fcd
GU		 1715 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) {
1716 const struct sci_irq_desc *desc;
1717 int irq;
73a19e4c 1718
e1910fcd
GU		 1719 if (SCIx_IRQ_IS_MUXED(port)) {
1720 i = SCIx_MUX_IRQ;
1721 irq = up->irq;
1722 } else {
1723 irq = port->irqs[i];
1724
1725 /*
1726 * Certain port types won't support all of the
1727 * available interrupt sources.
1728 */
1729 if (unlikely(irq < 0))
1730 continue;
1731 }
1732
1733 desc = sci_irq_desc + i;
1734 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s",
1735 dev_name(up->dev), desc->desc);
1736 if (!port->irqstr[j])
1737 goto out_nomem;
1738
1739 ret = request_irq(irq, desc->handler, up->irqflags,
1740 port->irqstr[j], port);
1741 if (unlikely(ret)) {
1742 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc);
1743 goto out_noirq;
1744 }
73a19e4c
GL		 1745 }
1746
e1910fcd 1747 return 0;
1da177e4 1748
e1910fcd
GU		 1749out_noirq:
1750 while (--i >= 0)
1751 free_irq(port->irqs[i], port);
f43dc23d 1752
e1910fcd
GU		 1753out_nomem:
1754 while (--j >= 0)
1755 kfree(port->irqstr[j]);
f43dc23d 1756
e1910fcd 1757 return ret;
1da177e4
LT		 1758}
1759
e1910fcd 1760static void sci_free_irq(struct sci_port *port)
1da177e4 1761{
e1910fcd 1762 int i;
1da177e4 1763
e1910fcd
GU		 1764 /*
1765 * Intentionally in reverse order so we iterate over the muxed
1766 * IRQ first.
1767 */
1768 for (i = 0; i < SCIx_NR_IRQS; i++) {
1769 int irq = port->irqs[i];
f43dc23d 1770
e1910fcd
GU		 1771 /*
1772 * Certain port types won't support all of the available
1773 * interrupt sources.
1774 */
1775 if (unlikely(irq < 0))
1776 continue;
f43dc23d 1777
e1910fcd
GU		 1778 free_irq(port->irqs[i], port);
1779 kfree(port->irqstr[i]);
f43dc23d 1780
e1910fcd
GU		 1781 if (SCIx_IRQ_IS_MUXED(port)) {
1782 /* If there's only one IRQ, we're done. */
1783 return;
1784 }
1785 }
1da177e4
LT		 1786}
1787
e1910fcd 1788static unsigned int sci_tx_empty(struct uart_port *port)
1da177e4 1789{
e1910fcd
GU		 1790 unsigned short status = serial_port_in(port, SCxSR);
1791 unsigned short in_tx_fifo = sci_txfill(port);
f43dc23d 1792
e1910fcd 1793 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
1da177e4
LT		 1794}
1795
e1910fcd
GU		 1796/*
1797 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally
1798 * CTS/RTS is supported in hardware by at least one port and controlled
1799 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently
1800 * handled via the ->init_pins() op, which is a bit of a one-way street,
1801 * lacking any ability to defer pin control -- this will later be
1802 * converted over to the GPIO framework).
1803 *
1804 * Other modes (such as loopback) are supported generically on certain
1805 * port types, but not others. For these it's sufficient to test for the
1806 * existence of the support register and simply ignore the port type.
1807 */
1808static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
1da177e4 1809{
e1910fcd
GU		 1810 if (mctrl & TIOCM_LOOP) {
1811 const struct plat_sci_reg *reg;
f43dc23d 1812
e1910fcd
GU		 1813 /*
1814 * Standard loopback mode for SCFCR ports.
1815 */
1816 reg = sci_getreg(port, SCFCR);
1817 if (reg->size)
1818 serial_port_out(port, SCFCR,
1819 serial_port_in(port, SCFCR) |
1820 SCFCR_LOOP);
1821 }
1822}
f43dc23d 1823
e1910fcd
GU		 1824static unsigned int sci_get_mctrl(struct uart_port *port)
1825{
1826 /*
1827 * CTS/RTS is handled in hardware when supported, while nothing
1828 * else is wired up. Keep it simple and simply assert DSR/CAR.
1829 */
1830 return TIOCM_DSR | TIOCM_CAR;
1da177e4
LT		 1831}
1832
1da177e4
LT		 1833static void sci_break_ctl(struct uart_port *port, int break_state)
1834{
bbb4ce50 1835 struct sci_port *s = to_sci_port(port);
d3184e68 1836 const struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR;
bbb4ce50
SY		 1837 unsigned short scscr, scsptr;
1838
a4e02f6d
SY		 1839 /* check wheter the port has SCSPTR */
1840 if (!reg->size) {
bbb4ce50
SY		 1841 /*
1842 * Not supported by hardware. Most parts couple break and rx
1843 * interrupts together, with break detection always enabled.
1844 */
a4e02f6d 1845 return;
bbb4ce50 1846 }
a4e02f6d
SY		 1847
1848 scsptr = serial_port_in(port, SCSPTR);
1849 scscr = serial_port_in(port, SCSCR);
1850
1851 if (break_state == -1) {
1852 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT;
1853 scscr &= ~SCSCR_TE;
1854 } else {
1855 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO;
1856 scscr |= SCSCR_TE;
1857 }
1858
1859 serial_port_out(port, SCSPTR, scsptr);
1860 serial_port_out(port, SCSCR, scscr);
1da177e4
LT		 1861}
1862
1863static int sci_startup(struct uart_port *port)
1864{
a5660ada 1865 struct sci_port *s = to_sci_port(port);
33b48e16 1866 unsigned long flags;
073e84c9 1867 int ret;
1da177e4 1868
73a19e4c
GL		 1869 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1870
073e84c9
PM		 1871 ret = sci_request_irq(s);
1872 if (unlikely(ret < 0))
1873 return ret;
1874
73a19e4c 1875 sci_request_dma(port);
073e84c9 1876
33b48e16 1877 spin_lock_irqsave(&port->lock, flags);
d656901b 1878 sci_start_tx(port);
73a19e4c 1879 sci_start_rx(port);
33b48e16 1880 spin_unlock_irqrestore(&port->lock, flags);
1da177e4
LT		 1881
1882 return 0;
1883}
1884
1885static void sci_shutdown(struct uart_port *port)
1886{
a5660ada 1887 struct sci_port *s = to_sci_port(port);
33b48e16 1888 unsigned long flags;
1da177e4 1889
73a19e4c
GL		 1890 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1891
33b48e16 1892 spin_lock_irqsave(&port->lock, flags);
1da177e4 1893 sci_stop_rx(port);
b129a8cc 1894 sci_stop_tx(port);
33b48e16 1895 spin_unlock_irqrestore(&port->lock, flags);
073e84c9 1896
9ab76556
AM		 1897#ifdef CONFIG_SERIAL_SH_SCI_DMA
1898 if (s->chan_rx) {
1899 dev_dbg(port->dev, "%s(%d) deleting rx_timer\n", __func__,
1900 port->line);
1901 del_timer_sync(&s->rx_timer);
1902 }
1903#endif
1904
73a19e4c 1905 sci_free_dma(port);
1da177e4 1906 sci_free_irq(s);
1da177e4
LT		 1907}
1908
b4a5c459
GU		 1909/* calculate sample rate, BRR, and clock select */
1910static void sci_scbrr_calc(struct sci_port *s, unsigned int bps,
1911 unsigned long freq, int *brr, unsigned int *srr,
1912 unsigned int *cks)
26c92f37 1913{
b4a5c459 1914 unsigned int min_sr, max_sr, shift, sr, br, prediv, scrate, c;
6c51332d 1915 int err, min_err = INT_MAX;
f303b364 1916
b4a5c459
GU		 1917 if (s->sampling_rate) {
1918 min_sr = max_sr = s->sampling_rate;
1919 shift = 0;
1920 } else {
1921 /* HSCIF has a variable sample rate */
1922 min_sr = 8;
1923 max_sr = 32;
1924 shift = 1;
1925 }
1926
6c51332d
GU		 1927 /*
1928 * Find the combination of sample rate and clock select with the
1929 * smallest deviation from the desired baud rate.
1930 * Prefer high sample rates to maximise the receive margin.
1931 *
1932 * M: Receive margin (%)
1933 * N: Ratio of bit rate to clock (N = sampling rate)
1934 * D: Clock duty (D = 0 to 1.0)
1935 * L: Frame length (L = 9 to 12)
1936 * F: Absolute value of clock frequency deviation
1937 *
1938 * M = |(0.5 - 1 / 2 * N) - ((L - 0.5) * F) -
1939 * (|D - 0.5| / N * (1 + F))|
1940 * NOTE: Usually, treat D for 0.5, F is 0 by this calculation.
1941 */
b4a5c459 1942 for (sr = max_sr; sr >= min_sr; sr--) {
f303b364
UH		 1943 for (c = 0; c <= 3; c++) {
1944 /* integerized formulas from HSCIF documentation */
b4a5c459 1945 prediv = sr * (1 << (2 * c + shift));
de01e6cd
GU		 1946
1947 /*
1948 * We need to calculate:
1949 *
1950 * br = freq / (prediv * bps) clamped to [1..256]
881a7489 1951 * err = freq / (br * prediv) - bps
de01e6cd
GU		 1952 *
1953 * Watch out for overflow when calculating the desired
1954 * sampling clock rate!
1955 */
1956 if (bps > UINT_MAX / prediv)
1957 break;
1958
1959 scrate = prediv * bps;
1960 br = DIV_ROUND_CLOSEST(freq, scrate);
95a2703e 1961 br = clamp(br, 1U, 256U);
6c51332d 1962
881a7489 1963 err = DIV_ROUND_CLOSEST(freq, br * prediv) - bps;
6c51332d 1964 if (abs(err) >= abs(min_err))
730c4e78
NI		 1965 continue;
1966
6c51332d 1967 min_err = err;
95a2703e 1968 *brr = br - 1;
730c4e78
NI		 1969 *srr = sr - 1;
1970 *cks = c;
6c51332d
GU		 1971
1972 if (!err)
1973 goto found;
f303b364
UH		 1974 }
1975 }
1976
6c51332d 1977found:
881a7489
GU		 1978 dev_dbg(s->port.dev, "BRR: %u%+d bps using N %u SR %u cks %u\n", bps,
1979 min_err, *brr, *srr + 1, *cks);
f303b364
UH		 1980}
1981
1ba76220
MD		 1982static void sci_reset(struct uart_port *port)
1983{
d3184e68 1984 const struct plat_sci_reg *reg;
1ba76220
MD		 1985 unsigned int status;
1986
1987 do {
b12bb29f 1988 status = serial_port_in(port, SCxSR);
1ba76220
MD		 1989 } while (!(status & SCxSR_TEND(port)));
1990
b12bb29f 1991 serial_port_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */
1ba76220 1992
0979e0e6
PM		 1993 reg = sci_getreg(port, SCFCR);
1994 if (reg->size)
b12bb29f 1995 serial_port_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
1ba76220
MD		 1996}
1997
606d099c
AC		 1998static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
1999 struct ktermios *old)
1da177e4 2000{
00b9de9c 2001 struct sci_port *s = to_sci_port(port);
d3184e68 2002 const struct plat_sci_reg *reg;
730c4e78 2003 unsigned int baud, smr_val = 0, max_baud, cks = 0;
a2159b52 2004 int t = -1;
d4759ded 2005 unsigned int srr = 15;
1da177e4 2006
730c4e78
NI		 2007 if ((termios->c_cflag & CSIZE) == CS7)
2008 smr_val |= SCSMR_CHR;
2009 if (termios->c_cflag & PARENB)
2010 smr_val |= SCSMR_PE;
2011 if (termios->c_cflag & PARODD)
2012 smr_val |= SCSMR_PE | SCSMR_ODD;
2013 if (termios->c_cflag & CSTOPB)
2014 smr_val |= SCSMR_STOP;
2015
154280fd
MD		 2016 /*
2017 * earlyprintk comes here early on with port->uartclk set to zero.
2018 * the clock framework is not up and running at this point so here
2019 * we assume that 115200 is the maximum baud rate. please note that
2020 * the baud rate is not programmed during earlyprintk - it is assumed
2021 * that the previous boot loader has enabled required clocks and
2022 * setup the baud rate generator hardware for us already.
2023 */
ff8b275f
GU		 2024 if (port->uartclk)
2025 max_baud = port->uartclk / max(s->sampling_rate, 8U);
2026 else
2027 max_baud = 115200;
1da177e4 2028
154280fd 2029 baud = uart_get_baud_rate(port, termios, old, 0, max_baud);
b4a5c459
GU		 2030 if (likely(baud && port->uartclk))
2031 sci_scbrr_calc(s, baud, port->uartclk, &t, &srr, &cks);
e108b2ca 2032
23241d43 2033 sci_port_enable(s);
36003386 2034
1ba76220 2035 sci_reset(port);
1da177e4 2036
2944a331 2037 smr_val |= serial_port_in(port, SCSMR) & SCSMR_CKS;
1da177e4
LT		 2038
2039 uart_update_timeout(port, termios->c_cflag, baud);
2040
9d482cc3
TY		 2041 dev_dbg(port->dev, "%s: SMR %x, cks %x, t %x, SCSCR %x\n",
2042 __func__, smr_val, cks, t, s->cfg->scscr);
73a19e4c 2043
4ffc3cdb 2044 if (t >= 0) {
26de4f1b 2045 serial_port_out(port, SCSMR, (smr_val & ~SCSMR_CKS) | cks);
b12bb29f 2046 serial_port_out(port, SCBRR, t);
f303b364
UH		 2047 reg = sci_getreg(port, HSSRR);
2048 if (reg->size)
2049 serial_port_out(port, HSSRR, srr | HSCIF_SRE);
1da177e4 2050 udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */
9d482cc3
TY		 2051 } else
2052 serial_port_out(port, SCSMR, smr_val);
1da177e4 2053
d5701647 2054 sci_init_pins(port, termios->c_cflag);
0979e0e6 2055
73c3d53f
PM		 2056 reg = sci_getreg(port, SCFCR);
2057 if (reg->size) {
b12bb29f 2058 unsigned short ctrl = serial_port_in(port, SCFCR);
0979e0e6 2059
73c3d53f 2060 if (s->cfg->capabilities & SCIx_HAVE_RTSCTS) {
faf02f8f
PM		 2061 if (termios->c_cflag & CRTSCTS)
2062 ctrl |= SCFCR_MCE;
2063 else
2064 ctrl &= ~SCFCR_MCE;
faf02f8f 2065 }
73c3d53f
PM		 2066
2067 /*
2068 * As we've done a sci_reset() above, ensure we don't
2069 * interfere with the FIFOs while toggling MCE. As the
2070 * reset values could still be set, simply mask them out.
2071 */
2072 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST);
2073
b12bb29f 2074 serial_port_out(port, SCFCR, ctrl);
0979e0e6 2075 }
b7a76e4b 2076
b12bb29f 2077 serial_port_out(port, SCSCR, s->cfg->scscr);
1da177e4 2078
3089f381
GL		 2079#ifdef CONFIG_SERIAL_SH_SCI_DMA
2080 /*
5f6d8515 2081 * Calculate delay for 2 DMA buffers (4 FIFO).
f5835c1d
GU		 2082 * See serial_core.c::uart_update_timeout().
2083 * With 10 bits (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above
2084 * function calculates 1 jiffie for the data plus 5 jiffies for the
2085 * "slop(e)." Then below we calculate 5 jiffies (20ms) for 2 DMA
2086 * buffers (4 FIFO sizes), but when performing a faster transfer, the
2087 * value obtained by this formula is too small. Therefore, if the value
2088 * is smaller than 20ms, use 20ms as the timeout value for DMA.
3089f381
GL		 2089 */
2090 if (s->chan_rx) {
5f6d8515
NI		 2091 unsigned int bits;
2092
2093 /* byte size and parity */
2094 switch (termios->c_cflag & CSIZE) {
2095 case CS5:
2096 bits = 7;
2097 break;
2098 case CS6:
2099 bits = 8;
2100 break;
2101 case CS7:
2102 bits = 9;
2103 break;
2104 default:
2105 bits = 10;
2106 break;
2107 }
2108
2109 if (termios->c_cflag & CSTOPB)
2110 bits++;
2111 if (termios->c_cflag & PARENB)
2112 bits++;
2113 s->rx_timeout = DIV_ROUND_UP((s->buf_len_rx * 2 * bits * HZ) /
2114 (baud / 10), 10);
9b971cd2 2115 dev_dbg(port->dev, "DMA Rx t-out %ums, tty t-out %u jiffies\n",
3089f381
GL		 2116 s->rx_timeout * 1000 / HZ, port->timeout);
2117 if (s->rx_timeout < msecs_to_jiffies(20))
2118 s->rx_timeout = msecs_to_jiffies(20);
2119 }
2120#endif
2121
1da177e4 2122 if ((termios->c_cflag & CREAD) != 0)
73a19e4c 2123 sci_start_rx(port);
36003386 2124
23241d43 2125 sci_port_disable(s);
1da177e4
LT		 2126}
2127
0174e5ca
TK		 2128static void sci_pm(struct uart_port *port, unsigned int state,
2129 unsigned int oldstate)
2130{
2131 struct sci_port *sci_port = to_sci_port(port);
2132
2133 switch (state) {
d3dfe5d9 2134 case UART_PM_STATE_OFF:
0174e5ca
TK		 2135 sci_port_disable(sci_port);
2136 break;
2137 default:
2138 sci_port_enable(sci_port);
2139 break;
2140 }
2141}
2142
1da177e4
LT		 2143static const char *sci_type(struct uart_port *port)
2144{
2145 switch (port->type) {
e7c98dc7
MT		 2146 case PORT_IRDA:
2147 return "irda";
2148 case PORT_SCI:
2149 return "sci";
2150 case PORT_SCIF:
2151 return "scif";
2152 case PORT_SCIFA:
2153 return "scifa";
d1d4b10c
GL		 2154 case PORT_SCIFB:
2155 return "scifb";
f303b364
UH		 2156 case PORT_HSCIF:
2157 return "hscif";
1da177e4
LT		 2158 }
2159
fa43972f 2160 return NULL;
1da177e4
LT		 2161}
2162
f6e9495d
PM		 2163static int sci_remap_port(struct uart_port *port)
2164{
e4d6f911 2165 struct sci_port *sport = to_sci_port(port);
f6e9495d
PM		 2166
2167 /*
2168 * Nothing to do if there's already an established membase.
2169 */
2170 if (port->membase)
2171 return 0;
2172
2173 if (port->flags & UPF_IOREMAP) {
e4d6f911 2174 port->membase = ioremap_nocache(port->mapbase, sport->reg_size);
f6e9495d
PM		 2175 if (unlikely(!port->membase)) {
2176 dev_err(port->dev, "can't remap port#%d\n", port->line);
2177 return -ENXIO;
2178 }
2179 } else {
2180 /*
2181 * For the simple (and majority of) cases where we don't
2182 * need to do any remapping, just cast the cookie
2183 * directly.
2184 */
3af4e960 2185 port->membase = (void __iomem *)(uintptr_t)port->mapbase;
f6e9495d
PM		 2186 }
2187
2188 return 0;
2189}
2190
e2651647 2191static void sci_release_port(struct uart_port *port)
1da177e4 2192{
e4d6f911
YS		 2193 struct sci_port *sport = to_sci_port(port);
2194
e2651647
PM		 2195 if (port->flags & UPF_IOREMAP) {
2196 iounmap(port->membase);
2197 port->membase = NULL;
2198 }
2199
e4d6f911 2200 release_mem_region(port->mapbase, sport->reg_size);
1da177e4
LT		 2201}
2202
e2651647 2203static int sci_request_port(struct uart_port *port)
1da177e4 2204{
e2651647 2205 struct resource *res;
e4d6f911 2206 struct sci_port *sport = to_sci_port(port);
f6e9495d 2207 int ret;
1da177e4 2208
e4d6f911
YS		 2209 res = request_mem_region(port->mapbase, sport->reg_size,
2210 dev_name(port->dev));
2211 if (unlikely(res == NULL)) {
2212 dev_err(port->dev, "request_mem_region failed.");
e2651647 2213 return -EBUSY;
e4d6f911 2214 }
1da177e4 2215
f6e9495d
PM		 2216 ret = sci_remap_port(port);
2217 if (unlikely(ret != 0)) {
2218 release_resource(res);
2219 return ret;
7ff731ae 2220 }
e2651647
PM		 2221
2222 return 0;
2223}
2224
2225static void sci_config_port(struct uart_port *port, int flags)
2226{
2227 if (flags & UART_CONFIG_TYPE) {
2228 struct sci_port *sport = to_sci_port(port);
2229
2230 port->type = sport->cfg->type;
2231 sci_request_port(port);
2232 }
1da177e4
LT		 2233}
2234
2235static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
2236{
1da177e4
LT		 2237 if (ser->baud_base < 2400)
2238 /* No paper tape reader for Mitch.. */
2239 return -EINVAL;
2240
2241 return 0;
2242}
2243
2244static struct uart_ops sci_uart_ops = {
2245 .tx_empty = sci_tx_empty,
2246 .set_mctrl = sci_set_mctrl,
2247 .get_mctrl = sci_get_mctrl,
2248 .start_tx = sci_start_tx,
2249 .stop_tx = sci_stop_tx,
2250 .stop_rx = sci_stop_rx,
1da177e4
LT		 2251 .break_ctl = sci_break_ctl,
2252 .startup = sci_startup,
2253 .shutdown = sci_shutdown,
2254 .set_termios = sci_set_termios,
0174e5ca 2255 .pm = sci_pm,
1da177e4
LT		 2256 .type = sci_type,
2257 .release_port = sci_release_port,
2258 .request_port = sci_request_port,
2259 .config_port = sci_config_port,
2260 .verify_port = sci_verify_port,
07d2a1a1
PM		 2261#ifdef CONFIG_CONSOLE_POLL
2262 .poll_get_char = sci_poll_get_char,
2263 .poll_put_char = sci_poll_put_char,
2264#endif
1da177e4
LT		 2265};
2266
a9ec81f4
LP		 2267static int sci_init_clocks(struct sci_port *sci_port, struct device *dev)
2268{
2269 /* Get the SCI functional clock. It's called "fck" on ARM. */
f4de472e 2270 sci_port->fclk = devm_clk_get(dev, "fck");
a9ec81f4
LP		 2271 if (PTR_ERR(sci_port->fclk) == -EPROBE_DEFER)
2272 return -EPROBE_DEFER;
2273 if (!IS_ERR(sci_port->fclk))
2274 return 0;
2275
2276 /*
2277 * But it used to be called "sci_ick", and we need to maintain DT
2278 * backward compatibility.
2279 */
f4de472e 2280 sci_port->fclk = devm_clk_get(dev, "sci_ick");
a9ec81f4
LP		 2281 if (PTR_ERR(sci_port->fclk) == -EPROBE_DEFER)
2282 return -EPROBE_DEFER;
2283 if (!IS_ERR(sci_port->fclk))
2284 return 0;
2285
2286 /* SH has historically named the clock "sci_fck". */
f4de472e 2287 sci_port->fclk = devm_clk_get(dev, "sci_fck");
a9ec81f4
LP		 2288 if (!IS_ERR(sci_port->fclk))
2289 return 0;
2290
2291 /*
2292 * Not all SH platforms declare a clock lookup entry for SCI devices,
2293 * in which case we need to get the global "peripheral_clk" clock.
2294 */
f4de472e 2295 sci_port->fclk = devm_clk_get(dev, "peripheral_clk");
a9ec81f4
LP		 2296 if (!IS_ERR(sci_port->fclk))
2297 return 0;
2298
2299 dev_err(dev, "failed to get functional clock\n");
2300 return PTR_ERR(sci_port->fclk);
2301}
2302
9671f099 2303static int sci_init_single(struct platform_device *dev,
1fcc91a6
LP		 2304 struct sci_port *sci_port, unsigned int index,
2305 struct plat_sci_port *p, bool early)
e108b2ca 2306{
73a19e4c 2307 struct uart_port *port = &sci_port->port;
1fcc91a6
LP		 2308 const struct resource *res;
2309 unsigned int i;
3127c6b2 2310 int ret;
e108b2ca 2311
50f0959a
PM		 2312 sci_port->cfg = p;
2313
73a19e4c
GL		 2314 port->ops = &sci_uart_ops;
2315 port->iotype = UPIO_MEM;
2316 port->line = index;
75136d48 2317
89b5c1ab
LP		 2318 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
2319 if (res == NULL)
2320 return -ENOMEM;
1fcc91a6 2321
89b5c1ab 2322 port->mapbase = res->start;
e4d6f911 2323 sci_port->reg_size = resource_size(res);
1fcc91a6 2324
89b5c1ab
LP		 2325 for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i)
2326 sci_port->irqs[i] = platform_get_irq(dev, i);
1fcc91a6 2327
89b5c1ab
LP		 2328 /* The SCI generates several interrupts. They can be muxed together or
2329 * connected to different interrupt lines. In the muxed case only one
2330 * interrupt resource is specified. In the non-muxed case three or four
2331 * interrupt resources are specified, as the BRI interrupt is optional.
2332 */
2333 if (sci_port->irqs[0] < 0)
2334 return -ENXIO;
1fcc91a6 2335
89b5c1ab
LP		 2336 if (sci_port->irqs[1] < 0) {
2337 sci_port->irqs[1] = sci_port->irqs[0];
2338 sci_port->irqs[2] = sci_port->irqs[0];
2339 sci_port->irqs[3] = sci_port->irqs[0];
1fcc91a6
LP		 2340 }
2341
b545e4f4
LP		 2342 if (p->regtype == SCIx_PROBE_REGTYPE) {
2343 ret = sci_probe_regmap(p);
2344 if (unlikely(ret))
2345 return ret;
2346 }
2347
75136d48 2348 switch (p->type) {
d1d4b10c
GL		 2349 case PORT_SCIFB:
2350 port->fifosize = 256;
2e0842a1 2351 sci_port->overrun_reg = SCxSR;
75c249fd 2352 sci_port->overrun_mask = SCIFA_ORER;
f84b6bdc 2353 sci_port->sampling_rate = 16;
d1d4b10c 2354 break;
f303b364
UH		 2355 case PORT_HSCIF:
2356 port->fifosize = 128;
2e0842a1 2357 sci_port->overrun_reg = SCLSR;
75c249fd 2358 sci_port->overrun_mask = SCLSR_ORER;
f84b6bdc 2359 sci_port->sampling_rate = 0;
f303b364 2360 break;
75136d48 2361 case PORT_SCIFA:
73a19e4c 2362 port->fifosize = 64;
2e0842a1 2363 sci_port->overrun_reg = SCxSR;
75c249fd 2364 sci_port->overrun_mask = SCIFA_ORER;
f84b6bdc 2365 sci_port->sampling_rate = 16;
75136d48
MP		 2366 break;
2367 case PORT_SCIF:
73a19e4c 2368 port->fifosize = 16;
ec09c5eb 2369 if (p->regtype == SCIx_SH7705_SCIF_REGTYPE) {
2e0842a1 2370 sci_port->overrun_reg = SCxSR;
75c249fd 2371 sci_port->overrun_mask = SCIFA_ORER;
f84b6bdc 2372 sci_port->sampling_rate = 16;
ec09c5eb 2373 } else {
2e0842a1 2374 sci_port->overrun_reg = SCLSR;
75c249fd 2375 sci_port->overrun_mask = SCLSR_ORER;
f84b6bdc 2376 sci_port->sampling_rate = 32;
ec09c5eb 2377 }
75136d48
MP		 2378 break;
2379 default:
73a19e4c 2380 port->fifosize = 1;
2e0842a1 2381 sci_port->overrun_reg = SCxSR;
75c249fd 2382 sci_port->overrun_mask = SCI_ORER;
f84b6bdc 2383 sci_port->sampling_rate = 32;
75136d48
MP		 2384 break;
2385 }
7b6fd3bf 2386
878fbb91
LP		 2387 /* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't
2388 * match the SoC datasheet, this should be investigated. Let platform
2389 * data override the sampling rate for now.
ec09c5eb 2390 */
f84b6bdc
GU		 2391 if (p->sampling_rate)
2392 sci_port->sampling_rate = p->sampling_rate;
ec09c5eb 2393
1fcc91a6 2394 if (!early) {
a9ec81f4
LP		 2395 ret = sci_init_clocks(sci_port, &dev->dev);
2396 if (ret < 0)
2397 return ret;
c7ed1ab3 2398
73a19e4c 2399 port->dev = &dev->dev;
5e50d2d6
MD		 2400
2401 pm_runtime_enable(&dev->dev);
7b6fd3bf 2402 }
e108b2ca 2403
7ed7e071
MD		 2404 sci_port->break_timer.data = (unsigned long)sci_port;
2405 sci_port->break_timer.function = sci_break_timer;
2406 init_timer(&sci_port->break_timer);
2407
debf9507
PM		 2408 /*
2409 * Establish some sensible defaults for the error detection.
2410 */
5da0f468
GU		 2411 if (p->type == PORT_SCI) {
2412 sci_port->error_mask = SCI_DEFAULT_ERROR_MASK;
2413 sci_port->error_clear = SCI_ERROR_CLEAR;
2414 } else {
2415 sci_port->error_mask = SCIF_DEFAULT_ERROR_MASK;
2416 sci_port->error_clear = SCIF_ERROR_CLEAR;
2417 }
debf9507 2418
3ae988d9
LP		 2419 /*
2420 * Make the error mask inclusive of overrun detection, if
2421 * supported.
2422 */
5da0f468 2423 if (sci_port->overrun_reg == SCxSR) {
afd66db6 2424 sci_port->error_mask |= sci_port->overrun_mask;
5da0f468
GU		 2425 sci_port->error_clear &= ~sci_port->overrun_mask;
2426 }
debf9507 2427
ce6738b6 2428 port->type = p->type;
b6e4a3f1 2429 port->flags = UPF_FIXED_PORT | p->flags;
61a6976b 2430 port->regshift = p->regshift;
73a19e4c 2431
ce6738b6 2432 /*
61a6976b 2433 * The UART port needs an IRQ value, so we peg this to the RX IRQ
ce6738b6
PM		 2434 * for the multi-IRQ ports, which is where we are primarily
2435 * concerned with the shutdown path synchronization.
2436 *
2437 * For the muxed case there's nothing more to do.
2438 */
1fcc91a6 2439 port->irq = sci_port->irqs[SCIx_RXI_IRQ];
9cfb5c05 2440 port->irqflags = 0;
73a19e4c 2441
61a6976b
PM		 2442 port->serial_in = sci_serial_in;
2443 port->serial_out = sci_serial_out;
2444
937bb6e4
GL		 2445 if (p->dma_slave_tx > 0 && p->dma_slave_rx > 0)
2446 dev_dbg(port->dev, "DMA tx %d, rx %d\n",
2447 p->dma_slave_tx, p->dma_slave_rx);
7ed7e071 2448
c7ed1ab3 2449 return 0;
e108b2ca
PM		 2450}
2451
6dae1421
LP		 2452static void sci_cleanup_single(struct sci_port *port)
2453{
6dae1421
LP		 2454 pm_runtime_disable(port->port.dev);
2455}
2456
1da177e4 2457#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
dc8e6f5b
MD		 2458static void serial_console_putchar(struct uart_port *port, int ch)
2459{
2460 sci_poll_put_char(port, ch);
2461}
2462
1da177e4
LT		 2463/*
2464 * Print a string to the serial port trying not to disturb
2465 * any possible real use of the port...
2466 */
2467static void serial_console_write(struct console *co, const char *s,
2468 unsigned count)
2469{
906b17dc
PM		 2470 struct sci_port *sci_port = &sci_ports[co->index];
2471 struct uart_port *port = &sci_port->port;
a67969b5 2472 unsigned short bits, ctrl, ctrl_temp;
40f70c03
SK		 2473 unsigned long flags;
2474 int locked = 1;
2475
2476 local_irq_save(flags);
2477 if (port->sysrq)
2478 locked = 0;
2479 else if (oops_in_progress)
2480 locked = spin_trylock(&port->lock);
2481 else
2482 spin_lock(&port->lock);
2483
a67969b5 2484 /* first save SCSCR then disable interrupts, keep clock source */
40f70c03 2485 ctrl = serial_port_in(port, SCSCR);
a67969b5
GU		 2486 ctrl_temp = (sci_port->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)) |
2487 (ctrl & (SCSCR_CKE1 | SCSCR_CKE0));
2488 serial_port_out(port, SCSCR, ctrl_temp);
07d2a1a1 2489
501b825d 2490 uart_console_write(port, s, count, serial_console_putchar);
973e5d52
MD		 2491
2492 /* wait until fifo is empty and last bit has been transmitted */
2493 bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
b12bb29f 2494 while ((serial_port_in(port, SCxSR) & bits) != bits)
973e5d52 2495 cpu_relax();
40f70c03
SK		 2496
2497 /* restore the SCSCR */
2498 serial_port_out(port, SCSCR, ctrl);
2499
2500 if (locked)
2501 spin_unlock(&port->lock);
2502 local_irq_restore(flags);
1da177e4
LT		 2503}
2504
9671f099 2505static int serial_console_setup(struct console *co, char *options)
1da177e4 2506{
dc8e6f5b 2507 struct sci_port *sci_port;
1da177e4
LT		 2508 struct uart_port *port;
2509 int baud = 115200;
2510 int bits = 8;
2511 int parity = 'n';
2512 int flow = 'n';
2513 int ret;
2514
e108b2ca 2515 /*
906b17dc 2516 * Refuse to handle any bogus ports.
1da177e4 2517 */
906b17dc 2518 if (co->index < 0 || co->index >= SCI_NPORTS)
e108b2ca 2519 return -ENODEV;
e108b2ca 2520
906b17dc
PM		 2521 sci_port = &sci_ports[co->index];
2522 port = &sci_port->port;
2523
b2267a6b
AC		 2524 /*
2525 * Refuse to handle uninitialized ports.
2526 */
2527 if (!port->ops)
2528 return -ENODEV;
2529
f6e9495d
PM		 2530 ret = sci_remap_port(port);
2531 if (unlikely(ret != 0))
2532 return ret;
e108b2ca 2533
1da177e4
LT		 2534 if (options)
2535 uart_parse_options(options, &baud, &parity, &bits, &flow);
2536
ab7cfb55 2537 return uart_set_options(port, co, baud, parity, bits, flow);
1da177e4
LT		 2538}
2539
2540static struct console serial_console = {
2541 .name = "ttySC",
906b17dc 2542 .device = uart_console_device,
1da177e4
LT		 2543 .write = serial_console_write,
2544 .setup = serial_console_setup,
fa5da2f7 2545 .flags = CON_PRINTBUFFER,
1da177e4 2546 .index = -1,
906b17dc 2547 .data = &sci_uart_driver,
1da177e4
LT		 2548};
2549
7b6fd3bf
MD		 2550static struct console early_serial_console = {
2551 .name = "early_ttySC",
2552 .write = serial_console_write,
2553 .flags = CON_PRINTBUFFER,
906b17dc 2554 .index = -1,
7b6fd3bf 2555};
ecdf8a46 2556
7b6fd3bf
MD		 2557static char early_serial_buf[32];
2558
9671f099 2559static int sci_probe_earlyprintk(struct platform_device *pdev)
ecdf8a46 2560{
574de559 2561 struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev);
ecdf8a46
PM		 2562
2563 if (early_serial_console.data)
2564 return -EEXIST;
2565
2566 early_serial_console.index = pdev->id;
ecdf8a46 2567
1fcc91a6 2568 sci_init_single(pdev, &sci_ports[pdev->id], pdev->id, cfg, true);
ecdf8a46
PM		 2569
2570 serial_console_setup(&early_serial_console, early_serial_buf);
2571
2572 if (!strstr(early_serial_buf, "keep"))
2573 early_serial_console.flags |= CON_BOOT;
2574
2575 register_console(&early_serial_console);
2576 return 0;
2577}
6a8c9799
NI		 2578
2579#define SCI_CONSOLE (&serial_console)
2580
ecdf8a46 2581#else
9671f099 2582static inline int sci_probe_earlyprintk(struct platform_device *pdev)
ecdf8a46
PM		 2583{
2584 return -EINVAL;
2585}
1da177e4 2586
6a8c9799
NI		 2587#define SCI_CONSOLE NULL
2588
2589#endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
1da177e4 2590
6c13d5d2 2591static const char banner[] __initconst = "SuperH (H)SCI(F) driver initialized";
1da177e4
LT		 2592
2593static struct uart_driver sci_uart_driver = {
2594 .owner = THIS_MODULE,
2595 .driver_name = "sci",
1da177e4
LT		 2596 .dev_name = "ttySC",
2597 .major = SCI_MAJOR,
2598 .minor = SCI_MINOR_START,
e108b2ca 2599 .nr = SCI_NPORTS,
1da177e4
LT		 2600 .cons = SCI_CONSOLE,
2601};
2602
54507f6e 2603static int sci_remove(struct platform_device *dev)
e552de24 2604{
d535a230 2605 struct sci_port *port = platform_get_drvdata(dev);
e552de24 2606
d535a230
PM		 2607 cpufreq_unregister_notifier(&port->freq_transition,
2608 CPUFREQ_TRANSITION_NOTIFIER);
e552de24 2609
d535a230
PM		 2610 uart_remove_one_port(&sci_uart_driver, &port->port);
2611
6dae1421 2612 sci_cleanup_single(port);
e552de24 2613
e552de24
MD		 2614 return 0;
2615}
2616
20bdcab8
BH		 2617struct sci_port_info {
2618 unsigned int type;
2619 unsigned int regtype;
2620};
2621
2622static const struct of_device_id of_sci_match[] = {
2623 {
2624 .compatible = "renesas,scif",
ff43da00 2625 .data = &(const struct sci_port_info) {
20bdcab8
BH		 2626 .type = PORT_SCIF,
2627 .regtype = SCIx_SH4_SCIF_REGTYPE,
2628 },
2629 }, {
2630 .compatible = "renesas,scifa",
ff43da00 2631 .data = &(const struct sci_port_info) {
20bdcab8
BH		 2632 .type = PORT_SCIFA,
2633 .regtype = SCIx_SCIFA_REGTYPE,
2634 },
2635 }, {
2636 .compatible = "renesas,scifb",
ff43da00 2637 .data = &(const struct sci_port_info) {
20bdcab8
BH		 2638 .type = PORT_SCIFB,
2639 .regtype = SCIx_SCIFB_REGTYPE,
2640 },
2641 }, {
2642 .compatible = "renesas,hscif",
ff43da00 2643 .data = &(const struct sci_port_info) {
20bdcab8
BH		 2644 .type = PORT_HSCIF,
2645 .regtype = SCIx_HSCIF_REGTYPE,
2646 },
e1d0be61
YS		 2647 }, {
2648 .compatible = "renesas,sci",
2649 .data = &(const struct sci_port_info) {
2650 .type = PORT_SCI,
2651 .regtype = SCIx_SCI_REGTYPE,
2652 },
20bdcab8
BH		 2653 }, {
2654 /* Terminator */
2655 },
2656};
2657MODULE_DEVICE_TABLE(of, of_sci_match);
2658
2659static struct plat_sci_port *
2660sci_parse_dt(struct platform_device *pdev, unsigned int *dev_id)
2661{
2662 struct device_node *np = pdev->dev.of_node;
2663 const struct of_device_id *match;
2664 const struct sci_port_info *info;
2665 struct plat_sci_port *p;
2666 int id;
2667
2668 if (!IS_ENABLED(CONFIG_OF) || !np)
2669 return NULL;
2670
495bb47c 2671 match = of_match_node(of_sci_match, np);
20bdcab8
BH		 2672 if (!match)
2673 return NULL;
2674
2675 info = match->data;
2676
2677 p = devm_kzalloc(&pdev->dev, sizeof(struct plat_sci_port), GFP_KERNEL);
4205463c 2678 if (!p)
20bdcab8 2679 return NULL;
20bdcab8 2680
2095fc76 2681 /* Get the line number from the aliases node. */
20bdcab8
BH		 2682 id = of_alias_get_id(np, "serial");
2683 if (id < 0) {
2684 dev_err(&pdev->dev, "failed to get alias id (%d)\n", id);
2685 return NULL;
2686 }
2687
2688 *dev_id = id;
2689
2690 p->flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF;
2691 p->type = info->type;
2692 p->regtype = info->regtype;
2693 p->scscr = SCSCR_RE | SCSCR_TE;
2694
2695 return p;
2696}
2697
9671f099 2698static int sci_probe_single(struct platform_device *dev,
0ee70712
MD		 2699 unsigned int index,
2700 struct plat_sci_port *p,
2701 struct sci_port *sciport)
2702{
0ee70712
MD		 2703 int ret;
2704
2705 /* Sanity check */
2706 if (unlikely(index >= SCI_NPORTS)) {
9b971cd2 2707 dev_notice(&dev->dev, "Attempting to register port %d when only %d are available\n",
0ee70712 2708 index+1, SCI_NPORTS);
9b971cd2 2709 dev_notice(&dev->dev, "Consider bumping CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
b6c5ef6f 2710 return -EINVAL;
0ee70712
MD		 2711 }
2712
1fcc91a6 2713 ret = sci_init_single(dev, sciport, index, p, false);
c7ed1ab3
PM		 2714 if (ret)
2715 return ret;
0ee70712 2716
6dae1421
LP		 2717 ret = uart_add_one_port(&sci_uart_driver, &sciport->port);
2718 if (ret) {
2719 sci_cleanup_single(sciport);
2720 return ret;
2721 }
2722
2723 return 0;
0ee70712
MD		 2724}
2725
9671f099 2726static int sci_probe(struct platform_device *dev)
1da177e4 2727{
20bdcab8
BH		 2728 struct plat_sci_port *p;
2729 struct sci_port *sp;
2730 unsigned int dev_id;
ecdf8a46 2731 int ret;
d535a230 2732
ecdf8a46
PM		 2733 /*
2734 * If we've come here via earlyprintk initialization, head off to
2735 * the special early probe. We don't have sufficient device state
2736 * to make it beyond this yet.
2737 */
2738 if (is_early_platform_device(dev))
2739 return sci_probe_earlyprintk(dev);
7b6fd3bf 2740
20bdcab8
BH		 2741 if (dev->dev.of_node) {
2742 p = sci_parse_dt(dev, &dev_id);
2743 if (p == NULL)
2744 return -EINVAL;
2745 } else {
2746 p = dev->dev.platform_data;
2747 if (p == NULL) {
2748 dev_err(&dev->dev, "no platform data supplied\n");
2749 return -EINVAL;
2750 }
2751
2752 dev_id = dev->id;
2753 }
2754
2755 sp = &sci_ports[dev_id];
d535a230 2756 platform_set_drvdata(dev, sp);
e552de24 2757
20bdcab8 2758 ret = sci_probe_single(dev, dev_id, p, sp);
d535a230 2759 if (ret)
6dae1421 2760 return ret;
e552de24 2761
d535a230 2762 sp->freq_transition.notifier_call = sci_notifier;
1da177e4 2763
d535a230
PM		 2764 ret = cpufreq_register_notifier(&sp->freq_transition,
2765 CPUFREQ_TRANSITION_NOTIFIER);
6dae1421 2766 if (unlikely(ret < 0)) {
bf13c9a8 2767 uart_remove_one_port(&sci_uart_driver, &sp->port);
6dae1421
LP		 2768 sci_cleanup_single(sp);
2769 return ret;
2770 }
1da177e4
LT		 2771
2772#ifdef CONFIG_SH_STANDARD_BIOS
2773 sh_bios_gdb_detach();
2774#endif
2775
e108b2ca 2776 return 0;
1da177e4
LT		 2777}
2778
cb876341 2779static __maybe_unused int sci_suspend(struct device *dev)
1da177e4 2780{
d535a230 2781 struct sci_port *sport = dev_get_drvdata(dev);
e108b2ca 2782
d535a230
PM		 2783 if (sport)
2784 uart_suspend_port(&sci_uart_driver, &sport->port);
1da177e4 2785
e108b2ca
PM		 2786 return 0;
2787}
1da177e4 2788
cb876341 2789static __maybe_unused int sci_resume(struct device *dev)
e108b2ca 2790{
d535a230 2791 struct sci_port *sport = dev_get_drvdata(dev);
e108b2ca 2792
d535a230
PM		 2793 if (sport)
2794 uart_resume_port(&sci_uart_driver, &sport->port);
e108b2ca
PM		 2795
2796 return 0;
2797}
2798
cb876341 2799static SIMPLE_DEV_PM_OPS(sci_dev_pm_ops, sci_suspend, sci_resume);
6daa79b3 2800
e108b2ca
PM		 2801static struct platform_driver sci_driver = {
2802 .probe = sci_probe,
b9e39c89 2803 .remove = sci_remove,
e108b2ca
PM		 2804 .driver = {
2805 .name = "sh-sci",
6daa79b3 2806 .pm = &sci_dev_pm_ops,
20bdcab8 2807 .of_match_table = of_match_ptr(of_sci_match),
e108b2ca
PM		 2808 },
2809};
2810
2811static int __init sci_init(void)
2812{
2813 int ret;
2814
6c13d5d2 2815 pr_info("%s\n", banner);
e108b2ca 2816
e108b2ca
PM		 2817 ret = uart_register_driver(&sci_uart_driver);
2818 if (likely(ret == 0)) {
2819 ret = platform_driver_register(&sci_driver);
2820 if (unlikely(ret))
2821 uart_unregister_driver(&sci_uart_driver);
2822 }
2823
2824 return ret;
2825}
2826
2827static void __exit sci_exit(void)
2828{
2829 platform_driver_unregister(&sci_driver);
1da177e4
LT		 2830 uart_unregister_driver(&sci_uart_driver);
2831}
2832
7b6fd3bf
MD		 2833#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
2834early_platform_init_buffer("earlyprintk", &sci_driver,
2835 early_serial_buf, ARRAY_SIZE(early_serial_buf));
2836#endif
1da177e4
LT		 2837module_init(sci_init);
2838module_exit(sci_exit);
2839
e108b2ca 2840MODULE_LICENSE("GPL");
e169c139 2841MODULE_ALIAS("platform:sh-sci");
7f405f9c 2842MODULE_AUTHOR("Paul Mundt");
f303b364 2843MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver");
Linux 6.x block layer and io_uring tree(s)