projects / linux-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
serial: sh-sci: fix common SCIFB regmap definition
[linux-block.git] / drivers / tty / serial / sh-sci.c
CommitLineData
1da177e4 1/*
1da177e4
LT		 2 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
3 *
f43dc23d 4 * Copyright (C) 2002 - 2011 Paul Mundt
3ea6bc3d 5 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
1da177e4
LT		 6 *
7 * based off of the old drivers/char/sh-sci.c by:
8 *
9 * Copyright (C) 1999, 2000 Niibe Yutaka
10 * Copyright (C) 2000 Sugioka Toshinobu
11 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
12 * Modified to support SecureEdge. David McCullough (2002)
13 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
d89ddd1c 14 * Removed SH7300 support (Jul 2007).
1da177e4
LT		 15 *
16 * This file is subject to the terms and conditions of the GNU General Public
17 * License. See the file "COPYING" in the main directory of this archive
18 * for more details.
19 */
0b3d4ef6
PM		 20#if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
21#define SUPPORT_SYSRQ
22#endif
1da177e4
LT		 23
24#undef DEBUG
25
1da177e4
LT		 26#include <linux/module.h>
27#include <linux/errno.h>
4dc4c516 28#include <linux/sh_dma.h>
1da177e4
LT		 29#include <linux/timer.h>
30#include <linux/interrupt.h>
31#include <linux/tty.h>
32#include <linux/tty_flip.h>
33#include <linux/serial.h>
34#include <linux/major.h>
35#include <linux/string.h>
36#include <linux/sysrq.h>
1da177e4
LT		 37#include <linux/ioport.h>
38#include <linux/mm.h>
1da177e4
LT		 39#include <linux/init.h>
40#include <linux/delay.h>
41#include <linux/console.h>
e108b2ca 42#include <linux/platform_device.h>
96de1a8f 43#include <linux/serial_sci.h>
1da177e4 44#include <linux/notifier.h>
5e50d2d6 45#include <linux/pm_runtime.h>
1da177e4 46#include <linux/cpufreq.h>
85f094ec 47#include <linux/clk.h>
fa5da2f7 48#include <linux/ctype.h>
7ff731ae 49#include <linux/err.h>
73a19e4c 50#include <linux/dmaengine.h>
5beabc7f 51#include <linux/dma-mapping.h>
73a19e4c 52#include <linux/scatterlist.h>
5a0e3ad6 53#include <linux/slab.h>
50f0959a 54#include <linux/gpio.h>
85f094ec
PM		 55
56#ifdef CONFIG_SUPERH
1da177e4
LT		 57#include <asm/sh_bios.h>
58#endif
59
1da177e4
LT		 60#include "sh-sci.h"
61
e108b2ca
PM		 62struct sci_port {
63 struct uart_port port;
64
ce6738b6
PM		 65 /* Platform configuration */
66 struct plat_sci_port *cfg;
e108b2ca 67
e108b2ca
PM		 68 /* Break timer */
69 struct timer_list break_timer;
70 int break_flag;
1534a3b3 71
501b825d
MD		 72 /* Interface clock */
73 struct clk *iclk;
c7ed1ab3
PM		 74 /* Function clock */
75 struct clk *fclk;
edad1f20 76
9174fc8f 77 char *irqstr[SCIx_NR_IRQS];
50f0959a 78 char *gpiostr[SCIx_NR_FNS];
9174fc8f 79
73a19e4c
GL		 80 struct dma_chan *chan_tx;
81 struct dma_chan *chan_rx;
f43dc23d 82
73a19e4c 83#ifdef CONFIG_SERIAL_SH_SCI_DMA
73a19e4c
GL		 84 struct dma_async_tx_descriptor *desc_tx;
85 struct dma_async_tx_descriptor *desc_rx[2];
86 dma_cookie_t cookie_tx;
87 dma_cookie_t cookie_rx[2];
88 dma_cookie_t active_rx;
89 struct scatterlist sg_tx;
90 unsigned int sg_len_tx;
91 struct scatterlist sg_rx[2];
92 size_t buf_len_rx;
93 struct sh_dmae_slave param_tx;
94 struct sh_dmae_slave param_rx;
95 struct work_struct work_tx;
96 struct work_struct work_rx;
97 struct timer_list rx_timer;
3089f381 98 unsigned int rx_timeout;
73a19e4c 99#endif
e552de24 100
d535a230 101 struct notifier_block freq_transition;
e108b2ca
PM		 102};
103
1da177e4 104/* Function prototypes */
d535a230 105static void sci_start_tx(struct uart_port *port);
b129a8cc 106static void sci_stop_tx(struct uart_port *port);
d535a230 107static void sci_start_rx(struct uart_port *port);
1da177e4 108
e108b2ca 109#define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
b7a76e4b 110
e108b2ca
PM		 111static struct sci_port sci_ports[SCI_NPORTS];
112static struct uart_driver sci_uart_driver;
1da177e4 113
e7c98dc7
MT		 114static inline struct sci_port *
115to_sci_port(struct uart_port *uart)
116{
117 return container_of(uart, struct sci_port, port);
118}
119
61a6976b
PM		 120struct plat_sci_reg {
121 u8 offset, size;
122};
123
124/* Helper for invalidating specific entries of an inherited map. */
125#define sci_reg_invalid { .offset = 0, .size = 0 }
126
127static struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = {
128 [SCIx_PROBE_REGTYPE] = {
129 [0 ... SCIx_NR_REGS - 1] = sci_reg_invalid,
130 },
131
132 /*
133 * Common SCI definitions, dependent on the port's regshift
134 * value.
135 */
136 [SCIx_SCI_REGTYPE] = {
137 [SCSMR] = { 0x00, 8 },
138 [SCBRR] = { 0x01, 8 },
139 [SCSCR] = { 0x02, 8 },
140 [SCxTDR] = { 0x03, 8 },
141 [SCxSR] = { 0x04, 8 },
142 [SCxRDR] = { 0x05, 8 },
143 [SCFCR] = sci_reg_invalid,
144 [SCFDR] = sci_reg_invalid,
145 [SCTFDR] = sci_reg_invalid,
146 [SCRFDR] = sci_reg_invalid,
147 [SCSPTR] = sci_reg_invalid,
148 [SCLSR] = sci_reg_invalid,
149 },
150
151 /*
152 * Common definitions for legacy IrDA ports, dependent on
153 * regshift value.
154 */
155 [SCIx_IRDA_REGTYPE] = {
156 [SCSMR] = { 0x00, 8 },
157 [SCBRR] = { 0x01, 8 },
158 [SCSCR] = { 0x02, 8 },
159 [SCxTDR] = { 0x03, 8 },
160 [SCxSR] = { 0x04, 8 },
161 [SCxRDR] = { 0x05, 8 },
162 [SCFCR] = { 0x06, 8 },
163 [SCFDR] = { 0x07, 16 },
164 [SCTFDR] = sci_reg_invalid,
165 [SCRFDR] = sci_reg_invalid,
166 [SCSPTR] = sci_reg_invalid,
167 [SCLSR] = sci_reg_invalid,
168 },
169
170 /*
171 * Common SCIFA definitions.
172 */
173 [SCIx_SCIFA_REGTYPE] = {
174 [SCSMR] = { 0x00, 16 },
175 [SCBRR] = { 0x04, 8 },
176 [SCSCR] = { 0x08, 16 },
177 [SCxTDR] = { 0x20, 8 },
178 [SCxSR] = { 0x14, 16 },
179 [SCxRDR] = { 0x24, 8 },
180 [SCFCR] = { 0x18, 16 },
181 [SCFDR] = { 0x1c, 16 },
182 [SCTFDR] = sci_reg_invalid,
183 [SCRFDR] = sci_reg_invalid,
184 [SCSPTR] = sci_reg_invalid,
185 [SCLSR] = sci_reg_invalid,
186 },
187
188 /*
189 * Common SCIFB definitions.
190 */
191 [SCIx_SCIFB_REGTYPE] = {
192 [SCSMR] = { 0x00, 16 },
193 [SCBRR] = { 0x04, 8 },
194 [SCSCR] = { 0x08, 16 },
195 [SCxTDR] = { 0x40, 8 },
196 [SCxSR] = { 0x14, 16 },
197 [SCxRDR] = { 0x60, 8 },
198 [SCFCR] = { 0x18, 16 },
8c66d6d2
TY		 199 [SCFDR] = sci_reg_invalid,
200 [SCTFDR] = { 0x38, 16 },
201 [SCRFDR] = { 0x3c, 16 },
61a6976b
PM		 202 [SCSPTR] = sci_reg_invalid,
203 [SCLSR] = sci_reg_invalid,
204 },
205
3af1f8a4
PE		 206 /*
207 * Common SH-2(A) SCIF definitions for ports with FIFO data
208 * count registers.
209 */
210 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = {
211 [SCSMR] = { 0x00, 16 },
212 [SCBRR] = { 0x04, 8 },
213 [SCSCR] = { 0x08, 16 },
214 [SCxTDR] = { 0x0c, 8 },
215 [SCxSR] = { 0x10, 16 },
216 [SCxRDR] = { 0x14, 8 },
217 [SCFCR] = { 0x18, 16 },
218 [SCFDR] = { 0x1c, 16 },
219 [SCTFDR] = sci_reg_invalid,
220 [SCRFDR] = sci_reg_invalid,
221 [SCSPTR] = { 0x20, 16 },
222 [SCLSR] = { 0x24, 16 },
223 },
224
61a6976b
PM		 225 /*
226 * Common SH-3 SCIF definitions.
227 */
228 [SCIx_SH3_SCIF_REGTYPE] = {
229 [SCSMR] = { 0x00, 8 },
230 [SCBRR] = { 0x02, 8 },
231 [SCSCR] = { 0x04, 8 },
232 [SCxTDR] = { 0x06, 8 },
233 [SCxSR] = { 0x08, 16 },
234 [SCxRDR] = { 0x0a, 8 },
235 [SCFCR] = { 0x0c, 8 },
236 [SCFDR] = { 0x0e, 16 },
237 [SCTFDR] = sci_reg_invalid,
238 [SCRFDR] = sci_reg_invalid,
239 [SCSPTR] = sci_reg_invalid,
240 [SCLSR] = sci_reg_invalid,
241 },
242
243 /*
244 * Common SH-4(A) SCIF(B) definitions.
245 */
246 [SCIx_SH4_SCIF_REGTYPE] = {
247 [SCSMR] = { 0x00, 16 },
248 [SCBRR] = { 0x04, 8 },
249 [SCSCR] = { 0x08, 16 },
250 [SCxTDR] = { 0x0c, 8 },
251 [SCxSR] = { 0x10, 16 },
252 [SCxRDR] = { 0x14, 8 },
253 [SCFCR] = { 0x18, 16 },
254 [SCFDR] = { 0x1c, 16 },
255 [SCTFDR] = sci_reg_invalid,
256 [SCRFDR] = sci_reg_invalid,
257 [SCSPTR] = { 0x20, 16 },
258 [SCLSR] = { 0x24, 16 },
259 },
260
261 /*
262 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR
263 * register.
264 */
265 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = {
266 [SCSMR] = { 0x00, 16 },
267 [SCBRR] = { 0x04, 8 },
268 [SCSCR] = { 0x08, 16 },
269 [SCxTDR] = { 0x0c, 8 },
270 [SCxSR] = { 0x10, 16 },
271 [SCxRDR] = { 0x14, 8 },
272 [SCFCR] = { 0x18, 16 },
273 [SCFDR] = { 0x1c, 16 },
274 [SCTFDR] = sci_reg_invalid,
275 [SCRFDR] = sci_reg_invalid,
276 [SCSPTR] = sci_reg_invalid,
277 [SCLSR] = { 0x24, 16 },
278 },
279
280 /*
281 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data
282 * count registers.
283 */
284 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = {
285 [SCSMR] = { 0x00, 16 },
286 [SCBRR] = { 0x04, 8 },
287 [SCSCR] = { 0x08, 16 },
288 [SCxTDR] = { 0x0c, 8 },
289 [SCxSR] = { 0x10, 16 },
290 [SCxRDR] = { 0x14, 8 },
291 [SCFCR] = { 0x18, 16 },
292 [SCFDR] = { 0x1c, 16 },
293 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */
294 [SCRFDR] = { 0x20, 16 },
295 [SCSPTR] = { 0x24, 16 },
296 [SCLSR] = { 0x28, 16 },
297 },
298
299 /*
300 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR
301 * registers.
302 */
303 [SCIx_SH7705_SCIF_REGTYPE] = {
304 [SCSMR] = { 0x00, 16 },
305 [SCBRR] = { 0x04, 8 },
306 [SCSCR] = { 0x08, 16 },
307 [SCxTDR] = { 0x20, 8 },
308 [SCxSR] = { 0x14, 16 },
309 [SCxRDR] = { 0x24, 8 },
310 [SCFCR] = { 0x18, 16 },
311 [SCFDR] = { 0x1c, 16 },
312 [SCTFDR] = sci_reg_invalid,
313 [SCRFDR] = sci_reg_invalid,
314 [SCSPTR] = sci_reg_invalid,
315 [SCLSR] = sci_reg_invalid,
316 },
317};
318
72b294cf
PM		 319#define sci_getreg(up, offset) (sci_regmap[to_sci_port(up)->cfg->regtype] + offset)
320
61a6976b
PM		 321/*
322 * The "offset" here is rather misleading, in that it refers to an enum
323 * value relative to the port mapping rather than the fixed offset
324 * itself, which needs to be manually retrieved from the platform's
325 * register map for the given port.
326 */
327static unsigned int sci_serial_in(struct uart_port *p, int offset)
328{
72b294cf 329 struct plat_sci_reg *reg = sci_getreg(p, offset);
61a6976b
PM		 330
331 if (reg->size == 8)
332 return ioread8(p->membase + (reg->offset << p->regshift));
333 else if (reg->size == 16)
334 return ioread16(p->membase + (reg->offset << p->regshift));
335 else
336 WARN(1, "Invalid register access\n");
337
338 return 0;
339}
340
341static void sci_serial_out(struct uart_port *p, int offset, int value)
342{
72b294cf 343 struct plat_sci_reg *reg = sci_getreg(p, offset);
61a6976b
PM		 344
345 if (reg->size == 8)
346 iowrite8(value, p->membase + (reg->offset << p->regshift));
347 else if (reg->size == 16)
348 iowrite16(value, p->membase + (reg->offset << p->regshift));
349 else
350 WARN(1, "Invalid register access\n");
351}
352
61a6976b
PM		 353static int sci_probe_regmap(struct plat_sci_port *cfg)
354{
355 switch (cfg->type) {
356 case PORT_SCI:
357 cfg->regtype = SCIx_SCI_REGTYPE;
358 break;
359 case PORT_IRDA:
360 cfg->regtype = SCIx_IRDA_REGTYPE;
361 break;
362 case PORT_SCIFA:
363 cfg->regtype = SCIx_SCIFA_REGTYPE;
364 break;
365 case PORT_SCIFB:
366 cfg->regtype = SCIx_SCIFB_REGTYPE;
367 break;
368 case PORT_SCIF:
369 /*
370 * The SH-4 is a bit of a misnomer here, although that's
371 * where this particular port layout originated. This
372 * configuration (or some slight variation thereof)
373 * remains the dominant model for all SCIFs.
374 */
375 cfg->regtype = SCIx_SH4_SCIF_REGTYPE;
376 break;
377 default:
378 printk(KERN_ERR "Can't probe register map for given port\n");
379 return -EINVAL;
380 }
381
382 return 0;
383}
384
23241d43
PM		 385static void sci_port_enable(struct sci_port *sci_port)
386{
387 if (!sci_port->port.dev)
388 return;
389
390 pm_runtime_get_sync(sci_port->port.dev);
391
392 clk_enable(sci_port->iclk);
393 sci_port->port.uartclk = clk_get_rate(sci_port->iclk);
394 clk_enable(sci_port->fclk);
395}
396
397static void sci_port_disable(struct sci_port *sci_port)
398{
399 if (!sci_port->port.dev)
400 return;
401
402 clk_disable(sci_port->fclk);
403 clk_disable(sci_port->iclk);
404
405 pm_runtime_put_sync(sci_port->port.dev);
406}
407
07d2a1a1 408#if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
1f6fd5c9
PM		 409
410#ifdef CONFIG_CONSOLE_POLL
07d2a1a1 411static int sci_poll_get_char(struct uart_port *port)
1da177e4 412{
1da177e4
LT		 413 unsigned short status;
414 int c;
415
e108b2ca 416 do {
b12bb29f 417 status = serial_port_in(port, SCxSR);
1da177e4 418 if (status & SCxSR_ERRORS(port)) {
b12bb29f 419 serial_port_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
1da177e4
LT		 420 continue;
421 }
3f255eb3
JW		 422 break;
423 } while (1);
424
425 if (!(status & SCxSR_RDxF(port)))
426 return NO_POLL_CHAR;
07d2a1a1 427
b12bb29f 428 c = serial_port_in(port, SCxRDR);
07d2a1a1 429
e7c98dc7 430 /* Dummy read */
b12bb29f
PM		 431 serial_port_in(port, SCxSR);
432 serial_port_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
1da177e4
LT		 433
434 return c;
435}
1f6fd5c9 436#endif
1da177e4 437
07d2a1a1 438static void sci_poll_put_char(struct uart_port *port, unsigned char c)
1da177e4 439{
1da177e4
LT		 440 unsigned short status;
441
1da177e4 442 do {
b12bb29f 443 status = serial_port_in(port, SCxSR);
1da177e4
LT		 444 } while (!(status & SCxSR_TDxE(port)));
445
b12bb29f
PM		 446 serial_port_out(port, SCxTDR, c);
447 serial_port_out(port, SCxSR, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
1da177e4 448}
07d2a1a1 449#endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE */
1da177e4 450
61a6976b 451static void sci_init_pins(struct uart_port *port, unsigned int cflag)
1da177e4 452{
61a6976b
PM		 453 struct sci_port *s = to_sci_port(port);
454 struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR;
1da177e4 455
61a6976b
PM		 456 /*
457 * Use port-specific handler if provided.
458 */
459 if (s->cfg->ops && s->cfg->ops->init_pins) {
460 s->cfg->ops->init_pins(port, cflag);
461 return;
1da177e4 462 }
41504c39 463
61a6976b
PM		 464 /*
465 * For the generic path SCSPTR is necessary. Bail out if that's
466 * unavailable, too.
467 */
468 if (!reg->size)
469 return;
41504c39 470
faf02f8f
PM		 471 if ((s->cfg->capabilities & SCIx_HAVE_RTSCTS) &&
472 ((!(cflag & CRTSCTS)))) {
473 unsigned short status;
474
b12bb29f 475 status = serial_port_in(port, SCSPTR);
faf02f8f
PM		 476 status &= ~SCSPTR_CTSIO;
477 status |= SCSPTR_RTSIO;
b12bb29f 478 serial_port_out(port, SCSPTR, status); /* Set RTS = 1 */
faf02f8f 479 }
d5701647 480}
e108b2ca 481
72b294cf 482static int sci_txfill(struct uart_port *port)
e108b2ca 483{
72b294cf 484 struct plat_sci_reg *reg;
e108b2ca 485
72b294cf
PM		 486 reg = sci_getreg(port, SCTFDR);
487 if (reg->size)
63f7ad11 488 return serial_port_in(port, SCTFDR) & ((port->fifosize << 1) - 1);
c63847a3 489
72b294cf
PM		 490 reg = sci_getreg(port, SCFDR);
491 if (reg->size)
b12bb29f 492 return serial_port_in(port, SCFDR) >> 8;
d1d4b10c 493
b12bb29f 494 return !(serial_port_in(port, SCxSR) & SCI_TDRE);
e108b2ca
PM		 495}
496
73a19e4c
GL		 497static int sci_txroom(struct uart_port *port)
498{
72b294cf 499 return port->fifosize - sci_txfill(port);
73a19e4c
GL		 500}
501
502static int sci_rxfill(struct uart_port *port)
e108b2ca 503{
72b294cf
PM		 504 struct plat_sci_reg *reg;
505
506 reg = sci_getreg(port, SCRFDR);
507 if (reg->size)
63f7ad11 508 return serial_port_in(port, SCRFDR) & ((port->fifosize << 1) - 1);
72b294cf
PM		 509
510 reg = sci_getreg(port, SCFDR);
511 if (reg->size)
b12bb29f 512 return serial_port_in(port, SCFDR) & ((port->fifosize << 1) - 1);
72b294cf 513
b12bb29f 514 return (serial_port_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
e108b2ca
PM		 515}
516
514820eb
PM		 517/*
518 * SCI helper for checking the state of the muxed port/RXD pins.
519 */
520static inline int sci_rxd_in(struct uart_port *port)
521{
522 struct sci_port *s = to_sci_port(port);
523
524 if (s->cfg->port_reg <= 0)
525 return 1;
526
0dd4d5cb
PM		 527 /* Cast for ARM damage */
528 return !!__raw_readb((void __iomem *)s->cfg->port_reg);
514820eb
PM		 529}
530
1da177e4
LT		 531/* ********************************************************************** *
532 * the interrupt related routines *
533 * ********************************************************************** */
534
535static void sci_transmit_chars(struct uart_port *port)
536{
ebd2c8f6 537 struct circ_buf *xmit = &port->state->xmit;
1da177e4 538 unsigned int stopped = uart_tx_stopped(port);
1da177e4
LT		 539 unsigned short status;
540 unsigned short ctrl;
e108b2ca 541 int count;
1da177e4 542
b12bb29f 543 status = serial_port_in(port, SCxSR);
1da177e4 544 if (!(status & SCxSR_TDxE(port))) {
b12bb29f 545 ctrl = serial_port_in(port, SCSCR);
e7c98dc7 546 if (uart_circ_empty(xmit))
8e698614 547 ctrl &= ~SCSCR_TIE;
e7c98dc7 548 else
8e698614 549 ctrl |= SCSCR_TIE;
b12bb29f 550 serial_port_out(port, SCSCR, ctrl);
1da177e4
LT		 551 return;
552 }
553
72b294cf 554 count = sci_txroom(port);
1da177e4
LT		 555
556 do {
557 unsigned char c;
558
559 if (port->x_char) {
560 c = port->x_char;
561 port->x_char = 0;
562 } else if (!uart_circ_empty(xmit) && !stopped) {
563 c = xmit->buf[xmit->tail];
564 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
565 } else {
566 break;
567 }
568
b12bb29f 569 serial_port_out(port, SCxTDR, c);
1da177e4
LT		 570
571 port->icount.tx++;
572 } while (--count > 0);
573
b12bb29f 574 serial_port_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
1da177e4
LT		 575
576 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
577 uart_write_wakeup(port);
578 if (uart_circ_empty(xmit)) {
b129a8cc 579 sci_stop_tx(port);
1da177e4 580 } else {
b12bb29f 581 ctrl = serial_port_in(port, SCSCR);
1da177e4 582
1a22f08d 583 if (port->type != PORT_SCI) {
b12bb29f
PM		 584 serial_port_in(port, SCxSR); /* Dummy read */
585 serial_port_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
1da177e4 586 }
1da177e4 587
8e698614 588 ctrl |= SCSCR_TIE;
b12bb29f 589 serial_port_out(port, SCSCR, ctrl);
1da177e4
LT		 590 }
591}
592
593/* On SH3, SCIF may read end-of-break as a space->mark char */
e7c98dc7 594#define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); })
1da177e4 595
94c8b6db 596static void sci_receive_chars(struct uart_port *port)
1da177e4 597{
e7c98dc7 598 struct sci_port *sci_port = to_sci_port(port);
ebd2c8f6 599 struct tty_struct *tty = port->state->port.tty;
1da177e4
LT		 600 int i, count, copied = 0;
601 unsigned short status;
33f0f88f 602 unsigned char flag;
1da177e4 603
b12bb29f 604 status = serial_port_in(port, SCxSR);
1da177e4
LT		 605 if (!(status & SCxSR_RDxF(port)))
606 return;
607
608 while (1) {
1da177e4 609 /* Don't copy more bytes than there is room for in the buffer */
72b294cf 610 count = tty_buffer_request_room(tty, sci_rxfill(port));
1da177e4
LT		 611
612 /* If for any reason we can't copy more data, we're done! */
613 if (count == 0)
614 break;
615
616 if (port->type == PORT_SCI) {
b12bb29f 617 char c = serial_port_in(port, SCxRDR);
e7c98dc7
MT		 618 if (uart_handle_sysrq_char(port, c) ||
619 sci_port->break_flag)
1da177e4 620 count = 0;
e7c98dc7 621 else
e108b2ca 622 tty_insert_flip_char(tty, c, TTY_NORMAL);
1da177e4 623 } else {
e7c98dc7 624 for (i = 0; i < count; i++) {
b12bb29f 625 char c = serial_port_in(port, SCxRDR);
d97fbbed 626
b12bb29f 627 status = serial_port_in(port, SCxSR);
1da177e4
LT		 628#if defined(CONFIG_CPU_SH3)
629 /* Skip "chars" during break */
e108b2ca 630 if (sci_port->break_flag) {
1da177e4
LT		 631 if ((c == 0) &&
632 (status & SCxSR_FER(port))) {
633 count--; i--;
634 continue;
635 }
e108b2ca 636
1da177e4 637 /* Nonzero => end-of-break */
762c69e3 638 dev_dbg(port->dev, "debounce<%02x>\n", c);
e108b2ca
PM		 639 sci_port->break_flag = 0;
640
1da177e4
LT		 641 if (STEPFN(c)) {
642 count--; i--;
643 continue;
644 }
645 }
646#endif /* CONFIG_CPU_SH3 */
7d12e780 647 if (uart_handle_sysrq_char(port, c)) {
1da177e4
LT		 648 count--; i--;
649 continue;
650 }
651
652 /* Store data and status */
73a19e4c 653 if (status & SCxSR_FER(port)) {
33f0f88f 654 flag = TTY_FRAME;
d97fbbed 655 port->icount.frame++;
762c69e3 656 dev_notice(port->dev, "frame error\n");
73a19e4c 657 } else if (status & SCxSR_PER(port)) {
33f0f88f 658 flag = TTY_PARITY;
d97fbbed 659 port->icount.parity++;
762c69e3 660 dev_notice(port->dev, "parity error\n");
33f0f88f
AC		 661 } else
662 flag = TTY_NORMAL;
762c69e3 663
33f0f88f 664 tty_insert_flip_char(tty, c, flag);
1da177e4
LT		 665 }
666 }
667
b12bb29f
PM		 668 serial_port_in(port, SCxSR); /* dummy read */
669 serial_port_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
1da177e4 670
1da177e4
LT		 671 copied += count;
672 port->icount.rx += count;
673 }
674
675 if (copied) {
676 /* Tell the rest of the system the news. New characters! */
677 tty_flip_buffer_push(tty);
678 } else {
b12bb29f
PM		 679 serial_port_in(port, SCxSR); /* dummy read */
680 serial_port_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
1da177e4
LT		 681 }
682}
683
684#define SCI_BREAK_JIFFIES (HZ/20)
94c8b6db
PM		 685
686/*
687 * The sci generates interrupts during the break,
1da177e4
LT		 688 * 1 per millisecond or so during the break period, for 9600 baud.
689 * So dont bother disabling interrupts.
690 * But dont want more than 1 break event.
691 * Use a kernel timer to periodically poll the rx line until
692 * the break is finished.
693 */
94c8b6db 694static inline void sci_schedule_break_timer(struct sci_port *port)
1da177e4 695{
bc9b3f5c 696 mod_timer(&port->break_timer, jiffies + SCI_BREAK_JIFFIES);
1da177e4 697}
94c8b6db 698
1da177e4
LT		 699/* Ensure that two consecutive samples find the break over. */
700static void sci_break_timer(unsigned long data)
701{
e108b2ca
PM		 702 struct sci_port *port = (struct sci_port *)data;
703
23241d43 704 sci_port_enable(port);
5e50d2d6 705
e108b2ca 706 if (sci_rxd_in(&port->port) == 0) {
1da177e4 707 port->break_flag = 1;
e108b2ca
PM		 708 sci_schedule_break_timer(port);
709 } else if (port->break_flag == 1) {
1da177e4
LT		 710 /* break is over. */
711 port->break_flag = 2;
e108b2ca
PM		 712 sci_schedule_break_timer(port);
713 } else
714 port->break_flag = 0;
5e50d2d6 715
23241d43 716 sci_port_disable(port);
1da177e4
LT		 717}
718
94c8b6db 719static int sci_handle_errors(struct uart_port *port)
1da177e4
LT		 720{
721 int copied = 0;
b12bb29f 722 unsigned short status = serial_port_in(port, SCxSR);
ebd2c8f6 723 struct tty_struct *tty = port->state->port.tty;
debf9507 724 struct sci_port *s = to_sci_port(port);
1da177e4 725
debf9507
PM		 726 /*
727 * Handle overruns, if supported.
728 */
729 if (s->cfg->overrun_bit != SCIx_NOT_SUPPORTED) {
730 if (status & (1 << s->cfg->overrun_bit)) {
d97fbbed
PM		 731 port->icount.overrun++;
732
debf9507
PM		 733 /* overrun error */
734 if (tty_insert_flip_char(tty, 0, TTY_OVERRUN))
735 copied++;
762c69e3 736
debf9507
PM		 737 dev_notice(port->dev, "overrun error");
738 }
1da177e4
LT		 739 }
740
e108b2ca 741 if (status & SCxSR_FER(port)) {
1da177e4
LT		 742 if (sci_rxd_in(port) == 0) {
743 /* Notify of BREAK */
e7c98dc7 744 struct sci_port *sci_port = to_sci_port(port);
e108b2ca
PM		 745
746 if (!sci_port->break_flag) {
d97fbbed
PM		 747 port->icount.brk++;
748
e108b2ca
PM		 749 sci_port->break_flag = 1;
750 sci_schedule_break_timer(sci_port);
751
1da177e4 752 /* Do sysrq handling. */
e108b2ca 753 if (uart_handle_break(port))
1da177e4 754 return 0;
762c69e3
PM		 755
756 dev_dbg(port->dev, "BREAK detected\n");
757
e108b2ca 758 if (tty_insert_flip_char(tty, 0, TTY_BREAK))
e7c98dc7
MT		 759 copied++;
760 }
761
e108b2ca 762 } else {
1da177e4 763 /* frame error */
d97fbbed
PM		 764 port->icount.frame++;
765
e108b2ca 766 if (tty_insert_flip_char(tty, 0, TTY_FRAME))
33f0f88f 767 copied++;
762c69e3
PM		 768
769 dev_notice(port->dev, "frame error\n");
1da177e4
LT		 770 }
771 }
772
e108b2ca 773 if (status & SCxSR_PER(port)) {
1da177e4 774 /* parity error */
d97fbbed
PM		 775 port->icount.parity++;
776
e108b2ca
PM		 777 if (tty_insert_flip_char(tty, 0, TTY_PARITY))
778 copied++;
762c69e3
PM		 779
780 dev_notice(port->dev, "parity error");
1da177e4
LT		 781 }
782
33f0f88f 783 if (copied)
1da177e4 784 tty_flip_buffer_push(tty);
1da177e4
LT		 785
786 return copied;
787}
788
94c8b6db 789static int sci_handle_fifo_overrun(struct uart_port *port)
d830fa45 790{
ebd2c8f6 791 struct tty_struct *tty = port->state->port.tty;
debf9507 792 struct sci_port *s = to_sci_port(port);
4b8c59a3 793 struct plat_sci_reg *reg;
d830fa45
PM		 794 int copied = 0;
795
4b8c59a3
PM		 796 reg = sci_getreg(port, SCLSR);
797 if (!reg->size)
d830fa45
PM		 798 return 0;
799
b12bb29f
PM		 800 if ((serial_port_in(port, SCLSR) & (1 << s->cfg->overrun_bit))) {
801 serial_port_out(port, SCLSR, 0);
d830fa45 802
d97fbbed
PM		 803 port->icount.overrun++;
804
d830fa45
PM		 805 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
806 tty_flip_buffer_push(tty);
807
808 dev_notice(port->dev, "overrun error\n");
809 copied++;
810 }
811
812 return copied;
813}
814
94c8b6db 815static int sci_handle_breaks(struct uart_port *port)
1da177e4
LT		 816{
817 int copied = 0;
b12bb29f 818 unsigned short status = serial_port_in(port, SCxSR);
ebd2c8f6 819 struct tty_struct *tty = port->state->port.tty;
a5660ada 820 struct sci_port *s = to_sci_port(port);
1da177e4 821
0b3d4ef6
PM		 822 if (uart_handle_break(port))
823 return 0;
824
b7a76e4b 825 if (!s->break_flag && status & SCxSR_BRK(port)) {
1da177e4
LT		 826#if defined(CONFIG_CPU_SH3)
827 /* Debounce break */
828 s->break_flag = 1;
829#endif
d97fbbed
PM		 830
831 port->icount.brk++;
832
1da177e4 833 /* Notify of BREAK */
e108b2ca 834 if (tty_insert_flip_char(tty, 0, TTY_BREAK))
33f0f88f 835 copied++;
762c69e3
PM		 836
837 dev_dbg(port->dev, "BREAK detected\n");
1da177e4
LT		 838 }
839
33f0f88f 840 if (copied)
1da177e4 841 tty_flip_buffer_push(tty);
e108b2ca 842
d830fa45
PM		 843 copied += sci_handle_fifo_overrun(port);
844
1da177e4
LT		 845 return copied;
846}
847
73a19e4c 848static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
1da177e4 849{
73a19e4c
GL		 850#ifdef CONFIG_SERIAL_SH_SCI_DMA
851 struct uart_port *port = ptr;
852 struct sci_port *s = to_sci_port(port);
853
854 if (s->chan_rx) {
b12bb29f
PM		 855 u16 scr = serial_port_in(port, SCSCR);
856 u16 ssr = serial_port_in(port, SCxSR);
73a19e4c
GL		 857
858 /* Disable future Rx interrupts */
d1d4b10c 859 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
3089f381
GL		 860 disable_irq_nosync(irq);
861 scr |= 0x4000;
862 } else {
f43dc23d 863 scr &= ~SCSCR_RIE;
3089f381 864 }
b12bb29f 865 serial_port_out(port, SCSCR, scr);
73a19e4c 866 /* Clear current interrupt */
b12bb29f 867 serial_port_out(port, SCxSR, ssr & ~(1 | SCxSR_RDxF(port)));
3089f381
GL		 868 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u jiffies\n",
869 jiffies, s->rx_timeout);
870 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
73a19e4c
GL		 871
872 return IRQ_HANDLED;
873 }
874#endif
875
1da177e4
LT		 876 /* I think sci_receive_chars has to be called irrespective
877 * of whether the I_IXOFF is set, otherwise, how is the interrupt
878 * to be disabled?
879 */
73a19e4c 880 sci_receive_chars(ptr);
1da177e4
LT		 881
882 return IRQ_HANDLED;
883}
884
7d12e780 885static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
1da177e4
LT		 886{
887 struct uart_port *port = ptr;
fd78a76a 888 unsigned long flags;
1da177e4 889
fd78a76a 890 spin_lock_irqsave(&port->lock, flags);
1da177e4 891 sci_transmit_chars(port);
fd78a76a 892 spin_unlock_irqrestore(&port->lock, flags);
1da177e4
LT		 893
894 return IRQ_HANDLED;
895}
896
7d12e780 897static irqreturn_t sci_er_interrupt(int irq, void *ptr)
1da177e4
LT		 898{
899 struct uart_port *port = ptr;
900
901 /* Handle errors */
902 if (port->type == PORT_SCI) {
903 if (sci_handle_errors(port)) {
904 /* discard character in rx buffer */
b12bb29f
PM		 905 serial_port_in(port, SCxSR);
906 serial_port_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
1da177e4
LT		 907 }
908 } else {
d830fa45 909 sci_handle_fifo_overrun(port);
7d12e780 910 sci_rx_interrupt(irq, ptr);
1da177e4
LT		 911 }
912
b12bb29f 913 serial_port_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
1da177e4
LT		 914
915 /* Kick the transmission */
7d12e780 916 sci_tx_interrupt(irq, ptr);
1da177e4
LT		 917
918 return IRQ_HANDLED;
919}
920
7d12e780 921static irqreturn_t sci_br_interrupt(int irq, void *ptr)
1da177e4
LT		 922{
923 struct uart_port *port = ptr;
924
925 /* Handle BREAKs */
926 sci_handle_breaks(port);
b12bb29f 927 serial_port_out(port, SCxSR, SCxSR_BREAK_CLEAR(port));
1da177e4
LT		 928
929 return IRQ_HANDLED;
930}
931
f43dc23d
PM		 932static inline unsigned long port_rx_irq_mask(struct uart_port *port)
933{
934 /*
935 * Not all ports (such as SCIFA) will support REIE. Rather than
936 * special-casing the port type, we check the port initialization
937 * IRQ enable mask to see whether the IRQ is desired at all. If
938 * it's unset, it's logically inferred that there's no point in
939 * testing for it.
940 */
ce6738b6 941 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE);
f43dc23d
PM		 942}
943
7d12e780 944static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
1da177e4 945{
44e18e9e 946 unsigned short ssr_status, scr_status, err_enabled;
a8884e34 947 struct uart_port *port = ptr;
73a19e4c 948 struct sci_port *s = to_sci_port(port);
a8884e34 949 irqreturn_t ret = IRQ_NONE;
1da177e4 950
b12bb29f
PM		 951 ssr_status = serial_port_in(port, SCxSR);
952 scr_status = serial_port_in(port, SCSCR);
f43dc23d 953 err_enabled = scr_status & port_rx_irq_mask(port);
1da177e4
LT		 954
955 /* Tx Interrupt */
f43dc23d 956 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) &&
73a19e4c 957 !s->chan_tx)
a8884e34 958 ret = sci_tx_interrupt(irq, ptr);
f43dc23d 959
73a19e4c
GL		 960 /*
961 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF /
962 * DR flags
963 */
964 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&
f43dc23d 965 (scr_status & SCSCR_RIE))
a8884e34 966 ret = sci_rx_interrupt(irq, ptr);
f43dc23d 967
1da177e4 968 /* Error Interrupt */
dd4da3a5 969 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
a8884e34 970 ret = sci_er_interrupt(irq, ptr);
f43dc23d 971
1da177e4 972 /* Break Interrupt */
dd4da3a5 973 if ((ssr_status & SCxSR_BRK(port)) && err_enabled)
a8884e34 974 ret = sci_br_interrupt(irq, ptr);
1da177e4 975
a8884e34 976 return ret;
1da177e4
LT		 977}
978
1da177e4 979/*
25985edc 980 * Here we define a transition notifier so that we can update all of our
1da177e4
LT		 981 * ports' baud rate when the peripheral clock changes.
982 */
e108b2ca
PM		 983static int sci_notifier(struct notifier_block *self,
984 unsigned long phase, void *p)
1da177e4 985{
e552de24
MD		 986 struct sci_port *sci_port;
987 unsigned long flags;
1da177e4 988
d535a230
PM		 989 sci_port = container_of(self, struct sci_port, freq_transition);
990
1da177e4 991 if ((phase == CPUFREQ_POSTCHANGE) ||
e552de24 992 (phase == CPUFREQ_RESUMECHANGE)) {
d535a230 993 struct uart_port *port = &sci_port->port;
073e84c9 994
d535a230
PM		 995 spin_lock_irqsave(&port->lock, flags);
996 port->uartclk = clk_get_rate(sci_port->iclk);
997 spin_unlock_irqrestore(&port->lock, flags);
e552de24 998 }
1da177e4 999
1da177e4
LT		 1000 return NOTIFY_OK;
1001}
501b825d 1002
9174fc8f
PM		 1003static struct sci_irq_desc {
1004 const char *desc;
1005 irq_handler_t handler;
1006} sci_irq_desc[] = {
1007 /*
1008 * Split out handlers, the default case.
1009 */
1010 [SCIx_ERI_IRQ] = {
1011 .desc = "rx err",
1012 .handler = sci_er_interrupt,
1013 },
1014
1015 [SCIx_RXI_IRQ] = {
1016 .desc = "rx full",
1017 .handler = sci_rx_interrupt,
1018 },
1019
1020 [SCIx_TXI_IRQ] = {
1021 .desc = "tx empty",
1022 .handler = sci_tx_interrupt,
1023 },
1024
1025 [SCIx_BRI_IRQ] = {
1026 .desc = "break",
1027 .handler = sci_br_interrupt,
1028 },
1029
1030 /*
1031 * Special muxed handler.
1032 */
1033 [SCIx_MUX_IRQ] = {
1034 .desc = "mux",
1035 .handler = sci_mpxed_interrupt,
1036 },
1037};
1038
1da177e4
LT		 1039static int sci_request_irq(struct sci_port *port)
1040{
9174fc8f
PM		 1041 struct uart_port *up = &port->port;
1042 int i, j, ret = 0;
1043
1044 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) {
1045 struct sci_irq_desc *desc;
1046 unsigned int irq;
1047
1048 if (SCIx_IRQ_IS_MUXED(port)) {
1049 i = SCIx_MUX_IRQ;
1050 irq = up->irq;
0e8963de 1051 } else {
9174fc8f
PM		 1052 irq = port->cfg->irqs[i];
1053
0e8963de
PM		 1054 /*
1055 * Certain port types won't support all of the
1056 * available interrupt sources.
1057 */
1058 if (unlikely(!irq))
1059 continue;
1060 }
1061
9174fc8f
PM		 1062 desc = sci_irq_desc + i;
1063 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s",
1064 dev_name(up->dev), desc->desc);
1065 if (!port->irqstr[j]) {
1066 dev_err(up->dev, "Failed to allocate %s IRQ string\n",
1067 desc->desc);
1068 goto out_nomem;
1da177e4 1069 }
9174fc8f
PM		 1070
1071 ret = request_irq(irq, desc->handler, up->irqflags,
1072 port->irqstr[j], port);
1073 if (unlikely(ret)) {
1074 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc);
1075 goto out_noirq;
1da177e4
LT		 1076 }
1077 }
1078
1079 return 0;
9174fc8f
PM		 1080
1081out_noirq:
1082 while (--i >= 0)
1083 free_irq(port->cfg->irqs[i], port);
1084
1085out_nomem:
1086 while (--j >= 0)
1087 kfree(port->irqstr[j]);
1088
1089 return ret;
1da177e4
LT		 1090}
1091
1092static void sci_free_irq(struct sci_port *port)
1093{
1094 int i;
1095
9174fc8f
PM		 1096 /*
1097 * Intentionally in reverse order so we iterate over the muxed
1098 * IRQ first.
1099 */
1100 for (i = 0; i < SCIx_NR_IRQS; i++) {
0e8963de
PM		 1101 unsigned int irq = port->cfg->irqs[i];
1102
1103 /*
1104 * Certain port types won't support all of the available
1105 * interrupt sources.
1106 */
1107 if (unlikely(!irq))
1108 continue;
1109
9174fc8f
PM		 1110 free_irq(port->cfg->irqs[i], port);
1111 kfree(port->irqstr[i]);
1da177e4 1112
9174fc8f
PM		 1113 if (SCIx_IRQ_IS_MUXED(port)) {
1114 /* If there's only one IRQ, we're done. */
1115 return;
1da177e4
LT		 1116 }
1117 }
1118}
1119
50f0959a
PM		 1120static const char *sci_gpio_names[SCIx_NR_FNS] = {
1121 "sck", "rxd", "txd", "cts", "rts",
1122};
1123
1124static const char *sci_gpio_str(unsigned int index)
1125{
1126 return sci_gpio_names[index];
1127}
1128
1129static void __devinit sci_init_gpios(struct sci_port *port)
1130{
1131 struct uart_port *up = &port->port;
1132 int i;
1133
1134 if (!port->cfg)
1135 return;
1136
1137 for (i = 0; i < SCIx_NR_FNS; i++) {
1138 const char *desc;
1139 int ret;
1140
1141 if (!port->cfg->gpios[i])
1142 continue;
1143
1144 desc = sci_gpio_str(i);
1145
1146 port->gpiostr[i] = kasprintf(GFP_KERNEL, "%s:%s",
1147 dev_name(up->dev), desc);
1148
1149 /*
1150 * If we've failed the allocation, we can still continue
1151 * on with a NULL string.
1152 */
1153 if (!port->gpiostr[i])
1154 dev_notice(up->dev, "%s string allocation failure\n",
1155 desc);
1156
1157 ret = gpio_request(port->cfg->gpios[i], port->gpiostr[i]);
1158 if (unlikely(ret != 0)) {
1159 dev_notice(up->dev, "failed %s gpio request\n", desc);
1160
1161 /*
1162 * If we can't get the GPIO for whatever reason,
1163 * no point in keeping the verbose string around.
1164 */
1165 kfree(port->gpiostr[i]);
1166 }
1167 }
1168}
1169
1170static void sci_free_gpios(struct sci_port *port)
1171{
1172 int i;
1173
1174 for (i = 0; i < SCIx_NR_FNS; i++)
1175 if (port->cfg->gpios[i]) {
1176 gpio_free(port->cfg->gpios[i]);
1177 kfree(port->gpiostr[i]);
1178 }
1179}
1180
1da177e4
LT		 1181static unsigned int sci_tx_empty(struct uart_port *port)
1182{
b12bb29f 1183 unsigned short status = serial_port_in(port, SCxSR);
72b294cf 1184 unsigned short in_tx_fifo = sci_txfill(port);
73a19e4c
GL		 1185
1186 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
1da177e4
LT		 1187}
1188
cdf7c42f
PM		 1189/*
1190 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally
1191 * CTS/RTS is supported in hardware by at least one port and controlled
1192 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently
1193 * handled via the ->init_pins() op, which is a bit of a one-way street,
1194 * lacking any ability to defer pin control -- this will later be
1195 * converted over to the GPIO framework).
dc7e3ef7
PM		 1196 *
1197 * Other modes (such as loopback) are supported generically on certain
1198 * port types, but not others. For these it's sufficient to test for the
1199 * existence of the support register and simply ignore the port type.
cdf7c42f 1200 */
1da177e4
LT		 1201static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
1202{
dc7e3ef7
PM		 1203 if (mctrl & TIOCM_LOOP) {
1204 struct plat_sci_reg *reg;
1205
1206 /*
1207 * Standard loopback mode for SCFCR ports.
1208 */
1209 reg = sci_getreg(port, SCFCR);
1210 if (reg->size)
b12bb29f 1211 serial_port_out(port, SCFCR, serial_port_in(port, SCFCR) | 1);
dc7e3ef7 1212 }
1da177e4
LT		 1213}
1214
1215static unsigned int sci_get_mctrl(struct uart_port *port)
1216{
cdf7c42f
PM		 1217 /*
1218 * CTS/RTS is handled in hardware when supported, while nothing
1219 * else is wired up. Keep it simple and simply assert DSR/CAR.
1220 */
1221 return TIOCM_DSR | TIOCM_CAR;
1da177e4
LT		 1222}
1223
73a19e4c
GL		 1224#ifdef CONFIG_SERIAL_SH_SCI_DMA
1225static void sci_dma_tx_complete(void *arg)
1226{
1227 struct sci_port *s = arg;
1228 struct uart_port *port = &s->port;
1229 struct circ_buf *xmit = &port->state->xmit;
1230 unsigned long flags;
1231
1232 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1233
1234 spin_lock_irqsave(&port->lock, flags);
1235
f354a381 1236 xmit->tail += sg_dma_len(&s->sg_tx);
73a19e4c
GL		 1237 xmit->tail &= UART_XMIT_SIZE - 1;
1238
f354a381 1239 port->icount.tx += sg_dma_len(&s->sg_tx);
73a19e4c
GL		 1240
1241 async_tx_ack(s->desc_tx);
73a19e4c
GL		 1242 s->desc_tx = NULL;
1243
73a19e4c
GL		 1244 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1245 uart_write_wakeup(port);
1246
3089f381 1247 if (!uart_circ_empty(xmit)) {
49d4bcad 1248 s->cookie_tx = 0;
73a19e4c 1249 schedule_work(&s->work_tx);
49d4bcad
YT		 1250 } else {
1251 s->cookie_tx = -EINVAL;
1252 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
b12bb29f
PM		 1253 u16 ctrl = serial_port_in(port, SCSCR);
1254 serial_port_out(port, SCSCR, ctrl & ~SCSCR_TIE);
49d4bcad 1255 }
3089f381
GL		 1256 }
1257
1258 spin_unlock_irqrestore(&port->lock, flags);
73a19e4c
GL		 1259}
1260
1261/* Locking: called with port lock held */
1262static int sci_dma_rx_push(struct sci_port *s, struct tty_struct *tty,
1263 size_t count)
1264{
1265 struct uart_port *port = &s->port;
1266 int i, active, room;
1267
1268 room = tty_buffer_request_room(tty, count);
1269
1270 if (s->active_rx == s->cookie_rx[0]) {
1271 active = 0;
1272 } else if (s->active_rx == s->cookie_rx[1]) {
1273 active = 1;
1274 } else {
1275 dev_err(port->dev, "cookie %d not found!\n", s->active_rx);
1276 return 0;
1277 }
1278
1279 if (room < count)
1280 dev_warn(port->dev, "Rx overrun: dropping %u bytes\n",
1281 count - room);
1282 if (!room)
1283 return room;
1284
1285 for (i = 0; i < room; i++)
1286 tty_insert_flip_char(tty, ((u8 *)sg_virt(&s->sg_rx[active]))[i],
1287 TTY_NORMAL);
1288
1289 port->icount.rx += room;
1290
1291 return room;
1292}
1293
1294static void sci_dma_rx_complete(void *arg)
1295{
1296 struct sci_port *s = arg;
1297 struct uart_port *port = &s->port;
1298 struct tty_struct *tty = port->state->port.tty;
1299 unsigned long flags;
1300 int count;
1301
3089f381 1302 dev_dbg(port->dev, "%s(%d) active #%d\n", __func__, port->line, s->active_rx);
73a19e4c
GL		 1303
1304 spin_lock_irqsave(&port->lock, flags);
1305
1306 count = sci_dma_rx_push(s, tty, s->buf_len_rx);
1307
3089f381 1308 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
73a19e4c
GL		 1309
1310 spin_unlock_irqrestore(&port->lock, flags);
1311
1312 if (count)
1313 tty_flip_buffer_push(tty);
1314
1315 schedule_work(&s->work_rx);
1316}
1317
73a19e4c
GL		 1318static void sci_rx_dma_release(struct sci_port *s, bool enable_pio)
1319{
1320 struct dma_chan *chan = s->chan_rx;
1321 struct uart_port *port = &s->port;
73a19e4c
GL		 1322
1323 s->chan_rx = NULL;
1324 s->cookie_rx[0] = s->cookie_rx[1] = -EINVAL;
1325 dma_release_channel(chan);
85b8e3ff
GL		 1326 if (sg_dma_address(&s->sg_rx[0]))
1327 dma_free_coherent(port->dev, s->buf_len_rx * 2,
1328 sg_virt(&s->sg_rx[0]), sg_dma_address(&s->sg_rx[0]));
73a19e4c
GL		 1329 if (enable_pio)
1330 sci_start_rx(port);
1331}
1332
1333static void sci_tx_dma_release(struct sci_port *s, bool enable_pio)
1334{
1335 struct dma_chan *chan = s->chan_tx;
1336 struct uart_port *port = &s->port;
73a19e4c
GL		 1337
1338 s->chan_tx = NULL;
1339 s->cookie_tx = -EINVAL;
1340 dma_release_channel(chan);
1341 if (enable_pio)
1342 sci_start_tx(port);
1343}
1344
1345static void sci_submit_rx(struct sci_port *s)
1346{
1347 struct dma_chan *chan = s->chan_rx;
1348 int i;
1349
1350 for (i = 0; i < 2; i++) {
1351 struct scatterlist *sg = &s->sg_rx[i];
1352 struct dma_async_tx_descriptor *desc;
1353
16052827 1354 desc = dmaengine_prep_slave_sg(chan,
a485df4b 1355 sg, 1, DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
73a19e4c
GL		 1356
1357 if (desc) {
1358 s->desc_rx[i] = desc;
1359 desc->callback = sci_dma_rx_complete;
1360 desc->callback_param = s;
1361 s->cookie_rx[i] = desc->tx_submit(desc);
1362 }
1363
1364 if (!desc || s->cookie_rx[i] < 0) {
1365 if (i) {
1366 async_tx_ack(s->desc_rx[0]);
1367 s->cookie_rx[0] = -EINVAL;
1368 }
1369 if (desc) {
1370 async_tx_ack(desc);
1371 s->cookie_rx[i] = -EINVAL;
1372 }
1373 dev_warn(s->port.dev,
1374 "failed to re-start DMA, using PIO\n");
1375 sci_rx_dma_release(s, true);
1376 return;
1377 }
3089f381
GL		 1378 dev_dbg(s->port.dev, "%s(): cookie %d to #%d\n", __func__,
1379 s->cookie_rx[i], i);
73a19e4c
GL		 1380 }
1381
1382 s->active_rx = s->cookie_rx[0];
1383
1384 dma_async_issue_pending(chan);
1385}
1386
1387static void work_fn_rx(struct work_struct *work)
1388{
1389 struct sci_port *s = container_of(work, struct sci_port, work_rx);
1390 struct uart_port *port = &s->port;
1391 struct dma_async_tx_descriptor *desc;
1392 int new;
1393
1394 if (s->active_rx == s->cookie_rx[0]) {
1395 new = 0;
1396 } else if (s->active_rx == s->cookie_rx[1]) {
1397 new = 1;
1398 } else {
1399 dev_err(port->dev, "cookie %d not found!\n", s->active_rx);
1400 return;
1401 }
1402 desc = s->desc_rx[new];
1403
1404 if (dma_async_is_tx_complete(s->chan_rx, s->active_rx, NULL, NULL) !=
1405 DMA_SUCCESS) {
1406 /* Handle incomplete DMA receive */
1407 struct tty_struct *tty = port->state->port.tty;
1408 struct dma_chan *chan = s->chan_rx;
4dc4c516
GL		 1409 struct shdma_desc *sh_desc = container_of(desc,
1410 struct shdma_desc, async_tx);
73a19e4c
GL		 1411 unsigned long flags;
1412 int count;
1413
05827630 1414 chan->device->device_control(chan, DMA_TERMINATE_ALL, 0);
73a19e4c
GL		 1415 dev_dbg(port->dev, "Read %u bytes with cookie %d\n",
1416 sh_desc->partial, sh_desc->cookie);
1417
1418 spin_lock_irqsave(&port->lock, flags);
1419 count = sci_dma_rx_push(s, tty, sh_desc->partial);
1420 spin_unlock_irqrestore(&port->lock, flags);
1421
1422 if (count)
1423 tty_flip_buffer_push(tty);
1424
1425 sci_submit_rx(s);
1426
1427 return;
1428 }
1429
1430 s->cookie_rx[new] = desc->tx_submit(desc);
1431 if (s->cookie_rx[new] < 0) {
1432 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
1433 sci_rx_dma_release(s, true);
1434 return;
1435 }
1436
73a19e4c 1437 s->active_rx = s->cookie_rx[!new];
3089f381
GL		 1438
1439 dev_dbg(port->dev, "%s: cookie %d #%d, new active #%d\n", __func__,
1440 s->cookie_rx[new], new, s->active_rx);
73a19e4c
GL		 1441}
1442
1443static void work_fn_tx(struct work_struct *work)
1444{
1445 struct sci_port *s = container_of(work, struct sci_port, work_tx);
1446 struct dma_async_tx_descriptor *desc;
1447 struct dma_chan *chan = s->chan_tx;
1448 struct uart_port *port = &s->port;
1449 struct circ_buf *xmit = &port->state->xmit;
1450 struct scatterlist *sg = &s->sg_tx;
1451
1452 /*
1453 * DMA is idle now.
1454 * Port xmit buffer is already mapped, and it is one page... Just adjust
1455 * offsets and lengths. Since it is a circular buffer, we have to
1456 * transmit till the end, and then the rest. Take the port lock to get a
1457 * consistent xmit buffer state.
1458 */
1459 spin_lock_irq(&port->lock);
1460 sg->offset = xmit->tail & (UART_XMIT_SIZE - 1);
f354a381 1461 sg_dma_address(sg) = (sg_dma_address(sg) & ~(UART_XMIT_SIZE - 1)) +
73a19e4c 1462 sg->offset;
f354a381 1463 sg_dma_len(sg) = min((int)CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE),
73a19e4c 1464 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE));
73a19e4c
GL		 1465 spin_unlock_irq(&port->lock);
1466
f354a381 1467 BUG_ON(!sg_dma_len(sg));
73a19e4c 1468
16052827 1469 desc = dmaengine_prep_slave_sg(chan,
a485df4b 1470 sg, s->sg_len_tx, DMA_MEM_TO_DEV,
73a19e4c
GL		 1471 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1472 if (!desc) {
1473 /* switch to PIO */
1474 sci_tx_dma_release(s, true);
1475 return;
1476 }
1477
1478 dma_sync_sg_for_device(port->dev, sg, 1, DMA_TO_DEVICE);
1479
1480 spin_lock_irq(&port->lock);
1481 s->desc_tx = desc;
1482 desc->callback = sci_dma_tx_complete;
1483 desc->callback_param = s;
1484 spin_unlock_irq(&port->lock);
1485 s->cookie_tx = desc->tx_submit(desc);
1486 if (s->cookie_tx < 0) {
1487 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
1488 /* switch to PIO */
1489 sci_tx_dma_release(s, true);
1490 return;
1491 }
1492
1493 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n", __func__,
1494 xmit->buf, xmit->tail, xmit->head, s->cookie_tx);
1495
1496 dma_async_issue_pending(chan);
1497}
1498#endif
1499
b129a8cc 1500static void sci_start_tx(struct uart_port *port)
1da177e4 1501{
3089f381 1502 struct sci_port *s = to_sci_port(port);
e108b2ca 1503 unsigned short ctrl;
1da177e4 1504
73a19e4c 1505#ifdef CONFIG_SERIAL_SH_SCI_DMA
d1d4b10c 1506 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
b12bb29f 1507 u16 new, scr = serial_port_in(port, SCSCR);
3089f381
GL		 1508 if (s->chan_tx)
1509 new = scr | 0x8000;
1510 else
1511 new = scr & ~0x8000;
1512 if (new != scr)
b12bb29f 1513 serial_port_out(port, SCSCR, new);
73a19e4c 1514 }
f43dc23d 1515
3089f381 1516 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) &&
49d4bcad
YT		 1517 s->cookie_tx < 0) {
1518 s->cookie_tx = 0;
3089f381 1519 schedule_work(&s->work_tx);
49d4bcad 1520 }
73a19e4c 1521#endif
f43dc23d 1522
d1d4b10c 1523 if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
3089f381 1524 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
b12bb29f
PM		 1525 ctrl = serial_port_in(port, SCSCR);
1526 serial_port_out(port, SCSCR, ctrl | SCSCR_TIE);
3089f381 1527 }
1da177e4
LT		 1528}
1529
b129a8cc 1530static void sci_stop_tx(struct uart_port *port)
1da177e4 1531{
1da177e4
LT		 1532 unsigned short ctrl;
1533
1534 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
b12bb29f 1535 ctrl = serial_port_in(port, SCSCR);
f43dc23d 1536
d1d4b10c 1537 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
3089f381 1538 ctrl &= ~0x8000;
f43dc23d 1539
8e698614 1540 ctrl &= ~SCSCR_TIE;
f43dc23d 1541
b12bb29f 1542 serial_port_out(port, SCSCR, ctrl);
1da177e4
LT		 1543}
1544
73a19e4c 1545static void sci_start_rx(struct uart_port *port)
1da177e4 1546{
1da177e4
LT		 1547 unsigned short ctrl;
1548
b12bb29f 1549 ctrl = serial_port_in(port, SCSCR) | port_rx_irq_mask(port);
1da177e4 1550
d1d4b10c 1551 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
3089f381 1552 ctrl &= ~0x4000;
f43dc23d 1553
b12bb29f 1554 serial_port_out(port, SCSCR, ctrl);
1da177e4
LT		 1555}
1556
1557static void sci_stop_rx(struct uart_port *port)
1558{
1da177e4
LT		 1559 unsigned short ctrl;
1560
b12bb29f 1561 ctrl = serial_port_in(port, SCSCR);
f43dc23d 1562
d1d4b10c 1563 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
3089f381 1564 ctrl &= ~0x4000;
f43dc23d
PM		 1565
1566 ctrl &= ~port_rx_irq_mask(port);
1567
b12bb29f 1568 serial_port_out(port, SCSCR, ctrl);
1da177e4
LT		 1569}
1570
1571static void sci_enable_ms(struct uart_port *port)
1572{
d39ec6ce
PM		 1573 /*
1574 * Not supported by hardware, always a nop.
1575 */
1da177e4
LT		 1576}
1577
1578static void sci_break_ctl(struct uart_port *port, int break_state)
1579{
bbb4ce50 1580 struct sci_port *s = to_sci_port(port);
a4e02f6d 1581 struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR;
bbb4ce50
SY		 1582 unsigned short scscr, scsptr;
1583
a4e02f6d
SY		 1584 /* check wheter the port has SCSPTR */
1585 if (!reg->size) {
bbb4ce50
SY		 1586 /*
1587 * Not supported by hardware. Most parts couple break and rx
1588 * interrupts together, with break detection always enabled.
1589 */
a4e02f6d 1590 return;
bbb4ce50 1591 }
a4e02f6d
SY		 1592
1593 scsptr = serial_port_in(port, SCSPTR);
1594 scscr = serial_port_in(port, SCSCR);
1595
1596 if (break_state == -1) {
1597 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT;
1598 scscr &= ~SCSCR_TE;
1599 } else {
1600 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO;
1601 scscr |= SCSCR_TE;
1602 }
1603
1604 serial_port_out(port, SCSPTR, scsptr);
1605 serial_port_out(port, SCSCR, scscr);
1da177e4
LT		 1606}
1607
73a19e4c
GL		 1608#ifdef CONFIG_SERIAL_SH_SCI_DMA
1609static bool filter(struct dma_chan *chan, void *slave)
1610{
1611 struct sh_dmae_slave *param = slave;
1612
1613 dev_dbg(chan->device->dev, "%s: slave ID %d\n", __func__,
d6fa5a4e 1614 param->shdma_slave.slave_id);
73a19e4c 1615
d6fa5a4e 1616 chan->private = &param->shdma_slave;
937bb6e4 1617 return true;
73a19e4c
GL		 1618}
1619
1620static void rx_timer_fn(unsigned long arg)
1621{
1622 struct sci_port *s = (struct sci_port *)arg;
1623 struct uart_port *port = &s->port;
b12bb29f 1624 u16 scr = serial_port_in(port, SCSCR);
3089f381 1625
d1d4b10c 1626 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
3089f381 1627 scr &= ~0x4000;
ce6738b6 1628 enable_irq(s->cfg->irqs[1]);
3089f381 1629 }
b12bb29f 1630 serial_port_out(port, SCSCR, scr | SCSCR_RIE);
73a19e4c
GL		 1631 dev_dbg(port->dev, "DMA Rx timed out\n");
1632 schedule_work(&s->work_rx);
1633}
1634
1635static void sci_request_dma(struct uart_port *port)
1636{
1637 struct sci_port *s = to_sci_port(port);
1638 struct sh_dmae_slave *param;
1639 struct dma_chan *chan;
1640 dma_cap_mask_t mask;
1641 int nent;
1642
937bb6e4
GL		 1643 dev_dbg(port->dev, "%s: port %d\n", __func__,
1644 port->line);
73a19e4c 1645
937bb6e4 1646 if (s->cfg->dma_slave_tx <= 0 || s->cfg->dma_slave_rx <= 0)
73a19e4c
GL		 1647 return;
1648
1649 dma_cap_zero(mask);
1650 dma_cap_set(DMA_SLAVE, mask);
1651
1652 param = &s->param_tx;
1653
1654 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_TX */
d6fa5a4e 1655 param->shdma_slave.slave_id = s->cfg->dma_slave_tx;
73a19e4c
GL		 1656
1657 s->cookie_tx = -EINVAL;
1658 chan = dma_request_channel(mask, filter, param);
1659 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
1660 if (chan) {
1661 s->chan_tx = chan;
1662 sg_init_table(&s->sg_tx, 1);
1663 /* UART circular tx buffer is an aligned page. */
1664 BUG_ON((int)port->state->xmit.buf & ~PAGE_MASK);
1665 sg_set_page(&s->sg_tx, virt_to_page(port->state->xmit.buf),
1666 UART_XMIT_SIZE, (int)port->state->xmit.buf & ~PAGE_MASK);
1667 nent = dma_map_sg(port->dev, &s->sg_tx, 1, DMA_TO_DEVICE);
1668 if (!nent)
1669 sci_tx_dma_release(s, false);
1670 else
1671 dev_dbg(port->dev, "%s: mapped %d@%p to %x\n", __func__,
1672 sg_dma_len(&s->sg_tx),
1673 port->state->xmit.buf, sg_dma_address(&s->sg_tx));
1674
1675 s->sg_len_tx = nent;
1676
1677 INIT_WORK(&s->work_tx, work_fn_tx);
1678 }
1679
1680 param = &s->param_rx;
1681
1682 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_RX */
d6fa5a4e 1683 param->shdma_slave.slave_id = s->cfg->dma_slave_rx;
73a19e4c
GL		 1684
1685 chan = dma_request_channel(mask, filter, param);
1686 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan);
1687 if (chan) {
1688 dma_addr_t dma[2];
1689 void *buf[2];
1690 int i;
1691
1692 s->chan_rx = chan;
1693
1694 s->buf_len_rx = 2 * max(16, (int)port->fifosize);
1695 buf[0] = dma_alloc_coherent(port->dev, s->buf_len_rx * 2,
1696 &dma[0], GFP_KERNEL);
1697
1698 if (!buf[0]) {
1699 dev_warn(port->dev,
1700 "failed to allocate dma buffer, using PIO\n");
1701 sci_rx_dma_release(s, true);
1702 return;
1703 }
1704
1705 buf[1] = buf[0] + s->buf_len_rx;
1706 dma[1] = dma[0] + s->buf_len_rx;
1707
1708 for (i = 0; i < 2; i++) {
1709 struct scatterlist *sg = &s->sg_rx[i];
1710
1711 sg_init_table(sg, 1);
1712 sg_set_page(sg, virt_to_page(buf[i]), s->buf_len_rx,
1713 (int)buf[i] & ~PAGE_MASK);
f354a381 1714 sg_dma_address(sg) = dma[i];
73a19e4c
GL		 1715 }
1716
1717 INIT_WORK(&s->work_rx, work_fn_rx);
1718 setup_timer(&s->rx_timer, rx_timer_fn, (unsigned long)s);
1719
1720 sci_submit_rx(s);
1721 }
1722}
1723
1724static void sci_free_dma(struct uart_port *port)
1725{
1726 struct sci_port *s = to_sci_port(port);
1727
73a19e4c
GL		 1728 if (s->chan_tx)
1729 sci_tx_dma_release(s, false);
1730 if (s->chan_rx)
1731 sci_rx_dma_release(s, false);
1732}
27bd1075
PM		 1733#else
1734static inline void sci_request_dma(struct uart_port *port)
1735{
1736}
1737
1738static inline void sci_free_dma(struct uart_port *port)
1739{
1740}
73a19e4c
GL		 1741#endif
1742
1da177e4
LT		 1743static int sci_startup(struct uart_port *port)
1744{
a5660ada 1745 struct sci_port *s = to_sci_port(port);
073e84c9 1746 int ret;
1da177e4 1747
73a19e4c
GL		 1748 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1749
073e84c9
PM		 1750 ret = sci_request_irq(s);
1751 if (unlikely(ret < 0))
1752 return ret;
1753
73a19e4c 1754 sci_request_dma(port);
073e84c9 1755
d656901b 1756 sci_start_tx(port);
73a19e4c 1757 sci_start_rx(port);
1da177e4
LT		 1758
1759 return 0;
1760}
1761
1762static void sci_shutdown(struct uart_port *port)
1763{
a5660ada 1764 struct sci_port *s = to_sci_port(port);
1da177e4 1765
73a19e4c
GL		 1766 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1767
1da177e4 1768 sci_stop_rx(port);
b129a8cc 1769 sci_stop_tx(port);
073e84c9 1770
73a19e4c 1771 sci_free_dma(port);
1da177e4 1772 sci_free_irq(s);
1da177e4
LT		 1773}
1774
26c92f37
PM		 1775static unsigned int sci_scbrr_calc(unsigned int algo_id, unsigned int bps,
1776 unsigned long freq)
1777{
1778 switch (algo_id) {
1779 case SCBRR_ALGO_1:
1780 return ((freq + 16 * bps) / (16 * bps) - 1);
1781 case SCBRR_ALGO_2:
1782 return ((freq + 16 * bps) / (32 * bps) - 1);
1783 case SCBRR_ALGO_3:
1784 return (((freq * 2) + 16 * bps) / (16 * bps) - 1);
1785 case SCBRR_ALGO_4:
1786 return (((freq * 2) + 16 * bps) / (32 * bps) - 1);
1787 case SCBRR_ALGO_5:
1788 return (((freq * 1000 / 32) / bps) - 1);
1789 }
1790
1791 /* Warn, but use a safe default */
1792 WARN_ON(1);
e8183a6c 1793
26c92f37
PM		 1794 return ((freq + 16 * bps) / (32 * bps) - 1);
1795}
1796
1ba76220
MD		 1797static void sci_reset(struct uart_port *port)
1798{
0979e0e6 1799 struct plat_sci_reg *reg;
1ba76220
MD		 1800 unsigned int status;
1801
1802 do {
b12bb29f 1803 status = serial_port_in(port, SCxSR);
1ba76220
MD		 1804 } while (!(status & SCxSR_TEND(port)));
1805
b12bb29f 1806 serial_port_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */
1ba76220 1807
0979e0e6
PM		 1808 reg = sci_getreg(port, SCFCR);
1809 if (reg->size)
b12bb29f 1810 serial_port_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
1ba76220
MD		 1811}
1812
606d099c
AC		 1813static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
1814 struct ktermios *old)
1da177e4 1815{
00b9de9c 1816 struct sci_port *s = to_sci_port(port);
0979e0e6 1817 struct plat_sci_reg *reg;
9d482cc3 1818 unsigned int baud, smr_val, max_baud, cks;
a2159b52 1819 int t = -1;
1da177e4 1820
154280fd
MD		 1821 /*
1822 * earlyprintk comes here early on with port->uartclk set to zero.
1823 * the clock framework is not up and running at this point so here
1824 * we assume that 115200 is the maximum baud rate. please note that
1825 * the baud rate is not programmed during earlyprintk - it is assumed
1826 * that the previous boot loader has enabled required clocks and
1827 * setup the baud rate generator hardware for us already.
1828 */
1829 max_baud = port->uartclk ? port->uartclk / 16 : 115200;
1da177e4 1830
154280fd
MD		 1831 baud = uart_get_baud_rate(port, termios, old, 0, max_baud);
1832 if (likely(baud && port->uartclk))
ce6738b6 1833 t = sci_scbrr_calc(s->cfg->scbrr_algo_id, baud, port->uartclk);
e108b2ca 1834
23241d43 1835 sci_port_enable(s);
36003386 1836
1ba76220 1837 sci_reset(port);
1da177e4 1838
b12bb29f 1839 smr_val = serial_port_in(port, SCSMR) & 3;
e8183a6c 1840
1da177e4
LT		 1841 if ((termios->c_cflag & CSIZE) == CS7)
1842 smr_val |= 0x40;
1843 if (termios->c_cflag & PARENB)
1844 smr_val |= 0x20;
1845 if (termios->c_cflag & PARODD)
1846 smr_val |= 0x30;
1847 if (termios->c_cflag & CSTOPB)
1848 smr_val |= 0x08;
1849
1850 uart_update_timeout(port, termios->c_cflag, baud);
1851
9d482cc3
TY		 1852 for (cks = 0; t >= 256 && cks <= 3; cks++)
1853 t >>= 2;
1da177e4 1854
9d482cc3
TY		 1855 dev_dbg(port->dev, "%s: SMR %x, cks %x, t %x, SCSCR %x\n",
1856 __func__, smr_val, cks, t, s->cfg->scscr);
73a19e4c 1857
4ffc3cdb 1858 if (t >= 0) {
9d482cc3 1859 serial_port_out(port, SCSMR, (smr_val & ~3) | cks);
b12bb29f 1860 serial_port_out(port, SCBRR, t);
1da177e4 1861 udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */
9d482cc3
TY		 1862 } else
1863 serial_port_out(port, SCSMR, smr_val);
1da177e4 1864
d5701647 1865 sci_init_pins(port, termios->c_cflag);
0979e0e6 1866
73c3d53f
PM		 1867 reg = sci_getreg(port, SCFCR);
1868 if (reg->size) {
b12bb29f 1869 unsigned short ctrl = serial_port_in(port, SCFCR);
0979e0e6 1870
73c3d53f 1871 if (s->cfg->capabilities & SCIx_HAVE_RTSCTS) {
faf02f8f
PM		 1872 if (termios->c_cflag & CRTSCTS)
1873 ctrl |= SCFCR_MCE;
1874 else
1875 ctrl &= ~SCFCR_MCE;
faf02f8f 1876 }
73c3d53f
PM		 1877
1878 /*
1879 * As we've done a sci_reset() above, ensure we don't
1880 * interfere with the FIFOs while toggling MCE. As the
1881 * reset values could still be set, simply mask them out.
1882 */
1883 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST);
1884
b12bb29f 1885 serial_port_out(port, SCFCR, ctrl);
0979e0e6 1886 }
b7a76e4b 1887
b12bb29f 1888 serial_port_out(port, SCSCR, s->cfg->scscr);
1da177e4 1889
3089f381
GL		 1890#ifdef CONFIG_SERIAL_SH_SCI_DMA
1891 /*
1892 * Calculate delay for 1.5 DMA buffers: see
1893 * drivers/serial/serial_core.c::uart_update_timeout(). With 10 bits
1894 * (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above function
1895 * calculates 1 jiffie for the data plus 5 jiffies for the "slop(e)."
1896 * Then below we calculate 3 jiffies (12ms) for 1.5 DMA buffers (3 FIFO
1897 * sizes), but it has been found out experimentally, that this is not
1898 * enough: the driver too often needlessly runs on a DMA timeout. 20ms
1899 * as a minimum seem to work perfectly.
1900 */
1901 if (s->chan_rx) {
1902 s->rx_timeout = (port->timeout - HZ / 50) * s->buf_len_rx * 3 /
1903 port->fifosize / 2;
1904 dev_dbg(port->dev,
1905 "DMA Rx t-out %ums, tty t-out %u jiffies\n",
1906 s->rx_timeout * 1000 / HZ, port->timeout);
1907 if (s->rx_timeout < msecs_to_jiffies(20))
1908 s->rx_timeout = msecs_to_jiffies(20);
1909 }
1910#endif
1911
1da177e4 1912 if ((termios->c_cflag & CREAD) != 0)
73a19e4c 1913 sci_start_rx(port);
36003386 1914
23241d43 1915 sci_port_disable(s);
1da177e4
LT		 1916}
1917
0174e5ca
TK		 1918static void sci_pm(struct uart_port *port, unsigned int state,
1919 unsigned int oldstate)
1920{
1921 struct sci_port *sci_port = to_sci_port(port);
1922
1923 switch (state) {
1924 case 3:
1925 sci_port_disable(sci_port);
1926 break;
1927 default:
1928 sci_port_enable(sci_port);
1929 break;
1930 }
1931}
1932
1da177e4
LT		 1933static const char *sci_type(struct uart_port *port)
1934{
1935 switch (port->type) {
e7c98dc7
MT		 1936 case PORT_IRDA:
1937 return "irda";
1938 case PORT_SCI:
1939 return "sci";
1940 case PORT_SCIF:
1941 return "scif";
1942 case PORT_SCIFA:
1943 return "scifa";
d1d4b10c
GL		 1944 case PORT_SCIFB:
1945 return "scifb";
1da177e4
LT		 1946 }
1947
fa43972f 1948 return NULL;
1da177e4
LT		 1949}
1950
e2651647 1951static inline unsigned long sci_port_size(struct uart_port *port)
1da177e4 1952{
e2651647
PM		 1953 /*
1954 * Pick an arbitrary size that encapsulates all of the base
1955 * registers by default. This can be optimized later, or derived
1956 * from platform resource data at such a time that ports begin to
1957 * behave more erratically.
1958 */
1959 return 64;
1da177e4
LT		 1960}
1961
f6e9495d
PM		 1962static int sci_remap_port(struct uart_port *port)
1963{
1964 unsigned long size = sci_port_size(port);
1965
1966 /*
1967 * Nothing to do if there's already an established membase.
1968 */
1969 if (port->membase)
1970 return 0;
1971
1972 if (port->flags & UPF_IOREMAP) {
1973 port->membase = ioremap_nocache(port->mapbase, size);
1974 if (unlikely(!port->membase)) {
1975 dev_err(port->dev, "can't remap port#%d\n", port->line);
1976 return -ENXIO;
1977 }
1978 } else {
1979 /*
1980 * For the simple (and majority of) cases where we don't
1981 * need to do any remapping, just cast the cookie
1982 * directly.
1983 */
1984 port->membase = (void __iomem *)port->mapbase;
1985 }
1986
1987 return 0;
1988}
1989
e2651647 1990static void sci_release_port(struct uart_port *port)
1da177e4 1991{
e2651647
PM		 1992 if (port->flags & UPF_IOREMAP) {
1993 iounmap(port->membase);
1994 port->membase = NULL;
1995 }
1996
1997 release_mem_region(port->mapbase, sci_port_size(port));
1da177e4
LT		 1998}
1999
e2651647 2000static int sci_request_port(struct uart_port *port)
1da177e4 2001{
e2651647
PM		 2002 unsigned long size = sci_port_size(port);
2003 struct resource *res;
f6e9495d 2004 int ret;
1da177e4 2005
1020520e 2006 res = request_mem_region(port->mapbase, size, dev_name(port->dev));
e2651647
PM		 2007 if (unlikely(res == NULL))
2008 return -EBUSY;
1da177e4 2009
f6e9495d
PM		 2010 ret = sci_remap_port(port);
2011 if (unlikely(ret != 0)) {
2012 release_resource(res);
2013 return ret;
7ff731ae 2014 }
e2651647
PM		 2015
2016 return 0;
2017}
2018
2019static void sci_config_port(struct uart_port *port, int flags)
2020{
2021 if (flags & UART_CONFIG_TYPE) {
2022 struct sci_port *sport = to_sci_port(port);
2023
2024 port->type = sport->cfg->type;
2025 sci_request_port(port);
2026 }
1da177e4
LT		 2027}
2028
2029static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
2030{
a5660ada 2031 struct sci_port *s = to_sci_port(port);
1da177e4 2032
ce6738b6 2033 if (ser->irq != s->cfg->irqs[SCIx_TXI_IRQ] || ser->irq > nr_irqs)
1da177e4
LT		 2034 return -EINVAL;
2035 if (ser->baud_base < 2400)
2036 /* No paper tape reader for Mitch.. */
2037 return -EINVAL;
2038
2039 return 0;
2040}
2041
2042static struct uart_ops sci_uart_ops = {
2043 .tx_empty = sci_tx_empty,
2044 .set_mctrl = sci_set_mctrl,
2045 .get_mctrl = sci_get_mctrl,
2046 .start_tx = sci_start_tx,
2047 .stop_tx = sci_stop_tx,
2048 .stop_rx = sci_stop_rx,
2049 .enable_ms = sci_enable_ms,
2050 .break_ctl = sci_break_ctl,
2051 .startup = sci_startup,
2052 .shutdown = sci_shutdown,
2053 .set_termios = sci_set_termios,
0174e5ca 2054 .pm = sci_pm,
1da177e4
LT		 2055 .type = sci_type,
2056 .release_port = sci_release_port,
2057 .request_port = sci_request_port,
2058 .config_port = sci_config_port,
2059 .verify_port = sci_verify_port,
07d2a1a1
PM		 2060#ifdef CONFIG_CONSOLE_POLL
2061 .poll_get_char = sci_poll_get_char,
2062 .poll_put_char = sci_poll_put_char,
2063#endif
1da177e4
LT		 2064};
2065
c7ed1ab3
PM		 2066static int __devinit sci_init_single(struct platform_device *dev,
2067 struct sci_port *sci_port,
2068 unsigned int index,
2069 struct plat_sci_port *p)
e108b2ca 2070{
73a19e4c 2071 struct uart_port *port = &sci_port->port;
3127c6b2 2072 int ret;
e108b2ca 2073
50f0959a
PM		 2074 sci_port->cfg = p;
2075
73a19e4c
GL		 2076 port->ops = &sci_uart_ops;
2077 port->iotype = UPIO_MEM;
2078 port->line = index;
75136d48
MP		 2079
2080 switch (p->type) {
d1d4b10c
GL		 2081 case PORT_SCIFB:
2082 port->fifosize = 256;
2083 break;
75136d48 2084 case PORT_SCIFA:
73a19e4c 2085 port->fifosize = 64;
75136d48
MP		 2086 break;
2087 case PORT_SCIF:
73a19e4c 2088 port->fifosize = 16;
75136d48
MP		 2089 break;
2090 default:
73a19e4c 2091 port->fifosize = 1;
75136d48
MP		 2092 break;
2093 }
7b6fd3bf 2094
3127c6b2
PM		 2095 if (p->regtype == SCIx_PROBE_REGTYPE) {
2096 ret = sci_probe_regmap(p);
fc97114b 2097 if (unlikely(ret))
3127c6b2
PM		 2098 return ret;
2099 }
61a6976b 2100
7b6fd3bf 2101 if (dev) {
c7ed1ab3
PM		 2102 sci_port->iclk = clk_get(&dev->dev, "sci_ick");
2103 if (IS_ERR(sci_port->iclk)) {
2104 sci_port->iclk = clk_get(&dev->dev, "peripheral_clk");
2105 if (IS_ERR(sci_port->iclk)) {
2106 dev_err(&dev->dev, "can't get iclk\n");
2107 return PTR_ERR(sci_port->iclk);
2108 }
2109 }
2110
2111 /*
2112 * The function clock is optional, ignore it if we can't
2113 * find it.
2114 */
2115 sci_port->fclk = clk_get(&dev->dev, "sci_fck");
2116 if (IS_ERR(sci_port->fclk))
2117 sci_port->fclk = NULL;
2118
73a19e4c 2119 port->dev = &dev->dev;
5e50d2d6 2120
50f0959a
PM		 2121 sci_init_gpios(sci_port);
2122
5e50d2d6 2123 pm_runtime_enable(&dev->dev);
7b6fd3bf 2124 }
e108b2ca 2125
7ed7e071
MD		 2126 sci_port->break_timer.data = (unsigned long)sci_port;
2127 sci_port->break_timer.function = sci_break_timer;
2128 init_timer(&sci_port->break_timer);
2129
debf9507
PM		 2130 /*
2131 * Establish some sensible defaults for the error detection.
2132 */
2133 if (!p->error_mask)
2134 p->error_mask = (p->type == PORT_SCI) ?
2135 SCI_DEFAULT_ERROR_MASK : SCIF_DEFAULT_ERROR_MASK;
2136
2137 /*
2138 * Establish sensible defaults for the overrun detection, unless
2139 * the part has explicitly disabled support for it.
2140 */
2141 if (p->overrun_bit != SCIx_NOT_SUPPORTED) {
2142 if (p->type == PORT_SCI)
2143 p->overrun_bit = 5;
2144 else if (p->scbrr_algo_id == SCBRR_ALGO_4)
2145 p->overrun_bit = 9;
2146 else
2147 p->overrun_bit = 0;
2148
2149 /*
2150 * Make the error mask inclusive of overrun detection, if
2151 * supported.
2152 */
2153 p->error_mask |= (1 << p->overrun_bit);
2154 }
2155
ce6738b6
PM		 2156 port->mapbase = p->mapbase;
2157 port->type = p->type;
f43dc23d 2158 port->flags = p->flags;
61a6976b 2159 port->regshift = p->regshift;
73a19e4c 2160
ce6738b6 2161 /*
61a6976b 2162 * The UART port needs an IRQ value, so we peg this to the RX IRQ
ce6738b6
PM		 2163 * for the multi-IRQ ports, which is where we are primarily
2164 * concerned with the shutdown path synchronization.
2165 *
2166 * For the muxed case there's nothing more to do.
2167 */
54aa89ea 2168 port->irq = p->irqs[SCIx_RXI_IRQ];
9cfb5c05 2169 port->irqflags = 0;
73a19e4c 2170
61a6976b
PM		 2171 port->serial_in = sci_serial_in;
2172 port->serial_out = sci_serial_out;
2173
937bb6e4
GL		 2174 if (p->dma_slave_tx > 0 && p->dma_slave_rx > 0)
2175 dev_dbg(port->dev, "DMA tx %d, rx %d\n",
2176 p->dma_slave_tx, p->dma_slave_rx);
7ed7e071 2177
c7ed1ab3 2178 return 0;
e108b2ca
PM		 2179}
2180
6dae1421
LP		 2181static void sci_cleanup_single(struct sci_port *port)
2182{
2183 sci_free_gpios(port);
2184
2185 clk_put(port->iclk);
2186 clk_put(port->fclk);
2187
2188 pm_runtime_disable(port->port.dev);
2189}
2190
1da177e4 2191#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
dc8e6f5b
MD		 2192static void serial_console_putchar(struct uart_port *port, int ch)
2193{
2194 sci_poll_put_char(port, ch);
2195}
2196
1da177e4
LT		 2197/*
2198 * Print a string to the serial port trying not to disturb
2199 * any possible real use of the port...
2200 */
2201static void serial_console_write(struct console *co, const char *s,
2202 unsigned count)
2203{
906b17dc
PM		 2204 struct sci_port *sci_port = &sci_ports[co->index];
2205 struct uart_port *port = &sci_port->port;
973e5d52 2206 unsigned short bits;
07d2a1a1 2207
501b825d 2208 uart_console_write(port, s, count, serial_console_putchar);
973e5d52
MD		 2209
2210 /* wait until fifo is empty and last bit has been transmitted */
2211 bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
b12bb29f 2212 while ((serial_port_in(port, SCxSR) & bits) != bits)
973e5d52 2213 cpu_relax();
1da177e4
LT		 2214}
2215
7b6fd3bf 2216static int __devinit serial_console_setup(struct console *co, char *options)
1da177e4 2217{
dc8e6f5b 2218 struct sci_port *sci_port;
1da177e4
LT		 2219 struct uart_port *port;
2220 int baud = 115200;
2221 int bits = 8;
2222 int parity = 'n';
2223 int flow = 'n';
2224 int ret;
2225
e108b2ca 2226 /*
906b17dc 2227 * Refuse to handle any bogus ports.
1da177e4 2228 */
906b17dc 2229 if (co->index < 0 || co->index >= SCI_NPORTS)
e108b2ca 2230 return -ENODEV;
e108b2ca 2231
906b17dc
PM		 2232 sci_port = &sci_ports[co->index];
2233 port = &sci_port->port;
2234
b2267a6b
AC		 2235 /*
2236 * Refuse to handle uninitialized ports.
2237 */
2238 if (!port->ops)
2239 return -ENODEV;
2240
f6e9495d
PM		 2241 ret = sci_remap_port(port);
2242 if (unlikely(ret != 0))
2243 return ret;
e108b2ca 2244
1da177e4
LT		 2245 if (options)
2246 uart_parse_options(options, &baud, &parity, &bits, &flow);
2247
ab7cfb55 2248 return uart_set_options(port, co, baud, parity, bits, flow);
1da177e4
LT		 2249}
2250
2251static struct console serial_console = {
2252 .name = "ttySC",
906b17dc 2253 .device = uart_console_device,
1da177e4
LT		 2254 .write = serial_console_write,
2255 .setup = serial_console_setup,
fa5da2f7 2256 .flags = CON_PRINTBUFFER,
1da177e4 2257 .index = -1,
906b17dc 2258 .data = &sci_uart_driver,
1da177e4
LT		 2259};
2260
7b6fd3bf
MD		 2261static struct console early_serial_console = {
2262 .name = "early_ttySC",
2263 .write = serial_console_write,
2264 .flags = CON_PRINTBUFFER,
906b17dc 2265 .index = -1,
7b6fd3bf 2266};
ecdf8a46 2267
7b6fd3bf
MD		 2268static char early_serial_buf[32];
2269
ecdf8a46
PM		 2270static int __devinit sci_probe_earlyprintk(struct platform_device *pdev)
2271{
2272 struct plat_sci_port *cfg = pdev->dev.platform_data;
2273
2274 if (early_serial_console.data)
2275 return -EEXIST;
2276
2277 early_serial_console.index = pdev->id;
ecdf8a46 2278
906b17dc 2279 sci_init_single(NULL, &sci_ports[pdev->id], pdev->id, cfg);
ecdf8a46
PM		 2280
2281 serial_console_setup(&early_serial_console, early_serial_buf);
2282
2283 if (!strstr(early_serial_buf, "keep"))
2284 early_serial_console.flags |= CON_BOOT;
2285
2286 register_console(&early_serial_console);
2287 return 0;
2288}
6a8c9799
NI		 2289
2290#define SCI_CONSOLE (&serial_console)
2291
ecdf8a46
PM		 2292#else
2293static inline int __devinit sci_probe_earlyprintk(struct platform_device *pdev)
2294{
2295 return -EINVAL;
2296}
1da177e4 2297
6a8c9799
NI		 2298#define SCI_CONSOLE NULL
2299
2300#endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
1da177e4
LT		 2301
2302static char banner[] __initdata =
2303 KERN_INFO "SuperH SCI(F) driver initialized\n";
2304
2305static struct uart_driver sci_uart_driver = {
2306 .owner = THIS_MODULE,
2307 .driver_name = "sci",
1da177e4
LT		 2308 .dev_name = "ttySC",
2309 .major = SCI_MAJOR,
2310 .minor = SCI_MINOR_START,
e108b2ca 2311 .nr = SCI_NPORTS,
1da177e4
LT		 2312 .cons = SCI_CONSOLE,
2313};
2314
54507f6e 2315static int sci_remove(struct platform_device *dev)
e552de24 2316{
d535a230 2317 struct sci_port *port = platform_get_drvdata(dev);
e552de24 2318
d535a230
PM		 2319 cpufreq_unregister_notifier(&port->freq_transition,
2320 CPUFREQ_TRANSITION_NOTIFIER);
e552de24 2321
d535a230
PM		 2322 uart_remove_one_port(&sci_uart_driver, &port->port);
2323
6dae1421 2324 sci_cleanup_single(port);
e552de24 2325
e552de24
MD		 2326 return 0;
2327}
2328
0ee70712
MD		 2329static int __devinit sci_probe_single(struct platform_device *dev,
2330 unsigned int index,
2331 struct plat_sci_port *p,
2332 struct sci_port *sciport)
2333{
0ee70712
MD		 2334 int ret;
2335
2336 /* Sanity check */
2337 if (unlikely(index >= SCI_NPORTS)) {
2338 dev_notice(&dev->dev, "Attempting to register port "
2339 "%d when only %d are available.\n",
2340 index+1, SCI_NPORTS);
2341 dev_notice(&dev->dev, "Consider bumping "
2342 "CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
b6c5ef6f 2343 return -EINVAL;
0ee70712
MD		 2344 }
2345
c7ed1ab3
PM		 2346 ret = sci_init_single(dev, sciport, index, p);
2347 if (ret)
2348 return ret;
0ee70712 2349
6dae1421
LP		 2350 ret = uart_add_one_port(&sci_uart_driver, &sciport->port);
2351 if (ret) {
2352 sci_cleanup_single(sciport);
2353 return ret;
2354 }
2355
2356 return 0;
0ee70712
MD		 2357}
2358
e108b2ca 2359static int __devinit sci_probe(struct platform_device *dev)
1da177e4 2360{
e108b2ca 2361 struct plat_sci_port *p = dev->dev.platform_data;
d535a230 2362 struct sci_port *sp = &sci_ports[dev->id];
ecdf8a46 2363 int ret;
d535a230 2364
ecdf8a46
PM		 2365 /*
2366 * If we've come here via earlyprintk initialization, head off to
2367 * the special early probe. We don't have sufficient device state
2368 * to make it beyond this yet.
2369 */
2370 if (is_early_platform_device(dev))
2371 return sci_probe_earlyprintk(dev);
7b6fd3bf 2372
d535a230 2373 platform_set_drvdata(dev, sp);
e552de24 2374
906b17dc 2375 ret = sci_probe_single(dev, dev->id, p, sp);
d535a230 2376 if (ret)
6dae1421 2377 return ret;
e552de24 2378
d535a230 2379 sp->freq_transition.notifier_call = sci_notifier;
1da177e4 2380
d535a230
PM		 2381 ret = cpufreq_register_notifier(&sp->freq_transition,
2382 CPUFREQ_TRANSITION_NOTIFIER);
6dae1421
LP		 2383 if (unlikely(ret < 0)) {
2384 sci_cleanup_single(sp);
2385 return ret;
2386 }
1da177e4
LT		 2387
2388#ifdef CONFIG_SH_STANDARD_BIOS
2389 sh_bios_gdb_detach();
2390#endif
2391
e108b2ca 2392 return 0;
1da177e4
LT		 2393}
2394
6daa79b3 2395static int sci_suspend(struct device *dev)
1da177e4 2396{
d535a230 2397 struct sci_port *sport = dev_get_drvdata(dev);
e108b2ca 2398
d535a230
PM		 2399 if (sport)
2400 uart_suspend_port(&sci_uart_driver, &sport->port);
1da177e4 2401
e108b2ca
PM		 2402 return 0;
2403}
1da177e4 2404
6daa79b3 2405static int sci_resume(struct device *dev)
e108b2ca 2406{
d535a230 2407 struct sci_port *sport = dev_get_drvdata(dev);
e108b2ca 2408
d535a230
PM		 2409 if (sport)
2410 uart_resume_port(&sci_uart_driver, &sport->port);
e108b2ca
PM		 2411
2412 return 0;
2413}
2414
47145210 2415static const struct dev_pm_ops sci_dev_pm_ops = {
6daa79b3
PM		 2416 .suspend = sci_suspend,
2417 .resume = sci_resume,
2418};
2419
e108b2ca
PM		 2420static struct platform_driver sci_driver = {
2421 .probe = sci_probe,
b9e39c89 2422 .remove = sci_remove,
e108b2ca
PM		 2423 .driver = {
2424 .name = "sh-sci",
2425 .owner = THIS_MODULE,
6daa79b3 2426 .pm = &sci_dev_pm_ops,
e108b2ca
PM		 2427 },
2428};
2429
2430static int __init sci_init(void)
2431{
2432 int ret;
2433
2434 printk(banner);
2435
e108b2ca
PM		 2436 ret = uart_register_driver(&sci_uart_driver);
2437 if (likely(ret == 0)) {
2438 ret = platform_driver_register(&sci_driver);
2439 if (unlikely(ret))
2440 uart_unregister_driver(&sci_uart_driver);
2441 }
2442
2443 return ret;
2444}
2445
2446static void __exit sci_exit(void)
2447{
2448 platform_driver_unregister(&sci_driver);
1da177e4
LT		 2449 uart_unregister_driver(&sci_uart_driver);
2450}
2451
7b6fd3bf
MD		 2452#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
2453early_platform_init_buffer("earlyprintk", &sci_driver,
2454 early_serial_buf, ARRAY_SIZE(early_serial_buf));
2455#endif
1da177e4
LT		 2456module_init(sci_init);
2457module_exit(sci_exit);
2458
e108b2ca 2459MODULE_LICENSE("GPL");
e169c139 2460MODULE_ALIAS("platform:sh-sci");
7f405f9c
PM		 2461MODULE_AUTHOR("Paul Mundt");
2462MODULE_DESCRIPTION("SuperH SCI(F) serial driver");
Linux 6.x block layer and io_uring tree(s)