Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
1da177e4 LT |
2 | * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO) |
3 | * | |
f43dc23d | 4 | * Copyright (C) 2002 - 2011 Paul Mundt |
3ea6bc3d | 5 | * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007). |
1da177e4 LT |
6 | * |
7 | * based off of the old drivers/char/sh-sci.c by: | |
8 | * | |
9 | * Copyright (C) 1999, 2000 Niibe Yutaka | |
10 | * Copyright (C) 2000 Sugioka Toshinobu | |
11 | * Modified to support multiple serial ports. Stuart Menefy (May 2000). | |
12 | * Modified to support SecureEdge. David McCullough (2002) | |
13 | * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003). | |
d89ddd1c | 14 | * Removed SH7300 support (Jul 2007). |
1da177e4 LT |
15 | * |
16 | * This file is subject to the terms and conditions of the GNU General Public | |
17 | * License. See the file "COPYING" in the main directory of this archive | |
18 | * for more details. | |
19 | */ | |
0b3d4ef6 PM |
20 | #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) |
21 | #define SUPPORT_SYSRQ | |
22 | #endif | |
1da177e4 LT |
23 | |
24 | #undef DEBUG | |
25 | ||
8fb9631c LP |
26 | #include <linux/clk.h> |
27 | #include <linux/console.h> | |
28 | #include <linux/ctype.h> | |
29 | #include <linux/cpufreq.h> | |
30 | #include <linux/delay.h> | |
31 | #include <linux/dmaengine.h> | |
32 | #include <linux/dma-mapping.h> | |
33 | #include <linux/err.h> | |
1da177e4 | 34 | #include <linux/errno.h> |
8fb9631c | 35 | #include <linux/init.h> |
1da177e4 | 36 | #include <linux/interrupt.h> |
1da177e4 | 37 | #include <linux/ioport.h> |
8fb9631c LP |
38 | #include <linux/major.h> |
39 | #include <linux/module.h> | |
1da177e4 | 40 | #include <linux/mm.h> |
1da177e4 | 41 | #include <linux/notifier.h> |
20bdcab8 | 42 | #include <linux/of.h> |
8fb9631c | 43 | #include <linux/platform_device.h> |
5e50d2d6 | 44 | #include <linux/pm_runtime.h> |
73a19e4c | 45 | #include <linux/scatterlist.h> |
8fb9631c LP |
46 | #include <linux/serial.h> |
47 | #include <linux/serial_sci.h> | |
48 | #include <linux/sh_dma.h> | |
5a0e3ad6 | 49 | #include <linux/slab.h> |
8fb9631c LP |
50 | #include <linux/string.h> |
51 | #include <linux/sysrq.h> | |
52 | #include <linux/timer.h> | |
53 | #include <linux/tty.h> | |
54 | #include <linux/tty_flip.h> | |
85f094ec PM |
55 | |
56 | #ifdef CONFIG_SUPERH | |
1da177e4 LT |
57 | #include <asm/sh_bios.h> |
58 | #endif | |
59 | ||
1da177e4 LT |
60 | #include "sh-sci.h" |
61 | ||
89b5c1ab LP |
62 | /* Offsets into the sci_port->irqs array */ |
63 | enum { | |
64 | SCIx_ERI_IRQ, | |
65 | SCIx_RXI_IRQ, | |
66 | SCIx_TXI_IRQ, | |
67 | SCIx_BRI_IRQ, | |
68 | SCIx_NR_IRQS, | |
69 | ||
70 | SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */ | |
71 | }; | |
72 | ||
73 | #define SCIx_IRQ_IS_MUXED(port) \ | |
74 | ((port)->irqs[SCIx_ERI_IRQ] == \ | |
75 | (port)->irqs[SCIx_RXI_IRQ]) || \ | |
76 | ((port)->irqs[SCIx_ERI_IRQ] && \ | |
77 | ((port)->irqs[SCIx_RXI_IRQ] < 0)) | |
78 | ||
e108b2ca PM |
79 | struct sci_port { |
80 | struct uart_port port; | |
81 | ||
ce6738b6 PM |
82 | /* Platform configuration */ |
83 | struct plat_sci_port *cfg; | |
3ae988d9 LP |
84 | int overrun_bit; |
85 | unsigned int error_mask; | |
ec09c5eb | 86 | unsigned int sampling_rate; |
3ae988d9 | 87 | |
e108b2ca | 88 | |
e108b2ca PM |
89 | /* Break timer */ |
90 | struct timer_list break_timer; | |
91 | int break_flag; | |
1534a3b3 | 92 | |
501b825d MD |
93 | /* Interface clock */ |
94 | struct clk *iclk; | |
c7ed1ab3 PM |
95 | /* Function clock */ |
96 | struct clk *fclk; | |
edad1f20 | 97 | |
1fcc91a6 | 98 | int irqs[SCIx_NR_IRQS]; |
9174fc8f PM |
99 | char *irqstr[SCIx_NR_IRQS]; |
100 | ||
73a19e4c GL |
101 | struct dma_chan *chan_tx; |
102 | struct dma_chan *chan_rx; | |
f43dc23d | 103 | |
73a19e4c | 104 | #ifdef CONFIG_SERIAL_SH_SCI_DMA |
73a19e4c GL |
105 | struct dma_async_tx_descriptor *desc_tx; |
106 | struct dma_async_tx_descriptor *desc_rx[2]; | |
107 | dma_cookie_t cookie_tx; | |
108 | dma_cookie_t cookie_rx[2]; | |
109 | dma_cookie_t active_rx; | |
110 | struct scatterlist sg_tx; | |
111 | unsigned int sg_len_tx; | |
112 | struct scatterlist sg_rx[2]; | |
113 | size_t buf_len_rx; | |
114 | struct sh_dmae_slave param_tx; | |
115 | struct sh_dmae_slave param_rx; | |
116 | struct work_struct work_tx; | |
117 | struct work_struct work_rx; | |
118 | struct timer_list rx_timer; | |
3089f381 | 119 | unsigned int rx_timeout; |
73a19e4c | 120 | #endif |
e552de24 | 121 | |
d535a230 | 122 | struct notifier_block freq_transition; |
e108b2ca PM |
123 | }; |
124 | ||
1da177e4 | 125 | /* Function prototypes */ |
d535a230 | 126 | static void sci_start_tx(struct uart_port *port); |
b129a8cc | 127 | static void sci_stop_tx(struct uart_port *port); |
d535a230 | 128 | static void sci_start_rx(struct uart_port *port); |
1da177e4 | 129 | |
e108b2ca | 130 | #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS |
b7a76e4b | 131 | |
e108b2ca PM |
132 | static struct sci_port sci_ports[SCI_NPORTS]; |
133 | static struct uart_driver sci_uart_driver; | |
1da177e4 | 134 | |
e7c98dc7 MT |
135 | static inline struct sci_port * |
136 | to_sci_port(struct uart_port *uart) | |
137 | { | |
138 | return container_of(uart, struct sci_port, port); | |
139 | } | |
140 | ||
61a6976b PM |
141 | struct plat_sci_reg { |
142 | u8 offset, size; | |
143 | }; | |
144 | ||
145 | /* Helper for invalidating specific entries of an inherited map. */ | |
146 | #define sci_reg_invalid { .offset = 0, .size = 0 } | |
147 | ||
148 | static struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = { | |
149 | [SCIx_PROBE_REGTYPE] = { | |
150 | [0 ... SCIx_NR_REGS - 1] = sci_reg_invalid, | |
151 | }, | |
152 | ||
153 | /* | |
154 | * Common SCI definitions, dependent on the port's regshift | |
155 | * value. | |
156 | */ | |
157 | [SCIx_SCI_REGTYPE] = { | |
158 | [SCSMR] = { 0x00, 8 }, | |
159 | [SCBRR] = { 0x01, 8 }, | |
160 | [SCSCR] = { 0x02, 8 }, | |
161 | [SCxTDR] = { 0x03, 8 }, | |
162 | [SCxSR] = { 0x04, 8 }, | |
163 | [SCxRDR] = { 0x05, 8 }, | |
164 | [SCFCR] = sci_reg_invalid, | |
165 | [SCFDR] = sci_reg_invalid, | |
166 | [SCTFDR] = sci_reg_invalid, | |
167 | [SCRFDR] = sci_reg_invalid, | |
168 | [SCSPTR] = sci_reg_invalid, | |
169 | [SCLSR] = sci_reg_invalid, | |
f303b364 | 170 | [HSSRR] = sci_reg_invalid, |
61a6976b PM |
171 | }, |
172 | ||
173 | /* | |
174 | * Common definitions for legacy IrDA ports, dependent on | |
175 | * regshift value. | |
176 | */ | |
177 | [SCIx_IRDA_REGTYPE] = { | |
178 | [SCSMR] = { 0x00, 8 }, | |
179 | [SCBRR] = { 0x01, 8 }, | |
180 | [SCSCR] = { 0x02, 8 }, | |
181 | [SCxTDR] = { 0x03, 8 }, | |
182 | [SCxSR] = { 0x04, 8 }, | |
183 | [SCxRDR] = { 0x05, 8 }, | |
184 | [SCFCR] = { 0x06, 8 }, | |
185 | [SCFDR] = { 0x07, 16 }, | |
186 | [SCTFDR] = sci_reg_invalid, | |
187 | [SCRFDR] = sci_reg_invalid, | |
188 | [SCSPTR] = sci_reg_invalid, | |
189 | [SCLSR] = sci_reg_invalid, | |
f303b364 | 190 | [HSSRR] = sci_reg_invalid, |
61a6976b PM |
191 | }, |
192 | ||
193 | /* | |
194 | * Common SCIFA definitions. | |
195 | */ | |
196 | [SCIx_SCIFA_REGTYPE] = { | |
197 | [SCSMR] = { 0x00, 16 }, | |
198 | [SCBRR] = { 0x04, 8 }, | |
199 | [SCSCR] = { 0x08, 16 }, | |
200 | [SCxTDR] = { 0x20, 8 }, | |
201 | [SCxSR] = { 0x14, 16 }, | |
202 | [SCxRDR] = { 0x24, 8 }, | |
203 | [SCFCR] = { 0x18, 16 }, | |
204 | [SCFDR] = { 0x1c, 16 }, | |
205 | [SCTFDR] = sci_reg_invalid, | |
206 | [SCRFDR] = sci_reg_invalid, | |
207 | [SCSPTR] = sci_reg_invalid, | |
208 | [SCLSR] = sci_reg_invalid, | |
f303b364 | 209 | [HSSRR] = sci_reg_invalid, |
61a6976b PM |
210 | }, |
211 | ||
212 | /* | |
213 | * Common SCIFB definitions. | |
214 | */ | |
215 | [SCIx_SCIFB_REGTYPE] = { | |
216 | [SCSMR] = { 0x00, 16 }, | |
217 | [SCBRR] = { 0x04, 8 }, | |
218 | [SCSCR] = { 0x08, 16 }, | |
219 | [SCxTDR] = { 0x40, 8 }, | |
220 | [SCxSR] = { 0x14, 16 }, | |
221 | [SCxRDR] = { 0x60, 8 }, | |
222 | [SCFCR] = { 0x18, 16 }, | |
8c66d6d2 TY |
223 | [SCFDR] = sci_reg_invalid, |
224 | [SCTFDR] = { 0x38, 16 }, | |
225 | [SCRFDR] = { 0x3c, 16 }, | |
61a6976b PM |
226 | [SCSPTR] = sci_reg_invalid, |
227 | [SCLSR] = sci_reg_invalid, | |
f303b364 | 228 | [HSSRR] = sci_reg_invalid, |
61a6976b PM |
229 | }, |
230 | ||
3af1f8a4 PE |
231 | /* |
232 | * Common SH-2(A) SCIF definitions for ports with FIFO data | |
233 | * count registers. | |
234 | */ | |
235 | [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = { | |
236 | [SCSMR] = { 0x00, 16 }, | |
237 | [SCBRR] = { 0x04, 8 }, | |
238 | [SCSCR] = { 0x08, 16 }, | |
239 | [SCxTDR] = { 0x0c, 8 }, | |
240 | [SCxSR] = { 0x10, 16 }, | |
241 | [SCxRDR] = { 0x14, 8 }, | |
242 | [SCFCR] = { 0x18, 16 }, | |
243 | [SCFDR] = { 0x1c, 16 }, | |
244 | [SCTFDR] = sci_reg_invalid, | |
245 | [SCRFDR] = sci_reg_invalid, | |
246 | [SCSPTR] = { 0x20, 16 }, | |
247 | [SCLSR] = { 0x24, 16 }, | |
f303b364 | 248 | [HSSRR] = sci_reg_invalid, |
3af1f8a4 PE |
249 | }, |
250 | ||
61a6976b PM |
251 | /* |
252 | * Common SH-3 SCIF definitions. | |
253 | */ | |
254 | [SCIx_SH3_SCIF_REGTYPE] = { | |
255 | [SCSMR] = { 0x00, 8 }, | |
256 | [SCBRR] = { 0x02, 8 }, | |
257 | [SCSCR] = { 0x04, 8 }, | |
258 | [SCxTDR] = { 0x06, 8 }, | |
259 | [SCxSR] = { 0x08, 16 }, | |
260 | [SCxRDR] = { 0x0a, 8 }, | |
261 | [SCFCR] = { 0x0c, 8 }, | |
262 | [SCFDR] = { 0x0e, 16 }, | |
263 | [SCTFDR] = sci_reg_invalid, | |
264 | [SCRFDR] = sci_reg_invalid, | |
265 | [SCSPTR] = sci_reg_invalid, | |
266 | [SCLSR] = sci_reg_invalid, | |
f303b364 | 267 | [HSSRR] = sci_reg_invalid, |
61a6976b PM |
268 | }, |
269 | ||
270 | /* | |
271 | * Common SH-4(A) SCIF(B) definitions. | |
272 | */ | |
273 | [SCIx_SH4_SCIF_REGTYPE] = { | |
274 | [SCSMR] = { 0x00, 16 }, | |
275 | [SCBRR] = { 0x04, 8 }, | |
276 | [SCSCR] = { 0x08, 16 }, | |
277 | [SCxTDR] = { 0x0c, 8 }, | |
278 | [SCxSR] = { 0x10, 16 }, | |
279 | [SCxRDR] = { 0x14, 8 }, | |
280 | [SCFCR] = { 0x18, 16 }, | |
281 | [SCFDR] = { 0x1c, 16 }, | |
282 | [SCTFDR] = sci_reg_invalid, | |
283 | [SCRFDR] = sci_reg_invalid, | |
284 | [SCSPTR] = { 0x20, 16 }, | |
285 | [SCLSR] = { 0x24, 16 }, | |
f303b364 UH |
286 | [HSSRR] = sci_reg_invalid, |
287 | }, | |
288 | ||
289 | /* | |
290 | * Common HSCIF definitions. | |
291 | */ | |
292 | [SCIx_HSCIF_REGTYPE] = { | |
293 | [SCSMR] = { 0x00, 16 }, | |
294 | [SCBRR] = { 0x04, 8 }, | |
295 | [SCSCR] = { 0x08, 16 }, | |
296 | [SCxTDR] = { 0x0c, 8 }, | |
297 | [SCxSR] = { 0x10, 16 }, | |
298 | [SCxRDR] = { 0x14, 8 }, | |
299 | [SCFCR] = { 0x18, 16 }, | |
300 | [SCFDR] = { 0x1c, 16 }, | |
301 | [SCTFDR] = sci_reg_invalid, | |
302 | [SCRFDR] = sci_reg_invalid, | |
303 | [SCSPTR] = { 0x20, 16 }, | |
304 | [SCLSR] = { 0x24, 16 }, | |
305 | [HSSRR] = { 0x40, 16 }, | |
61a6976b PM |
306 | }, |
307 | ||
308 | /* | |
309 | * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR | |
310 | * register. | |
311 | */ | |
312 | [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = { | |
313 | [SCSMR] = { 0x00, 16 }, | |
314 | [SCBRR] = { 0x04, 8 }, | |
315 | [SCSCR] = { 0x08, 16 }, | |
316 | [SCxTDR] = { 0x0c, 8 }, | |
317 | [SCxSR] = { 0x10, 16 }, | |
318 | [SCxRDR] = { 0x14, 8 }, | |
319 | [SCFCR] = { 0x18, 16 }, | |
320 | [SCFDR] = { 0x1c, 16 }, | |
321 | [SCTFDR] = sci_reg_invalid, | |
322 | [SCRFDR] = sci_reg_invalid, | |
323 | [SCSPTR] = sci_reg_invalid, | |
324 | [SCLSR] = { 0x24, 16 }, | |
f303b364 | 325 | [HSSRR] = sci_reg_invalid, |
61a6976b PM |
326 | }, |
327 | ||
328 | /* | |
329 | * Common SH-4(A) SCIF(B) definitions for ports with FIFO data | |
330 | * count registers. | |
331 | */ | |
332 | [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = { | |
333 | [SCSMR] = { 0x00, 16 }, | |
334 | [SCBRR] = { 0x04, 8 }, | |
335 | [SCSCR] = { 0x08, 16 }, | |
336 | [SCxTDR] = { 0x0c, 8 }, | |
337 | [SCxSR] = { 0x10, 16 }, | |
338 | [SCxRDR] = { 0x14, 8 }, | |
339 | [SCFCR] = { 0x18, 16 }, | |
340 | [SCFDR] = { 0x1c, 16 }, | |
341 | [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */ | |
342 | [SCRFDR] = { 0x20, 16 }, | |
343 | [SCSPTR] = { 0x24, 16 }, | |
344 | [SCLSR] = { 0x28, 16 }, | |
f303b364 | 345 | [HSSRR] = sci_reg_invalid, |
61a6976b PM |
346 | }, |
347 | ||
348 | /* | |
349 | * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR | |
350 | * registers. | |
351 | */ | |
352 | [SCIx_SH7705_SCIF_REGTYPE] = { | |
353 | [SCSMR] = { 0x00, 16 }, | |
354 | [SCBRR] = { 0x04, 8 }, | |
355 | [SCSCR] = { 0x08, 16 }, | |
356 | [SCxTDR] = { 0x20, 8 }, | |
357 | [SCxSR] = { 0x14, 16 }, | |
358 | [SCxRDR] = { 0x24, 8 }, | |
359 | [SCFCR] = { 0x18, 16 }, | |
360 | [SCFDR] = { 0x1c, 16 }, | |
361 | [SCTFDR] = sci_reg_invalid, | |
362 | [SCRFDR] = sci_reg_invalid, | |
363 | [SCSPTR] = sci_reg_invalid, | |
364 | [SCLSR] = sci_reg_invalid, | |
f303b364 | 365 | [HSSRR] = sci_reg_invalid, |
61a6976b PM |
366 | }, |
367 | }; | |
368 | ||
72b294cf PM |
369 | #define sci_getreg(up, offset) (sci_regmap[to_sci_port(up)->cfg->regtype] + offset) |
370 | ||
61a6976b PM |
371 | /* |
372 | * The "offset" here is rather misleading, in that it refers to an enum | |
373 | * value relative to the port mapping rather than the fixed offset | |
374 | * itself, which needs to be manually retrieved from the platform's | |
375 | * register map for the given port. | |
376 | */ | |
377 | static unsigned int sci_serial_in(struct uart_port *p, int offset) | |
378 | { | |
72b294cf | 379 | struct plat_sci_reg *reg = sci_getreg(p, offset); |
61a6976b PM |
380 | |
381 | if (reg->size == 8) | |
382 | return ioread8(p->membase + (reg->offset << p->regshift)); | |
383 | else if (reg->size == 16) | |
384 | return ioread16(p->membase + (reg->offset << p->regshift)); | |
385 | else | |
386 | WARN(1, "Invalid register access\n"); | |
387 | ||
388 | return 0; | |
389 | } | |
390 | ||
391 | static void sci_serial_out(struct uart_port *p, int offset, int value) | |
392 | { | |
72b294cf | 393 | struct plat_sci_reg *reg = sci_getreg(p, offset); |
61a6976b PM |
394 | |
395 | if (reg->size == 8) | |
396 | iowrite8(value, p->membase + (reg->offset << p->regshift)); | |
397 | else if (reg->size == 16) | |
398 | iowrite16(value, p->membase + (reg->offset << p->regshift)); | |
399 | else | |
400 | WARN(1, "Invalid register access\n"); | |
401 | } | |
402 | ||
61a6976b PM |
403 | static int sci_probe_regmap(struct plat_sci_port *cfg) |
404 | { | |
405 | switch (cfg->type) { | |
406 | case PORT_SCI: | |
407 | cfg->regtype = SCIx_SCI_REGTYPE; | |
408 | break; | |
409 | case PORT_IRDA: | |
410 | cfg->regtype = SCIx_IRDA_REGTYPE; | |
411 | break; | |
412 | case PORT_SCIFA: | |
413 | cfg->regtype = SCIx_SCIFA_REGTYPE; | |
414 | break; | |
415 | case PORT_SCIFB: | |
416 | cfg->regtype = SCIx_SCIFB_REGTYPE; | |
417 | break; | |
418 | case PORT_SCIF: | |
419 | /* | |
420 | * The SH-4 is a bit of a misnomer here, although that's | |
421 | * where this particular port layout originated. This | |
422 | * configuration (or some slight variation thereof) | |
423 | * remains the dominant model for all SCIFs. | |
424 | */ | |
425 | cfg->regtype = SCIx_SH4_SCIF_REGTYPE; | |
426 | break; | |
f303b364 UH |
427 | case PORT_HSCIF: |
428 | cfg->regtype = SCIx_HSCIF_REGTYPE; | |
429 | break; | |
61a6976b PM |
430 | default: |
431 | printk(KERN_ERR "Can't probe register map for given port\n"); | |
432 | return -EINVAL; | |
433 | } | |
434 | ||
435 | return 0; | |
436 | } | |
437 | ||
23241d43 PM |
438 | static void sci_port_enable(struct sci_port *sci_port) |
439 | { | |
440 | if (!sci_port->port.dev) | |
441 | return; | |
442 | ||
443 | pm_runtime_get_sync(sci_port->port.dev); | |
444 | ||
b016b646 | 445 | clk_prepare_enable(sci_port->iclk); |
23241d43 | 446 | sci_port->port.uartclk = clk_get_rate(sci_port->iclk); |
b016b646 | 447 | clk_prepare_enable(sci_port->fclk); |
23241d43 PM |
448 | } |
449 | ||
450 | static void sci_port_disable(struct sci_port *sci_port) | |
451 | { | |
452 | if (!sci_port->port.dev) | |
453 | return; | |
454 | ||
caec7038 LP |
455 | /* Cancel the break timer to ensure that the timer handler will not try |
456 | * to access the hardware with clocks and power disabled. Reset the | |
457 | * break flag to make the break debouncing state machine ready for the | |
458 | * next break. | |
459 | */ | |
460 | del_timer_sync(&sci_port->break_timer); | |
461 | sci_port->break_flag = 0; | |
462 | ||
b016b646 LP |
463 | clk_disable_unprepare(sci_port->fclk); |
464 | clk_disable_unprepare(sci_port->iclk); | |
23241d43 PM |
465 | |
466 | pm_runtime_put_sync(sci_port->port.dev); | |
467 | } | |
468 | ||
07d2a1a1 | 469 | #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE) |
1f6fd5c9 PM |
470 | |
471 | #ifdef CONFIG_CONSOLE_POLL | |
07d2a1a1 | 472 | static int sci_poll_get_char(struct uart_port *port) |
1da177e4 | 473 | { |
1da177e4 LT |
474 | unsigned short status; |
475 | int c; | |
476 | ||
e108b2ca | 477 | do { |
b12bb29f | 478 | status = serial_port_in(port, SCxSR); |
1da177e4 | 479 | if (status & SCxSR_ERRORS(port)) { |
b12bb29f | 480 | serial_port_out(port, SCxSR, SCxSR_ERROR_CLEAR(port)); |
1da177e4 LT |
481 | continue; |
482 | } | |
3f255eb3 JW |
483 | break; |
484 | } while (1); | |
485 | ||
486 | if (!(status & SCxSR_RDxF(port))) | |
487 | return NO_POLL_CHAR; | |
07d2a1a1 | 488 | |
b12bb29f | 489 | c = serial_port_in(port, SCxRDR); |
07d2a1a1 | 490 | |
e7c98dc7 | 491 | /* Dummy read */ |
b12bb29f PM |
492 | serial_port_in(port, SCxSR); |
493 | serial_port_out(port, SCxSR, SCxSR_RDxF_CLEAR(port)); | |
1da177e4 LT |
494 | |
495 | return c; | |
496 | } | |
1f6fd5c9 | 497 | #endif |
1da177e4 | 498 | |
07d2a1a1 | 499 | static void sci_poll_put_char(struct uart_port *port, unsigned char c) |
1da177e4 | 500 | { |
1da177e4 LT |
501 | unsigned short status; |
502 | ||
1da177e4 | 503 | do { |
b12bb29f | 504 | status = serial_port_in(port, SCxSR); |
1da177e4 LT |
505 | } while (!(status & SCxSR_TDxE(port))); |
506 | ||
b12bb29f PM |
507 | serial_port_out(port, SCxTDR, c); |
508 | serial_port_out(port, SCxSR, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port)); | |
1da177e4 | 509 | } |
07d2a1a1 | 510 | #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE */ |
1da177e4 | 511 | |
61a6976b | 512 | static void sci_init_pins(struct uart_port *port, unsigned int cflag) |
1da177e4 | 513 | { |
61a6976b PM |
514 | struct sci_port *s = to_sci_port(port); |
515 | struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR; | |
1da177e4 | 516 | |
61a6976b PM |
517 | /* |
518 | * Use port-specific handler if provided. | |
519 | */ | |
520 | if (s->cfg->ops && s->cfg->ops->init_pins) { | |
521 | s->cfg->ops->init_pins(port, cflag); | |
522 | return; | |
1da177e4 | 523 | } |
41504c39 | 524 | |
61a6976b PM |
525 | /* |
526 | * For the generic path SCSPTR is necessary. Bail out if that's | |
527 | * unavailable, too. | |
528 | */ | |
529 | if (!reg->size) | |
530 | return; | |
41504c39 | 531 | |
faf02f8f PM |
532 | if ((s->cfg->capabilities & SCIx_HAVE_RTSCTS) && |
533 | ((!(cflag & CRTSCTS)))) { | |
534 | unsigned short status; | |
535 | ||
b12bb29f | 536 | status = serial_port_in(port, SCSPTR); |
faf02f8f PM |
537 | status &= ~SCSPTR_CTSIO; |
538 | status |= SCSPTR_RTSIO; | |
b12bb29f | 539 | serial_port_out(port, SCSPTR, status); /* Set RTS = 1 */ |
faf02f8f | 540 | } |
d5701647 | 541 | } |
e108b2ca | 542 | |
72b294cf | 543 | static int sci_txfill(struct uart_port *port) |
e108b2ca | 544 | { |
72b294cf | 545 | struct plat_sci_reg *reg; |
e108b2ca | 546 | |
72b294cf PM |
547 | reg = sci_getreg(port, SCTFDR); |
548 | if (reg->size) | |
63f7ad11 | 549 | return serial_port_in(port, SCTFDR) & ((port->fifosize << 1) - 1); |
c63847a3 | 550 | |
72b294cf PM |
551 | reg = sci_getreg(port, SCFDR); |
552 | if (reg->size) | |
b12bb29f | 553 | return serial_port_in(port, SCFDR) >> 8; |
d1d4b10c | 554 | |
b12bb29f | 555 | return !(serial_port_in(port, SCxSR) & SCI_TDRE); |
e108b2ca PM |
556 | } |
557 | ||
73a19e4c GL |
558 | static int sci_txroom(struct uart_port *port) |
559 | { | |
72b294cf | 560 | return port->fifosize - sci_txfill(port); |
73a19e4c GL |
561 | } |
562 | ||
563 | static int sci_rxfill(struct uart_port *port) | |
e108b2ca | 564 | { |
72b294cf PM |
565 | struct plat_sci_reg *reg; |
566 | ||
567 | reg = sci_getreg(port, SCRFDR); | |
568 | if (reg->size) | |
63f7ad11 | 569 | return serial_port_in(port, SCRFDR) & ((port->fifosize << 1) - 1); |
72b294cf PM |
570 | |
571 | reg = sci_getreg(port, SCFDR); | |
572 | if (reg->size) | |
b12bb29f | 573 | return serial_port_in(port, SCFDR) & ((port->fifosize << 1) - 1); |
72b294cf | 574 | |
b12bb29f | 575 | return (serial_port_in(port, SCxSR) & SCxSR_RDxF(port)) != 0; |
e108b2ca PM |
576 | } |
577 | ||
514820eb PM |
578 | /* |
579 | * SCI helper for checking the state of the muxed port/RXD pins. | |
580 | */ | |
581 | static inline int sci_rxd_in(struct uart_port *port) | |
582 | { | |
583 | struct sci_port *s = to_sci_port(port); | |
584 | ||
585 | if (s->cfg->port_reg <= 0) | |
586 | return 1; | |
587 | ||
0dd4d5cb | 588 | /* Cast for ARM damage */ |
e2afca69 | 589 | return !!__raw_readb((void __iomem *)(uintptr_t)s->cfg->port_reg); |
514820eb PM |
590 | } |
591 | ||
1da177e4 LT |
592 | /* ********************************************************************** * |
593 | * the interrupt related routines * | |
594 | * ********************************************************************** */ | |
595 | ||
596 | static void sci_transmit_chars(struct uart_port *port) | |
597 | { | |
ebd2c8f6 | 598 | struct circ_buf *xmit = &port->state->xmit; |
1da177e4 | 599 | unsigned int stopped = uart_tx_stopped(port); |
1da177e4 LT |
600 | unsigned short status; |
601 | unsigned short ctrl; | |
e108b2ca | 602 | int count; |
1da177e4 | 603 | |
b12bb29f | 604 | status = serial_port_in(port, SCxSR); |
1da177e4 | 605 | if (!(status & SCxSR_TDxE(port))) { |
b12bb29f | 606 | ctrl = serial_port_in(port, SCSCR); |
e7c98dc7 | 607 | if (uart_circ_empty(xmit)) |
8e698614 | 608 | ctrl &= ~SCSCR_TIE; |
e7c98dc7 | 609 | else |
8e698614 | 610 | ctrl |= SCSCR_TIE; |
b12bb29f | 611 | serial_port_out(port, SCSCR, ctrl); |
1da177e4 LT |
612 | return; |
613 | } | |
614 | ||
72b294cf | 615 | count = sci_txroom(port); |
1da177e4 LT |
616 | |
617 | do { | |
618 | unsigned char c; | |
619 | ||
620 | if (port->x_char) { | |
621 | c = port->x_char; | |
622 | port->x_char = 0; | |
623 | } else if (!uart_circ_empty(xmit) && !stopped) { | |
624 | c = xmit->buf[xmit->tail]; | |
625 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); | |
626 | } else { | |
627 | break; | |
628 | } | |
629 | ||
b12bb29f | 630 | serial_port_out(port, SCxTDR, c); |
1da177e4 LT |
631 | |
632 | port->icount.tx++; | |
633 | } while (--count > 0); | |
634 | ||
b12bb29f | 635 | serial_port_out(port, SCxSR, SCxSR_TDxE_CLEAR(port)); |
1da177e4 LT |
636 | |
637 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
638 | uart_write_wakeup(port); | |
639 | if (uart_circ_empty(xmit)) { | |
b129a8cc | 640 | sci_stop_tx(port); |
1da177e4 | 641 | } else { |
b12bb29f | 642 | ctrl = serial_port_in(port, SCSCR); |
1da177e4 | 643 | |
1a22f08d | 644 | if (port->type != PORT_SCI) { |
b12bb29f PM |
645 | serial_port_in(port, SCxSR); /* Dummy read */ |
646 | serial_port_out(port, SCxSR, SCxSR_TDxE_CLEAR(port)); | |
1da177e4 | 647 | } |
1da177e4 | 648 | |
8e698614 | 649 | ctrl |= SCSCR_TIE; |
b12bb29f | 650 | serial_port_out(port, SCSCR, ctrl); |
1da177e4 LT |
651 | } |
652 | } | |
653 | ||
654 | /* On SH3, SCIF may read end-of-break as a space->mark char */ | |
e7c98dc7 | 655 | #define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); }) |
1da177e4 | 656 | |
94c8b6db | 657 | static void sci_receive_chars(struct uart_port *port) |
1da177e4 | 658 | { |
e7c98dc7 | 659 | struct sci_port *sci_port = to_sci_port(port); |
227434f8 | 660 | struct tty_port *tport = &port->state->port; |
1da177e4 LT |
661 | int i, count, copied = 0; |
662 | unsigned short status; | |
33f0f88f | 663 | unsigned char flag; |
1da177e4 | 664 | |
b12bb29f | 665 | status = serial_port_in(port, SCxSR); |
1da177e4 LT |
666 | if (!(status & SCxSR_RDxF(port))) |
667 | return; | |
668 | ||
669 | while (1) { | |
1da177e4 | 670 | /* Don't copy more bytes than there is room for in the buffer */ |
227434f8 | 671 | count = tty_buffer_request_room(tport, sci_rxfill(port)); |
1da177e4 LT |
672 | |
673 | /* If for any reason we can't copy more data, we're done! */ | |
674 | if (count == 0) | |
675 | break; | |
676 | ||
677 | if (port->type == PORT_SCI) { | |
b12bb29f | 678 | char c = serial_port_in(port, SCxRDR); |
e7c98dc7 MT |
679 | if (uart_handle_sysrq_char(port, c) || |
680 | sci_port->break_flag) | |
1da177e4 | 681 | count = 0; |
e7c98dc7 | 682 | else |
92a19f9c | 683 | tty_insert_flip_char(tport, c, TTY_NORMAL); |
1da177e4 | 684 | } else { |
e7c98dc7 | 685 | for (i = 0; i < count; i++) { |
b12bb29f | 686 | char c = serial_port_in(port, SCxRDR); |
d97fbbed | 687 | |
b12bb29f | 688 | status = serial_port_in(port, SCxSR); |
1da177e4 LT |
689 | #if defined(CONFIG_CPU_SH3) |
690 | /* Skip "chars" during break */ | |
e108b2ca | 691 | if (sci_port->break_flag) { |
1da177e4 LT |
692 | if ((c == 0) && |
693 | (status & SCxSR_FER(port))) { | |
694 | count--; i--; | |
695 | continue; | |
696 | } | |
e108b2ca | 697 | |
1da177e4 | 698 | /* Nonzero => end-of-break */ |
762c69e3 | 699 | dev_dbg(port->dev, "debounce<%02x>\n", c); |
e108b2ca PM |
700 | sci_port->break_flag = 0; |
701 | ||
1da177e4 LT |
702 | if (STEPFN(c)) { |
703 | count--; i--; | |
704 | continue; | |
705 | } | |
706 | } | |
707 | #endif /* CONFIG_CPU_SH3 */ | |
7d12e780 | 708 | if (uart_handle_sysrq_char(port, c)) { |
1da177e4 LT |
709 | count--; i--; |
710 | continue; | |
711 | } | |
712 | ||
713 | /* Store data and status */ | |
73a19e4c | 714 | if (status & SCxSR_FER(port)) { |
33f0f88f | 715 | flag = TTY_FRAME; |
d97fbbed | 716 | port->icount.frame++; |
762c69e3 | 717 | dev_notice(port->dev, "frame error\n"); |
73a19e4c | 718 | } else if (status & SCxSR_PER(port)) { |
33f0f88f | 719 | flag = TTY_PARITY; |
d97fbbed | 720 | port->icount.parity++; |
762c69e3 | 721 | dev_notice(port->dev, "parity error\n"); |
33f0f88f AC |
722 | } else |
723 | flag = TTY_NORMAL; | |
762c69e3 | 724 | |
92a19f9c | 725 | tty_insert_flip_char(tport, c, flag); |
1da177e4 LT |
726 | } |
727 | } | |
728 | ||
b12bb29f PM |
729 | serial_port_in(port, SCxSR); /* dummy read */ |
730 | serial_port_out(port, SCxSR, SCxSR_RDxF_CLEAR(port)); | |
1da177e4 | 731 | |
1da177e4 LT |
732 | copied += count; |
733 | port->icount.rx += count; | |
734 | } | |
735 | ||
736 | if (copied) { | |
737 | /* Tell the rest of the system the news. New characters! */ | |
2e124b4a | 738 | tty_flip_buffer_push(tport); |
1da177e4 | 739 | } else { |
b12bb29f PM |
740 | serial_port_in(port, SCxSR); /* dummy read */ |
741 | serial_port_out(port, SCxSR, SCxSR_RDxF_CLEAR(port)); | |
1da177e4 LT |
742 | } |
743 | } | |
744 | ||
745 | #define SCI_BREAK_JIFFIES (HZ/20) | |
94c8b6db PM |
746 | |
747 | /* | |
748 | * The sci generates interrupts during the break, | |
1da177e4 LT |
749 | * 1 per millisecond or so during the break period, for 9600 baud. |
750 | * So dont bother disabling interrupts. | |
751 | * But dont want more than 1 break event. | |
752 | * Use a kernel timer to periodically poll the rx line until | |
753 | * the break is finished. | |
754 | */ | |
94c8b6db | 755 | static inline void sci_schedule_break_timer(struct sci_port *port) |
1da177e4 | 756 | { |
bc9b3f5c | 757 | mod_timer(&port->break_timer, jiffies + SCI_BREAK_JIFFIES); |
1da177e4 | 758 | } |
94c8b6db | 759 | |
1da177e4 LT |
760 | /* Ensure that two consecutive samples find the break over. */ |
761 | static void sci_break_timer(unsigned long data) | |
762 | { | |
e108b2ca PM |
763 | struct sci_port *port = (struct sci_port *)data; |
764 | ||
765 | if (sci_rxd_in(&port->port) == 0) { | |
1da177e4 | 766 | port->break_flag = 1; |
e108b2ca PM |
767 | sci_schedule_break_timer(port); |
768 | } else if (port->break_flag == 1) { | |
1da177e4 LT |
769 | /* break is over. */ |
770 | port->break_flag = 2; | |
e108b2ca PM |
771 | sci_schedule_break_timer(port); |
772 | } else | |
773 | port->break_flag = 0; | |
1da177e4 LT |
774 | } |
775 | ||
94c8b6db | 776 | static int sci_handle_errors(struct uart_port *port) |
1da177e4 LT |
777 | { |
778 | int copied = 0; | |
b12bb29f | 779 | unsigned short status = serial_port_in(port, SCxSR); |
92a19f9c | 780 | struct tty_port *tport = &port->state->port; |
debf9507 | 781 | struct sci_port *s = to_sci_port(port); |
1da177e4 | 782 | |
3ae988d9 LP |
783 | /* Handle overruns */ |
784 | if (status & (1 << s->overrun_bit)) { | |
785 | port->icount.overrun++; | |
d97fbbed | 786 | |
3ae988d9 LP |
787 | /* overrun error */ |
788 | if (tty_insert_flip_char(tport, 0, TTY_OVERRUN)) | |
789 | copied++; | |
762c69e3 | 790 | |
3ae988d9 | 791 | dev_notice(port->dev, "overrun error"); |
1da177e4 LT |
792 | } |
793 | ||
e108b2ca | 794 | if (status & SCxSR_FER(port)) { |
1da177e4 LT |
795 | if (sci_rxd_in(port) == 0) { |
796 | /* Notify of BREAK */ | |
e7c98dc7 | 797 | struct sci_port *sci_port = to_sci_port(port); |
e108b2ca PM |
798 | |
799 | if (!sci_port->break_flag) { | |
d97fbbed PM |
800 | port->icount.brk++; |
801 | ||
e108b2ca PM |
802 | sci_port->break_flag = 1; |
803 | sci_schedule_break_timer(sci_port); | |
804 | ||
1da177e4 | 805 | /* Do sysrq handling. */ |
e108b2ca | 806 | if (uart_handle_break(port)) |
1da177e4 | 807 | return 0; |
762c69e3 PM |
808 | |
809 | dev_dbg(port->dev, "BREAK detected\n"); | |
810 | ||
92a19f9c | 811 | if (tty_insert_flip_char(tport, 0, TTY_BREAK)) |
e7c98dc7 MT |
812 | copied++; |
813 | } | |
814 | ||
e108b2ca | 815 | } else { |
1da177e4 | 816 | /* frame error */ |
d97fbbed PM |
817 | port->icount.frame++; |
818 | ||
92a19f9c | 819 | if (tty_insert_flip_char(tport, 0, TTY_FRAME)) |
33f0f88f | 820 | copied++; |
762c69e3 PM |
821 | |
822 | dev_notice(port->dev, "frame error\n"); | |
1da177e4 LT |
823 | } |
824 | } | |
825 | ||
e108b2ca | 826 | if (status & SCxSR_PER(port)) { |
1da177e4 | 827 | /* parity error */ |
d97fbbed PM |
828 | port->icount.parity++; |
829 | ||
92a19f9c | 830 | if (tty_insert_flip_char(tport, 0, TTY_PARITY)) |
e108b2ca | 831 | copied++; |
762c69e3 PM |
832 | |
833 | dev_notice(port->dev, "parity error"); | |
1da177e4 LT |
834 | } |
835 | ||
33f0f88f | 836 | if (copied) |
2e124b4a | 837 | tty_flip_buffer_push(tport); |
1da177e4 LT |
838 | |
839 | return copied; | |
840 | } | |
841 | ||
94c8b6db | 842 | static int sci_handle_fifo_overrun(struct uart_port *port) |
d830fa45 | 843 | { |
92a19f9c | 844 | struct tty_port *tport = &port->state->port; |
debf9507 | 845 | struct sci_port *s = to_sci_port(port); |
4b8c59a3 | 846 | struct plat_sci_reg *reg; |
d830fa45 PM |
847 | int copied = 0; |
848 | ||
4b8c59a3 PM |
849 | reg = sci_getreg(port, SCLSR); |
850 | if (!reg->size) | |
d830fa45 PM |
851 | return 0; |
852 | ||
3ae988d9 | 853 | if ((serial_port_in(port, SCLSR) & (1 << s->overrun_bit))) { |
b12bb29f | 854 | serial_port_out(port, SCLSR, 0); |
d830fa45 | 855 | |
d97fbbed PM |
856 | port->icount.overrun++; |
857 | ||
92a19f9c | 858 | tty_insert_flip_char(tport, 0, TTY_OVERRUN); |
2e124b4a | 859 | tty_flip_buffer_push(tport); |
d830fa45 PM |
860 | |
861 | dev_notice(port->dev, "overrun error\n"); | |
862 | copied++; | |
863 | } | |
864 | ||
865 | return copied; | |
866 | } | |
867 | ||
94c8b6db | 868 | static int sci_handle_breaks(struct uart_port *port) |
1da177e4 LT |
869 | { |
870 | int copied = 0; | |
b12bb29f | 871 | unsigned short status = serial_port_in(port, SCxSR); |
92a19f9c | 872 | struct tty_port *tport = &port->state->port; |
a5660ada | 873 | struct sci_port *s = to_sci_port(port); |
1da177e4 | 874 | |
0b3d4ef6 PM |
875 | if (uart_handle_break(port)) |
876 | return 0; | |
877 | ||
b7a76e4b | 878 | if (!s->break_flag && status & SCxSR_BRK(port)) { |
1da177e4 LT |
879 | #if defined(CONFIG_CPU_SH3) |
880 | /* Debounce break */ | |
881 | s->break_flag = 1; | |
882 | #endif | |
d97fbbed PM |
883 | |
884 | port->icount.brk++; | |
885 | ||
1da177e4 | 886 | /* Notify of BREAK */ |
92a19f9c | 887 | if (tty_insert_flip_char(tport, 0, TTY_BREAK)) |
33f0f88f | 888 | copied++; |
762c69e3 PM |
889 | |
890 | dev_dbg(port->dev, "BREAK detected\n"); | |
1da177e4 LT |
891 | } |
892 | ||
33f0f88f | 893 | if (copied) |
2e124b4a | 894 | tty_flip_buffer_push(tport); |
e108b2ca | 895 | |
d830fa45 PM |
896 | copied += sci_handle_fifo_overrun(port); |
897 | ||
1da177e4 LT |
898 | return copied; |
899 | } | |
900 | ||
73a19e4c | 901 | static irqreturn_t sci_rx_interrupt(int irq, void *ptr) |
1da177e4 | 902 | { |
73a19e4c GL |
903 | #ifdef CONFIG_SERIAL_SH_SCI_DMA |
904 | struct uart_port *port = ptr; | |
905 | struct sci_port *s = to_sci_port(port); | |
906 | ||
907 | if (s->chan_rx) { | |
b12bb29f PM |
908 | u16 scr = serial_port_in(port, SCSCR); |
909 | u16 ssr = serial_port_in(port, SCxSR); | |
73a19e4c GL |
910 | |
911 | /* Disable future Rx interrupts */ | |
d1d4b10c | 912 | if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { |
3089f381 GL |
913 | disable_irq_nosync(irq); |
914 | scr |= 0x4000; | |
915 | } else { | |
f43dc23d | 916 | scr &= ~SCSCR_RIE; |
3089f381 | 917 | } |
b12bb29f | 918 | serial_port_out(port, SCSCR, scr); |
73a19e4c | 919 | /* Clear current interrupt */ |
b12bb29f | 920 | serial_port_out(port, SCxSR, ssr & ~(1 | SCxSR_RDxF(port))); |
3089f381 GL |
921 | dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u jiffies\n", |
922 | jiffies, s->rx_timeout); | |
923 | mod_timer(&s->rx_timer, jiffies + s->rx_timeout); | |
73a19e4c GL |
924 | |
925 | return IRQ_HANDLED; | |
926 | } | |
927 | #endif | |
928 | ||
1da177e4 LT |
929 | /* I think sci_receive_chars has to be called irrespective |
930 | * of whether the I_IXOFF is set, otherwise, how is the interrupt | |
931 | * to be disabled? | |
932 | */ | |
73a19e4c | 933 | sci_receive_chars(ptr); |
1da177e4 LT |
934 | |
935 | return IRQ_HANDLED; | |
936 | } | |
937 | ||
7d12e780 | 938 | static irqreturn_t sci_tx_interrupt(int irq, void *ptr) |
1da177e4 LT |
939 | { |
940 | struct uart_port *port = ptr; | |
fd78a76a | 941 | unsigned long flags; |
1da177e4 | 942 | |
fd78a76a | 943 | spin_lock_irqsave(&port->lock, flags); |
1da177e4 | 944 | sci_transmit_chars(port); |
fd78a76a | 945 | spin_unlock_irqrestore(&port->lock, flags); |
1da177e4 LT |
946 | |
947 | return IRQ_HANDLED; | |
948 | } | |
949 | ||
7d12e780 | 950 | static irqreturn_t sci_er_interrupt(int irq, void *ptr) |
1da177e4 LT |
951 | { |
952 | struct uart_port *port = ptr; | |
953 | ||
954 | /* Handle errors */ | |
955 | if (port->type == PORT_SCI) { | |
956 | if (sci_handle_errors(port)) { | |
957 | /* discard character in rx buffer */ | |
b12bb29f PM |
958 | serial_port_in(port, SCxSR); |
959 | serial_port_out(port, SCxSR, SCxSR_RDxF_CLEAR(port)); | |
1da177e4 LT |
960 | } |
961 | } else { | |
d830fa45 | 962 | sci_handle_fifo_overrun(port); |
7d12e780 | 963 | sci_rx_interrupt(irq, ptr); |
1da177e4 LT |
964 | } |
965 | ||
b12bb29f | 966 | serial_port_out(port, SCxSR, SCxSR_ERROR_CLEAR(port)); |
1da177e4 LT |
967 | |
968 | /* Kick the transmission */ | |
7d12e780 | 969 | sci_tx_interrupt(irq, ptr); |
1da177e4 LT |
970 | |
971 | return IRQ_HANDLED; | |
972 | } | |
973 | ||
7d12e780 | 974 | static irqreturn_t sci_br_interrupt(int irq, void *ptr) |
1da177e4 LT |
975 | { |
976 | struct uart_port *port = ptr; | |
977 | ||
978 | /* Handle BREAKs */ | |
979 | sci_handle_breaks(port); | |
b12bb29f | 980 | serial_port_out(port, SCxSR, SCxSR_BREAK_CLEAR(port)); |
1da177e4 LT |
981 | |
982 | return IRQ_HANDLED; | |
983 | } | |
984 | ||
f43dc23d PM |
985 | static inline unsigned long port_rx_irq_mask(struct uart_port *port) |
986 | { | |
987 | /* | |
988 | * Not all ports (such as SCIFA) will support REIE. Rather than | |
989 | * special-casing the port type, we check the port initialization | |
990 | * IRQ enable mask to see whether the IRQ is desired at all. If | |
991 | * it's unset, it's logically inferred that there's no point in | |
992 | * testing for it. | |
993 | */ | |
ce6738b6 | 994 | return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE); |
f43dc23d PM |
995 | } |
996 | ||
7d12e780 | 997 | static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr) |
1da177e4 | 998 | { |
44e18e9e | 999 | unsigned short ssr_status, scr_status, err_enabled; |
a8884e34 | 1000 | struct uart_port *port = ptr; |
73a19e4c | 1001 | struct sci_port *s = to_sci_port(port); |
a8884e34 | 1002 | irqreturn_t ret = IRQ_NONE; |
1da177e4 | 1003 | |
b12bb29f PM |
1004 | ssr_status = serial_port_in(port, SCxSR); |
1005 | scr_status = serial_port_in(port, SCSCR); | |
f43dc23d | 1006 | err_enabled = scr_status & port_rx_irq_mask(port); |
1da177e4 LT |
1007 | |
1008 | /* Tx Interrupt */ | |
f43dc23d | 1009 | if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) && |
73a19e4c | 1010 | !s->chan_tx) |
a8884e34 | 1011 | ret = sci_tx_interrupt(irq, ptr); |
f43dc23d | 1012 | |
73a19e4c GL |
1013 | /* |
1014 | * Rx Interrupt: if we're using DMA, the DMA controller clears RDF / | |
1015 | * DR flags | |
1016 | */ | |
1017 | if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) && | |
f43dc23d | 1018 | (scr_status & SCSCR_RIE)) |
a8884e34 | 1019 | ret = sci_rx_interrupt(irq, ptr); |
f43dc23d | 1020 | |
1da177e4 | 1021 | /* Error Interrupt */ |
dd4da3a5 | 1022 | if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled) |
a8884e34 | 1023 | ret = sci_er_interrupt(irq, ptr); |
f43dc23d | 1024 | |
1da177e4 | 1025 | /* Break Interrupt */ |
dd4da3a5 | 1026 | if ((ssr_status & SCxSR_BRK(port)) && err_enabled) |
a8884e34 | 1027 | ret = sci_br_interrupt(irq, ptr); |
1da177e4 | 1028 | |
a8884e34 | 1029 | return ret; |
1da177e4 LT |
1030 | } |
1031 | ||
1da177e4 | 1032 | /* |
25985edc | 1033 | * Here we define a transition notifier so that we can update all of our |
1da177e4 LT |
1034 | * ports' baud rate when the peripheral clock changes. |
1035 | */ | |
e108b2ca PM |
1036 | static int sci_notifier(struct notifier_block *self, |
1037 | unsigned long phase, void *p) | |
1da177e4 | 1038 | { |
e552de24 MD |
1039 | struct sci_port *sci_port; |
1040 | unsigned long flags; | |
1da177e4 | 1041 | |
d535a230 PM |
1042 | sci_port = container_of(self, struct sci_port, freq_transition); |
1043 | ||
1da177e4 | 1044 | if ((phase == CPUFREQ_POSTCHANGE) || |
e552de24 | 1045 | (phase == CPUFREQ_RESUMECHANGE)) { |
d535a230 | 1046 | struct uart_port *port = &sci_port->port; |
073e84c9 | 1047 | |
d535a230 PM |
1048 | spin_lock_irqsave(&port->lock, flags); |
1049 | port->uartclk = clk_get_rate(sci_port->iclk); | |
1050 | spin_unlock_irqrestore(&port->lock, flags); | |
e552de24 | 1051 | } |
1da177e4 | 1052 | |
1da177e4 LT |
1053 | return NOTIFY_OK; |
1054 | } | |
501b825d | 1055 | |
9174fc8f PM |
1056 | static struct sci_irq_desc { |
1057 | const char *desc; | |
1058 | irq_handler_t handler; | |
1059 | } sci_irq_desc[] = { | |
1060 | /* | |
1061 | * Split out handlers, the default case. | |
1062 | */ | |
1063 | [SCIx_ERI_IRQ] = { | |
1064 | .desc = "rx err", | |
1065 | .handler = sci_er_interrupt, | |
1066 | }, | |
1067 | ||
1068 | [SCIx_RXI_IRQ] = { | |
1069 | .desc = "rx full", | |
1070 | .handler = sci_rx_interrupt, | |
1071 | }, | |
1072 | ||
1073 | [SCIx_TXI_IRQ] = { | |
1074 | .desc = "tx empty", | |
1075 | .handler = sci_tx_interrupt, | |
1076 | }, | |
1077 | ||
1078 | [SCIx_BRI_IRQ] = { | |
1079 | .desc = "break", | |
1080 | .handler = sci_br_interrupt, | |
1081 | }, | |
1082 | ||
1083 | /* | |
1084 | * Special muxed handler. | |
1085 | */ | |
1086 | [SCIx_MUX_IRQ] = { | |
1087 | .desc = "mux", | |
1088 | .handler = sci_mpxed_interrupt, | |
1089 | }, | |
1090 | }; | |
1091 | ||
1da177e4 LT |
1092 | static int sci_request_irq(struct sci_port *port) |
1093 | { | |
9174fc8f PM |
1094 | struct uart_port *up = &port->port; |
1095 | int i, j, ret = 0; | |
1096 | ||
1097 | for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) { | |
1098 | struct sci_irq_desc *desc; | |
1fcc91a6 | 1099 | int irq; |
9174fc8f PM |
1100 | |
1101 | if (SCIx_IRQ_IS_MUXED(port)) { | |
1102 | i = SCIx_MUX_IRQ; | |
1103 | irq = up->irq; | |
0e8963de | 1104 | } else { |
1fcc91a6 | 1105 | irq = port->irqs[i]; |
9174fc8f | 1106 | |
0e8963de PM |
1107 | /* |
1108 | * Certain port types won't support all of the | |
1109 | * available interrupt sources. | |
1110 | */ | |
1fcc91a6 | 1111 | if (unlikely(irq < 0)) |
0e8963de PM |
1112 | continue; |
1113 | } | |
1114 | ||
9174fc8f PM |
1115 | desc = sci_irq_desc + i; |
1116 | port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s", | |
1117 | dev_name(up->dev), desc->desc); | |
1118 | if (!port->irqstr[j]) { | |
1119 | dev_err(up->dev, "Failed to allocate %s IRQ string\n", | |
1120 | desc->desc); | |
1121 | goto out_nomem; | |
1da177e4 | 1122 | } |
9174fc8f PM |
1123 | |
1124 | ret = request_irq(irq, desc->handler, up->irqflags, | |
1125 | port->irqstr[j], port); | |
1126 | if (unlikely(ret)) { | |
1127 | dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc); | |
1128 | goto out_noirq; | |
1da177e4 LT |
1129 | } |
1130 | } | |
1131 | ||
1132 | return 0; | |
9174fc8f PM |
1133 | |
1134 | out_noirq: | |
1135 | while (--i >= 0) | |
1fcc91a6 | 1136 | free_irq(port->irqs[i], port); |
9174fc8f PM |
1137 | |
1138 | out_nomem: | |
1139 | while (--j >= 0) | |
1140 | kfree(port->irqstr[j]); | |
1141 | ||
1142 | return ret; | |
1da177e4 LT |
1143 | } |
1144 | ||
1145 | static void sci_free_irq(struct sci_port *port) | |
1146 | { | |
1147 | int i; | |
1148 | ||
9174fc8f PM |
1149 | /* |
1150 | * Intentionally in reverse order so we iterate over the muxed | |
1151 | * IRQ first. | |
1152 | */ | |
1153 | for (i = 0; i < SCIx_NR_IRQS; i++) { | |
1fcc91a6 | 1154 | int irq = port->irqs[i]; |
0e8963de PM |
1155 | |
1156 | /* | |
1157 | * Certain port types won't support all of the available | |
1158 | * interrupt sources. | |
1159 | */ | |
1fcc91a6 | 1160 | if (unlikely(irq < 0)) |
0e8963de PM |
1161 | continue; |
1162 | ||
1fcc91a6 | 1163 | free_irq(port->irqs[i], port); |
9174fc8f | 1164 | kfree(port->irqstr[i]); |
1da177e4 | 1165 | |
9174fc8f PM |
1166 | if (SCIx_IRQ_IS_MUXED(port)) { |
1167 | /* If there's only one IRQ, we're done. */ | |
1168 | return; | |
1da177e4 LT |
1169 | } |
1170 | } | |
1171 | } | |
1172 | ||
1173 | static unsigned int sci_tx_empty(struct uart_port *port) | |
1174 | { | |
b12bb29f | 1175 | unsigned short status = serial_port_in(port, SCxSR); |
72b294cf | 1176 | unsigned short in_tx_fifo = sci_txfill(port); |
73a19e4c GL |
1177 | |
1178 | return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0; | |
1da177e4 LT |
1179 | } |
1180 | ||
cdf7c42f PM |
1181 | /* |
1182 | * Modem control is a bit of a mixed bag for SCI(F) ports. Generally | |
1183 | * CTS/RTS is supported in hardware by at least one port and controlled | |
1184 | * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently | |
1185 | * handled via the ->init_pins() op, which is a bit of a one-way street, | |
1186 | * lacking any ability to defer pin control -- this will later be | |
1187 | * converted over to the GPIO framework). | |
dc7e3ef7 PM |
1188 | * |
1189 | * Other modes (such as loopback) are supported generically on certain | |
1190 | * port types, but not others. For these it's sufficient to test for the | |
1191 | * existence of the support register and simply ignore the port type. | |
cdf7c42f | 1192 | */ |
1da177e4 LT |
1193 | static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl) |
1194 | { | |
dc7e3ef7 PM |
1195 | if (mctrl & TIOCM_LOOP) { |
1196 | struct plat_sci_reg *reg; | |
1197 | ||
1198 | /* | |
1199 | * Standard loopback mode for SCFCR ports. | |
1200 | */ | |
1201 | reg = sci_getreg(port, SCFCR); | |
1202 | if (reg->size) | |
b12bb29f | 1203 | serial_port_out(port, SCFCR, serial_port_in(port, SCFCR) | 1); |
dc7e3ef7 | 1204 | } |
1da177e4 LT |
1205 | } |
1206 | ||
1207 | static unsigned int sci_get_mctrl(struct uart_port *port) | |
1208 | { | |
cdf7c42f PM |
1209 | /* |
1210 | * CTS/RTS is handled in hardware when supported, while nothing | |
1211 | * else is wired up. Keep it simple and simply assert DSR/CAR. | |
1212 | */ | |
1213 | return TIOCM_DSR | TIOCM_CAR; | |
1da177e4 LT |
1214 | } |
1215 | ||
73a19e4c GL |
1216 | #ifdef CONFIG_SERIAL_SH_SCI_DMA |
1217 | static void sci_dma_tx_complete(void *arg) | |
1218 | { | |
1219 | struct sci_port *s = arg; | |
1220 | struct uart_port *port = &s->port; | |
1221 | struct circ_buf *xmit = &port->state->xmit; | |
1222 | unsigned long flags; | |
1223 | ||
1224 | dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); | |
1225 | ||
1226 | spin_lock_irqsave(&port->lock, flags); | |
1227 | ||
f354a381 | 1228 | xmit->tail += sg_dma_len(&s->sg_tx); |
73a19e4c GL |
1229 | xmit->tail &= UART_XMIT_SIZE - 1; |
1230 | ||
f354a381 | 1231 | port->icount.tx += sg_dma_len(&s->sg_tx); |
73a19e4c GL |
1232 | |
1233 | async_tx_ack(s->desc_tx); | |
73a19e4c GL |
1234 | s->desc_tx = NULL; |
1235 | ||
73a19e4c GL |
1236 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) |
1237 | uart_write_wakeup(port); | |
1238 | ||
3089f381 | 1239 | if (!uart_circ_empty(xmit)) { |
49d4bcad | 1240 | s->cookie_tx = 0; |
73a19e4c | 1241 | schedule_work(&s->work_tx); |
49d4bcad YT |
1242 | } else { |
1243 | s->cookie_tx = -EINVAL; | |
1244 | if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { | |
b12bb29f PM |
1245 | u16 ctrl = serial_port_in(port, SCSCR); |
1246 | serial_port_out(port, SCSCR, ctrl & ~SCSCR_TIE); | |
49d4bcad | 1247 | } |
3089f381 GL |
1248 | } |
1249 | ||
1250 | spin_unlock_irqrestore(&port->lock, flags); | |
73a19e4c GL |
1251 | } |
1252 | ||
1253 | /* Locking: called with port lock held */ | |
92a19f9c | 1254 | static int sci_dma_rx_push(struct sci_port *s, size_t count) |
73a19e4c GL |
1255 | { |
1256 | struct uart_port *port = &s->port; | |
227434f8 | 1257 | struct tty_port *tport = &port->state->port; |
73a19e4c GL |
1258 | int i, active, room; |
1259 | ||
227434f8 | 1260 | room = tty_buffer_request_room(tport, count); |
73a19e4c GL |
1261 | |
1262 | if (s->active_rx == s->cookie_rx[0]) { | |
1263 | active = 0; | |
1264 | } else if (s->active_rx == s->cookie_rx[1]) { | |
1265 | active = 1; | |
1266 | } else { | |
1267 | dev_err(port->dev, "cookie %d not found!\n", s->active_rx); | |
1268 | return 0; | |
1269 | } | |
1270 | ||
1271 | if (room < count) | |
e2afca69 | 1272 | dev_warn(port->dev, "Rx overrun: dropping %zu bytes\n", |
73a19e4c GL |
1273 | count - room); |
1274 | if (!room) | |
1275 | return room; | |
1276 | ||
1277 | for (i = 0; i < room; i++) | |
92a19f9c | 1278 | tty_insert_flip_char(tport, ((u8 *)sg_virt(&s->sg_rx[active]))[i], |
73a19e4c GL |
1279 | TTY_NORMAL); |
1280 | ||
1281 | port->icount.rx += room; | |
1282 | ||
1283 | return room; | |
1284 | } | |
1285 | ||
1286 | static void sci_dma_rx_complete(void *arg) | |
1287 | { | |
1288 | struct sci_port *s = arg; | |
1289 | struct uart_port *port = &s->port; | |
73a19e4c GL |
1290 | unsigned long flags; |
1291 | int count; | |
1292 | ||
3089f381 | 1293 | dev_dbg(port->dev, "%s(%d) active #%d\n", __func__, port->line, s->active_rx); |
73a19e4c GL |
1294 | |
1295 | spin_lock_irqsave(&port->lock, flags); | |
1296 | ||
92a19f9c | 1297 | count = sci_dma_rx_push(s, s->buf_len_rx); |
73a19e4c | 1298 | |
3089f381 | 1299 | mod_timer(&s->rx_timer, jiffies + s->rx_timeout); |
73a19e4c GL |
1300 | |
1301 | spin_unlock_irqrestore(&port->lock, flags); | |
1302 | ||
1303 | if (count) | |
2e124b4a | 1304 | tty_flip_buffer_push(&port->state->port); |
73a19e4c GL |
1305 | |
1306 | schedule_work(&s->work_rx); | |
1307 | } | |
1308 | ||
73a19e4c GL |
1309 | static void sci_rx_dma_release(struct sci_port *s, bool enable_pio) |
1310 | { | |
1311 | struct dma_chan *chan = s->chan_rx; | |
1312 | struct uart_port *port = &s->port; | |
73a19e4c GL |
1313 | |
1314 | s->chan_rx = NULL; | |
1315 | s->cookie_rx[0] = s->cookie_rx[1] = -EINVAL; | |
1316 | dma_release_channel(chan); | |
85b8e3ff GL |
1317 | if (sg_dma_address(&s->sg_rx[0])) |
1318 | dma_free_coherent(port->dev, s->buf_len_rx * 2, | |
1319 | sg_virt(&s->sg_rx[0]), sg_dma_address(&s->sg_rx[0])); | |
73a19e4c GL |
1320 | if (enable_pio) |
1321 | sci_start_rx(port); | |
1322 | } | |
1323 | ||
1324 | static void sci_tx_dma_release(struct sci_port *s, bool enable_pio) | |
1325 | { | |
1326 | struct dma_chan *chan = s->chan_tx; | |
1327 | struct uart_port *port = &s->port; | |
73a19e4c GL |
1328 | |
1329 | s->chan_tx = NULL; | |
1330 | s->cookie_tx = -EINVAL; | |
1331 | dma_release_channel(chan); | |
1332 | if (enable_pio) | |
1333 | sci_start_tx(port); | |
1334 | } | |
1335 | ||
1336 | static void sci_submit_rx(struct sci_port *s) | |
1337 | { | |
1338 | struct dma_chan *chan = s->chan_rx; | |
1339 | int i; | |
1340 | ||
1341 | for (i = 0; i < 2; i++) { | |
1342 | struct scatterlist *sg = &s->sg_rx[i]; | |
1343 | struct dma_async_tx_descriptor *desc; | |
1344 | ||
16052827 | 1345 | desc = dmaengine_prep_slave_sg(chan, |
a485df4b | 1346 | sg, 1, DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT); |
73a19e4c GL |
1347 | |
1348 | if (desc) { | |
1349 | s->desc_rx[i] = desc; | |
1350 | desc->callback = sci_dma_rx_complete; | |
1351 | desc->callback_param = s; | |
1352 | s->cookie_rx[i] = desc->tx_submit(desc); | |
1353 | } | |
1354 | ||
1355 | if (!desc || s->cookie_rx[i] < 0) { | |
1356 | if (i) { | |
1357 | async_tx_ack(s->desc_rx[0]); | |
1358 | s->cookie_rx[0] = -EINVAL; | |
1359 | } | |
1360 | if (desc) { | |
1361 | async_tx_ack(desc); | |
1362 | s->cookie_rx[i] = -EINVAL; | |
1363 | } | |
1364 | dev_warn(s->port.dev, | |
1365 | "failed to re-start DMA, using PIO\n"); | |
1366 | sci_rx_dma_release(s, true); | |
1367 | return; | |
1368 | } | |
3089f381 GL |
1369 | dev_dbg(s->port.dev, "%s(): cookie %d to #%d\n", __func__, |
1370 | s->cookie_rx[i], i); | |
73a19e4c GL |
1371 | } |
1372 | ||
1373 | s->active_rx = s->cookie_rx[0]; | |
1374 | ||
1375 | dma_async_issue_pending(chan); | |
1376 | } | |
1377 | ||
1378 | static void work_fn_rx(struct work_struct *work) | |
1379 | { | |
1380 | struct sci_port *s = container_of(work, struct sci_port, work_rx); | |
1381 | struct uart_port *port = &s->port; | |
1382 | struct dma_async_tx_descriptor *desc; | |
1383 | int new; | |
1384 | ||
1385 | if (s->active_rx == s->cookie_rx[0]) { | |
1386 | new = 0; | |
1387 | } else if (s->active_rx == s->cookie_rx[1]) { | |
1388 | new = 1; | |
1389 | } else { | |
1390 | dev_err(port->dev, "cookie %d not found!\n", s->active_rx); | |
1391 | return; | |
1392 | } | |
1393 | desc = s->desc_rx[new]; | |
1394 | ||
1395 | if (dma_async_is_tx_complete(s->chan_rx, s->active_rx, NULL, NULL) != | |
0b3d7d39 | 1396 | DMA_COMPLETE) { |
73a19e4c | 1397 | /* Handle incomplete DMA receive */ |
73a19e4c | 1398 | struct dma_chan *chan = s->chan_rx; |
4dc4c516 GL |
1399 | struct shdma_desc *sh_desc = container_of(desc, |
1400 | struct shdma_desc, async_tx); | |
73a19e4c GL |
1401 | unsigned long flags; |
1402 | int count; | |
1403 | ||
05827630 | 1404 | chan->device->device_control(chan, DMA_TERMINATE_ALL, 0); |
e2afca69 | 1405 | dev_dbg(port->dev, "Read %zu bytes with cookie %d\n", |
73a19e4c GL |
1406 | sh_desc->partial, sh_desc->cookie); |
1407 | ||
1408 | spin_lock_irqsave(&port->lock, flags); | |
92a19f9c | 1409 | count = sci_dma_rx_push(s, sh_desc->partial); |
73a19e4c GL |
1410 | spin_unlock_irqrestore(&port->lock, flags); |
1411 | ||
1412 | if (count) | |
2e124b4a | 1413 | tty_flip_buffer_push(&port->state->port); |
73a19e4c GL |
1414 | |
1415 | sci_submit_rx(s); | |
1416 | ||
1417 | return; | |
1418 | } | |
1419 | ||
1420 | s->cookie_rx[new] = desc->tx_submit(desc); | |
1421 | if (s->cookie_rx[new] < 0) { | |
1422 | dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n"); | |
1423 | sci_rx_dma_release(s, true); | |
1424 | return; | |
1425 | } | |
1426 | ||
73a19e4c | 1427 | s->active_rx = s->cookie_rx[!new]; |
3089f381 GL |
1428 | |
1429 | dev_dbg(port->dev, "%s: cookie %d #%d, new active #%d\n", __func__, | |
1430 | s->cookie_rx[new], new, s->active_rx); | |
73a19e4c GL |
1431 | } |
1432 | ||
1433 | static void work_fn_tx(struct work_struct *work) | |
1434 | { | |
1435 | struct sci_port *s = container_of(work, struct sci_port, work_tx); | |
1436 | struct dma_async_tx_descriptor *desc; | |
1437 | struct dma_chan *chan = s->chan_tx; | |
1438 | struct uart_port *port = &s->port; | |
1439 | struct circ_buf *xmit = &port->state->xmit; | |
1440 | struct scatterlist *sg = &s->sg_tx; | |
1441 | ||
1442 | /* | |
1443 | * DMA is idle now. | |
1444 | * Port xmit buffer is already mapped, and it is one page... Just adjust | |
1445 | * offsets and lengths. Since it is a circular buffer, we have to | |
1446 | * transmit till the end, and then the rest. Take the port lock to get a | |
1447 | * consistent xmit buffer state. | |
1448 | */ | |
1449 | spin_lock_irq(&port->lock); | |
1450 | sg->offset = xmit->tail & (UART_XMIT_SIZE - 1); | |
f354a381 | 1451 | sg_dma_address(sg) = (sg_dma_address(sg) & ~(UART_XMIT_SIZE - 1)) + |
73a19e4c | 1452 | sg->offset; |
f354a381 | 1453 | sg_dma_len(sg) = min((int)CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE), |
73a19e4c | 1454 | CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE)); |
73a19e4c GL |
1455 | spin_unlock_irq(&port->lock); |
1456 | ||
f354a381 | 1457 | BUG_ON(!sg_dma_len(sg)); |
73a19e4c | 1458 | |
16052827 | 1459 | desc = dmaengine_prep_slave_sg(chan, |
a485df4b | 1460 | sg, s->sg_len_tx, DMA_MEM_TO_DEV, |
73a19e4c GL |
1461 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
1462 | if (!desc) { | |
1463 | /* switch to PIO */ | |
1464 | sci_tx_dma_release(s, true); | |
1465 | return; | |
1466 | } | |
1467 | ||
1468 | dma_sync_sg_for_device(port->dev, sg, 1, DMA_TO_DEVICE); | |
1469 | ||
1470 | spin_lock_irq(&port->lock); | |
1471 | s->desc_tx = desc; | |
1472 | desc->callback = sci_dma_tx_complete; | |
1473 | desc->callback_param = s; | |
1474 | spin_unlock_irq(&port->lock); | |
1475 | s->cookie_tx = desc->tx_submit(desc); | |
1476 | if (s->cookie_tx < 0) { | |
1477 | dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n"); | |
1478 | /* switch to PIO */ | |
1479 | sci_tx_dma_release(s, true); | |
1480 | return; | |
1481 | } | |
1482 | ||
1483 | dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n", __func__, | |
1484 | xmit->buf, xmit->tail, xmit->head, s->cookie_tx); | |
1485 | ||
1486 | dma_async_issue_pending(chan); | |
1487 | } | |
1488 | #endif | |
1489 | ||
b129a8cc | 1490 | static void sci_start_tx(struct uart_port *port) |
1da177e4 | 1491 | { |
3089f381 | 1492 | struct sci_port *s = to_sci_port(port); |
e108b2ca | 1493 | unsigned short ctrl; |
1da177e4 | 1494 | |
73a19e4c | 1495 | #ifdef CONFIG_SERIAL_SH_SCI_DMA |
d1d4b10c | 1496 | if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { |
b12bb29f | 1497 | u16 new, scr = serial_port_in(port, SCSCR); |
3089f381 GL |
1498 | if (s->chan_tx) |
1499 | new = scr | 0x8000; | |
1500 | else | |
1501 | new = scr & ~0x8000; | |
1502 | if (new != scr) | |
b12bb29f | 1503 | serial_port_out(port, SCSCR, new); |
73a19e4c | 1504 | } |
f43dc23d | 1505 | |
3089f381 | 1506 | if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) && |
49d4bcad YT |
1507 | s->cookie_tx < 0) { |
1508 | s->cookie_tx = 0; | |
3089f381 | 1509 | schedule_work(&s->work_tx); |
49d4bcad | 1510 | } |
73a19e4c | 1511 | #endif |
f43dc23d | 1512 | |
d1d4b10c | 1513 | if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) { |
3089f381 | 1514 | /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */ |
b12bb29f PM |
1515 | ctrl = serial_port_in(port, SCSCR); |
1516 | serial_port_out(port, SCSCR, ctrl | SCSCR_TIE); | |
3089f381 | 1517 | } |
1da177e4 LT |
1518 | } |
1519 | ||
b129a8cc | 1520 | static void sci_stop_tx(struct uart_port *port) |
1da177e4 | 1521 | { |
1da177e4 LT |
1522 | unsigned short ctrl; |
1523 | ||
1524 | /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */ | |
b12bb29f | 1525 | ctrl = serial_port_in(port, SCSCR); |
f43dc23d | 1526 | |
d1d4b10c | 1527 | if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) |
3089f381 | 1528 | ctrl &= ~0x8000; |
f43dc23d | 1529 | |
8e698614 | 1530 | ctrl &= ~SCSCR_TIE; |
f43dc23d | 1531 | |
b12bb29f | 1532 | serial_port_out(port, SCSCR, ctrl); |
1da177e4 LT |
1533 | } |
1534 | ||
73a19e4c | 1535 | static void sci_start_rx(struct uart_port *port) |
1da177e4 | 1536 | { |
1da177e4 LT |
1537 | unsigned short ctrl; |
1538 | ||
b12bb29f | 1539 | ctrl = serial_port_in(port, SCSCR) | port_rx_irq_mask(port); |
1da177e4 | 1540 | |
d1d4b10c | 1541 | if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) |
3089f381 | 1542 | ctrl &= ~0x4000; |
f43dc23d | 1543 | |
b12bb29f | 1544 | serial_port_out(port, SCSCR, ctrl); |
1da177e4 LT |
1545 | } |
1546 | ||
1547 | static void sci_stop_rx(struct uart_port *port) | |
1548 | { | |
1da177e4 LT |
1549 | unsigned short ctrl; |
1550 | ||
b12bb29f | 1551 | ctrl = serial_port_in(port, SCSCR); |
f43dc23d | 1552 | |
d1d4b10c | 1553 | if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) |
3089f381 | 1554 | ctrl &= ~0x4000; |
f43dc23d PM |
1555 | |
1556 | ctrl &= ~port_rx_irq_mask(port); | |
1557 | ||
b12bb29f | 1558 | serial_port_out(port, SCSCR, ctrl); |
1da177e4 LT |
1559 | } |
1560 | ||
1561 | static void sci_enable_ms(struct uart_port *port) | |
1562 | { | |
d39ec6ce PM |
1563 | /* |
1564 | * Not supported by hardware, always a nop. | |
1565 | */ | |
1da177e4 LT |
1566 | } |
1567 | ||
1568 | static void sci_break_ctl(struct uart_port *port, int break_state) | |
1569 | { | |
bbb4ce50 | 1570 | struct sci_port *s = to_sci_port(port); |
a4e02f6d | 1571 | struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR; |
bbb4ce50 SY |
1572 | unsigned short scscr, scsptr; |
1573 | ||
a4e02f6d SY |
1574 | /* check wheter the port has SCSPTR */ |
1575 | if (!reg->size) { | |
bbb4ce50 SY |
1576 | /* |
1577 | * Not supported by hardware. Most parts couple break and rx | |
1578 | * interrupts together, with break detection always enabled. | |
1579 | */ | |
a4e02f6d | 1580 | return; |
bbb4ce50 | 1581 | } |
a4e02f6d SY |
1582 | |
1583 | scsptr = serial_port_in(port, SCSPTR); | |
1584 | scscr = serial_port_in(port, SCSCR); | |
1585 | ||
1586 | if (break_state == -1) { | |
1587 | scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT; | |
1588 | scscr &= ~SCSCR_TE; | |
1589 | } else { | |
1590 | scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO; | |
1591 | scscr |= SCSCR_TE; | |
1592 | } | |
1593 | ||
1594 | serial_port_out(port, SCSPTR, scsptr); | |
1595 | serial_port_out(port, SCSCR, scscr); | |
1da177e4 LT |
1596 | } |
1597 | ||
73a19e4c GL |
1598 | #ifdef CONFIG_SERIAL_SH_SCI_DMA |
1599 | static bool filter(struct dma_chan *chan, void *slave) | |
1600 | { | |
1601 | struct sh_dmae_slave *param = slave; | |
1602 | ||
1603 | dev_dbg(chan->device->dev, "%s: slave ID %d\n", __func__, | |
d6fa5a4e | 1604 | param->shdma_slave.slave_id); |
73a19e4c | 1605 | |
d6fa5a4e | 1606 | chan->private = ¶m->shdma_slave; |
937bb6e4 | 1607 | return true; |
73a19e4c GL |
1608 | } |
1609 | ||
1610 | static void rx_timer_fn(unsigned long arg) | |
1611 | { | |
1612 | struct sci_port *s = (struct sci_port *)arg; | |
1613 | struct uart_port *port = &s->port; | |
b12bb29f | 1614 | u16 scr = serial_port_in(port, SCSCR); |
3089f381 | 1615 | |
d1d4b10c | 1616 | if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { |
3089f381 | 1617 | scr &= ~0x4000; |
1fcc91a6 | 1618 | enable_irq(s->irqs[SCIx_RXI_IRQ]); |
3089f381 | 1619 | } |
b12bb29f | 1620 | serial_port_out(port, SCSCR, scr | SCSCR_RIE); |
73a19e4c GL |
1621 | dev_dbg(port->dev, "DMA Rx timed out\n"); |
1622 | schedule_work(&s->work_rx); | |
1623 | } | |
1624 | ||
1625 | static void sci_request_dma(struct uart_port *port) | |
1626 | { | |
1627 | struct sci_port *s = to_sci_port(port); | |
1628 | struct sh_dmae_slave *param; | |
1629 | struct dma_chan *chan; | |
1630 | dma_cap_mask_t mask; | |
1631 | int nent; | |
1632 | ||
937bb6e4 GL |
1633 | dev_dbg(port->dev, "%s: port %d\n", __func__, |
1634 | port->line); | |
73a19e4c | 1635 | |
937bb6e4 | 1636 | if (s->cfg->dma_slave_tx <= 0 || s->cfg->dma_slave_rx <= 0) |
73a19e4c GL |
1637 | return; |
1638 | ||
1639 | dma_cap_zero(mask); | |
1640 | dma_cap_set(DMA_SLAVE, mask); | |
1641 | ||
1642 | param = &s->param_tx; | |
1643 | ||
1644 | /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_TX */ | |
d6fa5a4e | 1645 | param->shdma_slave.slave_id = s->cfg->dma_slave_tx; |
73a19e4c GL |
1646 | |
1647 | s->cookie_tx = -EINVAL; | |
1648 | chan = dma_request_channel(mask, filter, param); | |
1649 | dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan); | |
1650 | if (chan) { | |
1651 | s->chan_tx = chan; | |
1652 | sg_init_table(&s->sg_tx, 1); | |
1653 | /* UART circular tx buffer is an aligned page. */ | |
e2afca69 | 1654 | BUG_ON((uintptr_t)port->state->xmit.buf & ~PAGE_MASK); |
73a19e4c | 1655 | sg_set_page(&s->sg_tx, virt_to_page(port->state->xmit.buf), |
e2afca69 LP |
1656 | UART_XMIT_SIZE, |
1657 | (uintptr_t)port->state->xmit.buf & ~PAGE_MASK); | |
73a19e4c GL |
1658 | nent = dma_map_sg(port->dev, &s->sg_tx, 1, DMA_TO_DEVICE); |
1659 | if (!nent) | |
1660 | sci_tx_dma_release(s, false); | |
1661 | else | |
e2afca69 LP |
1662 | dev_dbg(port->dev, "%s: mapped %d@%p to %pad\n", __func__, |
1663 | sg_dma_len(&s->sg_tx), port->state->xmit.buf, | |
1664 | &sg_dma_address(&s->sg_tx)); | |
73a19e4c GL |
1665 | |
1666 | s->sg_len_tx = nent; | |
1667 | ||
1668 | INIT_WORK(&s->work_tx, work_fn_tx); | |
1669 | } | |
1670 | ||
1671 | param = &s->param_rx; | |
1672 | ||
1673 | /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_RX */ | |
d6fa5a4e | 1674 | param->shdma_slave.slave_id = s->cfg->dma_slave_rx; |
73a19e4c GL |
1675 | |
1676 | chan = dma_request_channel(mask, filter, param); | |
1677 | dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan); | |
1678 | if (chan) { | |
1679 | dma_addr_t dma[2]; | |
1680 | void *buf[2]; | |
1681 | int i; | |
1682 | ||
1683 | s->chan_rx = chan; | |
1684 | ||
1685 | s->buf_len_rx = 2 * max(16, (int)port->fifosize); | |
1686 | buf[0] = dma_alloc_coherent(port->dev, s->buf_len_rx * 2, | |
1687 | &dma[0], GFP_KERNEL); | |
1688 | ||
1689 | if (!buf[0]) { | |
1690 | dev_warn(port->dev, | |
1691 | "failed to allocate dma buffer, using PIO\n"); | |
1692 | sci_rx_dma_release(s, true); | |
1693 | return; | |
1694 | } | |
1695 | ||
1696 | buf[1] = buf[0] + s->buf_len_rx; | |
1697 | dma[1] = dma[0] + s->buf_len_rx; | |
1698 | ||
1699 | for (i = 0; i < 2; i++) { | |
1700 | struct scatterlist *sg = &s->sg_rx[i]; | |
1701 | ||
1702 | sg_init_table(sg, 1); | |
1703 | sg_set_page(sg, virt_to_page(buf[i]), s->buf_len_rx, | |
e2afca69 | 1704 | (uintptr_t)buf[i] & ~PAGE_MASK); |
f354a381 | 1705 | sg_dma_address(sg) = dma[i]; |
73a19e4c GL |
1706 | } |
1707 | ||
1708 | INIT_WORK(&s->work_rx, work_fn_rx); | |
1709 | setup_timer(&s->rx_timer, rx_timer_fn, (unsigned long)s); | |
1710 | ||
1711 | sci_submit_rx(s); | |
1712 | } | |
1713 | } | |
1714 | ||
1715 | static void sci_free_dma(struct uart_port *port) | |
1716 | { | |
1717 | struct sci_port *s = to_sci_port(port); | |
1718 | ||
73a19e4c GL |
1719 | if (s->chan_tx) |
1720 | sci_tx_dma_release(s, false); | |
1721 | if (s->chan_rx) | |
1722 | sci_rx_dma_release(s, false); | |
1723 | } | |
27bd1075 PM |
1724 | #else |
1725 | static inline void sci_request_dma(struct uart_port *port) | |
1726 | { | |
1727 | } | |
1728 | ||
1729 | static inline void sci_free_dma(struct uart_port *port) | |
1730 | { | |
1731 | } | |
73a19e4c GL |
1732 | #endif |
1733 | ||
1da177e4 LT |
1734 | static int sci_startup(struct uart_port *port) |
1735 | { | |
a5660ada | 1736 | struct sci_port *s = to_sci_port(port); |
33b48e16 | 1737 | unsigned long flags; |
073e84c9 | 1738 | int ret; |
1da177e4 | 1739 | |
73a19e4c GL |
1740 | dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); |
1741 | ||
073e84c9 PM |
1742 | ret = sci_request_irq(s); |
1743 | if (unlikely(ret < 0)) | |
1744 | return ret; | |
1745 | ||
73a19e4c | 1746 | sci_request_dma(port); |
073e84c9 | 1747 | |
33b48e16 | 1748 | spin_lock_irqsave(&port->lock, flags); |
d656901b | 1749 | sci_start_tx(port); |
73a19e4c | 1750 | sci_start_rx(port); |
33b48e16 | 1751 | spin_unlock_irqrestore(&port->lock, flags); |
1da177e4 LT |
1752 | |
1753 | return 0; | |
1754 | } | |
1755 | ||
1756 | static void sci_shutdown(struct uart_port *port) | |
1757 | { | |
a5660ada | 1758 | struct sci_port *s = to_sci_port(port); |
33b48e16 | 1759 | unsigned long flags; |
1da177e4 | 1760 | |
73a19e4c GL |
1761 | dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); |
1762 | ||
33b48e16 | 1763 | spin_lock_irqsave(&port->lock, flags); |
1da177e4 | 1764 | sci_stop_rx(port); |
b129a8cc | 1765 | sci_stop_tx(port); |
33b48e16 | 1766 | spin_unlock_irqrestore(&port->lock, flags); |
073e84c9 | 1767 | |
73a19e4c | 1768 | sci_free_dma(port); |
1da177e4 | 1769 | sci_free_irq(s); |
1da177e4 LT |
1770 | } |
1771 | ||
ec09c5eb | 1772 | static unsigned int sci_scbrr_calc(struct sci_port *s, unsigned int bps, |
26c92f37 PM |
1773 | unsigned long freq) |
1774 | { | |
ec09c5eb LP |
1775 | if (s->sampling_rate) |
1776 | return DIV_ROUND_CLOSEST(freq, s->sampling_rate * bps) - 1; | |
1777 | ||
26c92f37 PM |
1778 | /* Warn, but use a safe default */ |
1779 | WARN_ON(1); | |
e8183a6c | 1780 | |
26c92f37 PM |
1781 | return ((freq + 16 * bps) / (32 * bps) - 1); |
1782 | } | |
1783 | ||
f303b364 UH |
1784 | /* calculate sample rate, BRR, and clock select for HSCIF */ |
1785 | static void sci_baud_calc_hscif(unsigned int bps, unsigned long freq, | |
1786 | int *brr, unsigned int *srr, | |
1787 | unsigned int *cks) | |
1788 | { | |
1789 | int sr, c, br, err; | |
1790 | int min_err = 1000; /* 100% */ | |
1791 | ||
1792 | /* Find the combination of sample rate and clock select with the | |
1793 | smallest deviation from the desired baud rate. */ | |
1794 | for (sr = 8; sr <= 32; sr++) { | |
1795 | for (c = 0; c <= 3; c++) { | |
1796 | /* integerized formulas from HSCIF documentation */ | |
1797 | br = freq / (sr * (1 << (2 * c + 1)) * bps) - 1; | |
1798 | if (br < 0 || br > 255) | |
1799 | continue; | |
1800 | err = freq / ((br + 1) * bps * sr * | |
1801 | (1 << (2 * c + 1)) / 1000) - 1000; | |
1802 | if (min_err > err) { | |
1803 | min_err = err; | |
1804 | *brr = br; | |
1805 | *srr = sr - 1; | |
1806 | *cks = c; | |
1807 | } | |
1808 | } | |
1809 | } | |
1810 | ||
1811 | if (min_err == 1000) { | |
1812 | WARN_ON(1); | |
1813 | /* use defaults */ | |
1814 | *brr = 255; | |
1815 | *srr = 15; | |
1816 | *cks = 0; | |
1817 | } | |
1818 | } | |
1819 | ||
1ba76220 MD |
1820 | static void sci_reset(struct uart_port *port) |
1821 | { | |
0979e0e6 | 1822 | struct plat_sci_reg *reg; |
1ba76220 MD |
1823 | unsigned int status; |
1824 | ||
1825 | do { | |
b12bb29f | 1826 | status = serial_port_in(port, SCxSR); |
1ba76220 MD |
1827 | } while (!(status & SCxSR_TEND(port))); |
1828 | ||
b12bb29f | 1829 | serial_port_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */ |
1ba76220 | 1830 | |
0979e0e6 PM |
1831 | reg = sci_getreg(port, SCFCR); |
1832 | if (reg->size) | |
b12bb29f | 1833 | serial_port_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST); |
1ba76220 MD |
1834 | } |
1835 | ||
606d099c AC |
1836 | static void sci_set_termios(struct uart_port *port, struct ktermios *termios, |
1837 | struct ktermios *old) | |
1da177e4 | 1838 | { |
00b9de9c | 1839 | struct sci_port *s = to_sci_port(port); |
0979e0e6 | 1840 | struct plat_sci_reg *reg; |
d4759ded | 1841 | unsigned int baud, smr_val, max_baud, cks = 0; |
a2159b52 | 1842 | int t = -1; |
d4759ded | 1843 | unsigned int srr = 15; |
1da177e4 | 1844 | |
154280fd MD |
1845 | /* |
1846 | * earlyprintk comes here early on with port->uartclk set to zero. | |
1847 | * the clock framework is not up and running at this point so here | |
1848 | * we assume that 115200 is the maximum baud rate. please note that | |
1849 | * the baud rate is not programmed during earlyprintk - it is assumed | |
1850 | * that the previous boot loader has enabled required clocks and | |
1851 | * setup the baud rate generator hardware for us already. | |
1852 | */ | |
1853 | max_baud = port->uartclk ? port->uartclk / 16 : 115200; | |
1da177e4 | 1854 | |
154280fd | 1855 | baud = uart_get_baud_rate(port, termios, old, 0, max_baud); |
f303b364 | 1856 | if (likely(baud && port->uartclk)) { |
ec09c5eb | 1857 | if (s->cfg->type == PORT_HSCIF) { |
f303b364 UH |
1858 | sci_baud_calc_hscif(baud, port->uartclk, &t, &srr, |
1859 | &cks); | |
1860 | } else { | |
ec09c5eb | 1861 | t = sci_scbrr_calc(s, baud, port->uartclk); |
f303b364 UH |
1862 | for (cks = 0; t >= 256 && cks <= 3; cks++) |
1863 | t >>= 2; | |
1864 | } | |
1865 | } | |
e108b2ca | 1866 | |
23241d43 | 1867 | sci_port_enable(s); |
36003386 | 1868 | |
1ba76220 | 1869 | sci_reset(port); |
1da177e4 | 1870 | |
b12bb29f | 1871 | smr_val = serial_port_in(port, SCSMR) & 3; |
e8183a6c | 1872 | |
1da177e4 LT |
1873 | if ((termios->c_cflag & CSIZE) == CS7) |
1874 | smr_val |= 0x40; | |
1875 | if (termios->c_cflag & PARENB) | |
1876 | smr_val |= 0x20; | |
1877 | if (termios->c_cflag & PARODD) | |
1878 | smr_val |= 0x30; | |
1879 | if (termios->c_cflag & CSTOPB) | |
1880 | smr_val |= 0x08; | |
1881 | ||
1882 | uart_update_timeout(port, termios->c_cflag, baud); | |
1883 | ||
9d482cc3 TY |
1884 | dev_dbg(port->dev, "%s: SMR %x, cks %x, t %x, SCSCR %x\n", |
1885 | __func__, smr_val, cks, t, s->cfg->scscr); | |
73a19e4c | 1886 | |
4ffc3cdb | 1887 | if (t >= 0) { |
9d482cc3 | 1888 | serial_port_out(port, SCSMR, (smr_val & ~3) | cks); |
b12bb29f | 1889 | serial_port_out(port, SCBRR, t); |
f303b364 UH |
1890 | reg = sci_getreg(port, HSSRR); |
1891 | if (reg->size) | |
1892 | serial_port_out(port, HSSRR, srr | HSCIF_SRE); | |
1da177e4 | 1893 | udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */ |
9d482cc3 TY |
1894 | } else |
1895 | serial_port_out(port, SCSMR, smr_val); | |
1da177e4 | 1896 | |
d5701647 | 1897 | sci_init_pins(port, termios->c_cflag); |
0979e0e6 | 1898 | |
73c3d53f PM |
1899 | reg = sci_getreg(port, SCFCR); |
1900 | if (reg->size) { | |
b12bb29f | 1901 | unsigned short ctrl = serial_port_in(port, SCFCR); |
0979e0e6 | 1902 | |
73c3d53f | 1903 | if (s->cfg->capabilities & SCIx_HAVE_RTSCTS) { |
faf02f8f PM |
1904 | if (termios->c_cflag & CRTSCTS) |
1905 | ctrl |= SCFCR_MCE; | |
1906 | else | |
1907 | ctrl &= ~SCFCR_MCE; | |
faf02f8f | 1908 | } |
73c3d53f PM |
1909 | |
1910 | /* | |
1911 | * As we've done a sci_reset() above, ensure we don't | |
1912 | * interfere with the FIFOs while toggling MCE. As the | |
1913 | * reset values could still be set, simply mask them out. | |
1914 | */ | |
1915 | ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST); | |
1916 | ||
b12bb29f | 1917 | serial_port_out(port, SCFCR, ctrl); |
0979e0e6 | 1918 | } |
b7a76e4b | 1919 | |
b12bb29f | 1920 | serial_port_out(port, SCSCR, s->cfg->scscr); |
1da177e4 | 1921 | |
3089f381 GL |
1922 | #ifdef CONFIG_SERIAL_SH_SCI_DMA |
1923 | /* | |
1924 | * Calculate delay for 1.5 DMA buffers: see | |
1925 | * drivers/serial/serial_core.c::uart_update_timeout(). With 10 bits | |
1926 | * (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above function | |
1927 | * calculates 1 jiffie for the data plus 5 jiffies for the "slop(e)." | |
1928 | * Then below we calculate 3 jiffies (12ms) for 1.5 DMA buffers (3 FIFO | |
1929 | * sizes), but it has been found out experimentally, that this is not | |
1930 | * enough: the driver too often needlessly runs on a DMA timeout. 20ms | |
1931 | * as a minimum seem to work perfectly. | |
1932 | */ | |
1933 | if (s->chan_rx) { | |
1934 | s->rx_timeout = (port->timeout - HZ / 50) * s->buf_len_rx * 3 / | |
1935 | port->fifosize / 2; | |
1936 | dev_dbg(port->dev, | |
1937 | "DMA Rx t-out %ums, tty t-out %u jiffies\n", | |
1938 | s->rx_timeout * 1000 / HZ, port->timeout); | |
1939 | if (s->rx_timeout < msecs_to_jiffies(20)) | |
1940 | s->rx_timeout = msecs_to_jiffies(20); | |
1941 | } | |
1942 | #endif | |
1943 | ||
1da177e4 | 1944 | if ((termios->c_cflag & CREAD) != 0) |
73a19e4c | 1945 | sci_start_rx(port); |
36003386 | 1946 | |
23241d43 | 1947 | sci_port_disable(s); |
1da177e4 LT |
1948 | } |
1949 | ||
0174e5ca TK |
1950 | static void sci_pm(struct uart_port *port, unsigned int state, |
1951 | unsigned int oldstate) | |
1952 | { | |
1953 | struct sci_port *sci_port = to_sci_port(port); | |
1954 | ||
1955 | switch (state) { | |
1956 | case 3: | |
1957 | sci_port_disable(sci_port); | |
1958 | break; | |
1959 | default: | |
1960 | sci_port_enable(sci_port); | |
1961 | break; | |
1962 | } | |
1963 | } | |
1964 | ||
1da177e4 LT |
1965 | static const char *sci_type(struct uart_port *port) |
1966 | { | |
1967 | switch (port->type) { | |
e7c98dc7 MT |
1968 | case PORT_IRDA: |
1969 | return "irda"; | |
1970 | case PORT_SCI: | |
1971 | return "sci"; | |
1972 | case PORT_SCIF: | |
1973 | return "scif"; | |
1974 | case PORT_SCIFA: | |
1975 | return "scifa"; | |
d1d4b10c GL |
1976 | case PORT_SCIFB: |
1977 | return "scifb"; | |
f303b364 UH |
1978 | case PORT_HSCIF: |
1979 | return "hscif"; | |
1da177e4 LT |
1980 | } |
1981 | ||
fa43972f | 1982 | return NULL; |
1da177e4 LT |
1983 | } |
1984 | ||
e2651647 | 1985 | static inline unsigned long sci_port_size(struct uart_port *port) |
1da177e4 | 1986 | { |
e2651647 PM |
1987 | /* |
1988 | * Pick an arbitrary size that encapsulates all of the base | |
1989 | * registers by default. This can be optimized later, or derived | |
1990 | * from platform resource data at such a time that ports begin to | |
1991 | * behave more erratically. | |
1992 | */ | |
f303b364 UH |
1993 | if (port->type == PORT_HSCIF) |
1994 | return 96; | |
1995 | else | |
1996 | return 64; | |
1da177e4 LT |
1997 | } |
1998 | ||
f6e9495d PM |
1999 | static int sci_remap_port(struct uart_port *port) |
2000 | { | |
2001 | unsigned long size = sci_port_size(port); | |
2002 | ||
2003 | /* | |
2004 | * Nothing to do if there's already an established membase. | |
2005 | */ | |
2006 | if (port->membase) | |
2007 | return 0; | |
2008 | ||
2009 | if (port->flags & UPF_IOREMAP) { | |
2010 | port->membase = ioremap_nocache(port->mapbase, size); | |
2011 | if (unlikely(!port->membase)) { | |
2012 | dev_err(port->dev, "can't remap port#%d\n", port->line); | |
2013 | return -ENXIO; | |
2014 | } | |
2015 | } else { | |
2016 | /* | |
2017 | * For the simple (and majority of) cases where we don't | |
2018 | * need to do any remapping, just cast the cookie | |
2019 | * directly. | |
2020 | */ | |
3af4e960 | 2021 | port->membase = (void __iomem *)(uintptr_t)port->mapbase; |
f6e9495d PM |
2022 | } |
2023 | ||
2024 | return 0; | |
2025 | } | |
2026 | ||
e2651647 | 2027 | static void sci_release_port(struct uart_port *port) |
1da177e4 | 2028 | { |
e2651647 PM |
2029 | if (port->flags & UPF_IOREMAP) { |
2030 | iounmap(port->membase); | |
2031 | port->membase = NULL; | |
2032 | } | |
2033 | ||
2034 | release_mem_region(port->mapbase, sci_port_size(port)); | |
1da177e4 LT |
2035 | } |
2036 | ||
e2651647 | 2037 | static int sci_request_port(struct uart_port *port) |
1da177e4 | 2038 | { |
e2651647 PM |
2039 | unsigned long size = sci_port_size(port); |
2040 | struct resource *res; | |
f6e9495d | 2041 | int ret; |
1da177e4 | 2042 | |
1020520e | 2043 | res = request_mem_region(port->mapbase, size, dev_name(port->dev)); |
e2651647 PM |
2044 | if (unlikely(res == NULL)) |
2045 | return -EBUSY; | |
1da177e4 | 2046 | |
f6e9495d PM |
2047 | ret = sci_remap_port(port); |
2048 | if (unlikely(ret != 0)) { | |
2049 | release_resource(res); | |
2050 | return ret; | |
7ff731ae | 2051 | } |
e2651647 PM |
2052 | |
2053 | return 0; | |
2054 | } | |
2055 | ||
2056 | static void sci_config_port(struct uart_port *port, int flags) | |
2057 | { | |
2058 | if (flags & UART_CONFIG_TYPE) { | |
2059 | struct sci_port *sport = to_sci_port(port); | |
2060 | ||
2061 | port->type = sport->cfg->type; | |
2062 | sci_request_port(port); | |
2063 | } | |
1da177e4 LT |
2064 | } |
2065 | ||
2066 | static int sci_verify_port(struct uart_port *port, struct serial_struct *ser) | |
2067 | { | |
1da177e4 LT |
2068 | if (ser->baud_base < 2400) |
2069 | /* No paper tape reader for Mitch.. */ | |
2070 | return -EINVAL; | |
2071 | ||
2072 | return 0; | |
2073 | } | |
2074 | ||
2075 | static struct uart_ops sci_uart_ops = { | |
2076 | .tx_empty = sci_tx_empty, | |
2077 | .set_mctrl = sci_set_mctrl, | |
2078 | .get_mctrl = sci_get_mctrl, | |
2079 | .start_tx = sci_start_tx, | |
2080 | .stop_tx = sci_stop_tx, | |
2081 | .stop_rx = sci_stop_rx, | |
2082 | .enable_ms = sci_enable_ms, | |
2083 | .break_ctl = sci_break_ctl, | |
2084 | .startup = sci_startup, | |
2085 | .shutdown = sci_shutdown, | |
2086 | .set_termios = sci_set_termios, | |
0174e5ca | 2087 | .pm = sci_pm, |
1da177e4 LT |
2088 | .type = sci_type, |
2089 | .release_port = sci_release_port, | |
2090 | .request_port = sci_request_port, | |
2091 | .config_port = sci_config_port, | |
2092 | .verify_port = sci_verify_port, | |
07d2a1a1 PM |
2093 | #ifdef CONFIG_CONSOLE_POLL |
2094 | .poll_get_char = sci_poll_get_char, | |
2095 | .poll_put_char = sci_poll_put_char, | |
2096 | #endif | |
1da177e4 LT |
2097 | }; |
2098 | ||
9671f099 | 2099 | static int sci_init_single(struct platform_device *dev, |
1fcc91a6 LP |
2100 | struct sci_port *sci_port, unsigned int index, |
2101 | struct plat_sci_port *p, bool early) | |
e108b2ca | 2102 | { |
73a19e4c | 2103 | struct uart_port *port = &sci_port->port; |
1fcc91a6 | 2104 | const struct resource *res; |
ec09c5eb | 2105 | unsigned int sampling_rate; |
1fcc91a6 | 2106 | unsigned int i; |
3127c6b2 | 2107 | int ret; |
e108b2ca | 2108 | |
50f0959a PM |
2109 | sci_port->cfg = p; |
2110 | ||
73a19e4c GL |
2111 | port->ops = &sci_uart_ops; |
2112 | port->iotype = UPIO_MEM; | |
2113 | port->line = index; | |
75136d48 | 2114 | |
89b5c1ab LP |
2115 | res = platform_get_resource(dev, IORESOURCE_MEM, 0); |
2116 | if (res == NULL) | |
2117 | return -ENOMEM; | |
1fcc91a6 | 2118 | |
89b5c1ab | 2119 | port->mapbase = res->start; |
1fcc91a6 | 2120 | |
89b5c1ab LP |
2121 | for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i) |
2122 | sci_port->irqs[i] = platform_get_irq(dev, i); | |
1fcc91a6 | 2123 | |
89b5c1ab LP |
2124 | /* The SCI generates several interrupts. They can be muxed together or |
2125 | * connected to different interrupt lines. In the muxed case only one | |
2126 | * interrupt resource is specified. In the non-muxed case three or four | |
2127 | * interrupt resources are specified, as the BRI interrupt is optional. | |
2128 | */ | |
2129 | if (sci_port->irqs[0] < 0) | |
2130 | return -ENXIO; | |
1fcc91a6 | 2131 | |
89b5c1ab LP |
2132 | if (sci_port->irqs[1] < 0) { |
2133 | sci_port->irqs[1] = sci_port->irqs[0]; | |
2134 | sci_port->irqs[2] = sci_port->irqs[0]; | |
2135 | sci_port->irqs[3] = sci_port->irqs[0]; | |
1fcc91a6 LP |
2136 | } |
2137 | ||
b545e4f4 LP |
2138 | if (p->regtype == SCIx_PROBE_REGTYPE) { |
2139 | ret = sci_probe_regmap(p); | |
2140 | if (unlikely(ret)) | |
2141 | return ret; | |
2142 | } | |
2143 | ||
75136d48 | 2144 | switch (p->type) { |
d1d4b10c GL |
2145 | case PORT_SCIFB: |
2146 | port->fifosize = 256; | |
b545e4f4 | 2147 | sci_port->overrun_bit = 9; |
ec09c5eb | 2148 | sampling_rate = 16; |
d1d4b10c | 2149 | break; |
f303b364 UH |
2150 | case PORT_HSCIF: |
2151 | port->fifosize = 128; | |
ec09c5eb | 2152 | sampling_rate = 0; |
b545e4f4 | 2153 | sci_port->overrun_bit = 0; |
f303b364 | 2154 | break; |
75136d48 | 2155 | case PORT_SCIFA: |
73a19e4c | 2156 | port->fifosize = 64; |
b545e4f4 | 2157 | sci_port->overrun_bit = 9; |
ec09c5eb | 2158 | sampling_rate = 16; |
75136d48 MP |
2159 | break; |
2160 | case PORT_SCIF: | |
73a19e4c | 2161 | port->fifosize = 16; |
ec09c5eb | 2162 | if (p->regtype == SCIx_SH7705_SCIF_REGTYPE) { |
b545e4f4 | 2163 | sci_port->overrun_bit = 9; |
ec09c5eb LP |
2164 | sampling_rate = 16; |
2165 | } else { | |
b545e4f4 | 2166 | sci_port->overrun_bit = 0; |
ec09c5eb LP |
2167 | sampling_rate = 32; |
2168 | } | |
75136d48 MP |
2169 | break; |
2170 | default: | |
73a19e4c | 2171 | port->fifosize = 1; |
b545e4f4 | 2172 | sci_port->overrun_bit = 5; |
ec09c5eb | 2173 | sampling_rate = 32; |
75136d48 MP |
2174 | break; |
2175 | } | |
7b6fd3bf | 2176 | |
878fbb91 LP |
2177 | /* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't |
2178 | * match the SoC datasheet, this should be investigated. Let platform | |
2179 | * data override the sampling rate for now. | |
ec09c5eb | 2180 | */ |
878fbb91 LP |
2181 | sci_port->sampling_rate = p->sampling_rate ? p->sampling_rate |
2182 | : sampling_rate; | |
ec09c5eb | 2183 | |
1fcc91a6 | 2184 | if (!early) { |
c7ed1ab3 PM |
2185 | sci_port->iclk = clk_get(&dev->dev, "sci_ick"); |
2186 | if (IS_ERR(sci_port->iclk)) { | |
2187 | sci_port->iclk = clk_get(&dev->dev, "peripheral_clk"); | |
2188 | if (IS_ERR(sci_port->iclk)) { | |
2189 | dev_err(&dev->dev, "can't get iclk\n"); | |
2190 | return PTR_ERR(sci_port->iclk); | |
2191 | } | |
2192 | } | |
2193 | ||
2194 | /* | |
2195 | * The function clock is optional, ignore it if we can't | |
2196 | * find it. | |
2197 | */ | |
2198 | sci_port->fclk = clk_get(&dev->dev, "sci_fck"); | |
2199 | if (IS_ERR(sci_port->fclk)) | |
2200 | sci_port->fclk = NULL; | |
2201 | ||
73a19e4c | 2202 | port->dev = &dev->dev; |
5e50d2d6 MD |
2203 | |
2204 | pm_runtime_enable(&dev->dev); | |
7b6fd3bf | 2205 | } |
e108b2ca | 2206 | |
7ed7e071 MD |
2207 | sci_port->break_timer.data = (unsigned long)sci_port; |
2208 | sci_port->break_timer.function = sci_break_timer; | |
2209 | init_timer(&sci_port->break_timer); | |
2210 | ||
debf9507 PM |
2211 | /* |
2212 | * Establish some sensible defaults for the error detection. | |
2213 | */ | |
3ae988d9 | 2214 | sci_port->error_mask = (p->type == PORT_SCI) ? |
debf9507 PM |
2215 | SCI_DEFAULT_ERROR_MASK : SCIF_DEFAULT_ERROR_MASK; |
2216 | ||
2217 | /* | |
2218 | * Establish sensible defaults for the overrun detection, unless | |
2219 | * the part has explicitly disabled support for it. | |
2220 | */ | |
debf9507 | 2221 | |
3ae988d9 LP |
2222 | /* |
2223 | * Make the error mask inclusive of overrun detection, if | |
2224 | * supported. | |
2225 | */ | |
2226 | sci_port->error_mask |= 1 << sci_port->overrun_bit; | |
debf9507 | 2227 | |
ce6738b6 | 2228 | port->type = p->type; |
b6e4a3f1 | 2229 | port->flags = UPF_FIXED_PORT | p->flags; |
61a6976b | 2230 | port->regshift = p->regshift; |
73a19e4c | 2231 | |
ce6738b6 | 2232 | /* |
61a6976b | 2233 | * The UART port needs an IRQ value, so we peg this to the RX IRQ |
ce6738b6 PM |
2234 | * for the multi-IRQ ports, which is where we are primarily |
2235 | * concerned with the shutdown path synchronization. | |
2236 | * | |
2237 | * For the muxed case there's nothing more to do. | |
2238 | */ | |
1fcc91a6 | 2239 | port->irq = sci_port->irqs[SCIx_RXI_IRQ]; |
9cfb5c05 | 2240 | port->irqflags = 0; |
73a19e4c | 2241 | |
61a6976b PM |
2242 | port->serial_in = sci_serial_in; |
2243 | port->serial_out = sci_serial_out; | |
2244 | ||
937bb6e4 GL |
2245 | if (p->dma_slave_tx > 0 && p->dma_slave_rx > 0) |
2246 | dev_dbg(port->dev, "DMA tx %d, rx %d\n", | |
2247 | p->dma_slave_tx, p->dma_slave_rx); | |
7ed7e071 | 2248 | |
c7ed1ab3 | 2249 | return 0; |
e108b2ca PM |
2250 | } |
2251 | ||
6dae1421 LP |
2252 | static void sci_cleanup_single(struct sci_port *port) |
2253 | { | |
6dae1421 LP |
2254 | clk_put(port->iclk); |
2255 | clk_put(port->fclk); | |
2256 | ||
2257 | pm_runtime_disable(port->port.dev); | |
2258 | } | |
2259 | ||
1da177e4 | 2260 | #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE |
dc8e6f5b MD |
2261 | static void serial_console_putchar(struct uart_port *port, int ch) |
2262 | { | |
2263 | sci_poll_put_char(port, ch); | |
2264 | } | |
2265 | ||
1da177e4 LT |
2266 | /* |
2267 | * Print a string to the serial port trying not to disturb | |
2268 | * any possible real use of the port... | |
2269 | */ | |
2270 | static void serial_console_write(struct console *co, const char *s, | |
2271 | unsigned count) | |
2272 | { | |
906b17dc PM |
2273 | struct sci_port *sci_port = &sci_ports[co->index]; |
2274 | struct uart_port *port = &sci_port->port; | |
40f70c03 SK |
2275 | unsigned short bits, ctrl; |
2276 | unsigned long flags; | |
2277 | int locked = 1; | |
2278 | ||
2279 | local_irq_save(flags); | |
2280 | if (port->sysrq) | |
2281 | locked = 0; | |
2282 | else if (oops_in_progress) | |
2283 | locked = spin_trylock(&port->lock); | |
2284 | else | |
2285 | spin_lock(&port->lock); | |
2286 | ||
2287 | /* first save the SCSCR then disable the interrupts */ | |
2288 | ctrl = serial_port_in(port, SCSCR); | |
2289 | serial_port_out(port, SCSCR, sci_port->cfg->scscr); | |
07d2a1a1 | 2290 | |
501b825d | 2291 | uart_console_write(port, s, count, serial_console_putchar); |
973e5d52 MD |
2292 | |
2293 | /* wait until fifo is empty and last bit has been transmitted */ | |
2294 | bits = SCxSR_TDxE(port) | SCxSR_TEND(port); | |
b12bb29f | 2295 | while ((serial_port_in(port, SCxSR) & bits) != bits) |
973e5d52 | 2296 | cpu_relax(); |
40f70c03 SK |
2297 | |
2298 | /* restore the SCSCR */ | |
2299 | serial_port_out(port, SCSCR, ctrl); | |
2300 | ||
2301 | if (locked) | |
2302 | spin_unlock(&port->lock); | |
2303 | local_irq_restore(flags); | |
1da177e4 LT |
2304 | } |
2305 | ||
9671f099 | 2306 | static int serial_console_setup(struct console *co, char *options) |
1da177e4 | 2307 | { |
dc8e6f5b | 2308 | struct sci_port *sci_port; |
1da177e4 LT |
2309 | struct uart_port *port; |
2310 | int baud = 115200; | |
2311 | int bits = 8; | |
2312 | int parity = 'n'; | |
2313 | int flow = 'n'; | |
2314 | int ret; | |
2315 | ||
e108b2ca | 2316 | /* |
906b17dc | 2317 | * Refuse to handle any bogus ports. |
1da177e4 | 2318 | */ |
906b17dc | 2319 | if (co->index < 0 || co->index >= SCI_NPORTS) |
e108b2ca | 2320 | return -ENODEV; |
e108b2ca | 2321 | |
906b17dc PM |
2322 | sci_port = &sci_ports[co->index]; |
2323 | port = &sci_port->port; | |
2324 | ||
b2267a6b AC |
2325 | /* |
2326 | * Refuse to handle uninitialized ports. | |
2327 | */ | |
2328 | if (!port->ops) | |
2329 | return -ENODEV; | |
2330 | ||
f6e9495d PM |
2331 | ret = sci_remap_port(port); |
2332 | if (unlikely(ret != 0)) | |
2333 | return ret; | |
e108b2ca | 2334 | |
1da177e4 LT |
2335 | if (options) |
2336 | uart_parse_options(options, &baud, &parity, &bits, &flow); | |
2337 | ||
ab7cfb55 | 2338 | return uart_set_options(port, co, baud, parity, bits, flow); |
1da177e4 LT |
2339 | } |
2340 | ||
2341 | static struct console serial_console = { | |
2342 | .name = "ttySC", | |
906b17dc | 2343 | .device = uart_console_device, |
1da177e4 LT |
2344 | .write = serial_console_write, |
2345 | .setup = serial_console_setup, | |
fa5da2f7 | 2346 | .flags = CON_PRINTBUFFER, |
1da177e4 | 2347 | .index = -1, |
906b17dc | 2348 | .data = &sci_uart_driver, |
1da177e4 LT |
2349 | }; |
2350 | ||
7b6fd3bf MD |
2351 | static struct console early_serial_console = { |
2352 | .name = "early_ttySC", | |
2353 | .write = serial_console_write, | |
2354 | .flags = CON_PRINTBUFFER, | |
906b17dc | 2355 | .index = -1, |
7b6fd3bf | 2356 | }; |
ecdf8a46 | 2357 | |
7b6fd3bf MD |
2358 | static char early_serial_buf[32]; |
2359 | ||
9671f099 | 2360 | static int sci_probe_earlyprintk(struct platform_device *pdev) |
ecdf8a46 | 2361 | { |
574de559 | 2362 | struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev); |
ecdf8a46 PM |
2363 | |
2364 | if (early_serial_console.data) | |
2365 | return -EEXIST; | |
2366 | ||
2367 | early_serial_console.index = pdev->id; | |
ecdf8a46 | 2368 | |
1fcc91a6 | 2369 | sci_init_single(pdev, &sci_ports[pdev->id], pdev->id, cfg, true); |
ecdf8a46 PM |
2370 | |
2371 | serial_console_setup(&early_serial_console, early_serial_buf); | |
2372 | ||
2373 | if (!strstr(early_serial_buf, "keep")) | |
2374 | early_serial_console.flags |= CON_BOOT; | |
2375 | ||
2376 | register_console(&early_serial_console); | |
2377 | return 0; | |
2378 | } | |
6a8c9799 NI |
2379 | |
2380 | #define SCI_CONSOLE (&serial_console) | |
2381 | ||
ecdf8a46 | 2382 | #else |
9671f099 | 2383 | static inline int sci_probe_earlyprintk(struct platform_device *pdev) |
ecdf8a46 PM |
2384 | { |
2385 | return -EINVAL; | |
2386 | } | |
1da177e4 | 2387 | |
6a8c9799 NI |
2388 | #define SCI_CONSOLE NULL |
2389 | ||
2390 | #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */ | |
1da177e4 LT |
2391 | |
2392 | static char banner[] __initdata = | |
f303b364 | 2393 | KERN_INFO "SuperH (H)SCI(F) driver initialized\n"; |
1da177e4 LT |
2394 | |
2395 | static struct uart_driver sci_uart_driver = { | |
2396 | .owner = THIS_MODULE, | |
2397 | .driver_name = "sci", | |
1da177e4 LT |
2398 | .dev_name = "ttySC", |
2399 | .major = SCI_MAJOR, | |
2400 | .minor = SCI_MINOR_START, | |
e108b2ca | 2401 | .nr = SCI_NPORTS, |
1da177e4 LT |
2402 | .cons = SCI_CONSOLE, |
2403 | }; | |
2404 | ||
54507f6e | 2405 | static int sci_remove(struct platform_device *dev) |
e552de24 | 2406 | { |
d535a230 | 2407 | struct sci_port *port = platform_get_drvdata(dev); |
e552de24 | 2408 | |
d535a230 PM |
2409 | cpufreq_unregister_notifier(&port->freq_transition, |
2410 | CPUFREQ_TRANSITION_NOTIFIER); | |
e552de24 | 2411 | |
d535a230 PM |
2412 | uart_remove_one_port(&sci_uart_driver, &port->port); |
2413 | ||
6dae1421 | 2414 | sci_cleanup_single(port); |
e552de24 | 2415 | |
e552de24 MD |
2416 | return 0; |
2417 | } | |
2418 | ||
20bdcab8 BH |
2419 | struct sci_port_info { |
2420 | unsigned int type; | |
2421 | unsigned int regtype; | |
2422 | }; | |
2423 | ||
2424 | static const struct of_device_id of_sci_match[] = { | |
2425 | { | |
2426 | .compatible = "renesas,scif", | |
2427 | .data = (void *)&(const struct sci_port_info) { | |
2428 | .type = PORT_SCIF, | |
2429 | .regtype = SCIx_SH4_SCIF_REGTYPE, | |
2430 | }, | |
2431 | }, { | |
2432 | .compatible = "renesas,scifa", | |
2433 | .data = (void *)&(const struct sci_port_info) { | |
2434 | .type = PORT_SCIFA, | |
2435 | .regtype = SCIx_SCIFA_REGTYPE, | |
2436 | }, | |
2437 | }, { | |
2438 | .compatible = "renesas,scifb", | |
2439 | .data = (void *)&(const struct sci_port_info) { | |
2440 | .type = PORT_SCIFB, | |
2441 | .regtype = SCIx_SCIFB_REGTYPE, | |
2442 | }, | |
2443 | }, { | |
2444 | .compatible = "renesas,hscif", | |
2445 | .data = (void *)&(const struct sci_port_info) { | |
2446 | .type = PORT_HSCIF, | |
2447 | .regtype = SCIx_HSCIF_REGTYPE, | |
2448 | }, | |
2449 | }, { | |
2450 | /* Terminator */ | |
2451 | }, | |
2452 | }; | |
2453 | MODULE_DEVICE_TABLE(of, of_sci_match); | |
2454 | ||
2455 | static struct plat_sci_port * | |
2456 | sci_parse_dt(struct platform_device *pdev, unsigned int *dev_id) | |
2457 | { | |
2458 | struct device_node *np = pdev->dev.of_node; | |
2459 | const struct of_device_id *match; | |
2460 | const struct sci_port_info *info; | |
2461 | struct plat_sci_port *p; | |
2462 | int id; | |
2463 | ||
2464 | if (!IS_ENABLED(CONFIG_OF) || !np) | |
2465 | return NULL; | |
2466 | ||
2467 | match = of_match_node(of_sci_match, pdev->dev.of_node); | |
2468 | if (!match) | |
2469 | return NULL; | |
2470 | ||
2471 | info = match->data; | |
2472 | ||
2473 | p = devm_kzalloc(&pdev->dev, sizeof(struct plat_sci_port), GFP_KERNEL); | |
2474 | if (!p) { | |
2475 | dev_err(&pdev->dev, "failed to allocate DT config data\n"); | |
2476 | return NULL; | |
2477 | } | |
2478 | ||
2479 | /* Get the line number for the aliases node. */ | |
2480 | id = of_alias_get_id(np, "serial"); | |
2481 | if (id < 0) { | |
2482 | dev_err(&pdev->dev, "failed to get alias id (%d)\n", id); | |
2483 | return NULL; | |
2484 | } | |
2485 | ||
2486 | *dev_id = id; | |
2487 | ||
2488 | p->flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF; | |
2489 | p->type = info->type; | |
2490 | p->regtype = info->regtype; | |
2491 | p->scscr = SCSCR_RE | SCSCR_TE; | |
2492 | ||
2493 | return p; | |
2494 | } | |
2495 | ||
9671f099 | 2496 | static int sci_probe_single(struct platform_device *dev, |
0ee70712 MD |
2497 | unsigned int index, |
2498 | struct plat_sci_port *p, | |
2499 | struct sci_port *sciport) | |
2500 | { | |
0ee70712 MD |
2501 | int ret; |
2502 | ||
2503 | /* Sanity check */ | |
2504 | if (unlikely(index >= SCI_NPORTS)) { | |
2505 | dev_notice(&dev->dev, "Attempting to register port " | |
2506 | "%d when only %d are available.\n", | |
2507 | index+1, SCI_NPORTS); | |
2508 | dev_notice(&dev->dev, "Consider bumping " | |
2509 | "CONFIG_SERIAL_SH_SCI_NR_UARTS!\n"); | |
b6c5ef6f | 2510 | return -EINVAL; |
0ee70712 MD |
2511 | } |
2512 | ||
1fcc91a6 | 2513 | ret = sci_init_single(dev, sciport, index, p, false); |
c7ed1ab3 PM |
2514 | if (ret) |
2515 | return ret; | |
0ee70712 | 2516 | |
6dae1421 LP |
2517 | ret = uart_add_one_port(&sci_uart_driver, &sciport->port); |
2518 | if (ret) { | |
2519 | sci_cleanup_single(sciport); | |
2520 | return ret; | |
2521 | } | |
2522 | ||
2523 | return 0; | |
0ee70712 MD |
2524 | } |
2525 | ||
9671f099 | 2526 | static int sci_probe(struct platform_device *dev) |
1da177e4 | 2527 | { |
20bdcab8 BH |
2528 | struct plat_sci_port *p; |
2529 | struct sci_port *sp; | |
2530 | unsigned int dev_id; | |
ecdf8a46 | 2531 | int ret; |
d535a230 | 2532 | |
ecdf8a46 PM |
2533 | /* |
2534 | * If we've come here via earlyprintk initialization, head off to | |
2535 | * the special early probe. We don't have sufficient device state | |
2536 | * to make it beyond this yet. | |
2537 | */ | |
2538 | if (is_early_platform_device(dev)) | |
2539 | return sci_probe_earlyprintk(dev); | |
7b6fd3bf | 2540 | |
20bdcab8 BH |
2541 | if (dev->dev.of_node) { |
2542 | p = sci_parse_dt(dev, &dev_id); | |
2543 | if (p == NULL) | |
2544 | return -EINVAL; | |
2545 | } else { | |
2546 | p = dev->dev.platform_data; | |
2547 | if (p == NULL) { | |
2548 | dev_err(&dev->dev, "no platform data supplied\n"); | |
2549 | return -EINVAL; | |
2550 | } | |
2551 | ||
2552 | dev_id = dev->id; | |
2553 | } | |
2554 | ||
2555 | sp = &sci_ports[dev_id]; | |
d535a230 | 2556 | platform_set_drvdata(dev, sp); |
e552de24 | 2557 | |
20bdcab8 | 2558 | ret = sci_probe_single(dev, dev_id, p, sp); |
d535a230 | 2559 | if (ret) |
6dae1421 | 2560 | return ret; |
e552de24 | 2561 | |
d535a230 | 2562 | sp->freq_transition.notifier_call = sci_notifier; |
1da177e4 | 2563 | |
d535a230 PM |
2564 | ret = cpufreq_register_notifier(&sp->freq_transition, |
2565 | CPUFREQ_TRANSITION_NOTIFIER); | |
6dae1421 | 2566 | if (unlikely(ret < 0)) { |
bf13c9a8 | 2567 | uart_remove_one_port(&sci_uart_driver, &sp->port); |
6dae1421 LP |
2568 | sci_cleanup_single(sp); |
2569 | return ret; | |
2570 | } | |
1da177e4 LT |
2571 | |
2572 | #ifdef CONFIG_SH_STANDARD_BIOS | |
2573 | sh_bios_gdb_detach(); | |
2574 | #endif | |
2575 | ||
e108b2ca | 2576 | return 0; |
1da177e4 LT |
2577 | } |
2578 | ||
6daa79b3 | 2579 | static int sci_suspend(struct device *dev) |
1da177e4 | 2580 | { |
d535a230 | 2581 | struct sci_port *sport = dev_get_drvdata(dev); |
e108b2ca | 2582 | |
d535a230 PM |
2583 | if (sport) |
2584 | uart_suspend_port(&sci_uart_driver, &sport->port); | |
1da177e4 | 2585 | |
e108b2ca PM |
2586 | return 0; |
2587 | } | |
1da177e4 | 2588 | |
6daa79b3 | 2589 | static int sci_resume(struct device *dev) |
e108b2ca | 2590 | { |
d535a230 | 2591 | struct sci_port *sport = dev_get_drvdata(dev); |
e108b2ca | 2592 | |
d535a230 PM |
2593 | if (sport) |
2594 | uart_resume_port(&sci_uart_driver, &sport->port); | |
e108b2ca PM |
2595 | |
2596 | return 0; | |
2597 | } | |
2598 | ||
47145210 | 2599 | static const struct dev_pm_ops sci_dev_pm_ops = { |
6daa79b3 PM |
2600 | .suspend = sci_suspend, |
2601 | .resume = sci_resume, | |
2602 | }; | |
2603 | ||
e108b2ca PM |
2604 | static struct platform_driver sci_driver = { |
2605 | .probe = sci_probe, | |
b9e39c89 | 2606 | .remove = sci_remove, |
e108b2ca PM |
2607 | .driver = { |
2608 | .name = "sh-sci", | |
2609 | .owner = THIS_MODULE, | |
6daa79b3 | 2610 | .pm = &sci_dev_pm_ops, |
20bdcab8 | 2611 | .of_match_table = of_match_ptr(of_sci_match), |
e108b2ca PM |
2612 | }, |
2613 | }; | |
2614 | ||
2615 | static int __init sci_init(void) | |
2616 | { | |
2617 | int ret; | |
2618 | ||
2619 | printk(banner); | |
2620 | ||
e108b2ca PM |
2621 | ret = uart_register_driver(&sci_uart_driver); |
2622 | if (likely(ret == 0)) { | |
2623 | ret = platform_driver_register(&sci_driver); | |
2624 | if (unlikely(ret)) | |
2625 | uart_unregister_driver(&sci_uart_driver); | |
2626 | } | |
2627 | ||
2628 | return ret; | |
2629 | } | |
2630 | ||
2631 | static void __exit sci_exit(void) | |
2632 | { | |
2633 | platform_driver_unregister(&sci_driver); | |
1da177e4 LT |
2634 | uart_unregister_driver(&sci_uart_driver); |
2635 | } | |
2636 | ||
7b6fd3bf MD |
2637 | #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE |
2638 | early_platform_init_buffer("earlyprintk", &sci_driver, | |
2639 | early_serial_buf, ARRAY_SIZE(early_serial_buf)); | |
2640 | #endif | |
1da177e4 LT |
2641 | module_init(sci_init); |
2642 | module_exit(sci_exit); | |
2643 | ||
e108b2ca | 2644 | MODULE_LICENSE("GPL"); |
e169c139 | 2645 | MODULE_ALIAS("platform:sh-sci"); |
7f405f9c | 2646 | MODULE_AUTHOR("Paul Mundt"); |
f303b364 | 2647 | MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver"); |