projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge tag 'firewire-update2' of git://git.kernel.org/pub/scm/linux/kernel/git/ieee139...
[linux-2.6-block.git] / drivers / tty / serial / sh-sci.c
CommitLineData
1da177e4 1/*
1da177e4
LT		 2 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
3 *
f43dc23d 4 * Copyright (C) 2002 - 2011 Paul Mundt
f4998e55 5 * Copyright (C) 2015 Glider bvba
3ea6bc3d 6 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
1da177e4
LT		 7 *
8 * based off of the old drivers/char/sh-sci.c by:
9 *
10 * Copyright (C) 1999, 2000 Niibe Yutaka
11 * Copyright (C) 2000 Sugioka Toshinobu
12 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
13 * Modified to support SecureEdge. David McCullough (2002)
14 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
d89ddd1c 15 * Removed SH7300 support (Jul 2007).
1da177e4
LT		 16 *
17 * This file is subject to the terms and conditions of the GNU General Public
18 * License. See the file "COPYING" in the main directory of this archive
19 * for more details.
20 */
0b3d4ef6
PM		 21#if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
22#define SUPPORT_SYSRQ
23#endif
1da177e4
LT		 24
25#undef DEBUG
26
8fb9631c
LP		 27#include <linux/clk.h>
28#include <linux/console.h>
29#include <linux/ctype.h>
30#include <linux/cpufreq.h>
31#include <linux/delay.h>
32#include <linux/dmaengine.h>
33#include <linux/dma-mapping.h>
34#include <linux/err.h>
1da177e4 35#include <linux/errno.h>
8fb9631c 36#include <linux/init.h>
1da177e4 37#include <linux/interrupt.h>
1da177e4 38#include <linux/ioport.h>
8fb9631c
LP		 39#include <linux/major.h>
40#include <linux/module.h>
1da177e4 41#include <linux/mm.h>
20bdcab8 42#include <linux/of.h>
8fb9631c 43#include <linux/platform_device.h>
5e50d2d6 44#include <linux/pm_runtime.h>
73a19e4c 45#include <linux/scatterlist.h>
8fb9631c
LP		 46#include <linux/serial.h>
47#include <linux/serial_sci.h>
48#include <linux/sh_dma.h>
5a0e3ad6 49#include <linux/slab.h>
8fb9631c
LP		 50#include <linux/string.h>
51#include <linux/sysrq.h>
52#include <linux/timer.h>
53#include <linux/tty.h>
54#include <linux/tty_flip.h>
85f094ec
PM		 55
56#ifdef CONFIG_SUPERH
1da177e4
LT		 57#include <asm/sh_bios.h>
58#endif
59
1da177e4
LT		 60#include "sh-sci.h"
61
89b5c1ab
LP		 62/* Offsets into the sci_port->irqs array */
63enum {
64 SCIx_ERI_IRQ,
65 SCIx_RXI_IRQ,
66 SCIx_TXI_IRQ,
67 SCIx_BRI_IRQ,
68 SCIx_NR_IRQS,
69
70 SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */
71};
72
73#define SCIx_IRQ_IS_MUXED(port) \
74 ((port)->irqs[SCIx_ERI_IRQ] == \
75 (port)->irqs[SCIx_RXI_IRQ]) || \
76 ((port)->irqs[SCIx_ERI_IRQ] && \
77 ((port)->irqs[SCIx_RXI_IRQ] < 0))
78
f4998e55
GU		 79enum SCI_CLKS {
80 SCI_FCK, /* Functional Clock */
6af27bf2 81 SCI_SCK, /* Optional External Clock */
1270f865
GU		 82 SCI_BRG_INT, /* Optional BRG Internal Clock Source */
83 SCI_SCIF_CLK, /* Optional BRG External Clock Source */
f4998e55
GU		 84 SCI_NUM_CLKS
85};
86
69eee8e9
GU		 87/* Bit x set means sampling rate x + 1 is supported */
88#define SCI_SR(x) BIT((x) - 1)
89#define SCI_SR_RANGE(x, y) GENMASK((y) - 1, (x) - 1)
90
92a05748
GU		 91#define SCI_SR_SCIFAB SCI_SR(5) | SCI_SR(7) | SCI_SR(11) | \
92 SCI_SR(13) | SCI_SR(16) | SCI_SR(17) | \
93 SCI_SR(19) | SCI_SR(27)
94
69eee8e9
GU		 95#define min_sr(_port) ffs((_port)->sampling_rate_mask)
96#define max_sr(_port) fls((_port)->sampling_rate_mask)
97
98/* Iterate over all supported sampling rates, from high to low */
99#define for_each_sr(_sr, _port) \
100 for ((_sr) = max_sr(_port); (_sr) >= min_sr(_port); (_sr)--) \
101 if ((_port)->sampling_rate_mask & SCI_SR((_sr)))
102
e108b2ca
PM		 103struct sci_port {
104 struct uart_port port;
105
ce6738b6
PM		 106 /* Platform configuration */
107 struct plat_sci_port *cfg;
2e0842a1 108 unsigned int overrun_reg;
75c249fd 109 unsigned int overrun_mask;
3ae988d9 110 unsigned int error_mask;
5da0f468 111 unsigned int error_clear;
69eee8e9 112 unsigned int sampling_rate_mask;
e4d6f911 113 resource_size_t reg_size;
e108b2ca 114
e108b2ca
PM		 115 /* Break timer */
116 struct timer_list break_timer;
117 int break_flag;
1534a3b3 118
f4998e55
GU		 119 /* Clocks */
120 struct clk *clks[SCI_NUM_CLKS];
121 unsigned long clk_rates[SCI_NUM_CLKS];
edad1f20 122
1fcc91a6 123 int irqs[SCIx_NR_IRQS];
9174fc8f
PM		 124 char *irqstr[SCIx_NR_IRQS];
125
73a19e4c
GL		 126 struct dma_chan *chan_tx;
127 struct dma_chan *chan_rx;
f43dc23d 128
73a19e4c 129#ifdef CONFIG_SERIAL_SH_SCI_DMA
73a19e4c
GL		 130 dma_cookie_t cookie_tx;
131 dma_cookie_t cookie_rx[2];
132 dma_cookie_t active_rx;
79904420
GU		 133 dma_addr_t tx_dma_addr;
134 unsigned int tx_dma_len;
73a19e4c 135 struct scatterlist sg_rx[2];
7b39d901 136 void *rx_buf[2];
73a19e4c 137 size_t buf_len_rx;
73a19e4c 138 struct work_struct work_tx;
73a19e4c 139 struct timer_list rx_timer;
3089f381 140 unsigned int rx_timeout;
73a19e4c 141#endif
e108b2ca
PM		 142};
143
e108b2ca 144#define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
b7a76e4b 145
e108b2ca
PM		 146static struct sci_port sci_ports[SCI_NPORTS];
147static struct uart_driver sci_uart_driver;
1da177e4 148
e7c98dc7
MT		 149static inline struct sci_port *
150to_sci_port(struct uart_port *uart)
151{
152 return container_of(uart, struct sci_port, port);
153}
154
61a6976b
PM		 155struct plat_sci_reg {
156 u8 offset, size;
157};
158
159/* Helper for invalidating specific entries of an inherited map. */
160#define sci_reg_invalid { .offset = 0, .size = 0 }
161
d3184e68 162static const struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = {
61a6976b
PM		 163 [SCIx_PROBE_REGTYPE] = {
164 [0 ... SCIx_NR_REGS - 1] = sci_reg_invalid,
165 },
166
167 /*
168 * Common SCI definitions, dependent on the port's regshift
169 * value.
170 */
171 [SCIx_SCI_REGTYPE] = {
172 [SCSMR] = { 0x00, 8 },
173 [SCBRR] = { 0x01, 8 },
174 [SCSCR] = { 0x02, 8 },
175 [SCxTDR] = { 0x03, 8 },
176 [SCxSR] = { 0x04, 8 },
177 [SCxRDR] = { 0x05, 8 },
178 [SCFCR] = sci_reg_invalid,
179 [SCFDR] = sci_reg_invalid,
180 [SCTFDR] = sci_reg_invalid,
181 [SCRFDR] = sci_reg_invalid,
182 [SCSPTR] = sci_reg_invalid,
183 [SCLSR] = sci_reg_invalid,
f303b364 184 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 185 [SCPCR] = sci_reg_invalid,
186 [SCPDR] = sci_reg_invalid,
b8bbd6b2
GU		 187 [SCDL] = sci_reg_invalid,
188 [SCCKS] = sci_reg_invalid,
61a6976b
PM		 189 },
190
191 /*
192 * Common definitions for legacy IrDA ports, dependent on
193 * regshift value.
194 */
195 [SCIx_IRDA_REGTYPE] = {
196 [SCSMR] = { 0x00, 8 },
197 [SCBRR] = { 0x01, 8 },
198 [SCSCR] = { 0x02, 8 },
199 [SCxTDR] = { 0x03, 8 },
200 [SCxSR] = { 0x04, 8 },
201 [SCxRDR] = { 0x05, 8 },
202 [SCFCR] = { 0x06, 8 },
203 [SCFDR] = { 0x07, 16 },
204 [SCTFDR] = sci_reg_invalid,
205 [SCRFDR] = sci_reg_invalid,
206 [SCSPTR] = sci_reg_invalid,
207 [SCLSR] = sci_reg_invalid,
f303b364 208 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 209 [SCPCR] = sci_reg_invalid,
210 [SCPDR] = sci_reg_invalid,
b8bbd6b2
GU		 211 [SCDL] = sci_reg_invalid,
212 [SCCKS] = sci_reg_invalid,
61a6976b
PM		 213 },
214
215 /*
216 * Common SCIFA definitions.
217 */
218 [SCIx_SCIFA_REGTYPE] = {
219 [SCSMR] = { 0x00, 16 },
220 [SCBRR] = { 0x04, 8 },
221 [SCSCR] = { 0x08, 16 },
222 [SCxTDR] = { 0x20, 8 },
223 [SCxSR] = { 0x14, 16 },
224 [SCxRDR] = { 0x24, 8 },
225 [SCFCR] = { 0x18, 16 },
226 [SCFDR] = { 0x1c, 16 },
227 [SCTFDR] = sci_reg_invalid,
228 [SCRFDR] = sci_reg_invalid,
229 [SCSPTR] = sci_reg_invalid,
230 [SCLSR] = sci_reg_invalid,
f303b364 231 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 232 [SCPCR] = { 0x30, 16 },
233 [SCPDR] = { 0x34, 16 },
b8bbd6b2
GU		 234 [SCDL] = sci_reg_invalid,
235 [SCCKS] = sci_reg_invalid,
61a6976b
PM		 236 },
237
238 /*
239 * Common SCIFB definitions.
240 */
241 [SCIx_SCIFB_REGTYPE] = {
242 [SCSMR] = { 0x00, 16 },
243 [SCBRR] = { 0x04, 8 },
244 [SCSCR] = { 0x08, 16 },
245 [SCxTDR] = { 0x40, 8 },
246 [SCxSR] = { 0x14, 16 },
247 [SCxRDR] = { 0x60, 8 },
248 [SCFCR] = { 0x18, 16 },
8c66d6d2
TY		 249 [SCFDR] = sci_reg_invalid,
250 [SCTFDR] = { 0x38, 16 },
251 [SCRFDR] = { 0x3c, 16 },
61a6976b
PM		 252 [SCSPTR] = sci_reg_invalid,
253 [SCLSR] = sci_reg_invalid,
f303b364 254 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 255 [SCPCR] = { 0x30, 16 },
256 [SCPDR] = { 0x34, 16 },
b8bbd6b2
GU		 257 [SCDL] = sci_reg_invalid,
258 [SCCKS] = sci_reg_invalid,
61a6976b
PM		 259 },
260
3af1f8a4
PE		 261 /*
262 * Common SH-2(A) SCIF definitions for ports with FIFO data
263 * count registers.
264 */
265 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = {
266 [SCSMR] = { 0x00, 16 },
267 [SCBRR] = { 0x04, 8 },
268 [SCSCR] = { 0x08, 16 },
269 [SCxTDR] = { 0x0c, 8 },
270 [SCxSR] = { 0x10, 16 },
271 [SCxRDR] = { 0x14, 8 },
272 [SCFCR] = { 0x18, 16 },
273 [SCFDR] = { 0x1c, 16 },
274 [SCTFDR] = sci_reg_invalid,
275 [SCRFDR] = sci_reg_invalid,
276 [SCSPTR] = { 0x20, 16 },
277 [SCLSR] = { 0x24, 16 },
f303b364 278 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 279 [SCPCR] = sci_reg_invalid,
280 [SCPDR] = sci_reg_invalid,
b8bbd6b2
GU		 281 [SCDL] = sci_reg_invalid,
282 [SCCKS] = sci_reg_invalid,
3af1f8a4
PE		 283 },
284
61a6976b
PM		 285 /*
286 * Common SH-3 SCIF definitions.
287 */
288 [SCIx_SH3_SCIF_REGTYPE] = {
289 [SCSMR] = { 0x00, 8 },
290 [SCBRR] = { 0x02, 8 },
291 [SCSCR] = { 0x04, 8 },
292 [SCxTDR] = { 0x06, 8 },
293 [SCxSR] = { 0x08, 16 },
294 [SCxRDR] = { 0x0a, 8 },
295 [SCFCR] = { 0x0c, 8 },
296 [SCFDR] = { 0x0e, 16 },
297 [SCTFDR] = sci_reg_invalid,
298 [SCRFDR] = sci_reg_invalid,
299 [SCSPTR] = sci_reg_invalid,
300 [SCLSR] = sci_reg_invalid,
f303b364 301 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 302 [SCPCR] = sci_reg_invalid,
303 [SCPDR] = sci_reg_invalid,
b8bbd6b2
GU		 304 [SCDL] = sci_reg_invalid,
305 [SCCKS] = sci_reg_invalid,
61a6976b
PM		 306 },
307
308 /*
309 * Common SH-4(A) SCIF(B) definitions.
310 */
311 [SCIx_SH4_SCIF_REGTYPE] = {
312 [SCSMR] = { 0x00, 16 },
313 [SCBRR] = { 0x04, 8 },
314 [SCSCR] = { 0x08, 16 },
315 [SCxTDR] = { 0x0c, 8 },
316 [SCxSR] = { 0x10, 16 },
317 [SCxRDR] = { 0x14, 8 },
318 [SCFCR] = { 0x18, 16 },
319 [SCFDR] = { 0x1c, 16 },
320 [SCTFDR] = sci_reg_invalid,
321 [SCRFDR] = sci_reg_invalid,
322 [SCSPTR] = { 0x20, 16 },
323 [SCLSR] = { 0x24, 16 },
f303b364 324 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 325 [SCPCR] = sci_reg_invalid,
326 [SCPDR] = sci_reg_invalid,
b8bbd6b2
GU		 327 [SCDL] = sci_reg_invalid,
328 [SCCKS] = sci_reg_invalid,
329 },
330
331 /*
332 * Common SCIF definitions for ports with a Baud Rate Generator for
333 * External Clock (BRG).
334 */
335 [SCIx_SH4_SCIF_BRG_REGTYPE] = {
336 [SCSMR] = { 0x00, 16 },
337 [SCBRR] = { 0x04, 8 },
338 [SCSCR] = { 0x08, 16 },
339 [SCxTDR] = { 0x0c, 8 },
340 [SCxSR] = { 0x10, 16 },
341 [SCxRDR] = { 0x14, 8 },
342 [SCFCR] = { 0x18, 16 },
343 [SCFDR] = { 0x1c, 16 },
344 [SCTFDR] = sci_reg_invalid,
345 [SCRFDR] = sci_reg_invalid,
346 [SCSPTR] = { 0x20, 16 },
347 [SCLSR] = { 0x24, 16 },
348 [HSSRR] = sci_reg_invalid,
349 [SCPCR] = sci_reg_invalid,
350 [SCPDR] = sci_reg_invalid,
351 [SCDL] = { 0x30, 16 },
352 [SCCKS] = { 0x34, 16 },
f303b364
UH		 353 },
354
355 /*
356 * Common HSCIF definitions.
357 */
358 [SCIx_HSCIF_REGTYPE] = {
359 [SCSMR] = { 0x00, 16 },
360 [SCBRR] = { 0x04, 8 },
361 [SCSCR] = { 0x08, 16 },
362 [SCxTDR] = { 0x0c, 8 },
363 [SCxSR] = { 0x10, 16 },
364 [SCxRDR] = { 0x14, 8 },
365 [SCFCR] = { 0x18, 16 },
366 [SCFDR] = { 0x1c, 16 },
367 [SCTFDR] = sci_reg_invalid,
368 [SCRFDR] = sci_reg_invalid,
369 [SCSPTR] = { 0x20, 16 },
370 [SCLSR] = { 0x24, 16 },
371 [HSSRR] = { 0x40, 16 },
c097abc3
GU		 372 [SCPCR] = sci_reg_invalid,
373 [SCPDR] = sci_reg_invalid,
b8bbd6b2
GU		 374 [SCDL] = { 0x30, 16 },
375 [SCCKS] = { 0x34, 16 },
61a6976b
PM		 376 },
377
378 /*
379 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR
380 * register.
381 */
382 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = {
383 [SCSMR] = { 0x00, 16 },
384 [SCBRR] = { 0x04, 8 },
385 [SCSCR] = { 0x08, 16 },
386 [SCxTDR] = { 0x0c, 8 },
387 [SCxSR] = { 0x10, 16 },
388 [SCxRDR] = { 0x14, 8 },
389 [SCFCR] = { 0x18, 16 },
390 [SCFDR] = { 0x1c, 16 },
391 [SCTFDR] = sci_reg_invalid,
392 [SCRFDR] = sci_reg_invalid,
393 [SCSPTR] = sci_reg_invalid,
394 [SCLSR] = { 0x24, 16 },
f303b364 395 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 396 [SCPCR] = sci_reg_invalid,
397 [SCPDR] = sci_reg_invalid,
b8bbd6b2
GU		 398 [SCDL] = sci_reg_invalid,
399 [SCCKS] = sci_reg_invalid,
61a6976b
PM		 400 },
401
402 /*
403 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data
404 * count registers.
405 */
406 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = {
407 [SCSMR] = { 0x00, 16 },
408 [SCBRR] = { 0x04, 8 },
409 [SCSCR] = { 0x08, 16 },
410 [SCxTDR] = { 0x0c, 8 },
411 [SCxSR] = { 0x10, 16 },
412 [SCxRDR] = { 0x14, 8 },
413 [SCFCR] = { 0x18, 16 },
414 [SCFDR] = { 0x1c, 16 },
415 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */
416 [SCRFDR] = { 0x20, 16 },
417 [SCSPTR] = { 0x24, 16 },
418 [SCLSR] = { 0x28, 16 },
f303b364 419 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 420 [SCPCR] = sci_reg_invalid,
421 [SCPDR] = sci_reg_invalid,
b8bbd6b2
GU		 422 [SCDL] = sci_reg_invalid,
423 [SCCKS] = sci_reg_invalid,
61a6976b
PM		 424 },
425
426 /*
427 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR
428 * registers.
429 */
430 [SCIx_SH7705_SCIF_REGTYPE] = {
431 [SCSMR] = { 0x00, 16 },
432 [SCBRR] = { 0x04, 8 },
433 [SCSCR] = { 0x08, 16 },
434 [SCxTDR] = { 0x20, 8 },
435 [SCxSR] = { 0x14, 16 },
436 [SCxRDR] = { 0x24, 8 },
437 [SCFCR] = { 0x18, 16 },
438 [SCFDR] = { 0x1c, 16 },
439 [SCTFDR] = sci_reg_invalid,
440 [SCRFDR] = sci_reg_invalid,
441 [SCSPTR] = sci_reg_invalid,
442 [SCLSR] = sci_reg_invalid,
f303b364 443 [HSSRR] = sci_reg_invalid,
c097abc3
GU		 444 [SCPCR] = sci_reg_invalid,
445 [SCPDR] = sci_reg_invalid,
b8bbd6b2
GU		 446 [SCDL] = sci_reg_invalid,
447 [SCCKS] = sci_reg_invalid,
61a6976b
PM		 448 },
449};
450
72b294cf
PM		 451#define sci_getreg(up, offset) (sci_regmap[to_sci_port(up)->cfg->regtype] + offset)
452
61a6976b
PM		 453/*
454 * The "offset" here is rather misleading, in that it refers to an enum
455 * value relative to the port mapping rather than the fixed offset
456 * itself, which needs to be manually retrieved from the platform's
457 * register map for the given port.
458 */
459static unsigned int sci_serial_in(struct uart_port *p, int offset)
460{
d3184e68 461 const struct plat_sci_reg *reg = sci_getreg(p, offset);
61a6976b
PM		 462
463 if (reg->size == 8)
464 return ioread8(p->membase + (reg->offset << p->regshift));
465 else if (reg->size == 16)
466 return ioread16(p->membase + (reg->offset << p->regshift));
467 else
468 WARN(1, "Invalid register access\n");
469
470 return 0;
471}
472
473static void sci_serial_out(struct uart_port *p, int offset, int value)
474{
d3184e68 475 const struct plat_sci_reg *reg = sci_getreg(p, offset);
61a6976b
PM		 476
477 if (reg->size == 8)
478 iowrite8(value, p->membase + (reg->offset << p->regshift));
479 else if (reg->size == 16)
480 iowrite16(value, p->membase + (reg->offset << p->regshift));
481 else
482 WARN(1, "Invalid register access\n");
483}
484
61a6976b
PM		 485static int sci_probe_regmap(struct plat_sci_port *cfg)
486{
487 switch (cfg->type) {
488 case PORT_SCI:
489 cfg->regtype = SCIx_SCI_REGTYPE;
490 break;
491 case PORT_IRDA:
492 cfg->regtype = SCIx_IRDA_REGTYPE;
493 break;
494 case PORT_SCIFA:
495 cfg->regtype = SCIx_SCIFA_REGTYPE;
496 break;
497 case PORT_SCIFB:
498 cfg->regtype = SCIx_SCIFB_REGTYPE;
499 break;
500 case PORT_SCIF:
501 /*
502 * The SH-4 is a bit of a misnomer here, although that's
503 * where this particular port layout originated. This
504 * configuration (or some slight variation thereof)
505 * remains the dominant model for all SCIFs.
506 */
507 cfg->regtype = SCIx_SH4_SCIF_REGTYPE;
508 break;
f303b364
UH		 509 case PORT_HSCIF:
510 cfg->regtype = SCIx_HSCIF_REGTYPE;
511 break;
61a6976b 512 default:
6c13d5d2 513 pr_err("Can't probe register map for given port\n");
61a6976b
PM		 514 return -EINVAL;
515 }
516
517 return 0;
518}
519
23241d43
PM		 520static void sci_port_enable(struct sci_port *sci_port)
521{
f4998e55
GU		 522 unsigned int i;
523
23241d43
PM		 524 if (!sci_port->port.dev)
525 return;
526
527 pm_runtime_get_sync(sci_port->port.dev);
528
f4998e55
GU		 529 for (i = 0; i < SCI_NUM_CLKS; i++) {
530 clk_prepare_enable(sci_port->clks[i]);
531 sci_port->clk_rates[i] = clk_get_rate(sci_port->clks[i]);
532 }
533 sci_port->port.uartclk = sci_port->clk_rates[SCI_FCK];
23241d43
PM		 534}
535
536static void sci_port_disable(struct sci_port *sci_port)
537{
f4998e55
GU		 538 unsigned int i;
539
23241d43
PM		 540 if (!sci_port->port.dev)
541 return;
542
caec7038
LP		 543 /* Cancel the break timer to ensure that the timer handler will not try
544 * to access the hardware with clocks and power disabled. Reset the
545 * break flag to make the break debouncing state machine ready for the
546 * next break.
547 */
548 del_timer_sync(&sci_port->break_timer);
549 sci_port->break_flag = 0;
550
f4998e55
GU		 551 for (i = SCI_NUM_CLKS; i-- > 0; )
552 clk_disable_unprepare(sci_port->clks[i]);
23241d43
PM		 553
554 pm_runtime_put_sync(sci_port->port.dev);
555}
556
e1910fcd
GU		 557static inline unsigned long port_rx_irq_mask(struct uart_port *port)
558{
559 /*
560 * Not all ports (such as SCIFA) will support REIE. Rather than
561 * special-casing the port type, we check the port initialization
562 * IRQ enable mask to see whether the IRQ is desired at all. If
563 * it's unset, it's logically inferred that there's no point in
564 * testing for it.
565 */
566 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE);
567}
568
569static void sci_start_tx(struct uart_port *port)
570{
571 struct sci_port *s = to_sci_port(port);
572 unsigned short ctrl;
573
574#ifdef CONFIG_SERIAL_SH_SCI_DMA
575 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
576 u16 new, scr = serial_port_in(port, SCSCR);
577 if (s->chan_tx)
578 new = scr | SCSCR_TDRQE;
579 else
580 new = scr & ~SCSCR_TDRQE;
581 if (new != scr)
582 serial_port_out(port, SCSCR, new);
583 }
584
585 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) &&
586 dma_submit_error(s->cookie_tx)) {
587 s->cookie_tx = 0;
588 schedule_work(&s->work_tx);
589 }
590#endif
591
592 if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
593 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
594 ctrl = serial_port_in(port, SCSCR);
595 serial_port_out(port, SCSCR, ctrl | SCSCR_TIE);
596 }
597}
598
599static void sci_stop_tx(struct uart_port *port)
600{
601 unsigned short ctrl;
602
603 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
604 ctrl = serial_port_in(port, SCSCR);
605
606 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
607 ctrl &= ~SCSCR_TDRQE;
608
609 ctrl &= ~SCSCR_TIE;
610
611 serial_port_out(port, SCSCR, ctrl);
612}
613
614static void sci_start_rx(struct uart_port *port)
615{
616 unsigned short ctrl;
617
618 ctrl = serial_port_in(port, SCSCR) | port_rx_irq_mask(port);
619
620 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
621 ctrl &= ~SCSCR_RDRQE;
622
623 serial_port_out(port, SCSCR, ctrl);
624}
625
626static void sci_stop_rx(struct uart_port *port)
627{
628 unsigned short ctrl;
629
630 ctrl = serial_port_in(port, SCSCR);
631
632 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
633 ctrl &= ~SCSCR_RDRQE;
634
635 ctrl &= ~port_rx_irq_mask(port);
636
637 serial_port_out(port, SCSCR, ctrl);
638}
639
a1b5b43f
GU		 640static void sci_clear_SCxSR(struct uart_port *port, unsigned int mask)
641{
642 if (port->type == PORT_SCI) {
643 /* Just store the mask */
644 serial_port_out(port, SCxSR, mask);
645 } else if (to_sci_port(port)->overrun_mask == SCIFA_ORER) {
646 /* SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721 */
647 /* Only clear the status bits we want to clear */
648 serial_port_out(port, SCxSR,
649 serial_port_in(port, SCxSR) & mask);
650 } else {
651 /* Store the mask, clear parity/framing errors */
652 serial_port_out(port, SCxSR, mask & ~(SCIF_FERC | SCIF_PERC));
653 }
654}
655
0b0cced1
YS		 656#if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \
657 defined(CONFIG_SERIAL_SH_SCI_EARLYCON)
1f6fd5c9
PM		 658
659#ifdef CONFIG_CONSOLE_POLL
07d2a1a1 660static int sci_poll_get_char(struct uart_port *port)
1da177e4 661{
1da177e4
LT		 662 unsigned short status;
663 int c;
664
e108b2ca 665 do {
b12bb29f 666 status = serial_port_in(port, SCxSR);
1da177e4 667 if (status & SCxSR_ERRORS(port)) {
a1b5b43f 668 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
1da177e4
LT		 669 continue;
670 }
3f255eb3
JW		 671 break;
672 } while (1);
673
674 if (!(status & SCxSR_RDxF(port)))
675 return NO_POLL_CHAR;
07d2a1a1 676
b12bb29f 677 c = serial_port_in(port, SCxRDR);
07d2a1a1 678
e7c98dc7 679 /* Dummy read */
b12bb29f 680 serial_port_in(port, SCxSR);
a1b5b43f 681 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1da177e4
LT		 682
683 return c;
684}
1f6fd5c9 685#endif
1da177e4 686
07d2a1a1 687static void sci_poll_put_char(struct uart_port *port, unsigned char c)
1da177e4 688{
1da177e4
LT		 689 unsigned short status;
690
1da177e4 691 do {
b12bb29f 692 status = serial_port_in(port, SCxSR);
1da177e4
LT		 693 } while (!(status & SCxSR_TDxE(port)));
694
b12bb29f 695 serial_port_out(port, SCxTDR, c);
a1b5b43f 696 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
1da177e4 697}
0b0cced1
YS		 698#endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE ||
699 CONFIG_SERIAL_SH_SCI_EARLYCON */
1da177e4 700
61a6976b 701static void sci_init_pins(struct uart_port *port, unsigned int cflag)
1da177e4 702{
61a6976b 703 struct sci_port *s = to_sci_port(port);
d3184e68 704 const struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR;
1da177e4 705
61a6976b
PM		 706 /*
707 * Use port-specific handler if provided.
708 */
709 if (s->cfg->ops && s->cfg->ops->init_pins) {
710 s->cfg->ops->init_pins(port, cflag);
711 return;
1da177e4 712 }
41504c39 713
61a6976b
PM		 714 /*
715 * For the generic path SCSPTR is necessary. Bail out if that's
716 * unavailable, too.
717 */
718 if (!reg->size)
719 return;
41504c39 720
faf02f8f
PM		 721 if ((s->cfg->capabilities & SCIx_HAVE_RTSCTS) &&
722 ((!(cflag & CRTSCTS)))) {
723 unsigned short status;
724
b12bb29f 725 status = serial_port_in(port, SCSPTR);
faf02f8f
PM		 726 status &= ~SCSPTR_CTSIO;
727 status |= SCSPTR_RTSIO;
b12bb29f 728 serial_port_out(port, SCSPTR, status); /* Set RTS = 1 */
faf02f8f 729 }
d5701647 730}
e108b2ca 731
72b294cf 732static int sci_txfill(struct uart_port *port)
e108b2ca 733{
d3184e68 734 const struct plat_sci_reg *reg;
e108b2ca 735
72b294cf
PM		 736 reg = sci_getreg(port, SCTFDR);
737 if (reg->size)
63f7ad11 738 return serial_port_in(port, SCTFDR) & ((port->fifosize << 1) - 1);
c63847a3 739
72b294cf
PM		 740 reg = sci_getreg(port, SCFDR);
741 if (reg->size)
b12bb29f 742 return serial_port_in(port, SCFDR) >> 8;
d1d4b10c 743
b12bb29f 744 return !(serial_port_in(port, SCxSR) & SCI_TDRE);
e108b2ca
PM		 745}
746
73a19e4c
GL		 747static int sci_txroom(struct uart_port *port)
748{
72b294cf 749 return port->fifosize - sci_txfill(port);
73a19e4c
GL		 750}
751
752static int sci_rxfill(struct uart_port *port)
e108b2ca 753{
d3184e68 754 const struct plat_sci_reg *reg;
72b294cf
PM		 755
756 reg = sci_getreg(port, SCRFDR);
757 if (reg->size)
63f7ad11 758 return serial_port_in(port, SCRFDR) & ((port->fifosize << 1) - 1);
72b294cf
PM		 759
760 reg = sci_getreg(port, SCFDR);
761 if (reg->size)
b12bb29f 762 return serial_port_in(port, SCFDR) & ((port->fifosize << 1) - 1);
72b294cf 763
b12bb29f 764 return (serial_port_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
e108b2ca
PM		 765}
766
514820eb
PM		 767/*
768 * SCI helper for checking the state of the muxed port/RXD pins.
769 */
770static inline int sci_rxd_in(struct uart_port *port)
771{
772 struct sci_port *s = to_sci_port(port);
773
774 if (s->cfg->port_reg <= 0)
775 return 1;
776
0dd4d5cb 777 /* Cast for ARM damage */
e2afca69 778 return !!__raw_readb((void __iomem *)(uintptr_t)s->cfg->port_reg);
514820eb
PM		 779}
780
1da177e4
LT		 781/* ********************************************************************** *
782 * the interrupt related routines *
783 * ********************************************************************** */
784
785static void sci_transmit_chars(struct uart_port *port)
786{
ebd2c8f6 787 struct circ_buf *xmit = &port->state->xmit;
1da177e4 788 unsigned int stopped = uart_tx_stopped(port);
1da177e4
LT		 789 unsigned short status;
790 unsigned short ctrl;
e108b2ca 791 int count;
1da177e4 792
b12bb29f 793 status = serial_port_in(port, SCxSR);
1da177e4 794 if (!(status & SCxSR_TDxE(port))) {
b12bb29f 795 ctrl = serial_port_in(port, SCSCR);
e7c98dc7 796 if (uart_circ_empty(xmit))
8e698614 797 ctrl &= ~SCSCR_TIE;
e7c98dc7 798 else
8e698614 799 ctrl |= SCSCR_TIE;
b12bb29f 800 serial_port_out(port, SCSCR, ctrl);
1da177e4
LT		 801 return;
802 }
803
72b294cf 804 count = sci_txroom(port);
1da177e4
LT		 805
806 do {
807 unsigned char c;
808
809 if (port->x_char) {
810 c = port->x_char;
811 port->x_char = 0;
812 } else if (!uart_circ_empty(xmit) && !stopped) {
813 c = xmit->buf[xmit->tail];
814 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
815 } else {
816 break;
817 }
818
b12bb29f 819 serial_port_out(port, SCxTDR, c);
1da177e4
LT		 820
821 port->icount.tx++;
822 } while (--count > 0);
823
a1b5b43f 824 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
1da177e4
LT		 825
826 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
827 uart_write_wakeup(port);
828 if (uart_circ_empty(xmit)) {
b129a8cc 829 sci_stop_tx(port);
1da177e4 830 } else {
b12bb29f 831 ctrl = serial_port_in(port, SCSCR);
1da177e4 832
1a22f08d 833 if (port->type != PORT_SCI) {
b12bb29f 834 serial_port_in(port, SCxSR); /* Dummy read */
a1b5b43f 835 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
1da177e4 836 }
1da177e4 837
8e698614 838 ctrl |= SCSCR_TIE;
b12bb29f 839 serial_port_out(port, SCSCR, ctrl);
1da177e4
LT		 840 }
841}
842
843/* On SH3, SCIF may read end-of-break as a space->mark char */
e7c98dc7 844#define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); })
1da177e4 845
94c8b6db 846static void sci_receive_chars(struct uart_port *port)
1da177e4 847{
e7c98dc7 848 struct sci_port *sci_port = to_sci_port(port);
227434f8 849 struct tty_port *tport = &port->state->port;
1da177e4
LT		 850 int i, count, copied = 0;
851 unsigned short status;
33f0f88f 852 unsigned char flag;
1da177e4 853
b12bb29f 854 status = serial_port_in(port, SCxSR);
1da177e4
LT		 855 if (!(status & SCxSR_RDxF(port)))
856 return;
857
858 while (1) {
1da177e4 859 /* Don't copy more bytes than there is room for in the buffer */
227434f8 860 count = tty_buffer_request_room(tport, sci_rxfill(port));
1da177e4
LT		 861
862 /* If for any reason we can't copy more data, we're done! */
863 if (count == 0)
864 break;
865
866 if (port->type == PORT_SCI) {
b12bb29f 867 char c = serial_port_in(port, SCxRDR);
e7c98dc7
MT		 868 if (uart_handle_sysrq_char(port, c) ||
869 sci_port->break_flag)
1da177e4 870 count = 0;
e7c98dc7 871 else
92a19f9c 872 tty_insert_flip_char(tport, c, TTY_NORMAL);
1da177e4 873 } else {
e7c98dc7 874 for (i = 0; i < count; i++) {
b12bb29f 875 char c = serial_port_in(port, SCxRDR);
d97fbbed 876
b12bb29f 877 status = serial_port_in(port, SCxSR);
1da177e4
LT		 878#if defined(CONFIG_CPU_SH3)
879 /* Skip "chars" during break */
e108b2ca 880 if (sci_port->break_flag) {
1da177e4
LT		 881 if ((c == 0) &&
882 (status & SCxSR_FER(port))) {
883 count--; i--;
884 continue;
885 }
e108b2ca 886
1da177e4 887 /* Nonzero => end-of-break */
762c69e3 888 dev_dbg(port->dev, "debounce<%02x>\n", c);
e108b2ca
PM		 889 sci_port->break_flag = 0;
890
1da177e4
LT		 891 if (STEPFN(c)) {
892 count--; i--;
893 continue;
894 }
895 }
896#endif /* CONFIG_CPU_SH3 */
7d12e780 897 if (uart_handle_sysrq_char(port, c)) {
1da177e4
LT		 898 count--; i--;
899 continue;
900 }
901
902 /* Store data and status */
73a19e4c 903 if (status & SCxSR_FER(port)) {
33f0f88f 904 flag = TTY_FRAME;
d97fbbed 905 port->icount.frame++;
762c69e3 906 dev_notice(port->dev, "frame error\n");
73a19e4c 907 } else if (status & SCxSR_PER(port)) {
33f0f88f 908 flag = TTY_PARITY;
d97fbbed 909 port->icount.parity++;
762c69e3 910 dev_notice(port->dev, "parity error\n");
33f0f88f
AC		 911 } else
912 flag = TTY_NORMAL;
762c69e3 913
92a19f9c 914 tty_insert_flip_char(tport, c, flag);
1da177e4
LT		 915 }
916 }
917
b12bb29f 918 serial_port_in(port, SCxSR); /* dummy read */
a1b5b43f 919 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1da177e4 920
1da177e4
LT		 921 copied += count;
922 port->icount.rx += count;
923 }
924
925 if (copied) {
926 /* Tell the rest of the system the news. New characters! */
2e124b4a 927 tty_flip_buffer_push(tport);
1da177e4 928 } else {
b12bb29f 929 serial_port_in(port, SCxSR); /* dummy read */
a1b5b43f 930 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1da177e4
LT		 931 }
932}
933
934#define SCI_BREAK_JIFFIES (HZ/20)
94c8b6db
PM		 935
936/*
937 * The sci generates interrupts during the break,
1da177e4
LT		 938 * 1 per millisecond or so during the break period, for 9600 baud.
939 * So dont bother disabling interrupts.
940 * But dont want more than 1 break event.
941 * Use a kernel timer to periodically poll the rx line until
942 * the break is finished.
943 */
94c8b6db 944static inline void sci_schedule_break_timer(struct sci_port *port)
1da177e4 945{
bc9b3f5c 946 mod_timer(&port->break_timer, jiffies + SCI_BREAK_JIFFIES);
1da177e4 947}
94c8b6db 948
1da177e4
LT		 949/* Ensure that two consecutive samples find the break over. */
950static void sci_break_timer(unsigned long data)
951{
e108b2ca
PM		 952 struct sci_port *port = (struct sci_port *)data;
953
954 if (sci_rxd_in(&port->port) == 0) {
1da177e4 955 port->break_flag = 1;
e108b2ca
PM		 956 sci_schedule_break_timer(port);
957 } else if (port->break_flag == 1) {
1da177e4
LT		 958 /* break is over. */
959 port->break_flag = 2;
e108b2ca
PM		 960 sci_schedule_break_timer(port);
961 } else
962 port->break_flag = 0;
1da177e4
LT		 963}
964
94c8b6db 965static int sci_handle_errors(struct uart_port *port)
1da177e4
LT		 966{
967 int copied = 0;
b12bb29f 968 unsigned short status = serial_port_in(port, SCxSR);
92a19f9c 969 struct tty_port *tport = &port->state->port;
debf9507 970 struct sci_port *s = to_sci_port(port);
1da177e4 971
3ae988d9 972 /* Handle overruns */
75c249fd 973 if (status & s->overrun_mask) {
3ae988d9 974 port->icount.overrun++;
d97fbbed 975
3ae988d9
LP		 976 /* overrun error */
977 if (tty_insert_flip_char(tport, 0, TTY_OVERRUN))
978 copied++;
762c69e3 979
9b971cd2 980 dev_notice(port->dev, "overrun error\n");
1da177e4
LT		 981 }
982
e108b2ca 983 if (status & SCxSR_FER(port)) {
1da177e4
LT		 984 if (sci_rxd_in(port) == 0) {
985 /* Notify of BREAK */
e7c98dc7 986 struct sci_port *sci_port = to_sci_port(port);
e108b2ca
PM		 987
988 if (!sci_port->break_flag) {
d97fbbed
PM		 989 port->icount.brk++;
990
e108b2ca
PM		 991 sci_port->break_flag = 1;
992 sci_schedule_break_timer(sci_port);
993
1da177e4 994 /* Do sysrq handling. */
e108b2ca 995 if (uart_handle_break(port))
1da177e4 996 return 0;
762c69e3
PM		 997
998 dev_dbg(port->dev, "BREAK detected\n");
999
92a19f9c 1000 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
e7c98dc7
MT		 1001 copied++;
1002 }
1003
e108b2ca 1004 } else {
1da177e4 1005 /* frame error */
d97fbbed
PM		 1006 port->icount.frame++;
1007
92a19f9c 1008 if (tty_insert_flip_char(tport, 0, TTY_FRAME))
33f0f88f 1009 copied++;
762c69e3
PM		 1010
1011 dev_notice(port->dev, "frame error\n");
1da177e4
LT		 1012 }
1013 }
1014
e108b2ca 1015 if (status & SCxSR_PER(port)) {
1da177e4 1016 /* parity error */
d97fbbed
PM		 1017 port->icount.parity++;
1018
92a19f9c 1019 if (tty_insert_flip_char(tport, 0, TTY_PARITY))
e108b2ca 1020 copied++;
762c69e3 1021
9b971cd2 1022 dev_notice(port->dev, "parity error\n");
1da177e4
LT		 1023 }
1024
33f0f88f 1025 if (copied)
2e124b4a 1026 tty_flip_buffer_push(tport);
1da177e4
LT		 1027
1028 return copied;
1029}
1030
94c8b6db 1031static int sci_handle_fifo_overrun(struct uart_port *port)
d830fa45 1032{
92a19f9c 1033 struct tty_port *tport = &port->state->port;
debf9507 1034 struct sci_port *s = to_sci_port(port);
d3184e68 1035 const struct plat_sci_reg *reg;
2e0842a1 1036 int copied = 0;
75c249fd 1037 u16 status;
d830fa45 1038
2e0842a1 1039 reg = sci_getreg(port, s->overrun_reg);
4b8c59a3 1040 if (!reg->size)
d830fa45
PM		 1041 return 0;
1042
2e0842a1 1043 status = serial_port_in(port, s->overrun_reg);
75c249fd
GU		 1044 if (status & s->overrun_mask) {
1045 status &= ~s->overrun_mask;
2e0842a1 1046 serial_port_out(port, s->overrun_reg, status);
d830fa45 1047
d97fbbed
PM		 1048 port->icount.overrun++;
1049
92a19f9c 1050 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
2e124b4a 1051 tty_flip_buffer_push(tport);
d830fa45 1052
51b31f1c 1053 dev_dbg(port->dev, "overrun error\n");
d830fa45
PM		 1054 copied++;
1055 }
1056
1057 return copied;
1058}
1059
94c8b6db 1060static int sci_handle_breaks(struct uart_port *port)
1da177e4
LT		 1061{
1062 int copied = 0;
b12bb29f 1063 unsigned short status = serial_port_in(port, SCxSR);
92a19f9c 1064 struct tty_port *tport = &port->state->port;
a5660ada 1065 struct sci_port *s = to_sci_port(port);
1da177e4 1066
0b3d4ef6
PM		 1067 if (uart_handle_break(port))
1068 return 0;
1069
b7a76e4b 1070 if (!s->break_flag && status & SCxSR_BRK(port)) {
1da177e4
LT		 1071#if defined(CONFIG_CPU_SH3)
1072 /* Debounce break */
1073 s->break_flag = 1;
1074#endif
d97fbbed
PM		 1075
1076 port->icount.brk++;
1077
1da177e4 1078 /* Notify of BREAK */
92a19f9c 1079 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
33f0f88f 1080 copied++;
762c69e3
PM		 1081
1082 dev_dbg(port->dev, "BREAK detected\n");
1da177e4
LT		 1083 }
1084
33f0f88f 1085 if (copied)
2e124b4a 1086 tty_flip_buffer_push(tport);
e108b2ca 1087
d830fa45
PM		 1088 copied += sci_handle_fifo_overrun(port);
1089
1da177e4
LT		 1090 return copied;
1091}
1092
73a19e4c 1093#ifdef CONFIG_SERIAL_SH_SCI_DMA
e1910fcd
GU		 1094static void sci_dma_tx_complete(void *arg)
1095{
1096 struct sci_port *s = arg;
1097 struct uart_port *port = &s->port;
1098 struct circ_buf *xmit = &port->state->xmit;
1099 unsigned long flags;
73a19e4c 1100
e1910fcd 1101 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
73a19e4c 1102
e1910fcd 1103 spin_lock_irqsave(&port->lock, flags);
73a19e4c 1104
e1910fcd
GU		 1105 xmit->tail += s->tx_dma_len;
1106 xmit->tail &= UART_XMIT_SIZE - 1;
73a19e4c 1107
e1910fcd 1108 port->icount.tx += s->tx_dma_len;
1da177e4 1109
e1910fcd
GU		 1110 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1111 uart_write_wakeup(port);
1da177e4 1112
e1910fcd
GU		 1113 if (!uart_circ_empty(xmit)) {
1114 s->cookie_tx = 0;
1115 schedule_work(&s->work_tx);
1116 } else {
1117 s->cookie_tx = -EINVAL;
1118 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1119 u16 ctrl = serial_port_in(port, SCSCR);
1120 serial_port_out(port, SCSCR, ctrl & ~SCSCR_TIE);
1121 }
1122 }
1da177e4 1123
fd78a76a 1124 spin_unlock_irqrestore(&port->lock, flags);
1da177e4
LT		 1125}
1126
e1910fcd
GU		 1127/* Locking: called with port lock held */
1128static int sci_dma_rx_push(struct sci_port *s, void *buf, size_t count)
1da177e4 1129{
e1910fcd
GU		 1130 struct uart_port *port = &s->port;
1131 struct tty_port *tport = &port->state->port;
1132 int copied;
1da177e4 1133
e1910fcd
GU		 1134 copied = tty_insert_flip_string(tport, buf, count);
1135 if (copied < count) {
1136 dev_warn(port->dev, "Rx overrun: dropping %zu bytes\n",
1137 count - copied);
1138 port->icount.buf_overrun++;
1da177e4
LT		 1139 }
1140
e1910fcd 1141 port->icount.rx += copied;
1da177e4 1142
e1910fcd 1143 return copied;
1da177e4
LT		 1144}
1145
e1910fcd 1146static int sci_dma_rx_find_active(struct sci_port *s)
1da177e4 1147{
e1910fcd 1148 unsigned int i;
1da177e4 1149
e1910fcd
GU		 1150 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++)
1151 if (s->active_rx == s->cookie_rx[i])
1152 return i;
1da177e4 1153
e1910fcd
GU		 1154 dev_err(s->port.dev, "%s: Rx cookie %d not found!\n", __func__,
1155 s->active_rx);
1156 return -1;
1da177e4
LT		 1157}
1158
e1910fcd 1159static void sci_rx_dma_release(struct sci_port *s, bool enable_pio)
f43dc23d 1160{
e1910fcd
GU		 1161 struct dma_chan *chan = s->chan_rx;
1162 struct uart_port *port = &s->port;
1163 unsigned long flags;
1164
1165 spin_lock_irqsave(&port->lock, flags);
1166 s->chan_rx = NULL;
1167 s->cookie_rx[0] = s->cookie_rx[1] = -EINVAL;
1168 spin_unlock_irqrestore(&port->lock, flags);
1169 dmaengine_terminate_all(chan);
1170 dma_free_coherent(chan->device->dev, s->buf_len_rx * 2, s->rx_buf[0],
1171 sg_dma_address(&s->sg_rx[0]));
1172 dma_release_channel(chan);
1173 if (enable_pio)
1174 sci_start_rx(port);
f43dc23d
PM		 1175}
1176
e1910fcd 1177static void sci_dma_rx_complete(void *arg)
1da177e4 1178{
e1910fcd 1179 struct sci_port *s = arg;
1d3db608 1180 struct dma_chan *chan = s->chan_rx;
e1910fcd 1181 struct uart_port *port = &s->port;
67f462b0 1182 struct dma_async_tx_descriptor *desc;
e1910fcd
GU		 1183 unsigned long flags;
1184 int active, count = 0;
1da177e4 1185
e1910fcd
GU		 1186 dev_dbg(port->dev, "%s(%d) active cookie %d\n", __func__, port->line,
1187 s->active_rx);
cb772fe7 1188
e1910fcd 1189 spin_lock_irqsave(&port->lock, flags);
1da177e4 1190
e1910fcd
GU		 1191 active = sci_dma_rx_find_active(s);
1192 if (active >= 0)
1193 count = sci_dma_rx_push(s, s->rx_buf[active], s->buf_len_rx);
f43dc23d 1194
e1910fcd 1195 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
f43dc23d 1196
e1910fcd
GU		 1197 if (count)
1198 tty_flip_buffer_push(&port->state->port);
8b6ff84c 1199
67f462b0
GU		 1200 desc = dmaengine_prep_slave_sg(s->chan_rx, &s->sg_rx[active], 1,
1201 DMA_DEV_TO_MEM,
1202 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1203 if (!desc)
1204 goto fail;
1205
1206 desc->callback = sci_dma_rx_complete;
1207 desc->callback_param = s;
1208 s->cookie_rx[active] = dmaengine_submit(desc);
1209 if (dma_submit_error(s->cookie_rx[active]))
1210 goto fail;
1211
1212 s->active_rx = s->cookie_rx[!active];
1213
1d3db608
MHF		 1214 dma_async_issue_pending(chan);
1215
67f462b0
GU		 1216 dev_dbg(port->dev, "%s: cookie %d #%d, new active cookie %d\n",
1217 __func__, s->cookie_rx[active], active, s->active_rx);
1218 spin_unlock_irqrestore(&port->lock, flags);
1219 return;
1220
1221fail:
1222 spin_unlock_irqrestore(&port->lock, flags);
1223 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
1224 sci_rx_dma_release(s, true);
1da177e4
LT		 1225}
1226
e1910fcd 1227static void sci_tx_dma_release(struct sci_port *s, bool enable_pio)
1da177e4 1228{
e1910fcd
GU		 1229 struct dma_chan *chan = s->chan_tx;
1230 struct uart_port *port = &s->port;
e552de24 1231 unsigned long flags;
1da177e4 1232
e1910fcd
GU		 1233 spin_lock_irqsave(&port->lock, flags);
1234 s->chan_tx = NULL;
1235 s->cookie_tx = -EINVAL;
1236 spin_unlock_irqrestore(&port->lock, flags);
1237 dmaengine_terminate_all(chan);
1238 dma_unmap_single(chan->device->dev, s->tx_dma_addr, UART_XMIT_SIZE,
1239 DMA_TO_DEVICE);
1240 dma_release_channel(chan);
1241 if (enable_pio)
1242 sci_start_tx(port);
1243}
d535a230 1244
e1910fcd
GU		 1245static void sci_submit_rx(struct sci_port *s)
1246{
1247 struct dma_chan *chan = s->chan_rx;
1248 int i;
073e84c9 1249
e1910fcd
GU		 1250 for (i = 0; i < 2; i++) {
1251 struct scatterlist *sg = &s->sg_rx[i];
1252 struct dma_async_tx_descriptor *desc;
1da177e4 1253
e1910fcd
GU		 1254 desc = dmaengine_prep_slave_sg(chan,
1255 sg, 1, DMA_DEV_TO_MEM,
1256 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1257 if (!desc)
1258 goto fail;
501b825d 1259
e1910fcd
GU		 1260 desc->callback = sci_dma_rx_complete;
1261 desc->callback_param = s;
1262 s->cookie_rx[i] = dmaengine_submit(desc);
1263 if (dma_submit_error(s->cookie_rx[i]))
1264 goto fail;
9174fc8f 1265
e1910fcd
GU		 1266 dev_dbg(s->port.dev, "%s(): cookie %d to #%d\n", __func__,
1267 s->cookie_rx[i], i);
1268 }
9174fc8f 1269
e1910fcd 1270 s->active_rx = s->cookie_rx[0];
9174fc8f 1271
e1910fcd
GU		 1272 dma_async_issue_pending(chan);
1273 return;
9174fc8f 1274
e1910fcd
GU		 1275fail:
1276 if (i)
1277 dmaengine_terminate_all(chan);
1278 for (i = 0; i < 2; i++)
1279 s->cookie_rx[i] = -EINVAL;
1280 s->active_rx = -EINVAL;
1281 dev_warn(s->port.dev, "Failed to re-start Rx DMA, using PIO\n");
1282 sci_rx_dma_release(s, true);
1283}
9174fc8f 1284
e1910fcd 1285static void work_fn_tx(struct work_struct *work)
1da177e4 1286{
e1910fcd
GU		 1287 struct sci_port *s = container_of(work, struct sci_port, work_tx);
1288 struct dma_async_tx_descriptor *desc;
1289 struct dma_chan *chan = s->chan_tx;
1290 struct uart_port *port = &s->port;
1291 struct circ_buf *xmit = &port->state->xmit;
1292 dma_addr_t buf;
1da177e4 1293
9174fc8f 1294 /*
e1910fcd
GU		 1295 * DMA is idle now.
1296 * Port xmit buffer is already mapped, and it is one page... Just adjust
1297 * offsets and lengths. Since it is a circular buffer, we have to
1298 * transmit till the end, and then the rest. Take the port lock to get a
1299 * consistent xmit buffer state.
9174fc8f 1300 */
e1910fcd
GU		 1301 spin_lock_irq(&port->lock);
1302 buf = s->tx_dma_addr + (xmit->tail & (UART_XMIT_SIZE - 1));
1303 s->tx_dma_len = min_t(unsigned int,
1304 CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE),
1305 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE));
1306 spin_unlock_irq(&port->lock);
0e8963de 1307
e1910fcd
GU		 1308 desc = dmaengine_prep_slave_single(chan, buf, s->tx_dma_len,
1309 DMA_MEM_TO_DEV,
1310 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1311 if (!desc) {
1312 dev_warn(port->dev, "Failed preparing Tx DMA descriptor\n");
1313 /* switch to PIO */
1314 sci_tx_dma_release(s, true);
1315 return;
1316 }
0e8963de 1317
e1910fcd
GU		 1318 dma_sync_single_for_device(chan->device->dev, buf, s->tx_dma_len,
1319 DMA_TO_DEVICE);
1da177e4 1320
e1910fcd
GU		 1321 spin_lock_irq(&port->lock);
1322 desc->callback = sci_dma_tx_complete;
1323 desc->callback_param = s;
1324 spin_unlock_irq(&port->lock);
1325 s->cookie_tx = dmaengine_submit(desc);
1326 if (dma_submit_error(s->cookie_tx)) {
1327 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
1328 /* switch to PIO */
1329 sci_tx_dma_release(s, true);
1330 return;
1da177e4 1331 }
1da177e4 1332
e1910fcd
GU		 1333 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n",
1334 __func__, xmit->buf, xmit->tail, xmit->head, s->cookie_tx);
73a19e4c 1335
e1910fcd 1336 dma_async_issue_pending(chan);
1da177e4
LT		 1337}
1338
e1910fcd 1339static void rx_timer_fn(unsigned long arg)
1da177e4 1340{
e1910fcd 1341 struct sci_port *s = (struct sci_port *)arg;
e7327c09 1342 struct dma_chan *chan = s->chan_rx;
e1910fcd 1343 struct uart_port *port = &s->port;
67f462b0
GU		 1344 struct dma_tx_state state;
1345 enum dma_status status;
1346 unsigned long flags;
1347 unsigned int read;
1348 int active, count;
1349 u16 scr;
1350
1351 spin_lock_irqsave(&port->lock, flags);
e1910fcd 1352
67f462b0 1353 dev_dbg(port->dev, "DMA Rx timed out\n");
67f462b0
GU		 1354
1355 active = sci_dma_rx_find_active(s);
1356 if (active < 0) {
1357 spin_unlock_irqrestore(&port->lock, flags);
1358 return;
1359 }
1360
1361 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
3b963042 1362 if (status == DMA_COMPLETE) {
67f462b0
GU		 1363 dev_dbg(port->dev, "Cookie %d #%d has already completed\n",
1364 s->active_rx, active);
3b963042
MHF		 1365 spin_unlock_irqrestore(&port->lock, flags);
1366
1367 /* Let packet complete handler take care of the packet */
1368 return;
1369 }
67f462b0 1370
e7327c09
MHF		 1371 dmaengine_pause(chan);
1372
1373 /*
1374 * sometimes DMA transfer doesn't stop even if it is stopped and
1375 * data keeps on coming until transaction is complete so check
1376 * for DMA_COMPLETE again
1377 * Let packet complete handler take care of the packet
1378 */
1379 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
1380 if (status == DMA_COMPLETE) {
1381 spin_unlock_irqrestore(&port->lock, flags);
1382 dev_dbg(port->dev, "Transaction complete after DMA engine was stopped");
1383 return;
1384 }
1385
67f462b0
GU		 1386 /* Handle incomplete DMA receive */
1387 dmaengine_terminate_all(s->chan_rx);
1388 read = sg_dma_len(&s->sg_rx[active]) - state.residue;
1389 dev_dbg(port->dev, "Read %u bytes with cookie %d\n", read,
1390 s->active_rx);
1391
1392 if (read) {
1393 count = sci_dma_rx_push(s, s->rx_buf[active], read);
1394 if (count)
1395 tty_flip_buffer_push(&port->state->port);
1396 }
1397
756981be
GU		 1398 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1399 sci_submit_rx(s);
371cfed3
MHF		 1400
1401 /* Direct new serial port interrupts back to CPU */
1402 scr = serial_port_in(port, SCSCR);
1403 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1404 scr &= ~SCSCR_RDRQE;
1405 enable_irq(s->irqs[SCIx_RXI_IRQ]);
1406 }
1407 serial_port_out(port, SCSCR, scr | SCSCR_RIE);
1408
1409 spin_unlock_irqrestore(&port->lock, flags);
1da177e4
LT		 1410}
1411
ff441129
GU		 1412static struct dma_chan *sci_request_dma_chan(struct uart_port *port,
1413 enum dma_transfer_direction dir,
1414 unsigned int id)
1415{
1416 dma_cap_mask_t mask;
1417 struct dma_chan *chan;
1418 struct dma_slave_config cfg;
1419 int ret;
1420
1421 dma_cap_zero(mask);
1422 dma_cap_set(DMA_SLAVE, mask);
1423
1424 chan = dma_request_slave_channel_compat(mask, shdma_chan_filter,
1425 (void *)(unsigned long)id, port->dev,
1426 dir == DMA_MEM_TO_DEV ? "tx" : "rx");
1427 if (!chan) {
1428 dev_warn(port->dev,
1429 "dma_request_slave_channel_compat failed\n");
1430 return NULL;
1431 }
1432
1433 memset(&cfg, 0, sizeof(cfg));
1434 cfg.direction = dir;
1435 if (dir == DMA_MEM_TO_DEV) {
1436 cfg.dst_addr = port->mapbase +
1437 (sci_getreg(port, SCxTDR)->offset << port->regshift);
1438 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1439 } else {
1440 cfg.src_addr = port->mapbase +
1441 (sci_getreg(port, SCxRDR)->offset << port->regshift);
1442 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1443 }
1444
1445 ret = dmaengine_slave_config(chan, &cfg);
1446 if (ret) {
1447 dev_warn(port->dev, "dmaengine_slave_config failed %d\n", ret);
1448 dma_release_channel(chan);
1449 return NULL;
1450 }
1451
1452 return chan;
1453}
1454
e1910fcd 1455static void sci_request_dma(struct uart_port *port)
73a19e4c 1456{
e1910fcd 1457 struct sci_port *s = to_sci_port(port);
e1910fcd 1458 struct dma_chan *chan;
73a19e4c 1459
e1910fcd 1460 dev_dbg(port->dev, "%s: port %d\n", __func__, port->line);
73a19e4c 1461
ff441129
GU		 1462 if (!port->dev->of_node &&
1463 (s->cfg->dma_slave_tx <= 0 || s->cfg->dma_slave_rx <= 0))
e1910fcd 1464 return;
73a19e4c 1465
e1910fcd 1466 s->cookie_tx = -EINVAL;
ff441129 1467 chan = sci_request_dma_chan(port, DMA_MEM_TO_DEV, s->cfg->dma_slave_tx);
e1910fcd
GU		 1468 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
1469 if (chan) {
1470 s->chan_tx = chan;
1471 /* UART circular tx buffer is an aligned page. */
1472 s->tx_dma_addr = dma_map_single(chan->device->dev,
1473 port->state->xmit.buf,
1474 UART_XMIT_SIZE,
1475 DMA_TO_DEVICE);
1476 if (dma_mapping_error(chan->device->dev, s->tx_dma_addr)) {
1477 dev_warn(port->dev, "Failed mapping Tx DMA descriptor\n");
1478 dma_release_channel(chan);
1479 s->chan_tx = NULL;
1480 } else {
1481 dev_dbg(port->dev, "%s: mapped %lu@%p to %pad\n",
1482 __func__, UART_XMIT_SIZE,
1483 port->state->xmit.buf, &s->tx_dma_addr);
49d4bcad 1484 }
e1910fcd
GU		 1485
1486 INIT_WORK(&s->work_tx, work_fn_tx);
3089f381
GL		 1487 }
1488
ff441129 1489 chan = sci_request_dma_chan(port, DMA_DEV_TO_MEM, s->cfg->dma_slave_rx);
e1910fcd
GU		 1490 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan);
1491 if (chan) {
1492 unsigned int i;
1493 dma_addr_t dma;
1494 void *buf;
73a19e4c 1495
e1910fcd 1496 s->chan_rx = chan;
73a19e4c 1497
e1910fcd
GU		 1498 s->buf_len_rx = 2 * max_t(size_t, 16, port->fifosize);
1499 buf = dma_alloc_coherent(chan->device->dev, s->buf_len_rx * 2,
1500 &dma, GFP_KERNEL);
1501 if (!buf) {
1502 dev_warn(port->dev,
1503 "Failed to allocate Rx dma buffer, using PIO\n");
1504 dma_release_channel(chan);
1505 s->chan_rx = NULL;
e1910fcd
GU		 1506 return;
1507 }
73a19e4c 1508
e1910fcd
GU		 1509 for (i = 0; i < 2; i++) {
1510 struct scatterlist *sg = &s->sg_rx[i];
0533502d 1511
e1910fcd
GU		 1512 sg_init_table(sg, 1);
1513 s->rx_buf[i] = buf;
1514 sg_dma_address(sg) = dma;
d09959e7 1515 sg_dma_len(sg) = s->buf_len_rx;
0533502d 1516
e1910fcd
GU		 1517 buf += s->buf_len_rx;
1518 dma += s->buf_len_rx;
1519 }
1520
e1910fcd
GU		 1521 setup_timer(&s->rx_timer, rx_timer_fn, (unsigned long)s);
1522
756981be
GU		 1523 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1524 sci_submit_rx(s);
e1910fcd 1525 }
0533502d
GU		 1526}
1527
e1910fcd 1528static void sci_free_dma(struct uart_port *port)
73a19e4c 1529{
e1910fcd 1530 struct sci_port *s = to_sci_port(port);
73a19e4c 1531
e1910fcd
GU		 1532 if (s->chan_tx)
1533 sci_tx_dma_release(s, false);
1534 if (s->chan_rx)
1535 sci_rx_dma_release(s, false);
1536}
1537#else
1538static inline void sci_request_dma(struct uart_port *port)
1539{
1540}
73a19e4c 1541
e1910fcd
GU		 1542static inline void sci_free_dma(struct uart_port *port)
1543{
1544}
1545#endif
73a19e4c 1546
e1910fcd
GU		 1547static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
1548{
1549#ifdef CONFIG_SERIAL_SH_SCI_DMA
1550 struct uart_port *port = ptr;
1551 struct sci_port *s = to_sci_port(port);
73a19e4c 1552
e1910fcd
GU		 1553 if (s->chan_rx) {
1554 u16 scr = serial_port_in(port, SCSCR);
1555 u16 ssr = serial_port_in(port, SCxSR);
73a19e4c 1556
e1910fcd
GU		 1557 /* Disable future Rx interrupts */
1558 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1559 disable_irq_nosync(irq);
1560 scr |= SCSCR_RDRQE;
1561 } else {
1562 scr &= ~SCSCR_RIE;
756981be 1563 sci_submit_rx(s);
e1910fcd
GU		 1564 }
1565 serial_port_out(port, SCSCR, scr);
1566 /* Clear current interrupt */
1567 serial_port_out(port, SCxSR,
1568 ssr & ~(SCIF_DR | SCxSR_RDxF(port)));
1569 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u jiffies\n",
1570 jiffies, s->rx_timeout);
1571 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
73a19e4c 1572
e1910fcd
GU		 1573 return IRQ_HANDLED;
1574 }
1575#endif
73a19e4c 1576
e1910fcd
GU		 1577 /* I think sci_receive_chars has to be called irrespective
1578 * of whether the I_IXOFF is set, otherwise, how is the interrupt
1579 * to be disabled?
1580 */
1581 sci_receive_chars(ptr);
1582
1583 return IRQ_HANDLED;
73a19e4c
GL		 1584}
1585
e1910fcd 1586static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
73a19e4c 1587{
e1910fcd 1588 struct uart_port *port = ptr;
04928b79 1589 unsigned long flags;
73a19e4c 1590
04928b79 1591 spin_lock_irqsave(&port->lock, flags);
e1910fcd 1592 sci_transmit_chars(port);
04928b79 1593 spin_unlock_irqrestore(&port->lock, flags);
e1910fcd
GU		 1594
1595 return IRQ_HANDLED;
73a19e4c
GL		 1596}
1597
e1910fcd 1598static irqreturn_t sci_er_interrupt(int irq, void *ptr)
73a19e4c 1599{
e1910fcd
GU		 1600 struct uart_port *port = ptr;
1601 struct sci_port *s = to_sci_port(port);
73a19e4c 1602
e1910fcd
GU		 1603 /* Handle errors */
1604 if (port->type == PORT_SCI) {
1605 if (sci_handle_errors(port)) {
1606 /* discard character in rx buffer */
1607 serial_port_in(port, SCxSR);
1608 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1609 }
1610 } else {
1611 sci_handle_fifo_overrun(port);
1612 if (!s->chan_rx)
1613 sci_receive_chars(ptr);
1614 }
1615
1616 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
1617
1618 /* Kick the transmission */
1619 if (!s->chan_tx)
1620 sci_tx_interrupt(irq, ptr);
1621
1622 return IRQ_HANDLED;
73a19e4c
GL		 1623}
1624
e1910fcd 1625static irqreturn_t sci_br_interrupt(int irq, void *ptr)
73a19e4c 1626{
e1910fcd 1627 struct uart_port *port = ptr;
73a19e4c 1628
e1910fcd
GU		 1629 /* Handle BREAKs */
1630 sci_handle_breaks(port);
1631 sci_clear_SCxSR(port, SCxSR_BREAK_CLEAR(port));
73a19e4c 1632
e1910fcd
GU		 1633 return IRQ_HANDLED;
1634}
73a19e4c 1635
e1910fcd
GU		 1636static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
1637{
1638 unsigned short ssr_status, scr_status, err_enabled, orer_status = 0;
1639 struct uart_port *port = ptr;
1640 struct sci_port *s = to_sci_port(port);
1641 irqreturn_t ret = IRQ_NONE;
73a19e4c 1642
e1910fcd
GU		 1643 ssr_status = serial_port_in(port, SCxSR);
1644 scr_status = serial_port_in(port, SCSCR);
1645 if (s->overrun_reg == SCxSR)
1646 orer_status = ssr_status;
1647 else {
1648 if (sci_getreg(port, s->overrun_reg)->size)
1649 orer_status = serial_port_in(port, s->overrun_reg);
73a19e4c
GL		 1650 }
1651
e1910fcd 1652 err_enabled = scr_status & port_rx_irq_mask(port);
73a19e4c 1653
e1910fcd
GU		 1654 /* Tx Interrupt */
1655 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) &&
1656 !s->chan_tx)
1657 ret = sci_tx_interrupt(irq, ptr);
658daa95 1658
e1910fcd
GU		 1659 /*
1660 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF /
1661 * DR flags
1662 */
1663 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&
1664 (scr_status & SCSCR_RIE))
1665 ret = sci_rx_interrupt(irq, ptr);
73a19e4c 1666
e1910fcd
GU		 1667 /* Error Interrupt */
1668 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
1669 ret = sci_er_interrupt(irq, ptr);
73a19e4c 1670
e1910fcd
GU		 1671 /* Break Interrupt */
1672 if ((ssr_status & SCxSR_BRK(port)) && err_enabled)
1673 ret = sci_br_interrupt(irq, ptr);
1674
1675 /* Overrun Interrupt */
1676 if (orer_status & s->overrun_mask) {
1677 sci_handle_fifo_overrun(port);
1678 ret = IRQ_HANDLED;
73a19e4c 1679 }
73a19e4c 1680
e1910fcd
GU		 1681 return ret;
1682}
73a19e4c 1683
e1910fcd
GU		 1684static const struct sci_irq_desc {
1685 const char *desc;
1686 irq_handler_t handler;
1687} sci_irq_desc[] = {
1688 /*
1689 * Split out handlers, the default case.
1690 */
1691 [SCIx_ERI_IRQ] = {
1692 .desc = "rx err",
1693 .handler = sci_er_interrupt,
1694 },
3089f381 1695
e1910fcd
GU		 1696 [SCIx_RXI_IRQ] = {
1697 .desc = "rx full",
1698 .handler = sci_rx_interrupt,
1699 },
47aceb92 1700
e1910fcd
GU		 1701 [SCIx_TXI_IRQ] = {
1702 .desc = "tx empty",
1703 .handler = sci_tx_interrupt,
1704 },
73a19e4c 1705
e1910fcd
GU		 1706 [SCIx_BRI_IRQ] = {
1707 .desc = "break",
1708 .handler = sci_br_interrupt,
1709 },
73a19e4c
GL		 1710
1711 /*
e1910fcd 1712 * Special muxed handler.
73a19e4c 1713 */
e1910fcd
GU		 1714 [SCIx_MUX_IRQ] = {
1715 .desc = "mux",
1716 .handler = sci_mpxed_interrupt,
1717 },
1718};
73a19e4c 1719
e1910fcd
GU		 1720static int sci_request_irq(struct sci_port *port)
1721{
1722 struct uart_port *up = &port->port;
1723 int i, j, ret = 0;
73a19e4c 1724
e1910fcd
GU		 1725 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) {
1726 const struct sci_irq_desc *desc;
1727 int irq;
73a19e4c 1728
e1910fcd
GU		 1729 if (SCIx_IRQ_IS_MUXED(port)) {
1730 i = SCIx_MUX_IRQ;
1731 irq = up->irq;
1732 } else {
1733 irq = port->irqs[i];
1734
1735 /*
1736 * Certain port types won't support all of the
1737 * available interrupt sources.
1738 */
1739 if (unlikely(irq < 0))
1740 continue;
1741 }
1742
1743 desc = sci_irq_desc + i;
1744 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s",
1745 dev_name(up->dev), desc->desc);
1746 if (!port->irqstr[j])
1747 goto out_nomem;
1748
1749 ret = request_irq(irq, desc->handler, up->irqflags,
1750 port->irqstr[j], port);
1751 if (unlikely(ret)) {
1752 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc);
1753 goto out_noirq;
1754 }
73a19e4c
GL		 1755 }
1756
e1910fcd 1757 return 0;
1da177e4 1758
e1910fcd
GU		 1759out_noirq:
1760 while (--i >= 0)
1761 free_irq(port->irqs[i], port);
f43dc23d 1762
e1910fcd
GU		 1763out_nomem:
1764 while (--j >= 0)
1765 kfree(port->irqstr[j]);
f43dc23d 1766
e1910fcd 1767 return ret;
1da177e4
LT		 1768}
1769
e1910fcd 1770static void sci_free_irq(struct sci_port *port)
1da177e4 1771{
e1910fcd 1772 int i;
1da177e4 1773
e1910fcd
GU		 1774 /*
1775 * Intentionally in reverse order so we iterate over the muxed
1776 * IRQ first.
1777 */
1778 for (i = 0; i < SCIx_NR_IRQS; i++) {
1779 int irq = port->irqs[i];
f43dc23d 1780
e1910fcd
GU		 1781 /*
1782 * Certain port types won't support all of the available
1783 * interrupt sources.
1784 */
1785 if (unlikely(irq < 0))
1786 continue;
f43dc23d 1787
e1910fcd
GU		 1788 free_irq(port->irqs[i], port);
1789 kfree(port->irqstr[i]);
f43dc23d 1790
e1910fcd
GU		 1791 if (SCIx_IRQ_IS_MUXED(port)) {
1792 /* If there's only one IRQ, we're done. */
1793 return;
1794 }
1795 }
1da177e4
LT		 1796}
1797
e1910fcd 1798static unsigned int sci_tx_empty(struct uart_port *port)
1da177e4 1799{
e1910fcd
GU		 1800 unsigned short status = serial_port_in(port, SCxSR);
1801 unsigned short in_tx_fifo = sci_txfill(port);
f43dc23d 1802
e1910fcd 1803 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
1da177e4
LT		 1804}
1805
e1910fcd
GU		 1806/*
1807 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally
1808 * CTS/RTS is supported in hardware by at least one port and controlled
1809 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently
1810 * handled via the ->init_pins() op, which is a bit of a one-way street,
1811 * lacking any ability to defer pin control -- this will later be
1812 * converted over to the GPIO framework).
1813 *
1814 * Other modes (such as loopback) are supported generically on certain
1815 * port types, but not others. For these it's sufficient to test for the
1816 * existence of the support register and simply ignore the port type.
1817 */
1818static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
1da177e4 1819{
e1910fcd
GU		 1820 if (mctrl & TIOCM_LOOP) {
1821 const struct plat_sci_reg *reg;
f43dc23d 1822
e1910fcd
GU		 1823 /*
1824 * Standard loopback mode for SCFCR ports.
1825 */
1826 reg = sci_getreg(port, SCFCR);
1827 if (reg->size)
1828 serial_port_out(port, SCFCR,
1829 serial_port_in(port, SCFCR) |
1830 SCFCR_LOOP);
1831 }
1832}
f43dc23d 1833
e1910fcd
GU		 1834static unsigned int sci_get_mctrl(struct uart_port *port)
1835{
1836 /*
1837 * CTS/RTS is handled in hardware when supported, while nothing
1838 * else is wired up. Keep it simple and simply assert DSR/CAR.
1839 */
1840 return TIOCM_DSR | TIOCM_CAR;
1da177e4
LT		 1841}
1842
1da177e4
LT		 1843static void sci_break_ctl(struct uart_port *port, int break_state)
1844{
bbb4ce50 1845 struct sci_port *s = to_sci_port(port);
d3184e68 1846 const struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR;
bbb4ce50
SY		 1847 unsigned short scscr, scsptr;
1848
a4e02f6d
SY		 1849 /* check wheter the port has SCSPTR */
1850 if (!reg->size) {
bbb4ce50
SY		 1851 /*
1852 * Not supported by hardware. Most parts couple break and rx
1853 * interrupts together, with break detection always enabled.
1854 */
a4e02f6d 1855 return;
bbb4ce50 1856 }
a4e02f6d
SY		 1857
1858 scsptr = serial_port_in(port, SCSPTR);
1859 scscr = serial_port_in(port, SCSCR);
1860
1861 if (break_state == -1) {
1862 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT;
1863 scscr &= ~SCSCR_TE;
1864 } else {
1865 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO;
1866 scscr |= SCSCR_TE;
1867 }
1868
1869 serial_port_out(port, SCSPTR, scsptr);
1870 serial_port_out(port, SCSCR, scscr);
1da177e4
LT		 1871}
1872
1873static int sci_startup(struct uart_port *port)
1874{
a5660ada 1875 struct sci_port *s = to_sci_port(port);
33b48e16 1876 unsigned long flags;
073e84c9 1877 int ret;
1da177e4 1878
73a19e4c
GL		 1879 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1880
073e84c9
PM		 1881 ret = sci_request_irq(s);
1882 if (unlikely(ret < 0))
1883 return ret;
1884
73a19e4c 1885 sci_request_dma(port);
073e84c9 1886
33b48e16 1887 spin_lock_irqsave(&port->lock, flags);
d656901b 1888 sci_start_tx(port);
73a19e4c 1889 sci_start_rx(port);
33b48e16 1890 spin_unlock_irqrestore(&port->lock, flags);
1da177e4
LT		 1891
1892 return 0;
1893}
1894
1895static void sci_shutdown(struct uart_port *port)
1896{
a5660ada 1897 struct sci_port *s = to_sci_port(port);
33b48e16 1898 unsigned long flags;
1da177e4 1899
73a19e4c
GL		 1900 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1901
33b48e16 1902 spin_lock_irqsave(&port->lock, flags);
1da177e4 1903 sci_stop_rx(port);
b129a8cc 1904 sci_stop_tx(port);
33b48e16 1905 spin_unlock_irqrestore(&port->lock, flags);
073e84c9 1906
9ab76556
AM		 1907#ifdef CONFIG_SERIAL_SH_SCI_DMA
1908 if (s->chan_rx) {
1909 dev_dbg(port->dev, "%s(%d) deleting rx_timer\n", __func__,
1910 port->line);
1911 del_timer_sync(&s->rx_timer);
1912 }
1913#endif
1914
73a19e4c 1915 sci_free_dma(port);
1da177e4 1916 sci_free_irq(s);
1da177e4
LT		 1917}
1918
6af27bf2
GU		 1919static int sci_sck_calc(struct sci_port *s, unsigned int bps,
1920 unsigned int *srr)
26c92f37 1921{
6af27bf2 1922 unsigned long freq = s->clk_rates[SCI_SCK];
6af27bf2 1923 int err, min_err = INT_MAX;
69eee8e9 1924 unsigned int sr;
6af27bf2 1925
7b5c0c08
GU		 1926 if (s->port.type != PORT_HSCIF)
1927 freq *= 2;
6af27bf2 1928
69eee8e9 1929 for_each_sr(sr, s) {
6af27bf2
GU		 1930 err = DIV_ROUND_CLOSEST(freq, sr) - bps;
1931 if (abs(err) >= abs(min_err))
1932 continue;
1933
1934 min_err = err;
1935 *srr = sr - 1;
ec09c5eb 1936
6af27bf2
GU		 1937 if (!err)
1938 break;
1939 }
e8183a6c 1940
6af27bf2
GU		 1941 dev_dbg(s->port.dev, "SCK: %u%+d bps using SR %u\n", bps, min_err,
1942 *srr + 1);
1943 return min_err;
26c92f37
PM		 1944}
1945
1270f865
GU		 1946static int sci_brg_calc(struct sci_port *s, unsigned int bps,
1947 unsigned long freq, unsigned int *dlr,
1948 unsigned int *srr)
730c4e78 1949{
1270f865 1950 int err, min_err = INT_MAX;
69eee8e9 1951 unsigned int sr, dl;
730c4e78 1952
7b5c0c08
GU		 1953 if (s->port.type != PORT_HSCIF)
1954 freq *= 2;
730c4e78 1955
69eee8e9 1956 for_each_sr(sr, s) {
1270f865
GU		 1957 dl = DIV_ROUND_CLOSEST(freq, sr * bps);
1958 dl = clamp(dl, 1U, 65535U);
1959
1960 err = DIV_ROUND_CLOSEST(freq, sr * dl) - bps;
1961 if (abs(err) >= abs(min_err))
1962 continue;
1963
1964 min_err = err;
1965 *dlr = dl;
1966 *srr = sr - 1;
1967
1968 if (!err)
1969 break;
1970 }
730c4e78 1971
1270f865
GU		 1972 dev_dbg(s->port.dev, "BRG: %u%+d bps using DL %u SR %u\n", bps,
1973 min_err, *dlr, *srr + 1);
1974 return min_err;
1975}
730c4e78 1976
b4a5c459 1977/* calculate sample rate, BRR, and clock select */
f4998e55
GU		 1978static int sci_scbrr_calc(struct sci_port *s, unsigned int bps,
1979 unsigned int *brr, unsigned int *srr,
1980 unsigned int *cks)
f303b364 1981{
f4998e55 1982 unsigned long freq = s->clk_rates[SCI_FCK];
69eee8e9 1983 unsigned int sr, br, prediv, scrate, c;
6c51332d 1984 int err, min_err = INT_MAX;
f303b364 1985
7b5c0c08
GU		 1986 if (s->port.type != PORT_HSCIF)
1987 freq *= 2;
b4a5c459 1988
6c51332d
GU		 1989 /*
1990 * Find the combination of sample rate and clock select with the
1991 * smallest deviation from the desired baud rate.
1992 * Prefer high sample rates to maximise the receive margin.
1993 *
1994 * M: Receive margin (%)
1995 * N: Ratio of bit rate to clock (N = sampling rate)
1996 * D: Clock duty (D = 0 to 1.0)
1997 * L: Frame length (L = 9 to 12)
1998 * F: Absolute value of clock frequency deviation
1999 *
2000 * M = |(0.5 - 1 / 2 * N) - ((L - 0.5) * F) -
2001 * (|D - 0.5| / N * (1 + F))|
2002 * NOTE: Usually, treat D for 0.5, F is 0 by this calculation.
2003 */
69eee8e9 2004 for_each_sr(sr, s) {
f303b364
UH		 2005 for (c = 0; c <= 3; c++) {
2006 /* integerized formulas from HSCIF documentation */
7b5c0c08 2007 prediv = sr * (1 << (2 * c + 1));
de01e6cd
GU		 2008
2009 /*
2010 * We need to calculate:
2011 *
2012 * br = freq / (prediv * bps) clamped to [1..256]
881a7489 2013 * err = freq / (br * prediv) - bps
730c4e78 2014 *
de01e6cd
GU		 2015 * Watch out for overflow when calculating the desired
2016 * sampling clock rate!
730c4e78 2017 */
de01e6cd
GU		 2018 if (bps > UINT_MAX / prediv)
2019 break;
2020
2021 scrate = prediv * bps;
2022 br = DIV_ROUND_CLOSEST(freq, scrate);
95a2703e 2023 br = clamp(br, 1U, 256U);
6c51332d 2024
881a7489 2025 err = DIV_ROUND_CLOSEST(freq, br * prediv) - bps;
6c51332d 2026 if (abs(err) >= abs(min_err))
730c4e78
NI		 2027 continue;
2028
6c51332d 2029 min_err = err;
95a2703e 2030 *brr = br - 1;
730c4e78
NI		 2031 *srr = sr - 1;
2032 *cks = c;
6c51332d
GU		 2033
2034 if (!err)
2035 goto found;
f303b364
UH		 2036 }
2037 }
2038
6c51332d 2039found:
881a7489
GU		 2040 dev_dbg(s->port.dev, "BRR: %u%+d bps using N %u SR %u cks %u\n", bps,
2041 min_err, *brr, *srr + 1, *cks);
f4998e55 2042 return min_err;
f303b364
UH		 2043}
2044
1ba76220
MD		 2045static void sci_reset(struct uart_port *port)
2046{
d3184e68 2047 const struct plat_sci_reg *reg;
1ba76220
MD		 2048 unsigned int status;
2049
2050 do {
b12bb29f 2051 status = serial_port_in(port, SCxSR);
1ba76220
MD		 2052 } while (!(status & SCxSR_TEND(port)));
2053
b12bb29f 2054 serial_port_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */
1ba76220 2055
0979e0e6
PM		 2056 reg = sci_getreg(port, SCFCR);
2057 if (reg->size)
b12bb29f 2058 serial_port_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
1ba76220
MD		 2059}
2060
606d099c
AC		 2061static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
2062 struct ktermios *old)
1da177e4 2063{
95ee05c7 2064 unsigned int baud, smr_val = SCSMR_ASYNC, scr_val = 0, i;
1270f865
GU		 2065 unsigned int brr = 255, cks = 0, srr = 15, dl = 0, sccks = 0;
2066 unsigned int brr1 = 255, cks1 = 0, srr1 = 15, dl1 = 0;
00b9de9c 2067 struct sci_port *s = to_sci_port(port);
d3184e68 2068 const struct plat_sci_reg *reg;
f4998e55
GU		 2069 int min_err = INT_MAX, err;
2070 unsigned long max_freq = 0;
2071 int best_clk = -1;
1da177e4 2072
730c4e78
NI		 2073 if ((termios->c_cflag & CSIZE) == CS7)
2074 smr_val |= SCSMR_CHR;
2075 if (termios->c_cflag & PARENB)
2076 smr_val |= SCSMR_PE;
2077 if (termios->c_cflag & PARODD)
2078 smr_val |= SCSMR_PE | SCSMR_ODD;
2079 if (termios->c_cflag & CSTOPB)
2080 smr_val |= SCSMR_STOP;
2081
154280fd
MD		 2082 /*
2083 * earlyprintk comes here early on with port->uartclk set to zero.
2084 * the clock framework is not up and running at this point so here
2085 * we assume that 115200 is the maximum baud rate. please note that
2086 * the baud rate is not programmed during earlyprintk - it is assumed
2087 * that the previous boot loader has enabled required clocks and
2088 * setup the baud rate generator hardware for us already.
2089 */
f4998e55
GU		 2090 if (!port->uartclk) {
2091 baud = uart_get_baud_rate(port, termios, old, 0, 115200);
2092 goto done;
2093 }
1da177e4 2094
f4998e55
GU		 2095 for (i = 0; i < SCI_NUM_CLKS; i++)
2096 max_freq = max(max_freq, s->clk_rates[i]);
2097
69eee8e9 2098 baud = uart_get_baud_rate(port, termios, old, 0, max_freq / min_sr(s));
f4998e55
GU		 2099 if (!baud)
2100 goto done;
2101
2102 /*
2103 * There can be multiple sources for the sampling clock. Find the one
2104 * that gives us the smallest deviation from the desired baud rate.
2105 */
2106
6af27bf2
GU		 2107 /* Optional Undivided External Clock */
2108 if (s->clk_rates[SCI_SCK] && port->type != PORT_SCIFA &&
2109 port->type != PORT_SCIFB) {
2110 err = sci_sck_calc(s, baud, &srr1);
2111 if (abs(err) < abs(min_err)) {
2112 best_clk = SCI_SCK;
2113 scr_val = SCSCR_CKE1;
2114 sccks = SCCKS_CKS;
2115 min_err = err;
2116 srr = srr1;
2117 if (!err)
2118 goto done;
2119 }
2120 }
2121
1270f865
GU		 2122 /* Optional BRG Frequency Divided External Clock */
2123 if (s->clk_rates[SCI_SCIF_CLK] && sci_getreg(port, SCDL)->size) {
2124 err = sci_brg_calc(s, baud, s->clk_rates[SCI_SCIF_CLK], &dl1,
2125 &srr1);
2126 if (abs(err) < abs(min_err)) {
2127 best_clk = SCI_SCIF_CLK;
2128 scr_val = SCSCR_CKE1;
2129 sccks = 0;
2130 min_err = err;
2131 dl = dl1;
2132 srr = srr1;
2133 if (!err)
2134 goto done;
2135 }
2136 }
2137
2138 /* Optional BRG Frequency Divided Internal Clock */
2139 if (s->clk_rates[SCI_BRG_INT] && sci_getreg(port, SCDL)->size) {
2140 err = sci_brg_calc(s, baud, s->clk_rates[SCI_BRG_INT], &dl1,
2141 &srr1);
2142 if (abs(err) < abs(min_err)) {
2143 best_clk = SCI_BRG_INT;
2144 scr_val = SCSCR_CKE1;
2145 sccks = SCCKS_XIN;
2146 min_err = err;
2147 dl = dl1;
2148 srr = srr1;
2149 if (!min_err)
2150 goto done;
f303b364
UH		 2151 }
2152 }
e108b2ca 2153
f4998e55
GU		 2154 /* Divided Functional Clock using standard Bit Rate Register */
2155 err = sci_scbrr_calc(s, baud, &brr1, &srr1, &cks1);
2156 if (abs(err) < abs(min_err)) {
2157 best_clk = SCI_FCK;
6af27bf2 2158 scr_val = 0;
f4998e55
GU		 2159 min_err = err;
2160 brr = brr1;
2161 srr = srr1;
2162 cks = cks1;
2163 }
2164
2165done:
2166 if (best_clk >= 0)
2167 dev_dbg(port->dev, "Using clk %pC for %u%+d bps\n",
2168 s->clks[best_clk], baud, min_err);
e108b2ca 2169
23241d43 2170 sci_port_enable(s);
36003386 2171
6af27bf2
GU		 2172 /*
2173 * Program the optional External Baud Rate Generator (BRG) first.
2174 * It controls the mux to select (H)SCK or frequency divided clock.
2175 */
1270f865
GU		 2176 if (best_clk >= 0 && sci_getreg(port, SCCKS)->size) {
2177 serial_port_out(port, SCDL, dl);
6af27bf2 2178 serial_port_out(port, SCCKS, sccks);
1270f865 2179 }
1da177e4 2180
1ba76220 2181 sci_reset(port);
1da177e4
LT		 2182
2183 uart_update_timeout(port, termios->c_cflag, baud);
2184
f4998e55 2185 if (best_clk >= 0) {
92a05748
GU		 2186 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
2187 switch (srr + 1) {
2188 case 5: smr_val |= SCSMR_SRC_5; break;
2189 case 7: smr_val |= SCSMR_SRC_7; break;
2190 case 11: smr_val |= SCSMR_SRC_11; break;
2191 case 13: smr_val |= SCSMR_SRC_13; break;
2192 case 16: smr_val |= SCSMR_SRC_16; break;
2193 case 17: smr_val |= SCSMR_SRC_17; break;
2194 case 19: smr_val |= SCSMR_SRC_19; break;
2195 case 27: smr_val |= SCSMR_SRC_27; break;
2196 }
f4998e55 2197 smr_val |= cks;
6af27bf2 2198 dev_dbg(port->dev,
1270f865
GU		 2199 "SCR 0x%x SMR 0x%x BRR %u CKS 0x%x DL %u SRR %u\n",
2200 scr_val, smr_val, brr, sccks, dl, srr);
6af27bf2 2201 serial_port_out(port, SCSCR, scr_val);
f4998e55
GU		 2202 serial_port_out(port, SCSMR, smr_val);
2203 serial_port_out(port, SCBRR, brr);
2204 if (sci_getreg(port, HSSRR)->size)
f303b364 2205 serial_port_out(port, HSSRR, srr | HSCIF_SRE);
f4998e55
GU		 2206
2207 /* Wait one bit interval */
2208 udelay((1000000 + (baud - 1)) / baud);
2209 } else {
2210 /* Don't touch the bit rate configuration */
2211 scr_val = s->cfg->scscr & (SCSCR_CKE1 | SCSCR_CKE0);
3a964abe
GU		 2212 smr_val |= serial_port_in(port, SCSMR) &
2213 (SCSMR_CKEDG | SCSMR_SRC_MASK | SCSMR_CKS);
f4998e55
GU		 2214 dev_dbg(port->dev, "SCR 0x%x SMR 0x%x\n", scr_val, smr_val);
2215 serial_port_out(port, SCSCR, scr_val);
9d482cc3 2216 serial_port_out(port, SCSMR, smr_val);
f4998e55 2217 }
1da177e4 2218
d5701647 2219 sci_init_pins(port, termios->c_cflag);
0979e0e6 2220
73c3d53f
PM		 2221 reg = sci_getreg(port, SCFCR);
2222 if (reg->size) {
b12bb29f 2223 unsigned short ctrl = serial_port_in(port, SCFCR);
0979e0e6 2224
73c3d53f 2225 if (s->cfg->capabilities & SCIx_HAVE_RTSCTS) {
faf02f8f
PM		 2226 if (termios->c_cflag & CRTSCTS)
2227 ctrl |= SCFCR_MCE;
2228 else
2229 ctrl &= ~SCFCR_MCE;
faf02f8f 2230 }
73c3d53f
PM		 2231
2232 /*
2233 * As we've done a sci_reset() above, ensure we don't
2234 * interfere with the FIFOs while toggling MCE. As the
2235 * reset values could still be set, simply mask them out.
2236 */
2237 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST);
2238
b12bb29f 2239 serial_port_out(port, SCFCR, ctrl);
0979e0e6 2240 }
b7a76e4b 2241
f4998e55
GU		 2242 scr_val |= s->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0);
2243 dev_dbg(port->dev, "SCSCR 0x%x\n", scr_val);
2244 serial_port_out(port, SCSCR, scr_val);
92a05748
GU		 2245 if ((srr + 1 == 5) &&
2246 (port->type == PORT_SCIFA || port->type == PORT_SCIFB)) {
2247 /*
2248 * In asynchronous mode, when the sampling rate is 1/5, first
2249 * received data may become invalid on some SCIFA and SCIFB.
2250 * To avoid this problem wait more than 1 serial data time (1
2251 * bit time x serial data number) after setting SCSCR.RE = 1.
2252 */
2253 udelay(DIV_ROUND_UP(10 * 1000000, baud));
2254 }
1da177e4 2255
3089f381
GL		 2256#ifdef CONFIG_SERIAL_SH_SCI_DMA
2257 /*
5f6d8515 2258 * Calculate delay for 2 DMA buffers (4 FIFO).
f5835c1d
GU		 2259 * See serial_core.c::uart_update_timeout().
2260 * With 10 bits (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above
2261 * function calculates 1 jiffie for the data plus 5 jiffies for the
2262 * "slop(e)." Then below we calculate 5 jiffies (20ms) for 2 DMA
2263 * buffers (4 FIFO sizes), but when performing a faster transfer, the
2264 * value obtained by this formula is too small. Therefore, if the value
2265 * is smaller than 20ms, use 20ms as the timeout value for DMA.
3089f381
GL		 2266 */
2267 if (s->chan_rx) {
5f6d8515
NI		 2268 unsigned int bits;
2269
2270 /* byte size and parity */
2271 switch (termios->c_cflag & CSIZE) {
2272 case CS5:
2273 bits = 7;
2274 break;
2275 case CS6:
2276 bits = 8;
2277 break;
2278 case CS7:
2279 bits = 9;
2280 break;
2281 default:
2282 bits = 10;
2283 break;
2284 }
2285
2286 if (termios->c_cflag & CSTOPB)
2287 bits++;
2288 if (termios->c_cflag & PARENB)
2289 bits++;
2290 s->rx_timeout = DIV_ROUND_UP((s->buf_len_rx * 2 * bits * HZ) /
2291 (baud / 10), 10);
9b971cd2 2292 dev_dbg(port->dev, "DMA Rx t-out %ums, tty t-out %u jiffies\n",
3089f381
GL		 2293 s->rx_timeout * 1000 / HZ, port->timeout);
2294 if (s->rx_timeout < msecs_to_jiffies(20))
2295 s->rx_timeout = msecs_to_jiffies(20);
2296 }
2297#endif
2298
1da177e4 2299 if ((termios->c_cflag & CREAD) != 0)
73a19e4c 2300 sci_start_rx(port);
36003386 2301
23241d43 2302 sci_port_disable(s);
1da177e4
LT		 2303}
2304
0174e5ca
TK		 2305static void sci_pm(struct uart_port *port, unsigned int state,
2306 unsigned int oldstate)
2307{
2308 struct sci_port *sci_port = to_sci_port(port);
2309
2310 switch (state) {
d3dfe5d9 2311 case UART_PM_STATE_OFF:
0174e5ca
TK		 2312 sci_port_disable(sci_port);
2313 break;
2314 default:
2315 sci_port_enable(sci_port);
2316 break;
2317 }
2318}
2319
1da177e4
LT		 2320static const char *sci_type(struct uart_port *port)
2321{
2322 switch (port->type) {
e7c98dc7
MT		 2323 case PORT_IRDA:
2324 return "irda";
2325 case PORT_SCI:
2326 return "sci";
2327 case PORT_SCIF:
2328 return "scif";
2329 case PORT_SCIFA:
2330 return "scifa";
d1d4b10c
GL		 2331 case PORT_SCIFB:
2332 return "scifb";
f303b364
UH		 2333 case PORT_HSCIF:
2334 return "hscif";
1da177e4
LT		 2335 }
2336
fa43972f 2337 return NULL;
1da177e4
LT		 2338}
2339
f6e9495d
PM		 2340static int sci_remap_port(struct uart_port *port)
2341{
e4d6f911 2342 struct sci_port *sport = to_sci_port(port);
f6e9495d
PM		 2343
2344 /*
2345 * Nothing to do if there's already an established membase.
2346 */
2347 if (port->membase)
2348 return 0;
2349
2350 if (port->flags & UPF_IOREMAP) {
e4d6f911 2351 port->membase = ioremap_nocache(port->mapbase, sport->reg_size);
f6e9495d
PM		 2352 if (unlikely(!port->membase)) {
2353 dev_err(port->dev, "can't remap port#%d\n", port->line);
2354 return -ENXIO;
2355 }
2356 } else {
2357 /*
2358 * For the simple (and majority of) cases where we don't
2359 * need to do any remapping, just cast the cookie
2360 * directly.
2361 */
3af4e960 2362 port->membase = (void __iomem *)(uintptr_t)port->mapbase;
f6e9495d
PM		 2363 }
2364
2365 return 0;
2366}
2367
e2651647 2368static void sci_release_port(struct uart_port *port)
1da177e4 2369{
e4d6f911
YS		 2370 struct sci_port *sport = to_sci_port(port);
2371
e2651647
PM		 2372 if (port->flags & UPF_IOREMAP) {
2373 iounmap(port->membase);
2374 port->membase = NULL;
2375 }
2376
e4d6f911 2377 release_mem_region(port->mapbase, sport->reg_size);
1da177e4
LT		 2378}
2379
e2651647 2380static int sci_request_port(struct uart_port *port)
1da177e4 2381{
e2651647 2382 struct resource *res;
e4d6f911 2383 struct sci_port *sport = to_sci_port(port);
f6e9495d 2384 int ret;
1da177e4 2385
e4d6f911
YS		 2386 res = request_mem_region(port->mapbase, sport->reg_size,
2387 dev_name(port->dev));
2388 if (unlikely(res == NULL)) {
2389 dev_err(port->dev, "request_mem_region failed.");
e2651647 2390 return -EBUSY;
e4d6f911 2391 }
1da177e4 2392
f6e9495d
PM		 2393 ret = sci_remap_port(port);
2394 if (unlikely(ret != 0)) {
2395 release_resource(res);
2396 return ret;
7ff731ae 2397 }
e2651647
PM		 2398
2399 return 0;
2400}
2401
2402static void sci_config_port(struct uart_port *port, int flags)
2403{
2404 if (flags & UART_CONFIG_TYPE) {
2405 struct sci_port *sport = to_sci_port(port);
2406
2407 port->type = sport->cfg->type;
2408 sci_request_port(port);
2409 }
1da177e4
LT		 2410}
2411
2412static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
2413{
1da177e4
LT		 2414 if (ser->baud_base < 2400)
2415 /* No paper tape reader for Mitch.. */
2416 return -EINVAL;
2417
2418 return 0;
2419}
2420
2421static struct uart_ops sci_uart_ops = {
2422 .tx_empty = sci_tx_empty,
2423 .set_mctrl = sci_set_mctrl,
2424 .get_mctrl = sci_get_mctrl,
2425 .start_tx = sci_start_tx,
2426 .stop_tx = sci_stop_tx,
2427 .stop_rx = sci_stop_rx,
1da177e4
LT		 2428 .break_ctl = sci_break_ctl,
2429 .startup = sci_startup,
2430 .shutdown = sci_shutdown,
2431 .set_termios = sci_set_termios,
0174e5ca 2432 .pm = sci_pm,
1da177e4
LT		 2433 .type = sci_type,
2434 .release_port = sci_release_port,
2435 .request_port = sci_request_port,
2436 .config_port = sci_config_port,
2437 .verify_port = sci_verify_port,
07d2a1a1
PM		 2438#ifdef CONFIG_CONSOLE_POLL
2439 .poll_get_char = sci_poll_get_char,
2440 .poll_put_char = sci_poll_put_char,
2441#endif
1da177e4
LT		 2442};
2443
a9ec81f4
LP		 2444static int sci_init_clocks(struct sci_port *sci_port, struct device *dev)
2445{
f4998e55
GU		 2446 const char *clk_names[] = {
2447 [SCI_FCK] = "fck",
6af27bf2 2448 [SCI_SCK] = "sck",
1270f865
GU		 2449 [SCI_BRG_INT] = "brg_int",
2450 [SCI_SCIF_CLK] = "scif_clk",
f4998e55
GU		 2451 };
2452 struct clk *clk;
2453 unsigned int i;
a9ec81f4 2454
6af27bf2
GU		 2455 if (sci_port->cfg->type == PORT_HSCIF)
2456 clk_names[SCI_SCK] = "hsck";
2457
f4998e55
GU		 2458 for (i = 0; i < SCI_NUM_CLKS; i++) {
2459 clk = devm_clk_get(dev, clk_names[i]);
2460 if (PTR_ERR(clk) == -EPROBE_DEFER)
2461 return -EPROBE_DEFER;
a9ec81f4 2462
f4998e55
GU		 2463 if (IS_ERR(clk) && i == SCI_FCK) {
2464 /*
2465 * "fck" used to be called "sci_ick", and we need to
2466 * maintain DT backward compatibility.
2467 */
2468 clk = devm_clk_get(dev, "sci_ick");
2469 if (PTR_ERR(clk) == -EPROBE_DEFER)
2470 return -EPROBE_DEFER;
a9ec81f4 2471
f4998e55
GU		 2472 if (!IS_ERR(clk))
2473 goto found;
a9ec81f4 2474
f4998e55
GU		 2475 /*
2476 * Not all SH platforms declare a clock lookup entry
2477 * for SCI devices, in which case we need to get the
2478 * global "peripheral_clk" clock.
2479 */
2480 clk = devm_clk_get(dev, "peripheral_clk");
2481 if (!IS_ERR(clk))
2482 goto found;
2483
2484 dev_err(dev, "failed to get %s (%ld)\n", clk_names[i],
2485 PTR_ERR(clk));
2486 return PTR_ERR(clk);
2487 }
2488
2489found:
2490 if (IS_ERR(clk))
2491 dev_dbg(dev, "failed to get %s (%ld)\n", clk_names[i],
2492 PTR_ERR(clk));
2493 else
2494 dev_dbg(dev, "clk %s is %pC rate %pCr\n", clk_names[i],
2495 clk, clk);
2496 sci_port->clks[i] = IS_ERR(clk) ? NULL : clk;
2497 }
2498 return 0;
a9ec81f4
LP		 2499}
2500
9671f099 2501static int sci_init_single(struct platform_device *dev,
1fcc91a6
LP		 2502 struct sci_port *sci_port, unsigned int index,
2503 struct plat_sci_port *p, bool early)
e108b2ca 2504{
73a19e4c 2505 struct uart_port *port = &sci_port->port;
1fcc91a6
LP		 2506 const struct resource *res;
2507 unsigned int i;
3127c6b2 2508 int ret;
e108b2ca 2509
50f0959a
PM		 2510 sci_port->cfg = p;
2511
73a19e4c
GL		 2512 port->ops = &sci_uart_ops;
2513 port->iotype = UPIO_MEM;
2514 port->line = index;
75136d48 2515
89b5c1ab
LP		 2516 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
2517 if (res == NULL)
2518 return -ENOMEM;
1fcc91a6 2519
89b5c1ab 2520 port->mapbase = res->start;
e4d6f911 2521 sci_port->reg_size = resource_size(res);
1fcc91a6 2522
89b5c1ab
LP		 2523 for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i)
2524 sci_port->irqs[i] = platform_get_irq(dev, i);
1fcc91a6 2525
89b5c1ab
LP		 2526 /* The SCI generates several interrupts. They can be muxed together or
2527 * connected to different interrupt lines. In the muxed case only one
2528 * interrupt resource is specified. In the non-muxed case three or four
2529 * interrupt resources are specified, as the BRI interrupt is optional.
2530 */
2531 if (sci_port->irqs[0] < 0)
2532 return -ENXIO;
1fcc91a6 2533
89b5c1ab
LP		 2534 if (sci_port->irqs[1] < 0) {
2535 sci_port->irqs[1] = sci_port->irqs[0];
2536 sci_port->irqs[2] = sci_port->irqs[0];
2537 sci_port->irqs[3] = sci_port->irqs[0];
1fcc91a6
LP		 2538 }
2539
b545e4f4
LP		 2540 if (p->regtype == SCIx_PROBE_REGTYPE) {
2541 ret = sci_probe_regmap(p);
2542 if (unlikely(ret))
2543 return ret;
2544 }
2545
75136d48 2546 switch (p->type) {
d1d4b10c
GL		 2547 case PORT_SCIFB:
2548 port->fifosize = 256;
2e0842a1 2549 sci_port->overrun_reg = SCxSR;
75c249fd 2550 sci_port->overrun_mask = SCIFA_ORER;
92a05748 2551 sci_port->sampling_rate_mask = SCI_SR_SCIFAB;
d1d4b10c 2552 break;
f303b364
UH		 2553 case PORT_HSCIF:
2554 port->fifosize = 128;
2e0842a1 2555 sci_port->overrun_reg = SCLSR;
75c249fd 2556 sci_port->overrun_mask = SCLSR_ORER;
69eee8e9 2557 sci_port->sampling_rate_mask = SCI_SR_RANGE(8, 32);
f303b364 2558 break;
75136d48 2559 case PORT_SCIFA:
73a19e4c 2560 port->fifosize = 64;
2e0842a1 2561 sci_port->overrun_reg = SCxSR;
75c249fd 2562 sci_port->overrun_mask = SCIFA_ORER;
92a05748 2563 sci_port->sampling_rate_mask = SCI_SR_SCIFAB;
75136d48
MP		 2564 break;
2565 case PORT_SCIF:
73a19e4c 2566 port->fifosize = 16;
ec09c5eb 2567 if (p->regtype == SCIx_SH7705_SCIF_REGTYPE) {
2e0842a1 2568 sci_port->overrun_reg = SCxSR;
75c249fd 2569 sci_port->overrun_mask = SCIFA_ORER;
69eee8e9 2570 sci_port->sampling_rate_mask = SCI_SR(16);
ec09c5eb 2571 } else {
2e0842a1 2572 sci_port->overrun_reg = SCLSR;
75c249fd 2573 sci_port->overrun_mask = SCLSR_ORER;
69eee8e9 2574 sci_port->sampling_rate_mask = SCI_SR(32);
ec09c5eb 2575 }
75136d48
MP		 2576 break;
2577 default:
73a19e4c 2578 port->fifosize = 1;
2e0842a1 2579 sci_port->overrun_reg = SCxSR;
75c249fd 2580 sci_port->overrun_mask = SCI_ORER;
69eee8e9 2581 sci_port->sampling_rate_mask = SCI_SR(32);
75136d48
MP		 2582 break;
2583 }
7b6fd3bf 2584
878fbb91
LP		 2585 /* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't
2586 * match the SoC datasheet, this should be investigated. Let platform
2587 * data override the sampling rate for now.
ec09c5eb 2588 */
f84b6bdc 2589 if (p->sampling_rate)
69eee8e9 2590 sci_port->sampling_rate_mask = SCI_SR(p->sampling_rate);
ec09c5eb 2591
1fcc91a6 2592 if (!early) {
a9ec81f4
LP		 2593 ret = sci_init_clocks(sci_port, &dev->dev);
2594 if (ret < 0)
2595 return ret;
c7ed1ab3 2596
73a19e4c 2597 port->dev = &dev->dev;
5e50d2d6
MD		 2598
2599 pm_runtime_enable(&dev->dev);
7b6fd3bf 2600 }
e108b2ca 2601
7ed7e071
MD		 2602 sci_port->break_timer.data = (unsigned long)sci_port;
2603 sci_port->break_timer.function = sci_break_timer;
2604 init_timer(&sci_port->break_timer);
2605
debf9507
PM		 2606 /*
2607 * Establish some sensible defaults for the error detection.
2608 */
5da0f468
GU		 2609 if (p->type == PORT_SCI) {
2610 sci_port->error_mask = SCI_DEFAULT_ERROR_MASK;
2611 sci_port->error_clear = SCI_ERROR_CLEAR;
2612 } else {
2613 sci_port->error_mask = SCIF_DEFAULT_ERROR_MASK;
2614 sci_port->error_clear = SCIF_ERROR_CLEAR;
2615 }
debf9507 2616
3ae988d9
LP		 2617 /*
2618 * Make the error mask inclusive of overrun detection, if
2619 * supported.
2620 */
5da0f468 2621 if (sci_port->overrun_reg == SCxSR) {
afd66db6 2622 sci_port->error_mask |= sci_port->overrun_mask;
5da0f468
GU		 2623 sci_port->error_clear &= ~sci_port->overrun_mask;
2624 }
debf9507 2625
ce6738b6 2626 port->type = p->type;
b6e4a3f1 2627 port->flags = UPF_FIXED_PORT | p->flags;
61a6976b 2628 port->regshift = p->regshift;
73a19e4c 2629
ce6738b6 2630 /*
61a6976b 2631 * The UART port needs an IRQ value, so we peg this to the RX IRQ
ce6738b6
PM		 2632 * for the multi-IRQ ports, which is where we are primarily
2633 * concerned with the shutdown path synchronization.
2634 *
2635 * For the muxed case there's nothing more to do.
2636 */
1fcc91a6 2637 port->irq = sci_port->irqs[SCIx_RXI_IRQ];
9cfb5c05 2638 port->irqflags = 0;
73a19e4c 2639
61a6976b
PM		 2640 port->serial_in = sci_serial_in;
2641 port->serial_out = sci_serial_out;
2642
937bb6e4
GL		 2643 if (p->dma_slave_tx > 0 && p->dma_slave_rx > 0)
2644 dev_dbg(port->dev, "DMA tx %d, rx %d\n",
2645 p->dma_slave_tx, p->dma_slave_rx);
7ed7e071 2646
c7ed1ab3 2647 return 0;
e108b2ca
PM		 2648}
2649
6dae1421
LP		 2650static void sci_cleanup_single(struct sci_port *port)
2651{
6dae1421
LP		 2652 pm_runtime_disable(port->port.dev);
2653}
2654
0b0cced1
YS		 2655#if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \
2656 defined(CONFIG_SERIAL_SH_SCI_EARLYCON)
dc8e6f5b
MD		 2657static void serial_console_putchar(struct uart_port *port, int ch)
2658{
2659 sci_poll_put_char(port, ch);
2660}
2661
1da177e4
LT		 2662/*
2663 * Print a string to the serial port trying not to disturb
2664 * any possible real use of the port...
2665 */
2666static void serial_console_write(struct console *co, const char *s,
2667 unsigned count)
2668{
906b17dc
PM		 2669 struct sci_port *sci_port = &sci_ports[co->index];
2670 struct uart_port *port = &sci_port->port;
a67969b5 2671 unsigned short bits, ctrl, ctrl_temp;
40f70c03
SK		 2672 unsigned long flags;
2673 int locked = 1;
2674
2675 local_irq_save(flags);
0b0cced1 2676#if defined(SUPPORT_SYSRQ)
40f70c03
SK		 2677 if (port->sysrq)
2678 locked = 0;
0b0cced1
YS		 2679 else
2680#endif
2681 if (oops_in_progress)
40f70c03
SK		 2682 locked = spin_trylock(&port->lock);
2683 else
2684 spin_lock(&port->lock);
2685
a67969b5 2686 /* first save SCSCR then disable interrupts, keep clock source */
40f70c03 2687 ctrl = serial_port_in(port, SCSCR);
a67969b5
GU		 2688 ctrl_temp = (sci_port->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)) |
2689 (ctrl & (SCSCR_CKE1 | SCSCR_CKE0));
2690 serial_port_out(port, SCSCR, ctrl_temp);
07d2a1a1 2691
501b825d 2692 uart_console_write(port, s, count, serial_console_putchar);
973e5d52
MD		 2693
2694 /* wait until fifo is empty and last bit has been transmitted */
2695 bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
b12bb29f 2696 while ((serial_port_in(port, SCxSR) & bits) != bits)
973e5d52 2697 cpu_relax();
40f70c03
SK		 2698
2699 /* restore the SCSCR */
2700 serial_port_out(port, SCSCR, ctrl);
2701
2702 if (locked)
2703 spin_unlock(&port->lock);
2704 local_irq_restore(flags);
1da177e4
LT		 2705}
2706
9671f099 2707static int serial_console_setup(struct console *co, char *options)
1da177e4 2708{
dc8e6f5b 2709 struct sci_port *sci_port;
1da177e4
LT		 2710 struct uart_port *port;
2711 int baud = 115200;
2712 int bits = 8;
2713 int parity = 'n';
2714 int flow = 'n';
2715 int ret;
2716
e108b2ca 2717 /*
906b17dc 2718 * Refuse to handle any bogus ports.
1da177e4 2719 */
906b17dc 2720 if (co->index < 0 || co->index >= SCI_NPORTS)
e108b2ca 2721 return -ENODEV;
e108b2ca 2722
906b17dc
PM		 2723 sci_port = &sci_ports[co->index];
2724 port = &sci_port->port;
2725
b2267a6b
AC		 2726 /*
2727 * Refuse to handle uninitialized ports.
2728 */
2729 if (!port->ops)
2730 return -ENODEV;
2731
f6e9495d
PM		 2732 ret = sci_remap_port(port);
2733 if (unlikely(ret != 0))
2734 return ret;
e108b2ca 2735
1da177e4
LT		 2736 if (options)
2737 uart_parse_options(options, &baud, &parity, &bits, &flow);
2738
ab7cfb55 2739 return uart_set_options(port, co, baud, parity, bits, flow);
1da177e4
LT		 2740}
2741
2742static struct console serial_console = {
2743 .name = "ttySC",
906b17dc 2744 .device = uart_console_device,
1da177e4
LT		 2745 .write = serial_console_write,
2746 .setup = serial_console_setup,
fa5da2f7 2747 .flags = CON_PRINTBUFFER,
1da177e4 2748 .index = -1,
906b17dc 2749 .data = &sci_uart_driver,
1da177e4
LT		 2750};
2751
7b6fd3bf
MD		 2752static struct console early_serial_console = {
2753 .name = "early_ttySC",
2754 .write = serial_console_write,
2755 .flags = CON_PRINTBUFFER,
906b17dc 2756 .index = -1,
7b6fd3bf 2757};
ecdf8a46 2758
7b6fd3bf
MD		 2759static char early_serial_buf[32];
2760
9671f099 2761static int sci_probe_earlyprintk(struct platform_device *pdev)
ecdf8a46 2762{
574de559 2763 struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev);
ecdf8a46
PM		 2764
2765 if (early_serial_console.data)
2766 return -EEXIST;
2767
2768 early_serial_console.index = pdev->id;
ecdf8a46 2769
1fcc91a6 2770 sci_init_single(pdev, &sci_ports[pdev->id], pdev->id, cfg, true);
ecdf8a46
PM		 2771
2772 serial_console_setup(&early_serial_console, early_serial_buf);
2773
2774 if (!strstr(early_serial_buf, "keep"))
2775 early_serial_console.flags |= CON_BOOT;
2776
2777 register_console(&early_serial_console);
2778 return 0;
2779}
6a8c9799
NI		 2780
2781#define SCI_CONSOLE (&serial_console)
2782
ecdf8a46 2783#else
9671f099 2784static inline int sci_probe_earlyprintk(struct platform_device *pdev)
ecdf8a46
PM		 2785{
2786 return -EINVAL;
2787}
1da177e4 2788
6a8c9799
NI		 2789#define SCI_CONSOLE NULL
2790
0b0cced1 2791#endif /* CONFIG_SERIAL_SH_SCI_CONSOLE || CONFIG_SERIAL_SH_SCI_EARLYCON */
1da177e4 2792
6c13d5d2 2793static const char banner[] __initconst = "SuperH (H)SCI(F) driver initialized";
1da177e4
LT		 2794
2795static struct uart_driver sci_uart_driver = {
2796 .owner = THIS_MODULE,
2797 .driver_name = "sci",
1da177e4
LT		 2798 .dev_name = "ttySC",
2799 .major = SCI_MAJOR,
2800 .minor = SCI_MINOR_START,
e108b2ca 2801 .nr = SCI_NPORTS,
1da177e4
LT		 2802 .cons = SCI_CONSOLE,
2803};
2804
54507f6e 2805static int sci_remove(struct platform_device *dev)
e552de24 2806{
d535a230 2807 struct sci_port *port = platform_get_drvdata(dev);
e552de24 2808
d535a230
PM		 2809 uart_remove_one_port(&sci_uart_driver, &port->port);
2810
6dae1421 2811 sci_cleanup_single(port);
e552de24 2812
e552de24
MD		 2813 return 0;
2814}
2815
bd2238fb
GU		 2816
2817#define SCI_OF_DATA(type, regtype) (void *)((type) << 16 | (regtype))
2818#define SCI_OF_TYPE(data) ((unsigned long)(data) >> 16)
2819#define SCI_OF_REGTYPE(data) ((unsigned long)(data) & 0xffff)
20bdcab8
BH		 2820
2821static const struct of_device_id of_sci_match[] = {
f443ff80
GU		 2822 /* SoC-specific types */
2823 {
2824 .compatible = "renesas,scif-r7s72100",
2825 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH2_SCIF_FIFODATA_REGTYPE),
2826 },
9ed44bb2
GU		 2827 /* Family-specific types */
2828 {
2829 .compatible = "renesas,rcar-gen1-scif",
2830 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
2831 }, {
2832 .compatible = "renesas,rcar-gen2-scif",
2833 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
2834 }, {
2835 .compatible = "renesas,rcar-gen3-scif",
2836 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
2837 },
f443ff80 2838 /* Generic types */
20bdcab8
BH		 2839 {
2840 .compatible = "renesas,scif",
bd2238fb 2841 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_REGTYPE),
20bdcab8
BH		 2842 }, {
2843 .compatible = "renesas,scifa",
bd2238fb 2844 .data = SCI_OF_DATA(PORT_SCIFA, SCIx_SCIFA_REGTYPE),
20bdcab8
BH		 2845 }, {
2846 .compatible = "renesas,scifb",
bd2238fb 2847 .data = SCI_OF_DATA(PORT_SCIFB, SCIx_SCIFB_REGTYPE),
20bdcab8
BH		 2848 }, {
2849 .compatible = "renesas,hscif",
bd2238fb 2850 .data = SCI_OF_DATA(PORT_HSCIF, SCIx_HSCIF_REGTYPE),
e1d0be61
YS		 2851 }, {
2852 .compatible = "renesas,sci",
bd2238fb 2853 .data = SCI_OF_DATA(PORT_SCI, SCIx_SCI_REGTYPE),
20bdcab8
BH		 2854 }, {
2855 /* Terminator */
2856 },
2857};
2858MODULE_DEVICE_TABLE(of, of_sci_match);
2859
2860static struct plat_sci_port *
2861sci_parse_dt(struct platform_device *pdev, unsigned int *dev_id)
2862{
2863 struct device_node *np = pdev->dev.of_node;
2864 const struct of_device_id *match;
20bdcab8
BH		 2865 struct plat_sci_port *p;
2866 int id;
2867
2868 if (!IS_ENABLED(CONFIG_OF) || !np)
2869 return NULL;
2870
495bb47c 2871 match = of_match_node(of_sci_match, np);
20bdcab8
BH		 2872 if (!match)
2873 return NULL;
2874
20bdcab8 2875 p = devm_kzalloc(&pdev->dev, sizeof(struct plat_sci_port), GFP_KERNEL);
4205463c 2876 if (!p)
20bdcab8 2877 return NULL;
20bdcab8 2878
2095fc76 2879 /* Get the line number from the aliases node. */
20bdcab8
BH		 2880 id = of_alias_get_id(np, "serial");
2881 if (id < 0) {
2882 dev_err(&pdev->dev, "failed to get alias id (%d)\n", id);
2883 return NULL;
2884 }
2885
2886 *dev_id = id;
2887
2888 p->flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF;
bd2238fb
GU		 2889 p->type = SCI_OF_TYPE(match->data);
2890 p->regtype = SCI_OF_REGTYPE(match->data);
20bdcab8
BH		 2891 p->scscr = SCSCR_RE | SCSCR_TE;
2892
2893 return p;
2894}
2895
9671f099 2896static int sci_probe_single(struct platform_device *dev,
0ee70712
MD		 2897 unsigned int index,
2898 struct plat_sci_port *p,
2899 struct sci_port *sciport)
2900{
0ee70712
MD		 2901 int ret;
2902
2903 /* Sanity check */
2904 if (unlikely(index >= SCI_NPORTS)) {
9b971cd2 2905 dev_notice(&dev->dev, "Attempting to register port %d when only %d are available\n",
0ee70712 2906 index+1, SCI_NPORTS);
9b971cd2 2907 dev_notice(&dev->dev, "Consider bumping CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
b6c5ef6f 2908 return -EINVAL;
0ee70712
MD		 2909 }
2910
1fcc91a6 2911 ret = sci_init_single(dev, sciport, index, p, false);
c7ed1ab3
PM		 2912 if (ret)
2913 return ret;
0ee70712 2914
6dae1421
LP		 2915 ret = uart_add_one_port(&sci_uart_driver, &sciport->port);
2916 if (ret) {
2917 sci_cleanup_single(sciport);
2918 return ret;
2919 }
2920
2921 return 0;
0ee70712
MD		 2922}
2923
9671f099 2924static int sci_probe(struct platform_device *dev)
1da177e4 2925{
20bdcab8
BH		 2926 struct plat_sci_port *p;
2927 struct sci_port *sp;
2928 unsigned int dev_id;
ecdf8a46 2929 int ret;
d535a230 2930
ecdf8a46
PM		 2931 /*
2932 * If we've come here via earlyprintk initialization, head off to
2933 * the special early probe. We don't have sufficient device state
2934 * to make it beyond this yet.
2935 */
2936 if (is_early_platform_device(dev))
2937 return sci_probe_earlyprintk(dev);
7b6fd3bf 2938
20bdcab8
BH		 2939 if (dev->dev.of_node) {
2940 p = sci_parse_dt(dev, &dev_id);
2941 if (p == NULL)
2942 return -EINVAL;
2943 } else {
2944 p = dev->dev.platform_data;
2945 if (p == NULL) {
2946 dev_err(&dev->dev, "no platform data supplied\n");
2947 return -EINVAL;
2948 }
2949
2950 dev_id = dev->id;
2951 }
2952
2953 sp = &sci_ports[dev_id];
d535a230 2954 platform_set_drvdata(dev, sp);
e552de24 2955
20bdcab8 2956 ret = sci_probe_single(dev, dev_id, p, sp);
d535a230 2957 if (ret)
6dae1421 2958 return ret;
e552de24 2959
1da177e4
LT		 2960#ifdef CONFIG_SH_STANDARD_BIOS
2961 sh_bios_gdb_detach();
2962#endif
2963
e108b2ca 2964 return 0;
1da177e4
LT		 2965}
2966
cb876341 2967static __maybe_unused int sci_suspend(struct device *dev)
1da177e4 2968{
d535a230 2969 struct sci_port *sport = dev_get_drvdata(dev);
e108b2ca 2970
d535a230
PM		 2971 if (sport)
2972 uart_suspend_port(&sci_uart_driver, &sport->port);
1da177e4 2973
e108b2ca
PM		 2974 return 0;
2975}
1da177e4 2976
cb876341 2977static __maybe_unused int sci_resume(struct device *dev)
e108b2ca 2978{
d535a230 2979 struct sci_port *sport = dev_get_drvdata(dev);
e108b2ca 2980
d535a230
PM		 2981 if (sport)
2982 uart_resume_port(&sci_uart_driver, &sport->port);
e108b2ca
PM		 2983
2984 return 0;
2985}
2986
cb876341 2987static SIMPLE_DEV_PM_OPS(sci_dev_pm_ops, sci_suspend, sci_resume);
6daa79b3 2988
e108b2ca
PM		 2989static struct platform_driver sci_driver = {
2990 .probe = sci_probe,
b9e39c89 2991 .remove = sci_remove,
e108b2ca
PM		 2992 .driver = {
2993 .name = "sh-sci",
6daa79b3 2994 .pm = &sci_dev_pm_ops,
20bdcab8 2995 .of_match_table = of_match_ptr(of_sci_match),
e108b2ca
PM		 2996 },
2997};
2998
2999static int __init sci_init(void)
3000{
3001 int ret;
3002
6c13d5d2 3003 pr_info("%s\n", banner);
e108b2ca 3004
e108b2ca
PM		 3005 ret = uart_register_driver(&sci_uart_driver);
3006 if (likely(ret == 0)) {
3007 ret = platform_driver_register(&sci_driver);
3008 if (unlikely(ret))
3009 uart_unregister_driver(&sci_uart_driver);
3010 }
3011
3012 return ret;
3013}
3014
3015static void __exit sci_exit(void)
3016{
3017 platform_driver_unregister(&sci_driver);
1da177e4
LT		 3018 uart_unregister_driver(&sci_uart_driver);
3019}
3020
7b6fd3bf
MD		 3021#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
3022early_platform_init_buffer("earlyprintk", &sci_driver,
3023 early_serial_buf, ARRAY_SIZE(early_serial_buf));
3024#endif
0b0cced1
YS		 3025#ifdef CONFIG_SERIAL_SH_SCI_EARLYCON
3026static struct __init plat_sci_port port_cfg;
3027
3028static int __init early_console_setup(struct earlycon_device *device,
3029 int type)
3030{
3031 if (!device->port.membase)
3032 return -ENODEV;
3033
3034 device->port.serial_in = sci_serial_in;
3035 device->port.serial_out = sci_serial_out;
3036 device->port.type = type;
3037 memcpy(&sci_ports[0].port, &device->port, sizeof(struct uart_port));
3038 sci_ports[0].cfg = &port_cfg;
3039 sci_ports[0].cfg->type = type;
3040 sci_probe_regmap(sci_ports[0].cfg);
3041 port_cfg.scscr = sci_serial_in(&sci_ports[0].port, SCSCR) |
3042 SCSCR_RE | SCSCR_TE;
3043 sci_serial_out(&sci_ports[0].port, SCSCR, port_cfg.scscr);
3044
3045 device->con->write = serial_console_write;
3046 return 0;
3047}
3048static int __init sci_early_console_setup(struct earlycon_device *device,
3049 const char *opt)
3050{
3051 return early_console_setup(device, PORT_SCI);
3052}
3053static int __init scif_early_console_setup(struct earlycon_device *device,
3054 const char *opt)
3055{
3056 return early_console_setup(device, PORT_SCIF);
3057}
3058static int __init scifa_early_console_setup(struct earlycon_device *device,
3059 const char *opt)
3060{
3061 return early_console_setup(device, PORT_SCIFA);
3062}
3063static int __init scifb_early_console_setup(struct earlycon_device *device,
3064 const char *opt)
3065{
3066 return early_console_setup(device, PORT_SCIFB);
3067}
3068static int __init hscif_early_console_setup(struct earlycon_device *device,
3069 const char *opt)
3070{
3071 return early_console_setup(device, PORT_HSCIF);
3072}
3073
0b0cced1 3074OF_EARLYCON_DECLARE(sci, "renesas,sci", sci_early_console_setup);
0b0cced1 3075OF_EARLYCON_DECLARE(scif, "renesas,scif", scif_early_console_setup);
0b0cced1 3076OF_EARLYCON_DECLARE(scifa, "renesas,scifa", scifa_early_console_setup);
0b0cced1 3077OF_EARLYCON_DECLARE(scifb, "renesas,scifb", scifb_early_console_setup);
0b0cced1
YS		 3078OF_EARLYCON_DECLARE(hscif, "renesas,hscif", hscif_early_console_setup);
3079#endif /* CONFIG_SERIAL_SH_SCI_EARLYCON */
3080
1da177e4
LT		 3081module_init(sci_init);
3082module_exit(sci_exit);
3083
e108b2ca 3084MODULE_LICENSE("GPL");
e169c139 3085MODULE_ALIAS("platform:sh-sci");
7f405f9c 3086MODULE_AUTHOR("Paul Mundt");
f303b364 3087MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver");
Linux 6.x block layer and io_uring tree(s)