Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
1da177e4 LT |
2 | * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO) |
3 | * | |
f43dc23d | 4 | * Copyright (C) 2002 - 2011 Paul Mundt |
f4998e55 | 5 | * Copyright (C) 2015 Glider bvba |
3ea6bc3d | 6 | * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007). |
1da177e4 LT |
7 | * |
8 | * based off of the old drivers/char/sh-sci.c by: | |
9 | * | |
10 | * Copyright (C) 1999, 2000 Niibe Yutaka | |
11 | * Copyright (C) 2000 Sugioka Toshinobu | |
12 | * Modified to support multiple serial ports. Stuart Menefy (May 2000). | |
13 | * Modified to support SecureEdge. David McCullough (2002) | |
14 | * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003). | |
d89ddd1c | 15 | * Removed SH7300 support (Jul 2007). |
1da177e4 LT |
16 | * |
17 | * This file is subject to the terms and conditions of the GNU General Public | |
18 | * License. See the file "COPYING" in the main directory of this archive | |
19 | * for more details. | |
20 | */ | |
0b3d4ef6 PM |
21 | #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) |
22 | #define SUPPORT_SYSRQ | |
23 | #endif | |
1da177e4 LT |
24 | |
25 | #undef DEBUG | |
26 | ||
8fb9631c LP |
27 | #include <linux/clk.h> |
28 | #include <linux/console.h> | |
29 | #include <linux/ctype.h> | |
30 | #include <linux/cpufreq.h> | |
31 | #include <linux/delay.h> | |
32 | #include <linux/dmaengine.h> | |
33 | #include <linux/dma-mapping.h> | |
34 | #include <linux/err.h> | |
1da177e4 | 35 | #include <linux/errno.h> |
8fb9631c | 36 | #include <linux/init.h> |
1da177e4 | 37 | #include <linux/interrupt.h> |
1da177e4 | 38 | #include <linux/ioport.h> |
8fb9631c LP |
39 | #include <linux/major.h> |
40 | #include <linux/module.h> | |
1da177e4 | 41 | #include <linux/mm.h> |
20bdcab8 | 42 | #include <linux/of.h> |
8fb9631c | 43 | #include <linux/platform_device.h> |
5e50d2d6 | 44 | #include <linux/pm_runtime.h> |
73a19e4c | 45 | #include <linux/scatterlist.h> |
8fb9631c LP |
46 | #include <linux/serial.h> |
47 | #include <linux/serial_sci.h> | |
48 | #include <linux/sh_dma.h> | |
5a0e3ad6 | 49 | #include <linux/slab.h> |
8fb9631c LP |
50 | #include <linux/string.h> |
51 | #include <linux/sysrq.h> | |
52 | #include <linux/timer.h> | |
53 | #include <linux/tty.h> | |
54 | #include <linux/tty_flip.h> | |
85f094ec PM |
55 | |
56 | #ifdef CONFIG_SUPERH | |
1da177e4 LT |
57 | #include <asm/sh_bios.h> |
58 | #endif | |
59 | ||
1da177e4 LT |
60 | #include "sh-sci.h" |
61 | ||
89b5c1ab LP |
62 | /* Offsets into the sci_port->irqs array */ |
63 | enum { | |
64 | SCIx_ERI_IRQ, | |
65 | SCIx_RXI_IRQ, | |
66 | SCIx_TXI_IRQ, | |
67 | SCIx_BRI_IRQ, | |
68 | SCIx_NR_IRQS, | |
69 | ||
70 | SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */ | |
71 | }; | |
72 | ||
73 | #define SCIx_IRQ_IS_MUXED(port) \ | |
74 | ((port)->irqs[SCIx_ERI_IRQ] == \ | |
75 | (port)->irqs[SCIx_RXI_IRQ]) || \ | |
76 | ((port)->irqs[SCIx_ERI_IRQ] && \ | |
77 | ((port)->irqs[SCIx_RXI_IRQ] < 0)) | |
78 | ||
f4998e55 GU |
79 | enum SCI_CLKS { |
80 | SCI_FCK, /* Functional Clock */ | |
6af27bf2 | 81 | SCI_SCK, /* Optional External Clock */ |
1270f865 GU |
82 | SCI_BRG_INT, /* Optional BRG Internal Clock Source */ |
83 | SCI_SCIF_CLK, /* Optional BRG External Clock Source */ | |
f4998e55 GU |
84 | SCI_NUM_CLKS |
85 | }; | |
86 | ||
e108b2ca PM |
87 | struct sci_port { |
88 | struct uart_port port; | |
89 | ||
ce6738b6 PM |
90 | /* Platform configuration */ |
91 | struct plat_sci_port *cfg; | |
2e0842a1 | 92 | unsigned int overrun_reg; |
75c249fd | 93 | unsigned int overrun_mask; |
3ae988d9 | 94 | unsigned int error_mask; |
5da0f468 | 95 | unsigned int error_clear; |
ec09c5eb | 96 | unsigned int sampling_rate; |
e4d6f911 | 97 | resource_size_t reg_size; |
e108b2ca | 98 | |
e108b2ca PM |
99 | /* Break timer */ |
100 | struct timer_list break_timer; | |
101 | int break_flag; | |
1534a3b3 | 102 | |
f4998e55 GU |
103 | /* Clocks */ |
104 | struct clk *clks[SCI_NUM_CLKS]; | |
105 | unsigned long clk_rates[SCI_NUM_CLKS]; | |
edad1f20 | 106 | |
1fcc91a6 | 107 | int irqs[SCIx_NR_IRQS]; |
9174fc8f PM |
108 | char *irqstr[SCIx_NR_IRQS]; |
109 | ||
73a19e4c GL |
110 | struct dma_chan *chan_tx; |
111 | struct dma_chan *chan_rx; | |
f43dc23d | 112 | |
73a19e4c | 113 | #ifdef CONFIG_SERIAL_SH_SCI_DMA |
73a19e4c GL |
114 | dma_cookie_t cookie_tx; |
115 | dma_cookie_t cookie_rx[2]; | |
116 | dma_cookie_t active_rx; | |
79904420 GU |
117 | dma_addr_t tx_dma_addr; |
118 | unsigned int tx_dma_len; | |
73a19e4c | 119 | struct scatterlist sg_rx[2]; |
7b39d901 | 120 | void *rx_buf[2]; |
73a19e4c | 121 | size_t buf_len_rx; |
73a19e4c | 122 | struct work_struct work_tx; |
73a19e4c | 123 | struct timer_list rx_timer; |
3089f381 | 124 | unsigned int rx_timeout; |
73a19e4c | 125 | #endif |
e108b2ca PM |
126 | }; |
127 | ||
e108b2ca | 128 | #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS |
b7a76e4b | 129 | |
e108b2ca PM |
130 | static struct sci_port sci_ports[SCI_NPORTS]; |
131 | static struct uart_driver sci_uart_driver; | |
1da177e4 | 132 | |
e7c98dc7 MT |
133 | static inline struct sci_port * |
134 | to_sci_port(struct uart_port *uart) | |
135 | { | |
136 | return container_of(uart, struct sci_port, port); | |
137 | } | |
138 | ||
61a6976b PM |
139 | struct plat_sci_reg { |
140 | u8 offset, size; | |
141 | }; | |
142 | ||
143 | /* Helper for invalidating specific entries of an inherited map. */ | |
144 | #define sci_reg_invalid { .offset = 0, .size = 0 } | |
145 | ||
d3184e68 | 146 | static const struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = { |
61a6976b PM |
147 | [SCIx_PROBE_REGTYPE] = { |
148 | [0 ... SCIx_NR_REGS - 1] = sci_reg_invalid, | |
149 | }, | |
150 | ||
151 | /* | |
152 | * Common SCI definitions, dependent on the port's regshift | |
153 | * value. | |
154 | */ | |
155 | [SCIx_SCI_REGTYPE] = { | |
156 | [SCSMR] = { 0x00, 8 }, | |
157 | [SCBRR] = { 0x01, 8 }, | |
158 | [SCSCR] = { 0x02, 8 }, | |
159 | [SCxTDR] = { 0x03, 8 }, | |
160 | [SCxSR] = { 0x04, 8 }, | |
161 | [SCxRDR] = { 0x05, 8 }, | |
162 | [SCFCR] = sci_reg_invalid, | |
163 | [SCFDR] = sci_reg_invalid, | |
164 | [SCTFDR] = sci_reg_invalid, | |
165 | [SCRFDR] = sci_reg_invalid, | |
166 | [SCSPTR] = sci_reg_invalid, | |
167 | [SCLSR] = sci_reg_invalid, | |
f303b364 | 168 | [HSSRR] = sci_reg_invalid, |
c097abc3 GU |
169 | [SCPCR] = sci_reg_invalid, |
170 | [SCPDR] = sci_reg_invalid, | |
b8bbd6b2 GU |
171 | [SCDL] = sci_reg_invalid, |
172 | [SCCKS] = sci_reg_invalid, | |
61a6976b PM |
173 | }, |
174 | ||
175 | /* | |
176 | * Common definitions for legacy IrDA ports, dependent on | |
177 | * regshift value. | |
178 | */ | |
179 | [SCIx_IRDA_REGTYPE] = { | |
180 | [SCSMR] = { 0x00, 8 }, | |
181 | [SCBRR] = { 0x01, 8 }, | |
182 | [SCSCR] = { 0x02, 8 }, | |
183 | [SCxTDR] = { 0x03, 8 }, | |
184 | [SCxSR] = { 0x04, 8 }, | |
185 | [SCxRDR] = { 0x05, 8 }, | |
186 | [SCFCR] = { 0x06, 8 }, | |
187 | [SCFDR] = { 0x07, 16 }, | |
188 | [SCTFDR] = sci_reg_invalid, | |
189 | [SCRFDR] = sci_reg_invalid, | |
190 | [SCSPTR] = sci_reg_invalid, | |
191 | [SCLSR] = sci_reg_invalid, | |
f303b364 | 192 | [HSSRR] = sci_reg_invalid, |
c097abc3 GU |
193 | [SCPCR] = sci_reg_invalid, |
194 | [SCPDR] = sci_reg_invalid, | |
b8bbd6b2 GU |
195 | [SCDL] = sci_reg_invalid, |
196 | [SCCKS] = sci_reg_invalid, | |
61a6976b PM |
197 | }, |
198 | ||
199 | /* | |
200 | * Common SCIFA definitions. | |
201 | */ | |
202 | [SCIx_SCIFA_REGTYPE] = { | |
203 | [SCSMR] = { 0x00, 16 }, | |
204 | [SCBRR] = { 0x04, 8 }, | |
205 | [SCSCR] = { 0x08, 16 }, | |
206 | [SCxTDR] = { 0x20, 8 }, | |
207 | [SCxSR] = { 0x14, 16 }, | |
208 | [SCxRDR] = { 0x24, 8 }, | |
209 | [SCFCR] = { 0x18, 16 }, | |
210 | [SCFDR] = { 0x1c, 16 }, | |
211 | [SCTFDR] = sci_reg_invalid, | |
212 | [SCRFDR] = sci_reg_invalid, | |
213 | [SCSPTR] = sci_reg_invalid, | |
214 | [SCLSR] = sci_reg_invalid, | |
f303b364 | 215 | [HSSRR] = sci_reg_invalid, |
c097abc3 GU |
216 | [SCPCR] = { 0x30, 16 }, |
217 | [SCPDR] = { 0x34, 16 }, | |
b8bbd6b2 GU |
218 | [SCDL] = sci_reg_invalid, |
219 | [SCCKS] = sci_reg_invalid, | |
61a6976b PM |
220 | }, |
221 | ||
222 | /* | |
223 | * Common SCIFB definitions. | |
224 | */ | |
225 | [SCIx_SCIFB_REGTYPE] = { | |
226 | [SCSMR] = { 0x00, 16 }, | |
227 | [SCBRR] = { 0x04, 8 }, | |
228 | [SCSCR] = { 0x08, 16 }, | |
229 | [SCxTDR] = { 0x40, 8 }, | |
230 | [SCxSR] = { 0x14, 16 }, | |
231 | [SCxRDR] = { 0x60, 8 }, | |
232 | [SCFCR] = { 0x18, 16 }, | |
8c66d6d2 TY |
233 | [SCFDR] = sci_reg_invalid, |
234 | [SCTFDR] = { 0x38, 16 }, | |
235 | [SCRFDR] = { 0x3c, 16 }, | |
61a6976b PM |
236 | [SCSPTR] = sci_reg_invalid, |
237 | [SCLSR] = sci_reg_invalid, | |
f303b364 | 238 | [HSSRR] = sci_reg_invalid, |
c097abc3 GU |
239 | [SCPCR] = { 0x30, 16 }, |
240 | [SCPDR] = { 0x34, 16 }, | |
b8bbd6b2 GU |
241 | [SCDL] = sci_reg_invalid, |
242 | [SCCKS] = sci_reg_invalid, | |
61a6976b PM |
243 | }, |
244 | ||
3af1f8a4 PE |
245 | /* |
246 | * Common SH-2(A) SCIF definitions for ports with FIFO data | |
247 | * count registers. | |
248 | */ | |
249 | [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = { | |
250 | [SCSMR] = { 0x00, 16 }, | |
251 | [SCBRR] = { 0x04, 8 }, | |
252 | [SCSCR] = { 0x08, 16 }, | |
253 | [SCxTDR] = { 0x0c, 8 }, | |
254 | [SCxSR] = { 0x10, 16 }, | |
255 | [SCxRDR] = { 0x14, 8 }, | |
256 | [SCFCR] = { 0x18, 16 }, | |
257 | [SCFDR] = { 0x1c, 16 }, | |
258 | [SCTFDR] = sci_reg_invalid, | |
259 | [SCRFDR] = sci_reg_invalid, | |
260 | [SCSPTR] = { 0x20, 16 }, | |
261 | [SCLSR] = { 0x24, 16 }, | |
f303b364 | 262 | [HSSRR] = sci_reg_invalid, |
c097abc3 GU |
263 | [SCPCR] = sci_reg_invalid, |
264 | [SCPDR] = sci_reg_invalid, | |
b8bbd6b2 GU |
265 | [SCDL] = sci_reg_invalid, |
266 | [SCCKS] = sci_reg_invalid, | |
3af1f8a4 PE |
267 | }, |
268 | ||
61a6976b PM |
269 | /* |
270 | * Common SH-3 SCIF definitions. | |
271 | */ | |
272 | [SCIx_SH3_SCIF_REGTYPE] = { | |
273 | [SCSMR] = { 0x00, 8 }, | |
274 | [SCBRR] = { 0x02, 8 }, | |
275 | [SCSCR] = { 0x04, 8 }, | |
276 | [SCxTDR] = { 0x06, 8 }, | |
277 | [SCxSR] = { 0x08, 16 }, | |
278 | [SCxRDR] = { 0x0a, 8 }, | |
279 | [SCFCR] = { 0x0c, 8 }, | |
280 | [SCFDR] = { 0x0e, 16 }, | |
281 | [SCTFDR] = sci_reg_invalid, | |
282 | [SCRFDR] = sci_reg_invalid, | |
283 | [SCSPTR] = sci_reg_invalid, | |
284 | [SCLSR] = sci_reg_invalid, | |
f303b364 | 285 | [HSSRR] = sci_reg_invalid, |
c097abc3 GU |
286 | [SCPCR] = sci_reg_invalid, |
287 | [SCPDR] = sci_reg_invalid, | |
b8bbd6b2 GU |
288 | [SCDL] = sci_reg_invalid, |
289 | [SCCKS] = sci_reg_invalid, | |
61a6976b PM |
290 | }, |
291 | ||
292 | /* | |
293 | * Common SH-4(A) SCIF(B) definitions. | |
294 | */ | |
295 | [SCIx_SH4_SCIF_REGTYPE] = { | |
296 | [SCSMR] = { 0x00, 16 }, | |
297 | [SCBRR] = { 0x04, 8 }, | |
298 | [SCSCR] = { 0x08, 16 }, | |
299 | [SCxTDR] = { 0x0c, 8 }, | |
300 | [SCxSR] = { 0x10, 16 }, | |
301 | [SCxRDR] = { 0x14, 8 }, | |
302 | [SCFCR] = { 0x18, 16 }, | |
303 | [SCFDR] = { 0x1c, 16 }, | |
304 | [SCTFDR] = sci_reg_invalid, | |
305 | [SCRFDR] = sci_reg_invalid, | |
306 | [SCSPTR] = { 0x20, 16 }, | |
307 | [SCLSR] = { 0x24, 16 }, | |
f303b364 | 308 | [HSSRR] = sci_reg_invalid, |
c097abc3 GU |
309 | [SCPCR] = sci_reg_invalid, |
310 | [SCPDR] = sci_reg_invalid, | |
b8bbd6b2 GU |
311 | [SCDL] = sci_reg_invalid, |
312 | [SCCKS] = sci_reg_invalid, | |
313 | }, | |
314 | ||
315 | /* | |
316 | * Common SCIF definitions for ports with a Baud Rate Generator for | |
317 | * External Clock (BRG). | |
318 | */ | |
319 | [SCIx_SH4_SCIF_BRG_REGTYPE] = { | |
320 | [SCSMR] = { 0x00, 16 }, | |
321 | [SCBRR] = { 0x04, 8 }, | |
322 | [SCSCR] = { 0x08, 16 }, | |
323 | [SCxTDR] = { 0x0c, 8 }, | |
324 | [SCxSR] = { 0x10, 16 }, | |
325 | [SCxRDR] = { 0x14, 8 }, | |
326 | [SCFCR] = { 0x18, 16 }, | |
327 | [SCFDR] = { 0x1c, 16 }, | |
328 | [SCTFDR] = sci_reg_invalid, | |
329 | [SCRFDR] = sci_reg_invalid, | |
330 | [SCSPTR] = { 0x20, 16 }, | |
331 | [SCLSR] = { 0x24, 16 }, | |
332 | [HSSRR] = sci_reg_invalid, | |
333 | [SCPCR] = sci_reg_invalid, | |
334 | [SCPDR] = sci_reg_invalid, | |
335 | [SCDL] = { 0x30, 16 }, | |
336 | [SCCKS] = { 0x34, 16 }, | |
f303b364 UH |
337 | }, |
338 | ||
339 | /* | |
340 | * Common HSCIF definitions. | |
341 | */ | |
342 | [SCIx_HSCIF_REGTYPE] = { | |
343 | [SCSMR] = { 0x00, 16 }, | |
344 | [SCBRR] = { 0x04, 8 }, | |
345 | [SCSCR] = { 0x08, 16 }, | |
346 | [SCxTDR] = { 0x0c, 8 }, | |
347 | [SCxSR] = { 0x10, 16 }, | |
348 | [SCxRDR] = { 0x14, 8 }, | |
349 | [SCFCR] = { 0x18, 16 }, | |
350 | [SCFDR] = { 0x1c, 16 }, | |
351 | [SCTFDR] = sci_reg_invalid, | |
352 | [SCRFDR] = sci_reg_invalid, | |
353 | [SCSPTR] = { 0x20, 16 }, | |
354 | [SCLSR] = { 0x24, 16 }, | |
355 | [HSSRR] = { 0x40, 16 }, | |
c097abc3 GU |
356 | [SCPCR] = sci_reg_invalid, |
357 | [SCPDR] = sci_reg_invalid, | |
b8bbd6b2 GU |
358 | [SCDL] = { 0x30, 16 }, |
359 | [SCCKS] = { 0x34, 16 }, | |
61a6976b PM |
360 | }, |
361 | ||
362 | /* | |
363 | * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR | |
364 | * register. | |
365 | */ | |
366 | [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = { | |
367 | [SCSMR] = { 0x00, 16 }, | |
368 | [SCBRR] = { 0x04, 8 }, | |
369 | [SCSCR] = { 0x08, 16 }, | |
370 | [SCxTDR] = { 0x0c, 8 }, | |
371 | [SCxSR] = { 0x10, 16 }, | |
372 | [SCxRDR] = { 0x14, 8 }, | |
373 | [SCFCR] = { 0x18, 16 }, | |
374 | [SCFDR] = { 0x1c, 16 }, | |
375 | [SCTFDR] = sci_reg_invalid, | |
376 | [SCRFDR] = sci_reg_invalid, | |
377 | [SCSPTR] = sci_reg_invalid, | |
378 | [SCLSR] = { 0x24, 16 }, | |
f303b364 | 379 | [HSSRR] = sci_reg_invalid, |
c097abc3 GU |
380 | [SCPCR] = sci_reg_invalid, |
381 | [SCPDR] = sci_reg_invalid, | |
b8bbd6b2 GU |
382 | [SCDL] = sci_reg_invalid, |
383 | [SCCKS] = sci_reg_invalid, | |
61a6976b PM |
384 | }, |
385 | ||
386 | /* | |
387 | * Common SH-4(A) SCIF(B) definitions for ports with FIFO data | |
388 | * count registers. | |
389 | */ | |
390 | [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = { | |
391 | [SCSMR] = { 0x00, 16 }, | |
392 | [SCBRR] = { 0x04, 8 }, | |
393 | [SCSCR] = { 0x08, 16 }, | |
394 | [SCxTDR] = { 0x0c, 8 }, | |
395 | [SCxSR] = { 0x10, 16 }, | |
396 | [SCxRDR] = { 0x14, 8 }, | |
397 | [SCFCR] = { 0x18, 16 }, | |
398 | [SCFDR] = { 0x1c, 16 }, | |
399 | [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */ | |
400 | [SCRFDR] = { 0x20, 16 }, | |
401 | [SCSPTR] = { 0x24, 16 }, | |
402 | [SCLSR] = { 0x28, 16 }, | |
f303b364 | 403 | [HSSRR] = sci_reg_invalid, |
c097abc3 GU |
404 | [SCPCR] = sci_reg_invalid, |
405 | [SCPDR] = sci_reg_invalid, | |
b8bbd6b2 GU |
406 | [SCDL] = sci_reg_invalid, |
407 | [SCCKS] = sci_reg_invalid, | |
61a6976b PM |
408 | }, |
409 | ||
410 | /* | |
411 | * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR | |
412 | * registers. | |
413 | */ | |
414 | [SCIx_SH7705_SCIF_REGTYPE] = { | |
415 | [SCSMR] = { 0x00, 16 }, | |
416 | [SCBRR] = { 0x04, 8 }, | |
417 | [SCSCR] = { 0x08, 16 }, | |
418 | [SCxTDR] = { 0x20, 8 }, | |
419 | [SCxSR] = { 0x14, 16 }, | |
420 | [SCxRDR] = { 0x24, 8 }, | |
421 | [SCFCR] = { 0x18, 16 }, | |
422 | [SCFDR] = { 0x1c, 16 }, | |
423 | [SCTFDR] = sci_reg_invalid, | |
424 | [SCRFDR] = sci_reg_invalid, | |
425 | [SCSPTR] = sci_reg_invalid, | |
426 | [SCLSR] = sci_reg_invalid, | |
f303b364 | 427 | [HSSRR] = sci_reg_invalid, |
c097abc3 GU |
428 | [SCPCR] = sci_reg_invalid, |
429 | [SCPDR] = sci_reg_invalid, | |
b8bbd6b2 GU |
430 | [SCDL] = sci_reg_invalid, |
431 | [SCCKS] = sci_reg_invalid, | |
61a6976b PM |
432 | }, |
433 | }; | |
434 | ||
72b294cf PM |
435 | #define sci_getreg(up, offset) (sci_regmap[to_sci_port(up)->cfg->regtype] + offset) |
436 | ||
61a6976b PM |
437 | /* |
438 | * The "offset" here is rather misleading, in that it refers to an enum | |
439 | * value relative to the port mapping rather than the fixed offset | |
440 | * itself, which needs to be manually retrieved from the platform's | |
441 | * register map for the given port. | |
442 | */ | |
443 | static unsigned int sci_serial_in(struct uart_port *p, int offset) | |
444 | { | |
d3184e68 | 445 | const struct plat_sci_reg *reg = sci_getreg(p, offset); |
61a6976b PM |
446 | |
447 | if (reg->size == 8) | |
448 | return ioread8(p->membase + (reg->offset << p->regshift)); | |
449 | else if (reg->size == 16) | |
450 | return ioread16(p->membase + (reg->offset << p->regshift)); | |
451 | else | |
452 | WARN(1, "Invalid register access\n"); | |
453 | ||
454 | return 0; | |
455 | } | |
456 | ||
457 | static void sci_serial_out(struct uart_port *p, int offset, int value) | |
458 | { | |
d3184e68 | 459 | const struct plat_sci_reg *reg = sci_getreg(p, offset); |
61a6976b PM |
460 | |
461 | if (reg->size == 8) | |
462 | iowrite8(value, p->membase + (reg->offset << p->regshift)); | |
463 | else if (reg->size == 16) | |
464 | iowrite16(value, p->membase + (reg->offset << p->regshift)); | |
465 | else | |
466 | WARN(1, "Invalid register access\n"); | |
467 | } | |
468 | ||
61a6976b PM |
469 | static int sci_probe_regmap(struct plat_sci_port *cfg) |
470 | { | |
471 | switch (cfg->type) { | |
472 | case PORT_SCI: | |
473 | cfg->regtype = SCIx_SCI_REGTYPE; | |
474 | break; | |
475 | case PORT_IRDA: | |
476 | cfg->regtype = SCIx_IRDA_REGTYPE; | |
477 | break; | |
478 | case PORT_SCIFA: | |
479 | cfg->regtype = SCIx_SCIFA_REGTYPE; | |
480 | break; | |
481 | case PORT_SCIFB: | |
482 | cfg->regtype = SCIx_SCIFB_REGTYPE; | |
483 | break; | |
484 | case PORT_SCIF: | |
485 | /* | |
486 | * The SH-4 is a bit of a misnomer here, although that's | |
487 | * where this particular port layout originated. This | |
488 | * configuration (or some slight variation thereof) | |
489 | * remains the dominant model for all SCIFs. | |
490 | */ | |
491 | cfg->regtype = SCIx_SH4_SCIF_REGTYPE; | |
492 | break; | |
f303b364 UH |
493 | case PORT_HSCIF: |
494 | cfg->regtype = SCIx_HSCIF_REGTYPE; | |
495 | break; | |
61a6976b | 496 | default: |
6c13d5d2 | 497 | pr_err("Can't probe register map for given port\n"); |
61a6976b PM |
498 | return -EINVAL; |
499 | } | |
500 | ||
501 | return 0; | |
502 | } | |
503 | ||
23241d43 PM |
504 | static void sci_port_enable(struct sci_port *sci_port) |
505 | { | |
f4998e55 GU |
506 | unsigned int i; |
507 | ||
23241d43 PM |
508 | if (!sci_port->port.dev) |
509 | return; | |
510 | ||
511 | pm_runtime_get_sync(sci_port->port.dev); | |
512 | ||
f4998e55 GU |
513 | for (i = 0; i < SCI_NUM_CLKS; i++) { |
514 | clk_prepare_enable(sci_port->clks[i]); | |
515 | sci_port->clk_rates[i] = clk_get_rate(sci_port->clks[i]); | |
516 | } | |
517 | sci_port->port.uartclk = sci_port->clk_rates[SCI_FCK]; | |
23241d43 PM |
518 | } |
519 | ||
520 | static void sci_port_disable(struct sci_port *sci_port) | |
521 | { | |
f4998e55 GU |
522 | unsigned int i; |
523 | ||
23241d43 PM |
524 | if (!sci_port->port.dev) |
525 | return; | |
526 | ||
caec7038 LP |
527 | /* Cancel the break timer to ensure that the timer handler will not try |
528 | * to access the hardware with clocks and power disabled. Reset the | |
529 | * break flag to make the break debouncing state machine ready for the | |
530 | * next break. | |
531 | */ | |
532 | del_timer_sync(&sci_port->break_timer); | |
533 | sci_port->break_flag = 0; | |
534 | ||
f4998e55 GU |
535 | for (i = SCI_NUM_CLKS; i-- > 0; ) |
536 | clk_disable_unprepare(sci_port->clks[i]); | |
23241d43 PM |
537 | |
538 | pm_runtime_put_sync(sci_port->port.dev); | |
539 | } | |
540 | ||
e1910fcd GU |
541 | static inline unsigned long port_rx_irq_mask(struct uart_port *port) |
542 | { | |
543 | /* | |
544 | * Not all ports (such as SCIFA) will support REIE. Rather than | |
545 | * special-casing the port type, we check the port initialization | |
546 | * IRQ enable mask to see whether the IRQ is desired at all. If | |
547 | * it's unset, it's logically inferred that there's no point in | |
548 | * testing for it. | |
549 | */ | |
550 | return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE); | |
551 | } | |
552 | ||
553 | static void sci_start_tx(struct uart_port *port) | |
554 | { | |
555 | struct sci_port *s = to_sci_port(port); | |
556 | unsigned short ctrl; | |
557 | ||
558 | #ifdef CONFIG_SERIAL_SH_SCI_DMA | |
559 | if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { | |
560 | u16 new, scr = serial_port_in(port, SCSCR); | |
561 | if (s->chan_tx) | |
562 | new = scr | SCSCR_TDRQE; | |
563 | else | |
564 | new = scr & ~SCSCR_TDRQE; | |
565 | if (new != scr) | |
566 | serial_port_out(port, SCSCR, new); | |
567 | } | |
568 | ||
569 | if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) && | |
570 | dma_submit_error(s->cookie_tx)) { | |
571 | s->cookie_tx = 0; | |
572 | schedule_work(&s->work_tx); | |
573 | } | |
574 | #endif | |
575 | ||
576 | if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) { | |
577 | /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */ | |
578 | ctrl = serial_port_in(port, SCSCR); | |
579 | serial_port_out(port, SCSCR, ctrl | SCSCR_TIE); | |
580 | } | |
581 | } | |
582 | ||
583 | static void sci_stop_tx(struct uart_port *port) | |
584 | { | |
585 | unsigned short ctrl; | |
586 | ||
587 | /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */ | |
588 | ctrl = serial_port_in(port, SCSCR); | |
589 | ||
590 | if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) | |
591 | ctrl &= ~SCSCR_TDRQE; | |
592 | ||
593 | ctrl &= ~SCSCR_TIE; | |
594 | ||
595 | serial_port_out(port, SCSCR, ctrl); | |
596 | } | |
597 | ||
598 | static void sci_start_rx(struct uart_port *port) | |
599 | { | |
600 | unsigned short ctrl; | |
601 | ||
602 | ctrl = serial_port_in(port, SCSCR) | port_rx_irq_mask(port); | |
603 | ||
604 | if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) | |
605 | ctrl &= ~SCSCR_RDRQE; | |
606 | ||
607 | serial_port_out(port, SCSCR, ctrl); | |
608 | } | |
609 | ||
610 | static void sci_stop_rx(struct uart_port *port) | |
611 | { | |
612 | unsigned short ctrl; | |
613 | ||
614 | ctrl = serial_port_in(port, SCSCR); | |
615 | ||
616 | if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) | |
617 | ctrl &= ~SCSCR_RDRQE; | |
618 | ||
619 | ctrl &= ~port_rx_irq_mask(port); | |
620 | ||
621 | serial_port_out(port, SCSCR, ctrl); | |
622 | } | |
623 | ||
a1b5b43f GU |
624 | static void sci_clear_SCxSR(struct uart_port *port, unsigned int mask) |
625 | { | |
626 | if (port->type == PORT_SCI) { | |
627 | /* Just store the mask */ | |
628 | serial_port_out(port, SCxSR, mask); | |
629 | } else if (to_sci_port(port)->overrun_mask == SCIFA_ORER) { | |
630 | /* SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721 */ | |
631 | /* Only clear the status bits we want to clear */ | |
632 | serial_port_out(port, SCxSR, | |
633 | serial_port_in(port, SCxSR) & mask); | |
634 | } else { | |
635 | /* Store the mask, clear parity/framing errors */ | |
636 | serial_port_out(port, SCxSR, mask & ~(SCIF_FERC | SCIF_PERC)); | |
637 | } | |
638 | } | |
639 | ||
0b0cced1 YS |
640 | #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \ |
641 | defined(CONFIG_SERIAL_SH_SCI_EARLYCON) | |
1f6fd5c9 PM |
642 | |
643 | #ifdef CONFIG_CONSOLE_POLL | |
07d2a1a1 | 644 | static int sci_poll_get_char(struct uart_port *port) |
1da177e4 | 645 | { |
1da177e4 LT |
646 | unsigned short status; |
647 | int c; | |
648 | ||
e108b2ca | 649 | do { |
b12bb29f | 650 | status = serial_port_in(port, SCxSR); |
1da177e4 | 651 | if (status & SCxSR_ERRORS(port)) { |
a1b5b43f | 652 | sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port)); |
1da177e4 LT |
653 | continue; |
654 | } | |
3f255eb3 JW |
655 | break; |
656 | } while (1); | |
657 | ||
658 | if (!(status & SCxSR_RDxF(port))) | |
659 | return NO_POLL_CHAR; | |
07d2a1a1 | 660 | |
b12bb29f | 661 | c = serial_port_in(port, SCxRDR); |
07d2a1a1 | 662 | |
e7c98dc7 | 663 | /* Dummy read */ |
b12bb29f | 664 | serial_port_in(port, SCxSR); |
a1b5b43f | 665 | sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port)); |
1da177e4 LT |
666 | |
667 | return c; | |
668 | } | |
1f6fd5c9 | 669 | #endif |
1da177e4 | 670 | |
07d2a1a1 | 671 | static void sci_poll_put_char(struct uart_port *port, unsigned char c) |
1da177e4 | 672 | { |
1da177e4 LT |
673 | unsigned short status; |
674 | ||
1da177e4 | 675 | do { |
b12bb29f | 676 | status = serial_port_in(port, SCxSR); |
1da177e4 LT |
677 | } while (!(status & SCxSR_TDxE(port))); |
678 | ||
b12bb29f | 679 | serial_port_out(port, SCxTDR, c); |
a1b5b43f | 680 | sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port)); |
1da177e4 | 681 | } |
0b0cced1 YS |
682 | #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE || |
683 | CONFIG_SERIAL_SH_SCI_EARLYCON */ | |
1da177e4 | 684 | |
61a6976b | 685 | static void sci_init_pins(struct uart_port *port, unsigned int cflag) |
1da177e4 | 686 | { |
61a6976b | 687 | struct sci_port *s = to_sci_port(port); |
d3184e68 | 688 | const struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR; |
1da177e4 | 689 | |
61a6976b PM |
690 | /* |
691 | * Use port-specific handler if provided. | |
692 | */ | |
693 | if (s->cfg->ops && s->cfg->ops->init_pins) { | |
694 | s->cfg->ops->init_pins(port, cflag); | |
695 | return; | |
1da177e4 | 696 | } |
41504c39 | 697 | |
61a6976b PM |
698 | /* |
699 | * For the generic path SCSPTR is necessary. Bail out if that's | |
700 | * unavailable, too. | |
701 | */ | |
702 | if (!reg->size) | |
703 | return; | |
41504c39 | 704 | |
faf02f8f PM |
705 | if ((s->cfg->capabilities & SCIx_HAVE_RTSCTS) && |
706 | ((!(cflag & CRTSCTS)))) { | |
707 | unsigned short status; | |
708 | ||
b12bb29f | 709 | status = serial_port_in(port, SCSPTR); |
faf02f8f PM |
710 | status &= ~SCSPTR_CTSIO; |
711 | status |= SCSPTR_RTSIO; | |
b12bb29f | 712 | serial_port_out(port, SCSPTR, status); /* Set RTS = 1 */ |
faf02f8f | 713 | } |
d5701647 | 714 | } |
e108b2ca | 715 | |
72b294cf | 716 | static int sci_txfill(struct uart_port *port) |
e108b2ca | 717 | { |
d3184e68 | 718 | const struct plat_sci_reg *reg; |
e108b2ca | 719 | |
72b294cf PM |
720 | reg = sci_getreg(port, SCTFDR); |
721 | if (reg->size) | |
63f7ad11 | 722 | return serial_port_in(port, SCTFDR) & ((port->fifosize << 1) - 1); |
c63847a3 | 723 | |
72b294cf PM |
724 | reg = sci_getreg(port, SCFDR); |
725 | if (reg->size) | |
b12bb29f | 726 | return serial_port_in(port, SCFDR) >> 8; |
d1d4b10c | 727 | |
b12bb29f | 728 | return !(serial_port_in(port, SCxSR) & SCI_TDRE); |
e108b2ca PM |
729 | } |
730 | ||
73a19e4c GL |
731 | static int sci_txroom(struct uart_port *port) |
732 | { | |
72b294cf | 733 | return port->fifosize - sci_txfill(port); |
73a19e4c GL |
734 | } |
735 | ||
736 | static int sci_rxfill(struct uart_port *port) | |
e108b2ca | 737 | { |
d3184e68 | 738 | const struct plat_sci_reg *reg; |
72b294cf PM |
739 | |
740 | reg = sci_getreg(port, SCRFDR); | |
741 | if (reg->size) | |
63f7ad11 | 742 | return serial_port_in(port, SCRFDR) & ((port->fifosize << 1) - 1); |
72b294cf PM |
743 | |
744 | reg = sci_getreg(port, SCFDR); | |
745 | if (reg->size) | |
b12bb29f | 746 | return serial_port_in(port, SCFDR) & ((port->fifosize << 1) - 1); |
72b294cf | 747 | |
b12bb29f | 748 | return (serial_port_in(port, SCxSR) & SCxSR_RDxF(port)) != 0; |
e108b2ca PM |
749 | } |
750 | ||
514820eb PM |
751 | /* |
752 | * SCI helper for checking the state of the muxed port/RXD pins. | |
753 | */ | |
754 | static inline int sci_rxd_in(struct uart_port *port) | |
755 | { | |
756 | struct sci_port *s = to_sci_port(port); | |
757 | ||
758 | if (s->cfg->port_reg <= 0) | |
759 | return 1; | |
760 | ||
0dd4d5cb | 761 | /* Cast for ARM damage */ |
e2afca69 | 762 | return !!__raw_readb((void __iomem *)(uintptr_t)s->cfg->port_reg); |
514820eb PM |
763 | } |
764 | ||
1da177e4 LT |
765 | /* ********************************************************************** * |
766 | * the interrupt related routines * | |
767 | * ********************************************************************** */ | |
768 | ||
769 | static void sci_transmit_chars(struct uart_port *port) | |
770 | { | |
ebd2c8f6 | 771 | struct circ_buf *xmit = &port->state->xmit; |
1da177e4 | 772 | unsigned int stopped = uart_tx_stopped(port); |
1da177e4 LT |
773 | unsigned short status; |
774 | unsigned short ctrl; | |
e108b2ca | 775 | int count; |
1da177e4 | 776 | |
b12bb29f | 777 | status = serial_port_in(port, SCxSR); |
1da177e4 | 778 | if (!(status & SCxSR_TDxE(port))) { |
b12bb29f | 779 | ctrl = serial_port_in(port, SCSCR); |
e7c98dc7 | 780 | if (uart_circ_empty(xmit)) |
8e698614 | 781 | ctrl &= ~SCSCR_TIE; |
e7c98dc7 | 782 | else |
8e698614 | 783 | ctrl |= SCSCR_TIE; |
b12bb29f | 784 | serial_port_out(port, SCSCR, ctrl); |
1da177e4 LT |
785 | return; |
786 | } | |
787 | ||
72b294cf | 788 | count = sci_txroom(port); |
1da177e4 LT |
789 | |
790 | do { | |
791 | unsigned char c; | |
792 | ||
793 | if (port->x_char) { | |
794 | c = port->x_char; | |
795 | port->x_char = 0; | |
796 | } else if (!uart_circ_empty(xmit) && !stopped) { | |
797 | c = xmit->buf[xmit->tail]; | |
798 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); | |
799 | } else { | |
800 | break; | |
801 | } | |
802 | ||
b12bb29f | 803 | serial_port_out(port, SCxTDR, c); |
1da177e4 LT |
804 | |
805 | port->icount.tx++; | |
806 | } while (--count > 0); | |
807 | ||
a1b5b43f | 808 | sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port)); |
1da177e4 LT |
809 | |
810 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
811 | uart_write_wakeup(port); | |
812 | if (uart_circ_empty(xmit)) { | |
b129a8cc | 813 | sci_stop_tx(port); |
1da177e4 | 814 | } else { |
b12bb29f | 815 | ctrl = serial_port_in(port, SCSCR); |
1da177e4 | 816 | |
1a22f08d | 817 | if (port->type != PORT_SCI) { |
b12bb29f | 818 | serial_port_in(port, SCxSR); /* Dummy read */ |
a1b5b43f | 819 | sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port)); |
1da177e4 | 820 | } |
1da177e4 | 821 | |
8e698614 | 822 | ctrl |= SCSCR_TIE; |
b12bb29f | 823 | serial_port_out(port, SCSCR, ctrl); |
1da177e4 LT |
824 | } |
825 | } | |
826 | ||
827 | /* On SH3, SCIF may read end-of-break as a space->mark char */ | |
e7c98dc7 | 828 | #define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); }) |
1da177e4 | 829 | |
94c8b6db | 830 | static void sci_receive_chars(struct uart_port *port) |
1da177e4 | 831 | { |
e7c98dc7 | 832 | struct sci_port *sci_port = to_sci_port(port); |
227434f8 | 833 | struct tty_port *tport = &port->state->port; |
1da177e4 LT |
834 | int i, count, copied = 0; |
835 | unsigned short status; | |
33f0f88f | 836 | unsigned char flag; |
1da177e4 | 837 | |
b12bb29f | 838 | status = serial_port_in(port, SCxSR); |
1da177e4 LT |
839 | if (!(status & SCxSR_RDxF(port))) |
840 | return; | |
841 | ||
842 | while (1) { | |
1da177e4 | 843 | /* Don't copy more bytes than there is room for in the buffer */ |
227434f8 | 844 | count = tty_buffer_request_room(tport, sci_rxfill(port)); |
1da177e4 LT |
845 | |
846 | /* If for any reason we can't copy more data, we're done! */ | |
847 | if (count == 0) | |
848 | break; | |
849 | ||
850 | if (port->type == PORT_SCI) { | |
b12bb29f | 851 | char c = serial_port_in(port, SCxRDR); |
e7c98dc7 MT |
852 | if (uart_handle_sysrq_char(port, c) || |
853 | sci_port->break_flag) | |
1da177e4 | 854 | count = 0; |
e7c98dc7 | 855 | else |
92a19f9c | 856 | tty_insert_flip_char(tport, c, TTY_NORMAL); |
1da177e4 | 857 | } else { |
e7c98dc7 | 858 | for (i = 0; i < count; i++) { |
b12bb29f | 859 | char c = serial_port_in(port, SCxRDR); |
d97fbbed | 860 | |
b12bb29f | 861 | status = serial_port_in(port, SCxSR); |
1da177e4 LT |
862 | #if defined(CONFIG_CPU_SH3) |
863 | /* Skip "chars" during break */ | |
e108b2ca | 864 | if (sci_port->break_flag) { |
1da177e4 LT |
865 | if ((c == 0) && |
866 | (status & SCxSR_FER(port))) { | |
867 | count--; i--; | |
868 | continue; | |
869 | } | |
e108b2ca | 870 | |
1da177e4 | 871 | /* Nonzero => end-of-break */ |
762c69e3 | 872 | dev_dbg(port->dev, "debounce<%02x>\n", c); |
e108b2ca PM |
873 | sci_port->break_flag = 0; |
874 | ||
1da177e4 LT |
875 | if (STEPFN(c)) { |
876 | count--; i--; | |
877 | continue; | |
878 | } | |
879 | } | |
880 | #endif /* CONFIG_CPU_SH3 */ | |
7d12e780 | 881 | if (uart_handle_sysrq_char(port, c)) { |
1da177e4 LT |
882 | count--; i--; |
883 | continue; | |
884 | } | |
885 | ||
886 | /* Store data and status */ | |
73a19e4c | 887 | if (status & SCxSR_FER(port)) { |
33f0f88f | 888 | flag = TTY_FRAME; |
d97fbbed | 889 | port->icount.frame++; |
762c69e3 | 890 | dev_notice(port->dev, "frame error\n"); |
73a19e4c | 891 | } else if (status & SCxSR_PER(port)) { |
33f0f88f | 892 | flag = TTY_PARITY; |
d97fbbed | 893 | port->icount.parity++; |
762c69e3 | 894 | dev_notice(port->dev, "parity error\n"); |
33f0f88f AC |
895 | } else |
896 | flag = TTY_NORMAL; | |
762c69e3 | 897 | |
92a19f9c | 898 | tty_insert_flip_char(tport, c, flag); |
1da177e4 LT |
899 | } |
900 | } | |
901 | ||
b12bb29f | 902 | serial_port_in(port, SCxSR); /* dummy read */ |
a1b5b43f | 903 | sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port)); |
1da177e4 | 904 | |
1da177e4 LT |
905 | copied += count; |
906 | port->icount.rx += count; | |
907 | } | |
908 | ||
909 | if (copied) { | |
910 | /* Tell the rest of the system the news. New characters! */ | |
2e124b4a | 911 | tty_flip_buffer_push(tport); |
1da177e4 | 912 | } else { |
b12bb29f | 913 | serial_port_in(port, SCxSR); /* dummy read */ |
a1b5b43f | 914 | sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port)); |
1da177e4 LT |
915 | } |
916 | } | |
917 | ||
918 | #define SCI_BREAK_JIFFIES (HZ/20) | |
94c8b6db PM |
919 | |
920 | /* | |
921 | * The sci generates interrupts during the break, | |
1da177e4 LT |
922 | * 1 per millisecond or so during the break period, for 9600 baud. |
923 | * So dont bother disabling interrupts. | |
924 | * But dont want more than 1 break event. | |
925 | * Use a kernel timer to periodically poll the rx line until | |
926 | * the break is finished. | |
927 | */ | |
94c8b6db | 928 | static inline void sci_schedule_break_timer(struct sci_port *port) |
1da177e4 | 929 | { |
bc9b3f5c | 930 | mod_timer(&port->break_timer, jiffies + SCI_BREAK_JIFFIES); |
1da177e4 | 931 | } |
94c8b6db | 932 | |
1da177e4 LT |
933 | /* Ensure that two consecutive samples find the break over. */ |
934 | static void sci_break_timer(unsigned long data) | |
935 | { | |
e108b2ca PM |
936 | struct sci_port *port = (struct sci_port *)data; |
937 | ||
938 | if (sci_rxd_in(&port->port) == 0) { | |
1da177e4 | 939 | port->break_flag = 1; |
e108b2ca PM |
940 | sci_schedule_break_timer(port); |
941 | } else if (port->break_flag == 1) { | |
1da177e4 LT |
942 | /* break is over. */ |
943 | port->break_flag = 2; | |
e108b2ca PM |
944 | sci_schedule_break_timer(port); |
945 | } else | |
946 | port->break_flag = 0; | |
1da177e4 LT |
947 | } |
948 | ||
94c8b6db | 949 | static int sci_handle_errors(struct uart_port *port) |
1da177e4 LT |
950 | { |
951 | int copied = 0; | |
b12bb29f | 952 | unsigned short status = serial_port_in(port, SCxSR); |
92a19f9c | 953 | struct tty_port *tport = &port->state->port; |
debf9507 | 954 | struct sci_port *s = to_sci_port(port); |
1da177e4 | 955 | |
3ae988d9 | 956 | /* Handle overruns */ |
75c249fd | 957 | if (status & s->overrun_mask) { |
3ae988d9 | 958 | port->icount.overrun++; |
d97fbbed | 959 | |
3ae988d9 LP |
960 | /* overrun error */ |
961 | if (tty_insert_flip_char(tport, 0, TTY_OVERRUN)) | |
962 | copied++; | |
762c69e3 | 963 | |
9b971cd2 | 964 | dev_notice(port->dev, "overrun error\n"); |
1da177e4 LT |
965 | } |
966 | ||
e108b2ca | 967 | if (status & SCxSR_FER(port)) { |
1da177e4 LT |
968 | if (sci_rxd_in(port) == 0) { |
969 | /* Notify of BREAK */ | |
e7c98dc7 | 970 | struct sci_port *sci_port = to_sci_port(port); |
e108b2ca PM |
971 | |
972 | if (!sci_port->break_flag) { | |
d97fbbed PM |
973 | port->icount.brk++; |
974 | ||
e108b2ca PM |
975 | sci_port->break_flag = 1; |
976 | sci_schedule_break_timer(sci_port); | |
977 | ||
1da177e4 | 978 | /* Do sysrq handling. */ |
e108b2ca | 979 | if (uart_handle_break(port)) |
1da177e4 | 980 | return 0; |
762c69e3 PM |
981 | |
982 | dev_dbg(port->dev, "BREAK detected\n"); | |
983 | ||
92a19f9c | 984 | if (tty_insert_flip_char(tport, 0, TTY_BREAK)) |
e7c98dc7 MT |
985 | copied++; |
986 | } | |
987 | ||
e108b2ca | 988 | } else { |
1da177e4 | 989 | /* frame error */ |
d97fbbed PM |
990 | port->icount.frame++; |
991 | ||
92a19f9c | 992 | if (tty_insert_flip_char(tport, 0, TTY_FRAME)) |
33f0f88f | 993 | copied++; |
762c69e3 PM |
994 | |
995 | dev_notice(port->dev, "frame error\n"); | |
1da177e4 LT |
996 | } |
997 | } | |
998 | ||
e108b2ca | 999 | if (status & SCxSR_PER(port)) { |
1da177e4 | 1000 | /* parity error */ |
d97fbbed PM |
1001 | port->icount.parity++; |
1002 | ||
92a19f9c | 1003 | if (tty_insert_flip_char(tport, 0, TTY_PARITY)) |
e108b2ca | 1004 | copied++; |
762c69e3 | 1005 | |
9b971cd2 | 1006 | dev_notice(port->dev, "parity error\n"); |
1da177e4 LT |
1007 | } |
1008 | ||
33f0f88f | 1009 | if (copied) |
2e124b4a | 1010 | tty_flip_buffer_push(tport); |
1da177e4 LT |
1011 | |
1012 | return copied; | |
1013 | } | |
1014 | ||
94c8b6db | 1015 | static int sci_handle_fifo_overrun(struct uart_port *port) |
d830fa45 | 1016 | { |
92a19f9c | 1017 | struct tty_port *tport = &port->state->port; |
debf9507 | 1018 | struct sci_port *s = to_sci_port(port); |
d3184e68 | 1019 | const struct plat_sci_reg *reg; |
2e0842a1 | 1020 | int copied = 0; |
75c249fd | 1021 | u16 status; |
d830fa45 | 1022 | |
2e0842a1 | 1023 | reg = sci_getreg(port, s->overrun_reg); |
4b8c59a3 | 1024 | if (!reg->size) |
d830fa45 PM |
1025 | return 0; |
1026 | ||
2e0842a1 | 1027 | status = serial_port_in(port, s->overrun_reg); |
75c249fd GU |
1028 | if (status & s->overrun_mask) { |
1029 | status &= ~s->overrun_mask; | |
2e0842a1 | 1030 | serial_port_out(port, s->overrun_reg, status); |
d830fa45 | 1031 | |
d97fbbed PM |
1032 | port->icount.overrun++; |
1033 | ||
92a19f9c | 1034 | tty_insert_flip_char(tport, 0, TTY_OVERRUN); |
2e124b4a | 1035 | tty_flip_buffer_push(tport); |
d830fa45 | 1036 | |
51b31f1c | 1037 | dev_dbg(port->dev, "overrun error\n"); |
d830fa45 PM |
1038 | copied++; |
1039 | } | |
1040 | ||
1041 | return copied; | |
1042 | } | |
1043 | ||
94c8b6db | 1044 | static int sci_handle_breaks(struct uart_port *port) |
1da177e4 LT |
1045 | { |
1046 | int copied = 0; | |
b12bb29f | 1047 | unsigned short status = serial_port_in(port, SCxSR); |
92a19f9c | 1048 | struct tty_port *tport = &port->state->port; |
a5660ada | 1049 | struct sci_port *s = to_sci_port(port); |
1da177e4 | 1050 | |
0b3d4ef6 PM |
1051 | if (uart_handle_break(port)) |
1052 | return 0; | |
1053 | ||
b7a76e4b | 1054 | if (!s->break_flag && status & SCxSR_BRK(port)) { |
1da177e4 LT |
1055 | #if defined(CONFIG_CPU_SH3) |
1056 | /* Debounce break */ | |
1057 | s->break_flag = 1; | |
1058 | #endif | |
d97fbbed PM |
1059 | |
1060 | port->icount.brk++; | |
1061 | ||
1da177e4 | 1062 | /* Notify of BREAK */ |
92a19f9c | 1063 | if (tty_insert_flip_char(tport, 0, TTY_BREAK)) |
33f0f88f | 1064 | copied++; |
762c69e3 PM |
1065 | |
1066 | dev_dbg(port->dev, "BREAK detected\n"); | |
1da177e4 LT |
1067 | } |
1068 | ||
33f0f88f | 1069 | if (copied) |
2e124b4a | 1070 | tty_flip_buffer_push(tport); |
e108b2ca | 1071 | |
d830fa45 PM |
1072 | copied += sci_handle_fifo_overrun(port); |
1073 | ||
1da177e4 LT |
1074 | return copied; |
1075 | } | |
1076 | ||
73a19e4c | 1077 | #ifdef CONFIG_SERIAL_SH_SCI_DMA |
e1910fcd GU |
1078 | static void sci_dma_tx_complete(void *arg) |
1079 | { | |
1080 | struct sci_port *s = arg; | |
1081 | struct uart_port *port = &s->port; | |
1082 | struct circ_buf *xmit = &port->state->xmit; | |
1083 | unsigned long flags; | |
73a19e4c | 1084 | |
e1910fcd | 1085 | dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); |
73a19e4c | 1086 | |
e1910fcd | 1087 | spin_lock_irqsave(&port->lock, flags); |
73a19e4c | 1088 | |
e1910fcd GU |
1089 | xmit->tail += s->tx_dma_len; |
1090 | xmit->tail &= UART_XMIT_SIZE - 1; | |
73a19e4c | 1091 | |
e1910fcd | 1092 | port->icount.tx += s->tx_dma_len; |
1da177e4 | 1093 | |
e1910fcd GU |
1094 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) |
1095 | uart_write_wakeup(port); | |
1da177e4 | 1096 | |
e1910fcd GU |
1097 | if (!uart_circ_empty(xmit)) { |
1098 | s->cookie_tx = 0; | |
1099 | schedule_work(&s->work_tx); | |
1100 | } else { | |
1101 | s->cookie_tx = -EINVAL; | |
1102 | if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { | |
1103 | u16 ctrl = serial_port_in(port, SCSCR); | |
1104 | serial_port_out(port, SCSCR, ctrl & ~SCSCR_TIE); | |
1105 | } | |
1106 | } | |
1da177e4 | 1107 | |
fd78a76a | 1108 | spin_unlock_irqrestore(&port->lock, flags); |
1da177e4 LT |
1109 | } |
1110 | ||
e1910fcd GU |
1111 | /* Locking: called with port lock held */ |
1112 | static int sci_dma_rx_push(struct sci_port *s, void *buf, size_t count) | |
1da177e4 | 1113 | { |
e1910fcd GU |
1114 | struct uart_port *port = &s->port; |
1115 | struct tty_port *tport = &port->state->port; | |
1116 | int copied; | |
1da177e4 | 1117 | |
e1910fcd GU |
1118 | copied = tty_insert_flip_string(tport, buf, count); |
1119 | if (copied < count) { | |
1120 | dev_warn(port->dev, "Rx overrun: dropping %zu bytes\n", | |
1121 | count - copied); | |
1122 | port->icount.buf_overrun++; | |
1da177e4 LT |
1123 | } |
1124 | ||
e1910fcd | 1125 | port->icount.rx += copied; |
1da177e4 | 1126 | |
e1910fcd | 1127 | return copied; |
1da177e4 LT |
1128 | } |
1129 | ||
e1910fcd | 1130 | static int sci_dma_rx_find_active(struct sci_port *s) |
1da177e4 | 1131 | { |
e1910fcd | 1132 | unsigned int i; |
1da177e4 | 1133 | |
e1910fcd GU |
1134 | for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++) |
1135 | if (s->active_rx == s->cookie_rx[i]) | |
1136 | return i; | |
1da177e4 | 1137 | |
e1910fcd GU |
1138 | dev_err(s->port.dev, "%s: Rx cookie %d not found!\n", __func__, |
1139 | s->active_rx); | |
1140 | return -1; | |
1da177e4 LT |
1141 | } |
1142 | ||
e1910fcd | 1143 | static void sci_rx_dma_release(struct sci_port *s, bool enable_pio) |
f43dc23d | 1144 | { |
e1910fcd GU |
1145 | struct dma_chan *chan = s->chan_rx; |
1146 | struct uart_port *port = &s->port; | |
1147 | unsigned long flags; | |
1148 | ||
1149 | spin_lock_irqsave(&port->lock, flags); | |
1150 | s->chan_rx = NULL; | |
1151 | s->cookie_rx[0] = s->cookie_rx[1] = -EINVAL; | |
1152 | spin_unlock_irqrestore(&port->lock, flags); | |
1153 | dmaengine_terminate_all(chan); | |
1154 | dma_free_coherent(chan->device->dev, s->buf_len_rx * 2, s->rx_buf[0], | |
1155 | sg_dma_address(&s->sg_rx[0])); | |
1156 | dma_release_channel(chan); | |
1157 | if (enable_pio) | |
1158 | sci_start_rx(port); | |
f43dc23d PM |
1159 | } |
1160 | ||
e1910fcd | 1161 | static void sci_dma_rx_complete(void *arg) |
1da177e4 | 1162 | { |
e1910fcd | 1163 | struct sci_port *s = arg; |
1d3db608 | 1164 | struct dma_chan *chan = s->chan_rx; |
e1910fcd | 1165 | struct uart_port *port = &s->port; |
67f462b0 | 1166 | struct dma_async_tx_descriptor *desc; |
e1910fcd GU |
1167 | unsigned long flags; |
1168 | int active, count = 0; | |
1da177e4 | 1169 | |
e1910fcd GU |
1170 | dev_dbg(port->dev, "%s(%d) active cookie %d\n", __func__, port->line, |
1171 | s->active_rx); | |
cb772fe7 | 1172 | |
e1910fcd | 1173 | spin_lock_irqsave(&port->lock, flags); |
1da177e4 | 1174 | |
e1910fcd GU |
1175 | active = sci_dma_rx_find_active(s); |
1176 | if (active >= 0) | |
1177 | count = sci_dma_rx_push(s, s->rx_buf[active], s->buf_len_rx); | |
f43dc23d | 1178 | |
e1910fcd | 1179 | mod_timer(&s->rx_timer, jiffies + s->rx_timeout); |
f43dc23d | 1180 | |
e1910fcd GU |
1181 | if (count) |
1182 | tty_flip_buffer_push(&port->state->port); | |
8b6ff84c | 1183 | |
67f462b0 GU |
1184 | desc = dmaengine_prep_slave_sg(s->chan_rx, &s->sg_rx[active], 1, |
1185 | DMA_DEV_TO_MEM, | |
1186 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
1187 | if (!desc) | |
1188 | goto fail; | |
1189 | ||
1190 | desc->callback = sci_dma_rx_complete; | |
1191 | desc->callback_param = s; | |
1192 | s->cookie_rx[active] = dmaengine_submit(desc); | |
1193 | if (dma_submit_error(s->cookie_rx[active])) | |
1194 | goto fail; | |
1195 | ||
1196 | s->active_rx = s->cookie_rx[!active]; | |
1197 | ||
1d3db608 MHF |
1198 | dma_async_issue_pending(chan); |
1199 | ||
67f462b0 GU |
1200 | dev_dbg(port->dev, "%s: cookie %d #%d, new active cookie %d\n", |
1201 | __func__, s->cookie_rx[active], active, s->active_rx); | |
1202 | spin_unlock_irqrestore(&port->lock, flags); | |
1203 | return; | |
1204 | ||
1205 | fail: | |
1206 | spin_unlock_irqrestore(&port->lock, flags); | |
1207 | dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n"); | |
1208 | sci_rx_dma_release(s, true); | |
1da177e4 LT |
1209 | } |
1210 | ||
e1910fcd | 1211 | static void sci_tx_dma_release(struct sci_port *s, bool enable_pio) |
1da177e4 | 1212 | { |
e1910fcd GU |
1213 | struct dma_chan *chan = s->chan_tx; |
1214 | struct uart_port *port = &s->port; | |
e552de24 | 1215 | unsigned long flags; |
1da177e4 | 1216 | |
e1910fcd GU |
1217 | spin_lock_irqsave(&port->lock, flags); |
1218 | s->chan_tx = NULL; | |
1219 | s->cookie_tx = -EINVAL; | |
1220 | spin_unlock_irqrestore(&port->lock, flags); | |
1221 | dmaengine_terminate_all(chan); | |
1222 | dma_unmap_single(chan->device->dev, s->tx_dma_addr, UART_XMIT_SIZE, | |
1223 | DMA_TO_DEVICE); | |
1224 | dma_release_channel(chan); | |
1225 | if (enable_pio) | |
1226 | sci_start_tx(port); | |
1227 | } | |
d535a230 | 1228 | |
e1910fcd GU |
1229 | static void sci_submit_rx(struct sci_port *s) |
1230 | { | |
1231 | struct dma_chan *chan = s->chan_rx; | |
1232 | int i; | |
073e84c9 | 1233 | |
e1910fcd GU |
1234 | for (i = 0; i < 2; i++) { |
1235 | struct scatterlist *sg = &s->sg_rx[i]; | |
1236 | struct dma_async_tx_descriptor *desc; | |
1da177e4 | 1237 | |
e1910fcd GU |
1238 | desc = dmaengine_prep_slave_sg(chan, |
1239 | sg, 1, DMA_DEV_TO_MEM, | |
1240 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
1241 | if (!desc) | |
1242 | goto fail; | |
501b825d | 1243 | |
e1910fcd GU |
1244 | desc->callback = sci_dma_rx_complete; |
1245 | desc->callback_param = s; | |
1246 | s->cookie_rx[i] = dmaengine_submit(desc); | |
1247 | if (dma_submit_error(s->cookie_rx[i])) | |
1248 | goto fail; | |
9174fc8f | 1249 | |
e1910fcd GU |
1250 | dev_dbg(s->port.dev, "%s(): cookie %d to #%d\n", __func__, |
1251 | s->cookie_rx[i], i); | |
1252 | } | |
9174fc8f | 1253 | |
e1910fcd | 1254 | s->active_rx = s->cookie_rx[0]; |
9174fc8f | 1255 | |
e1910fcd GU |
1256 | dma_async_issue_pending(chan); |
1257 | return; | |
9174fc8f | 1258 | |
e1910fcd GU |
1259 | fail: |
1260 | if (i) | |
1261 | dmaengine_terminate_all(chan); | |
1262 | for (i = 0; i < 2; i++) | |
1263 | s->cookie_rx[i] = -EINVAL; | |
1264 | s->active_rx = -EINVAL; | |
1265 | dev_warn(s->port.dev, "Failed to re-start Rx DMA, using PIO\n"); | |
1266 | sci_rx_dma_release(s, true); | |
1267 | } | |
9174fc8f | 1268 | |
e1910fcd | 1269 | static void work_fn_tx(struct work_struct *work) |
1da177e4 | 1270 | { |
e1910fcd GU |
1271 | struct sci_port *s = container_of(work, struct sci_port, work_tx); |
1272 | struct dma_async_tx_descriptor *desc; | |
1273 | struct dma_chan *chan = s->chan_tx; | |
1274 | struct uart_port *port = &s->port; | |
1275 | struct circ_buf *xmit = &port->state->xmit; | |
1276 | dma_addr_t buf; | |
1da177e4 | 1277 | |
9174fc8f | 1278 | /* |
e1910fcd GU |
1279 | * DMA is idle now. |
1280 | * Port xmit buffer is already mapped, and it is one page... Just adjust | |
1281 | * offsets and lengths. Since it is a circular buffer, we have to | |
1282 | * transmit till the end, and then the rest. Take the port lock to get a | |
1283 | * consistent xmit buffer state. | |
9174fc8f | 1284 | */ |
e1910fcd GU |
1285 | spin_lock_irq(&port->lock); |
1286 | buf = s->tx_dma_addr + (xmit->tail & (UART_XMIT_SIZE - 1)); | |
1287 | s->tx_dma_len = min_t(unsigned int, | |
1288 | CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE), | |
1289 | CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE)); | |
1290 | spin_unlock_irq(&port->lock); | |
0e8963de | 1291 | |
e1910fcd GU |
1292 | desc = dmaengine_prep_slave_single(chan, buf, s->tx_dma_len, |
1293 | DMA_MEM_TO_DEV, | |
1294 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
1295 | if (!desc) { | |
1296 | dev_warn(port->dev, "Failed preparing Tx DMA descriptor\n"); | |
1297 | /* switch to PIO */ | |
1298 | sci_tx_dma_release(s, true); | |
1299 | return; | |
1300 | } | |
0e8963de | 1301 | |
e1910fcd GU |
1302 | dma_sync_single_for_device(chan->device->dev, buf, s->tx_dma_len, |
1303 | DMA_TO_DEVICE); | |
1da177e4 | 1304 | |
e1910fcd GU |
1305 | spin_lock_irq(&port->lock); |
1306 | desc->callback = sci_dma_tx_complete; | |
1307 | desc->callback_param = s; | |
1308 | spin_unlock_irq(&port->lock); | |
1309 | s->cookie_tx = dmaengine_submit(desc); | |
1310 | if (dma_submit_error(s->cookie_tx)) { | |
1311 | dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n"); | |
1312 | /* switch to PIO */ | |
1313 | sci_tx_dma_release(s, true); | |
1314 | return; | |
1da177e4 | 1315 | } |
1da177e4 | 1316 | |
e1910fcd GU |
1317 | dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n", |
1318 | __func__, xmit->buf, xmit->tail, xmit->head, s->cookie_tx); | |
73a19e4c | 1319 | |
e1910fcd | 1320 | dma_async_issue_pending(chan); |
1da177e4 LT |
1321 | } |
1322 | ||
e1910fcd | 1323 | static void rx_timer_fn(unsigned long arg) |
1da177e4 | 1324 | { |
e1910fcd | 1325 | struct sci_port *s = (struct sci_port *)arg; |
e7327c09 | 1326 | struct dma_chan *chan = s->chan_rx; |
e1910fcd | 1327 | struct uart_port *port = &s->port; |
67f462b0 GU |
1328 | struct dma_tx_state state; |
1329 | enum dma_status status; | |
1330 | unsigned long flags; | |
1331 | unsigned int read; | |
1332 | int active, count; | |
1333 | u16 scr; | |
1334 | ||
1335 | spin_lock_irqsave(&port->lock, flags); | |
e1910fcd | 1336 | |
67f462b0 | 1337 | dev_dbg(port->dev, "DMA Rx timed out\n"); |
67f462b0 GU |
1338 | |
1339 | active = sci_dma_rx_find_active(s); | |
1340 | if (active < 0) { | |
1341 | spin_unlock_irqrestore(&port->lock, flags); | |
1342 | return; | |
1343 | } | |
1344 | ||
1345 | status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state); | |
3b963042 | 1346 | if (status == DMA_COMPLETE) { |
67f462b0 GU |
1347 | dev_dbg(port->dev, "Cookie %d #%d has already completed\n", |
1348 | s->active_rx, active); | |
3b963042 MHF |
1349 | spin_unlock_irqrestore(&port->lock, flags); |
1350 | ||
1351 | /* Let packet complete handler take care of the packet */ | |
1352 | return; | |
1353 | } | |
67f462b0 | 1354 | |
e7327c09 MHF |
1355 | dmaengine_pause(chan); |
1356 | ||
1357 | /* | |
1358 | * sometimes DMA transfer doesn't stop even if it is stopped and | |
1359 | * data keeps on coming until transaction is complete so check | |
1360 | * for DMA_COMPLETE again | |
1361 | * Let packet complete handler take care of the packet | |
1362 | */ | |
1363 | status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state); | |
1364 | if (status == DMA_COMPLETE) { | |
1365 | spin_unlock_irqrestore(&port->lock, flags); | |
1366 | dev_dbg(port->dev, "Transaction complete after DMA engine was stopped"); | |
1367 | return; | |
1368 | } | |
1369 | ||
67f462b0 GU |
1370 | /* Handle incomplete DMA receive */ |
1371 | dmaengine_terminate_all(s->chan_rx); | |
1372 | read = sg_dma_len(&s->sg_rx[active]) - state.residue; | |
1373 | dev_dbg(port->dev, "Read %u bytes with cookie %d\n", read, | |
1374 | s->active_rx); | |
1375 | ||
1376 | if (read) { | |
1377 | count = sci_dma_rx_push(s, s->rx_buf[active], read); | |
1378 | if (count) | |
1379 | tty_flip_buffer_push(&port->state->port); | |
1380 | } | |
1381 | ||
756981be GU |
1382 | if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) |
1383 | sci_submit_rx(s); | |
371cfed3 MHF |
1384 | |
1385 | /* Direct new serial port interrupts back to CPU */ | |
1386 | scr = serial_port_in(port, SCSCR); | |
1387 | if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { | |
1388 | scr &= ~SCSCR_RDRQE; | |
1389 | enable_irq(s->irqs[SCIx_RXI_IRQ]); | |
1390 | } | |
1391 | serial_port_out(port, SCSCR, scr | SCSCR_RIE); | |
1392 | ||
1393 | spin_unlock_irqrestore(&port->lock, flags); | |
1da177e4 LT |
1394 | } |
1395 | ||
ff441129 GU |
1396 | static struct dma_chan *sci_request_dma_chan(struct uart_port *port, |
1397 | enum dma_transfer_direction dir, | |
1398 | unsigned int id) | |
1399 | { | |
1400 | dma_cap_mask_t mask; | |
1401 | struct dma_chan *chan; | |
1402 | struct dma_slave_config cfg; | |
1403 | int ret; | |
1404 | ||
1405 | dma_cap_zero(mask); | |
1406 | dma_cap_set(DMA_SLAVE, mask); | |
1407 | ||
1408 | chan = dma_request_slave_channel_compat(mask, shdma_chan_filter, | |
1409 | (void *)(unsigned long)id, port->dev, | |
1410 | dir == DMA_MEM_TO_DEV ? "tx" : "rx"); | |
1411 | if (!chan) { | |
1412 | dev_warn(port->dev, | |
1413 | "dma_request_slave_channel_compat failed\n"); | |
1414 | return NULL; | |
1415 | } | |
1416 | ||
1417 | memset(&cfg, 0, sizeof(cfg)); | |
1418 | cfg.direction = dir; | |
1419 | if (dir == DMA_MEM_TO_DEV) { | |
1420 | cfg.dst_addr = port->mapbase + | |
1421 | (sci_getreg(port, SCxTDR)->offset << port->regshift); | |
1422 | cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; | |
1423 | } else { | |
1424 | cfg.src_addr = port->mapbase + | |
1425 | (sci_getreg(port, SCxRDR)->offset << port->regshift); | |
1426 | cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; | |
1427 | } | |
1428 | ||
1429 | ret = dmaengine_slave_config(chan, &cfg); | |
1430 | if (ret) { | |
1431 | dev_warn(port->dev, "dmaengine_slave_config failed %d\n", ret); | |
1432 | dma_release_channel(chan); | |
1433 | return NULL; | |
1434 | } | |
1435 | ||
1436 | return chan; | |
1437 | } | |
1438 | ||
e1910fcd | 1439 | static void sci_request_dma(struct uart_port *port) |
73a19e4c | 1440 | { |
e1910fcd | 1441 | struct sci_port *s = to_sci_port(port); |
e1910fcd | 1442 | struct dma_chan *chan; |
73a19e4c | 1443 | |
e1910fcd | 1444 | dev_dbg(port->dev, "%s: port %d\n", __func__, port->line); |
73a19e4c | 1445 | |
ff441129 GU |
1446 | if (!port->dev->of_node && |
1447 | (s->cfg->dma_slave_tx <= 0 || s->cfg->dma_slave_rx <= 0)) | |
e1910fcd | 1448 | return; |
73a19e4c | 1449 | |
e1910fcd | 1450 | s->cookie_tx = -EINVAL; |
ff441129 | 1451 | chan = sci_request_dma_chan(port, DMA_MEM_TO_DEV, s->cfg->dma_slave_tx); |
e1910fcd GU |
1452 | dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan); |
1453 | if (chan) { | |
1454 | s->chan_tx = chan; | |
1455 | /* UART circular tx buffer is an aligned page. */ | |
1456 | s->tx_dma_addr = dma_map_single(chan->device->dev, | |
1457 | port->state->xmit.buf, | |
1458 | UART_XMIT_SIZE, | |
1459 | DMA_TO_DEVICE); | |
1460 | if (dma_mapping_error(chan->device->dev, s->tx_dma_addr)) { | |
1461 | dev_warn(port->dev, "Failed mapping Tx DMA descriptor\n"); | |
1462 | dma_release_channel(chan); | |
1463 | s->chan_tx = NULL; | |
1464 | } else { | |
1465 | dev_dbg(port->dev, "%s: mapped %lu@%p to %pad\n", | |
1466 | __func__, UART_XMIT_SIZE, | |
1467 | port->state->xmit.buf, &s->tx_dma_addr); | |
49d4bcad | 1468 | } |
e1910fcd GU |
1469 | |
1470 | INIT_WORK(&s->work_tx, work_fn_tx); | |
3089f381 GL |
1471 | } |
1472 | ||
ff441129 | 1473 | chan = sci_request_dma_chan(port, DMA_DEV_TO_MEM, s->cfg->dma_slave_rx); |
e1910fcd GU |
1474 | dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan); |
1475 | if (chan) { | |
1476 | unsigned int i; | |
1477 | dma_addr_t dma; | |
1478 | void *buf; | |
73a19e4c | 1479 | |
e1910fcd | 1480 | s->chan_rx = chan; |
73a19e4c | 1481 | |
e1910fcd GU |
1482 | s->buf_len_rx = 2 * max_t(size_t, 16, port->fifosize); |
1483 | buf = dma_alloc_coherent(chan->device->dev, s->buf_len_rx * 2, | |
1484 | &dma, GFP_KERNEL); | |
1485 | if (!buf) { | |
1486 | dev_warn(port->dev, | |
1487 | "Failed to allocate Rx dma buffer, using PIO\n"); | |
1488 | dma_release_channel(chan); | |
1489 | s->chan_rx = NULL; | |
e1910fcd GU |
1490 | return; |
1491 | } | |
73a19e4c | 1492 | |
e1910fcd GU |
1493 | for (i = 0; i < 2; i++) { |
1494 | struct scatterlist *sg = &s->sg_rx[i]; | |
0533502d | 1495 | |
e1910fcd GU |
1496 | sg_init_table(sg, 1); |
1497 | s->rx_buf[i] = buf; | |
1498 | sg_dma_address(sg) = dma; | |
d09959e7 | 1499 | sg_dma_len(sg) = s->buf_len_rx; |
0533502d | 1500 | |
e1910fcd GU |
1501 | buf += s->buf_len_rx; |
1502 | dma += s->buf_len_rx; | |
1503 | } | |
1504 | ||
e1910fcd GU |
1505 | setup_timer(&s->rx_timer, rx_timer_fn, (unsigned long)s); |
1506 | ||
756981be GU |
1507 | if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) |
1508 | sci_submit_rx(s); | |
e1910fcd | 1509 | } |
0533502d GU |
1510 | } |
1511 | ||
e1910fcd | 1512 | static void sci_free_dma(struct uart_port *port) |
73a19e4c | 1513 | { |
e1910fcd | 1514 | struct sci_port *s = to_sci_port(port); |
73a19e4c | 1515 | |
e1910fcd GU |
1516 | if (s->chan_tx) |
1517 | sci_tx_dma_release(s, false); | |
1518 | if (s->chan_rx) | |
1519 | sci_rx_dma_release(s, false); | |
1520 | } | |
1521 | #else | |
1522 | static inline void sci_request_dma(struct uart_port *port) | |
1523 | { | |
1524 | } | |
73a19e4c | 1525 | |
e1910fcd GU |
1526 | static inline void sci_free_dma(struct uart_port *port) |
1527 | { | |
1528 | } | |
1529 | #endif | |
73a19e4c | 1530 | |
e1910fcd GU |
1531 | static irqreturn_t sci_rx_interrupt(int irq, void *ptr) |
1532 | { | |
1533 | #ifdef CONFIG_SERIAL_SH_SCI_DMA | |
1534 | struct uart_port *port = ptr; | |
1535 | struct sci_port *s = to_sci_port(port); | |
73a19e4c | 1536 | |
e1910fcd GU |
1537 | if (s->chan_rx) { |
1538 | u16 scr = serial_port_in(port, SCSCR); | |
1539 | u16 ssr = serial_port_in(port, SCxSR); | |
73a19e4c | 1540 | |
e1910fcd GU |
1541 | /* Disable future Rx interrupts */ |
1542 | if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) { | |
1543 | disable_irq_nosync(irq); | |
1544 | scr |= SCSCR_RDRQE; | |
1545 | } else { | |
1546 | scr &= ~SCSCR_RIE; | |
756981be | 1547 | sci_submit_rx(s); |
e1910fcd GU |
1548 | } |
1549 | serial_port_out(port, SCSCR, scr); | |
1550 | /* Clear current interrupt */ | |
1551 | serial_port_out(port, SCxSR, | |
1552 | ssr & ~(SCIF_DR | SCxSR_RDxF(port))); | |
1553 | dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u jiffies\n", | |
1554 | jiffies, s->rx_timeout); | |
1555 | mod_timer(&s->rx_timer, jiffies + s->rx_timeout); | |
73a19e4c | 1556 | |
e1910fcd GU |
1557 | return IRQ_HANDLED; |
1558 | } | |
1559 | #endif | |
73a19e4c | 1560 | |
e1910fcd GU |
1561 | /* I think sci_receive_chars has to be called irrespective |
1562 | * of whether the I_IXOFF is set, otherwise, how is the interrupt | |
1563 | * to be disabled? | |
1564 | */ | |
1565 | sci_receive_chars(ptr); | |
1566 | ||
1567 | return IRQ_HANDLED; | |
73a19e4c GL |
1568 | } |
1569 | ||
e1910fcd | 1570 | static irqreturn_t sci_tx_interrupt(int irq, void *ptr) |
73a19e4c | 1571 | { |
e1910fcd | 1572 | struct uart_port *port = ptr; |
04928b79 | 1573 | unsigned long flags; |
73a19e4c | 1574 | |
04928b79 | 1575 | spin_lock_irqsave(&port->lock, flags); |
e1910fcd | 1576 | sci_transmit_chars(port); |
04928b79 | 1577 | spin_unlock_irqrestore(&port->lock, flags); |
e1910fcd GU |
1578 | |
1579 | return IRQ_HANDLED; | |
73a19e4c GL |
1580 | } |
1581 | ||
e1910fcd | 1582 | static irqreturn_t sci_er_interrupt(int irq, void *ptr) |
73a19e4c | 1583 | { |
e1910fcd GU |
1584 | struct uart_port *port = ptr; |
1585 | struct sci_port *s = to_sci_port(port); | |
73a19e4c | 1586 | |
e1910fcd GU |
1587 | /* Handle errors */ |
1588 | if (port->type == PORT_SCI) { | |
1589 | if (sci_handle_errors(port)) { | |
1590 | /* discard character in rx buffer */ | |
1591 | serial_port_in(port, SCxSR); | |
1592 | sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port)); | |
1593 | } | |
1594 | } else { | |
1595 | sci_handle_fifo_overrun(port); | |
1596 | if (!s->chan_rx) | |
1597 | sci_receive_chars(ptr); | |
1598 | } | |
1599 | ||
1600 | sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port)); | |
1601 | ||
1602 | /* Kick the transmission */ | |
1603 | if (!s->chan_tx) | |
1604 | sci_tx_interrupt(irq, ptr); | |
1605 | ||
1606 | return IRQ_HANDLED; | |
73a19e4c GL |
1607 | } |
1608 | ||
e1910fcd | 1609 | static irqreturn_t sci_br_interrupt(int irq, void *ptr) |
73a19e4c | 1610 | { |
e1910fcd | 1611 | struct uart_port *port = ptr; |
73a19e4c | 1612 | |
e1910fcd GU |
1613 | /* Handle BREAKs */ |
1614 | sci_handle_breaks(port); | |
1615 | sci_clear_SCxSR(port, SCxSR_BREAK_CLEAR(port)); | |
73a19e4c | 1616 | |
e1910fcd GU |
1617 | return IRQ_HANDLED; |
1618 | } | |
73a19e4c | 1619 | |
e1910fcd GU |
1620 | static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr) |
1621 | { | |
1622 | unsigned short ssr_status, scr_status, err_enabled, orer_status = 0; | |
1623 | struct uart_port *port = ptr; | |
1624 | struct sci_port *s = to_sci_port(port); | |
1625 | irqreturn_t ret = IRQ_NONE; | |
73a19e4c | 1626 | |
e1910fcd GU |
1627 | ssr_status = serial_port_in(port, SCxSR); |
1628 | scr_status = serial_port_in(port, SCSCR); | |
1629 | if (s->overrun_reg == SCxSR) | |
1630 | orer_status = ssr_status; | |
1631 | else { | |
1632 | if (sci_getreg(port, s->overrun_reg)->size) | |
1633 | orer_status = serial_port_in(port, s->overrun_reg); | |
73a19e4c GL |
1634 | } |
1635 | ||
e1910fcd | 1636 | err_enabled = scr_status & port_rx_irq_mask(port); |
73a19e4c | 1637 | |
e1910fcd GU |
1638 | /* Tx Interrupt */ |
1639 | if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) && | |
1640 | !s->chan_tx) | |
1641 | ret = sci_tx_interrupt(irq, ptr); | |
658daa95 | 1642 | |
e1910fcd GU |
1643 | /* |
1644 | * Rx Interrupt: if we're using DMA, the DMA controller clears RDF / | |
1645 | * DR flags | |
1646 | */ | |
1647 | if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) && | |
1648 | (scr_status & SCSCR_RIE)) | |
1649 | ret = sci_rx_interrupt(irq, ptr); | |
73a19e4c | 1650 | |
e1910fcd GU |
1651 | /* Error Interrupt */ |
1652 | if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled) | |
1653 | ret = sci_er_interrupt(irq, ptr); | |
73a19e4c | 1654 | |
e1910fcd GU |
1655 | /* Break Interrupt */ |
1656 | if ((ssr_status & SCxSR_BRK(port)) && err_enabled) | |
1657 | ret = sci_br_interrupt(irq, ptr); | |
1658 | ||
1659 | /* Overrun Interrupt */ | |
1660 | if (orer_status & s->overrun_mask) { | |
1661 | sci_handle_fifo_overrun(port); | |
1662 | ret = IRQ_HANDLED; | |
73a19e4c | 1663 | } |
73a19e4c | 1664 | |
e1910fcd GU |
1665 | return ret; |
1666 | } | |
73a19e4c | 1667 | |
e1910fcd GU |
1668 | static const struct sci_irq_desc { |
1669 | const char *desc; | |
1670 | irq_handler_t handler; | |
1671 | } sci_irq_desc[] = { | |
1672 | /* | |
1673 | * Split out handlers, the default case. | |
1674 | */ | |
1675 | [SCIx_ERI_IRQ] = { | |
1676 | .desc = "rx err", | |
1677 | .handler = sci_er_interrupt, | |
1678 | }, | |
3089f381 | 1679 | |
e1910fcd GU |
1680 | [SCIx_RXI_IRQ] = { |
1681 | .desc = "rx full", | |
1682 | .handler = sci_rx_interrupt, | |
1683 | }, | |
47aceb92 | 1684 | |
e1910fcd GU |
1685 | [SCIx_TXI_IRQ] = { |
1686 | .desc = "tx empty", | |
1687 | .handler = sci_tx_interrupt, | |
1688 | }, | |
73a19e4c | 1689 | |
e1910fcd GU |
1690 | [SCIx_BRI_IRQ] = { |
1691 | .desc = "break", | |
1692 | .handler = sci_br_interrupt, | |
1693 | }, | |
73a19e4c GL |
1694 | |
1695 | /* | |
e1910fcd | 1696 | * Special muxed handler. |
73a19e4c | 1697 | */ |
e1910fcd GU |
1698 | [SCIx_MUX_IRQ] = { |
1699 | .desc = "mux", | |
1700 | .handler = sci_mpxed_interrupt, | |
1701 | }, | |
1702 | }; | |
73a19e4c | 1703 | |
e1910fcd GU |
1704 | static int sci_request_irq(struct sci_port *port) |
1705 | { | |
1706 | struct uart_port *up = &port->port; | |
1707 | int i, j, ret = 0; | |
73a19e4c | 1708 | |
e1910fcd GU |
1709 | for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) { |
1710 | const struct sci_irq_desc *desc; | |
1711 | int irq; | |
73a19e4c | 1712 | |
e1910fcd GU |
1713 | if (SCIx_IRQ_IS_MUXED(port)) { |
1714 | i = SCIx_MUX_IRQ; | |
1715 | irq = up->irq; | |
1716 | } else { | |
1717 | irq = port->irqs[i]; | |
1718 | ||
1719 | /* | |
1720 | * Certain port types won't support all of the | |
1721 | * available interrupt sources. | |
1722 | */ | |
1723 | if (unlikely(irq < 0)) | |
1724 | continue; | |
1725 | } | |
1726 | ||
1727 | desc = sci_irq_desc + i; | |
1728 | port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s", | |
1729 | dev_name(up->dev), desc->desc); | |
1730 | if (!port->irqstr[j]) | |
1731 | goto out_nomem; | |
1732 | ||
1733 | ret = request_irq(irq, desc->handler, up->irqflags, | |
1734 | port->irqstr[j], port); | |
1735 | if (unlikely(ret)) { | |
1736 | dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc); | |
1737 | goto out_noirq; | |
1738 | } | |
73a19e4c GL |
1739 | } |
1740 | ||
e1910fcd | 1741 | return 0; |
1da177e4 | 1742 | |
e1910fcd GU |
1743 | out_noirq: |
1744 | while (--i >= 0) | |
1745 | free_irq(port->irqs[i], port); | |
f43dc23d | 1746 | |
e1910fcd GU |
1747 | out_nomem: |
1748 | while (--j >= 0) | |
1749 | kfree(port->irqstr[j]); | |
f43dc23d | 1750 | |
e1910fcd | 1751 | return ret; |
1da177e4 LT |
1752 | } |
1753 | ||
e1910fcd | 1754 | static void sci_free_irq(struct sci_port *port) |
1da177e4 | 1755 | { |
e1910fcd | 1756 | int i; |
1da177e4 | 1757 | |
e1910fcd GU |
1758 | /* |
1759 | * Intentionally in reverse order so we iterate over the muxed | |
1760 | * IRQ first. | |
1761 | */ | |
1762 | for (i = 0; i < SCIx_NR_IRQS; i++) { | |
1763 | int irq = port->irqs[i]; | |
f43dc23d | 1764 | |
e1910fcd GU |
1765 | /* |
1766 | * Certain port types won't support all of the available | |
1767 | * interrupt sources. | |
1768 | */ | |
1769 | if (unlikely(irq < 0)) | |
1770 | continue; | |
f43dc23d | 1771 | |
e1910fcd GU |
1772 | free_irq(port->irqs[i], port); |
1773 | kfree(port->irqstr[i]); | |
f43dc23d | 1774 | |
e1910fcd GU |
1775 | if (SCIx_IRQ_IS_MUXED(port)) { |
1776 | /* If there's only one IRQ, we're done. */ | |
1777 | return; | |
1778 | } | |
1779 | } | |
1da177e4 LT |
1780 | } |
1781 | ||
e1910fcd | 1782 | static unsigned int sci_tx_empty(struct uart_port *port) |
1da177e4 | 1783 | { |
e1910fcd GU |
1784 | unsigned short status = serial_port_in(port, SCxSR); |
1785 | unsigned short in_tx_fifo = sci_txfill(port); | |
f43dc23d | 1786 | |
e1910fcd | 1787 | return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0; |
1da177e4 LT |
1788 | } |
1789 | ||
e1910fcd GU |
1790 | /* |
1791 | * Modem control is a bit of a mixed bag for SCI(F) ports. Generally | |
1792 | * CTS/RTS is supported in hardware by at least one port and controlled | |
1793 | * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently | |
1794 | * handled via the ->init_pins() op, which is a bit of a one-way street, | |
1795 | * lacking any ability to defer pin control -- this will later be | |
1796 | * converted over to the GPIO framework). | |
1797 | * | |
1798 | * Other modes (such as loopback) are supported generically on certain | |
1799 | * port types, but not others. For these it's sufficient to test for the | |
1800 | * existence of the support register and simply ignore the port type. | |
1801 | */ | |
1802 | static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl) | |
1da177e4 | 1803 | { |
e1910fcd GU |
1804 | if (mctrl & TIOCM_LOOP) { |
1805 | const struct plat_sci_reg *reg; | |
f43dc23d | 1806 | |
e1910fcd GU |
1807 | /* |
1808 | * Standard loopback mode for SCFCR ports. | |
1809 | */ | |
1810 | reg = sci_getreg(port, SCFCR); | |
1811 | if (reg->size) | |
1812 | serial_port_out(port, SCFCR, | |
1813 | serial_port_in(port, SCFCR) | | |
1814 | SCFCR_LOOP); | |
1815 | } | |
1816 | } | |
f43dc23d | 1817 | |
e1910fcd GU |
1818 | static unsigned int sci_get_mctrl(struct uart_port *port) |
1819 | { | |
1820 | /* | |
1821 | * CTS/RTS is handled in hardware when supported, while nothing | |
1822 | * else is wired up. Keep it simple and simply assert DSR/CAR. | |
1823 | */ | |
1824 | return TIOCM_DSR | TIOCM_CAR; | |
1da177e4 LT |
1825 | } |
1826 | ||
1da177e4 LT |
1827 | static void sci_break_ctl(struct uart_port *port, int break_state) |
1828 | { | |
bbb4ce50 | 1829 | struct sci_port *s = to_sci_port(port); |
d3184e68 | 1830 | const struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR; |
bbb4ce50 SY |
1831 | unsigned short scscr, scsptr; |
1832 | ||
a4e02f6d SY |
1833 | /* check wheter the port has SCSPTR */ |
1834 | if (!reg->size) { | |
bbb4ce50 SY |
1835 | /* |
1836 | * Not supported by hardware. Most parts couple break and rx | |
1837 | * interrupts together, with break detection always enabled. | |
1838 | */ | |
a4e02f6d | 1839 | return; |
bbb4ce50 | 1840 | } |
a4e02f6d SY |
1841 | |
1842 | scsptr = serial_port_in(port, SCSPTR); | |
1843 | scscr = serial_port_in(port, SCSCR); | |
1844 | ||
1845 | if (break_state == -1) { | |
1846 | scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT; | |
1847 | scscr &= ~SCSCR_TE; | |
1848 | } else { | |
1849 | scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO; | |
1850 | scscr |= SCSCR_TE; | |
1851 | } | |
1852 | ||
1853 | serial_port_out(port, SCSPTR, scsptr); | |
1854 | serial_port_out(port, SCSCR, scscr); | |
1da177e4 LT |
1855 | } |
1856 | ||
1857 | static int sci_startup(struct uart_port *port) | |
1858 | { | |
a5660ada | 1859 | struct sci_port *s = to_sci_port(port); |
33b48e16 | 1860 | unsigned long flags; |
073e84c9 | 1861 | int ret; |
1da177e4 | 1862 | |
73a19e4c GL |
1863 | dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); |
1864 | ||
073e84c9 PM |
1865 | ret = sci_request_irq(s); |
1866 | if (unlikely(ret < 0)) | |
1867 | return ret; | |
1868 | ||
73a19e4c | 1869 | sci_request_dma(port); |
073e84c9 | 1870 | |
33b48e16 | 1871 | spin_lock_irqsave(&port->lock, flags); |
d656901b | 1872 | sci_start_tx(port); |
73a19e4c | 1873 | sci_start_rx(port); |
33b48e16 | 1874 | spin_unlock_irqrestore(&port->lock, flags); |
1da177e4 LT |
1875 | |
1876 | return 0; | |
1877 | } | |
1878 | ||
1879 | static void sci_shutdown(struct uart_port *port) | |
1880 | { | |
a5660ada | 1881 | struct sci_port *s = to_sci_port(port); |
33b48e16 | 1882 | unsigned long flags; |
1da177e4 | 1883 | |
73a19e4c GL |
1884 | dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); |
1885 | ||
33b48e16 | 1886 | spin_lock_irqsave(&port->lock, flags); |
1da177e4 | 1887 | sci_stop_rx(port); |
b129a8cc | 1888 | sci_stop_tx(port); |
33b48e16 | 1889 | spin_unlock_irqrestore(&port->lock, flags); |
073e84c9 | 1890 | |
9ab76556 AM |
1891 | #ifdef CONFIG_SERIAL_SH_SCI_DMA |
1892 | if (s->chan_rx) { | |
1893 | dev_dbg(port->dev, "%s(%d) deleting rx_timer\n", __func__, | |
1894 | port->line); | |
1895 | del_timer_sync(&s->rx_timer); | |
1896 | } | |
1897 | #endif | |
1898 | ||
73a19e4c | 1899 | sci_free_dma(port); |
1da177e4 | 1900 | sci_free_irq(s); |
1da177e4 LT |
1901 | } |
1902 | ||
6af27bf2 GU |
1903 | static int sci_sck_calc(struct sci_port *s, unsigned int bps, |
1904 | unsigned int *srr) | |
26c92f37 | 1905 | { |
6af27bf2 GU |
1906 | unsigned long freq = s->clk_rates[SCI_SCK]; |
1907 | unsigned int min_sr, max_sr, sr; | |
1908 | int err, min_err = INT_MAX; | |
1909 | ||
1910 | if (s->sampling_rate) { | |
1911 | /* SCI(F) has a fixed sampling rate */ | |
1912 | min_sr = max_sr = s->sampling_rate / 2; | |
1913 | } else { | |
1914 | /* HSCIF has a variable 1/(8..32) sampling rate */ | |
1915 | min_sr = 8; | |
1916 | max_sr = 32; | |
1917 | } | |
1918 | ||
1919 | for (sr = max_sr; sr >= min_sr; sr--) { | |
1920 | err = DIV_ROUND_CLOSEST(freq, sr) - bps; | |
1921 | if (abs(err) >= abs(min_err)) | |
1922 | continue; | |
1923 | ||
1924 | min_err = err; | |
1925 | *srr = sr - 1; | |
ec09c5eb | 1926 | |
6af27bf2 GU |
1927 | if (!err) |
1928 | break; | |
1929 | } | |
e8183a6c | 1930 | |
6af27bf2 GU |
1931 | dev_dbg(s->port.dev, "SCK: %u%+d bps using SR %u\n", bps, min_err, |
1932 | *srr + 1); | |
1933 | return min_err; | |
26c92f37 PM |
1934 | } |
1935 | ||
1270f865 GU |
1936 | static int sci_brg_calc(struct sci_port *s, unsigned int bps, |
1937 | unsigned long freq, unsigned int *dlr, | |
1938 | unsigned int *srr) | |
730c4e78 | 1939 | { |
1270f865 GU |
1940 | unsigned int min_sr, max_sr, sr, dl; |
1941 | int err, min_err = INT_MAX; | |
730c4e78 | 1942 | |
1270f865 GU |
1943 | if (s->sampling_rate) { |
1944 | /* SCIF has a fixed sampling rate */ | |
1945 | min_sr = max_sr = s->sampling_rate / 2; | |
1946 | } else { | |
1947 | /* HSCIF has a variable 1/(8..32) sampling rate */ | |
1948 | min_sr = 8; | |
1949 | max_sr = 32; | |
1950 | } | |
730c4e78 | 1951 | |
1270f865 GU |
1952 | for (sr = max_sr; sr >= min_sr; sr--) { |
1953 | dl = DIV_ROUND_CLOSEST(freq, sr * bps); | |
1954 | dl = clamp(dl, 1U, 65535U); | |
1955 | ||
1956 | err = DIV_ROUND_CLOSEST(freq, sr * dl) - bps; | |
1957 | if (abs(err) >= abs(min_err)) | |
1958 | continue; | |
1959 | ||
1960 | min_err = err; | |
1961 | *dlr = dl; | |
1962 | *srr = sr - 1; | |
1963 | ||
1964 | if (!err) | |
1965 | break; | |
1966 | } | |
730c4e78 | 1967 | |
1270f865 GU |
1968 | dev_dbg(s->port.dev, "BRG: %u%+d bps using DL %u SR %u\n", bps, |
1969 | min_err, *dlr, *srr + 1); | |
1970 | return min_err; | |
1971 | } | |
730c4e78 | 1972 | |
b4a5c459 | 1973 | /* calculate sample rate, BRR, and clock select */ |
f4998e55 GU |
1974 | static int sci_scbrr_calc(struct sci_port *s, unsigned int bps, |
1975 | unsigned int *brr, unsigned int *srr, | |
1976 | unsigned int *cks) | |
f303b364 | 1977 | { |
b4a5c459 | 1978 | unsigned int min_sr, max_sr, shift, sr, br, prediv, scrate, c; |
f4998e55 | 1979 | unsigned long freq = s->clk_rates[SCI_FCK]; |
6c51332d | 1980 | int err, min_err = INT_MAX; |
f303b364 | 1981 | |
b4a5c459 GU |
1982 | if (s->sampling_rate) { |
1983 | min_sr = max_sr = s->sampling_rate; | |
1984 | shift = 0; | |
1985 | } else { | |
1986 | /* HSCIF has a variable sample rate */ | |
1987 | min_sr = 8; | |
1988 | max_sr = 32; | |
1989 | shift = 1; | |
1990 | } | |
1991 | ||
6c51332d GU |
1992 | /* |
1993 | * Find the combination of sample rate and clock select with the | |
1994 | * smallest deviation from the desired baud rate. | |
1995 | * Prefer high sample rates to maximise the receive margin. | |
1996 | * | |
1997 | * M: Receive margin (%) | |
1998 | * N: Ratio of bit rate to clock (N = sampling rate) | |
1999 | * D: Clock duty (D = 0 to 1.0) | |
2000 | * L: Frame length (L = 9 to 12) | |
2001 | * F: Absolute value of clock frequency deviation | |
2002 | * | |
2003 | * M = |(0.5 - 1 / 2 * N) - ((L - 0.5) * F) - | |
2004 | * (|D - 0.5| / N * (1 + F))| | |
2005 | * NOTE: Usually, treat D for 0.5, F is 0 by this calculation. | |
2006 | */ | |
b4a5c459 | 2007 | for (sr = max_sr; sr >= min_sr; sr--) { |
f303b364 UH |
2008 | for (c = 0; c <= 3; c++) { |
2009 | /* integerized formulas from HSCIF documentation */ | |
b4a5c459 | 2010 | prediv = sr * (1 << (2 * c + shift)); |
de01e6cd GU |
2011 | |
2012 | /* | |
2013 | * We need to calculate: | |
2014 | * | |
2015 | * br = freq / (prediv * bps) clamped to [1..256] | |
881a7489 | 2016 | * err = freq / (br * prediv) - bps |
730c4e78 | 2017 | * |
de01e6cd GU |
2018 | * Watch out for overflow when calculating the desired |
2019 | * sampling clock rate! | |
730c4e78 | 2020 | */ |
de01e6cd GU |
2021 | if (bps > UINT_MAX / prediv) |
2022 | break; | |
2023 | ||
2024 | scrate = prediv * bps; | |
2025 | br = DIV_ROUND_CLOSEST(freq, scrate); | |
95a2703e | 2026 | br = clamp(br, 1U, 256U); |
6c51332d | 2027 | |
881a7489 | 2028 | err = DIV_ROUND_CLOSEST(freq, br * prediv) - bps; |
6c51332d | 2029 | if (abs(err) >= abs(min_err)) |
730c4e78 NI |
2030 | continue; |
2031 | ||
6c51332d | 2032 | min_err = err; |
95a2703e | 2033 | *brr = br - 1; |
730c4e78 NI |
2034 | *srr = sr - 1; |
2035 | *cks = c; | |
6c51332d GU |
2036 | |
2037 | if (!err) | |
2038 | goto found; | |
f303b364 UH |
2039 | } |
2040 | } | |
2041 | ||
6c51332d | 2042 | found: |
881a7489 GU |
2043 | dev_dbg(s->port.dev, "BRR: %u%+d bps using N %u SR %u cks %u\n", bps, |
2044 | min_err, *brr, *srr + 1, *cks); | |
f4998e55 | 2045 | return min_err; |
f303b364 UH |
2046 | } |
2047 | ||
1ba76220 MD |
2048 | static void sci_reset(struct uart_port *port) |
2049 | { | |
d3184e68 | 2050 | const struct plat_sci_reg *reg; |
1ba76220 MD |
2051 | unsigned int status; |
2052 | ||
2053 | do { | |
b12bb29f | 2054 | status = serial_port_in(port, SCxSR); |
1ba76220 MD |
2055 | } while (!(status & SCxSR_TEND(port))); |
2056 | ||
b12bb29f | 2057 | serial_port_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */ |
1ba76220 | 2058 | |
0979e0e6 PM |
2059 | reg = sci_getreg(port, SCFCR); |
2060 | if (reg->size) | |
b12bb29f | 2061 | serial_port_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST); |
1ba76220 MD |
2062 | } |
2063 | ||
606d099c AC |
2064 | static void sci_set_termios(struct uart_port *port, struct ktermios *termios, |
2065 | struct ktermios *old) | |
1da177e4 | 2066 | { |
95ee05c7 | 2067 | unsigned int baud, smr_val = SCSMR_ASYNC, scr_val = 0, i; |
1270f865 GU |
2068 | unsigned int brr = 255, cks = 0, srr = 15, dl = 0, sccks = 0; |
2069 | unsigned int brr1 = 255, cks1 = 0, srr1 = 15, dl1 = 0; | |
00b9de9c | 2070 | struct sci_port *s = to_sci_port(port); |
d3184e68 | 2071 | const struct plat_sci_reg *reg; |
f4998e55 GU |
2072 | int min_err = INT_MAX, err; |
2073 | unsigned long max_freq = 0; | |
2074 | int best_clk = -1; | |
1da177e4 | 2075 | |
730c4e78 NI |
2076 | if ((termios->c_cflag & CSIZE) == CS7) |
2077 | smr_val |= SCSMR_CHR; | |
2078 | if (termios->c_cflag & PARENB) | |
2079 | smr_val |= SCSMR_PE; | |
2080 | if (termios->c_cflag & PARODD) | |
2081 | smr_val |= SCSMR_PE | SCSMR_ODD; | |
2082 | if (termios->c_cflag & CSTOPB) | |
2083 | smr_val |= SCSMR_STOP; | |
2084 | ||
154280fd MD |
2085 | /* |
2086 | * earlyprintk comes here early on with port->uartclk set to zero. | |
2087 | * the clock framework is not up and running at this point so here | |
2088 | * we assume that 115200 is the maximum baud rate. please note that | |
2089 | * the baud rate is not programmed during earlyprintk - it is assumed | |
2090 | * that the previous boot loader has enabled required clocks and | |
2091 | * setup the baud rate generator hardware for us already. | |
2092 | */ | |
f4998e55 GU |
2093 | if (!port->uartclk) { |
2094 | baud = uart_get_baud_rate(port, termios, old, 0, 115200); | |
2095 | goto done; | |
2096 | } | |
1da177e4 | 2097 | |
f4998e55 GU |
2098 | for (i = 0; i < SCI_NUM_CLKS; i++) |
2099 | max_freq = max(max_freq, s->clk_rates[i]); | |
2100 | ||
2101 | baud = uart_get_baud_rate(port, termios, old, 0, | |
2102 | max_freq / max(s->sampling_rate, 8U)); | |
2103 | if (!baud) | |
2104 | goto done; | |
2105 | ||
2106 | /* | |
2107 | * There can be multiple sources for the sampling clock. Find the one | |
2108 | * that gives us the smallest deviation from the desired baud rate. | |
2109 | */ | |
2110 | ||
6af27bf2 GU |
2111 | /* Optional Undivided External Clock */ |
2112 | if (s->clk_rates[SCI_SCK] && port->type != PORT_SCIFA && | |
2113 | port->type != PORT_SCIFB) { | |
2114 | err = sci_sck_calc(s, baud, &srr1); | |
2115 | if (abs(err) < abs(min_err)) { | |
2116 | best_clk = SCI_SCK; | |
2117 | scr_val = SCSCR_CKE1; | |
2118 | sccks = SCCKS_CKS; | |
2119 | min_err = err; | |
2120 | srr = srr1; | |
2121 | if (!err) | |
2122 | goto done; | |
2123 | } | |
2124 | } | |
2125 | ||
1270f865 GU |
2126 | /* Optional BRG Frequency Divided External Clock */ |
2127 | if (s->clk_rates[SCI_SCIF_CLK] && sci_getreg(port, SCDL)->size) { | |
2128 | err = sci_brg_calc(s, baud, s->clk_rates[SCI_SCIF_CLK], &dl1, | |
2129 | &srr1); | |
2130 | if (abs(err) < abs(min_err)) { | |
2131 | best_clk = SCI_SCIF_CLK; | |
2132 | scr_val = SCSCR_CKE1; | |
2133 | sccks = 0; | |
2134 | min_err = err; | |
2135 | dl = dl1; | |
2136 | srr = srr1; | |
2137 | if (!err) | |
2138 | goto done; | |
2139 | } | |
2140 | } | |
2141 | ||
2142 | /* Optional BRG Frequency Divided Internal Clock */ | |
2143 | if (s->clk_rates[SCI_BRG_INT] && sci_getreg(port, SCDL)->size) { | |
2144 | err = sci_brg_calc(s, baud, s->clk_rates[SCI_BRG_INT], &dl1, | |
2145 | &srr1); | |
2146 | if (abs(err) < abs(min_err)) { | |
2147 | best_clk = SCI_BRG_INT; | |
2148 | scr_val = SCSCR_CKE1; | |
2149 | sccks = SCCKS_XIN; | |
2150 | min_err = err; | |
2151 | dl = dl1; | |
2152 | srr = srr1; | |
2153 | if (!min_err) | |
2154 | goto done; | |
f303b364 UH |
2155 | } |
2156 | } | |
e108b2ca | 2157 | |
f4998e55 GU |
2158 | /* Divided Functional Clock using standard Bit Rate Register */ |
2159 | err = sci_scbrr_calc(s, baud, &brr1, &srr1, &cks1); | |
2160 | if (abs(err) < abs(min_err)) { | |
2161 | best_clk = SCI_FCK; | |
6af27bf2 | 2162 | scr_val = 0; |
f4998e55 GU |
2163 | min_err = err; |
2164 | brr = brr1; | |
2165 | srr = srr1; | |
2166 | cks = cks1; | |
2167 | } | |
2168 | ||
2169 | done: | |
2170 | if (best_clk >= 0) | |
2171 | dev_dbg(port->dev, "Using clk %pC for %u%+d bps\n", | |
2172 | s->clks[best_clk], baud, min_err); | |
e108b2ca | 2173 | |
23241d43 | 2174 | sci_port_enable(s); |
36003386 | 2175 | |
6af27bf2 GU |
2176 | /* |
2177 | * Program the optional External Baud Rate Generator (BRG) first. | |
2178 | * It controls the mux to select (H)SCK or frequency divided clock. | |
2179 | */ | |
1270f865 GU |
2180 | if (best_clk >= 0 && sci_getreg(port, SCCKS)->size) { |
2181 | serial_port_out(port, SCDL, dl); | |
6af27bf2 | 2182 | serial_port_out(port, SCCKS, sccks); |
1270f865 | 2183 | } |
1da177e4 | 2184 | |
1ba76220 | 2185 | sci_reset(port); |
1da177e4 LT |
2186 | |
2187 | uart_update_timeout(port, termios->c_cflag, baud); | |
2188 | ||
f4998e55 GU |
2189 | if (best_clk >= 0) { |
2190 | smr_val |= cks; | |
6af27bf2 | 2191 | dev_dbg(port->dev, |
1270f865 GU |
2192 | "SCR 0x%x SMR 0x%x BRR %u CKS 0x%x DL %u SRR %u\n", |
2193 | scr_val, smr_val, brr, sccks, dl, srr); | |
6af27bf2 | 2194 | serial_port_out(port, SCSCR, scr_val); |
f4998e55 GU |
2195 | serial_port_out(port, SCSMR, smr_val); |
2196 | serial_port_out(port, SCBRR, brr); | |
2197 | if (sci_getreg(port, HSSRR)->size) | |
f303b364 | 2198 | serial_port_out(port, HSSRR, srr | HSCIF_SRE); |
f4998e55 GU |
2199 | |
2200 | /* Wait one bit interval */ | |
2201 | udelay((1000000 + (baud - 1)) / baud); | |
2202 | } else { | |
2203 | /* Don't touch the bit rate configuration */ | |
2204 | scr_val = s->cfg->scscr & (SCSCR_CKE1 | SCSCR_CKE0); | |
3a964abe GU |
2205 | smr_val |= serial_port_in(port, SCSMR) & |
2206 | (SCSMR_CKEDG | SCSMR_SRC_MASK | SCSMR_CKS); | |
f4998e55 GU |
2207 | dev_dbg(port->dev, "SCR 0x%x SMR 0x%x\n", scr_val, smr_val); |
2208 | serial_port_out(port, SCSCR, scr_val); | |
9d482cc3 | 2209 | serial_port_out(port, SCSMR, smr_val); |
f4998e55 | 2210 | } |
1da177e4 | 2211 | |
d5701647 | 2212 | sci_init_pins(port, termios->c_cflag); |
0979e0e6 | 2213 | |
73c3d53f PM |
2214 | reg = sci_getreg(port, SCFCR); |
2215 | if (reg->size) { | |
b12bb29f | 2216 | unsigned short ctrl = serial_port_in(port, SCFCR); |
0979e0e6 | 2217 | |
73c3d53f | 2218 | if (s->cfg->capabilities & SCIx_HAVE_RTSCTS) { |
faf02f8f PM |
2219 | if (termios->c_cflag & CRTSCTS) |
2220 | ctrl |= SCFCR_MCE; | |
2221 | else | |
2222 | ctrl &= ~SCFCR_MCE; | |
faf02f8f | 2223 | } |
73c3d53f PM |
2224 | |
2225 | /* | |
2226 | * As we've done a sci_reset() above, ensure we don't | |
2227 | * interfere with the FIFOs while toggling MCE. As the | |
2228 | * reset values could still be set, simply mask them out. | |
2229 | */ | |
2230 | ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST); | |
2231 | ||
b12bb29f | 2232 | serial_port_out(port, SCFCR, ctrl); |
0979e0e6 | 2233 | } |
b7a76e4b | 2234 | |
f4998e55 GU |
2235 | scr_val |= s->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0); |
2236 | dev_dbg(port->dev, "SCSCR 0x%x\n", scr_val); | |
2237 | serial_port_out(port, SCSCR, scr_val); | |
1da177e4 | 2238 | |
3089f381 GL |
2239 | #ifdef CONFIG_SERIAL_SH_SCI_DMA |
2240 | /* | |
5f6d8515 | 2241 | * Calculate delay for 2 DMA buffers (4 FIFO). |
f5835c1d GU |
2242 | * See serial_core.c::uart_update_timeout(). |
2243 | * With 10 bits (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above | |
2244 | * function calculates 1 jiffie for the data plus 5 jiffies for the | |
2245 | * "slop(e)." Then below we calculate 5 jiffies (20ms) for 2 DMA | |
2246 | * buffers (4 FIFO sizes), but when performing a faster transfer, the | |
2247 | * value obtained by this formula is too small. Therefore, if the value | |
2248 | * is smaller than 20ms, use 20ms as the timeout value for DMA. | |
3089f381 GL |
2249 | */ |
2250 | if (s->chan_rx) { | |
5f6d8515 NI |
2251 | unsigned int bits; |
2252 | ||
2253 | /* byte size and parity */ | |
2254 | switch (termios->c_cflag & CSIZE) { | |
2255 | case CS5: | |
2256 | bits = 7; | |
2257 | break; | |
2258 | case CS6: | |
2259 | bits = 8; | |
2260 | break; | |
2261 | case CS7: | |
2262 | bits = 9; | |
2263 | break; | |
2264 | default: | |
2265 | bits = 10; | |
2266 | break; | |
2267 | } | |
2268 | ||
2269 | if (termios->c_cflag & CSTOPB) | |
2270 | bits++; | |
2271 | if (termios->c_cflag & PARENB) | |
2272 | bits++; | |
2273 | s->rx_timeout = DIV_ROUND_UP((s->buf_len_rx * 2 * bits * HZ) / | |
2274 | (baud / 10), 10); | |
9b971cd2 | 2275 | dev_dbg(port->dev, "DMA Rx t-out %ums, tty t-out %u jiffies\n", |
3089f381 GL |
2276 | s->rx_timeout * 1000 / HZ, port->timeout); |
2277 | if (s->rx_timeout < msecs_to_jiffies(20)) | |
2278 | s->rx_timeout = msecs_to_jiffies(20); | |
2279 | } | |
2280 | #endif | |
2281 | ||
1da177e4 | 2282 | if ((termios->c_cflag & CREAD) != 0) |
73a19e4c | 2283 | sci_start_rx(port); |
36003386 | 2284 | |
23241d43 | 2285 | sci_port_disable(s); |
1da177e4 LT |
2286 | } |
2287 | ||
0174e5ca TK |
2288 | static void sci_pm(struct uart_port *port, unsigned int state, |
2289 | unsigned int oldstate) | |
2290 | { | |
2291 | struct sci_port *sci_port = to_sci_port(port); | |
2292 | ||
2293 | switch (state) { | |
d3dfe5d9 | 2294 | case UART_PM_STATE_OFF: |
0174e5ca TK |
2295 | sci_port_disable(sci_port); |
2296 | break; | |
2297 | default: | |
2298 | sci_port_enable(sci_port); | |
2299 | break; | |
2300 | } | |
2301 | } | |
2302 | ||
1da177e4 LT |
2303 | static const char *sci_type(struct uart_port *port) |
2304 | { | |
2305 | switch (port->type) { | |
e7c98dc7 MT |
2306 | case PORT_IRDA: |
2307 | return "irda"; | |
2308 | case PORT_SCI: | |
2309 | return "sci"; | |
2310 | case PORT_SCIF: | |
2311 | return "scif"; | |
2312 | case PORT_SCIFA: | |
2313 | return "scifa"; | |
d1d4b10c GL |
2314 | case PORT_SCIFB: |
2315 | return "scifb"; | |
f303b364 UH |
2316 | case PORT_HSCIF: |
2317 | return "hscif"; | |
1da177e4 LT |
2318 | } |
2319 | ||
fa43972f | 2320 | return NULL; |
1da177e4 LT |
2321 | } |
2322 | ||
f6e9495d PM |
2323 | static int sci_remap_port(struct uart_port *port) |
2324 | { | |
e4d6f911 | 2325 | struct sci_port *sport = to_sci_port(port); |
f6e9495d PM |
2326 | |
2327 | /* | |
2328 | * Nothing to do if there's already an established membase. | |
2329 | */ | |
2330 | if (port->membase) | |
2331 | return 0; | |
2332 | ||
2333 | if (port->flags & UPF_IOREMAP) { | |
e4d6f911 | 2334 | port->membase = ioremap_nocache(port->mapbase, sport->reg_size); |
f6e9495d PM |
2335 | if (unlikely(!port->membase)) { |
2336 | dev_err(port->dev, "can't remap port#%d\n", port->line); | |
2337 | return -ENXIO; | |
2338 | } | |
2339 | } else { | |
2340 | /* | |
2341 | * For the simple (and majority of) cases where we don't | |
2342 | * need to do any remapping, just cast the cookie | |
2343 | * directly. | |
2344 | */ | |
3af4e960 | 2345 | port->membase = (void __iomem *)(uintptr_t)port->mapbase; |
f6e9495d PM |
2346 | } |
2347 | ||
2348 | return 0; | |
2349 | } | |
2350 | ||
e2651647 | 2351 | static void sci_release_port(struct uart_port *port) |
1da177e4 | 2352 | { |
e4d6f911 YS |
2353 | struct sci_port *sport = to_sci_port(port); |
2354 | ||
e2651647 PM |
2355 | if (port->flags & UPF_IOREMAP) { |
2356 | iounmap(port->membase); | |
2357 | port->membase = NULL; | |
2358 | } | |
2359 | ||
e4d6f911 | 2360 | release_mem_region(port->mapbase, sport->reg_size); |
1da177e4 LT |
2361 | } |
2362 | ||
e2651647 | 2363 | static int sci_request_port(struct uart_port *port) |
1da177e4 | 2364 | { |
e2651647 | 2365 | struct resource *res; |
e4d6f911 | 2366 | struct sci_port *sport = to_sci_port(port); |
f6e9495d | 2367 | int ret; |
1da177e4 | 2368 | |
e4d6f911 YS |
2369 | res = request_mem_region(port->mapbase, sport->reg_size, |
2370 | dev_name(port->dev)); | |
2371 | if (unlikely(res == NULL)) { | |
2372 | dev_err(port->dev, "request_mem_region failed."); | |
e2651647 | 2373 | return -EBUSY; |
e4d6f911 | 2374 | } |
1da177e4 | 2375 | |
f6e9495d PM |
2376 | ret = sci_remap_port(port); |
2377 | if (unlikely(ret != 0)) { | |
2378 | release_resource(res); | |
2379 | return ret; | |
7ff731ae | 2380 | } |
e2651647 PM |
2381 | |
2382 | return 0; | |
2383 | } | |
2384 | ||
2385 | static void sci_config_port(struct uart_port *port, int flags) | |
2386 | { | |
2387 | if (flags & UART_CONFIG_TYPE) { | |
2388 | struct sci_port *sport = to_sci_port(port); | |
2389 | ||
2390 | port->type = sport->cfg->type; | |
2391 | sci_request_port(port); | |
2392 | } | |
1da177e4 LT |
2393 | } |
2394 | ||
2395 | static int sci_verify_port(struct uart_port *port, struct serial_struct *ser) | |
2396 | { | |
1da177e4 LT |
2397 | if (ser->baud_base < 2400) |
2398 | /* No paper tape reader for Mitch.. */ | |
2399 | return -EINVAL; | |
2400 | ||
2401 | return 0; | |
2402 | } | |
2403 | ||
2404 | static struct uart_ops sci_uart_ops = { | |
2405 | .tx_empty = sci_tx_empty, | |
2406 | .set_mctrl = sci_set_mctrl, | |
2407 | .get_mctrl = sci_get_mctrl, | |
2408 | .start_tx = sci_start_tx, | |
2409 | .stop_tx = sci_stop_tx, | |
2410 | .stop_rx = sci_stop_rx, | |
1da177e4 LT |
2411 | .break_ctl = sci_break_ctl, |
2412 | .startup = sci_startup, | |
2413 | .shutdown = sci_shutdown, | |
2414 | .set_termios = sci_set_termios, | |
0174e5ca | 2415 | .pm = sci_pm, |
1da177e4 LT |
2416 | .type = sci_type, |
2417 | .release_port = sci_release_port, | |
2418 | .request_port = sci_request_port, | |
2419 | .config_port = sci_config_port, | |
2420 | .verify_port = sci_verify_port, | |
07d2a1a1 PM |
2421 | #ifdef CONFIG_CONSOLE_POLL |
2422 | .poll_get_char = sci_poll_get_char, | |
2423 | .poll_put_char = sci_poll_put_char, | |
2424 | #endif | |
1da177e4 LT |
2425 | }; |
2426 | ||
a9ec81f4 LP |
2427 | static int sci_init_clocks(struct sci_port *sci_port, struct device *dev) |
2428 | { | |
f4998e55 GU |
2429 | const char *clk_names[] = { |
2430 | [SCI_FCK] = "fck", | |
6af27bf2 | 2431 | [SCI_SCK] = "sck", |
1270f865 GU |
2432 | [SCI_BRG_INT] = "brg_int", |
2433 | [SCI_SCIF_CLK] = "scif_clk", | |
f4998e55 GU |
2434 | }; |
2435 | struct clk *clk; | |
2436 | unsigned int i; | |
a9ec81f4 | 2437 | |
6af27bf2 GU |
2438 | if (sci_port->cfg->type == PORT_HSCIF) |
2439 | clk_names[SCI_SCK] = "hsck"; | |
2440 | ||
f4998e55 GU |
2441 | for (i = 0; i < SCI_NUM_CLKS; i++) { |
2442 | clk = devm_clk_get(dev, clk_names[i]); | |
2443 | if (PTR_ERR(clk) == -EPROBE_DEFER) | |
2444 | return -EPROBE_DEFER; | |
a9ec81f4 | 2445 | |
f4998e55 GU |
2446 | if (IS_ERR(clk) && i == SCI_FCK) { |
2447 | /* | |
2448 | * "fck" used to be called "sci_ick", and we need to | |
2449 | * maintain DT backward compatibility. | |
2450 | */ | |
2451 | clk = devm_clk_get(dev, "sci_ick"); | |
2452 | if (PTR_ERR(clk) == -EPROBE_DEFER) | |
2453 | return -EPROBE_DEFER; | |
a9ec81f4 | 2454 | |
f4998e55 GU |
2455 | if (!IS_ERR(clk)) |
2456 | goto found; | |
a9ec81f4 | 2457 | |
f4998e55 GU |
2458 | /* |
2459 | * Not all SH platforms declare a clock lookup entry | |
2460 | * for SCI devices, in which case we need to get the | |
2461 | * global "peripheral_clk" clock. | |
2462 | */ | |
2463 | clk = devm_clk_get(dev, "peripheral_clk"); | |
2464 | if (!IS_ERR(clk)) | |
2465 | goto found; | |
2466 | ||
2467 | dev_err(dev, "failed to get %s (%ld)\n", clk_names[i], | |
2468 | PTR_ERR(clk)); | |
2469 | return PTR_ERR(clk); | |
2470 | } | |
2471 | ||
2472 | found: | |
2473 | if (IS_ERR(clk)) | |
2474 | dev_dbg(dev, "failed to get %s (%ld)\n", clk_names[i], | |
2475 | PTR_ERR(clk)); | |
2476 | else | |
2477 | dev_dbg(dev, "clk %s is %pC rate %pCr\n", clk_names[i], | |
2478 | clk, clk); | |
2479 | sci_port->clks[i] = IS_ERR(clk) ? NULL : clk; | |
2480 | } | |
2481 | return 0; | |
a9ec81f4 LP |
2482 | } |
2483 | ||
9671f099 | 2484 | static int sci_init_single(struct platform_device *dev, |
1fcc91a6 LP |
2485 | struct sci_port *sci_port, unsigned int index, |
2486 | struct plat_sci_port *p, bool early) | |
e108b2ca | 2487 | { |
73a19e4c | 2488 | struct uart_port *port = &sci_port->port; |
1fcc91a6 LP |
2489 | const struct resource *res; |
2490 | unsigned int i; | |
3127c6b2 | 2491 | int ret; |
e108b2ca | 2492 | |
50f0959a PM |
2493 | sci_port->cfg = p; |
2494 | ||
73a19e4c GL |
2495 | port->ops = &sci_uart_ops; |
2496 | port->iotype = UPIO_MEM; | |
2497 | port->line = index; | |
75136d48 | 2498 | |
89b5c1ab LP |
2499 | res = platform_get_resource(dev, IORESOURCE_MEM, 0); |
2500 | if (res == NULL) | |
2501 | return -ENOMEM; | |
1fcc91a6 | 2502 | |
89b5c1ab | 2503 | port->mapbase = res->start; |
e4d6f911 | 2504 | sci_port->reg_size = resource_size(res); |
1fcc91a6 | 2505 | |
89b5c1ab LP |
2506 | for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i) |
2507 | sci_port->irqs[i] = platform_get_irq(dev, i); | |
1fcc91a6 | 2508 | |
89b5c1ab LP |
2509 | /* The SCI generates several interrupts. They can be muxed together or |
2510 | * connected to different interrupt lines. In the muxed case only one | |
2511 | * interrupt resource is specified. In the non-muxed case three or four | |
2512 | * interrupt resources are specified, as the BRI interrupt is optional. | |
2513 | */ | |
2514 | if (sci_port->irqs[0] < 0) | |
2515 | return -ENXIO; | |
1fcc91a6 | 2516 | |
89b5c1ab LP |
2517 | if (sci_port->irqs[1] < 0) { |
2518 | sci_port->irqs[1] = sci_port->irqs[0]; | |
2519 | sci_port->irqs[2] = sci_port->irqs[0]; | |
2520 | sci_port->irqs[3] = sci_port->irqs[0]; | |
1fcc91a6 LP |
2521 | } |
2522 | ||
b545e4f4 LP |
2523 | if (p->regtype == SCIx_PROBE_REGTYPE) { |
2524 | ret = sci_probe_regmap(p); | |
2525 | if (unlikely(ret)) | |
2526 | return ret; | |
2527 | } | |
2528 | ||
75136d48 | 2529 | switch (p->type) { |
d1d4b10c GL |
2530 | case PORT_SCIFB: |
2531 | port->fifosize = 256; | |
2e0842a1 | 2532 | sci_port->overrun_reg = SCxSR; |
75c249fd | 2533 | sci_port->overrun_mask = SCIFA_ORER; |
f84b6bdc | 2534 | sci_port->sampling_rate = 16; |
d1d4b10c | 2535 | break; |
f303b364 UH |
2536 | case PORT_HSCIF: |
2537 | port->fifosize = 128; | |
2e0842a1 | 2538 | sci_port->overrun_reg = SCLSR; |
75c249fd | 2539 | sci_port->overrun_mask = SCLSR_ORER; |
f84b6bdc | 2540 | sci_port->sampling_rate = 0; |
f303b364 | 2541 | break; |
75136d48 | 2542 | case PORT_SCIFA: |
73a19e4c | 2543 | port->fifosize = 64; |
2e0842a1 | 2544 | sci_port->overrun_reg = SCxSR; |
75c249fd | 2545 | sci_port->overrun_mask = SCIFA_ORER; |
f84b6bdc | 2546 | sci_port->sampling_rate = 16; |
75136d48 MP |
2547 | break; |
2548 | case PORT_SCIF: | |
73a19e4c | 2549 | port->fifosize = 16; |
ec09c5eb | 2550 | if (p->regtype == SCIx_SH7705_SCIF_REGTYPE) { |
2e0842a1 | 2551 | sci_port->overrun_reg = SCxSR; |
75c249fd | 2552 | sci_port->overrun_mask = SCIFA_ORER; |
f84b6bdc | 2553 | sci_port->sampling_rate = 16; |
ec09c5eb | 2554 | } else { |
2e0842a1 | 2555 | sci_port->overrun_reg = SCLSR; |
75c249fd | 2556 | sci_port->overrun_mask = SCLSR_ORER; |
f84b6bdc | 2557 | sci_port->sampling_rate = 32; |
ec09c5eb | 2558 | } |
75136d48 MP |
2559 | break; |
2560 | default: | |
73a19e4c | 2561 | port->fifosize = 1; |
2e0842a1 | 2562 | sci_port->overrun_reg = SCxSR; |
75c249fd | 2563 | sci_port->overrun_mask = SCI_ORER; |
f84b6bdc | 2564 | sci_port->sampling_rate = 32; |
75136d48 MP |
2565 | break; |
2566 | } | |
7b6fd3bf | 2567 | |
878fbb91 LP |
2568 | /* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't |
2569 | * match the SoC datasheet, this should be investigated. Let platform | |
2570 | * data override the sampling rate for now. | |
ec09c5eb | 2571 | */ |
f84b6bdc GU |
2572 | if (p->sampling_rate) |
2573 | sci_port->sampling_rate = p->sampling_rate; | |
ec09c5eb | 2574 | |
1fcc91a6 | 2575 | if (!early) { |
a9ec81f4 LP |
2576 | ret = sci_init_clocks(sci_port, &dev->dev); |
2577 | if (ret < 0) | |
2578 | return ret; | |
c7ed1ab3 | 2579 | |
73a19e4c | 2580 | port->dev = &dev->dev; |
5e50d2d6 MD |
2581 | |
2582 | pm_runtime_enable(&dev->dev); | |
7b6fd3bf | 2583 | } |
e108b2ca | 2584 | |
7ed7e071 MD |
2585 | sci_port->break_timer.data = (unsigned long)sci_port; |
2586 | sci_port->break_timer.function = sci_break_timer; | |
2587 | init_timer(&sci_port->break_timer); | |
2588 | ||
debf9507 PM |
2589 | /* |
2590 | * Establish some sensible defaults for the error detection. | |
2591 | */ | |
5da0f468 GU |
2592 | if (p->type == PORT_SCI) { |
2593 | sci_port->error_mask = SCI_DEFAULT_ERROR_MASK; | |
2594 | sci_port->error_clear = SCI_ERROR_CLEAR; | |
2595 | } else { | |
2596 | sci_port->error_mask = SCIF_DEFAULT_ERROR_MASK; | |
2597 | sci_port->error_clear = SCIF_ERROR_CLEAR; | |
2598 | } | |
debf9507 | 2599 | |
3ae988d9 LP |
2600 | /* |
2601 | * Make the error mask inclusive of overrun detection, if | |
2602 | * supported. | |
2603 | */ | |
5da0f468 | 2604 | if (sci_port->overrun_reg == SCxSR) { |
afd66db6 | 2605 | sci_port->error_mask |= sci_port->overrun_mask; |
5da0f468 GU |
2606 | sci_port->error_clear &= ~sci_port->overrun_mask; |
2607 | } | |
debf9507 | 2608 | |
ce6738b6 | 2609 | port->type = p->type; |
b6e4a3f1 | 2610 | port->flags = UPF_FIXED_PORT | p->flags; |
61a6976b | 2611 | port->regshift = p->regshift; |
73a19e4c | 2612 | |
ce6738b6 | 2613 | /* |
61a6976b | 2614 | * The UART port needs an IRQ value, so we peg this to the RX IRQ |
ce6738b6 PM |
2615 | * for the multi-IRQ ports, which is where we are primarily |
2616 | * concerned with the shutdown path synchronization. | |
2617 | * | |
2618 | * For the muxed case there's nothing more to do. | |
2619 | */ | |
1fcc91a6 | 2620 | port->irq = sci_port->irqs[SCIx_RXI_IRQ]; |
9cfb5c05 | 2621 | port->irqflags = 0; |
73a19e4c | 2622 | |
61a6976b PM |
2623 | port->serial_in = sci_serial_in; |
2624 | port->serial_out = sci_serial_out; | |
2625 | ||
937bb6e4 GL |
2626 | if (p->dma_slave_tx > 0 && p->dma_slave_rx > 0) |
2627 | dev_dbg(port->dev, "DMA tx %d, rx %d\n", | |
2628 | p->dma_slave_tx, p->dma_slave_rx); | |
7ed7e071 | 2629 | |
c7ed1ab3 | 2630 | return 0; |
e108b2ca PM |
2631 | } |
2632 | ||
6dae1421 LP |
2633 | static void sci_cleanup_single(struct sci_port *port) |
2634 | { | |
6dae1421 LP |
2635 | pm_runtime_disable(port->port.dev); |
2636 | } | |
2637 | ||
0b0cced1 YS |
2638 | #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \ |
2639 | defined(CONFIG_SERIAL_SH_SCI_EARLYCON) | |
dc8e6f5b MD |
2640 | static void serial_console_putchar(struct uart_port *port, int ch) |
2641 | { | |
2642 | sci_poll_put_char(port, ch); | |
2643 | } | |
2644 | ||
1da177e4 LT |
2645 | /* |
2646 | * Print a string to the serial port trying not to disturb | |
2647 | * any possible real use of the port... | |
2648 | */ | |
2649 | static void serial_console_write(struct console *co, const char *s, | |
2650 | unsigned count) | |
2651 | { | |
906b17dc PM |
2652 | struct sci_port *sci_port = &sci_ports[co->index]; |
2653 | struct uart_port *port = &sci_port->port; | |
a67969b5 | 2654 | unsigned short bits, ctrl, ctrl_temp; |
40f70c03 SK |
2655 | unsigned long flags; |
2656 | int locked = 1; | |
2657 | ||
2658 | local_irq_save(flags); | |
0b0cced1 | 2659 | #if defined(SUPPORT_SYSRQ) |
40f70c03 SK |
2660 | if (port->sysrq) |
2661 | locked = 0; | |
0b0cced1 YS |
2662 | else |
2663 | #endif | |
2664 | if (oops_in_progress) | |
40f70c03 SK |
2665 | locked = spin_trylock(&port->lock); |
2666 | else | |
2667 | spin_lock(&port->lock); | |
2668 | ||
a67969b5 | 2669 | /* first save SCSCR then disable interrupts, keep clock source */ |
40f70c03 | 2670 | ctrl = serial_port_in(port, SCSCR); |
a67969b5 GU |
2671 | ctrl_temp = (sci_port->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)) | |
2672 | (ctrl & (SCSCR_CKE1 | SCSCR_CKE0)); | |
2673 | serial_port_out(port, SCSCR, ctrl_temp); | |
07d2a1a1 | 2674 | |
501b825d | 2675 | uart_console_write(port, s, count, serial_console_putchar); |
973e5d52 MD |
2676 | |
2677 | /* wait until fifo is empty and last bit has been transmitted */ | |
2678 | bits = SCxSR_TDxE(port) | SCxSR_TEND(port); | |
b12bb29f | 2679 | while ((serial_port_in(port, SCxSR) & bits) != bits) |
973e5d52 | 2680 | cpu_relax(); |
40f70c03 SK |
2681 | |
2682 | /* restore the SCSCR */ | |
2683 | serial_port_out(port, SCSCR, ctrl); | |
2684 | ||
2685 | if (locked) | |
2686 | spin_unlock(&port->lock); | |
2687 | local_irq_restore(flags); | |
1da177e4 LT |
2688 | } |
2689 | ||
9671f099 | 2690 | static int serial_console_setup(struct console *co, char *options) |
1da177e4 | 2691 | { |
dc8e6f5b | 2692 | struct sci_port *sci_port; |
1da177e4 LT |
2693 | struct uart_port *port; |
2694 | int baud = 115200; | |
2695 | int bits = 8; | |
2696 | int parity = 'n'; | |
2697 | int flow = 'n'; | |
2698 | int ret; | |
2699 | ||
e108b2ca | 2700 | /* |
906b17dc | 2701 | * Refuse to handle any bogus ports. |
1da177e4 | 2702 | */ |
906b17dc | 2703 | if (co->index < 0 || co->index >= SCI_NPORTS) |
e108b2ca | 2704 | return -ENODEV; |
e108b2ca | 2705 | |
906b17dc PM |
2706 | sci_port = &sci_ports[co->index]; |
2707 | port = &sci_port->port; | |
2708 | ||
b2267a6b AC |
2709 | /* |
2710 | * Refuse to handle uninitialized ports. | |
2711 | */ | |
2712 | if (!port->ops) | |
2713 | return -ENODEV; | |
2714 | ||
f6e9495d PM |
2715 | ret = sci_remap_port(port); |
2716 | if (unlikely(ret != 0)) | |
2717 | return ret; | |
e108b2ca | 2718 | |
1da177e4 LT |
2719 | if (options) |
2720 | uart_parse_options(options, &baud, &parity, &bits, &flow); | |
2721 | ||
ab7cfb55 | 2722 | return uart_set_options(port, co, baud, parity, bits, flow); |
1da177e4 LT |
2723 | } |
2724 | ||
2725 | static struct console serial_console = { | |
2726 | .name = "ttySC", | |
906b17dc | 2727 | .device = uart_console_device, |
1da177e4 LT |
2728 | .write = serial_console_write, |
2729 | .setup = serial_console_setup, | |
fa5da2f7 | 2730 | .flags = CON_PRINTBUFFER, |
1da177e4 | 2731 | .index = -1, |
906b17dc | 2732 | .data = &sci_uart_driver, |
1da177e4 LT |
2733 | }; |
2734 | ||
7b6fd3bf MD |
2735 | static struct console early_serial_console = { |
2736 | .name = "early_ttySC", | |
2737 | .write = serial_console_write, | |
2738 | .flags = CON_PRINTBUFFER, | |
906b17dc | 2739 | .index = -1, |
7b6fd3bf | 2740 | }; |
ecdf8a46 | 2741 | |
7b6fd3bf MD |
2742 | static char early_serial_buf[32]; |
2743 | ||
9671f099 | 2744 | static int sci_probe_earlyprintk(struct platform_device *pdev) |
ecdf8a46 | 2745 | { |
574de559 | 2746 | struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev); |
ecdf8a46 PM |
2747 | |
2748 | if (early_serial_console.data) | |
2749 | return -EEXIST; | |
2750 | ||
2751 | early_serial_console.index = pdev->id; | |
ecdf8a46 | 2752 | |
1fcc91a6 | 2753 | sci_init_single(pdev, &sci_ports[pdev->id], pdev->id, cfg, true); |
ecdf8a46 PM |
2754 | |
2755 | serial_console_setup(&early_serial_console, early_serial_buf); | |
2756 | ||
2757 | if (!strstr(early_serial_buf, "keep")) | |
2758 | early_serial_console.flags |= CON_BOOT; | |
2759 | ||
2760 | register_console(&early_serial_console); | |
2761 | return 0; | |
2762 | } | |
6a8c9799 NI |
2763 | |
2764 | #define SCI_CONSOLE (&serial_console) | |
2765 | ||
ecdf8a46 | 2766 | #else |
9671f099 | 2767 | static inline int sci_probe_earlyprintk(struct platform_device *pdev) |
ecdf8a46 PM |
2768 | { |
2769 | return -EINVAL; | |
2770 | } | |
1da177e4 | 2771 | |
6a8c9799 NI |
2772 | #define SCI_CONSOLE NULL |
2773 | ||
0b0cced1 | 2774 | #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE || CONFIG_SERIAL_SH_SCI_EARLYCON */ |
1da177e4 | 2775 | |
6c13d5d2 | 2776 | static const char banner[] __initconst = "SuperH (H)SCI(F) driver initialized"; |
1da177e4 LT |
2777 | |
2778 | static struct uart_driver sci_uart_driver = { | |
2779 | .owner = THIS_MODULE, | |
2780 | .driver_name = "sci", | |
1da177e4 LT |
2781 | .dev_name = "ttySC", |
2782 | .major = SCI_MAJOR, | |
2783 | .minor = SCI_MINOR_START, | |
e108b2ca | 2784 | .nr = SCI_NPORTS, |
1da177e4 LT |
2785 | .cons = SCI_CONSOLE, |
2786 | }; | |
2787 | ||
54507f6e | 2788 | static int sci_remove(struct platform_device *dev) |
e552de24 | 2789 | { |
d535a230 | 2790 | struct sci_port *port = platform_get_drvdata(dev); |
e552de24 | 2791 | |
d535a230 PM |
2792 | uart_remove_one_port(&sci_uart_driver, &port->port); |
2793 | ||
6dae1421 | 2794 | sci_cleanup_single(port); |
e552de24 | 2795 | |
e552de24 MD |
2796 | return 0; |
2797 | } | |
2798 | ||
bd2238fb GU |
2799 | |
2800 | #define SCI_OF_DATA(type, regtype) (void *)((type) << 16 | (regtype)) | |
2801 | #define SCI_OF_TYPE(data) ((unsigned long)(data) >> 16) | |
2802 | #define SCI_OF_REGTYPE(data) ((unsigned long)(data) & 0xffff) | |
20bdcab8 BH |
2803 | |
2804 | static const struct of_device_id of_sci_match[] = { | |
f443ff80 GU |
2805 | /* SoC-specific types */ |
2806 | { | |
2807 | .compatible = "renesas,scif-r7s72100", | |
2808 | .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH2_SCIF_FIFODATA_REGTYPE), | |
2809 | }, | |
9ed44bb2 GU |
2810 | /* Family-specific types */ |
2811 | { | |
2812 | .compatible = "renesas,rcar-gen1-scif", | |
2813 | .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE), | |
2814 | }, { | |
2815 | .compatible = "renesas,rcar-gen2-scif", | |
2816 | .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE), | |
2817 | }, { | |
2818 | .compatible = "renesas,rcar-gen3-scif", | |
2819 | .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE), | |
2820 | }, | |
f443ff80 | 2821 | /* Generic types */ |
20bdcab8 BH |
2822 | { |
2823 | .compatible = "renesas,scif", | |
bd2238fb | 2824 | .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_REGTYPE), |
20bdcab8 BH |
2825 | }, { |
2826 | .compatible = "renesas,scifa", | |
bd2238fb | 2827 | .data = SCI_OF_DATA(PORT_SCIFA, SCIx_SCIFA_REGTYPE), |
20bdcab8 BH |
2828 | }, { |
2829 | .compatible = "renesas,scifb", | |
bd2238fb | 2830 | .data = SCI_OF_DATA(PORT_SCIFB, SCIx_SCIFB_REGTYPE), |
20bdcab8 BH |
2831 | }, { |
2832 | .compatible = "renesas,hscif", | |
bd2238fb | 2833 | .data = SCI_OF_DATA(PORT_HSCIF, SCIx_HSCIF_REGTYPE), |
e1d0be61 YS |
2834 | }, { |
2835 | .compatible = "renesas,sci", | |
bd2238fb | 2836 | .data = SCI_OF_DATA(PORT_SCI, SCIx_SCI_REGTYPE), |
20bdcab8 BH |
2837 | }, { |
2838 | /* Terminator */ | |
2839 | }, | |
2840 | }; | |
2841 | MODULE_DEVICE_TABLE(of, of_sci_match); | |
2842 | ||
2843 | static struct plat_sci_port * | |
2844 | sci_parse_dt(struct platform_device *pdev, unsigned int *dev_id) | |
2845 | { | |
2846 | struct device_node *np = pdev->dev.of_node; | |
2847 | const struct of_device_id *match; | |
20bdcab8 BH |
2848 | struct plat_sci_port *p; |
2849 | int id; | |
2850 | ||
2851 | if (!IS_ENABLED(CONFIG_OF) || !np) | |
2852 | return NULL; | |
2853 | ||
495bb47c | 2854 | match = of_match_node(of_sci_match, np); |
20bdcab8 BH |
2855 | if (!match) |
2856 | return NULL; | |
2857 | ||
20bdcab8 | 2858 | p = devm_kzalloc(&pdev->dev, sizeof(struct plat_sci_port), GFP_KERNEL); |
4205463c | 2859 | if (!p) |
20bdcab8 | 2860 | return NULL; |
20bdcab8 | 2861 | |
2095fc76 | 2862 | /* Get the line number from the aliases node. */ |
20bdcab8 BH |
2863 | id = of_alias_get_id(np, "serial"); |
2864 | if (id < 0) { | |
2865 | dev_err(&pdev->dev, "failed to get alias id (%d)\n", id); | |
2866 | return NULL; | |
2867 | } | |
2868 | ||
2869 | *dev_id = id; | |
2870 | ||
2871 | p->flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF; | |
bd2238fb GU |
2872 | p->type = SCI_OF_TYPE(match->data); |
2873 | p->regtype = SCI_OF_REGTYPE(match->data); | |
20bdcab8 BH |
2874 | p->scscr = SCSCR_RE | SCSCR_TE; |
2875 | ||
2876 | return p; | |
2877 | } | |
2878 | ||
9671f099 | 2879 | static int sci_probe_single(struct platform_device *dev, |
0ee70712 MD |
2880 | unsigned int index, |
2881 | struct plat_sci_port *p, | |
2882 | struct sci_port *sciport) | |
2883 | { | |
0ee70712 MD |
2884 | int ret; |
2885 | ||
2886 | /* Sanity check */ | |
2887 | if (unlikely(index >= SCI_NPORTS)) { | |
9b971cd2 | 2888 | dev_notice(&dev->dev, "Attempting to register port %d when only %d are available\n", |
0ee70712 | 2889 | index+1, SCI_NPORTS); |
9b971cd2 | 2890 | dev_notice(&dev->dev, "Consider bumping CONFIG_SERIAL_SH_SCI_NR_UARTS!\n"); |
b6c5ef6f | 2891 | return -EINVAL; |
0ee70712 MD |
2892 | } |
2893 | ||
1fcc91a6 | 2894 | ret = sci_init_single(dev, sciport, index, p, false); |
c7ed1ab3 PM |
2895 | if (ret) |
2896 | return ret; | |
0ee70712 | 2897 | |
6dae1421 LP |
2898 | ret = uart_add_one_port(&sci_uart_driver, &sciport->port); |
2899 | if (ret) { | |
2900 | sci_cleanup_single(sciport); | |
2901 | return ret; | |
2902 | } | |
2903 | ||
2904 | return 0; | |
0ee70712 MD |
2905 | } |
2906 | ||
9671f099 | 2907 | static int sci_probe(struct platform_device *dev) |
1da177e4 | 2908 | { |
20bdcab8 BH |
2909 | struct plat_sci_port *p; |
2910 | struct sci_port *sp; | |
2911 | unsigned int dev_id; | |
ecdf8a46 | 2912 | int ret; |
d535a230 | 2913 | |
ecdf8a46 PM |
2914 | /* |
2915 | * If we've come here via earlyprintk initialization, head off to | |
2916 | * the special early probe. We don't have sufficient device state | |
2917 | * to make it beyond this yet. | |
2918 | */ | |
2919 | if (is_early_platform_device(dev)) | |
2920 | return sci_probe_earlyprintk(dev); | |
7b6fd3bf | 2921 | |
20bdcab8 BH |
2922 | if (dev->dev.of_node) { |
2923 | p = sci_parse_dt(dev, &dev_id); | |
2924 | if (p == NULL) | |
2925 | return -EINVAL; | |
2926 | } else { | |
2927 | p = dev->dev.platform_data; | |
2928 | if (p == NULL) { | |
2929 | dev_err(&dev->dev, "no platform data supplied\n"); | |
2930 | return -EINVAL; | |
2931 | } | |
2932 | ||
2933 | dev_id = dev->id; | |
2934 | } | |
2935 | ||
2936 | sp = &sci_ports[dev_id]; | |
d535a230 | 2937 | platform_set_drvdata(dev, sp); |
e552de24 | 2938 | |
20bdcab8 | 2939 | ret = sci_probe_single(dev, dev_id, p, sp); |
d535a230 | 2940 | if (ret) |
6dae1421 | 2941 | return ret; |
e552de24 | 2942 | |
1da177e4 LT |
2943 | #ifdef CONFIG_SH_STANDARD_BIOS |
2944 | sh_bios_gdb_detach(); | |
2945 | #endif | |
2946 | ||
e108b2ca | 2947 | return 0; |
1da177e4 LT |
2948 | } |
2949 | ||
cb876341 | 2950 | static __maybe_unused int sci_suspend(struct device *dev) |
1da177e4 | 2951 | { |
d535a230 | 2952 | struct sci_port *sport = dev_get_drvdata(dev); |
e108b2ca | 2953 | |
d535a230 PM |
2954 | if (sport) |
2955 | uart_suspend_port(&sci_uart_driver, &sport->port); | |
1da177e4 | 2956 | |
e108b2ca PM |
2957 | return 0; |
2958 | } | |
1da177e4 | 2959 | |
cb876341 | 2960 | static __maybe_unused int sci_resume(struct device *dev) |
e108b2ca | 2961 | { |
d535a230 | 2962 | struct sci_port *sport = dev_get_drvdata(dev); |
e108b2ca | 2963 | |
d535a230 PM |
2964 | if (sport) |
2965 | uart_resume_port(&sci_uart_driver, &sport->port); | |
e108b2ca PM |
2966 | |
2967 | return 0; | |
2968 | } | |
2969 | ||
cb876341 | 2970 | static SIMPLE_DEV_PM_OPS(sci_dev_pm_ops, sci_suspend, sci_resume); |
6daa79b3 | 2971 | |
e108b2ca PM |
2972 | static struct platform_driver sci_driver = { |
2973 | .probe = sci_probe, | |
b9e39c89 | 2974 | .remove = sci_remove, |
e108b2ca PM |
2975 | .driver = { |
2976 | .name = "sh-sci", | |
6daa79b3 | 2977 | .pm = &sci_dev_pm_ops, |
20bdcab8 | 2978 | .of_match_table = of_match_ptr(of_sci_match), |
e108b2ca PM |
2979 | }, |
2980 | }; | |
2981 | ||
2982 | static int __init sci_init(void) | |
2983 | { | |
2984 | int ret; | |
2985 | ||
6c13d5d2 | 2986 | pr_info("%s\n", banner); |
e108b2ca | 2987 | |
e108b2ca PM |
2988 | ret = uart_register_driver(&sci_uart_driver); |
2989 | if (likely(ret == 0)) { | |
2990 | ret = platform_driver_register(&sci_driver); | |
2991 | if (unlikely(ret)) | |
2992 | uart_unregister_driver(&sci_uart_driver); | |
2993 | } | |
2994 | ||
2995 | return ret; | |
2996 | } | |
2997 | ||
2998 | static void __exit sci_exit(void) | |
2999 | { | |
3000 | platform_driver_unregister(&sci_driver); | |
1da177e4 LT |
3001 | uart_unregister_driver(&sci_uart_driver); |
3002 | } | |
3003 | ||
7b6fd3bf MD |
3004 | #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE |
3005 | early_platform_init_buffer("earlyprintk", &sci_driver, | |
3006 | early_serial_buf, ARRAY_SIZE(early_serial_buf)); | |
3007 | #endif | |
0b0cced1 YS |
3008 | #ifdef CONFIG_SERIAL_SH_SCI_EARLYCON |
3009 | static struct __init plat_sci_port port_cfg; | |
3010 | ||
3011 | static int __init early_console_setup(struct earlycon_device *device, | |
3012 | int type) | |
3013 | { | |
3014 | if (!device->port.membase) | |
3015 | return -ENODEV; | |
3016 | ||
3017 | device->port.serial_in = sci_serial_in; | |
3018 | device->port.serial_out = sci_serial_out; | |
3019 | device->port.type = type; | |
3020 | memcpy(&sci_ports[0].port, &device->port, sizeof(struct uart_port)); | |
3021 | sci_ports[0].cfg = &port_cfg; | |
3022 | sci_ports[0].cfg->type = type; | |
3023 | sci_probe_regmap(sci_ports[0].cfg); | |
3024 | port_cfg.scscr = sci_serial_in(&sci_ports[0].port, SCSCR) | | |
3025 | SCSCR_RE | SCSCR_TE; | |
3026 | sci_serial_out(&sci_ports[0].port, SCSCR, port_cfg.scscr); | |
3027 | ||
3028 | device->con->write = serial_console_write; | |
3029 | return 0; | |
3030 | } | |
3031 | static int __init sci_early_console_setup(struct earlycon_device *device, | |
3032 | const char *opt) | |
3033 | { | |
3034 | return early_console_setup(device, PORT_SCI); | |
3035 | } | |
3036 | static int __init scif_early_console_setup(struct earlycon_device *device, | |
3037 | const char *opt) | |
3038 | { | |
3039 | return early_console_setup(device, PORT_SCIF); | |
3040 | } | |
3041 | static int __init scifa_early_console_setup(struct earlycon_device *device, | |
3042 | const char *opt) | |
3043 | { | |
3044 | return early_console_setup(device, PORT_SCIFA); | |
3045 | } | |
3046 | static int __init scifb_early_console_setup(struct earlycon_device *device, | |
3047 | const char *opt) | |
3048 | { | |
3049 | return early_console_setup(device, PORT_SCIFB); | |
3050 | } | |
3051 | static int __init hscif_early_console_setup(struct earlycon_device *device, | |
3052 | const char *opt) | |
3053 | { | |
3054 | return early_console_setup(device, PORT_HSCIF); | |
3055 | } | |
3056 | ||
3057 | EARLYCON_DECLARE(sci, sci_early_console_setup); | |
3058 | OF_EARLYCON_DECLARE(sci, "renesas,sci", sci_early_console_setup); | |
3059 | EARLYCON_DECLARE(scif, scif_early_console_setup); | |
3060 | OF_EARLYCON_DECLARE(scif, "renesas,scif", scif_early_console_setup); | |
3061 | EARLYCON_DECLARE(scifa, scifa_early_console_setup); | |
3062 | OF_EARLYCON_DECLARE(scifa, "renesas,scifa", scifa_early_console_setup); | |
3063 | EARLYCON_DECLARE(scifb, scifb_early_console_setup); | |
3064 | OF_EARLYCON_DECLARE(scifb, "renesas,scifb", scifb_early_console_setup); | |
3065 | EARLYCON_DECLARE(hscif, hscif_early_console_setup); | |
3066 | OF_EARLYCON_DECLARE(hscif, "renesas,hscif", hscif_early_console_setup); | |
3067 | #endif /* CONFIG_SERIAL_SH_SCI_EARLYCON */ | |
3068 | ||
1da177e4 LT |
3069 | module_init(sci_init); |
3070 | module_exit(sci_exit); | |
3071 | ||
e108b2ca | 3072 | MODULE_LICENSE("GPL"); |
e169c139 | 3073 | MODULE_ALIAS("platform:sh-sci"); |
7f405f9c | 3074 | MODULE_AUTHOR("Paul Mundt"); |
f303b364 | 3075 | MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver"); |