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Merge tag 'rtc-4.18' of git://git.kernel.org/pub/scm/linux/kernel/git/abelloni/linux
[linux-2.6-block.git] / drivers / tty / serial / sc16is7xx.c
CommitLineData
e3b3d0f5 1// SPDX-License-Identifier: GPL-2.0+
dfeae619
JR		 2/*
3 * SC16IS7xx tty serial driver - Copyright (C) 2014 GridPoint
4 * Author: Jon Ringle <jringle@gridpoint.com>
5 *
6 * Based on max310x.c, by Alexander Shiyan <shc_work@mail.ru>
dfeae619
JR		 7 */
8
c6434972
JK		 9#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
10
dfeae619
JR		 11#include <linux/bitops.h>
12#include <linux/clk.h>
13#include <linux/delay.h>
14#include <linux/device.h>
dee07cea 15#include <linux/gpio/driver.h>
dfeae619
JR		 16#include <linux/i2c.h>
17#include <linux/module.h>
18#include <linux/of.h>
19#include <linux/of_device.h>
20#include <linux/regmap.h>
21#include <linux/serial_core.h>
22#include <linux/serial.h>
23#include <linux/tty.h>
24#include <linux/tty_flip.h>
2c837a8a 25#include <linux/spi/spi.h>
d952795d 26#include <linux/uaccess.h>
ae7e81c0 27#include <uapi/linux/sched/types.h>
dfeae619
JR		 28
29#define SC16IS7XX_NAME "sc16is7xx"
c6434972 30#define SC16IS7XX_MAX_DEVS 8
dfeae619
JR		 31
32/* SC16IS7XX register definitions */
33#define SC16IS7XX_RHR_REG (0x00) /* RX FIFO */
34#define SC16IS7XX_THR_REG (0x00) /* TX FIFO */
35#define SC16IS7XX_IER_REG (0x01) /* Interrupt enable */
36#define SC16IS7XX_IIR_REG (0x02) /* Interrupt Identification */
37#define SC16IS7XX_FCR_REG (0x02) /* FIFO control */
38#define SC16IS7XX_LCR_REG (0x03) /* Line Control */
39#define SC16IS7XX_MCR_REG (0x04) /* Modem Control */
40#define SC16IS7XX_LSR_REG (0x05) /* Line Status */
41#define SC16IS7XX_MSR_REG (0x06) /* Modem Status */
42#define SC16IS7XX_SPR_REG (0x07) /* Scratch Pad */
43#define SC16IS7XX_TXLVL_REG (0x08) /* TX FIFO level */
44#define SC16IS7XX_RXLVL_REG (0x09) /* RX FIFO level */
45#define SC16IS7XX_IODIR_REG (0x0a) /* I/O Direction
46 * - only on 75x/76x
47 */
48#define SC16IS7XX_IOSTATE_REG (0x0b) /* I/O State
49 * - only on 75x/76x
50 */
51#define SC16IS7XX_IOINTENA_REG (0x0c) /* I/O Interrupt Enable
52 * - only on 75x/76x
53 */
54#define SC16IS7XX_IOCONTROL_REG (0x0e) /* I/O Control
55 * - only on 75x/76x
56 */
57#define SC16IS7XX_EFCR_REG (0x0f) /* Extra Features Control */
58
59/* TCR/TLR Register set: Only if ((MCR[2] == 1) && (EFR[4] == 1)) */
60#define SC16IS7XX_TCR_REG (0x06) /* Transmit control */
61#define SC16IS7XX_TLR_REG (0x07) /* Trigger level */
62
63/* Special Register set: Only if ((LCR[7] == 1) && (LCR != 0xBF)) */
64#define SC16IS7XX_DLL_REG (0x00) /* Divisor Latch Low */
65#define SC16IS7XX_DLH_REG (0x01) /* Divisor Latch High */
66
67/* Enhanced Register set: Only if (LCR == 0xBF) */
68#define SC16IS7XX_EFR_REG (0x02) /* Enhanced Features */
69#define SC16IS7XX_XON1_REG (0x04) /* Xon1 word */
70#define SC16IS7XX_XON2_REG (0x05) /* Xon2 word */
71#define SC16IS7XX_XOFF1_REG (0x06) /* Xoff1 word */
72#define SC16IS7XX_XOFF2_REG (0x07) /* Xoff2 word */
73
74/* IER register bits */
75#define SC16IS7XX_IER_RDI_BIT (1 << 0) /* Enable RX data interrupt */
76#define SC16IS7XX_IER_THRI_BIT (1 << 1) /* Enable TX holding register
77 * interrupt */
78#define SC16IS7XX_IER_RLSI_BIT (1 << 2) /* Enable RX line status
79 * interrupt */
80#define SC16IS7XX_IER_MSI_BIT (1 << 3) /* Enable Modem status
81 * interrupt */
82
83/* IER register bits - write only if (EFR[4] == 1) */
84#define SC16IS7XX_IER_SLEEP_BIT (1 << 4) /* Enable Sleep mode */
85#define SC16IS7XX_IER_XOFFI_BIT (1 << 5) /* Enable Xoff interrupt */
86#define SC16IS7XX_IER_RTSI_BIT (1 << 6) /* Enable nRTS interrupt */
87#define SC16IS7XX_IER_CTSI_BIT (1 << 7) /* Enable nCTS interrupt */
88
89/* FCR register bits */
90#define SC16IS7XX_FCR_FIFO_BIT (1 << 0) /* Enable FIFO */
91#define SC16IS7XX_FCR_RXRESET_BIT (1 << 1) /* Reset RX FIFO */
92#define SC16IS7XX_FCR_TXRESET_BIT (1 << 2) /* Reset TX FIFO */
93#define SC16IS7XX_FCR_RXLVLL_BIT (1 << 6) /* RX Trigger level LSB */
94#define SC16IS7XX_FCR_RXLVLH_BIT (1 << 7) /* RX Trigger level MSB */
95
96/* FCR register bits - write only if (EFR[4] == 1) */
97#define SC16IS7XX_FCR_TXLVLL_BIT (1 << 4) /* TX Trigger level LSB */
98#define SC16IS7XX_FCR_TXLVLH_BIT (1 << 5) /* TX Trigger level MSB */
99
100/* IIR register bits */
101#define SC16IS7XX_IIR_NO_INT_BIT (1 << 0) /* No interrupts pending */
102#define SC16IS7XX_IIR_ID_MASK 0x3e /* Mask for the interrupt ID */
103#define SC16IS7XX_IIR_THRI_SRC 0x02 /* TX holding register empty */
104#define SC16IS7XX_IIR_RDI_SRC 0x04 /* RX data interrupt */
105#define SC16IS7XX_IIR_RLSE_SRC 0x06 /* RX line status error */
106#define SC16IS7XX_IIR_RTOI_SRC 0x0c /* RX time-out interrupt */
107#define SC16IS7XX_IIR_MSI_SRC 0x00 /* Modem status interrupt
108 * - only on 75x/76x
109 */
110#define SC16IS7XX_IIR_INPIN_SRC 0x30 /* Input pin change of state
111 * - only on 75x/76x
112 */
113#define SC16IS7XX_IIR_XOFFI_SRC 0x10 /* Received Xoff */
114#define SC16IS7XX_IIR_CTSRTS_SRC 0x20 /* nCTS,nRTS change of state
115 * from active (LOW)
116 * to inactive (HIGH)
117 */
118/* LCR register bits */
119#define SC16IS7XX_LCR_LENGTH0_BIT (1 << 0) /* Word length bit 0 */
120#define SC16IS7XX_LCR_LENGTH1_BIT (1 << 1) /* Word length bit 1
121 *
122 * Word length bits table:
123 * 00 -> 5 bit words
124 * 01 -> 6 bit words
125 * 10 -> 7 bit words
126 * 11 -> 8 bit words
127 */
128#define SC16IS7XX_LCR_STOPLEN_BIT (1 << 2) /* STOP length bit
129 *
130 * STOP length bit table:
131 * 0 -> 1 stop bit
132 * 1 -> 1-1.5 stop bits if
133 * word length is 5,
134 * 2 stop bits otherwise
135 */
136#define SC16IS7XX_LCR_PARITY_BIT (1 << 3) /* Parity bit enable */
137#define SC16IS7XX_LCR_EVENPARITY_BIT (1 << 4) /* Even parity bit enable */
138#define SC16IS7XX_LCR_FORCEPARITY_BIT (1 << 5) /* 9-bit multidrop parity */
139#define SC16IS7XX_LCR_TXBREAK_BIT (1 << 6) /* TX break enable */
140#define SC16IS7XX_LCR_DLAB_BIT (1 << 7) /* Divisor Latch enable */
141#define SC16IS7XX_LCR_WORD_LEN_5 (0x00)
142#define SC16IS7XX_LCR_WORD_LEN_6 (0x01)
143#define SC16IS7XX_LCR_WORD_LEN_7 (0x02)
144#define SC16IS7XX_LCR_WORD_LEN_8 (0x03)
145#define SC16IS7XX_LCR_CONF_MODE_A SC16IS7XX_LCR_DLAB_BIT /* Special
146 * reg set */
147#define SC16IS7XX_LCR_CONF_MODE_B 0xBF /* Enhanced
148 * reg set */
149
150/* MCR register bits */
151#define SC16IS7XX_MCR_DTR_BIT (1 << 0) /* DTR complement
152 * - only on 75x/76x
153 */
154#define SC16IS7XX_MCR_RTS_BIT (1 << 1) /* RTS complement */
155#define SC16IS7XX_MCR_TCRTLR_BIT (1 << 2) /* TCR/TLR register enable */
156#define SC16IS7XX_MCR_LOOP_BIT (1 << 4) /* Enable loopback test mode */
157#define SC16IS7XX_MCR_XONANY_BIT (1 << 5) /* Enable Xon Any
158 * - write enabled
159 * if (EFR[4] == 1)
160 */
161#define SC16IS7XX_MCR_IRDA_BIT (1 << 6) /* Enable IrDA mode
162 * - write enabled
163 * if (EFR[4] == 1)
164 */
165#define SC16IS7XX_MCR_CLKSEL_BIT (1 << 7) /* Divide clock by 4
166 * - write enabled
167 * if (EFR[4] == 1)
168 */
169
170/* LSR register bits */
171#define SC16IS7XX_LSR_DR_BIT (1 << 0) /* Receiver data ready */
172#define SC16IS7XX_LSR_OE_BIT (1 << 1) /* Overrun Error */
173#define SC16IS7XX_LSR_PE_BIT (1 << 2) /* Parity Error */
174#define SC16IS7XX_LSR_FE_BIT (1 << 3) /* Frame Error */
175#define SC16IS7XX_LSR_BI_BIT (1 << 4) /* Break Interrupt */
176#define SC16IS7XX_LSR_BRK_ERROR_MASK 0x1E /* BI, FE, PE, OE bits */
177#define SC16IS7XX_LSR_THRE_BIT (1 << 5) /* TX holding register empty */
178#define SC16IS7XX_LSR_TEMT_BIT (1 << 6) /* Transmitter empty */
179#define SC16IS7XX_LSR_FIFOE_BIT (1 << 7) /* Fifo Error */
180
181/* MSR register bits */
182#define SC16IS7XX_MSR_DCTS_BIT (1 << 0) /* Delta CTS Clear To Send */
183#define SC16IS7XX_MSR_DDSR_BIT (1 << 1) /* Delta DSR Data Set Ready
184 * or (IO4)
185 * - only on 75x/76x
186 */
187#define SC16IS7XX_MSR_DRI_BIT (1 << 2) /* Delta RI Ring Indicator
188 * or (IO7)
189 * - only on 75x/76x
190 */
191#define SC16IS7XX_MSR_DCD_BIT (1 << 3) /* Delta CD Carrier Detect
192 * or (IO6)
193 * - only on 75x/76x
194 */
b7ed5161
WW		 195#define SC16IS7XX_MSR_CTS_BIT (1 << 4) /* CTS */
196#define SC16IS7XX_MSR_DSR_BIT (1 << 5) /* DSR (IO4)
dfeae619
JR		 197 * - only on 75x/76x
198 */
b7ed5161 199#define SC16IS7XX_MSR_RI_BIT (1 << 6) /* RI (IO7)
dfeae619
JR		 200 * - only on 75x/76x
201 */
b7ed5161 202#define SC16IS7XX_MSR_CD_BIT (1 << 7) /* CD (IO6)
dfeae619
JR		 203 * - only on 75x/76x
204 */
205#define SC16IS7XX_MSR_DELTA_MASK 0x0F /* Any of the delta bits! */
206
207/*
208 * TCR register bits
209 * TCR trigger levels are available from 0 to 60 characters with a granularity
210 * of four.
211 * The programmer must program the TCR such that TCR[3:0] > TCR[7:4]. There is
212 * no built-in hardware check to make sure this condition is met. Also, the TCR
213 * must be programmed with this condition before auto RTS or software flow
214 * control is enabled to avoid spurious operation of the device.
215 */
216#define SC16IS7XX_TCR_RX_HALT(words) ((((words) / 4) & 0x0f) << 0)
217#define SC16IS7XX_TCR_RX_RESUME(words) ((((words) / 4) & 0x0f) << 4)
218
219/*
220 * TLR register bits
221 * If TLR[3:0] or TLR[7:4] are logical 0, the selectable trigger levels via the
222 * FIFO Control Register (FCR) are used for the transmit and receive FIFO
223 * trigger levels. Trigger levels from 4 characters to 60 characters are
224 * available with a granularity of four.
225 *
226 * When the trigger level setting in TLR is zero, the SC16IS740/750/760 uses the
227 * trigger level setting defined in FCR. If TLR has non-zero trigger level value
228 * the trigger level defined in FCR is discarded. This applies to both transmit
229 * FIFO and receive FIFO trigger level setting.
230 *
231 * When TLR is used for RX trigger level control, FCR[7:6] should be left at the
232 * default state, that is, '00'.
233 */
234#define SC16IS7XX_TLR_TX_TRIGGER(words) ((((words) / 4) & 0x0f) << 0)
235#define SC16IS7XX_TLR_RX_TRIGGER(words) ((((words) / 4) & 0x0f) << 4)
236
237/* IOControl register bits (Only 750/760) */
238#define SC16IS7XX_IOCONTROL_LATCH_BIT (1 << 0) /* Enable input latching */
b7ed5161 239#define SC16IS7XX_IOCONTROL_MODEM_BIT (1 << 1) /* Enable GPIO[7:4] as modem pins */
dfeae619
JR		 240#define SC16IS7XX_IOCONTROL_SRESET_BIT (1 << 3) /* Software Reset */
241
242/* EFCR register bits */
243#define SC16IS7XX_EFCR_9BIT_MODE_BIT (1 << 0) /* Enable 9-bit or Multidrop
244 * mode (RS485) */
245#define SC16IS7XX_EFCR_RXDISABLE_BIT (1 << 1) /* Disable receiver */
246#define SC16IS7XX_EFCR_TXDISABLE_BIT (1 << 2) /* Disable transmitter */
247#define SC16IS7XX_EFCR_AUTO_RS485_BIT (1 << 4) /* Auto RS485 RTS direction */
248#define SC16IS7XX_EFCR_RTS_INVERT_BIT (1 << 5) /* RTS output inversion */
249#define SC16IS7XX_EFCR_IRDA_MODE_BIT (1 << 7) /* IrDA mode
250 * 0 = rate upto 115.2 kbit/s
251 * - Only 750/760
252 * 1 = rate upto 1.152 Mbit/s
253 * - Only 760
254 */
255
256/* EFR register bits */
257#define SC16IS7XX_EFR_AUTORTS_BIT (1 << 6) /* Auto RTS flow ctrl enable */
258#define SC16IS7XX_EFR_AUTOCTS_BIT (1 << 7) /* Auto CTS flow ctrl enable */
259#define SC16IS7XX_EFR_XOFF2_DETECT_BIT (1 << 5) /* Enable Xoff2 detection */
260#define SC16IS7XX_EFR_ENABLE_BIT (1 << 4) /* Enable enhanced functions
261 * and writing to IER[7:4],
262 * FCR[5:4], MCR[7:5]
263 */
264#define SC16IS7XX_EFR_SWFLOW3_BIT (1 << 3) /* SWFLOW bit 3 */
265#define SC16IS7XX_EFR_SWFLOW2_BIT (1 << 2) /* SWFLOW bit 2
266 *
267 * SWFLOW bits 3 & 2 table:
268 * 00 -> no transmitter flow
269 * control
270 * 01 -> transmitter generates
271 * XON2 and XOFF2
272 * 10 -> transmitter generates
273 * XON1 and XOFF1
274 * 11 -> transmitter generates
275 * XON1, XON2, XOFF1 and
276 * XOFF2
277 */
278#define SC16IS7XX_EFR_SWFLOW1_BIT (1 << 1) /* SWFLOW bit 2 */
279#define SC16IS7XX_EFR_SWFLOW0_BIT (1 << 0) /* SWFLOW bit 3
280 *
281 * SWFLOW bits 3 & 2 table:
282 * 00 -> no received flow
283 * control
284 * 01 -> receiver compares
285 * XON2 and XOFF2
286 * 10 -> receiver compares
287 * XON1 and XOFF1
288 * 11 -> receiver compares
289 * XON1, XON2, XOFF1 and
290 * XOFF2
291 */
292
293/* Misc definitions */
294#define SC16IS7XX_FIFO_SIZE (64)
295#define SC16IS7XX_REG_SHIFT 2
296
297struct sc16is7xx_devtype {
298 char name[10];
299 int nr_gpio;
300 int nr_uart;
301};
302
a0104085 303#define SC16IS7XX_RECONF_MD (1 << 0)
059d5815 304#define SC16IS7XX_RECONF_IER (1 << 1)
478d1051 305#define SC16IS7XX_RECONF_RS485 (1 << 2)
a0104085
JK		 306
307struct sc16is7xx_one_config {
308 unsigned int flags;
059d5815 309 u8 ier_clear;
a0104085
JK		 310};
311
dfeae619
JR		 312struct sc16is7xx_one {
313 struct uart_port port;
e92a886b 314 u8 line;
9e6f4ca3 315 struct kthread_work tx_work;
a0104085
JK		 316 struct kthread_work reg_work;
317 struct sc16is7xx_one_config config;
dfeae619
JR		 318};
319
320struct sc16is7xx_port {
68be64ca 321 const struct sc16is7xx_devtype *devtype;
dfeae619 322 struct regmap *regmap;
dfeae619
JR		 323 struct clk *clk;
324#ifdef CONFIG_GPIOLIB
325 struct gpio_chip gpio;
326#endif
beb04a9f 327 unsigned char buf[SC16IS7XX_FIFO_SIZE];
9e6f4ca3
JK		 328 struct kthread_worker kworker;
329 struct task_struct *kworker_task;
330 struct kthread_work irq_work;
dfeae619
JR		 331 struct sc16is7xx_one p[0];
332};
333
c6434972
JK		 334static unsigned long sc16is7xx_lines;
335
336static struct uart_driver sc16is7xx_uart = {
337 .owner = THIS_MODULE,
338 .dev_name = "ttySC",
339 .nr = SC16IS7XX_MAX_DEVS,
340};
341
9e6f4ca3 342#define to_sc16is7xx_port(p,e) ((container_of((p), struct sc16is7xx_port, e)))
dfeae619
JR		 343#define to_sc16is7xx_one(p,e) ((container_of((p), struct sc16is7xx_one, e)))
344
e92a886b
JK		 345static int sc16is7xx_line(struct uart_port *port)
346{
347 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
348
349 return one->line;
350}
351
dfeae619
JR		 352static u8 sc16is7xx_port_read(struct uart_port *port, u8 reg)
353{
354 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
355 unsigned int val = 0;
e92a886b 356 const u8 line = sc16is7xx_line(port);
dfeae619 357
e92a886b 358 regmap_read(s->regmap, (reg << SC16IS7XX_REG_SHIFT) | line, &val);
dfeae619
JR		 359
360 return val;
361}
362
363static void sc16is7xx_port_write(struct uart_port *port, u8 reg, u8 val)
364{
365 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
e92a886b 366 const u8 line = sc16is7xx_line(port);
dfeae619 367
e92a886b 368 regmap_write(s->regmap, (reg << SC16IS7XX_REG_SHIFT) | line, val);
dfeae619
JR		 369}
370
dec273ec
BS		 371static void sc16is7xx_fifo_read(struct uart_port *port, unsigned int rxlen)
372{
373 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
e92a886b
JK		 374 const u8 line = sc16is7xx_line(port);
375 u8 addr = (SC16IS7XX_RHR_REG << SC16IS7XX_REG_SHIFT) | line;
dec273ec
BS		 376
377 regcache_cache_bypass(s->regmap, true);
378 regmap_raw_read(s->regmap, addr, s->buf, rxlen);
379 regcache_cache_bypass(s->regmap, false);
380}
381
382static void sc16is7xx_fifo_write(struct uart_port *port, u8 to_send)
383{
384 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
e92a886b
JK		 385 const u8 line = sc16is7xx_line(port);
386 u8 addr = (SC16IS7XX_THR_REG << SC16IS7XX_REG_SHIFT) | line;
dec273ec 387
ed7a8504
FA		 388 /*
389 * Don't send zero-length data, at least on SPI it confuses the chip
390 * delivering wrong TXLVL data.
391 */
392 if (unlikely(!to_send))
393 return;
394
dec273ec
BS		 395 regcache_cache_bypass(s->regmap, true);
396 regmap_raw_write(s->regmap, addr, s->buf, to_send);
397 regcache_cache_bypass(s->regmap, false);
398}
399
dfeae619
JR		 400static void sc16is7xx_port_update(struct uart_port *port, u8 reg,
401 u8 mask, u8 val)
402{
403 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
e92a886b 404 const u8 line = sc16is7xx_line(port);
dfeae619 405
e92a886b 406 regmap_update_bits(s->regmap, (reg << SC16IS7XX_REG_SHIFT) | line,
dfeae619
JR		 407 mask, val);
408}
409
c6434972
JK		 410static int sc16is7xx_alloc_line(void)
411{
412 int i;
413
414 BUILD_BUG_ON(SC16IS7XX_MAX_DEVS > BITS_PER_LONG);
415
416 for (i = 0; i < SC16IS7XX_MAX_DEVS; i++)
417 if (!test_and_set_bit(i, &sc16is7xx_lines))
418 break;
419
420 return i;
421}
dfeae619
JR		 422
423static void sc16is7xx_power(struct uart_port *port, int on)
424{
425 sc16is7xx_port_update(port, SC16IS7XX_IER_REG,
426 SC16IS7XX_IER_SLEEP_BIT,
427 on ? 0 : SC16IS7XX_IER_SLEEP_BIT);
428}
429
430static const struct sc16is7xx_devtype sc16is74x_devtype = {
431 .name = "SC16IS74X",
432 .nr_gpio = 0,
433 .nr_uart = 1,
434};
435
436static const struct sc16is7xx_devtype sc16is750_devtype = {
437 .name = "SC16IS750",
438 .nr_gpio = 8,
439 .nr_uart = 1,
440};
441
442static const struct sc16is7xx_devtype sc16is752_devtype = {
443 .name = "SC16IS752",
444 .nr_gpio = 8,
445 .nr_uart = 2,
446};
447
448static const struct sc16is7xx_devtype sc16is760_devtype = {
449 .name = "SC16IS760",
450 .nr_gpio = 8,
451 .nr_uart = 1,
452};
453
454static const struct sc16is7xx_devtype sc16is762_devtype = {
455 .name = "SC16IS762",
456 .nr_gpio = 8,
457 .nr_uart = 2,
458};
459
460static bool sc16is7xx_regmap_volatile(struct device *dev, unsigned int reg)
461{
462 switch (reg >> SC16IS7XX_REG_SHIFT) {
463 case SC16IS7XX_RHR_REG:
464 case SC16IS7XX_IIR_REG:
465 case SC16IS7XX_LSR_REG:
466 case SC16IS7XX_MSR_REG:
467 case SC16IS7XX_TXLVL_REG:
468 case SC16IS7XX_RXLVL_REG:
469 case SC16IS7XX_IOSTATE_REG:
470 return true;
471 default:
472 break;
473 }
474
475 return false;
476}
477
478static bool sc16is7xx_regmap_precious(struct device *dev, unsigned int reg)
479{
480 switch (reg >> SC16IS7XX_REG_SHIFT) {
481 case SC16IS7XX_RHR_REG:
482 return true;
483 default:
484 break;
485 }
486
487 return false;
488}
489
490static int sc16is7xx_set_baud(struct uart_port *port, int baud)
491{
492 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
493 u8 lcr;
494 u8 prescaler = 0;
495 unsigned long clk = port->uartclk, div = clk / 16 / baud;
496
497 if (div > 0xffff) {
498 prescaler = SC16IS7XX_MCR_CLKSEL_BIT;
499 div /= 4;
500 }
501
502 lcr = sc16is7xx_port_read(port, SC16IS7XX_LCR_REG);
503
504 /* Open the LCR divisors for configuration */
505 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG,
506 SC16IS7XX_LCR_CONF_MODE_B);
507
508 /* Enable enhanced features */
509 regcache_cache_bypass(s->regmap, true);
510 sc16is7xx_port_write(port, SC16IS7XX_EFR_REG,
511 SC16IS7XX_EFR_ENABLE_BIT);
512 regcache_cache_bypass(s->regmap, false);
513
514 /* Put LCR back to the normal mode */
515 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr);
516
517 sc16is7xx_port_update(port, SC16IS7XX_MCR_REG,
518 SC16IS7XX_MCR_CLKSEL_BIT,
519 prescaler);
520
521 /* Open the LCR divisors for configuration */
522 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG,
523 SC16IS7XX_LCR_CONF_MODE_A);
524
525 /* Write the new divisor */
526 regcache_cache_bypass(s->regmap, true);
527 sc16is7xx_port_write(port, SC16IS7XX_DLH_REG, div / 256);
528 sc16is7xx_port_write(port, SC16IS7XX_DLL_REG, div % 256);
529 regcache_cache_bypass(s->regmap, false);
530
531 /* Put LCR back to the normal mode */
532 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr);
533
534 return DIV_ROUND_CLOSEST(clk / 16, div);
535}
536
537static void sc16is7xx_handle_rx(struct uart_port *port, unsigned int rxlen,
538 unsigned int iir)
539{
540 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
541 unsigned int lsr = 0, ch, flag, bytes_read, i;
dfeae619
JR		 542 bool read_lsr = (iir == SC16IS7XX_IIR_RLSE_SRC) ? true : false;
543
beb04a9f 544 if (unlikely(rxlen >= sizeof(s->buf))) {
dfeae619 545 dev_warn_ratelimited(port->dev,
e92a886b 546 "ttySC%i: Possible RX FIFO overrun: %d\n",
dfeae619
JR		 547 port->line, rxlen);
548 port->icount.buf_overrun++;
549 /* Ensure sanity of RX level */
beb04a9f 550 rxlen = sizeof(s->buf);
dfeae619
JR		 551 }
552
553 while (rxlen) {
554 /* Only read lsr if there are possible errors in FIFO */
555 if (read_lsr) {
556 lsr = sc16is7xx_port_read(port, SC16IS7XX_LSR_REG);
557 if (!(lsr & SC16IS7XX_LSR_FIFOE_BIT))
558 read_lsr = false; /* No errors left in FIFO */
559 } else
560 lsr = 0;
561
562 if (read_lsr) {
beb04a9f 563 s->buf[0] = sc16is7xx_port_read(port, SC16IS7XX_RHR_REG);
dfeae619
JR		 564 bytes_read = 1;
565 } else {
dec273ec 566 sc16is7xx_fifo_read(port, rxlen);
dfeae619
JR		 567 bytes_read = rxlen;
568 }
569
570 lsr &= SC16IS7XX_LSR_BRK_ERROR_MASK;
571
572 port->icount.rx++;
573 flag = TTY_NORMAL;
574
575 if (unlikely(lsr)) {
576 if (lsr & SC16IS7XX_LSR_BI_BIT) {
577 port->icount.brk++;
578 if (uart_handle_break(port))
579 continue;
580 } else if (lsr & SC16IS7XX_LSR_PE_BIT)
581 port->icount.parity++;
582 else if (lsr & SC16IS7XX_LSR_FE_BIT)
583 port->icount.frame++;
584 else if (lsr & SC16IS7XX_LSR_OE_BIT)
585 port->icount.overrun++;
586
587 lsr &= port->read_status_mask;
588 if (lsr & SC16IS7XX_LSR_BI_BIT)
589 flag = TTY_BREAK;
590 else if (lsr & SC16IS7XX_LSR_PE_BIT)
591 flag = TTY_PARITY;
592 else if (lsr & SC16IS7XX_LSR_FE_BIT)
593 flag = TTY_FRAME;
594 else if (lsr & SC16IS7XX_LSR_OE_BIT)
595 flag = TTY_OVERRUN;
596 }
597
598 for (i = 0; i < bytes_read; ++i) {
beb04a9f 599 ch = s->buf[i];
dfeae619
JR		 600 if (uart_handle_sysrq_char(port, ch))
601 continue;
602
603 if (lsr & port->ignore_status_mask)
604 continue;
605
606 uart_insert_char(port, lsr, SC16IS7XX_LSR_OE_BIT, ch,
607 flag);
608 }
609 rxlen -= bytes_read;
610 }
611
612 tty_flip_buffer_push(&port->state->port);
613}
614
615static void sc16is7xx_handle_tx(struct uart_port *port)
616{
617 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
618 struct circ_buf *xmit = &port->state->xmit;
619 unsigned int txlen, to_send, i;
dfeae619
JR		 620
621 if (unlikely(port->x_char)) {
622 sc16is7xx_port_write(port, SC16IS7XX_THR_REG, port->x_char);
623 port->icount.tx++;
624 port->x_char = 0;
625 return;
626 }
627
628 if (uart_circ_empty(xmit) || uart_tx_stopped(port))
629 return;
630
631 /* Get length of data pending in circular buffer */
632 to_send = uart_circ_chars_pending(xmit);
633 if (likely(to_send)) {
634 /* Limit to size of TX FIFO */
635 txlen = sc16is7xx_port_read(port, SC16IS7XX_TXLVL_REG);
ed7a8504
FA		 636 if (txlen > SC16IS7XX_FIFO_SIZE) {
637 dev_err_ratelimited(port->dev,
638 "chip reports %d free bytes in TX fifo, but it only has %d",
639 txlen, SC16IS7XX_FIFO_SIZE);
640 txlen = 0;
641 }
dfeae619
JR		 642 to_send = (to_send > txlen) ? txlen : to_send;
643
644 /* Add data to send */
645 port->icount.tx += to_send;
646
647 /* Convert to linear buffer */
648 for (i = 0; i < to_send; ++i) {
beb04a9f 649 s->buf[i] = xmit->buf[xmit->tail];
dfeae619
JR		 650 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
651 }
dec273ec
BS		 652
653 sc16is7xx_fifo_write(port, to_send);
dfeae619
JR		 654 }
655
656 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
657 uart_write_wakeup(port);
658}
659
660static void sc16is7xx_port_irq(struct sc16is7xx_port *s, int portno)
661{
662 struct uart_port *port = &s->p[portno].port;
663
664 do {
e69ef01f 665 unsigned int iir, rxlen;
dfeae619
JR		 666
667 iir = sc16is7xx_port_read(port, SC16IS7XX_IIR_REG);
668 if (iir & SC16IS7XX_IIR_NO_INT_BIT)
669 break;
670
671 iir &= SC16IS7XX_IIR_ID_MASK;
672
673 switch (iir) {
674 case SC16IS7XX_IIR_RDI_SRC:
675 case SC16IS7XX_IIR_RLSE_SRC:
676 case SC16IS7XX_IIR_RTOI_SRC:
677 case SC16IS7XX_IIR_XOFFI_SRC:
678 rxlen = sc16is7xx_port_read(port, SC16IS7XX_RXLVL_REG);
679 if (rxlen)
680 sc16is7xx_handle_rx(port, rxlen, iir);
681 break;
dfeae619 682 case SC16IS7XX_IIR_THRI_SRC:
dfeae619 683 sc16is7xx_handle_tx(port);
dfeae619
JR		 684 break;
685 default:
686 dev_err_ratelimited(port->dev,
e92a886b 687 "ttySC%i: Unexpected interrupt: %x",
dfeae619
JR		 688 port->line, iir);
689 break;
690 }
691 } while (1);
692}
693
9e6f4ca3 694static void sc16is7xx_ist(struct kthread_work *ws)
dfeae619 695{
9e6f4ca3 696 struct sc16is7xx_port *s = to_sc16is7xx_port(ws, irq_work);
dfeae619
JR		 697 int i;
698
c6434972 699 for (i = 0; i < s->devtype->nr_uart; ++i)
dfeae619 700 sc16is7xx_port_irq(s, i);
9e6f4ca3
JK		 701}
702
703static irqreturn_t sc16is7xx_irq(int irq, void *dev_id)
704{
705 struct sc16is7xx_port *s = (struct sc16is7xx_port *)dev_id;
706
3989144f 707 kthread_queue_work(&s->kworker, &s->irq_work);
dfeae619
JR		 708
709 return IRQ_HANDLED;
710}
711
9e6f4ca3 712static void sc16is7xx_tx_proc(struct kthread_work *ws)
dfeae619 713{
dbe5a40c 714 struct uart_port *port = &(to_sc16is7xx_one(ws, tx_work)->port);
dfeae619 715
dbe5a40c
JK		 716 if ((port->rs485.flags & SER_RS485_ENABLED) &&
717 (port->rs485.delay_rts_before_send > 0))
718 msleep(port->rs485.delay_rts_before_send);
719
720 sc16is7xx_handle_tx(port);
dfeae619
JR		 721}
722
478d1051
JK		 723static void sc16is7xx_reconf_rs485(struct uart_port *port)
724{
725 const u32 mask = SC16IS7XX_EFCR_AUTO_RS485_BIT |
726 SC16IS7XX_EFCR_RTS_INVERT_BIT;
727 u32 efcr = 0;
728 struct serial_rs485 *rs485 = &port->rs485;
729 unsigned long irqflags;
730
731 spin_lock_irqsave(&port->lock, irqflags);
732 if (rs485->flags & SER_RS485_ENABLED) {
733 efcr |= SC16IS7XX_EFCR_AUTO_RS485_BIT;
734
735 if (rs485->flags & SER_RS485_RTS_AFTER_SEND)
736 efcr |= SC16IS7XX_EFCR_RTS_INVERT_BIT;
737 }
738 spin_unlock_irqrestore(&port->lock, irqflags);
739
740 sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG, mask, efcr);
741}
742
a0104085
JK		 743static void sc16is7xx_reg_proc(struct kthread_work *ws)
744{
745 struct sc16is7xx_one *one = to_sc16is7xx_one(ws, reg_work);
746 struct sc16is7xx_one_config config;
747 unsigned long irqflags;
748
749 spin_lock_irqsave(&one->port.lock, irqflags);
750 config = one->config;
751 memset(&one->config, 0, sizeof(one->config));
752 spin_unlock_irqrestore(&one->port.lock, irqflags);
753
b7dfdea8 754 if (config.flags & SC16IS7XX_RECONF_MD) {
a0104085
JK		 755 sc16is7xx_port_update(&one->port, SC16IS7XX_MCR_REG,
756 SC16IS7XX_MCR_LOOP_BIT,
757 (one->port.mctrl & TIOCM_LOOP) ?
758 SC16IS7XX_MCR_LOOP_BIT : 0);
b7dfdea8
MB		 759 sc16is7xx_port_update(&one->port, SC16IS7XX_MCR_REG,
760 SC16IS7XX_MCR_RTS_BIT,
761 (one->port.mctrl & TIOCM_RTS) ?
762 SC16IS7XX_MCR_RTS_BIT : 0);
763 sc16is7xx_port_update(&one->port, SC16IS7XX_MCR_REG,
764 SC16IS7XX_MCR_DTR_BIT,
765 (one->port.mctrl & TIOCM_DTR) ?
766 SC16IS7XX_MCR_DTR_BIT : 0);
767 }
059d5815
JK		 768 if (config.flags & SC16IS7XX_RECONF_IER)
769 sc16is7xx_port_update(&one->port, SC16IS7XX_IER_REG,
770 config.ier_clear, 0);
478d1051
JK		 771
772 if (config.flags & SC16IS7XX_RECONF_RS485)
773 sc16is7xx_reconf_rs485(&one->port);
a0104085
JK		 774}
775
059d5815 776static void sc16is7xx_ier_clear(struct uart_port *port, u8 bit)
dfeae619 777{
059d5815
JK		 778 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
779 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
780
781 one->config.flags |= SC16IS7XX_RECONF_IER;
782 one->config.ier_clear |= bit;
3989144f 783 kthread_queue_work(&s->kworker, &one->reg_work);
dfeae619
JR		 784}
785
059d5815 786static void sc16is7xx_stop_tx(struct uart_port *port)
dfeae619 787{
059d5815
JK		 788 sc16is7xx_ier_clear(port, SC16IS7XX_IER_THRI_BIT);
789}
dfeae619 790
059d5815
JK		 791static void sc16is7xx_stop_rx(struct uart_port *port)
792{
793 sc16is7xx_ier_clear(port, SC16IS7XX_IER_RDI_BIT);
dfeae619
JR		 794}
795
796static void sc16is7xx_start_tx(struct uart_port *port)
797{
9e6f4ca3 798 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
dfeae619
JR		 799 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
800
3989144f 801 kthread_queue_work(&s->kworker, &one->tx_work);
dfeae619
JR		 802}
803
804static unsigned int sc16is7xx_tx_empty(struct uart_port *port)
805{
4ae82e5d 806 unsigned int lsr;
dfeae619 807
dfeae619
JR		 808 lsr = sc16is7xx_port_read(port, SC16IS7XX_LSR_REG);
809
4ae82e5d 810 return (lsr & SC16IS7XX_LSR_TEMT_BIT) ? TIOCSER_TEMT : 0;
dfeae619
JR		 811}
812
813static unsigned int sc16is7xx_get_mctrl(struct uart_port *port)
814{
5f535733
GKH		 815 /* DCD and DSR are not wired and CTS/RTS is handled automatically
816 * so just indicate DSR and CAR asserted
817 */
818 return TIOCM_DSR | TIOCM_CAR;
dfeae619
JR		 819}
820
dfeae619
JR		 821static void sc16is7xx_set_mctrl(struct uart_port *port, unsigned int mctrl)
822{
a0104085 823 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
dfeae619
JR		 824 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
825
a0104085 826 one->config.flags |= SC16IS7XX_RECONF_MD;
3989144f 827 kthread_queue_work(&s->kworker, &one->reg_work);
dfeae619
JR		 828}
829
830static void sc16is7xx_break_ctl(struct uart_port *port, int break_state)
831{
832 sc16is7xx_port_update(port, SC16IS7XX_LCR_REG,
833 SC16IS7XX_LCR_TXBREAK_BIT,
834 break_state ? SC16IS7XX_LCR_TXBREAK_BIT : 0);
835}
836
837static void sc16is7xx_set_termios(struct uart_port *port,
838 struct ktermios *termios,
839 struct ktermios *old)
840{
841 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
842 unsigned int lcr, flow = 0;
843 int baud;
844
845 /* Mask termios capabilities we don't support */
846 termios->c_cflag &= ~CMSPAR;
847
848 /* Word size */
849 switch (termios->c_cflag & CSIZE) {
850 case CS5:
851 lcr = SC16IS7XX_LCR_WORD_LEN_5;
852 break;
853 case CS6:
854 lcr = SC16IS7XX_LCR_WORD_LEN_6;
855 break;
856 case CS7:
857 lcr = SC16IS7XX_LCR_WORD_LEN_7;
858 break;
859 case CS8:
860 lcr = SC16IS7XX_LCR_WORD_LEN_8;
861 break;
862 default:
863 lcr = SC16IS7XX_LCR_WORD_LEN_8;
864 termios->c_cflag &= ~CSIZE;
865 termios->c_cflag |= CS8;
866 break;
867 }
868
869 /* Parity */
870 if (termios->c_cflag & PARENB) {
871 lcr |= SC16IS7XX_LCR_PARITY_BIT;
872 if (!(termios->c_cflag & PARODD))
873 lcr |= SC16IS7XX_LCR_EVENPARITY_BIT;
874 }
875
876 /* Stop bits */
877 if (termios->c_cflag & CSTOPB)
878 lcr |= SC16IS7XX_LCR_STOPLEN_BIT; /* 2 stops */
879
880 /* Set read status mask */
881 port->read_status_mask = SC16IS7XX_LSR_OE_BIT;
882 if (termios->c_iflag & INPCK)
883 port->read_status_mask |= SC16IS7XX_LSR_PE_BIT |
884 SC16IS7XX_LSR_FE_BIT;
885 if (termios->c_iflag & (BRKINT | PARMRK))
886 port->read_status_mask |= SC16IS7XX_LSR_BI_BIT;
887
888 /* Set status ignore mask */
889 port->ignore_status_mask = 0;
890 if (termios->c_iflag & IGNBRK)
891 port->ignore_status_mask |= SC16IS7XX_LSR_BI_BIT;
892 if (!(termios->c_cflag & CREAD))
893 port->ignore_status_mask |= SC16IS7XX_LSR_BRK_ERROR_MASK;
894
895 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG,
896 SC16IS7XX_LCR_CONF_MODE_B);
897
898 /* Configure flow control */
899 regcache_cache_bypass(s->regmap, true);
900 sc16is7xx_port_write(port, SC16IS7XX_XON1_REG, termios->c_cc[VSTART]);
901 sc16is7xx_port_write(port, SC16IS7XX_XOFF1_REG, termios->c_cc[VSTOP]);
902 if (termios->c_cflag & CRTSCTS)
903 flow |= SC16IS7XX_EFR_AUTOCTS_BIT |
904 SC16IS7XX_EFR_AUTORTS_BIT;
905 if (termios->c_iflag & IXON)
906 flow |= SC16IS7XX_EFR_SWFLOW3_BIT;
907 if (termios->c_iflag & IXOFF)
908 flow |= SC16IS7XX_EFR_SWFLOW1_BIT;
909
910 sc16is7xx_port_write(port, SC16IS7XX_EFR_REG, flow);
911 regcache_cache_bypass(s->regmap, false);
912
913 /* Update LCR register */
914 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, lcr);
915
916 /* Get baud rate generator configuration */
917 baud = uart_get_baud_rate(port, termios, old,
918 port->uartclk / 16 / 4 / 0xffff,
919 port->uartclk / 16);
920
921 /* Setup baudrate generator */
922 baud = sc16is7xx_set_baud(port, baud);
923
924 /* Update timeout according to new baud rate */
925 uart_update_timeout(port, termios->c_cflag, baud);
926}
927
b57d15fe 928static int sc16is7xx_config_rs485(struct uart_port *port,
f0e38115 929 struct serial_rs485 *rs485)
dfeae619 930{
478d1051
JK		 931 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
932 struct sc16is7xx_one *one = to_sc16is7xx_one(port, port);
f0e38115
JK		 933
934 if (rs485->flags & SER_RS485_ENABLED) {
935 bool rts_during_rx, rts_during_tx;
936
937 rts_during_rx = rs485->flags & SER_RS485_RTS_AFTER_SEND;
938 rts_during_tx = rs485->flags & SER_RS485_RTS_ON_SEND;
939
478d1051 940 if (rts_during_rx == rts_during_tx)
f0e38115
JK		 941 dev_err(port->dev,
942 "unsupported RTS signalling on_send:%d after_send:%d - exactly one of RS485 RTS flags should be set\n",
943 rts_during_tx, rts_during_rx);
5451bb29
JK		 944
945 /*
946 * RTS signal is handled by HW, it's timing can't be influenced.
947 * However, it's sometimes useful to delay TX even without RTS
948 * control therefore we try to handle .delay_rts_before_send.
949 */
950 if (rs485->delay_rts_after_send)
951 return -EINVAL;
f0e38115
JK		 952 }
953
b57d15fe 954 port->rs485 = *rs485;
478d1051 955 one->config.flags |= SC16IS7XX_RECONF_RS485;
3989144f 956 kthread_queue_work(&s->kworker, &one->reg_work);
dfeae619 957
b57d15fe 958 return 0;
dfeae619
JR		 959}
960
961static int sc16is7xx_startup(struct uart_port *port)
962{
963 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
964 unsigned int val;
965
966 sc16is7xx_power(port, 1);
967
968 /* Reset FIFOs*/
969 val = SC16IS7XX_FCR_RXRESET_BIT | SC16IS7XX_FCR_TXRESET_BIT;
970 sc16is7xx_port_write(port, SC16IS7XX_FCR_REG, val);
971 udelay(5);
972 sc16is7xx_port_write(port, SC16IS7XX_FCR_REG,
973 SC16IS7XX_FCR_FIFO_BIT);
974
975 /* Enable EFR */
976 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG,
977 SC16IS7XX_LCR_CONF_MODE_B);
978
979 regcache_cache_bypass(s->regmap, true);
980
981 /* Enable write access to enhanced features and internal clock div */
982 sc16is7xx_port_write(port, SC16IS7XX_EFR_REG,
983 SC16IS7XX_EFR_ENABLE_BIT);
984
985 /* Enable TCR/TLR */
986 sc16is7xx_port_update(port, SC16IS7XX_MCR_REG,
987 SC16IS7XX_MCR_TCRTLR_BIT,
988 SC16IS7XX_MCR_TCRTLR_BIT);
989
990 /* Configure flow control levels */
991 /* Flow control halt level 48, resume level 24 */
992 sc16is7xx_port_write(port, SC16IS7XX_TCR_REG,
993 SC16IS7XX_TCR_RX_RESUME(24) |
994 SC16IS7XX_TCR_RX_HALT(48));
995
996 regcache_cache_bypass(s->regmap, false);
997
998 /* Now, initialize the UART */
999 sc16is7xx_port_write(port, SC16IS7XX_LCR_REG, SC16IS7XX_LCR_WORD_LEN_8);
1000
1001 /* Enable the Rx and Tx FIFO */
1002 sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG,
1003 SC16IS7XX_EFCR_RXDISABLE_BIT |
1004 SC16IS7XX_EFCR_TXDISABLE_BIT,
1005 0);
1006
e69ef01f
WW		 1007 /* Enable RX, TX interrupts */
1008 val = SC16IS7XX_IER_RDI_BIT | SC16IS7XX_IER_THRI_BIT;
dfeae619
JR		 1009 sc16is7xx_port_write(port, SC16IS7XX_IER_REG, val);
1010
1011 return 0;
1012}
1013
1014static void sc16is7xx_shutdown(struct uart_port *port)
1015{
9e6f4ca3
JK		 1016 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
1017
dfeae619
JR		 1018 /* Disable all interrupts */
1019 sc16is7xx_port_write(port, SC16IS7XX_IER_REG, 0);
1020 /* Disable TX/RX */
9764e7a0
JK		 1021 sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG,
1022 SC16IS7XX_EFCR_RXDISABLE_BIT |
1023 SC16IS7XX_EFCR_TXDISABLE_BIT,
1024 SC16IS7XX_EFCR_RXDISABLE_BIT |
1025 SC16IS7XX_EFCR_TXDISABLE_BIT);
dfeae619
JR		 1026
1027 sc16is7xx_power(port, 0);
9e6f4ca3 1028
3989144f 1029 kthread_flush_worker(&s->kworker);
dfeae619
JR		 1030}
1031
1032static const char *sc16is7xx_type(struct uart_port *port)
1033{
1034 struct sc16is7xx_port *s = dev_get_drvdata(port->dev);
1035
1036 return (port->type == PORT_SC16IS7XX) ? s->devtype->name : NULL;
1037}
1038
1039static int sc16is7xx_request_port(struct uart_port *port)
1040{
1041 /* Do nothing */
1042 return 0;
1043}
1044
1045static void sc16is7xx_config_port(struct uart_port *port, int flags)
1046{
1047 if (flags & UART_CONFIG_TYPE)
1048 port->type = PORT_SC16IS7XX;
1049}
1050
1051static int sc16is7xx_verify_port(struct uart_port *port,
1052 struct serial_struct *s)
1053{
1054 if ((s->type != PORT_UNKNOWN) && (s->type != PORT_SC16IS7XX))
1055 return -EINVAL;
1056 if (s->irq != port->irq)
1057 return -EINVAL;
1058
1059 return 0;
1060}
1061
1062static void sc16is7xx_pm(struct uart_port *port, unsigned int state,
1063 unsigned int oldstate)
1064{
1065 sc16is7xx_power(port, (state == UART_PM_STATE_ON) ? 1 : 0);
1066}
1067
1068static void sc16is7xx_null_void(struct uart_port *port)
1069{
1070 /* Do nothing */
1071}
1072
1073static const struct uart_ops sc16is7xx_ops = {
1074 .tx_empty = sc16is7xx_tx_empty,
1075 .set_mctrl = sc16is7xx_set_mctrl,
1076 .get_mctrl = sc16is7xx_get_mctrl,
1077 .stop_tx = sc16is7xx_stop_tx,
1078 .start_tx = sc16is7xx_start_tx,
1079 .stop_rx = sc16is7xx_stop_rx,
dfeae619
JR		 1080 .break_ctl = sc16is7xx_break_ctl,
1081 .startup = sc16is7xx_startup,
1082 .shutdown = sc16is7xx_shutdown,
1083 .set_termios = sc16is7xx_set_termios,
1084 .type = sc16is7xx_type,
1085 .request_port = sc16is7xx_request_port,
1086 .release_port = sc16is7xx_null_void,
1087 .config_port = sc16is7xx_config_port,
1088 .verify_port = sc16is7xx_verify_port,
dfeae619
JR		 1089 .pm = sc16is7xx_pm,
1090};
1091
1092#ifdef CONFIG_GPIOLIB
1093static int sc16is7xx_gpio_get(struct gpio_chip *chip, unsigned offset)
1094{
1095 unsigned int val;
dee07cea 1096 struct sc16is7xx_port *s = gpiochip_get_data(chip);
dfeae619
JR		 1097 struct uart_port *port = &s->p[0].port;
1098
1099 val = sc16is7xx_port_read(port, SC16IS7XX_IOSTATE_REG);
1100
1101 return !!(val & BIT(offset));
1102}
1103
1104static void sc16is7xx_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
1105{
dee07cea 1106 struct sc16is7xx_port *s = gpiochip_get_data(chip);
dfeae619
JR		 1107 struct uart_port *port = &s->p[0].port;
1108
1109 sc16is7xx_port_update(port, SC16IS7XX_IOSTATE_REG, BIT(offset),
1110 val ? BIT(offset) : 0);
1111}
1112
1113static int sc16is7xx_gpio_direction_input(struct gpio_chip *chip,
1114 unsigned offset)
1115{
dee07cea 1116 struct sc16is7xx_port *s = gpiochip_get_data(chip);
dfeae619
JR		 1117 struct uart_port *port = &s->p[0].port;
1118
1119 sc16is7xx_port_update(port, SC16IS7XX_IODIR_REG, BIT(offset), 0);
1120
1121 return 0;
1122}
1123
1124static int sc16is7xx_gpio_direction_output(struct gpio_chip *chip,
1125 unsigned offset, int val)
1126{
dee07cea 1127 struct sc16is7xx_port *s = gpiochip_get_data(chip);
dfeae619 1128 struct uart_port *port = &s->p[0].port;
03842c17 1129 u8 state = sc16is7xx_port_read(port, SC16IS7XX_IOSTATE_REG);
dfeae619 1130
03842c17
FB		 1131 if (val)
1132 state |= BIT(offset);
1133 else
1134 state &= ~BIT(offset);
1135 sc16is7xx_port_write(port, SC16IS7XX_IOSTATE_REG, state);
dfeae619
JR		 1136 sc16is7xx_port_update(port, SC16IS7XX_IODIR_REG, BIT(offset),
1137 BIT(offset));
1138
1139 return 0;
1140}
1141#endif
1142
1143static int sc16is7xx_probe(struct device *dev,
68be64ca 1144 const struct sc16is7xx_devtype *devtype,
dfeae619
JR		 1145 struct regmap *regmap, int irq, unsigned long flags)
1146{
9e6f4ca3 1147 struct sched_param sched_param = { .sched_priority = MAX_RT_PRIO / 2 };
dfeae619 1148 unsigned long freq, *pfreq = dev_get_platdata(dev);
dfeae619
JR		 1149 int i, ret;
1150 struct sc16is7xx_port *s;
1151
1152 if (IS_ERR(regmap))
1153 return PTR_ERR(regmap);
1154
1155 /* Alloc port structure */
1156 s = devm_kzalloc(dev, sizeof(*s) +
1157 sizeof(struct sc16is7xx_one) * devtype->nr_uart,
1158 GFP_KERNEL);
1159 if (!s) {
1160 dev_err(dev, "Error allocating port structure\n");
1161 return -ENOMEM;
1162 }
1163
dc824ebe
JR		 1164 s->clk = devm_clk_get(dev, NULL);
1165 if (IS_ERR(s->clk)) {
dfeae619
JR		 1166 if (pfreq)
1167 freq = *pfreq;
1168 else
dc824ebe 1169 return PTR_ERR(s->clk);
dfeae619 1170 } else {
e76785d0
SP		 1171 ret = clk_prepare_enable(s->clk);
1172 if (ret)
1173 return ret;
1174
dc824ebe 1175 freq = clk_get_rate(s->clk);
dfeae619
JR		 1176 }
1177
1178 s->regmap = regmap;
1179 s->devtype = devtype;
1180 dev_set_drvdata(dev, s);
1181
3989144f
PM		 1182 kthread_init_worker(&s->kworker);
1183 kthread_init_work(&s->irq_work, sc16is7xx_ist);
9e6f4ca3
JK		 1184 s->kworker_task = kthread_run(kthread_worker_fn, &s->kworker,
1185 "sc16is7xx");
1186 if (IS_ERR(s->kworker_task)) {
1187 ret = PTR_ERR(s->kworker_task);
c6434972 1188 goto out_clk;
9e6f4ca3
JK		 1189 }
1190 sched_setscheduler(s->kworker_task, SCHED_FIFO, &sched_param);
1191
dfeae619
JR		 1192#ifdef CONFIG_GPIOLIB
1193 if (devtype->nr_gpio) {
1194 /* Setup GPIO cotroller */
1195 s->gpio.owner = THIS_MODULE;
58383c78 1196 s->gpio.parent = dev;
dfeae619
JR		 1197 s->gpio.label = dev_name(dev);
1198 s->gpio.direction_input = sc16is7xx_gpio_direction_input;
1199 s->gpio.get = sc16is7xx_gpio_get;
1200 s->gpio.direction_output = sc16is7xx_gpio_direction_output;
1201 s->gpio.set = sc16is7xx_gpio_set;
1202 s->gpio.base = -1;
1203 s->gpio.ngpio = devtype->nr_gpio;
1204 s->gpio.can_sleep = 1;
dee07cea 1205 ret = gpiochip_add_data(&s->gpio, s);
dfeae619 1206 if (ret)
9e6f4ca3 1207 goto out_thread;
dfeae619
JR		 1208 }
1209#endif
1210
43c51bb5
FV		 1211 /* reset device, purging any pending irq / data */
1212 regmap_write(s->regmap, SC16IS7XX_IOCONTROL_REG << SC16IS7XX_REG_SHIFT,
1213 SC16IS7XX_IOCONTROL_SRESET_BIT);
1214
dfeae619 1215 for (i = 0; i < devtype->nr_uart; ++i) {
e92a886b 1216 s->p[i].line = i;
dfeae619 1217 /* Initialize port data */
dfeae619
JR		 1218 s->p[i].port.dev = dev;
1219 s->p[i].port.irq = irq;
1220 s->p[i].port.type = PORT_SC16IS7XX;
1221 s->p[i].port.fifosize = SC16IS7XX_FIFO_SIZE;
1222 s->p[i].port.flags = UPF_FIXED_TYPE | UPF_LOW_LATENCY;
1223 s->p[i].port.iotype = UPIO_PORT;
1224 s->p[i].port.uartclk = freq;
b57d15fe 1225 s->p[i].port.rs485_config = sc16is7xx_config_rs485;
dfeae619 1226 s->p[i].port.ops = &sc16is7xx_ops;
c6434972
JK		 1227 s->p[i].port.line = sc16is7xx_alloc_line();
1228 if (s->p[i].port.line >= SC16IS7XX_MAX_DEVS) {
1229 ret = -ENOMEM;
1230 goto out_ports;
1231 }
1232
dfeae619
JR		 1233 /* Disable all interrupts */
1234 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_IER_REG, 0);
1235 /* Disable TX/RX */
1236 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_EFCR_REG,
1237 SC16IS7XX_EFCR_RXDISABLE_BIT |
1238 SC16IS7XX_EFCR_TXDISABLE_BIT);
a0104085 1239 /* Initialize kthread work structs */
3989144f
PM		 1240 kthread_init_work(&s->p[i].tx_work, sc16is7xx_tx_proc);
1241 kthread_init_work(&s->p[i].reg_work, sc16is7xx_reg_proc);
dfeae619 1242 /* Register port */
c6434972 1243 uart_add_one_port(&sc16is7xx_uart, &s->p[i].port);
43c51bb5
FV		 1244
1245 /* Enable EFR */
1246 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_LCR_REG,
1247 SC16IS7XX_LCR_CONF_MODE_B);
1248
1249 regcache_cache_bypass(s->regmap, true);
1250
1251 /* Enable write access to enhanced features */
1252 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_EFR_REG,
1253 SC16IS7XX_EFR_ENABLE_BIT);
1254
1255 regcache_cache_bypass(s->regmap, false);
1256
1257 /* Restore access to general registers */
1258 sc16is7xx_port_write(&s->p[i].port, SC16IS7XX_LCR_REG, 0x00);
1259
dfeae619
JR		 1260 /* Go to suspend mode */
1261 sc16is7xx_power(&s->p[i].port, 0);
1262 }
1263
1264 /* Setup interrupt */
9e6f4ca3 1265 ret = devm_request_irq(dev, irq, sc16is7xx_irq,
04da7380 1266 flags, dev_name(dev), s);
dfeae619
JR		 1267 if (!ret)
1268 return 0;
1269
c6434972
JK		 1270out_ports:
1271 for (i--; i >= 0; i--) {
1272 uart_remove_one_port(&sc16is7xx_uart, &s->p[i].port);
1273 clear_bit(s->p[i].port.line, &sc16is7xx_lines);
1274 }
11b03ea0 1275
dfeae619
JR		 1276#ifdef CONFIG_GPIOLIB
1277 if (devtype->nr_gpio)
e27e2786 1278 gpiochip_remove(&s->gpio);
dfeae619 1279
9e6f4ca3 1280out_thread:
dfeae619 1281#endif
9e6f4ca3
JK		 1282 kthread_stop(s->kworker_task);
1283
dfeae619
JR		 1284out_clk:
1285 if (!IS_ERR(s->clk))
1286 clk_disable_unprepare(s->clk);
1287
1288 return ret;
1289}
1290
1291static int sc16is7xx_remove(struct device *dev)
1292{
1293 struct sc16is7xx_port *s = dev_get_drvdata(dev);
e27e2786 1294 int i;
dfeae619
JR		 1295
1296#ifdef CONFIG_GPIOLIB
e27e2786
LW		 1297 if (s->devtype->nr_gpio)
1298 gpiochip_remove(&s->gpio);
dfeae619
JR		 1299#endif
1300
c6434972
JK		 1301 for (i = 0; i < s->devtype->nr_uart; i++) {
1302 uart_remove_one_port(&sc16is7xx_uart, &s->p[i].port);
1303 clear_bit(s->p[i].port.line, &sc16is7xx_lines);
dfeae619
JR		 1304 sc16is7xx_power(&s->p[i].port, 0);
1305 }
1306
3989144f 1307 kthread_flush_worker(&s->kworker);
9e6f4ca3
JK		 1308 kthread_stop(s->kworker_task);
1309
dfeae619
JR		 1310 if (!IS_ERR(s->clk))
1311 clk_disable_unprepare(s->clk);
1312
e27e2786 1313 return 0;
dfeae619
JR		 1314}
1315
1316static const struct of_device_id __maybe_unused sc16is7xx_dt_ids[] = {
1317 { .compatible = "nxp,sc16is740", .data = &sc16is74x_devtype, },
1318 { .compatible = "nxp,sc16is741", .data = &sc16is74x_devtype, },
1319 { .compatible = "nxp,sc16is750", .data = &sc16is750_devtype, },
1320 { .compatible = "nxp,sc16is752", .data = &sc16is752_devtype, },
1321 { .compatible = "nxp,sc16is760", .data = &sc16is760_devtype, },
1322 { .compatible = "nxp,sc16is762", .data = &sc16is762_devtype, },
1323 { }
1324};
1325MODULE_DEVICE_TABLE(of, sc16is7xx_dt_ids);
1326
1327static struct regmap_config regcfg = {
1328 .reg_bits = 7,
1329 .pad_bits = 1,
1330 .val_bits = 8,
1331 .cache_type = REGCACHE_RBTREE,
1332 .volatile_reg = sc16is7xx_regmap_volatile,
1333 .precious_reg = sc16is7xx_regmap_precious,
1334};
1335
2c837a8a
RKKI		 1336#ifdef CONFIG_SERIAL_SC16IS7XX_SPI
1337static int sc16is7xx_spi_probe(struct spi_device *spi)
1338{
68be64ca 1339 const struct sc16is7xx_devtype *devtype;
2c837a8a
RKKI		 1340 unsigned long flags = 0;
1341 struct regmap *regmap;
1342 int ret;
1343
1344 /* Setup SPI bus */
1345 spi->bits_per_word = 8;
1346 /* only supports mode 0 on SC16IS762 */
1347 spi->mode = spi->mode ? : SPI_MODE_0;
1348 spi->max_speed_hz = spi->max_speed_hz ? : 15000000;
1349 ret = spi_setup(spi);
1350 if (ret)
1351 return ret;
1352
1353 if (spi->dev.of_node) {
1354 const struct of_device_id *of_id =
1355 of_match_device(sc16is7xx_dt_ids, &spi->dev);
1356
2b0159d1
SN		 1357 if (!of_id)
1358 return -ENODEV;
1359
2c837a8a
RKKI		 1360 devtype = (struct sc16is7xx_devtype *)of_id->data;
1361 } else {
1362 const struct spi_device_id *id_entry = spi_get_device_id(spi);
1363
1364 devtype = (struct sc16is7xx_devtype *)id_entry->driver_data;
1365 flags = IRQF_TRIGGER_FALLING;
1366 }
1367
1368 regcfg.max_register = (0xf << SC16IS7XX_REG_SHIFT) |
1369 (devtype->nr_uart - 1);
1370 regmap = devm_regmap_init_spi(spi, &regcfg);
1371
1372 return sc16is7xx_probe(&spi->dev, devtype, regmap, spi->irq, flags);
1373}
1374
1375static int sc16is7xx_spi_remove(struct spi_device *spi)
1376{
1377 return sc16is7xx_remove(&spi->dev);
1378}
1379
1380static const struct spi_device_id sc16is7xx_spi_id_table[] = {
1381 { "sc16is74x", (kernel_ulong_t)&sc16is74x_devtype, },
4117a60c
JK		 1382 { "sc16is740", (kernel_ulong_t)&sc16is74x_devtype, },
1383 { "sc16is741", (kernel_ulong_t)&sc16is74x_devtype, },
2c837a8a
RKKI		 1384 { "sc16is750", (kernel_ulong_t)&sc16is750_devtype, },
1385 { "sc16is752", (kernel_ulong_t)&sc16is752_devtype, },
1386 { "sc16is760", (kernel_ulong_t)&sc16is760_devtype, },
1387 { "sc16is762", (kernel_ulong_t)&sc16is762_devtype, },
1388 { }
1389};
1390
1391MODULE_DEVICE_TABLE(spi, sc16is7xx_spi_id_table);
1392
1393static struct spi_driver sc16is7xx_spi_uart_driver = {
1394 .driver = {
1395 .name = SC16IS7XX_NAME,
2c837a8a
RKKI		 1396 .of_match_table = of_match_ptr(sc16is7xx_dt_ids),
1397 },
1398 .probe = sc16is7xx_spi_probe,
1399 .remove = sc16is7xx_spi_remove,
1400 .id_table = sc16is7xx_spi_id_table,
1401};
1402
1403MODULE_ALIAS("spi:sc16is7xx");
1404#endif
1405
1406#ifdef CONFIG_SERIAL_SC16IS7XX_I2C
dfeae619
JR		 1407static int sc16is7xx_i2c_probe(struct i2c_client *i2c,
1408 const struct i2c_device_id *id)
1409{
68be64ca 1410 const struct sc16is7xx_devtype *devtype;
dfeae619
JR		 1411 unsigned long flags = 0;
1412 struct regmap *regmap;
1413
1414 if (i2c->dev.of_node) {
1415 const struct of_device_id *of_id =
1416 of_match_device(sc16is7xx_dt_ids, &i2c->dev);
1417
2b0159d1
SN		 1418 if (!of_id)
1419 return -ENODEV;
1420
dfeae619
JR		 1421 devtype = (struct sc16is7xx_devtype *)of_id->data;
1422 } else {
1423 devtype = (struct sc16is7xx_devtype *)id->driver_data;
1424 flags = IRQF_TRIGGER_FALLING;
1425 }
1426
1427 regcfg.max_register = (0xf << SC16IS7XX_REG_SHIFT) |
1428 (devtype->nr_uart - 1);
1429 regmap = devm_regmap_init_i2c(i2c, &regcfg);
1430
1431 return sc16is7xx_probe(&i2c->dev, devtype, regmap, i2c->irq, flags);
1432}
1433
1434static int sc16is7xx_i2c_remove(struct i2c_client *client)
1435{
1436 return sc16is7xx_remove(&client->dev);
1437}
1438
1439static const struct i2c_device_id sc16is7xx_i2c_id_table[] = {
1440 { "sc16is74x", (kernel_ulong_t)&sc16is74x_devtype, },
4117a60c
JK		 1441 { "sc16is740", (kernel_ulong_t)&sc16is74x_devtype, },
1442 { "sc16is741", (kernel_ulong_t)&sc16is74x_devtype, },
dfeae619
JR		 1443 { "sc16is750", (kernel_ulong_t)&sc16is750_devtype, },
1444 { "sc16is752", (kernel_ulong_t)&sc16is752_devtype, },
1445 { "sc16is760", (kernel_ulong_t)&sc16is760_devtype, },
1446 { "sc16is762", (kernel_ulong_t)&sc16is762_devtype, },
1447 { }
1448};
1449MODULE_DEVICE_TABLE(i2c, sc16is7xx_i2c_id_table);
1450
1451static struct i2c_driver sc16is7xx_i2c_uart_driver = {
1452 .driver = {
1453 .name = SC16IS7XX_NAME,
dfeae619
JR		 1454 .of_match_table = of_match_ptr(sc16is7xx_dt_ids),
1455 },
1456 .probe = sc16is7xx_i2c_probe,
1457 .remove = sc16is7xx_i2c_remove,
1458 .id_table = sc16is7xx_i2c_id_table,
1459};
2c837a8a 1460
2c837a8a
RKKI		 1461#endif
1462
1463static int __init sc16is7xx_init(void)
1464{
c6434972
JK		 1465 int ret;
1466
1467 ret = uart_register_driver(&sc16is7xx_uart);
1468 if (ret) {
1469 pr_err("Registering UART driver failed\n");
1470 return ret;
1471 }
1472
2c837a8a
RKKI		 1473#ifdef CONFIG_SERIAL_SC16IS7XX_I2C
1474 ret = i2c_add_driver(&sc16is7xx_i2c_uart_driver);
1475 if (ret < 0) {
1476 pr_err("failed to init sc16is7xx i2c --> %d\n", ret);
1477 return ret;
1478 }
1479#endif
1480
1481#ifdef CONFIG_SERIAL_SC16IS7XX_SPI
1482 ret = spi_register_driver(&sc16is7xx_spi_uart_driver);
1483 if (ret < 0) {
1484 pr_err("failed to init sc16is7xx spi --> %d\n", ret);
1485 return ret;
1486 }
1487#endif
1488 return ret;
1489}
1490module_init(sc16is7xx_init);
1491
1492static void __exit sc16is7xx_exit(void)
1493{
1494#ifdef CONFIG_SERIAL_SC16IS7XX_I2C
1495 i2c_del_driver(&sc16is7xx_i2c_uart_driver);
1496#endif
1497
1498#ifdef CONFIG_SERIAL_SC16IS7XX_SPI
1499 spi_unregister_driver(&sc16is7xx_spi_uart_driver);
1500#endif
c6434972 1501 uart_unregister_driver(&sc16is7xx_uart);
2c837a8a
RKKI		 1502}
1503module_exit(sc16is7xx_exit);
dfeae619
JR		 1504
1505MODULE_LICENSE("GPL");
1506MODULE_AUTHOR("Jon Ringle <jringle@gridpoint.com>");
1507MODULE_DESCRIPTION("SC16IS7XX serial driver");
Linux 6.x block layer and io_uring tree(s)