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tty: add SPDX identifiers to all remaining files in drivers/tty/
[linux-2.6-block.git] / drivers / tty / serial / sb1250-duart.c
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e3b3d0f5 1// SPDX-License-Identifier: GPL-2.0+
b45d5279 2/*
b45d5279
MR		 3 * Support for the asynchronous serial interface (DUART) included
4 * in the BCM1250 and derived System-On-a-Chip (SOC) devices.
5 *
6 * Copyright (c) 2007 Maciej W. Rozycki
7 *
8 * Derived from drivers/char/sb1250_duart.c for which the following
9 * copyright applies:
10 *
11 * Copyright (c) 2000, 2001, 2002, 2003, 2004 Broadcom Corporation
12 *
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License
15 * as published by the Free Software Foundation; either version
16 * 2 of the License, or (at your option) any later version.
17 *
18 * References:
19 *
20 * "BCM1250/BCM1125/BCM1125H User Manual", Broadcom Corporation
21 */
22
23#if defined(CONFIG_SERIAL_SB1250_DUART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
24#define SUPPORT_SYSRQ
25#endif
26
86d0004a 27#include <linux/compiler.h>
b45d5279
MR		 28#include <linux/console.h>
29#include <linux/delay.h>
30#include <linux/errno.h>
31#include <linux/init.h>
32#include <linux/interrupt.h>
33#include <linux/ioport.h>
34#include <linux/kernel.h>
346f81a9 35#include <linux/module.h>
b45d5279
MR		 36#include <linux/major.h>
37#include <linux/serial.h>
38#include <linux/serial_core.h>
39#include <linux/spinlock.h>
40#include <linux/sysrq.h>
41#include <linux/tty.h>
ee160a38 42#include <linux/tty_flip.h>
b45d5279
MR		 43#include <linux/types.h>
44
22a33651 45#include <linux/refcount.h>
b45d5279
MR		 46#include <asm/io.h>
47#include <asm/war.h>
48
49#include <asm/sibyte/sb1250.h>
50#include <asm/sibyte/sb1250_uart.h>
51#include <asm/sibyte/swarm.h>
52
53
54#if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
55#include <asm/sibyte/bcm1480_regs.h>
56#include <asm/sibyte/bcm1480_int.h>
57
58#define SBD_CHANREGS(line) A_BCM1480_DUART_CHANREG((line), 0)
59#define SBD_CTRLREGS(line) A_BCM1480_DUART_CTRLREG((line), 0)
60#define SBD_INT(line) (K_BCM1480_INT_UART_0 + (line))
61
719b6f29
TS		 62#define DUART_CHANREG_SPACING BCM1480_DUART_CHANREG_SPACING
63
64#define R_DUART_IMRREG(line) R_BCM1480_DUART_IMRREG(line)
65#define R_DUART_INCHREG(line) R_BCM1480_DUART_INCHREG(line)
66#define R_DUART_ISRREG(line) R_BCM1480_DUART_ISRREG(line)
67
b45d5279
MR		 68#elif defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X)
69#include <asm/sibyte/sb1250_regs.h>
70#include <asm/sibyte/sb1250_int.h>
71
72#define SBD_CHANREGS(line) A_DUART_CHANREG((line), 0)
73#define SBD_CTRLREGS(line) A_DUART_CTRLREG(0)
74#define SBD_INT(line) (K_INT_UART_0 + (line))
75
76#else
77#error invalid SB1250 UART configuration
78
79#endif
80
81
82MODULE_AUTHOR("Maciej W. Rozycki <macro@linux-mips.org>");
83MODULE_DESCRIPTION("BCM1xxx on-chip DUART serial driver");
84MODULE_LICENSE("GPL");
85
86
87#define DUART_MAX_CHIP 2
88#define DUART_MAX_SIDE 2
89
90/*
91 * Per-port state.
92 */
93struct sbd_port {
94 struct sbd_duart *duart;
95 struct uart_port port;
96 unsigned char __iomem *memctrl;
97 int tx_stopped;
98 int initialised;
99};
100
101/*
102 * Per-DUART state for the shared register space.
103 */
104struct sbd_duart {
105 struct sbd_port sport[2];
106 unsigned long mapctrl;
22a33651 107 refcount_t map_guard;
b45d5279
MR		 108};
109
110#define to_sport(uport) container_of(uport, struct sbd_port, port)
111
112static struct sbd_duart sbd_duarts[DUART_MAX_CHIP];
113
b45d5279
MR		 114
115/*
116 * Reading and writing SB1250 DUART registers.
117 *
118 * There are three register spaces: two per-channel ones and
119 * a shared one. We have to define accessors appropriately.
120 * All registers are 64-bit and all but the Baud Rate Clock
121 * registers only define 8 least significant bits. There is
122 * also a workaround to take into account. Raw accessors use
123 * the full register width, but cooked ones truncate it
124 * intentionally so that the rest of the driver does not care.
125 */
126static u64 __read_sbdchn(struct sbd_port *sport, int reg)
127{
128 void __iomem *csr = sport->port.membase + reg;
129
130 return __raw_readq(csr);
131}
132
133static u64 __read_sbdshr(struct sbd_port *sport, int reg)
134{
135 void __iomem *csr = sport->memctrl + reg;
136
137 return __raw_readq(csr);
138}
139
140static void __write_sbdchn(struct sbd_port *sport, int reg, u64 value)
141{
142 void __iomem *csr = sport->port.membase + reg;
143
144 __raw_writeq(value, csr);
145}
146
147static void __write_sbdshr(struct sbd_port *sport, int reg, u64 value)
148{
149 void __iomem *csr = sport->memctrl + reg;
150
151 __raw_writeq(value, csr);
152}
153
154/*
155 * In bug 1956, we get glitches that can mess up uart registers. This
156 * "read-mode-reg after any register access" is an accepted workaround.
157 */
158static void __war_sbd1956(struct sbd_port *sport)
159{
160 __read_sbdchn(sport, R_DUART_MODE_REG_1);
161 __read_sbdchn(sport, R_DUART_MODE_REG_2);
162}
163
164static unsigned char read_sbdchn(struct sbd_port *sport, int reg)
165{
166 unsigned char retval;
167
168 retval = __read_sbdchn(sport, reg);
169 if (SIBYTE_1956_WAR)
170 __war_sbd1956(sport);
171 return retval;
172}
173
174static unsigned char read_sbdshr(struct sbd_port *sport, int reg)
175{
176 unsigned char retval;
177
178 retval = __read_sbdshr(sport, reg);
179 if (SIBYTE_1956_WAR)
180 __war_sbd1956(sport);
181 return retval;
182}
183
184static void write_sbdchn(struct sbd_port *sport, int reg, unsigned int value)
185{
186 __write_sbdchn(sport, reg, value);
187 if (SIBYTE_1956_WAR)
188 __war_sbd1956(sport);
189}
190
191static void write_sbdshr(struct sbd_port *sport, int reg, unsigned int value)
192{
193 __write_sbdshr(sport, reg, value);
194 if (SIBYTE_1956_WAR)
195 __war_sbd1956(sport);
196}
197
198
199static int sbd_receive_ready(struct sbd_port *sport)
200{
201 return read_sbdchn(sport, R_DUART_STATUS) & M_DUART_RX_RDY;
202}
203
204static int sbd_receive_drain(struct sbd_port *sport)
205{
206 int loops = 10000;
207
52e3632e 208 while (sbd_receive_ready(sport) && --loops)
b45d5279
MR		 209 read_sbdchn(sport, R_DUART_RX_HOLD);
210 return loops;
211}
212
86d0004a 213static int __maybe_unused sbd_transmit_ready(struct sbd_port *sport)
b45d5279
MR		 214{
215 return read_sbdchn(sport, R_DUART_STATUS) & M_DUART_TX_RDY;
216}
217
86d0004a 218static int __maybe_unused sbd_transmit_drain(struct sbd_port *sport)
b45d5279
MR		 219{
220 int loops = 10000;
221
52e3632e 222 while (!sbd_transmit_ready(sport) && --loops)
b45d5279
MR		 223 udelay(2);
224 return loops;
225}
226
227static int sbd_transmit_empty(struct sbd_port *sport)
228{
229 return read_sbdchn(sport, R_DUART_STATUS) & M_DUART_TX_EMT;
230}
231
232static int sbd_line_drain(struct sbd_port *sport)
233{
234 int loops = 10000;
235
52e3632e 236 while (!sbd_transmit_empty(sport) && --loops)
b45d5279
MR		 237 udelay(2);
238 return loops;
239}
240
241
242static unsigned int sbd_tx_empty(struct uart_port *uport)
243{
244 struct sbd_port *sport = to_sport(uport);
245
246 return sbd_transmit_empty(sport) ? TIOCSER_TEMT : 0;
247}
248
249static unsigned int sbd_get_mctrl(struct uart_port *uport)
250{
251 struct sbd_port *sport = to_sport(uport);
252 unsigned int mctrl, status;
253
254 status = read_sbdshr(sport, R_DUART_IN_PORT);
255 status >>= (uport->line) % 2;
256 mctrl = (!(status & M_DUART_IN_PIN0_VAL) ? TIOCM_CTS : 0) |
257 (!(status & M_DUART_IN_PIN4_VAL) ? TIOCM_CAR : 0) |
258 (!(status & M_DUART_RIN0_PIN) ? TIOCM_RNG : 0) |
259 (!(status & M_DUART_IN_PIN2_VAL) ? TIOCM_DSR : 0);
260 return mctrl;
261}
262
263static void sbd_set_mctrl(struct uart_port *uport, unsigned int mctrl)
264{
265 struct sbd_port *sport = to_sport(uport);
266 unsigned int clr = 0, set = 0, mode2;
267
268 if (mctrl & TIOCM_DTR)
269 set |= M_DUART_SET_OPR2;
270 else
271 clr |= M_DUART_CLR_OPR2;
272 if (mctrl & TIOCM_RTS)
273 set |= M_DUART_SET_OPR0;
274 else
275 clr |= M_DUART_CLR_OPR0;
276 clr <<= (uport->line) % 2;
277 set <<= (uport->line) % 2;
278
279 mode2 = read_sbdchn(sport, R_DUART_MODE_REG_2);
280 mode2 &= ~M_DUART_CHAN_MODE;
281 if (mctrl & TIOCM_LOOP)
282 mode2 |= V_DUART_CHAN_MODE_LCL_LOOP;
283 else
284 mode2 |= V_DUART_CHAN_MODE_NORMAL;
285
286 write_sbdshr(sport, R_DUART_CLEAR_OPR, clr);
287 write_sbdshr(sport, R_DUART_SET_OPR, set);
288 write_sbdchn(sport, R_DUART_MODE_REG_2, mode2);
289}
290
291static void sbd_stop_tx(struct uart_port *uport)
292{
293 struct sbd_port *sport = to_sport(uport);
294
295 write_sbdchn(sport, R_DUART_CMD, M_DUART_TX_DIS);
296 sport->tx_stopped = 1;
297};
298
299static void sbd_start_tx(struct uart_port *uport)
300{
301 struct sbd_port *sport = to_sport(uport);
302 unsigned int mask;
303
304 /* Enable tx interrupts. */
305 mask = read_sbdshr(sport, R_DUART_IMRREG((uport->line) % 2));
306 mask |= M_DUART_IMR_TX;
307 write_sbdshr(sport, R_DUART_IMRREG((uport->line) % 2), mask);
308
309 /* Go!, go!, go!... */
310 write_sbdchn(sport, R_DUART_CMD, M_DUART_TX_EN);
311 sport->tx_stopped = 0;
312};
313
314static void sbd_stop_rx(struct uart_port *uport)
315{
316 struct sbd_port *sport = to_sport(uport);
317
318 write_sbdshr(sport, R_DUART_IMRREG((uport->line) % 2), 0);
319};
320
321static void sbd_enable_ms(struct uart_port *uport)
322{
323 struct sbd_port *sport = to_sport(uport);
324
325 write_sbdchn(sport, R_DUART_AUXCTL_X,
326 M_DUART_CIN_CHNG_ENA | M_DUART_CTS_CHNG_ENA);
327}
328
329static void sbd_break_ctl(struct uart_port *uport, int break_state)
330{
331 struct sbd_port *sport = to_sport(uport);
332
333 if (break_state == -1)
334 write_sbdchn(sport, R_DUART_CMD, V_DUART_MISC_CMD_START_BREAK);
335 else
336 write_sbdchn(sport, R_DUART_CMD, V_DUART_MISC_CMD_STOP_BREAK);
337}
338
339
340static void sbd_receive_chars(struct sbd_port *sport)
341{
342 struct uart_port *uport = &sport->port;
343 struct uart_icount *icount;
344 unsigned int status, ch, flag;
345 int count;
346
347 for (count = 16; count; count--) {
348 status = read_sbdchn(sport, R_DUART_STATUS);
349 if (!(status & M_DUART_RX_RDY))
350 break;
351
352 ch = read_sbdchn(sport, R_DUART_RX_HOLD);
353
354 flag = TTY_NORMAL;
355
356 icount = &uport->icount;
357 icount->rx++;
358
359 if (unlikely(status &
360 (M_DUART_RCVD_BRK | M_DUART_FRM_ERR |
361 M_DUART_PARITY_ERR | M_DUART_OVRUN_ERR))) {
362 if (status & M_DUART_RCVD_BRK) {
363 icount->brk++;
364 if (uart_handle_break(uport))
365 continue;
366 } else if (status & M_DUART_FRM_ERR)
367 icount->frame++;
368 else if (status & M_DUART_PARITY_ERR)
369 icount->parity++;
370 if (status & M_DUART_OVRUN_ERR)
371 icount->overrun++;
372
373 status &= uport->read_status_mask;
374 if (status & M_DUART_RCVD_BRK)
375 flag = TTY_BREAK;
376 else if (status & M_DUART_FRM_ERR)
377 flag = TTY_FRAME;
378 else if (status & M_DUART_PARITY_ERR)
379 flag = TTY_PARITY;
380 }
381
382 if (uart_handle_sysrq_char(uport, ch))
383 continue;
384
385 uart_insert_char(uport, status, M_DUART_OVRUN_ERR, ch, flag);
386 }
387
2e124b4a 388 tty_flip_buffer_push(&uport->state->port);
b45d5279
MR		 389}
390
391static void sbd_transmit_chars(struct sbd_port *sport)
392{
393 struct uart_port *uport = &sport->port;
ebd2c8f6 394 struct circ_buf *xmit = &sport->port.state->xmit;
b45d5279
MR		 395 unsigned int mask;
396 int stop_tx;
397
398 /* XON/XOFF chars. */
399 if (sport->port.x_char) {
400 write_sbdchn(sport, R_DUART_TX_HOLD, sport->port.x_char);
401 sport->port.icount.tx++;
402 sport->port.x_char = 0;
403 return;
404 }
405
406 /* If nothing to do or stopped or hardware stopped. */
407 stop_tx = (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port));
408
409 /* Send char. */
410 if (!stop_tx) {
411 write_sbdchn(sport, R_DUART_TX_HOLD, xmit->buf[xmit->tail]);
412 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
413 sport->port.icount.tx++;
414
415 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
416 uart_write_wakeup(&sport->port);
417 }
418
419 /* Are we are done? */
420 if (stop_tx || uart_circ_empty(xmit)) {
421 /* Disable tx interrupts. */
422 mask = read_sbdshr(sport, R_DUART_IMRREG((uport->line) % 2));
423 mask &= ~M_DUART_IMR_TX;
424 write_sbdshr(sport, R_DUART_IMRREG((uport->line) % 2), mask);
425 }
426}
427
428static void sbd_status_handle(struct sbd_port *sport)
429{
430 struct uart_port *uport = &sport->port;
431 unsigned int delta;
432
433 delta = read_sbdshr(sport, R_DUART_INCHREG((uport->line) % 2));
434 delta >>= (uport->line) % 2;
435
436 if (delta & (M_DUART_IN_PIN0_VAL << S_DUART_IN_PIN_CHNG))
437 uart_handle_cts_change(uport, !(delta & M_DUART_IN_PIN0_VAL));
438
439 if (delta & (M_DUART_IN_PIN2_VAL << S_DUART_IN_PIN_CHNG))
440 uport->icount.dsr++;
441
442 if (delta & ((M_DUART_IN_PIN2_VAL | M_DUART_IN_PIN0_VAL) <<
443 S_DUART_IN_PIN_CHNG))
bdc04e31 444 wake_up_interruptible(&uport->state->port.delta_msr_wait);
b45d5279
MR		 445}
446
447static irqreturn_t sbd_interrupt(int irq, void *dev_id)
448{
449 struct sbd_port *sport = dev_id;
450 struct uart_port *uport = &sport->port;
451 irqreturn_t status = IRQ_NONE;
452 unsigned int intstat;
453 int count;
454
455 for (count = 16; count; count--) {
456 intstat = read_sbdshr(sport,
457 R_DUART_ISRREG((uport->line) % 2));
458 intstat &= read_sbdshr(sport,
459 R_DUART_IMRREG((uport->line) % 2));
460 intstat &= M_DUART_ISR_ALL;
461 if (!intstat)
462 break;
463
464 if (intstat & M_DUART_ISR_RX)
465 sbd_receive_chars(sport);
466 if (intstat & M_DUART_ISR_IN)
467 sbd_status_handle(sport);
468 if (intstat & M_DUART_ISR_TX)
469 sbd_transmit_chars(sport);
470
471 status = IRQ_HANDLED;
472 }
473
474 return status;
475}
476
477
478static int sbd_startup(struct uart_port *uport)
479{
480 struct sbd_port *sport = to_sport(uport);
481 unsigned int mode1;
482 int ret;
483
484 ret = request_irq(sport->port.irq, sbd_interrupt,
485 IRQF_SHARED, "sb1250-duart", sport);
486 if (ret)
487 return ret;
488
489 /* Clear the receive FIFO. */
490 sbd_receive_drain(sport);
491
492 /* Clear the interrupt registers. */
493 write_sbdchn(sport, R_DUART_CMD, V_DUART_MISC_CMD_RESET_BREAK_INT);
494 read_sbdshr(sport, R_DUART_INCHREG((uport->line) % 2));
495
496 /* Set rx/tx interrupt to FIFO available. */
497 mode1 = read_sbdchn(sport, R_DUART_MODE_REG_1);
498 mode1 &= ~(M_DUART_RX_IRQ_SEL_RXFULL | M_DUART_TX_IRQ_SEL_TXEMPT);
499 write_sbdchn(sport, R_DUART_MODE_REG_1, mode1);
500
501 /* Disable tx, enable rx. */
502 write_sbdchn(sport, R_DUART_CMD, M_DUART_TX_DIS | M_DUART_RX_EN);
503 sport->tx_stopped = 1;
504
505 /* Enable interrupts. */
506 write_sbdshr(sport, R_DUART_IMRREG((uport->line) % 2),
507 M_DUART_IMR_IN | M_DUART_IMR_RX);
508
509 return 0;
510}
511
512static void sbd_shutdown(struct uart_port *uport)
513{
514 struct sbd_port *sport = to_sport(uport);
515
516 write_sbdchn(sport, R_DUART_CMD, M_DUART_TX_DIS | M_DUART_RX_DIS);
517 sport->tx_stopped = 1;
518 free_irq(sport->port.irq, sport);
519}
520
521
522static void sbd_init_port(struct sbd_port *sport)
523{
524 struct uart_port *uport = &sport->port;
525
526 if (sport->initialised)
527 return;
528
529 /* There is no DUART reset feature, so just set some sane defaults. */
530 write_sbdchn(sport, R_DUART_CMD, V_DUART_MISC_CMD_RESET_TX);
531 write_sbdchn(sport, R_DUART_CMD, V_DUART_MISC_CMD_RESET_RX);
532 write_sbdchn(sport, R_DUART_MODE_REG_1, V_DUART_BITS_PER_CHAR_8);
533 write_sbdchn(sport, R_DUART_MODE_REG_2, 0);
534 write_sbdchn(sport, R_DUART_FULL_CTL,
535 V_DUART_INT_TIME(0) | V_DUART_SIG_FULL(15));
536 write_sbdchn(sport, R_DUART_OPCR_X, 0);
537 write_sbdchn(sport, R_DUART_AUXCTL_X, 0);
538 write_sbdshr(sport, R_DUART_IMRREG((uport->line) % 2), 0);
539
540 sport->initialised = 1;
541}
542
543static void sbd_set_termios(struct uart_port *uport, struct ktermios *termios,
544 struct ktermios *old_termios)
545{
546 struct sbd_port *sport = to_sport(uport);
547 unsigned int mode1 = 0, mode2 = 0, aux = 0;
548 unsigned int mode1mask = 0, mode2mask = 0, auxmask = 0;
549 unsigned int oldmode1, oldmode2, oldaux;
550 unsigned int baud, brg;
551 unsigned int command;
552
553 mode1mask |= ~(M_DUART_PARITY_MODE | M_DUART_PARITY_TYPE_ODD |
554 M_DUART_BITS_PER_CHAR);
555 mode2mask |= ~M_DUART_STOP_BIT_LEN_2;
556 auxmask |= ~M_DUART_CTS_CHNG_ENA;
557
558 /* Byte size. */
559 switch (termios->c_cflag & CSIZE) {
560 case CS5:
561 case CS6:
562 /* Unsupported, leave unchanged. */
563 mode1mask |= M_DUART_PARITY_MODE;
564 break;
565 case CS7:
566 mode1 |= V_DUART_BITS_PER_CHAR_7;
567 break;
568 case CS8:
569 default:
570 mode1 |= V_DUART_BITS_PER_CHAR_8;
571 break;
572 }
573
574 /* Parity and stop bits. */
575 if (termios->c_cflag & CSTOPB)
576 mode2 |= M_DUART_STOP_BIT_LEN_2;
577 else
578 mode2 |= M_DUART_STOP_BIT_LEN_1;
579 if (termios->c_cflag & PARENB)
580 mode1 |= V_DUART_PARITY_MODE_ADD;
581 else
582 mode1 |= V_DUART_PARITY_MODE_NONE;
583 if (termios->c_cflag & PARODD)
584 mode1 |= M_DUART_PARITY_TYPE_ODD;
585 else
586 mode1 |= M_DUART_PARITY_TYPE_EVEN;
587
588 baud = uart_get_baud_rate(uport, termios, old_termios, 1200, 5000000);
589 brg = V_DUART_BAUD_RATE(baud);
590 /* The actual lower bound is 1221bps, so compensate. */
591 if (brg > M_DUART_CLK_COUNTER)
592 brg = M_DUART_CLK_COUNTER;
593
594 uart_update_timeout(uport, termios->c_cflag, baud);
595
596 uport->read_status_mask = M_DUART_OVRUN_ERR;
597 if (termios->c_iflag & INPCK)
598 uport->read_status_mask |= M_DUART_FRM_ERR |
599 M_DUART_PARITY_ERR;
ef8b9ddc 600 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
b45d5279
MR		 601 uport->read_status_mask |= M_DUART_RCVD_BRK;
602
603 uport->ignore_status_mask = 0;
604 if (termios->c_iflag & IGNPAR)
605 uport->ignore_status_mask |= M_DUART_FRM_ERR |
606 M_DUART_PARITY_ERR;
607 if (termios->c_iflag & IGNBRK) {
608 uport->ignore_status_mask |= M_DUART_RCVD_BRK;
609 if (termios->c_iflag & IGNPAR)
610 uport->ignore_status_mask |= M_DUART_OVRUN_ERR;
611 }
612
613 if (termios->c_cflag & CREAD)
614 command = M_DUART_RX_EN;
615 else
616 command = M_DUART_RX_DIS;
617
618 if (termios->c_cflag & CRTSCTS)
619 aux |= M_DUART_CTS_CHNG_ENA;
620 else
621 aux &= ~M_DUART_CTS_CHNG_ENA;
622
623 spin_lock(&uport->lock);
624
625 if (sport->tx_stopped)
626 command |= M_DUART_TX_DIS;
627 else
628 command |= M_DUART_TX_EN;
629
630 oldmode1 = read_sbdchn(sport, R_DUART_MODE_REG_1) & mode1mask;
631 oldmode2 = read_sbdchn(sport, R_DUART_MODE_REG_2) & mode2mask;
632 oldaux = read_sbdchn(sport, R_DUART_AUXCTL_X) & auxmask;
633
634 if (!sport->tx_stopped)
635 sbd_line_drain(sport);
636 write_sbdchn(sport, R_DUART_CMD, M_DUART_TX_DIS | M_DUART_RX_DIS);
637
638 write_sbdchn(sport, R_DUART_MODE_REG_1, mode1 | oldmode1);
639 write_sbdchn(sport, R_DUART_MODE_REG_2, mode2 | oldmode2);
640 write_sbdchn(sport, R_DUART_CLK_SEL, brg);
641 write_sbdchn(sport, R_DUART_AUXCTL_X, aux | oldaux);
642
643 write_sbdchn(sport, R_DUART_CMD, command);
644
645 spin_unlock(&uport->lock);
646}
647
648
649static const char *sbd_type(struct uart_port *uport)
650{
651 return "SB1250 DUART";
652}
653
654static void sbd_release_port(struct uart_port *uport)
655{
656 struct sbd_port *sport = to_sport(uport);
657 struct sbd_duart *duart = sport->duart;
b45d5279
MR		 658
659 iounmap(sport->memctrl);
660 sport->memctrl = NULL;
661 iounmap(uport->membase);
662 uport->membase = NULL;
663
22a33651 664 if(refcount_dec_and_test(&duart->map_guard))
b45d5279
MR		 665 release_mem_region(duart->mapctrl, DUART_CHANREG_SPACING);
666 release_mem_region(uport->mapbase, DUART_CHANREG_SPACING);
667}
668
669static int sbd_map_port(struct uart_port *uport)
670{
86d0004a 671 const char *err = KERN_ERR "sbd: Cannot map MMIO\n";
b45d5279
MR		 672 struct sbd_port *sport = to_sport(uport);
673 struct sbd_duart *duart = sport->duart;
674
675 if (!uport->membase)
676 uport->membase = ioremap_nocache(uport->mapbase,
677 DUART_CHANREG_SPACING);
678 if (!uport->membase) {
679 printk(err);
680 return -ENOMEM;
681 }
682
683 if (!sport->memctrl)
684 sport->memctrl = ioremap_nocache(duart->mapctrl,
685 DUART_CHANREG_SPACING);
686 if (!sport->memctrl) {
687 printk(err);
688 iounmap(uport->membase);
689 uport->membase = NULL;
690 return -ENOMEM;
691 }
692
693 return 0;
694}
695
696static int sbd_request_port(struct uart_port *uport)
697{
86d0004a 698 const char *err = KERN_ERR "sbd: Unable to reserve MMIO resource\n";
b45d5279 699 struct sbd_duart *duart = to_sport(uport)->duart;
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MR		 700 int ret = 0;
701
702 if (!request_mem_region(uport->mapbase, DUART_CHANREG_SPACING,
703 "sb1250-duart")) {
704 printk(err);
705 return -EBUSY;
706 }
22a33651
ER		 707 refcount_inc(&duart->map_guard);
708 if (refcount_read(&duart->map_guard) == 1) {
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MR		 709 if (!request_mem_region(duart->mapctrl, DUART_CHANREG_SPACING,
710 "sb1250-duart")) {
22a33651 711 refcount_dec(&duart->map_guard);
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MR		 712 printk(err);
713 ret = -EBUSY;
714 }
715 }
716 if (!ret) {
717 ret = sbd_map_port(uport);
718 if (ret) {
22a33651 719 if (refcount_dec_and_test(&duart->map_guard))
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MR		 720 release_mem_region(duart->mapctrl,
721 DUART_CHANREG_SPACING);
722 }
723 }
724 if (ret) {
725 release_mem_region(uport->mapbase, DUART_CHANREG_SPACING);
726 return ret;
727 }
728 return 0;
729}
730
731static void sbd_config_port(struct uart_port *uport, int flags)
732{
733 struct sbd_port *sport = to_sport(uport);
734
735 if (flags & UART_CONFIG_TYPE) {
736 if (sbd_request_port(uport))
737 return;
738
739 uport->type = PORT_SB1250_DUART;
740
741 sbd_init_port(sport);
742 }
743}
744
745static int sbd_verify_port(struct uart_port *uport, struct serial_struct *ser)
746{
747 int ret = 0;
748
749 if (ser->type != PORT_UNKNOWN && ser->type != PORT_SB1250_DUART)
750 ret = -EINVAL;
751 if (ser->irq != uport->irq)
752 ret = -EINVAL;
753 if (ser->baud_base != uport->uartclk / 16)
754 ret = -EINVAL;
755 return ret;
756}
757
758
86d0004a 759static const struct uart_ops sbd_ops = {
b45d5279
MR		 760 .tx_empty = sbd_tx_empty,
761 .set_mctrl = sbd_set_mctrl,
762 .get_mctrl = sbd_get_mctrl,
763 .stop_tx = sbd_stop_tx,
764 .start_tx = sbd_start_tx,
765 .stop_rx = sbd_stop_rx,
766 .enable_ms = sbd_enable_ms,
767 .break_ctl = sbd_break_ctl,
768 .startup = sbd_startup,
769 .shutdown = sbd_shutdown,
770 .set_termios = sbd_set_termios,
771 .type = sbd_type,
772 .release_port = sbd_release_port,
773 .request_port = sbd_request_port,
774 .config_port = sbd_config_port,
775 .verify_port = sbd_verify_port,
776};
777
778/* Initialize SB1250 DUART port structures. */
779static void __init sbd_probe_duarts(void)
780{
781 static int probed;
782 int chip, side;
783 int max_lines, line;
784
785 if (probed)
786 return;
787
788 /* Set the number of available units based on the SOC type. */
789 switch (soc_type) {
790 case K_SYS_SOC_TYPE_BCM1x55:
791 case K_SYS_SOC_TYPE_BCM1x80:
792 max_lines = 4;
793 break;
794 default:
795 /* Assume at least two serial ports at the normal address. */
796 max_lines = 2;
797 break;
798 }
799
800 probed = 1;
801
802 for (chip = 0, line = 0; chip < DUART_MAX_CHIP && line < max_lines;
803 chip++) {
804 sbd_duarts[chip].mapctrl = SBD_CTRLREGS(line);
805
806 for (side = 0; side < DUART_MAX_SIDE && line < max_lines;
807 side++, line++) {
808 struct sbd_port *sport = &sbd_duarts[chip].sport[side];
809 struct uart_port *uport = &sport->port;
810
811 sport->duart = &sbd_duarts[chip];
812
813 uport->irq = SBD_INT(line);
814 uport->uartclk = 100000000 / 20 * 16;
815 uport->fifosize = 16;
816 uport->iotype = UPIO_MEM;
817 uport->flags = UPF_BOOT_AUTOCONF;
818 uport->ops = &sbd_ops;
819 uport->line = line;
820 uport->mapbase = SBD_CHANREGS(line);
821 }
822 }
823}
824
825
826#ifdef CONFIG_SERIAL_SB1250_DUART_CONSOLE
827/*
828 * Serial console stuff. Very basic, polling driver for doing serial
ac751efa 829 * console output. The console_lock is held by the caller, so we
b45d5279
MR		 830 * shouldn't be interrupted for more console activity.
831 */
832static void sbd_console_putchar(struct uart_port *uport, int ch)
833{
834 struct sbd_port *sport = to_sport(uport);
835
836 sbd_transmit_drain(sport);
837 write_sbdchn(sport, R_DUART_TX_HOLD, ch);
838}
839
840static void sbd_console_write(struct console *co, const char *s,
841 unsigned int count)
842{
843 int chip = co->index / DUART_MAX_SIDE;
844 int side = co->index % DUART_MAX_SIDE;
845 struct sbd_port *sport = &sbd_duarts[chip].sport[side];
846 struct uart_port *uport = &sport->port;
847 unsigned long flags;
848 unsigned int mask;
849
850 /* Disable transmit interrupts and enable the transmitter. */
851 spin_lock_irqsave(&uport->lock, flags);
852 mask = read_sbdshr(sport, R_DUART_IMRREG((uport->line) % 2));
853 write_sbdshr(sport, R_DUART_IMRREG((uport->line) % 2),
854 mask & ~M_DUART_IMR_TX);
855 write_sbdchn(sport, R_DUART_CMD, M_DUART_TX_EN);
856 spin_unlock_irqrestore(&uport->lock, flags);
857
858 uart_console_write(&sport->port, s, count, sbd_console_putchar);
859
860 /* Restore transmit interrupts and the transmitter enable. */
861 spin_lock_irqsave(&uport->lock, flags);
862 sbd_line_drain(sport);
863 if (sport->tx_stopped)
864 write_sbdchn(sport, R_DUART_CMD, M_DUART_TX_DIS);
865 write_sbdshr(sport, R_DUART_IMRREG((uport->line) % 2), mask);
866 spin_unlock_irqrestore(&uport->lock, flags);
867}
868
869static int __init sbd_console_setup(struct console *co, char *options)
870{
871 int chip = co->index / DUART_MAX_SIDE;
872 int side = co->index % DUART_MAX_SIDE;
873 struct sbd_port *sport = &sbd_duarts[chip].sport[side];
874 struct uart_port *uport = &sport->port;
875 int baud = 115200;
876 int bits = 8;
877 int parity = 'n';
878 int flow = 'n';
879 int ret;
880
881 if (!sport->duart)
882 return -ENXIO;
883
884 ret = sbd_map_port(uport);
885 if (ret)
886 return ret;
887
888 sbd_init_port(sport);
889
890 if (options)
891 uart_parse_options(options, &baud, &parity, &bits, &flow);
892 return uart_set_options(uport, co, baud, parity, bits, flow);
893}
894
895static struct uart_driver sbd_reg;
896static struct console sbd_console = {
897 .name = "duart",
898 .write = sbd_console_write,
899 .device = uart_console_device,
900 .setup = sbd_console_setup,
901 .flags = CON_PRINTBUFFER,
902 .index = -1,
903 .data = &sbd_reg
904};
905
906static int __init sbd_serial_console_init(void)
907{
908 sbd_probe_duarts();
909 register_console(&sbd_console);
910
911 return 0;
912}
913
914console_initcall(sbd_serial_console_init);
915
916#define SERIAL_SB1250_DUART_CONSOLE &sbd_console
917#else
918#define SERIAL_SB1250_DUART_CONSOLE NULL
919#endif /* CONFIG_SERIAL_SB1250_DUART_CONSOLE */
920
921
922static struct uart_driver sbd_reg = {
923 .owner = THIS_MODULE,
4feead71 924 .driver_name = "sb1250_duart",
b45d5279
MR		 925 .dev_name = "duart",
926 .major = TTY_MAJOR,
927 .minor = SB1250_DUART_MINOR_BASE,
928 .nr = DUART_MAX_CHIP * DUART_MAX_SIDE,
929 .cons = SERIAL_SB1250_DUART_CONSOLE,
930};
931
932/* Set up the driver and register it. */
933static int __init sbd_init(void)
934{
935 int i, ret;
936
937 sbd_probe_duarts();
938
939 ret = uart_register_driver(&sbd_reg);
940 if (ret)
941 return ret;
942
943 for (i = 0; i < DUART_MAX_CHIP * DUART_MAX_SIDE; i++) {
944 struct sbd_duart *duart = &sbd_duarts[i / DUART_MAX_SIDE];
945 struct sbd_port *sport = &duart->sport[i % DUART_MAX_SIDE];
946 struct uart_port *uport = &sport->port;
947
948 if (sport->duart)
949 uart_add_one_port(&sbd_reg, uport);
950 }
951
952 return 0;
953}
954
955/* Unload the driver. Unregister stuff, get ready to go away. */
956static void __exit sbd_exit(void)
957{
958 int i;
959
960 for (i = DUART_MAX_CHIP * DUART_MAX_SIDE - 1; i >= 0; i--) {
961 struct sbd_duart *duart = &sbd_duarts[i / DUART_MAX_SIDE];
962 struct sbd_port *sport = &duart->sport[i % DUART_MAX_SIDE];
963 struct uart_port *uport = &sport->port;
964
965 if (sport->duart)
966 uart_remove_one_port(&sbd_reg, uport);
967 }
968
969 uart_unregister_driver(&sbd_reg);
970}
971
972module_init(sbd_init);
973module_exit(sbd_exit);
Linux 6.x block layer and io_uring tree(s)