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serial: samsung: remove unused 'irq' parameter
[linux-2.6-block.git] / drivers / tty / serial / samsung.c
CommitLineData
99edb3d1 1/*
b497549a
BD		 2 * Driver core for Samsung SoC onboard UARTs.
3 *
ccae941e 4 * Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics
b497549a
BD		 5 * http://armlinux.simtec.co.uk/
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12/* Hote on 2410 error handling
13 *
14 * The s3c2410 manual has a love/hate affair with the contents of the
15 * UERSTAT register in the UART blocks, and keeps marking some of the
16 * error bits as reserved. Having checked with the s3c2410x01,
17 * it copes with BREAKs properly, so I am happy to ignore the RESERVED
18 * feature from the latter versions of the manual.
19 *
20 * If it becomes aparrent that latter versions of the 2410 remove these
21 * bits, then action will have to be taken to differentiate the versions
22 * and change the policy on BREAK
23 *
24 * BJD, 04-Nov-2004
25*/
26
27#if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
28#define SUPPORT_SYSRQ
29#endif
30
62c37eed
RB		 31#include <linux/dmaengine.h>
32#include <linux/dma-mapping.h>
33#include <linux/slab.h>
b497549a
BD		 34#include <linux/module.h>
35#include <linux/ioport.h>
36#include <linux/io.h>
37#include <linux/platform_device.h>
38#include <linux/init.h>
39#include <linux/sysrq.h>
40#include <linux/console.h>
41#include <linux/tty.h>
42#include <linux/tty_flip.h>
43#include <linux/serial_core.h>
44#include <linux/serial.h>
9ee51f01 45#include <linux/serial_s3c.h>
b497549a
BD		 46#include <linux/delay.h>
47#include <linux/clk.h>
30555476 48#include <linux/cpufreq.h>
26c919e1 49#include <linux/of.h>
b497549a
BD		 50
51#include <asm/irq.h>
52
b497549a
BD		 53#include "samsung.h"
54
e4ac92df 55#if defined(CONFIG_SERIAL_SAMSUNG_DEBUG) && \
e4ac92df
JP		 56 !defined(MODULE)
57
58extern void printascii(const char *);
59
60__printf(1, 2)
61static void dbg(const char *fmt, ...)
62{
63 va_list va;
64 char buff[256];
65
66 va_start(va, fmt);
a859c8b2 67 vscnprintf(buff, sizeof(buff), fmt, va);
e4ac92df
JP		 68 va_end(va);
69
70 printascii(buff);
71}
72
73#else
74#define dbg(fmt, ...) do { if (0) no_printk(fmt, ##__VA_ARGS__); } while (0)
75#endif
76
b497549a
BD		 77/* UART name and device definitions */
78
79#define S3C24XX_SERIAL_NAME "ttySAC"
80#define S3C24XX_SERIAL_MAJOR 204
81#define S3C24XX_SERIAL_MINOR 64
82
29bef799
RB		 83#define S3C24XX_TX_PIO 1
84#define S3C24XX_TX_DMA 2
b543c301
RB		 85#define S3C24XX_RX_PIO 1
86#define S3C24XX_RX_DMA 2
b497549a
BD		 87/* macros to change one thing to another */
88
89#define tx_enabled(port) ((port)->unused[0])
90#define rx_enabled(port) ((port)->unused[1])
91
25985edc 92/* flag to ignore all characters coming in */
b497549a
BD		 93#define RXSTAT_DUMMY_READ (0x10000000)
94
95static inline struct s3c24xx_uart_port *to_ourport(struct uart_port *port)
96{
97 return container_of(port, struct s3c24xx_uart_port, port);
98}
99
100/* translate a port to the device name */
101
102static inline const char *s3c24xx_serial_portname(struct uart_port *port)
103{
104 return to_platform_device(port->dev)->name;
105}
106
107static int s3c24xx_serial_txempty_nofifo(struct uart_port *port)
108{
9303ac15 109 return rd_regl(port, S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE;
b497549a
BD		 110}
111
88bb4ea1
TA		 112/*
113 * s3c64xx and later SoC's include the interrupt mask and status registers in
114 * the controller itself, unlike the s3c24xx SoC's which have these registers
115 * in the interrupt controller. Check if the port type is s3c64xx or higher.
116 */
117static int s3c24xx_serial_has_interrupt_mask(struct uart_port *port)
118{
119 return to_ourport(port)->info->type == PORT_S3C6400;
120}
121
b497549a
BD		 122static void s3c24xx_serial_rx_enable(struct uart_port *port)
123{
124 unsigned long flags;
125 unsigned int ucon, ufcon;
126 int count = 10000;
127
128 spin_lock_irqsave(&port->lock, flags);
129
130 while (--count && !s3c24xx_serial_txempty_nofifo(port))
131 udelay(100);
132
133 ufcon = rd_regl(port, S3C2410_UFCON);
134 ufcon |= S3C2410_UFCON_RESETRX;
135 wr_regl(port, S3C2410_UFCON, ufcon);
136
137 ucon = rd_regl(port, S3C2410_UCON);
138 ucon |= S3C2410_UCON_RXIRQMODE;
139 wr_regl(port, S3C2410_UCON, ucon);
140
141 rx_enabled(port) = 1;
142 spin_unlock_irqrestore(&port->lock, flags);
143}
144
145static void s3c24xx_serial_rx_disable(struct uart_port *port)
146{
147 unsigned long flags;
148 unsigned int ucon;
149
150 spin_lock_irqsave(&port->lock, flags);
151
152 ucon = rd_regl(port, S3C2410_UCON);
153 ucon &= ~S3C2410_UCON_RXIRQMODE;
154 wr_regl(port, S3C2410_UCON, ucon);
155
156 rx_enabled(port) = 0;
157 spin_unlock_irqrestore(&port->lock, flags);
158}
159
160static void s3c24xx_serial_stop_tx(struct uart_port *port)
161{
b73c289c 162 struct s3c24xx_uart_port *ourport = to_ourport(port);
29bef799
RB		 163 struct s3c24xx_uart_dma *dma = ourport->dma;
164 struct circ_buf *xmit = &port->state->xmit;
165 struct dma_tx_state state;
166 int count;
b73c289c 167
29bef799
RB		 168 if (!tx_enabled(port))
169 return;
170
171 if (s3c24xx_serial_has_interrupt_mask(port))
172 __set_bit(S3C64XX_UINTM_TXD,
173 portaddrl(port, S3C64XX_UINTM));
174 else
175 disable_irq_nosync(ourport->tx_irq);
176
177 if (dma && dma->tx_chan && ourport->tx_in_progress == S3C24XX_TX_DMA) {
178 dmaengine_pause(dma->tx_chan);
179 dmaengine_tx_status(dma->tx_chan, dma->tx_cookie, &state);
180 dmaengine_terminate_all(dma->tx_chan);
181 dma_sync_single_for_cpu(ourport->port.dev,
182 dma->tx_transfer_addr, dma->tx_size, DMA_TO_DEVICE);
183 async_tx_ack(dma->tx_desc);
184 count = dma->tx_bytes_requested - state.residue;
185 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
186 port->icount.tx += count;
b497549a 187 }
29bef799
RB		 188
189 tx_enabled(port) = 0;
190 ourport->tx_in_progress = 0;
191
192 if (port->flags & UPF_CONS_FLOW)
193 s3c24xx_serial_rx_enable(port);
194
195 ourport->tx_mode = 0;
196}
197
198static void s3c24xx_serial_start_next_tx(struct s3c24xx_uart_port *ourport);
199
200static void s3c24xx_serial_tx_dma_complete(void *args)
201{
202 struct s3c24xx_uart_port *ourport = args;
203 struct uart_port *port = &ourport->port;
204 struct circ_buf *xmit = &port->state->xmit;
205 struct s3c24xx_uart_dma *dma = ourport->dma;
206 struct dma_tx_state state;
207 unsigned long flags;
208 int count;
209
210
211 dmaengine_tx_status(dma->tx_chan, dma->tx_cookie, &state);
212 count = dma->tx_bytes_requested - state.residue;
213 async_tx_ack(dma->tx_desc);
214
215 dma_sync_single_for_cpu(ourport->port.dev, dma->tx_transfer_addr,
216 dma->tx_size, DMA_TO_DEVICE);
217
218 spin_lock_irqsave(&port->lock, flags);
219
220 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
221 port->icount.tx += count;
222 ourport->tx_in_progress = 0;
223
224 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
225 uart_write_wakeup(port);
226
227 s3c24xx_serial_start_next_tx(ourport);
228 spin_unlock_irqrestore(&port->lock, flags);
229}
230
231static void enable_tx_dma(struct s3c24xx_uart_port *ourport)
232{
233 struct uart_port *port = &ourport->port;
234 u32 ucon;
235
236 /* Mask Tx interrupt */
237 if (s3c24xx_serial_has_interrupt_mask(port))
238 __set_bit(S3C64XX_UINTM_TXD,
239 portaddrl(port, S3C64XX_UINTM));
240 else
241 disable_irq_nosync(ourport->tx_irq);
242
243 /* Enable tx dma mode */
244 ucon = rd_regl(port, S3C2410_UCON);
245 ucon &= ~(S3C64XX_UCON_TXBURST_MASK | S3C64XX_UCON_TXMODE_MASK);
246 ucon |= (dma_get_cache_alignment() >= 16) ?
247 S3C64XX_UCON_TXBURST_16 : S3C64XX_UCON_TXBURST_1;
248 ucon |= S3C64XX_UCON_TXMODE_DMA;
249 wr_regl(port, S3C2410_UCON, ucon);
250
251 ourport->tx_mode = S3C24XX_TX_DMA;
252}
253
254static void enable_tx_pio(struct s3c24xx_uart_port *ourport)
255{
256 struct uart_port *port = &ourport->port;
257 u32 ucon, ufcon;
258
259 /* Set ufcon txtrig */
260 ourport->tx_in_progress = S3C24XX_TX_PIO;
261 ufcon = rd_regl(port, S3C2410_UFCON);
262 wr_regl(port, S3C2410_UFCON, ufcon);
263
264 /* Enable tx pio mode */
265 ucon = rd_regl(port, S3C2410_UCON);
266 ucon &= ~(S3C64XX_UCON_TXMODE_MASK);
267 ucon |= S3C64XX_UCON_TXMODE_CPU;
268 wr_regl(port, S3C2410_UCON, ucon);
269
270 /* Unmask Tx interrupt */
271 if (s3c24xx_serial_has_interrupt_mask(port))
272 __clear_bit(S3C64XX_UINTM_TXD,
273 portaddrl(port, S3C64XX_UINTM));
274 else
275 enable_irq(ourport->tx_irq);
276
277 ourport->tx_mode = S3C24XX_TX_PIO;
278}
279
280static void s3c24xx_serial_start_tx_pio(struct s3c24xx_uart_port *ourport)
281{
282 if (ourport->tx_mode != S3C24XX_TX_PIO)
283 enable_tx_pio(ourport);
b497549a
BD		 284}
285
29bef799
RB		 286static int s3c24xx_serial_start_tx_dma(struct s3c24xx_uart_port *ourport,
287 unsigned int count)
288{
289 struct uart_port *port = &ourport->port;
290 struct circ_buf *xmit = &port->state->xmit;
291 struct s3c24xx_uart_dma *dma = ourport->dma;
292
293
294 if (ourport->tx_mode != S3C24XX_TX_DMA)
295 enable_tx_dma(ourport);
296
29bef799
RB		 297 dma->tx_size = count & ~(dma_get_cache_alignment() - 1);
298 dma->tx_transfer_addr = dma->tx_addr + xmit->tail;
299
300 dma_sync_single_for_device(ourport->port.dev, dma->tx_transfer_addr,
301 dma->tx_size, DMA_TO_DEVICE);
302
303 dma->tx_desc = dmaengine_prep_slave_single(dma->tx_chan,
304 dma->tx_transfer_addr, dma->tx_size,
305 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
306 if (!dma->tx_desc) {
307 dev_err(ourport->port.dev, "Unable to get desc for Tx\n");
308 return -EIO;
309 }
310
311 dma->tx_desc->callback = s3c24xx_serial_tx_dma_complete;
312 dma->tx_desc->callback_param = ourport;
313 dma->tx_bytes_requested = dma->tx_size;
314
315 ourport->tx_in_progress = S3C24XX_TX_DMA;
316 dma->tx_cookie = dmaengine_submit(dma->tx_desc);
317 dma_async_issue_pending(dma->tx_chan);
318 return 0;
319}
320
321static void s3c24xx_serial_start_next_tx(struct s3c24xx_uart_port *ourport)
322{
323 struct uart_port *port = &ourport->port;
324 struct circ_buf *xmit = &port->state->xmit;
325 unsigned long count;
326
327 /* Get data size up to the end of buffer */
328 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
329
330 if (!count) {
331 s3c24xx_serial_stop_tx(port);
332 return;
333 }
334
81ccb2a6 335 if (!ourport->dma || !ourport->dma->tx_chan ||
736cd79f
RB		 336 count < ourport->min_dma_size ||
337 xmit->tail & (dma_get_cache_alignment() - 1))
29bef799
RB		 338 s3c24xx_serial_start_tx_pio(ourport);
339 else
340 s3c24xx_serial_start_tx_dma(ourport, count);
341}
342
75781979 343static void s3c24xx_serial_start_tx(struct uart_port *port)
b497549a 344{
b73c289c 345 struct s3c24xx_uart_port *ourport = to_ourport(port);
29bef799 346 struct circ_buf *xmit = &port->state->xmit;
b73c289c 347
b497549a
BD		 348 if (!tx_enabled(port)) {
349 if (port->flags & UPF_CONS_FLOW)
350 s3c24xx_serial_rx_disable(port);
351
b497549a 352 tx_enabled(port) = 1;
ba019a3e 353 if (!ourport->dma || !ourport->dma->tx_chan)
29bef799 354 s3c24xx_serial_start_tx_pio(ourport);
29bef799
RB		 355 }
356
357 if (ourport->dma && ourport->dma->tx_chan) {
358 if (!uart_circ_empty(xmit) && !ourport->tx_in_progress)
359 s3c24xx_serial_start_next_tx(ourport);
b497549a
BD		 360 }
361}
362
b543c301
RB		 363static void s3c24xx_uart_copy_rx_to_tty(struct s3c24xx_uart_port *ourport,
364 struct tty_port *tty, int count)
365{
366 struct s3c24xx_uart_dma *dma = ourport->dma;
367 int copied;
368
369 if (!count)
370 return;
371
372 dma_sync_single_for_cpu(ourport->port.dev, dma->rx_addr,
373 dma->rx_size, DMA_FROM_DEVICE);
374
375 ourport->port.icount.rx += count;
376 if (!tty) {
377 dev_err(ourport->port.dev, "No tty port\n");
378 return;
379 }
380 copied = tty_insert_flip_string(tty,
381 ((unsigned char *)(ourport->dma->rx_buf)), count);
382 if (copied != count) {
383 WARN_ON(1);
384 dev_err(ourport->port.dev, "RxData copy to tty layer failed\n");
385 }
386}
387
388static int s3c24xx_serial_rx_fifocnt(struct s3c24xx_uart_port *ourport,
389 unsigned long ufstat);
390
391static void uart_rx_drain_fifo(struct s3c24xx_uart_port *ourport)
392{
393 struct uart_port *port = &ourport->port;
394 struct tty_port *tty = &port->state->port;
395 unsigned int ch, ufstat;
396 unsigned int count;
397
398 ufstat = rd_regl(port, S3C2410_UFSTAT);
399 count = s3c24xx_serial_rx_fifocnt(ourport, ufstat);
400
401 if (!count)
402 return;
403
404 while (count-- > 0) {
405 ch = rd_regb(port, S3C2410_URXH);
406
407 ourport->port.icount.rx++;
408 tty_insert_flip_char(tty, ch, TTY_NORMAL);
409 }
410
411 tty_flip_buffer_push(tty);
412}
413
b497549a
BD		 414static void s3c24xx_serial_stop_rx(struct uart_port *port)
415{
b73c289c 416 struct s3c24xx_uart_port *ourport = to_ourport(port);
b543c301
RB		 417 struct s3c24xx_uart_dma *dma = ourport->dma;
418 struct tty_port *t = &port->state->port;
419 struct dma_tx_state state;
420 enum dma_status dma_status;
421 unsigned int received;
b73c289c 422
b497549a
BD		 423 if (rx_enabled(port)) {
424 dbg("s3c24xx_serial_stop_rx: port=%p\n", port);
88bb4ea1
TA		 425 if (s3c24xx_serial_has_interrupt_mask(port))
426 __set_bit(S3C64XX_UINTM_RXD,
427 portaddrl(port, S3C64XX_UINTM));
428 else
429 disable_irq_nosync(ourport->rx_irq);
b497549a
BD		 430 rx_enabled(port) = 0;
431 }
b543c301
RB		 432 if (dma && dma->rx_chan) {
433 dmaengine_pause(dma->tx_chan);
434 dma_status = dmaengine_tx_status(dma->rx_chan,
435 dma->rx_cookie, &state);
436 if (dma_status == DMA_IN_PROGRESS ||
437 dma_status == DMA_PAUSED) {
438 received = dma->rx_bytes_requested - state.residue;
439 dmaengine_terminate_all(dma->rx_chan);
440 s3c24xx_uart_copy_rx_to_tty(ourport, t, received);
441 }
442 }
b497549a
BD		 443}
444
ef4aca70
RB		 445static inline struct s3c24xx_uart_info
446 *s3c24xx_port_to_info(struct uart_port *port)
b497549a
BD		 447{
448 return to_ourport(port)->info;
449}
450
ef4aca70
RB		 451static inline struct s3c2410_uartcfg
452 *s3c24xx_port_to_cfg(struct uart_port *port)
b497549a 453{
4d84e970
TA		 454 struct s3c24xx_uart_port *ourport;
455
b497549a
BD		 456 if (port->dev == NULL)
457 return NULL;
458
4d84e970
TA		 459 ourport = container_of(port, struct s3c24xx_uart_port, port);
460 return ourport->cfg;
b497549a
BD		 461}
462
463static int s3c24xx_serial_rx_fifocnt(struct s3c24xx_uart_port *ourport,
464 unsigned long ufstat)
465{
466 struct s3c24xx_uart_info *info = ourport->info;
467
468 if (ufstat & info->rx_fifofull)
da121506 469 return ourport->port.fifosize;
b497549a
BD		 470
471 return (ufstat & info->rx_fifomask) >> info->rx_fifoshift;
472}
473
b543c301
RB		 474static void s3c64xx_start_rx_dma(struct s3c24xx_uart_port *ourport);
475static void s3c24xx_serial_rx_dma_complete(void *args)
476{
477 struct s3c24xx_uart_port *ourport = args;
478 struct uart_port *port = &ourport->port;
479
480 struct s3c24xx_uart_dma *dma = ourport->dma;
481 struct tty_port *t = &port->state->port;
482 struct tty_struct *tty = tty_port_tty_get(&ourport->port.state->port);
483
484 struct dma_tx_state state;
485 unsigned long flags;
486 int received;
487
488 dmaengine_tx_status(dma->rx_chan, dma->rx_cookie, &state);
489 received = dma->rx_bytes_requested - state.residue;
490 async_tx_ack(dma->rx_desc);
491
492 spin_lock_irqsave(&port->lock, flags);
493
494 if (received)
495 s3c24xx_uart_copy_rx_to_tty(ourport, t, received);
496
497 if (tty) {
498 tty_flip_buffer_push(t);
499 tty_kref_put(tty);
500 }
501
502 s3c64xx_start_rx_dma(ourport);
503
504 spin_unlock_irqrestore(&port->lock, flags);
505}
506
507static void s3c64xx_start_rx_dma(struct s3c24xx_uart_port *ourport)
508{
509 struct s3c24xx_uart_dma *dma = ourport->dma;
510
511 dma_sync_single_for_device(ourport->port.dev, dma->rx_addr,
512 dma->rx_size, DMA_FROM_DEVICE);
513
514 dma->rx_desc = dmaengine_prep_slave_single(dma->rx_chan,
515 dma->rx_addr, dma->rx_size, DMA_DEV_TO_MEM,
516 DMA_PREP_INTERRUPT);
517 if (!dma->rx_desc) {
518 dev_err(ourport->port.dev, "Unable to get desc for Rx\n");
519 return;
520 }
521
522 dma->rx_desc->callback = s3c24xx_serial_rx_dma_complete;
523 dma->rx_desc->callback_param = ourport;
524 dma->rx_bytes_requested = dma->rx_size;
525
526 dma->rx_cookie = dmaengine_submit(dma->rx_desc);
527 dma_async_issue_pending(dma->rx_chan);
528}
b497549a
BD		 529
530/* ? - where has parity gone?? */
531#define S3C2410_UERSTAT_PARITY (0x1000)
532
b543c301
RB		 533static void enable_rx_dma(struct s3c24xx_uart_port *ourport)
534{
535 struct uart_port *port = &ourport->port;
536 unsigned int ucon;
537
538 /* set Rx mode to DMA mode */
539 ucon = rd_regl(port, S3C2410_UCON);
540 ucon &= ~(S3C64XX_UCON_RXBURST_MASK |
541 S3C64XX_UCON_TIMEOUT_MASK |
542 S3C64XX_UCON_EMPTYINT_EN |
543 S3C64XX_UCON_DMASUS_EN |
544 S3C64XX_UCON_TIMEOUT_EN |
545 S3C64XX_UCON_RXMODE_MASK);
546 ucon |= S3C64XX_UCON_RXBURST_16 |
547 0xf << S3C64XX_UCON_TIMEOUT_SHIFT |
548 S3C64XX_UCON_EMPTYINT_EN |
549 S3C64XX_UCON_TIMEOUT_EN |
550 S3C64XX_UCON_RXMODE_DMA;
551 wr_regl(port, S3C2410_UCON, ucon);
552
553 ourport->rx_mode = S3C24XX_RX_DMA;
554}
555
556static void enable_rx_pio(struct s3c24xx_uart_port *ourport)
557{
558 struct uart_port *port = &ourport->port;
559 unsigned int ucon;
560
561 /* set Rx mode to DMA mode */
562 ucon = rd_regl(port, S3C2410_UCON);
563 ucon &= ~(S3C64XX_UCON_TIMEOUT_MASK |
564 S3C64XX_UCON_EMPTYINT_EN |
565 S3C64XX_UCON_DMASUS_EN |
566 S3C64XX_UCON_TIMEOUT_EN |
567 S3C64XX_UCON_RXMODE_MASK);
568 ucon |= 0xf << S3C64XX_UCON_TIMEOUT_SHIFT |
569 S3C64XX_UCON_TIMEOUT_EN |
570 S3C64XX_UCON_RXMODE_CPU;
571 wr_regl(port, S3C2410_UCON, ucon);
572
573 ourport->rx_mode = S3C24XX_RX_PIO;
574}
575
e4678afe 576static irqreturn_t s3c24xx_serial_rx_chars_dma(void *dev_id)
b543c301
RB		 577{
578 unsigned int utrstat, ufstat, received;
579 struct s3c24xx_uart_port *ourport = dev_id;
580 struct uart_port *port = &ourport->port;
581 struct s3c24xx_uart_dma *dma = ourport->dma;
582 struct tty_struct *tty = tty_port_tty_get(&ourport->port.state->port);
583 struct tty_port *t = &port->state->port;
584 unsigned long flags;
585 struct dma_tx_state state;
586
587 utrstat = rd_regl(port, S3C2410_UTRSTAT);
588 ufstat = rd_regl(port, S3C2410_UFSTAT);
589
590 spin_lock_irqsave(&port->lock, flags);
591
592 if (!(utrstat & S3C2410_UTRSTAT_TIMEOUT)) {
593 s3c64xx_start_rx_dma(ourport);
594 if (ourport->rx_mode == S3C24XX_RX_PIO)
595 enable_rx_dma(ourport);
596 goto finish;
597 }
598
599 if (ourport->rx_mode == S3C24XX_RX_DMA) {
600 dmaengine_pause(dma->rx_chan);
601 dmaengine_tx_status(dma->rx_chan, dma->rx_cookie, &state);
602 dmaengine_terminate_all(dma->rx_chan);
603 received = dma->rx_bytes_requested - state.residue;
604 s3c24xx_uart_copy_rx_to_tty(ourport, t, received);
605
606 enable_rx_pio(ourport);
607 }
608
609 uart_rx_drain_fifo(ourport);
610
611 if (tty) {
612 tty_flip_buffer_push(t);
613 tty_kref_put(tty);
614 }
615
616 wr_regl(port, S3C2410_UTRSTAT, S3C2410_UTRSTAT_TIMEOUT);
617
618finish:
619 spin_unlock_irqrestore(&port->lock, flags);
620
621 return IRQ_HANDLED;
622}
623
e4678afe 624static irqreturn_t s3c24xx_serial_rx_chars_pio(void *dev_id)
b497549a
BD		 625{
626 struct s3c24xx_uart_port *ourport = dev_id;
627 struct uart_port *port = &ourport->port;
b497549a 628 unsigned int ufcon, ch, flag, ufstat, uerstat;
c15c3747 629 unsigned long flags;
57850a50 630 int max_count = port->fifosize;
b497549a 631
c15c3747
TA		 632 spin_lock_irqsave(&port->lock, flags);
633
b497549a
BD		 634 while (max_count-- > 0) {
635 ufcon = rd_regl(port, S3C2410_UFCON);
636 ufstat = rd_regl(port, S3C2410_UFSTAT);
637
638 if (s3c24xx_serial_rx_fifocnt(ourport, ufstat) == 0)
639 break;
640
641 uerstat = rd_regl(port, S3C2410_UERSTAT);
642 ch = rd_regb(port, S3C2410_URXH);
643
644 if (port->flags & UPF_CONS_FLOW) {
645 int txe = s3c24xx_serial_txempty_nofifo(port);
646
647 if (rx_enabled(port)) {
648 if (!txe) {
649 rx_enabled(port) = 0;
650 continue;
651 }
652 } else {
653 if (txe) {
654 ufcon |= S3C2410_UFCON_RESETRX;
655 wr_regl(port, S3C2410_UFCON, ufcon);
656 rx_enabled(port) = 1;
f5693ea2
VK		 657 spin_unlock_irqrestore(&port->lock,
658 flags);
b497549a
BD		 659 goto out;
660 }
661 continue;
662 }
663 }
664
665 /* insert the character into the buffer */
666
667 flag = TTY_NORMAL;
668 port->icount.rx++;
669
670 if (unlikely(uerstat & S3C2410_UERSTAT_ANY)) {
671 dbg("rxerr: port ch=0x%02x, rxs=0x%08x\n",
672 ch, uerstat);
673
674 /* check for break */
675 if (uerstat & S3C2410_UERSTAT_BREAK) {
676 dbg("break!\n");
677 port->icount.brk++;
678 if (uart_handle_break(port))
9303ac15 679 goto ignore_char;
b497549a
BD		 680 }
681
682 if (uerstat & S3C2410_UERSTAT_FRAME)
683 port->icount.frame++;
684 if (uerstat & S3C2410_UERSTAT_OVERRUN)
685 port->icount.overrun++;
686
687 uerstat &= port->read_status_mask;
688
689 if (uerstat & S3C2410_UERSTAT_BREAK)
690 flag = TTY_BREAK;
691 else if (uerstat & S3C2410_UERSTAT_PARITY)
692 flag = TTY_PARITY;
693 else if (uerstat & (S3C2410_UERSTAT_FRAME |
694 S3C2410_UERSTAT_OVERRUN))
695 flag = TTY_FRAME;
696 }
697
698 if (uart_handle_sysrq_char(port, ch))
699 goto ignore_char;
700
701 uart_insert_char(port, uerstat, S3C2410_UERSTAT_OVERRUN,
702 ch, flag);
703
ef4aca70 704ignore_char:
b497549a
BD		 705 continue;
706 }
f5693ea2
VK		 707
708 spin_unlock_irqrestore(&port->lock, flags);
2e124b4a 709 tty_flip_buffer_push(&port->state->port);
b497549a 710
ef4aca70 711out:
b497549a
BD		 712 return IRQ_HANDLED;
713}
714
b543c301
RB		 715
716static irqreturn_t s3c24xx_serial_rx_chars(int irq, void *dev_id)
717{
718 struct s3c24xx_uart_port *ourport = dev_id;
719
720 if (ourport->dma && ourport->dma->rx_chan)
e4678afe
RB		 721 return s3c24xx_serial_rx_chars_dma(dev_id);
722 return s3c24xx_serial_rx_chars_pio(dev_id);
b543c301
RB		 723}
724
b497549a
BD		 725static irqreturn_t s3c24xx_serial_tx_chars(int irq, void *id)
726{
727 struct s3c24xx_uart_port *ourport = id;
728 struct uart_port *port = &ourport->port;
ebd2c8f6 729 struct circ_buf *xmit = &port->state->xmit;
c15c3747 730 unsigned long flags;
736cd79f 731 int count, dma_count = 0;
b497549a 732
c15c3747
TA		 733 spin_lock_irqsave(&port->lock, flags);
734
29bef799
RB		 735 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
736
81ccb2a6
MS		 737 if (ourport->dma && ourport->dma->tx_chan &&
738 count >= ourport->min_dma_size) {
736cd79f
RB		 739 int align = dma_get_cache_alignment() -
740 (xmit->tail & (dma_get_cache_alignment() - 1));
741 if (count-align >= ourport->min_dma_size) {
742 dma_count = count-align;
743 count = align;
744 }
29bef799
RB		 745 }
746
b497549a
BD		 747 if (port->x_char) {
748 wr_regb(port, S3C2410_UTXH, port->x_char);
749 port->icount.tx++;
750 port->x_char = 0;
751 goto out;
752 }
753
25985edc 754 /* if there isn't anything more to transmit, or the uart is now
b497549a
BD		 755 * stopped, disable the uart and exit
756 */
757
758 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
759 s3c24xx_serial_stop_tx(port);
760 goto out;
761 }
762
763 /* try and drain the buffer... */
764
736cd79f
RB		 765 if (count > port->fifosize) {
766 count = port->fifosize;
767 dma_count = 0;
768 }
769
770 while (!uart_circ_empty(xmit) && count > 0) {
b497549a
BD		 771 if (rd_regl(port, S3C2410_UFSTAT) & ourport->info->tx_fifofull)
772 break;
773
774 wr_regb(port, S3C2410_UTXH, xmit->buf[xmit->tail]);
775 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
776 port->icount.tx++;
736cd79f
RB		 777 count--;
778 }
779
780 if (!count && dma_count) {
781 s3c24xx_serial_start_tx_dma(ourport, dma_count);
782 goto out;
b497549a
BD		 783 }
784
c15c3747
TA		 785 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) {
786 spin_unlock(&port->lock);
b497549a 787 uart_write_wakeup(port);
c15c3747
TA		 788 spin_lock(&port->lock);
789 }
b497549a
BD		 790
791 if (uart_circ_empty(xmit))
792 s3c24xx_serial_stop_tx(port);
793
ef4aca70 794out:
c15c3747 795 spin_unlock_irqrestore(&port->lock, flags);
b497549a
BD		 796 return IRQ_HANDLED;
797}
798
88bb4ea1
TA		 799/* interrupt handler for s3c64xx and later SoC's.*/
800static irqreturn_t s3c64xx_serial_handle_irq(int irq, void *id)
801{
802 struct s3c24xx_uart_port *ourport = id;
803 struct uart_port *port = &ourport->port;
804 unsigned int pend = rd_regl(port, S3C64XX_UINTP);
88bb4ea1
TA		 805 irqreturn_t ret = IRQ_HANDLED;
806
88bb4ea1
TA		 807 if (pend & S3C64XX_UINTM_RXD_MSK) {
808 ret = s3c24xx_serial_rx_chars(irq, id);
809 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_RXD_MSK);
810 }
811 if (pend & S3C64XX_UINTM_TXD_MSK) {
812 ret = s3c24xx_serial_tx_chars(irq, id);
813 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_TXD_MSK);
814 }
88bb4ea1
TA		 815 return ret;
816}
817
b497549a
BD		 818static unsigned int s3c24xx_serial_tx_empty(struct uart_port *port)
819{
820 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
821 unsigned long ufstat = rd_regl(port, S3C2410_UFSTAT);
822 unsigned long ufcon = rd_regl(port, S3C2410_UFCON);
823
824 if (ufcon & S3C2410_UFCON_FIFOMODE) {
825 if ((ufstat & info->tx_fifomask) != 0 ||
826 (ufstat & info->tx_fifofull))
827 return 0;
828
829 return 1;
830 }
831
832 return s3c24xx_serial_txempty_nofifo(port);
833}
834
835/* no modem control lines */
836static unsigned int s3c24xx_serial_get_mctrl(struct uart_port *port)
837{
838 unsigned int umstat = rd_regb(port, S3C2410_UMSTAT);
839
840 if (umstat & S3C2410_UMSTAT_CTS)
841 return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
842 else
843 return TIOCM_CAR | TIOCM_DSR;
844}
845
846static void s3c24xx_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
847{
2d1e5a48
JMG		 848 unsigned int umcon = rd_regl(port, S3C2410_UMCON);
849
850 if (mctrl & TIOCM_RTS)
851 umcon |= S3C2410_UMCOM_RTS_LOW;
852 else
853 umcon &= ~S3C2410_UMCOM_RTS_LOW;
854
855 wr_regl(port, S3C2410_UMCON, umcon);
b497549a
BD		 856}
857
858static void s3c24xx_serial_break_ctl(struct uart_port *port, int break_state)
859{
860 unsigned long flags;
861 unsigned int ucon;
862
863 spin_lock_irqsave(&port->lock, flags);
864
865 ucon = rd_regl(port, S3C2410_UCON);
866
867 if (break_state)
868 ucon |= S3C2410_UCON_SBREAK;
869 else
870 ucon &= ~S3C2410_UCON_SBREAK;
871
872 wr_regl(port, S3C2410_UCON, ucon);
873
874 spin_unlock_irqrestore(&port->lock, flags);
875}
876
62c37eed
RB		 877static int s3c24xx_serial_request_dma(struct s3c24xx_uart_port *p)
878{
879 struct s3c24xx_uart_dma *dma = p->dma;
880 dma_cap_mask_t mask;
881 unsigned long flags;
882
883 /* Default slave configuration parameters */
884 dma->rx_conf.direction = DMA_DEV_TO_MEM;
885 dma->rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
886 dma->rx_conf.src_addr = p->port.mapbase + S3C2410_URXH;
887 dma->rx_conf.src_maxburst = 16;
888
889 dma->tx_conf.direction = DMA_MEM_TO_DEV;
890 dma->tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
891 dma->tx_conf.dst_addr = p->port.mapbase + S3C2410_UTXH;
892 if (dma_get_cache_alignment() >= 16)
893 dma->tx_conf.dst_maxburst = 16;
894 else
895 dma->tx_conf.dst_maxburst = 1;
896
897 dma_cap_zero(mask);
898 dma_cap_set(DMA_SLAVE, mask);
899
900 dma->rx_chan = dma_request_slave_channel_compat(mask, dma->fn,
901 dma->rx_param, p->port.dev, "rx");
902 if (!dma->rx_chan)
903 return -ENODEV;
904
905 dmaengine_slave_config(dma->rx_chan, &dma->rx_conf);
906
907 dma->tx_chan = dma_request_slave_channel_compat(mask, dma->fn,
908 dma->tx_param, p->port.dev, "tx");
909 if (!dma->tx_chan) {
910 dma_release_channel(dma->rx_chan);
911 return -ENODEV;
912 }
913
914 dmaengine_slave_config(dma->tx_chan, &dma->tx_conf);
915
916 /* RX buffer */
917 dma->rx_size = PAGE_SIZE;
918
919 dma->rx_buf = kmalloc(dma->rx_size, GFP_KERNEL);
920
921 if (!dma->rx_buf) {
922 dma_release_channel(dma->rx_chan);
923 dma_release_channel(dma->tx_chan);
924 return -ENOMEM;
925 }
926
927 dma->rx_addr = dma_map_single(dma->rx_chan->device->dev, dma->rx_buf,
928 dma->rx_size, DMA_FROM_DEVICE);
929
930 spin_lock_irqsave(&p->port.lock, flags);
931
932 /* TX buffer */
933 dma->tx_addr = dma_map_single(dma->tx_chan->device->dev,
934 p->port.state->xmit.buf,
935 UART_XMIT_SIZE, DMA_TO_DEVICE);
936
937 spin_unlock_irqrestore(&p->port.lock, flags);
938
939 return 0;
940}
941
942static void s3c24xx_serial_release_dma(struct s3c24xx_uart_port *p)
943{
944 struct s3c24xx_uart_dma *dma = p->dma;
945
946 if (dma->rx_chan) {
947 dmaengine_terminate_all(dma->rx_chan);
948 dma_unmap_single(dma->rx_chan->device->dev, dma->rx_addr,
949 dma->rx_size, DMA_FROM_DEVICE);
950 kfree(dma->rx_buf);
951 dma_release_channel(dma->rx_chan);
952 dma->rx_chan = NULL;
953 }
954
955 if (dma->tx_chan) {
956 dmaengine_terminate_all(dma->tx_chan);
957 dma_unmap_single(dma->tx_chan->device->dev, dma->tx_addr,
958 UART_XMIT_SIZE, DMA_TO_DEVICE);
959 dma_release_channel(dma->tx_chan);
960 dma->tx_chan = NULL;
961 }
962}
963
b497549a
BD		 964static void s3c24xx_serial_shutdown(struct uart_port *port)
965{
966 struct s3c24xx_uart_port *ourport = to_ourport(port);
967
968 if (ourport->tx_claimed) {
88bb4ea1
TA		 969 if (!s3c24xx_serial_has_interrupt_mask(port))
970 free_irq(ourport->tx_irq, ourport);
b497549a
BD		 971 tx_enabled(port) = 0;
972 ourport->tx_claimed = 0;
e91d863d 973 ourport->tx_mode = 0;
b497549a
BD		 974 }
975
976 if (ourport->rx_claimed) {
88bb4ea1
TA		 977 if (!s3c24xx_serial_has_interrupt_mask(port))
978 free_irq(ourport->rx_irq, ourport);
b497549a
BD		 979 ourport->rx_claimed = 0;
980 rx_enabled(port) = 0;
981 }
b497549a 982
88bb4ea1
TA		 983 /* Clear pending interrupts and mask all interrupts */
984 if (s3c24xx_serial_has_interrupt_mask(port)) {
b6ad2935
TF		 985 free_irq(port->irq, ourport);
986
88bb4ea1
TA		 987 wr_regl(port, S3C64XX_UINTP, 0xf);
988 wr_regl(port, S3C64XX_UINTM, 0xf);
989 }
62c37eed
RB		 990
991 if (ourport->dma)
992 s3c24xx_serial_release_dma(ourport);
993
29bef799 994 ourport->tx_in_progress = 0;
88bb4ea1 995}
b497549a
BD		 996
997static int s3c24xx_serial_startup(struct uart_port *port)
998{
999 struct s3c24xx_uart_port *ourport = to_ourport(port);
1000 int ret;
1001
e4ac92df
JP		 1002 dbg("s3c24xx_serial_startup: port=%p (%08llx,%p)\n",
1003 port, (unsigned long long)port->mapbase, port->membase);
b497549a
BD		 1004
1005 rx_enabled(port) = 1;
1006
b73c289c 1007 ret = request_irq(ourport->rx_irq, s3c24xx_serial_rx_chars, 0,
b497549a
BD		 1008 s3c24xx_serial_portname(port), ourport);
1009
1010 if (ret != 0) {
d20925e1 1011 dev_err(port->dev, "cannot get irq %d\n", ourport->rx_irq);
b497549a
BD		 1012 return ret;
1013 }
1014
1015 ourport->rx_claimed = 1;
1016
1017 dbg("requesting tx irq...\n");
1018
1019 tx_enabled(port) = 1;
1020
b73c289c 1021 ret = request_irq(ourport->tx_irq, s3c24xx_serial_tx_chars, 0,
b497549a
BD		 1022 s3c24xx_serial_portname(port), ourport);
1023
1024 if (ret) {
d20925e1 1025 dev_err(port->dev, "cannot get irq %d\n", ourport->tx_irq);
b497549a
BD		 1026 goto err;
1027 }
1028
1029 ourport->tx_claimed = 1;
1030
1031 dbg("s3c24xx_serial_startup ok\n");
1032
1033 /* the port reset code should have done the correct
1034 * register setup for the port controls */
1035
1036 return ret;
1037
ef4aca70 1038err:
b497549a
BD		 1039 s3c24xx_serial_shutdown(port);
1040 return ret;
1041}
1042
88bb4ea1
TA		 1043static int s3c64xx_serial_startup(struct uart_port *port)
1044{
1045 struct s3c24xx_uart_port *ourport = to_ourport(port);
b543c301
RB		 1046 unsigned long flags;
1047 unsigned int ufcon;
88bb4ea1
TA		 1048 int ret;
1049
e4ac92df
JP		 1050 dbg("s3c64xx_serial_startup: port=%p (%08llx,%p)\n",
1051 port, (unsigned long long)port->mapbase, port->membase);
88bb4ea1 1052
b6ad2935 1053 wr_regl(port, S3C64XX_UINTM, 0xf);
62c37eed
RB		 1054 if (ourport->dma) {
1055 ret = s3c24xx_serial_request_dma(ourport);
1056 if (ret < 0) {
1057 dev_warn(port->dev, "DMA request failed\n");
1058 return ret;
1059 }
1060 }
b6ad2935 1061
88bb4ea1
TA		 1062 ret = request_irq(port->irq, s3c64xx_serial_handle_irq, IRQF_SHARED,
1063 s3c24xx_serial_portname(port), ourport);
1064 if (ret) {
d20925e1 1065 dev_err(port->dev, "cannot get irq %d\n", port->irq);
88bb4ea1
TA		 1066 return ret;
1067 }
1068
1069 /* For compatibility with s3c24xx Soc's */
1070 rx_enabled(port) = 1;
1071 ourport->rx_claimed = 1;
1072 tx_enabled(port) = 0;
1073 ourport->tx_claimed = 1;
1074
29bef799
RB		 1075 spin_lock_irqsave(&port->lock, flags);
1076
1077 ufcon = rd_regl(port, S3C2410_UFCON);
31c6ba97
RB		 1078 ufcon |= S3C2410_UFCON_RESETRX | S5PV210_UFCON_RXTRIG8;
1079 if (!uart_console(port))
1080 ufcon |= S3C2410_UFCON_RESETTX;
29bef799
RB		 1081 wr_regl(port, S3C2410_UFCON, ufcon);
1082
1083 enable_rx_pio(ourport);
1084
1085 spin_unlock_irqrestore(&port->lock, flags);
1086
88bb4ea1
TA		 1087 /* Enable Rx Interrupt */
1088 __clear_bit(S3C64XX_UINTM_RXD, portaddrl(port, S3C64XX_UINTM));
29bef799 1089
88bb4ea1
TA		 1090 dbg("s3c64xx_serial_startup ok\n");
1091 return ret;
1092}
1093
b497549a
BD		 1094/* power power management control */
1095
1096static void s3c24xx_serial_pm(struct uart_port *port, unsigned int level,
1097 unsigned int old)
1098{
1099 struct s3c24xx_uart_port *ourport = to_ourport(port);
1ff383a4 1100 int timeout = 10000;
b497549a 1101
30555476
BD		 1102 ourport->pm_level = level;
1103
b497549a
BD		 1104 switch (level) {
1105 case 3:
1ff383a4
RB		 1106 while (--timeout && !s3c24xx_serial_txempty_nofifo(port))
1107 udelay(100);
1108
7cd88831 1109 if (!IS_ERR(ourport->baudclk))
9484b009 1110 clk_disable_unprepare(ourport->baudclk);
b497549a 1111
9484b009 1112 clk_disable_unprepare(ourport->clk);
b497549a
BD		 1113 break;
1114
1115 case 0:
9484b009 1116 clk_prepare_enable(ourport->clk);
b497549a 1117
7cd88831 1118 if (!IS_ERR(ourport->baudclk))
9484b009 1119 clk_prepare_enable(ourport->baudclk);
b497549a
BD		 1120
1121 break;
1122 default:
d20925e1 1123 dev_err(port->dev, "s3c24xx_serial: unknown pm %d\n", level);
b497549a
BD		 1124 }
1125}
1126
1127/* baud rate calculation
1128 *
1129 * The UARTs on the S3C2410/S3C2440 can take their clocks from a number
1130 * of different sources, including the peripheral clock ("pclk") and an
1131 * external clock ("uclk"). The S3C2440 also adds the core clock ("fclk")
1132 * with a programmable extra divisor.
1133 *
1134 * The following code goes through the clock sources, and calculates the
1135 * baud clocks (and the resultant actual baud rates) and then tries to
1136 * pick the closest one and select that.
1137 *
1138*/
1139
5f5a7a55 1140#define MAX_CLK_NAME_LENGTH 15
b497549a 1141
5f5a7a55 1142static inline int s3c24xx_serial_getsource(struct uart_port *port)
b497549a
BD		 1143{
1144 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
5f5a7a55 1145 unsigned int ucon;
b497549a 1146
5f5a7a55
TA		 1147 if (info->num_clks == 1)
1148 return 0;
b497549a 1149
5f5a7a55
TA		 1150 ucon = rd_regl(port, S3C2410_UCON);
1151 ucon &= info->clksel_mask;
1152 return ucon >> info->clksel_shift;
b497549a
BD		 1153}
1154
5f5a7a55
TA		 1155static void s3c24xx_serial_setsource(struct uart_port *port,
1156 unsigned int clk_sel)
b497549a 1157{
5f5a7a55
TA		 1158 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1159 unsigned int ucon;
b497549a 1160
5f5a7a55
TA		 1161 if (info->num_clks == 1)
1162 return;
090f848d 1163
5f5a7a55
TA		 1164 ucon = rd_regl(port, S3C2410_UCON);
1165 if ((ucon & info->clksel_mask) >> info->clksel_shift == clk_sel)
1166 return;
b497549a 1167
5f5a7a55
TA		 1168 ucon &= ~info->clksel_mask;
1169 ucon |= clk_sel << info->clksel_shift;
1170 wr_regl(port, S3C2410_UCON, ucon);
b497549a
BD		 1171}
1172
5f5a7a55
TA		 1173static unsigned int s3c24xx_serial_getclk(struct s3c24xx_uart_port *ourport,
1174 unsigned int req_baud, struct clk **best_clk,
1175 unsigned int *clk_num)
b497549a 1176{
5f5a7a55
TA		 1177 struct s3c24xx_uart_info *info = ourport->info;
1178 struct clk *clk;
1179 unsigned long rate;
1180 unsigned int cnt, baud, quot, clk_sel, best_quot = 0;
1181 char clkname[MAX_CLK_NAME_LENGTH];
1182 int calc_deviation, deviation = (1 << 30) - 1;
1183
5f5a7a55
TA		 1184 clk_sel = (ourport->cfg->clk_sel) ? ourport->cfg->clk_sel :
1185 ourport->info->def_clk_sel;
1186 for (cnt = 0; cnt < info->num_clks; cnt++) {
1187 if (!(clk_sel & (1 << cnt)))
1188 continue;
1189
1190 sprintf(clkname, "clk_uart_baud%d", cnt);
1191 clk = clk_get(ourport->port.dev, clkname);
7cd88831 1192 if (IS_ERR(clk))
5f5a7a55
TA		 1193 continue;
1194
1195 rate = clk_get_rate(clk);
1196 if (!rate)
1197 continue;
1198
1199 if (ourport->info->has_divslot) {
1200 unsigned long div = rate / req_baud;
1201
1202 /* The UDIVSLOT register on the newer UARTs allows us to
1203 * get a divisor adjustment of 1/16th on the baud clock.
1204 *
1205 * We don't keep the UDIVSLOT value (the 16ths we
1206 * calculated by not multiplying the baud by 16) as it
1207 * is easy enough to recalculate.
1208 */
1209
1210 quot = div / 16;
1211 baud = rate / div;
1212 } else {
1213 quot = (rate + (8 * req_baud)) / (16 * req_baud);
1214 baud = rate / (quot * 16);
b497549a 1215 }
5f5a7a55 1216 quot--;
b497549a 1217
5f5a7a55
TA		 1218 calc_deviation = req_baud - baud;
1219 if (calc_deviation < 0)
1220 calc_deviation = -calc_deviation;
b497549a 1221
5f5a7a55
TA		 1222 if (calc_deviation < deviation) {
1223 *best_clk = clk;
1224 best_quot = quot;
1225 *clk_num = cnt;
1226 deviation = calc_deviation;
b497549a
BD		 1227 }
1228 }
1229
5f5a7a55 1230 return best_quot;
b497549a
BD		 1231}
1232
090f848d
BD		 1233/* udivslot_table[]
1234 *
1235 * This table takes the fractional value of the baud divisor and gives
1236 * the recommended setting for the UDIVSLOT register.
1237 */
1238static u16 udivslot_table[16] = {
1239 [0] = 0x0000,
1240 [1] = 0x0080,
1241 [2] = 0x0808,
1242 [3] = 0x0888,
1243 [4] = 0x2222,
1244 [5] = 0x4924,
1245 [6] = 0x4A52,
1246 [7] = 0x54AA,
1247 [8] = 0x5555,
1248 [9] = 0xD555,
1249 [10] = 0xD5D5,
1250 [11] = 0xDDD5,
1251 [12] = 0xDDDD,
1252 [13] = 0xDFDD,
1253 [14] = 0xDFDF,
1254 [15] = 0xFFDF,
1255};
1256
b497549a
BD		 1257static void s3c24xx_serial_set_termios(struct uart_port *port,
1258 struct ktermios *termios,
1259 struct ktermios *old)
1260{
1261 struct s3c2410_uartcfg *cfg = s3c24xx_port_to_cfg(port);
1262 struct s3c24xx_uart_port *ourport = to_ourport(port);
7cd88831 1263 struct clk *clk = ERR_PTR(-EINVAL);
b497549a 1264 unsigned long flags;
5f5a7a55 1265 unsigned int baud, quot, clk_sel = 0;
b497549a
BD		 1266 unsigned int ulcon;
1267 unsigned int umcon;
090f848d 1268 unsigned int udivslot = 0;
b497549a
BD		 1269
1270 /*
1271 * We don't support modem control lines.
1272 */
1273 termios->c_cflag &= ~(HUPCL | CMSPAR);
1274 termios->c_cflag |= CLOCAL;
1275
1276 /*
1277 * Ask the core to calculate the divisor for us.
1278 */
1279
1280 baud = uart_get_baud_rate(port, termios, old, 0, 115200*8);
5f5a7a55 1281 quot = s3c24xx_serial_getclk(ourport, baud, &clk, &clk_sel);
b497549a
BD		 1282 if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST)
1283 quot = port->custom_divisor;
7cd88831 1284 if (IS_ERR(clk))
5f5a7a55 1285 return;
b497549a
BD		 1286
1287 /* check to see if we need to change clock source */
1288
5f5a7a55
TA		 1289 if (ourport->baudclk != clk) {
1290 s3c24xx_serial_setsource(port, clk_sel);
b497549a 1291
7cd88831 1292 if (!IS_ERR(ourport->baudclk)) {
9484b009 1293 clk_disable_unprepare(ourport->baudclk);
7cd88831 1294 ourport->baudclk = ERR_PTR(-EINVAL);
b497549a
BD		 1295 }
1296
9484b009 1297 clk_prepare_enable(clk);
b497549a 1298
b497549a 1299 ourport->baudclk = clk;
30555476 1300 ourport->baudclk_rate = clk ? clk_get_rate(clk) : 0;
b497549a
BD		 1301 }
1302
090f848d
BD		 1303 if (ourport->info->has_divslot) {
1304 unsigned int div = ourport->baudclk_rate / baud;
1305
8b526ae4
JL		 1306 if (cfg->has_fracval) {
1307 udivslot = (div & 15);
1308 dbg("fracval = %04x\n", udivslot);
1309 } else {
1310 udivslot = udivslot_table[div & 15];
1311 dbg("udivslot = %04x (div %d)\n", udivslot, div & 15);
1312 }
090f848d
BD		 1313 }
1314
b497549a
BD		 1315 switch (termios->c_cflag & CSIZE) {
1316 case CS5:
1317 dbg("config: 5bits/char\n");
1318 ulcon = S3C2410_LCON_CS5;
1319 break;
1320 case CS6:
1321 dbg("config: 6bits/char\n");
1322 ulcon = S3C2410_LCON_CS6;
1323 break;
1324 case CS7:
1325 dbg("config: 7bits/char\n");
1326 ulcon = S3C2410_LCON_CS7;
1327 break;
1328 case CS8:
1329 default:
1330 dbg("config: 8bits/char\n");
1331 ulcon = S3C2410_LCON_CS8;
1332 break;
1333 }
1334
1335 /* preserve original lcon IR settings */
1336 ulcon |= (cfg->ulcon & S3C2410_LCON_IRM);
1337
1338 if (termios->c_cflag & CSTOPB)
1339 ulcon |= S3C2410_LCON_STOPB;
1340
b497549a
BD		 1341 if (termios->c_cflag & PARENB) {
1342 if (termios->c_cflag & PARODD)
1343 ulcon |= S3C2410_LCON_PODD;
1344 else
1345 ulcon |= S3C2410_LCON_PEVEN;
1346 } else {
1347 ulcon |= S3C2410_LCON_PNONE;
1348 }
1349
1350 spin_lock_irqsave(&port->lock, flags);
1351
090f848d
BD		 1352 dbg("setting ulcon to %08x, brddiv to %d, udivslot %08x\n",
1353 ulcon, quot, udivslot);
b497549a
BD		 1354
1355 wr_regl(port, S3C2410_ULCON, ulcon);
1356 wr_regl(port, S3C2410_UBRDIV, quot);
2d1e5a48
JMG		 1357
1358 umcon = rd_regl(port, S3C2410_UMCON);
1359 if (termios->c_cflag & CRTSCTS) {
1360 umcon |= S3C2410_UMCOM_AFC;
1361 /* Disable RTS when RX FIFO contains 63 bytes */
1362 umcon &= ~S3C2412_UMCON_AFC_8;
1363 } else {
1364 umcon &= ~S3C2410_UMCOM_AFC;
1365 }
b497549a
BD		 1366 wr_regl(port, S3C2410_UMCON, umcon);
1367
090f848d
BD		 1368 if (ourport->info->has_divslot)
1369 wr_regl(port, S3C2443_DIVSLOT, udivslot);
1370
b497549a
BD		 1371 dbg("uart: ulcon = 0x%08x, ucon = 0x%08x, ufcon = 0x%08x\n",
1372 rd_regl(port, S3C2410_ULCON),
1373 rd_regl(port, S3C2410_UCON),
1374 rd_regl(port, S3C2410_UFCON));
1375
1376 /*
1377 * Update the per-port timeout.
1378 */
1379 uart_update_timeout(port, termios->c_cflag, baud);
1380
1381 /*
1382 * Which character status flags are we interested in?
1383 */
1384 port->read_status_mask = S3C2410_UERSTAT_OVERRUN;
1385 if (termios->c_iflag & INPCK)
ef4aca70
RB		 1386 port->read_status_mask |= S3C2410_UERSTAT_FRAME |
1387 S3C2410_UERSTAT_PARITY;
b497549a
BD		 1388 /*
1389 * Which character status flags should we ignore?
1390 */
1391 port->ignore_status_mask = 0;
1392 if (termios->c_iflag & IGNPAR)
1393 port->ignore_status_mask |= S3C2410_UERSTAT_OVERRUN;
1394 if (termios->c_iflag & IGNBRK && termios->c_iflag & IGNPAR)
1395 port->ignore_status_mask |= S3C2410_UERSTAT_FRAME;
1396
1397 /*
1398 * Ignore all characters if CREAD is not set.
1399 */
1400 if ((termios->c_cflag & CREAD) == 0)
1401 port->ignore_status_mask |= RXSTAT_DUMMY_READ;
1402
1403 spin_unlock_irqrestore(&port->lock, flags);
1404}
1405
1406static const char *s3c24xx_serial_type(struct uart_port *port)
1407{
1408 switch (port->type) {
1409 case PORT_S3C2410:
1410 return "S3C2410";
1411 case PORT_S3C2440:
1412 return "S3C2440";
1413 case PORT_S3C2412:
1414 return "S3C2412";
b690ace5
BD		 1415 case PORT_S3C6400:
1416 return "S3C6400/10";
b497549a
BD		 1417 default:
1418 return NULL;
1419 }
1420}
1421
1422#define MAP_SIZE (0x100)
1423
1424static void s3c24xx_serial_release_port(struct uart_port *port)
1425{
1426 release_mem_region(port->mapbase, MAP_SIZE);
1427}
1428
1429static int s3c24xx_serial_request_port(struct uart_port *port)
1430{
1431 const char *name = s3c24xx_serial_portname(port);
1432 return request_mem_region(port->mapbase, MAP_SIZE, name) ? 0 : -EBUSY;
1433}
1434
1435static void s3c24xx_serial_config_port(struct uart_port *port, int flags)
1436{
1437 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1438
1439 if (flags & UART_CONFIG_TYPE &&
1440 s3c24xx_serial_request_port(port) == 0)
1441 port->type = info->type;
1442}
1443
1444/*
1445 * verify the new serial_struct (for TIOCSSERIAL).
1446 */
1447static int
1448s3c24xx_serial_verify_port(struct uart_port *port, struct serial_struct *ser)
1449{
1450 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1451
1452 if (ser->type != PORT_UNKNOWN && ser->type != info->type)
1453 return -EINVAL;
1454
1455 return 0;
1456}
1457
1458
1459#ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
1460
1461static struct console s3c24xx_serial_console;
1462
93b5c032
JP		 1463static int __init s3c24xx_serial_console_init(void)
1464{
1465 register_console(&s3c24xx_serial_console);
1466 return 0;
1467}
1468console_initcall(s3c24xx_serial_console_init);
1469
b497549a
BD		 1470#define S3C24XX_SERIAL_CONSOLE &s3c24xx_serial_console
1471#else
1472#define S3C24XX_SERIAL_CONSOLE NULL
1473#endif
1474
84f57d9e 1475#if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
93b5c032
JP		 1476static int s3c24xx_serial_get_poll_char(struct uart_port *port);
1477static void s3c24xx_serial_put_poll_char(struct uart_port *port,
1478 unsigned char c);
1479#endif
1480
b497549a
BD		 1481static struct uart_ops s3c24xx_serial_ops = {
1482 .pm = s3c24xx_serial_pm,
1483 .tx_empty = s3c24xx_serial_tx_empty,
1484 .get_mctrl = s3c24xx_serial_get_mctrl,
1485 .set_mctrl = s3c24xx_serial_set_mctrl,
1486 .stop_tx = s3c24xx_serial_stop_tx,
1487 .start_tx = s3c24xx_serial_start_tx,
1488 .stop_rx = s3c24xx_serial_stop_rx,
b497549a
BD		 1489 .break_ctl = s3c24xx_serial_break_ctl,
1490 .startup = s3c24xx_serial_startup,
1491 .shutdown = s3c24xx_serial_shutdown,
1492 .set_termios = s3c24xx_serial_set_termios,
1493 .type = s3c24xx_serial_type,
1494 .release_port = s3c24xx_serial_release_port,
1495 .request_port = s3c24xx_serial_request_port,
1496 .config_port = s3c24xx_serial_config_port,
1497 .verify_port = s3c24xx_serial_verify_port,
84f57d9e 1498#if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
93b5c032
JP		 1499 .poll_get_char = s3c24xx_serial_get_poll_char,
1500 .poll_put_char = s3c24xx_serial_put_poll_char,
1501#endif
b497549a
BD		 1502};
1503
b497549a
BD		 1504static struct uart_driver s3c24xx_uart_drv = {
1505 .owner = THIS_MODULE,
2cf0c58e 1506 .driver_name = "s3c2410_serial",
bdd4915a 1507 .nr = CONFIG_SERIAL_SAMSUNG_UARTS,
b497549a 1508 .cons = S3C24XX_SERIAL_CONSOLE,
2cf0c58e 1509 .dev_name = S3C24XX_SERIAL_NAME,
b497549a
BD		 1510 .major = S3C24XX_SERIAL_MAJOR,
1511 .minor = S3C24XX_SERIAL_MINOR,
1512};
1513
ef4aca70
RB		 1514#define __PORT_LOCK_UNLOCKED(i) \
1515 __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[i].port.lock)
1516static struct s3c24xx_uart_port
1517s3c24xx_serial_ports[CONFIG_SERIAL_SAMSUNG_UARTS] = {
b497549a
BD		 1518 [0] = {
1519 .port = {
ef4aca70 1520 .lock = __PORT_LOCK_UNLOCKED(0),
b497549a 1521 .iotype = UPIO_MEM,
b497549a
BD		 1522 .uartclk = 0,
1523 .fifosize = 16,
1524 .ops = &s3c24xx_serial_ops,
1525 .flags = UPF_BOOT_AUTOCONF,
1526 .line = 0,
1527 }
1528 },
1529 [1] = {
1530 .port = {
ef4aca70 1531 .lock = __PORT_LOCK_UNLOCKED(1),
b497549a 1532 .iotype = UPIO_MEM,
b497549a
BD		 1533 .uartclk = 0,
1534 .fifosize = 16,
1535 .ops = &s3c24xx_serial_ops,
1536 .flags = UPF_BOOT_AUTOCONF,
1537 .line = 1,
1538 }
1539 },
03d5e77b 1540#if CONFIG_SERIAL_SAMSUNG_UARTS > 2
b497549a
BD		 1541
1542 [2] = {
1543 .port = {
ef4aca70 1544 .lock = __PORT_LOCK_UNLOCKED(2),
b497549a 1545 .iotype = UPIO_MEM,
b497549a
BD		 1546 .uartclk = 0,
1547 .fifosize = 16,
1548 .ops = &s3c24xx_serial_ops,
1549 .flags = UPF_BOOT_AUTOCONF,
1550 .line = 2,
1551 }
03d5e77b
BD		 1552 },
1553#endif
1554#if CONFIG_SERIAL_SAMSUNG_UARTS > 3
1555 [3] = {
1556 .port = {
ef4aca70 1557 .lock = __PORT_LOCK_UNLOCKED(3),
03d5e77b 1558 .iotype = UPIO_MEM,
03d5e77b
BD		 1559 .uartclk = 0,
1560 .fifosize = 16,
1561 .ops = &s3c24xx_serial_ops,
1562 .flags = UPF_BOOT_AUTOCONF,
1563 .line = 3,
1564 }
b497549a
BD		 1565 }
1566#endif
1567};
ef4aca70 1568#undef __PORT_LOCK_UNLOCKED
b497549a
BD		 1569
1570/* s3c24xx_serial_resetport
1571 *
0dfb3b41 1572 * reset the fifos and other the settings.
b497549a
BD		 1573*/
1574
0dfb3b41
TA		 1575static void s3c24xx_serial_resetport(struct uart_port *port,
1576 struct s3c2410_uartcfg *cfg)
b497549a
BD		 1577{
1578 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
0dfb3b41
TA		 1579 unsigned long ucon = rd_regl(port, S3C2410_UCON);
1580 unsigned int ucon_mask;
b497549a 1581
0dfb3b41
TA		 1582 ucon_mask = info->clksel_mask;
1583 if (info->type == PORT_S3C2440)
1584 ucon_mask |= S3C2440_UCON0_DIVMASK;
1585
1586 ucon &= ucon_mask;
1587 wr_regl(port, S3C2410_UCON, ucon | cfg->ucon);
1588
1589 /* reset both fifos */
1590 wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
1591 wr_regl(port, S3C2410_UFCON, cfg->ufcon);
1592
1593 /* some delay is required after fifo reset */
1594 udelay(1);
b497549a
BD		 1595}
1596
30555476
BD		 1597
1598#ifdef CONFIG_CPU_FREQ
1599
1600static int s3c24xx_serial_cpufreq_transition(struct notifier_block *nb,
1601 unsigned long val, void *data)
1602{
1603 struct s3c24xx_uart_port *port;
1604 struct uart_port *uport;
1605
1606 port = container_of(nb, struct s3c24xx_uart_port, freq_transition);
1607 uport = &port->port;
1608
1609 /* check to see if port is enabled */
1610
1611 if (port->pm_level != 0)
1612 return 0;
1613
1614 /* try and work out if the baudrate is changing, we can detect
1615 * a change in rate, but we do not have support for detecting
1616 * a disturbance in the clock-rate over the change.
1617 */
1618
25f04ad4 1619 if (IS_ERR(port->baudclk))
30555476
BD		 1620 goto exit;
1621
25f04ad4 1622 if (port->baudclk_rate == clk_get_rate(port->baudclk))
30555476
BD		 1623 goto exit;
1624
1625 if (val == CPUFREQ_PRECHANGE) {
1626 /* we should really shut the port down whilst the
1627 * frequency change is in progress. */
1628
1629 } else if (val == CPUFREQ_POSTCHANGE) {
1630 struct ktermios *termios;
1631 struct tty_struct *tty;
1632
ebd2c8f6 1633 if (uport->state == NULL)
30555476 1634 goto exit;
30555476 1635
ebd2c8f6 1636 tty = uport->state->port.tty;
30555476 1637
7de40c21 1638 if (tty == NULL)
30555476 1639 goto exit;
30555476 1640
adc8d746 1641 termios = &tty->termios;
30555476
BD		 1642
1643 if (termios == NULL) {
d20925e1 1644 dev_warn(uport->dev, "%s: no termios?\n", __func__);
30555476
BD		 1645 goto exit;
1646 }
1647
1648 s3c24xx_serial_set_termios(uport, termios, NULL);
1649 }
1650
ef4aca70 1651exit:
30555476
BD		 1652 return 0;
1653}
1654
ef4aca70
RB		 1655static inline int
1656s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port)
30555476
BD		 1657{
1658 port->freq_transition.notifier_call = s3c24xx_serial_cpufreq_transition;
1659
1660 return cpufreq_register_notifier(&port->freq_transition,
1661 CPUFREQ_TRANSITION_NOTIFIER);
1662}
1663
ef4aca70
RB		 1664static inline void
1665s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port)
30555476
BD		 1666{
1667 cpufreq_unregister_notifier(&port->freq_transition,
1668 CPUFREQ_TRANSITION_NOTIFIER);
1669}
1670
1671#else
ef4aca70
RB		 1672static inline int
1673s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port)
30555476
BD		 1674{
1675 return 0;
1676}
1677
ef4aca70
RB		 1678static inline void
1679s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port)
30555476
BD		 1680{
1681}
1682#endif
1683
b497549a
BD		 1684/* s3c24xx_serial_init_port
1685 *
1686 * initialise a single serial port from the platform device given
1687 */
1688
1689static int s3c24xx_serial_init_port(struct s3c24xx_uart_port *ourport,
b497549a
BD		 1690 struct platform_device *platdev)
1691{
1692 struct uart_port *port = &ourport->port;
da121506 1693 struct s3c2410_uartcfg *cfg = ourport->cfg;
b497549a
BD		 1694 struct resource *res;
1695 int ret;
1696
1697 dbg("s3c24xx_serial_init_port: port=%p, platdev=%p\n", port, platdev);
1698
1699 if (platdev == NULL)
1700 return -ENODEV;
1701
b497549a
BD		 1702 if (port->mapbase != 0)
1703 return 0;
1704
b497549a
BD		 1705 /* setup info for port */
1706 port->dev = &platdev->dev;
b497549a 1707
88bb4ea1
TA		 1708 /* Startup sequence is different for s3c64xx and higher SoC's */
1709 if (s3c24xx_serial_has_interrupt_mask(port))
1710 s3c24xx_serial_ops.startup = s3c64xx_serial_startup;
1711
b497549a
BD		 1712 port->uartclk = 1;
1713
1714 if (cfg->uart_flags & UPF_CONS_FLOW) {
1715 dbg("s3c24xx_serial_init_port: enabling flow control\n");
1716 port->flags |= UPF_CONS_FLOW;
1717 }
1718
1719 /* sort our the physical and virtual addresses for each UART */
1720
1721 res = platform_get_resource(platdev, IORESOURCE_MEM, 0);
1722 if (res == NULL) {
d20925e1 1723 dev_err(port->dev, "failed to find memory resource for uart\n");
b497549a
BD		 1724 return -EINVAL;
1725 }
1726
e4ac92df 1727 dbg("resource %pR)\n", res);
b497549a 1728
41147bfd
TA		 1729 port->membase = devm_ioremap(port->dev, res->start, resource_size(res));
1730 if (!port->membase) {
1731 dev_err(port->dev, "failed to remap controller address\n");
1732 return -EBUSY;
1733 }
1734
b690ace5 1735 port->mapbase = res->start;
b497549a
BD		 1736 ret = platform_get_irq(platdev, 0);
1737 if (ret < 0)
1738 port->irq = 0;
b73c289c 1739 else {
b497549a 1740 port->irq = ret;
b73c289c
BD		 1741 ourport->rx_irq = ret;
1742 ourport->tx_irq = ret + 1;
1743 }
9303ac15 1744
b73c289c
BD		 1745 ret = platform_get_irq(platdev, 1);
1746 if (ret > 0)
1747 ourport->tx_irq = ret;
658c9d2b
RB		 1748 /*
1749 * DMA is currently supported only on DT platforms, if DMA properties
1750 * are specified.
1751 */
1752 if (platdev->dev.of_node && of_find_property(platdev->dev.of_node,
1753 "dmas", NULL)) {
1754 ourport->dma = devm_kzalloc(port->dev,
1755 sizeof(*ourport->dma),
1756 GFP_KERNEL);
1757 if (!ourport->dma)
1758 return -ENOMEM;
1759 }
b497549a
BD		 1760
1761 ourport->clk = clk_get(&platdev->dev, "uart");
60e93575
CK		 1762 if (IS_ERR(ourport->clk)) {
1763 pr_err("%s: Controller clock not found\n",
1764 dev_name(&platdev->dev));
1765 return PTR_ERR(ourport->clk);
1766 }
1767
1768 ret = clk_prepare_enable(ourport->clk);
1769 if (ret) {
1770 pr_err("uart: clock failed to prepare+enable: %d\n", ret);
1771 clk_put(ourport->clk);
1772 return ret;
1773 }
b497549a 1774
88bb4ea1
TA		 1775 /* Keep all interrupts masked and cleared */
1776 if (s3c24xx_serial_has_interrupt_mask(port)) {
1777 wr_regl(port, S3C64XX_UINTM, 0xf);
1778 wr_regl(port, S3C64XX_UINTP, 0xf);
1779 wr_regl(port, S3C64XX_UINTSP, 0xf);
1780 }
1781
1ff5b64d
FE		 1782 dbg("port: map=%pa, mem=%p, irq=%d (%d,%d), clock=%u\n",
1783 &port->mapbase, port->membase, port->irq,
b73c289c 1784 ourport->rx_irq, ourport->tx_irq, port->uartclk);
b497549a
BD		 1785
1786 /* reset the fifos (and setup the uart) */
1787 s3c24xx_serial_resetport(port, cfg);
1788 return 0;
1789}
1790
b497549a
BD		 1791/* Device driver serial port probe */
1792
26c919e1 1793static const struct of_device_id s3c24xx_uart_dt_match[];
b497549a
BD		 1794static int probe_index;
1795
26c919e1
TA		 1796static inline struct s3c24xx_serial_drv_data *s3c24xx_get_driver_data(
1797 struct platform_device *pdev)
1798{
1799#ifdef CONFIG_OF
1800 if (pdev->dev.of_node) {
1801 const struct of_device_id *match;
1802 match = of_match_node(s3c24xx_uart_dt_match, pdev->dev.of_node);
1803 return (struct s3c24xx_serial_drv_data *)match->data;
1804 }
1805#endif
1806 return (struct s3c24xx_serial_drv_data *)
1807 platform_get_device_id(pdev)->driver_data;
1808}
1809
da121506 1810static int s3c24xx_serial_probe(struct platform_device *pdev)
b497549a 1811{
4622eb68 1812 struct device_node *np = pdev->dev.of_node;
b497549a 1813 struct s3c24xx_uart_port *ourport;
13a9f6c6 1814 int index = probe_index;
b497549a
BD		 1815 int ret;
1816
4622eb68
NKC		 1817 if (np) {
1818 ret = of_alias_get_id(np, "serial");
13a9f6c6
TF		 1819 if (ret >= 0)
1820 index = ret;
1821 }
1822
1823 dbg("s3c24xx_serial_probe(%p) %d\n", pdev, index);
b497549a 1824
13a9f6c6 1825 ourport = &s3c24xx_serial_ports[index];
da121506 1826
26c919e1
TA		 1827 ourport->drv_data = s3c24xx_get_driver_data(pdev);
1828 if (!ourport->drv_data) {
1829 dev_err(&pdev->dev, "could not find driver data\n");
1830 return -ENODEV;
1831 }
da121506 1832
7cd88831 1833 ourport->baudclk = ERR_PTR(-EINVAL);
da121506 1834 ourport->info = ourport->drv_data->info;
574de559 1835 ourport->cfg = (dev_get_platdata(&pdev->dev)) ?
d4aab206 1836 dev_get_platdata(&pdev->dev) :
da121506
TA		 1837 ourport->drv_data->def_cfg;
1838
4622eb68
NKC		 1839 if (np)
1840 of_property_read_u32(np,
135f07c3
NKC		 1841 "samsung,uart-fifosize", &ourport->port.fifosize);
1842
2f1ba72d
RB		 1843 if (ourport->drv_data->fifosize[index])
1844 ourport->port.fifosize = ourport->drv_data->fifosize[index];
1845 else if (ourport->info->fifosize)
1846 ourport->port.fifosize = ourport->info->fifosize;
da121506 1847
81ccb2a6
MS		 1848 /*
1849 * DMA transfers must be aligned at least to cache line size,
1850 * so find minimal transfer size suitable for DMA mode
1851 */
1852 ourport->min_dma_size = max_t(int, ourport->port.fifosize,
1853 dma_get_cache_alignment());
1854
b497549a
BD		 1855 probe_index++;
1856
1857 dbg("%s: initialising port %p...\n", __func__, ourport);
1858
da121506 1859 ret = s3c24xx_serial_init_port(ourport, pdev);
b497549a 1860 if (ret < 0)
8ad711a9 1861 return ret;
b497549a 1862
6f134c3c
TB		 1863 if (!s3c24xx_uart_drv.state) {
1864 ret = uart_register_driver(&s3c24xx_uart_drv);
1865 if (ret < 0) {
1866 pr_err("Failed to register Samsung UART driver\n");
1867 return ret;
1868 }
1869 }
1870
b497549a
BD		 1871 dbg("%s: adding port\n", __func__);
1872 uart_add_one_port(&s3c24xx_uart_drv, &ourport->port);
da121506 1873 platform_set_drvdata(pdev, &ourport->port);
b497549a 1874
0da3336f
HS		 1875 /*
1876 * Deactivate the clock enabled in s3c24xx_serial_init_port here,
1877 * so that a potential re-enablement through the pm-callback overlaps
1878 * and keeps the clock enabled in this case.
1879 */
1880 clk_disable_unprepare(ourport->clk);
1881
30555476
BD		 1882 ret = s3c24xx_serial_cpufreq_register(ourport);
1883 if (ret < 0)
da121506 1884 dev_err(&pdev->dev, "failed to add cpufreq notifier\n");
30555476 1885
b497549a 1886 return 0;
b497549a
BD		 1887}
1888
ae8d8a14 1889static int s3c24xx_serial_remove(struct platform_device *dev)
b497549a
BD		 1890{
1891 struct uart_port *port = s3c24xx_dev_to_port(&dev->dev);
1892
1893 if (port) {
30555476 1894 s3c24xx_serial_cpufreq_deregister(to_ourport(port));
b497549a
BD		 1895 uart_remove_one_port(&s3c24xx_uart_drv, port);
1896 }
1897
6f134c3c
TB		 1898 uart_unregister_driver(&s3c24xx_uart_drv);
1899
b497549a
BD		 1900 return 0;
1901}
1902
b497549a 1903/* UART power management code */
aef7fe52
MH		 1904#ifdef CONFIG_PM_SLEEP
1905static int s3c24xx_serial_suspend(struct device *dev)
b497549a 1906{
aef7fe52 1907 struct uart_port *port = s3c24xx_dev_to_port(dev);
b497549a
BD		 1908
1909 if (port)
1910 uart_suspend_port(&s3c24xx_uart_drv, port);
1911
1912 return 0;
1913}
1914
aef7fe52 1915static int s3c24xx_serial_resume(struct device *dev)
b497549a 1916{
aef7fe52 1917 struct uart_port *port = s3c24xx_dev_to_port(dev);
b497549a
BD		 1918 struct s3c24xx_uart_port *ourport = to_ourport(port);
1919
1920 if (port) {
9484b009 1921 clk_prepare_enable(ourport->clk);
b497549a 1922 s3c24xx_serial_resetport(port, s3c24xx_port_to_cfg(port));
9484b009 1923 clk_disable_unprepare(ourport->clk);
b497549a
BD		 1924
1925 uart_resume_port(&s3c24xx_uart_drv, port);
1926 }
1927
1928 return 0;
1929}
aef7fe52 1930
d09a7308
MS		 1931static int s3c24xx_serial_resume_noirq(struct device *dev)
1932{
1933 struct uart_port *port = s3c24xx_dev_to_port(dev);
1934
1935 if (port) {
1936 /* restore IRQ mask */
1937 if (s3c24xx_serial_has_interrupt_mask(port)) {
1938 unsigned int uintm = 0xf;
1939 if (tx_enabled(port))
1940 uintm &= ~S3C64XX_UINTM_TXD_MSK;
1941 if (rx_enabled(port))
1942 uintm &= ~S3C64XX_UINTM_RXD_MSK;
1943 wr_regl(port, S3C64XX_UINTM, uintm);
1944 }
1945 }
1946
1947 return 0;
1948}
1949
aef7fe52
MH		 1950static const struct dev_pm_ops s3c24xx_serial_pm_ops = {
1951 .suspend = s3c24xx_serial_suspend,
1952 .resume = s3c24xx_serial_resume,
d09a7308 1953 .resume_noirq = s3c24xx_serial_resume_noirq,
aef7fe52 1954};
b882fc1b
KK		 1955#define SERIAL_SAMSUNG_PM_OPS (&s3c24xx_serial_pm_ops)
1956
aef7fe52 1957#else /* !CONFIG_PM_SLEEP */
b882fc1b
KK		 1958
1959#define SERIAL_SAMSUNG_PM_OPS NULL
aef7fe52 1960#endif /* CONFIG_PM_SLEEP */
b497549a 1961
b497549a
BD		 1962/* Console code */
1963
1964#ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
1965
1966static struct uart_port *cons_uart;
1967
1968static int
1969s3c24xx_serial_console_txrdy(struct uart_port *port, unsigned int ufcon)
1970{
1971 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1972 unsigned long ufstat, utrstat;
1973
1974 if (ufcon & S3C2410_UFCON_FIFOMODE) {
9ddc5b6f 1975 /* fifo mode - check amount of data in fifo registers... */
b497549a
BD		 1976
1977 ufstat = rd_regl(port, S3C2410_UFSTAT);
1978 return (ufstat & info->tx_fifofull) ? 0 : 1;
1979 }
1980
1981 /* in non-fifo mode, we go and use the tx buffer empty */
1982
1983 utrstat = rd_regl(port, S3C2410_UTRSTAT);
1984 return (utrstat & S3C2410_UTRSTAT_TXE) ? 1 : 0;
1985}
1986
38adbc54
MS		 1987static bool
1988s3c24xx_port_configured(unsigned int ucon)
1989{
1990 /* consider the serial port configured if the tx/rx mode set */
1991 return (ucon & 0xf) != 0;
1992}
1993
93b5c032
JP		 1994#ifdef CONFIG_CONSOLE_POLL
1995/*
1996 * Console polling routines for writing and reading from the uart while
1997 * in an interrupt or debug context.
1998 */
1999
2000static int s3c24xx_serial_get_poll_char(struct uart_port *port)
2001{
2002 struct s3c24xx_uart_port *ourport = to_ourport(port);
2003 unsigned int ufstat;
2004
2005 ufstat = rd_regl(port, S3C2410_UFSTAT);
2006 if (s3c24xx_serial_rx_fifocnt(ourport, ufstat) == 0)
2007 return NO_POLL_CHAR;
2008
2009 return rd_regb(port, S3C2410_URXH);
2010}
2011
2012static void s3c24xx_serial_put_poll_char(struct uart_port *port,
2013 unsigned char c)
2014{
bb7f09ba
DA		 2015 unsigned int ufcon = rd_regl(port, S3C2410_UFCON);
2016 unsigned int ucon = rd_regl(port, S3C2410_UCON);
38adbc54
MS		 2017
2018 /* not possible to xmit on unconfigured port */
2019 if (!s3c24xx_port_configured(ucon))
2020 return;
93b5c032
JP		 2021
2022 while (!s3c24xx_serial_console_txrdy(port, ufcon))
2023 cpu_relax();
bb7f09ba 2024 wr_regb(port, S3C2410_UTXH, c);
93b5c032
JP		 2025}
2026
2027#endif /* CONFIG_CONSOLE_POLL */
2028
b497549a
BD		 2029static void
2030s3c24xx_serial_console_putchar(struct uart_port *port, int ch)
2031{
bb7f09ba 2032 unsigned int ufcon = rd_regl(port, S3C2410_UFCON);
38adbc54 2033
b497549a 2034 while (!s3c24xx_serial_console_txrdy(port, ufcon))
f94b0572 2035 cpu_relax();
bb7f09ba 2036 wr_regb(port, S3C2410_UTXH, ch);
b497549a
BD		 2037}
2038
2039static void
2040s3c24xx_serial_console_write(struct console *co, const char *s,
2041 unsigned int count)
2042{
ab88c8dc
DA		 2043 unsigned int ucon = rd_regl(cons_uart, S3C2410_UCON);
2044
2045 /* not possible to xmit on unconfigured port */
2046 if (!s3c24xx_port_configured(ucon))
2047 return;
2048
b497549a
BD		 2049 uart_console_write(cons_uart, s, count, s3c24xx_serial_console_putchar);
2050}
2051
2052static void __init
2053s3c24xx_serial_get_options(struct uart_port *port, int *baud,
2054 int *parity, int *bits)
2055{
b497549a
BD		 2056 struct clk *clk;
2057 unsigned int ulcon;
2058 unsigned int ucon;
2059 unsigned int ubrdiv;
2060 unsigned long rate;
5f5a7a55
TA		 2061 unsigned int clk_sel;
2062 char clk_name[MAX_CLK_NAME_LENGTH];
b497549a
BD		 2063
2064 ulcon = rd_regl(port, S3C2410_ULCON);
2065 ucon = rd_regl(port, S3C2410_UCON);
2066 ubrdiv = rd_regl(port, S3C2410_UBRDIV);
2067
2068 dbg("s3c24xx_serial_get_options: port=%p\n"
2069 "registers: ulcon=%08x, ucon=%08x, ubdriv=%08x\n",
2070 port, ulcon, ucon, ubrdiv);
2071
38adbc54 2072 if (s3c24xx_port_configured(ucon)) {
b497549a
BD		 2073 switch (ulcon & S3C2410_LCON_CSMASK) {
2074 case S3C2410_LCON_CS5:
2075 *bits = 5;
2076 break;
2077 case S3C2410_LCON_CS6:
2078 *bits = 6;
2079 break;
2080 case S3C2410_LCON_CS7:
2081 *bits = 7;
2082 break;
b497549a 2083 case S3C2410_LCON_CS8:
3bcce591 2084 default:
b497549a
BD		 2085 *bits = 8;
2086 break;
2087 }
2088
2089 switch (ulcon & S3C2410_LCON_PMASK) {
2090 case S3C2410_LCON_PEVEN:
2091 *parity = 'e';
2092 break;
2093
2094 case S3C2410_LCON_PODD:
2095 *parity = 'o';
2096 break;
2097
2098 case S3C2410_LCON_PNONE:
2099 default:
2100 *parity = 'n';
2101 }
2102
2103 /* now calculate the baud rate */
2104
5f5a7a55
TA		 2105 clk_sel = s3c24xx_serial_getsource(port);
2106 sprintf(clk_name, "clk_uart_baud%d", clk_sel);
b497549a 2107
5f5a7a55 2108 clk = clk_get(port->dev, clk_name);
7cd88831 2109 if (!IS_ERR(clk))
5f5a7a55 2110 rate = clk_get_rate(clk);
b497549a
BD		 2111 else
2112 rate = 1;
2113
b497549a
BD		 2114 *baud = rate / (16 * (ubrdiv + 1));
2115 dbg("calculated baud %d\n", *baud);
2116 }
2117
2118}
2119
b497549a
BD		 2120static int __init
2121s3c24xx_serial_console_setup(struct console *co, char *options)
2122{
2123 struct uart_port *port;
2124 int baud = 9600;
2125 int bits = 8;
2126 int parity = 'n';
2127 int flow = 'n';
2128
2129 dbg("s3c24xx_serial_console_setup: co=%p (%d), %s\n",
2130 co, co->index, options);
2131
2132 /* is this a valid port */
2133
03d5e77b 2134 if (co->index == -1 || co->index >= CONFIG_SERIAL_SAMSUNG_UARTS)
b497549a
BD		 2135 co->index = 0;
2136
2137 port = &s3c24xx_serial_ports[co->index].port;
2138
2139 /* is the port configured? */
2140
ee430f16
TA		 2141 if (port->mapbase == 0x0)
2142 return -ENODEV;
b497549a
BD		 2143
2144 cons_uart = port;
2145
2146 dbg("s3c24xx_serial_console_setup: port=%p (%d)\n", port, co->index);
2147
2148 /*
2149 * Check whether an invalid uart number has been specified, and
2150 * if so, search for the first available port that does have
2151 * console support.
2152 */
2153 if (options)
2154 uart_parse_options(options, &baud, &parity, &bits, &flow);
2155 else
2156 s3c24xx_serial_get_options(port, &baud, &parity, &bits);
2157
2158 dbg("s3c24xx_serial_console_setup: baud %d\n", baud);
2159
2160 return uart_set_options(port, co, baud, parity, bits, flow);
2161}
2162
b497549a
BD		 2163static struct console s3c24xx_serial_console = {
2164 .name = S3C24XX_SERIAL_NAME,
2165 .device = uart_console_device,
2166 .flags = CON_PRINTBUFFER,
2167 .index = -1,
2168 .write = s3c24xx_serial_console_write,
5822a5df
TA		 2169 .setup = s3c24xx_serial_console_setup,
2170 .data = &s3c24xx_uart_drv,
b497549a 2171};
da121506
TA		 2172#endif /* CONFIG_SERIAL_SAMSUNG_CONSOLE */
2173
2174#ifdef CONFIG_CPU_S3C2410
2175static struct s3c24xx_serial_drv_data s3c2410_serial_drv_data = {
2176 .info = &(struct s3c24xx_uart_info) {
2177 .name = "Samsung S3C2410 UART",
2178 .type = PORT_S3C2410,
2179 .fifosize = 16,
2180 .rx_fifomask = S3C2410_UFSTAT_RXMASK,
2181 .rx_fifoshift = S3C2410_UFSTAT_RXSHIFT,
2182 .rx_fifofull = S3C2410_UFSTAT_RXFULL,
2183 .tx_fifofull = S3C2410_UFSTAT_TXFULL,
2184 .tx_fifomask = S3C2410_UFSTAT_TXMASK,
2185 .tx_fifoshift = S3C2410_UFSTAT_TXSHIFT,
2186 .def_clk_sel = S3C2410_UCON_CLKSEL0,
2187 .num_clks = 2,
2188 .clksel_mask = S3C2410_UCON_CLKMASK,
2189 .clksel_shift = S3C2410_UCON_CLKSHIFT,
2190 },
2191 .def_cfg = &(struct s3c2410_uartcfg) {
2192 .ucon = S3C2410_UCON_DEFAULT,
2193 .ufcon = S3C2410_UFCON_DEFAULT,
2194 },
2195};
2196#define S3C2410_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2410_serial_drv_data)
2197#else
2198#define S3C2410_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2199#endif
b497549a 2200
da121506
TA		 2201#ifdef CONFIG_CPU_S3C2412
2202static struct s3c24xx_serial_drv_data s3c2412_serial_drv_data = {
2203 .info = &(struct s3c24xx_uart_info) {
2204 .name = "Samsung S3C2412 UART",
2205 .type = PORT_S3C2412,
2206 .fifosize = 64,
2207 .has_divslot = 1,
2208 .rx_fifomask = S3C2440_UFSTAT_RXMASK,
2209 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
2210 .rx_fifofull = S3C2440_UFSTAT_RXFULL,
2211 .tx_fifofull = S3C2440_UFSTAT_TXFULL,
2212 .tx_fifomask = S3C2440_UFSTAT_TXMASK,
2213 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
2214 .def_clk_sel = S3C2410_UCON_CLKSEL2,
2215 .num_clks = 4,
2216 .clksel_mask = S3C2412_UCON_CLKMASK,
2217 .clksel_shift = S3C2412_UCON_CLKSHIFT,
2218 },
2219 .def_cfg = &(struct s3c2410_uartcfg) {
2220 .ucon = S3C2410_UCON_DEFAULT,
2221 .ufcon = S3C2410_UFCON_DEFAULT,
2222 },
2223};
2224#define S3C2412_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2412_serial_drv_data)
2225#else
2226#define S3C2412_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2227#endif
b497549a 2228
da121506 2229#if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2416) || \
b26469a8 2230 defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2442)
da121506
TA		 2231static struct s3c24xx_serial_drv_data s3c2440_serial_drv_data = {
2232 .info = &(struct s3c24xx_uart_info) {
2233 .name = "Samsung S3C2440 UART",
2234 .type = PORT_S3C2440,
2235 .fifosize = 64,
2236 .has_divslot = 1,
2237 .rx_fifomask = S3C2440_UFSTAT_RXMASK,
2238 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
2239 .rx_fifofull = S3C2440_UFSTAT_RXFULL,
2240 .tx_fifofull = S3C2440_UFSTAT_TXFULL,
2241 .tx_fifomask = S3C2440_UFSTAT_TXMASK,
2242 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
2243 .def_clk_sel = S3C2410_UCON_CLKSEL2,
2244 .num_clks = 4,
2245 .clksel_mask = S3C2412_UCON_CLKMASK,
2246 .clksel_shift = S3C2412_UCON_CLKSHIFT,
2247 },
2248 .def_cfg = &(struct s3c2410_uartcfg) {
2249 .ucon = S3C2410_UCON_DEFAULT,
2250 .ufcon = S3C2410_UFCON_DEFAULT,
2251 },
2252};
2253#define S3C2440_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2440_serial_drv_data)
2254#else
2255#define S3C2440_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2256#endif
b497549a 2257
953b53a7 2258#if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
da121506
TA		 2259static struct s3c24xx_serial_drv_data s3c6400_serial_drv_data = {
2260 .info = &(struct s3c24xx_uart_info) {
2261 .name = "Samsung S3C6400 UART",
2262 .type = PORT_S3C6400,
2263 .fifosize = 64,
2264 .has_divslot = 1,
2265 .rx_fifomask = S3C2440_UFSTAT_RXMASK,
2266 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
2267 .rx_fifofull = S3C2440_UFSTAT_RXFULL,
2268 .tx_fifofull = S3C2440_UFSTAT_TXFULL,
2269 .tx_fifomask = S3C2440_UFSTAT_TXMASK,
2270 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
2271 .def_clk_sel = S3C2410_UCON_CLKSEL2,
2272 .num_clks = 4,
2273 .clksel_mask = S3C6400_UCON_CLKMASK,
2274 .clksel_shift = S3C6400_UCON_CLKSHIFT,
2275 },
2276 .def_cfg = &(struct s3c2410_uartcfg) {
2277 .ucon = S3C2410_UCON_DEFAULT,
2278 .ufcon = S3C2410_UFCON_DEFAULT,
2279 },
2280};
2281#define S3C6400_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c6400_serial_drv_data)
2282#else
2283#define S3C6400_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2284#endif
b497549a 2285
da121506
TA		 2286#ifdef CONFIG_CPU_S5PV210
2287static struct s3c24xx_serial_drv_data s5pv210_serial_drv_data = {
2288 .info = &(struct s3c24xx_uart_info) {
2289 .name = "Samsung S5PV210 UART",
2290 .type = PORT_S3C6400,
2291 .has_divslot = 1,
2292 .rx_fifomask = S5PV210_UFSTAT_RXMASK,
2293 .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT,
2294 .rx_fifofull = S5PV210_UFSTAT_RXFULL,
2295 .tx_fifofull = S5PV210_UFSTAT_TXFULL,
2296 .tx_fifomask = S5PV210_UFSTAT_TXMASK,
2297 .tx_fifoshift = S5PV210_UFSTAT_TXSHIFT,
2298 .def_clk_sel = S3C2410_UCON_CLKSEL0,
2299 .num_clks = 2,
2300 .clksel_mask = S5PV210_UCON_CLKMASK,
2301 .clksel_shift = S5PV210_UCON_CLKSHIFT,
2302 },
2303 .def_cfg = &(struct s3c2410_uartcfg) {
2304 .ucon = S5PV210_UCON_DEFAULT,
2305 .ufcon = S5PV210_UFCON_DEFAULT,
2306 },
2307 .fifosize = { 256, 64, 16, 16 },
2308};
2309#define S5PV210_SERIAL_DRV_DATA ((kernel_ulong_t)&s5pv210_serial_drv_data)
2310#else
2311#define S5PV210_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2312#endif
b497549a 2313
33f88136 2314#if defined(CONFIG_ARCH_EXYNOS)
31ec77ac
CC		 2315#define EXYNOS_COMMON_SERIAL_DRV_DATA \
2316 .info = &(struct s3c24xx_uart_info) { \
2317 .name = "Samsung Exynos UART", \
2318 .type = PORT_S3C6400, \
2319 .has_divslot = 1, \
2320 .rx_fifomask = S5PV210_UFSTAT_RXMASK, \
2321 .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT, \
2322 .rx_fifofull = S5PV210_UFSTAT_RXFULL, \
2323 .tx_fifofull = S5PV210_UFSTAT_TXFULL, \
2324 .tx_fifomask = S5PV210_UFSTAT_TXMASK, \
2325 .tx_fifoshift = S5PV210_UFSTAT_TXSHIFT, \
2326 .def_clk_sel = S3C2410_UCON_CLKSEL0, \
2327 .num_clks = 1, \
2328 .clksel_mask = 0, \
2329 .clksel_shift = 0, \
2330 }, \
2331 .def_cfg = &(struct s3c2410_uartcfg) { \
2332 .ucon = S5PV210_UCON_DEFAULT, \
2333 .ufcon = S5PV210_UFCON_DEFAULT, \
2334 .has_fracval = 1, \
2335 } \
2336
da121506 2337static struct s3c24xx_serial_drv_data exynos4210_serial_drv_data = {
31ec77ac 2338 EXYNOS_COMMON_SERIAL_DRV_DATA,
da121506
TA		 2339 .fifosize = { 256, 64, 16, 16 },
2340};
31ec77ac
CC		 2341
2342static struct s3c24xx_serial_drv_data exynos5433_serial_drv_data = {
2343 EXYNOS_COMMON_SERIAL_DRV_DATA,
2344 .fifosize = { 64, 256, 16, 256 },
2345};
2346
da121506 2347#define EXYNOS4210_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos4210_serial_drv_data)
31ec77ac 2348#define EXYNOS5433_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos5433_serial_drv_data)
da121506
TA		 2349#else
2350#define EXYNOS4210_SERIAL_DRV_DATA (kernel_ulong_t)NULL
31ec77ac 2351#define EXYNOS5433_SERIAL_DRV_DATA (kernel_ulong_t)NULL
da121506 2352#endif
b497549a 2353
24ee4df1 2354static const struct platform_device_id s3c24xx_serial_driver_ids[] = {
da121506
TA		 2355 {
2356 .name = "s3c2410-uart",
2357 .driver_data = S3C2410_SERIAL_DRV_DATA,
2358 }, {
2359 .name = "s3c2412-uart",
2360 .driver_data = S3C2412_SERIAL_DRV_DATA,
2361 }, {
2362 .name = "s3c2440-uart",
2363 .driver_data = S3C2440_SERIAL_DRV_DATA,
2364 }, {
2365 .name = "s3c6400-uart",
2366 .driver_data = S3C6400_SERIAL_DRV_DATA,
2367 }, {
2368 .name = "s5pv210-uart",
2369 .driver_data = S5PV210_SERIAL_DRV_DATA,
2370 }, {
2371 .name = "exynos4210-uart",
2372 .driver_data = EXYNOS4210_SERIAL_DRV_DATA,
31ec77ac
CC		 2373 }, {
2374 .name = "exynos5433-uart",
2375 .driver_data = EXYNOS5433_SERIAL_DRV_DATA,
da121506
TA		 2376 },
2377 { },
2378};
2379MODULE_DEVICE_TABLE(platform, s3c24xx_serial_driver_ids);
2380
26c919e1
TA		 2381#ifdef CONFIG_OF
2382static const struct of_device_id s3c24xx_uart_dt_match[] = {
666ca0b9
HS		 2383 { .compatible = "samsung,s3c2410-uart",
2384 .data = (void *)S3C2410_SERIAL_DRV_DATA },
2385 { .compatible = "samsung,s3c2412-uart",
2386 .data = (void *)S3C2412_SERIAL_DRV_DATA },
2387 { .compatible = "samsung,s3c2440-uart",
2388 .data = (void *)S3C2440_SERIAL_DRV_DATA },
2389 { .compatible = "samsung,s3c6400-uart",
2390 .data = (void *)S3C6400_SERIAL_DRV_DATA },
2391 { .compatible = "samsung,s5pv210-uart",
2392 .data = (void *)S5PV210_SERIAL_DRV_DATA },
26c919e1 2393 { .compatible = "samsung,exynos4210-uart",
a169a888 2394 .data = (void *)EXYNOS4210_SERIAL_DRV_DATA },
31ec77ac
CC		 2395 { .compatible = "samsung,exynos5433-uart",
2396 .data = (void *)EXYNOS5433_SERIAL_DRV_DATA },
26c919e1
TA		 2397 {},
2398};
2399MODULE_DEVICE_TABLE(of, s3c24xx_uart_dt_match);
26c919e1
TA		 2400#endif
2401
da121506
TA		 2402static struct platform_driver samsung_serial_driver = {
2403 .probe = s3c24xx_serial_probe,
2d47b716 2404 .remove = s3c24xx_serial_remove,
da121506
TA		 2405 .id_table = s3c24xx_serial_driver_ids,
2406 .driver = {
2407 .name = "samsung-uart",
da121506 2408 .pm = SERIAL_SAMSUNG_PM_OPS,
905f4ba2 2409 .of_match_table = of_match_ptr(s3c24xx_uart_dt_match),
da121506
TA		 2410 },
2411};
b497549a 2412
6f134c3c 2413module_platform_driver(samsung_serial_driver);
b497549a 2414
c3bda295 2415#ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
b94ba032
TF		 2416/*
2417 * Early console.
2418 */
2419
2420struct samsung_early_console_data {
2421 u32 txfull_mask;
2422};
2423
2424static void samsung_early_busyuart(struct uart_port *port)
2425{
2426 while (!(readl(port->membase + S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXFE))
2427 ;
2428}
2429
2430static void samsung_early_busyuart_fifo(struct uart_port *port)
2431{
2432 struct samsung_early_console_data *data = port->private_data;
2433
2434 while (readl(port->membase + S3C2410_UFSTAT) & data->txfull_mask)
2435 ;
2436}
2437
2438static void samsung_early_putc(struct uart_port *port, int c)
2439{
2440 if (readl(port->membase + S3C2410_UFCON) & S3C2410_UFCON_FIFOMODE)
2441 samsung_early_busyuart_fifo(port);
2442 else
2443 samsung_early_busyuart(port);
2444
2445 writeb(c, port->membase + S3C2410_UTXH);
2446}
2447
2448static void samsung_early_write(struct console *con, const char *s, unsigned n)
2449{
2450 struct earlycon_device *dev = con->data;
2451
2452 uart_console_write(&dev->port, s, n, samsung_early_putc);
2453}
2454
2455static int __init samsung_early_console_setup(struct earlycon_device *device,
2456 const char *opt)
2457{
2458 if (!device->port.membase)
2459 return -ENODEV;
2460
2461 device->con->write = samsung_early_write;
2462 return 0;
2463}
2464
2465/* S3C2410 */
2466static struct samsung_early_console_data s3c2410_early_console_data = {
2467 .txfull_mask = S3C2410_UFSTAT_TXFULL,
2468};
2469
2470static int __init s3c2410_early_console_setup(struct earlycon_device *device,
2471 const char *opt)
2472{
2473 device->port.private_data = &s3c2410_early_console_data;
2474 return samsung_early_console_setup(device, opt);
2475}
2476OF_EARLYCON_DECLARE(s3c2410, "samsung,s3c2410-uart",
2477 s3c2410_early_console_setup);
2478EARLYCON_DECLARE(s3c2410, s3c2410_early_console_setup);
2479
2480/* S3C2412, S3C2440, S3C64xx */
2481static struct samsung_early_console_data s3c2440_early_console_data = {
2482 .txfull_mask = S3C2440_UFSTAT_TXFULL,
2483};
2484
2485static int __init s3c2440_early_console_setup(struct earlycon_device *device,
2486 const char *opt)
2487{
2488 device->port.private_data = &s3c2440_early_console_data;
2489 return samsung_early_console_setup(device, opt);
2490}
2491OF_EARLYCON_DECLARE(s3c2412, "samsung,s3c2412-uart",
2492 s3c2440_early_console_setup);
2493OF_EARLYCON_DECLARE(s3c2440, "samsung,s3c2440-uart",
2494 s3c2440_early_console_setup);
2495OF_EARLYCON_DECLARE(s3c6400, "samsung,s3c6400-uart",
2496 s3c2440_early_console_setup);
2497EARLYCON_DECLARE(s3c2412, s3c2440_early_console_setup);
2498EARLYCON_DECLARE(s3c2440, s3c2440_early_console_setup);
2499EARLYCON_DECLARE(s3c6400, s3c2440_early_console_setup);
2500
2501/* S5PV210, EXYNOS */
2502static struct samsung_early_console_data s5pv210_early_console_data = {
2503 .txfull_mask = S5PV210_UFSTAT_TXFULL,
2504};
2505
2506static int __init s5pv210_early_console_setup(struct earlycon_device *device,
2507 const char *opt)
2508{
2509 device->port.private_data = &s5pv210_early_console_data;
2510 return samsung_early_console_setup(device, opt);
2511}
2512OF_EARLYCON_DECLARE(s5pv210, "samsung,s5pv210-uart",
2513 s5pv210_early_console_setup);
2514OF_EARLYCON_DECLARE(exynos4210, "samsung,exynos4210-uart",
2515 s5pv210_early_console_setup);
2516EARLYCON_DECLARE(s5pv210, s5pv210_early_console_setup);
2517EARLYCON_DECLARE(exynos4210, s5pv210_early_console_setup);
c3bda295 2518#endif
b94ba032 2519
da121506 2520MODULE_ALIAS("platform:samsung-uart");
b497549a
BD		 2521MODULE_DESCRIPTION("Samsung SoC Serial port driver");
2522MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
2523MODULE_LICENSE("GPL v2");
Linux 6.x block layer and io_uring tree(s)