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tty: add SPDX identifiers to all remaining files in drivers/tty/
[linux-block.git] / drivers / tty / serial / samsung.c
CommitLineData
e3b3d0f5 1// SPDX-License-Identifier: GPL-2.0
99edb3d1 2/*
b497549a
BD		 3 * Driver core for Samsung SoC onboard UARTs.
4 *
ccae941e 5 * Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics
b497549a
BD		 6 * http://armlinux.simtec.co.uk/
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13/* Hote on 2410 error handling
14 *
15 * The s3c2410 manual has a love/hate affair with the contents of the
16 * UERSTAT register in the UART blocks, and keeps marking some of the
17 * error bits as reserved. Having checked with the s3c2410x01,
18 * it copes with BREAKs properly, so I am happy to ignore the RESERVED
19 * feature from the latter versions of the manual.
20 *
21 * If it becomes aparrent that latter versions of the 2410 remove these
22 * bits, then action will have to be taken to differentiate the versions
23 * and change the policy on BREAK
24 *
25 * BJD, 04-Nov-2004
26*/
27
28#if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
29#define SUPPORT_SYSRQ
30#endif
31
62c37eed
RB		 32#include <linux/dmaengine.h>
33#include <linux/dma-mapping.h>
34#include <linux/slab.h>
b497549a
BD		 35#include <linux/module.h>
36#include <linux/ioport.h>
37#include <linux/io.h>
38#include <linux/platform_device.h>
39#include <linux/init.h>
40#include <linux/sysrq.h>
41#include <linux/console.h>
42#include <linux/tty.h>
43#include <linux/tty_flip.h>
44#include <linux/serial_core.h>
45#include <linux/serial.h>
9ee51f01 46#include <linux/serial_s3c.h>
b497549a
BD		 47#include <linux/delay.h>
48#include <linux/clk.h>
30555476 49#include <linux/cpufreq.h>
26c919e1 50#include <linux/of.h>
b497549a
BD		 51
52#include <asm/irq.h>
53
b497549a
BD		 54#include "samsung.h"
55
e4ac92df 56#if defined(CONFIG_SERIAL_SAMSUNG_DEBUG) && \
e4ac92df
JP		 57 !defined(MODULE)
58
59extern void printascii(const char *);
60
61__printf(1, 2)
62static void dbg(const char *fmt, ...)
63{
64 va_list va;
65 char buff[256];
66
67 va_start(va, fmt);
a859c8b2 68 vscnprintf(buff, sizeof(buff), fmt, va);
e4ac92df
JP		 69 va_end(va);
70
71 printascii(buff);
72}
73
74#else
75#define dbg(fmt, ...) do { if (0) no_printk(fmt, ##__VA_ARGS__); } while (0)
76#endif
77
b497549a
BD		 78/* UART name and device definitions */
79
80#define S3C24XX_SERIAL_NAME "ttySAC"
81#define S3C24XX_SERIAL_MAJOR 204
82#define S3C24XX_SERIAL_MINOR 64
83
29bef799
RB		 84#define S3C24XX_TX_PIO 1
85#define S3C24XX_TX_DMA 2
b543c301
RB		 86#define S3C24XX_RX_PIO 1
87#define S3C24XX_RX_DMA 2
b497549a
BD		 88/* macros to change one thing to another */
89
90#define tx_enabled(port) ((port)->unused[0])
91#define rx_enabled(port) ((port)->unused[1])
92
25985edc 93/* flag to ignore all characters coming in */
b497549a
BD		 94#define RXSTAT_DUMMY_READ (0x10000000)
95
96static inline struct s3c24xx_uart_port *to_ourport(struct uart_port *port)
97{
98 return container_of(port, struct s3c24xx_uart_port, port);
99}
100
101/* translate a port to the device name */
102
103static inline const char *s3c24xx_serial_portname(struct uart_port *port)
104{
105 return to_platform_device(port->dev)->name;
106}
107
108static int s3c24xx_serial_txempty_nofifo(struct uart_port *port)
109{
9303ac15 110 return rd_regl(port, S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE;
b497549a
BD		 111}
112
88bb4ea1
TA		 113/*
114 * s3c64xx and later SoC's include the interrupt mask and status registers in
115 * the controller itself, unlike the s3c24xx SoC's which have these registers
116 * in the interrupt controller. Check if the port type is s3c64xx or higher.
117 */
118static int s3c24xx_serial_has_interrupt_mask(struct uart_port *port)
119{
120 return to_ourport(port)->info->type == PORT_S3C6400;
121}
122
b497549a
BD		 123static void s3c24xx_serial_rx_enable(struct uart_port *port)
124{
125 unsigned long flags;
126 unsigned int ucon, ufcon;
127 int count = 10000;
128
129 spin_lock_irqsave(&port->lock, flags);
130
131 while (--count && !s3c24xx_serial_txempty_nofifo(port))
132 udelay(100);
133
134 ufcon = rd_regl(port, S3C2410_UFCON);
135 ufcon |= S3C2410_UFCON_RESETRX;
136 wr_regl(port, S3C2410_UFCON, ufcon);
137
138 ucon = rd_regl(port, S3C2410_UCON);
139 ucon |= S3C2410_UCON_RXIRQMODE;
140 wr_regl(port, S3C2410_UCON, ucon);
141
142 rx_enabled(port) = 1;
143 spin_unlock_irqrestore(&port->lock, flags);
144}
145
146static void s3c24xx_serial_rx_disable(struct uart_port *port)
147{
148 unsigned long flags;
149 unsigned int ucon;
150
151 spin_lock_irqsave(&port->lock, flags);
152
153 ucon = rd_regl(port, S3C2410_UCON);
154 ucon &= ~S3C2410_UCON_RXIRQMODE;
155 wr_regl(port, S3C2410_UCON, ucon);
156
157 rx_enabled(port) = 0;
158 spin_unlock_irqrestore(&port->lock, flags);
159}
160
161static void s3c24xx_serial_stop_tx(struct uart_port *port)
162{
b73c289c 163 struct s3c24xx_uart_port *ourport = to_ourport(port);
29bef799
RB		 164 struct s3c24xx_uart_dma *dma = ourport->dma;
165 struct circ_buf *xmit = &port->state->xmit;
166 struct dma_tx_state state;
167 int count;
b73c289c 168
29bef799
RB		 169 if (!tx_enabled(port))
170 return;
171
172 if (s3c24xx_serial_has_interrupt_mask(port))
bbb5ff91 173 s3c24xx_set_bit(port, S3C64XX_UINTM_TXD, S3C64XX_UINTM);
29bef799
RB		 174 else
175 disable_irq_nosync(ourport->tx_irq);
176
177 if (dma && dma->tx_chan && ourport->tx_in_progress == S3C24XX_TX_DMA) {
178 dmaengine_pause(dma->tx_chan);
179 dmaengine_tx_status(dma->tx_chan, dma->tx_cookie, &state);
180 dmaengine_terminate_all(dma->tx_chan);
181 dma_sync_single_for_cpu(ourport->port.dev,
182 dma->tx_transfer_addr, dma->tx_size, DMA_TO_DEVICE);
183 async_tx_ack(dma->tx_desc);
184 count = dma->tx_bytes_requested - state.residue;
185 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
186 port->icount.tx += count;
b497549a 187 }
29bef799
RB		 188
189 tx_enabled(port) = 0;
190 ourport->tx_in_progress = 0;
191
192 if (port->flags & UPF_CONS_FLOW)
193 s3c24xx_serial_rx_enable(port);
194
195 ourport->tx_mode = 0;
196}
197
198static void s3c24xx_serial_start_next_tx(struct s3c24xx_uart_port *ourport);
199
200static void s3c24xx_serial_tx_dma_complete(void *args)
201{
202 struct s3c24xx_uart_port *ourport = args;
203 struct uart_port *port = &ourport->port;
204 struct circ_buf *xmit = &port->state->xmit;
205 struct s3c24xx_uart_dma *dma = ourport->dma;
206 struct dma_tx_state state;
207 unsigned long flags;
208 int count;
209
210
211 dmaengine_tx_status(dma->tx_chan, dma->tx_cookie, &state);
212 count = dma->tx_bytes_requested - state.residue;
213 async_tx_ack(dma->tx_desc);
214
215 dma_sync_single_for_cpu(ourport->port.dev, dma->tx_transfer_addr,
216 dma->tx_size, DMA_TO_DEVICE);
217
218 spin_lock_irqsave(&port->lock, flags);
219
220 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
221 port->icount.tx += count;
222 ourport->tx_in_progress = 0;
223
224 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
225 uart_write_wakeup(port);
226
227 s3c24xx_serial_start_next_tx(ourport);
228 spin_unlock_irqrestore(&port->lock, flags);
229}
230
231static void enable_tx_dma(struct s3c24xx_uart_port *ourport)
232{
233 struct uart_port *port = &ourport->port;
234 u32 ucon;
235
236 /* Mask Tx interrupt */
237 if (s3c24xx_serial_has_interrupt_mask(port))
bbb5ff91 238 s3c24xx_set_bit(port, S3C64XX_UINTM_TXD, S3C64XX_UINTM);
29bef799
RB		 239 else
240 disable_irq_nosync(ourport->tx_irq);
241
242 /* Enable tx dma mode */
243 ucon = rd_regl(port, S3C2410_UCON);
244 ucon &= ~(S3C64XX_UCON_TXBURST_MASK | S3C64XX_UCON_TXMODE_MASK);
245 ucon |= (dma_get_cache_alignment() >= 16) ?
246 S3C64XX_UCON_TXBURST_16 : S3C64XX_UCON_TXBURST_1;
247 ucon |= S3C64XX_UCON_TXMODE_DMA;
248 wr_regl(port, S3C2410_UCON, ucon);
249
250 ourport->tx_mode = S3C24XX_TX_DMA;
251}
252
253static void enable_tx_pio(struct s3c24xx_uart_port *ourport)
254{
255 struct uart_port *port = &ourport->port;
256 u32 ucon, ufcon;
257
258 /* Set ufcon txtrig */
259 ourport->tx_in_progress = S3C24XX_TX_PIO;
260 ufcon = rd_regl(port, S3C2410_UFCON);
261 wr_regl(port, S3C2410_UFCON, ufcon);
262
263 /* Enable tx pio mode */
264 ucon = rd_regl(port, S3C2410_UCON);
265 ucon &= ~(S3C64XX_UCON_TXMODE_MASK);
266 ucon |= S3C64XX_UCON_TXMODE_CPU;
267 wr_regl(port, S3C2410_UCON, ucon);
268
269 /* Unmask Tx interrupt */
270 if (s3c24xx_serial_has_interrupt_mask(port))
bbb5ff91
ML		 271 s3c24xx_clear_bit(port, S3C64XX_UINTM_TXD,
272 S3C64XX_UINTM);
29bef799
RB		 273 else
274 enable_irq(ourport->tx_irq);
275
276 ourport->tx_mode = S3C24XX_TX_PIO;
277}
278
279static void s3c24xx_serial_start_tx_pio(struct s3c24xx_uart_port *ourport)
280{
281 if (ourport->tx_mode != S3C24XX_TX_PIO)
282 enable_tx_pio(ourport);
b497549a
BD		 283}
284
29bef799
RB		 285static int s3c24xx_serial_start_tx_dma(struct s3c24xx_uart_port *ourport,
286 unsigned int count)
287{
288 struct uart_port *port = &ourport->port;
289 struct circ_buf *xmit = &port->state->xmit;
290 struct s3c24xx_uart_dma *dma = ourport->dma;
291
292
293 if (ourport->tx_mode != S3C24XX_TX_DMA)
294 enable_tx_dma(ourport);
295
29bef799
RB		 296 dma->tx_size = count & ~(dma_get_cache_alignment() - 1);
297 dma->tx_transfer_addr = dma->tx_addr + xmit->tail;
298
299 dma_sync_single_for_device(ourport->port.dev, dma->tx_transfer_addr,
300 dma->tx_size, DMA_TO_DEVICE);
301
302 dma->tx_desc = dmaengine_prep_slave_single(dma->tx_chan,
303 dma->tx_transfer_addr, dma->tx_size,
304 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
305 if (!dma->tx_desc) {
306 dev_err(ourport->port.dev, "Unable to get desc for Tx\n");
307 return -EIO;
308 }
309
310 dma->tx_desc->callback = s3c24xx_serial_tx_dma_complete;
311 dma->tx_desc->callback_param = ourport;
312 dma->tx_bytes_requested = dma->tx_size;
313
314 ourport->tx_in_progress = S3C24XX_TX_DMA;
315 dma->tx_cookie = dmaengine_submit(dma->tx_desc);
316 dma_async_issue_pending(dma->tx_chan);
317 return 0;
318}
319
320static void s3c24xx_serial_start_next_tx(struct s3c24xx_uart_port *ourport)
321{
322 struct uart_port *port = &ourport->port;
323 struct circ_buf *xmit = &port->state->xmit;
324 unsigned long count;
325
326 /* Get data size up to the end of buffer */
327 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
328
329 if (!count) {
330 s3c24xx_serial_stop_tx(port);
331 return;
332 }
333
81ccb2a6 334 if (!ourport->dma || !ourport->dma->tx_chan ||
736cd79f
RB		 335 count < ourport->min_dma_size ||
336 xmit->tail & (dma_get_cache_alignment() - 1))
29bef799
RB		 337 s3c24xx_serial_start_tx_pio(ourport);
338 else
339 s3c24xx_serial_start_tx_dma(ourport, count);
340}
341
75781979 342static void s3c24xx_serial_start_tx(struct uart_port *port)
b497549a 343{
b73c289c 344 struct s3c24xx_uart_port *ourport = to_ourport(port);
29bef799 345 struct circ_buf *xmit = &port->state->xmit;
b73c289c 346
b497549a
BD		 347 if (!tx_enabled(port)) {
348 if (port->flags & UPF_CONS_FLOW)
349 s3c24xx_serial_rx_disable(port);
350
b497549a 351 tx_enabled(port) = 1;
ba019a3e 352 if (!ourport->dma || !ourport->dma->tx_chan)
29bef799 353 s3c24xx_serial_start_tx_pio(ourport);
29bef799
RB		 354 }
355
356 if (ourport->dma && ourport->dma->tx_chan) {
357 if (!uart_circ_empty(xmit) && !ourport->tx_in_progress)
358 s3c24xx_serial_start_next_tx(ourport);
b497549a
BD		 359 }
360}
361
b543c301
RB		 362static void s3c24xx_uart_copy_rx_to_tty(struct s3c24xx_uart_port *ourport,
363 struct tty_port *tty, int count)
364{
365 struct s3c24xx_uart_dma *dma = ourport->dma;
366 int copied;
367
368 if (!count)
369 return;
370
371 dma_sync_single_for_cpu(ourport->port.dev, dma->rx_addr,
372 dma->rx_size, DMA_FROM_DEVICE);
373
374 ourport->port.icount.rx += count;
375 if (!tty) {
376 dev_err(ourport->port.dev, "No tty port\n");
377 return;
378 }
379 copied = tty_insert_flip_string(tty,
380 ((unsigned char *)(ourport->dma->rx_buf)), count);
381 if (copied != count) {
382 WARN_ON(1);
383 dev_err(ourport->port.dev, "RxData copy to tty layer failed\n");
384 }
385}
386
b497549a
BD		 387static void s3c24xx_serial_stop_rx(struct uart_port *port)
388{
b73c289c 389 struct s3c24xx_uart_port *ourport = to_ourport(port);
b543c301
RB		 390 struct s3c24xx_uart_dma *dma = ourport->dma;
391 struct tty_port *t = &port->state->port;
392 struct dma_tx_state state;
393 enum dma_status dma_status;
394 unsigned int received;
b73c289c 395
b497549a
BD		 396 if (rx_enabled(port)) {
397 dbg("s3c24xx_serial_stop_rx: port=%p\n", port);
88bb4ea1 398 if (s3c24xx_serial_has_interrupt_mask(port))
bbb5ff91
ML		 399 s3c24xx_set_bit(port, S3C64XX_UINTM_RXD,
400 S3C64XX_UINTM);
88bb4ea1
TA		 401 else
402 disable_irq_nosync(ourport->rx_irq);
b497549a
BD		 403 rx_enabled(port) = 0;
404 }
b543c301
RB		 405 if (dma && dma->rx_chan) {
406 dmaengine_pause(dma->tx_chan);
407 dma_status = dmaengine_tx_status(dma->rx_chan,
408 dma->rx_cookie, &state);
409 if (dma_status == DMA_IN_PROGRESS ||
410 dma_status == DMA_PAUSED) {
411 received = dma->rx_bytes_requested - state.residue;
412 dmaengine_terminate_all(dma->rx_chan);
413 s3c24xx_uart_copy_rx_to_tty(ourport, t, received);
414 }
415 }
b497549a
BD		 416}
417
ef4aca70
RB		 418static inline struct s3c24xx_uart_info
419 *s3c24xx_port_to_info(struct uart_port *port)
b497549a
BD		 420{
421 return to_ourport(port)->info;
422}
423
ef4aca70
RB		 424static inline struct s3c2410_uartcfg
425 *s3c24xx_port_to_cfg(struct uart_port *port)
b497549a 426{
4d84e970
TA		 427 struct s3c24xx_uart_port *ourport;
428
b497549a
BD		 429 if (port->dev == NULL)
430 return NULL;
431
4d84e970
TA		 432 ourport = container_of(port, struct s3c24xx_uart_port, port);
433 return ourport->cfg;
b497549a
BD		 434}
435
436static int s3c24xx_serial_rx_fifocnt(struct s3c24xx_uart_port *ourport,
437 unsigned long ufstat)
438{
439 struct s3c24xx_uart_info *info = ourport->info;
440
441 if (ufstat & info->rx_fifofull)
da121506 442 return ourport->port.fifosize;
b497549a
BD		 443
444 return (ufstat & info->rx_fifomask) >> info->rx_fifoshift;
445}
446
b543c301
RB		 447static void s3c64xx_start_rx_dma(struct s3c24xx_uart_port *ourport);
448static void s3c24xx_serial_rx_dma_complete(void *args)
449{
450 struct s3c24xx_uart_port *ourport = args;
451 struct uart_port *port = &ourport->port;
452
453 struct s3c24xx_uart_dma *dma = ourport->dma;
454 struct tty_port *t = &port->state->port;
455 struct tty_struct *tty = tty_port_tty_get(&ourport->port.state->port);
456
457 struct dma_tx_state state;
458 unsigned long flags;
459 int received;
460
461 dmaengine_tx_status(dma->rx_chan, dma->rx_cookie, &state);
462 received = dma->rx_bytes_requested - state.residue;
463 async_tx_ack(dma->rx_desc);
464
465 spin_lock_irqsave(&port->lock, flags);
466
467 if (received)
468 s3c24xx_uart_copy_rx_to_tty(ourport, t, received);
469
470 if (tty) {
471 tty_flip_buffer_push(t);
472 tty_kref_put(tty);
473 }
474
475 s3c64xx_start_rx_dma(ourport);
476
477 spin_unlock_irqrestore(&port->lock, flags);
478}
479
480static void s3c64xx_start_rx_dma(struct s3c24xx_uart_port *ourport)
481{
482 struct s3c24xx_uart_dma *dma = ourport->dma;
483
484 dma_sync_single_for_device(ourport->port.dev, dma->rx_addr,
485 dma->rx_size, DMA_FROM_DEVICE);
486
487 dma->rx_desc = dmaengine_prep_slave_single(dma->rx_chan,
488 dma->rx_addr, dma->rx_size, DMA_DEV_TO_MEM,
489 DMA_PREP_INTERRUPT);
490 if (!dma->rx_desc) {
491 dev_err(ourport->port.dev, "Unable to get desc for Rx\n");
492 return;
493 }
494
495 dma->rx_desc->callback = s3c24xx_serial_rx_dma_complete;
496 dma->rx_desc->callback_param = ourport;
497 dma->rx_bytes_requested = dma->rx_size;
498
499 dma->rx_cookie = dmaengine_submit(dma->rx_desc);
500 dma_async_issue_pending(dma->rx_chan);
501}
b497549a
BD		 502
503/* ? - where has parity gone?? */
504#define S3C2410_UERSTAT_PARITY (0x1000)
505
b543c301
RB		 506static void enable_rx_dma(struct s3c24xx_uart_port *ourport)
507{
508 struct uart_port *port = &ourport->port;
509 unsigned int ucon;
510
511 /* set Rx mode to DMA mode */
512 ucon = rd_regl(port, S3C2410_UCON);
513 ucon &= ~(S3C64XX_UCON_RXBURST_MASK |
514 S3C64XX_UCON_TIMEOUT_MASK |
515 S3C64XX_UCON_EMPTYINT_EN |
516 S3C64XX_UCON_DMASUS_EN |
517 S3C64XX_UCON_TIMEOUT_EN |
518 S3C64XX_UCON_RXMODE_MASK);
519 ucon |= S3C64XX_UCON_RXBURST_16 |
520 0xf << S3C64XX_UCON_TIMEOUT_SHIFT |
521 S3C64XX_UCON_EMPTYINT_EN |
522 S3C64XX_UCON_TIMEOUT_EN |
523 S3C64XX_UCON_RXMODE_DMA;
524 wr_regl(port, S3C2410_UCON, ucon);
525
526 ourport->rx_mode = S3C24XX_RX_DMA;
527}
528
529static void enable_rx_pio(struct s3c24xx_uart_port *ourport)
530{
531 struct uart_port *port = &ourport->port;
532 unsigned int ucon;
533
534 /* set Rx mode to DMA mode */
535 ucon = rd_regl(port, S3C2410_UCON);
536 ucon &= ~(S3C64XX_UCON_TIMEOUT_MASK |
537 S3C64XX_UCON_EMPTYINT_EN |
538 S3C64XX_UCON_DMASUS_EN |
539 S3C64XX_UCON_TIMEOUT_EN |
540 S3C64XX_UCON_RXMODE_MASK);
541 ucon |= 0xf << S3C64XX_UCON_TIMEOUT_SHIFT |
542 S3C64XX_UCON_TIMEOUT_EN |
543 S3C64XX_UCON_RXMODE_CPU;
544 wr_regl(port, S3C2410_UCON, ucon);
545
546 ourport->rx_mode = S3C24XX_RX_PIO;
547}
548
09557c01
RB		 549static void s3c24xx_serial_rx_drain_fifo(struct s3c24xx_uart_port *ourport);
550
e4678afe 551static irqreturn_t s3c24xx_serial_rx_chars_dma(void *dev_id)
b543c301
RB		 552{
553 unsigned int utrstat, ufstat, received;
554 struct s3c24xx_uart_port *ourport = dev_id;
555 struct uart_port *port = &ourport->port;
556 struct s3c24xx_uart_dma *dma = ourport->dma;
557 struct tty_struct *tty = tty_port_tty_get(&ourport->port.state->port);
558 struct tty_port *t = &port->state->port;
559 unsigned long flags;
560 struct dma_tx_state state;
561
562 utrstat = rd_regl(port, S3C2410_UTRSTAT);
563 ufstat = rd_regl(port, S3C2410_UFSTAT);
564
565 spin_lock_irqsave(&port->lock, flags);
566
567 if (!(utrstat & S3C2410_UTRSTAT_TIMEOUT)) {
568 s3c64xx_start_rx_dma(ourport);
569 if (ourport->rx_mode == S3C24XX_RX_PIO)
570 enable_rx_dma(ourport);
571 goto finish;
572 }
573
574 if (ourport->rx_mode == S3C24XX_RX_DMA) {
575 dmaengine_pause(dma->rx_chan);
576 dmaengine_tx_status(dma->rx_chan, dma->rx_cookie, &state);
577 dmaengine_terminate_all(dma->rx_chan);
578 received = dma->rx_bytes_requested - state.residue;
579 s3c24xx_uart_copy_rx_to_tty(ourport, t, received);
580
581 enable_rx_pio(ourport);
582 }
583
09557c01 584 s3c24xx_serial_rx_drain_fifo(ourport);
b543c301
RB		 585
586 if (tty) {
587 tty_flip_buffer_push(t);
588 tty_kref_put(tty);
589 }
590
591 wr_regl(port, S3C2410_UTRSTAT, S3C2410_UTRSTAT_TIMEOUT);
592
593finish:
594 spin_unlock_irqrestore(&port->lock, flags);
595
596 return IRQ_HANDLED;
597}
598
01732dd2 599static void s3c24xx_serial_rx_drain_fifo(struct s3c24xx_uart_port *ourport)
b497549a 600{
b497549a 601 struct uart_port *port = &ourport->port;
b497549a 602 unsigned int ufcon, ch, flag, ufstat, uerstat;
aba06e92 603 unsigned int fifocnt = 0;
57850a50 604 int max_count = port->fifosize;
b497549a
BD		 605
606 while (max_count-- > 0) {
aba06e92
YN		 607 /*
608 * Receive all characters known to be in FIFO
609 * before reading FIFO level again
610 */
611 if (fifocnt == 0) {
612 ufstat = rd_regl(port, S3C2410_UFSTAT);
613 fifocnt = s3c24xx_serial_rx_fifocnt(ourport, ufstat);
614 if (fifocnt == 0)
615 break;
616 }
617 fifocnt--;
b497549a
BD		 618
619 uerstat = rd_regl(port, S3C2410_UERSTAT);
620 ch = rd_regb(port, S3C2410_URXH);
621
622 if (port->flags & UPF_CONS_FLOW) {
623 int txe = s3c24xx_serial_txempty_nofifo(port);
624
625 if (rx_enabled(port)) {
626 if (!txe) {
627 rx_enabled(port) = 0;
628 continue;
629 }
630 } else {
631 if (txe) {
aba06e92 632 ufcon = rd_regl(port, S3C2410_UFCON);
b497549a
BD		 633 ufcon |= S3C2410_UFCON_RESETRX;
634 wr_regl(port, S3C2410_UFCON, ufcon);
635 rx_enabled(port) = 1;
01732dd2 636 return;
b497549a
BD		 637 }
638 continue;
639 }
640 }
641
642 /* insert the character into the buffer */
643
644 flag = TTY_NORMAL;
645 port->icount.rx++;
646
647 if (unlikely(uerstat & S3C2410_UERSTAT_ANY)) {
648 dbg("rxerr: port ch=0x%02x, rxs=0x%08x\n",
649 ch, uerstat);
650
651 /* check for break */
652 if (uerstat & S3C2410_UERSTAT_BREAK) {
653 dbg("break!\n");
654 port->icount.brk++;
655 if (uart_handle_break(port))
620bb214 656 continue; /* Ignore character */
b497549a
BD		 657 }
658
659 if (uerstat & S3C2410_UERSTAT_FRAME)
660 port->icount.frame++;
661 if (uerstat & S3C2410_UERSTAT_OVERRUN)
662 port->icount.overrun++;
663
664 uerstat &= port->read_status_mask;
665
666 if (uerstat & S3C2410_UERSTAT_BREAK)
667 flag = TTY_BREAK;
668 else if (uerstat & S3C2410_UERSTAT_PARITY)
669 flag = TTY_PARITY;
670 else if (uerstat & (S3C2410_UERSTAT_FRAME |
671 S3C2410_UERSTAT_OVERRUN))
672 flag = TTY_FRAME;
673 }
674
675 if (uart_handle_sysrq_char(port, ch))
620bb214 676 continue; /* Ignore character */
b497549a
BD		 677
678 uart_insert_char(port, uerstat, S3C2410_UERSTAT_OVERRUN,
679 ch, flag);
b497549a 680 }
f5693ea2 681
2e124b4a 682 tty_flip_buffer_push(&port->state->port);
01732dd2
RB		 683}
684
685static irqreturn_t s3c24xx_serial_rx_chars_pio(void *dev_id)
686{
687 struct s3c24xx_uart_port *ourport = dev_id;
688 struct uart_port *port = &ourport->port;
689 unsigned long flags;
690
691 spin_lock_irqsave(&port->lock, flags);
692 s3c24xx_serial_rx_drain_fifo(ourport);
693 spin_unlock_irqrestore(&port->lock, flags);
b497549a 694
b497549a
BD		 695 return IRQ_HANDLED;
696}
697
b543c301
RB		 698
699static irqreturn_t s3c24xx_serial_rx_chars(int irq, void *dev_id)
700{
701 struct s3c24xx_uart_port *ourport = dev_id;
702
703 if (ourport->dma && ourport->dma->rx_chan)
e4678afe
RB		 704 return s3c24xx_serial_rx_chars_dma(dev_id);
705 return s3c24xx_serial_rx_chars_pio(dev_id);
b543c301
RB		 706}
707
b497549a
BD		 708static irqreturn_t s3c24xx_serial_tx_chars(int irq, void *id)
709{
710 struct s3c24xx_uart_port *ourport = id;
711 struct uart_port *port = &ourport->port;
ebd2c8f6 712 struct circ_buf *xmit = &port->state->xmit;
c15c3747 713 unsigned long flags;
736cd79f 714 int count, dma_count = 0;
b497549a 715
c15c3747
TA		 716 spin_lock_irqsave(&port->lock, flags);
717
29bef799
RB		 718 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
719
81ccb2a6
MS		 720 if (ourport->dma && ourport->dma->tx_chan &&
721 count >= ourport->min_dma_size) {
736cd79f
RB		 722 int align = dma_get_cache_alignment() -
723 (xmit->tail & (dma_get_cache_alignment() - 1));
724 if (count-align >= ourport->min_dma_size) {
725 dma_count = count-align;
726 count = align;
727 }
29bef799
RB		 728 }
729
b497549a
BD		 730 if (port->x_char) {
731 wr_regb(port, S3C2410_UTXH, port->x_char);
732 port->icount.tx++;
733 port->x_char = 0;
734 goto out;
735 }
736
25985edc 737 /* if there isn't anything more to transmit, or the uart is now
b497549a
BD		 738 * stopped, disable the uart and exit
739 */
740
741 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
742 s3c24xx_serial_stop_tx(port);
743 goto out;
744 }
745
746 /* try and drain the buffer... */
747
736cd79f
RB		 748 if (count > port->fifosize) {
749 count = port->fifosize;
750 dma_count = 0;
751 }
752
753 while (!uart_circ_empty(xmit) && count > 0) {
b497549a
BD		 754 if (rd_regl(port, S3C2410_UFSTAT) & ourport->info->tx_fifofull)
755 break;
756
757 wr_regb(port, S3C2410_UTXH, xmit->buf[xmit->tail]);
758 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
759 port->icount.tx++;
736cd79f
RB		 760 count--;
761 }
762
763 if (!count && dma_count) {
764 s3c24xx_serial_start_tx_dma(ourport, dma_count);
765 goto out;
b497549a
BD		 766 }
767
c15c3747
TA		 768 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) {
769 spin_unlock(&port->lock);
b497549a 770 uart_write_wakeup(port);
c15c3747
TA		 771 spin_lock(&port->lock);
772 }
b497549a
BD		 773
774 if (uart_circ_empty(xmit))
775 s3c24xx_serial_stop_tx(port);
776
ef4aca70 777out:
c15c3747 778 spin_unlock_irqrestore(&port->lock, flags);
b497549a
BD		 779 return IRQ_HANDLED;
780}
781
88bb4ea1
TA		 782/* interrupt handler for s3c64xx and later SoC's.*/
783static irqreturn_t s3c64xx_serial_handle_irq(int irq, void *id)
784{
785 struct s3c24xx_uart_port *ourport = id;
786 struct uart_port *port = &ourport->port;
787 unsigned int pend = rd_regl(port, S3C64XX_UINTP);
88bb4ea1
TA		 788 irqreturn_t ret = IRQ_HANDLED;
789
88bb4ea1
TA		 790 if (pend & S3C64XX_UINTM_RXD_MSK) {
791 ret = s3c24xx_serial_rx_chars(irq, id);
792 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_RXD_MSK);
793 }
794 if (pend & S3C64XX_UINTM_TXD_MSK) {
795 ret = s3c24xx_serial_tx_chars(irq, id);
796 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_TXD_MSK);
797 }
88bb4ea1
TA		 798 return ret;
799}
800
b497549a
BD		 801static unsigned int s3c24xx_serial_tx_empty(struct uart_port *port)
802{
803 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
804 unsigned long ufstat = rd_regl(port, S3C2410_UFSTAT);
805 unsigned long ufcon = rd_regl(port, S3C2410_UFCON);
806
807 if (ufcon & S3C2410_UFCON_FIFOMODE) {
808 if ((ufstat & info->tx_fifomask) != 0 ||
809 (ufstat & info->tx_fifofull))
810 return 0;
811
812 return 1;
813 }
814
815 return s3c24xx_serial_txempty_nofifo(port);
816}
817
818/* no modem control lines */
819static unsigned int s3c24xx_serial_get_mctrl(struct uart_port *port)
820{
821 unsigned int umstat = rd_regb(port, S3C2410_UMSTAT);
822
823 if (umstat & S3C2410_UMSTAT_CTS)
824 return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
825 else
826 return TIOCM_CAR | TIOCM_DSR;
827}
828
829static void s3c24xx_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
830{
2d1e5a48
JMG		 831 unsigned int umcon = rd_regl(port, S3C2410_UMCON);
832
833 if (mctrl & TIOCM_RTS)
834 umcon |= S3C2410_UMCOM_RTS_LOW;
835 else
836 umcon &= ~S3C2410_UMCOM_RTS_LOW;
837
838 wr_regl(port, S3C2410_UMCON, umcon);
b497549a
BD		 839}
840
841static void s3c24xx_serial_break_ctl(struct uart_port *port, int break_state)
842{
843 unsigned long flags;
844 unsigned int ucon;
845
846 spin_lock_irqsave(&port->lock, flags);
847
848 ucon = rd_regl(port, S3C2410_UCON);
849
850 if (break_state)
851 ucon |= S3C2410_UCON_SBREAK;
852 else
853 ucon &= ~S3C2410_UCON_SBREAK;
854
855 wr_regl(port, S3C2410_UCON, ucon);
856
857 spin_unlock_irqrestore(&port->lock, flags);
858}
859
62c37eed
RB		 860static int s3c24xx_serial_request_dma(struct s3c24xx_uart_port *p)
861{
862 struct s3c24xx_uart_dma *dma = p->dma;
500fcc08 863 int ret;
62c37eed
RB		 864
865 /* Default slave configuration parameters */
866 dma->rx_conf.direction = DMA_DEV_TO_MEM;
867 dma->rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
868 dma->rx_conf.src_addr = p->port.mapbase + S3C2410_URXH;
869 dma->rx_conf.src_maxburst = 16;
870
871 dma->tx_conf.direction = DMA_MEM_TO_DEV;
872 dma->tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
873 dma->tx_conf.dst_addr = p->port.mapbase + S3C2410_UTXH;
874 if (dma_get_cache_alignment() >= 16)
875 dma->tx_conf.dst_maxburst = 16;
876 else
877 dma->tx_conf.dst_maxburst = 1;
878
ba3d6f8f 879 dma->rx_chan = dma_request_chan(p->port.dev, "rx");
62c37eed 880
ba3d6f8f
MS		 881 if (IS_ERR(dma->rx_chan))
882 return PTR_ERR(dma->rx_chan);
62c37eed
RB		 883
884 dmaengine_slave_config(dma->rx_chan, &dma->rx_conf);
885
ba3d6f8f
MS		 886 dma->tx_chan = dma_request_chan(p->port.dev, "tx");
887 if (IS_ERR(dma->tx_chan)) {
500fcc08
MS		 888 ret = PTR_ERR(dma->tx_chan);
889 goto err_release_rx;
62c37eed
RB		 890 }
891
892 dmaengine_slave_config(dma->tx_chan, &dma->tx_conf);
893
894 /* RX buffer */
895 dma->rx_size = PAGE_SIZE;
896
897 dma->rx_buf = kmalloc(dma->rx_size, GFP_KERNEL);
62c37eed 898 if (!dma->rx_buf) {
500fcc08
MS		 899 ret = -ENOMEM;
900 goto err_release_tx;
62c37eed
RB		 901 }
902
768d64f4 903 dma->rx_addr = dma_map_single(p->port.dev, dma->rx_buf,
62c37eed 904 dma->rx_size, DMA_FROM_DEVICE);
500fcc08
MS		 905 if (dma_mapping_error(p->port.dev, dma->rx_addr)) {
906 ret = -EIO;
907 goto err_free_rx;
908 }
62c37eed 909
62c37eed 910 /* TX buffer */
768d64f4 911 dma->tx_addr = dma_map_single(p->port.dev, p->port.state->xmit.buf,
62c37eed 912 UART_XMIT_SIZE, DMA_TO_DEVICE);
500fcc08
MS		 913 if (dma_mapping_error(p->port.dev, dma->tx_addr)) {
914 ret = -EIO;
915 goto err_unmap_rx;
916 }
62c37eed
RB		 917
918 return 0;
500fcc08
MS		 919
920err_unmap_rx:
921 dma_unmap_single(p->port.dev, dma->rx_addr, dma->rx_size,
922 DMA_FROM_DEVICE);
923err_free_rx:
924 kfree(dma->rx_buf);
925err_release_tx:
926 dma_release_channel(dma->tx_chan);
927err_release_rx:
928 dma_release_channel(dma->rx_chan);
929 return ret;
62c37eed
RB		 930}
931
932static void s3c24xx_serial_release_dma(struct s3c24xx_uart_port *p)
933{
934 struct s3c24xx_uart_dma *dma = p->dma;
935
936 if (dma->rx_chan) {
937 dmaengine_terminate_all(dma->rx_chan);
768d64f4 938 dma_unmap_single(p->port.dev, dma->rx_addr,
62c37eed
RB		 939 dma->rx_size, DMA_FROM_DEVICE);
940 kfree(dma->rx_buf);
941 dma_release_channel(dma->rx_chan);
942 dma->rx_chan = NULL;
943 }
944
945 if (dma->tx_chan) {
946 dmaengine_terminate_all(dma->tx_chan);
768d64f4 947 dma_unmap_single(p->port.dev, dma->tx_addr,
62c37eed
RB		 948 UART_XMIT_SIZE, DMA_TO_DEVICE);
949 dma_release_channel(dma->tx_chan);
950 dma->tx_chan = NULL;
951 }
952}
953
b497549a
BD		 954static void s3c24xx_serial_shutdown(struct uart_port *port)
955{
956 struct s3c24xx_uart_port *ourport = to_ourport(port);
957
958 if (ourport->tx_claimed) {
88bb4ea1
TA		 959 if (!s3c24xx_serial_has_interrupt_mask(port))
960 free_irq(ourport->tx_irq, ourport);
b497549a
BD		 961 tx_enabled(port) = 0;
962 ourport->tx_claimed = 0;
e91d863d 963 ourport->tx_mode = 0;
b497549a
BD		 964 }
965
966 if (ourport->rx_claimed) {
88bb4ea1
TA		 967 if (!s3c24xx_serial_has_interrupt_mask(port))
968 free_irq(ourport->rx_irq, ourport);
b497549a
BD		 969 ourport->rx_claimed = 0;
970 rx_enabled(port) = 0;
971 }
b497549a 972
88bb4ea1
TA		 973 /* Clear pending interrupts and mask all interrupts */
974 if (s3c24xx_serial_has_interrupt_mask(port)) {
b6ad2935
TF		 975 free_irq(port->irq, ourport);
976
88bb4ea1
TA		 977 wr_regl(port, S3C64XX_UINTP, 0xf);
978 wr_regl(port, S3C64XX_UINTM, 0xf);
979 }
62c37eed
RB		 980
981 if (ourport->dma)
982 s3c24xx_serial_release_dma(ourport);
983
29bef799 984 ourport->tx_in_progress = 0;
88bb4ea1 985}
b497549a
BD		 986
987static int s3c24xx_serial_startup(struct uart_port *port)
988{
989 struct s3c24xx_uart_port *ourport = to_ourport(port);
990 int ret;
991
e4ac92df
JP		 992 dbg("s3c24xx_serial_startup: port=%p (%08llx,%p)\n",
993 port, (unsigned long long)port->mapbase, port->membase);
b497549a
BD		 994
995 rx_enabled(port) = 1;
996
b73c289c 997 ret = request_irq(ourport->rx_irq, s3c24xx_serial_rx_chars, 0,
b497549a
BD		 998 s3c24xx_serial_portname(port), ourport);
999
1000 if (ret != 0) {
d20925e1 1001 dev_err(port->dev, "cannot get irq %d\n", ourport->rx_irq);
b497549a
BD		 1002 return ret;
1003 }
1004
1005 ourport->rx_claimed = 1;
1006
1007 dbg("requesting tx irq...\n");
1008
1009 tx_enabled(port) = 1;
1010
b73c289c 1011 ret = request_irq(ourport->tx_irq, s3c24xx_serial_tx_chars, 0,
b497549a
BD		 1012 s3c24xx_serial_portname(port), ourport);
1013
1014 if (ret) {
d20925e1 1015 dev_err(port->dev, "cannot get irq %d\n", ourport->tx_irq);
b497549a
BD		 1016 goto err;
1017 }
1018
1019 ourport->tx_claimed = 1;
1020
1021 dbg("s3c24xx_serial_startup ok\n");
1022
1023 /* the port reset code should have done the correct
1024 * register setup for the port controls */
1025
1026 return ret;
1027
ef4aca70 1028err:
b497549a
BD		 1029 s3c24xx_serial_shutdown(port);
1030 return ret;
1031}
1032
88bb4ea1
TA		 1033static int s3c64xx_serial_startup(struct uart_port *port)
1034{
1035 struct s3c24xx_uart_port *ourport = to_ourport(port);
b543c301
RB		 1036 unsigned long flags;
1037 unsigned int ufcon;
88bb4ea1
TA		 1038 int ret;
1039
e4ac92df
JP		 1040 dbg("s3c64xx_serial_startup: port=%p (%08llx,%p)\n",
1041 port, (unsigned long long)port->mapbase, port->membase);
88bb4ea1 1042
b6ad2935 1043 wr_regl(port, S3C64XX_UINTM, 0xf);
62c37eed
RB		 1044 if (ourport->dma) {
1045 ret = s3c24xx_serial_request_dma(ourport);
1046 if (ret < 0) {
f98c7bce
KK		 1047 dev_warn(port->dev,
1048 "DMA request failed, DMA will not be used\n");
1049 devm_kfree(port->dev, ourport->dma);
1050 ourport->dma = NULL;
62c37eed
RB		 1051 }
1052 }
b6ad2935 1053
88bb4ea1
TA		 1054 ret = request_irq(port->irq, s3c64xx_serial_handle_irq, IRQF_SHARED,
1055 s3c24xx_serial_portname(port), ourport);
1056 if (ret) {
d20925e1 1057 dev_err(port->dev, "cannot get irq %d\n", port->irq);
88bb4ea1
TA		 1058 return ret;
1059 }
1060
1061 /* For compatibility with s3c24xx Soc's */
1062 rx_enabled(port) = 1;
1063 ourport->rx_claimed = 1;
1064 tx_enabled(port) = 0;
1065 ourport->tx_claimed = 1;
1066
29bef799
RB		 1067 spin_lock_irqsave(&port->lock, flags);
1068
1069 ufcon = rd_regl(port, S3C2410_UFCON);
31c6ba97
RB		 1070 ufcon |= S3C2410_UFCON_RESETRX | S5PV210_UFCON_RXTRIG8;
1071 if (!uart_console(port))
1072 ufcon |= S3C2410_UFCON_RESETTX;
29bef799
RB		 1073 wr_regl(port, S3C2410_UFCON, ufcon);
1074
1075 enable_rx_pio(ourport);
1076
1077 spin_unlock_irqrestore(&port->lock, flags);
1078
88bb4ea1 1079 /* Enable Rx Interrupt */
bbb5ff91 1080 s3c24xx_clear_bit(port, S3C64XX_UINTM_RXD, S3C64XX_UINTM);
29bef799 1081
88bb4ea1
TA		 1082 dbg("s3c64xx_serial_startup ok\n");
1083 return ret;
1084}
1085
b497549a
BD		 1086/* power power management control */
1087
1088static void s3c24xx_serial_pm(struct uart_port *port, unsigned int level,
1089 unsigned int old)
1090{
1091 struct s3c24xx_uart_port *ourport = to_ourport(port);
1ff383a4 1092 int timeout = 10000;
b497549a 1093
30555476
BD		 1094 ourport->pm_level = level;
1095
b497549a
BD		 1096 switch (level) {
1097 case 3:
1ff383a4
RB		 1098 while (--timeout && !s3c24xx_serial_txempty_nofifo(port))
1099 udelay(100);
1100
7cd88831 1101 if (!IS_ERR(ourport->baudclk))
9484b009 1102 clk_disable_unprepare(ourport->baudclk);
b497549a 1103
9484b009 1104 clk_disable_unprepare(ourport->clk);
b497549a
BD		 1105 break;
1106
1107 case 0:
9484b009 1108 clk_prepare_enable(ourport->clk);
b497549a 1109
7cd88831 1110 if (!IS_ERR(ourport->baudclk))
9484b009 1111 clk_prepare_enable(ourport->baudclk);
b497549a
BD		 1112
1113 break;
1114 default:
d20925e1 1115 dev_err(port->dev, "s3c24xx_serial: unknown pm %d\n", level);
b497549a
BD		 1116 }
1117}
1118
1119/* baud rate calculation
1120 *
1121 * The UARTs on the S3C2410/S3C2440 can take their clocks from a number
1122 * of different sources, including the peripheral clock ("pclk") and an
1123 * external clock ("uclk"). The S3C2440 also adds the core clock ("fclk")
1124 * with a programmable extra divisor.
1125 *
1126 * The following code goes through the clock sources, and calculates the
1127 * baud clocks (and the resultant actual baud rates) and then tries to
1128 * pick the closest one and select that.
1129 *
1130*/
1131
5f5a7a55 1132#define MAX_CLK_NAME_LENGTH 15
b497549a 1133
5f5a7a55 1134static inline int s3c24xx_serial_getsource(struct uart_port *port)
b497549a
BD		 1135{
1136 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
5f5a7a55 1137 unsigned int ucon;
b497549a 1138
5f5a7a55
TA		 1139 if (info->num_clks == 1)
1140 return 0;
b497549a 1141
5f5a7a55
TA		 1142 ucon = rd_regl(port, S3C2410_UCON);
1143 ucon &= info->clksel_mask;
1144 return ucon >> info->clksel_shift;
b497549a
BD		 1145}
1146
5f5a7a55
TA		 1147static void s3c24xx_serial_setsource(struct uart_port *port,
1148 unsigned int clk_sel)
b497549a 1149{
5f5a7a55
TA		 1150 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1151 unsigned int ucon;
b497549a 1152
5f5a7a55
TA		 1153 if (info->num_clks == 1)
1154 return;
090f848d 1155
5f5a7a55
TA		 1156 ucon = rd_regl(port, S3C2410_UCON);
1157 if ((ucon & info->clksel_mask) >> info->clksel_shift == clk_sel)
1158 return;
b497549a 1159
5f5a7a55
TA		 1160 ucon &= ~info->clksel_mask;
1161 ucon |= clk_sel << info->clksel_shift;
1162 wr_regl(port, S3C2410_UCON, ucon);
b497549a
BD		 1163}
1164
5f5a7a55
TA		 1165static unsigned int s3c24xx_serial_getclk(struct s3c24xx_uart_port *ourport,
1166 unsigned int req_baud, struct clk **best_clk,
1167 unsigned int *clk_num)
b497549a 1168{
5f5a7a55
TA		 1169 struct s3c24xx_uart_info *info = ourport->info;
1170 struct clk *clk;
1171 unsigned long rate;
1172 unsigned int cnt, baud, quot, clk_sel, best_quot = 0;
1173 char clkname[MAX_CLK_NAME_LENGTH];
1174 int calc_deviation, deviation = (1 << 30) - 1;
1175
5f5a7a55
TA		 1176 clk_sel = (ourport->cfg->clk_sel) ? ourport->cfg->clk_sel :
1177 ourport->info->def_clk_sel;
1178 for (cnt = 0; cnt < info->num_clks; cnt++) {
1179 if (!(clk_sel & (1 << cnt)))
1180 continue;
1181
1182 sprintf(clkname, "clk_uart_baud%d", cnt);
1183 clk = clk_get(ourport->port.dev, clkname);
7cd88831 1184 if (IS_ERR(clk))
5f5a7a55
TA		 1185 continue;
1186
1187 rate = clk_get_rate(clk);
1188 if (!rate)
1189 continue;
1190
1191 if (ourport->info->has_divslot) {
1192 unsigned long div = rate / req_baud;
1193
1194 /* The UDIVSLOT register on the newer UARTs allows us to
1195 * get a divisor adjustment of 1/16th on the baud clock.
1196 *
1197 * We don't keep the UDIVSLOT value (the 16ths we
1198 * calculated by not multiplying the baud by 16) as it
1199 * is easy enough to recalculate.
1200 */
1201
1202 quot = div / 16;
1203 baud = rate / div;
1204 } else {
1205 quot = (rate + (8 * req_baud)) / (16 * req_baud);
1206 baud = rate / (quot * 16);
b497549a 1207 }
5f5a7a55 1208 quot--;
b497549a 1209
5f5a7a55
TA		 1210 calc_deviation = req_baud - baud;
1211 if (calc_deviation < 0)
1212 calc_deviation = -calc_deviation;
b497549a 1213
5f5a7a55
TA		 1214 if (calc_deviation < deviation) {
1215 *best_clk = clk;
1216 best_quot = quot;
1217 *clk_num = cnt;
1218 deviation = calc_deviation;
b497549a
BD		 1219 }
1220 }
1221
5f5a7a55 1222 return best_quot;
b497549a
BD		 1223}
1224
090f848d
BD		 1225/* udivslot_table[]
1226 *
1227 * This table takes the fractional value of the baud divisor and gives
1228 * the recommended setting for the UDIVSLOT register.
1229 */
1230static u16 udivslot_table[16] = {
1231 [0] = 0x0000,
1232 [1] = 0x0080,
1233 [2] = 0x0808,
1234 [3] = 0x0888,
1235 [4] = 0x2222,
1236 [5] = 0x4924,
1237 [6] = 0x4A52,
1238 [7] = 0x54AA,
1239 [8] = 0x5555,
1240 [9] = 0xD555,
1241 [10] = 0xD5D5,
1242 [11] = 0xDDD5,
1243 [12] = 0xDDDD,
1244 [13] = 0xDFDD,
1245 [14] = 0xDFDF,
1246 [15] = 0xFFDF,
1247};
1248
b497549a
BD		 1249static void s3c24xx_serial_set_termios(struct uart_port *port,
1250 struct ktermios *termios,
1251 struct ktermios *old)
1252{
1253 struct s3c2410_uartcfg *cfg = s3c24xx_port_to_cfg(port);
1254 struct s3c24xx_uart_port *ourport = to_ourport(port);
7cd88831 1255 struct clk *clk = ERR_PTR(-EINVAL);
b497549a 1256 unsigned long flags;
5f5a7a55 1257 unsigned int baud, quot, clk_sel = 0;
b497549a
BD		 1258 unsigned int ulcon;
1259 unsigned int umcon;
090f848d 1260 unsigned int udivslot = 0;
b497549a
BD		 1261
1262 /*
1263 * We don't support modem control lines.
1264 */
1265 termios->c_cflag &= ~(HUPCL | CMSPAR);
1266 termios->c_cflag |= CLOCAL;
1267
1268 /*
1269 * Ask the core to calculate the divisor for us.
1270 */
1271
1272 baud = uart_get_baud_rate(port, termios, old, 0, 115200*8);
5f5a7a55 1273 quot = s3c24xx_serial_getclk(ourport, baud, &clk, &clk_sel);
b497549a
BD		 1274 if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST)
1275 quot = port->custom_divisor;
7cd88831 1276 if (IS_ERR(clk))
5f5a7a55 1277 return;
b497549a
BD		 1278
1279 /* check to see if we need to change clock source */
1280
5f5a7a55 1281 if (ourport->baudclk != clk) {
b8995f52
CC		 1282 clk_prepare_enable(clk);
1283
5f5a7a55 1284 s3c24xx_serial_setsource(port, clk_sel);
b497549a 1285
7cd88831 1286 if (!IS_ERR(ourport->baudclk)) {
9484b009 1287 clk_disable_unprepare(ourport->baudclk);
7cd88831 1288 ourport->baudclk = ERR_PTR(-EINVAL);
b497549a
BD		 1289 }
1290
b497549a 1291 ourport->baudclk = clk;
30555476 1292 ourport->baudclk_rate = clk ? clk_get_rate(clk) : 0;
b497549a
BD		 1293 }
1294
090f848d
BD		 1295 if (ourport->info->has_divslot) {
1296 unsigned int div = ourport->baudclk_rate / baud;
1297
8b526ae4
JL		 1298 if (cfg->has_fracval) {
1299 udivslot = (div & 15);
1300 dbg("fracval = %04x\n", udivslot);
1301 } else {
1302 udivslot = udivslot_table[div & 15];
1303 dbg("udivslot = %04x (div %d)\n", udivslot, div & 15);
1304 }
090f848d
BD		 1305 }
1306
b497549a
BD		 1307 switch (termios->c_cflag & CSIZE) {
1308 case CS5:
1309 dbg("config: 5bits/char\n");
1310 ulcon = S3C2410_LCON_CS5;
1311 break;
1312 case CS6:
1313 dbg("config: 6bits/char\n");
1314 ulcon = S3C2410_LCON_CS6;
1315 break;
1316 case CS7:
1317 dbg("config: 7bits/char\n");
1318 ulcon = S3C2410_LCON_CS7;
1319 break;
1320 case CS8:
1321 default:
1322 dbg("config: 8bits/char\n");
1323 ulcon = S3C2410_LCON_CS8;
1324 break;
1325 }
1326
1327 /* preserve original lcon IR settings */
1328 ulcon |= (cfg->ulcon & S3C2410_LCON_IRM);
1329
1330 if (termios->c_cflag & CSTOPB)
1331 ulcon |= S3C2410_LCON_STOPB;
1332
b497549a
BD		 1333 if (termios->c_cflag & PARENB) {
1334 if (termios->c_cflag & PARODD)
1335 ulcon |= S3C2410_LCON_PODD;
1336 else
1337 ulcon |= S3C2410_LCON_PEVEN;
1338 } else {
1339 ulcon |= S3C2410_LCON_PNONE;
1340 }
1341
1342 spin_lock_irqsave(&port->lock, flags);
1343
090f848d
BD		 1344 dbg("setting ulcon to %08x, brddiv to %d, udivslot %08x\n",
1345 ulcon, quot, udivslot);
b497549a
BD		 1346
1347 wr_regl(port, S3C2410_ULCON, ulcon);
1348 wr_regl(port, S3C2410_UBRDIV, quot);
2d1e5a48
JMG		 1349
1350 umcon = rd_regl(port, S3C2410_UMCON);
1351 if (termios->c_cflag & CRTSCTS) {
1352 umcon |= S3C2410_UMCOM_AFC;
1353 /* Disable RTS when RX FIFO contains 63 bytes */
1354 umcon &= ~S3C2412_UMCON_AFC_8;
1355 } else {
1356 umcon &= ~S3C2410_UMCOM_AFC;
1357 }
b497549a
BD		 1358 wr_regl(port, S3C2410_UMCON, umcon);
1359
090f848d
BD		 1360 if (ourport->info->has_divslot)
1361 wr_regl(port, S3C2443_DIVSLOT, udivslot);
1362
b497549a
BD		 1363 dbg("uart: ulcon = 0x%08x, ucon = 0x%08x, ufcon = 0x%08x\n",
1364 rd_regl(port, S3C2410_ULCON),
1365 rd_regl(port, S3C2410_UCON),
1366 rd_regl(port, S3C2410_UFCON));
1367
1368 /*
1369 * Update the per-port timeout.
1370 */
1371 uart_update_timeout(port, termios->c_cflag, baud);
1372
1373 /*
1374 * Which character status flags are we interested in?
1375 */
1376 port->read_status_mask = S3C2410_UERSTAT_OVERRUN;
1377 if (termios->c_iflag & INPCK)
ef4aca70
RB		 1378 port->read_status_mask |= S3C2410_UERSTAT_FRAME |
1379 S3C2410_UERSTAT_PARITY;
b497549a
BD		 1380 /*
1381 * Which character status flags should we ignore?
1382 */
1383 port->ignore_status_mask = 0;
1384 if (termios->c_iflag & IGNPAR)
1385 port->ignore_status_mask |= S3C2410_UERSTAT_OVERRUN;
1386 if (termios->c_iflag & IGNBRK && termios->c_iflag & IGNPAR)
1387 port->ignore_status_mask |= S3C2410_UERSTAT_FRAME;
1388
1389 /*
1390 * Ignore all characters if CREAD is not set.
1391 */
1392 if ((termios->c_cflag & CREAD) == 0)
1393 port->ignore_status_mask |= RXSTAT_DUMMY_READ;
1394
1395 spin_unlock_irqrestore(&port->lock, flags);
1396}
1397
1398static const char *s3c24xx_serial_type(struct uart_port *port)
1399{
1400 switch (port->type) {
1401 case PORT_S3C2410:
1402 return "S3C2410";
1403 case PORT_S3C2440:
1404 return "S3C2440";
1405 case PORT_S3C2412:
1406 return "S3C2412";
b690ace5
BD		 1407 case PORT_S3C6400:
1408 return "S3C6400/10";
b497549a
BD		 1409 default:
1410 return NULL;
1411 }
1412}
1413
1414#define MAP_SIZE (0x100)
1415
1416static void s3c24xx_serial_release_port(struct uart_port *port)
1417{
1418 release_mem_region(port->mapbase, MAP_SIZE);
1419}
1420
1421static int s3c24xx_serial_request_port(struct uart_port *port)
1422{
1423 const char *name = s3c24xx_serial_portname(port);
1424 return request_mem_region(port->mapbase, MAP_SIZE, name) ? 0 : -EBUSY;
1425}
1426
1427static void s3c24xx_serial_config_port(struct uart_port *port, int flags)
1428{
1429 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1430
1431 if (flags & UART_CONFIG_TYPE &&
1432 s3c24xx_serial_request_port(port) == 0)
1433 port->type = info->type;
1434}
1435
1436/*
1437 * verify the new serial_struct (for TIOCSSERIAL).
1438 */
1439static int
1440s3c24xx_serial_verify_port(struct uart_port *port, struct serial_struct *ser)
1441{
1442 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1443
1444 if (ser->type != PORT_UNKNOWN && ser->type != info->type)
1445 return -EINVAL;
1446
1447 return 0;
1448}
1449
1450
1451#ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
1452
1453static struct console s3c24xx_serial_console;
1454
93b5c032
JP		 1455static int __init s3c24xx_serial_console_init(void)
1456{
1457 register_console(&s3c24xx_serial_console);
1458 return 0;
1459}
1460console_initcall(s3c24xx_serial_console_init);
1461
b497549a
BD		 1462#define S3C24XX_SERIAL_CONSOLE &s3c24xx_serial_console
1463#else
1464#define S3C24XX_SERIAL_CONSOLE NULL
1465#endif
1466
84f57d9e 1467#if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
93b5c032
JP		 1468static int s3c24xx_serial_get_poll_char(struct uart_port *port);
1469static void s3c24xx_serial_put_poll_char(struct uart_port *port,
1470 unsigned char c);
1471#endif
1472
b497549a
BD		 1473static struct uart_ops s3c24xx_serial_ops = {
1474 .pm = s3c24xx_serial_pm,
1475 .tx_empty = s3c24xx_serial_tx_empty,
1476 .get_mctrl = s3c24xx_serial_get_mctrl,
1477 .set_mctrl = s3c24xx_serial_set_mctrl,
1478 .stop_tx = s3c24xx_serial_stop_tx,
1479 .start_tx = s3c24xx_serial_start_tx,
1480 .stop_rx = s3c24xx_serial_stop_rx,
b497549a
BD		 1481 .break_ctl = s3c24xx_serial_break_ctl,
1482 .startup = s3c24xx_serial_startup,
1483 .shutdown = s3c24xx_serial_shutdown,
1484 .set_termios = s3c24xx_serial_set_termios,
1485 .type = s3c24xx_serial_type,
1486 .release_port = s3c24xx_serial_release_port,
1487 .request_port = s3c24xx_serial_request_port,
1488 .config_port = s3c24xx_serial_config_port,
1489 .verify_port = s3c24xx_serial_verify_port,
84f57d9e 1490#if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
93b5c032
JP		 1491 .poll_get_char = s3c24xx_serial_get_poll_char,
1492 .poll_put_char = s3c24xx_serial_put_poll_char,
1493#endif
b497549a
BD		 1494};
1495
b497549a
BD		 1496static struct uart_driver s3c24xx_uart_drv = {
1497 .owner = THIS_MODULE,
2cf0c58e 1498 .driver_name = "s3c2410_serial",
bdd4915a 1499 .nr = CONFIG_SERIAL_SAMSUNG_UARTS,
b497549a 1500 .cons = S3C24XX_SERIAL_CONSOLE,
2cf0c58e 1501 .dev_name = S3C24XX_SERIAL_NAME,
b497549a
BD		 1502 .major = S3C24XX_SERIAL_MAJOR,
1503 .minor = S3C24XX_SERIAL_MINOR,
1504};
1505
ef4aca70
RB		 1506#define __PORT_LOCK_UNLOCKED(i) \
1507 __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[i].port.lock)
1508static struct s3c24xx_uart_port
1509s3c24xx_serial_ports[CONFIG_SERIAL_SAMSUNG_UARTS] = {
b497549a
BD		 1510 [0] = {
1511 .port = {
ef4aca70 1512 .lock = __PORT_LOCK_UNLOCKED(0),
b497549a 1513 .iotype = UPIO_MEM,
b497549a
BD		 1514 .uartclk = 0,
1515 .fifosize = 16,
1516 .ops = &s3c24xx_serial_ops,
1517 .flags = UPF_BOOT_AUTOCONF,
1518 .line = 0,
1519 }
1520 },
1521 [1] = {
1522 .port = {
ef4aca70 1523 .lock = __PORT_LOCK_UNLOCKED(1),
b497549a 1524 .iotype = UPIO_MEM,
b497549a
BD		 1525 .uartclk = 0,
1526 .fifosize = 16,
1527 .ops = &s3c24xx_serial_ops,
1528 .flags = UPF_BOOT_AUTOCONF,
1529 .line = 1,
1530 }
1531 },
03d5e77b 1532#if CONFIG_SERIAL_SAMSUNG_UARTS > 2
b497549a
BD		 1533
1534 [2] = {
1535 .port = {
ef4aca70 1536 .lock = __PORT_LOCK_UNLOCKED(2),
b497549a 1537 .iotype = UPIO_MEM,
b497549a
BD		 1538 .uartclk = 0,
1539 .fifosize = 16,
1540 .ops = &s3c24xx_serial_ops,
1541 .flags = UPF_BOOT_AUTOCONF,
1542 .line = 2,
1543 }
03d5e77b
BD		 1544 },
1545#endif
1546#if CONFIG_SERIAL_SAMSUNG_UARTS > 3
1547 [3] = {
1548 .port = {
ef4aca70 1549 .lock = __PORT_LOCK_UNLOCKED(3),
03d5e77b 1550 .iotype = UPIO_MEM,
03d5e77b
BD		 1551 .uartclk = 0,
1552 .fifosize = 16,
1553 .ops = &s3c24xx_serial_ops,
1554 .flags = UPF_BOOT_AUTOCONF,
1555 .line = 3,
1556 }
b497549a
BD		 1557 }
1558#endif
1559};
ef4aca70 1560#undef __PORT_LOCK_UNLOCKED
b497549a
BD		 1561
1562/* s3c24xx_serial_resetport
1563 *
0dfb3b41 1564 * reset the fifos and other the settings.
b497549a
BD		 1565*/
1566
0dfb3b41
TA		 1567static void s3c24xx_serial_resetport(struct uart_port *port,
1568 struct s3c2410_uartcfg *cfg)
b497549a
BD		 1569{
1570 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
0dfb3b41
TA		 1571 unsigned long ucon = rd_regl(port, S3C2410_UCON);
1572 unsigned int ucon_mask;
b497549a 1573
0dfb3b41
TA		 1574 ucon_mask = info->clksel_mask;
1575 if (info->type == PORT_S3C2440)
1576 ucon_mask |= S3C2440_UCON0_DIVMASK;
1577
1578 ucon &= ucon_mask;
1579 wr_regl(port, S3C2410_UCON, ucon | cfg->ucon);
1580
1581 /* reset both fifos */
1582 wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
1583 wr_regl(port, S3C2410_UFCON, cfg->ufcon);
1584
1585 /* some delay is required after fifo reset */
1586 udelay(1);
b497549a
BD		 1587}
1588
30555476 1589
ebaa81c7 1590#ifdef CONFIG_ARM_S3C24XX_CPUFREQ
30555476
BD		 1591
1592static int s3c24xx_serial_cpufreq_transition(struct notifier_block *nb,
1593 unsigned long val, void *data)
1594{
1595 struct s3c24xx_uart_port *port;
1596 struct uart_port *uport;
1597
1598 port = container_of(nb, struct s3c24xx_uart_port, freq_transition);
1599 uport = &port->port;
1600
1601 /* check to see if port is enabled */
1602
1603 if (port->pm_level != 0)
1604 return 0;
1605
1606 /* try and work out if the baudrate is changing, we can detect
1607 * a change in rate, but we do not have support for detecting
1608 * a disturbance in the clock-rate over the change.
1609 */
1610
25f04ad4 1611 if (IS_ERR(port->baudclk))
30555476
BD		 1612 goto exit;
1613
25f04ad4 1614 if (port->baudclk_rate == clk_get_rate(port->baudclk))
30555476
BD		 1615 goto exit;
1616
1617 if (val == CPUFREQ_PRECHANGE) {
1618 /* we should really shut the port down whilst the
1619 * frequency change is in progress. */
1620
1621 } else if (val == CPUFREQ_POSTCHANGE) {
1622 struct ktermios *termios;
1623 struct tty_struct *tty;
1624
ebd2c8f6 1625 if (uport->state == NULL)
30555476 1626 goto exit;
30555476 1627
ebd2c8f6 1628 tty = uport->state->port.tty;
30555476 1629
7de40c21 1630 if (tty == NULL)
30555476 1631 goto exit;
30555476 1632
adc8d746 1633 termios = &tty->termios;
30555476
BD		 1634
1635 if (termios == NULL) {
d20925e1 1636 dev_warn(uport->dev, "%s: no termios?\n", __func__);
30555476
BD		 1637 goto exit;
1638 }
1639
1640 s3c24xx_serial_set_termios(uport, termios, NULL);
1641 }
1642
ef4aca70 1643exit:
30555476
BD		 1644 return 0;
1645}
1646
ef4aca70
RB		 1647static inline int
1648s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port)
30555476
BD		 1649{
1650 port->freq_transition.notifier_call = s3c24xx_serial_cpufreq_transition;
1651
1652 return cpufreq_register_notifier(&port->freq_transition,
1653 CPUFREQ_TRANSITION_NOTIFIER);
1654}
1655
ef4aca70
RB		 1656static inline void
1657s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port)
30555476
BD		 1658{
1659 cpufreq_unregister_notifier(&port->freq_transition,
1660 CPUFREQ_TRANSITION_NOTIFIER);
1661}
1662
1663#else
ef4aca70
RB		 1664static inline int
1665s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port)
30555476
BD		 1666{
1667 return 0;
1668}
1669
ef4aca70
RB		 1670static inline void
1671s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port)
30555476
BD		 1672{
1673}
1674#endif
1675
b497549a
BD		 1676/* s3c24xx_serial_init_port
1677 *
1678 * initialise a single serial port from the platform device given
1679 */
1680
1681static int s3c24xx_serial_init_port(struct s3c24xx_uart_port *ourport,
b497549a
BD		 1682 struct platform_device *platdev)
1683{
1684 struct uart_port *port = &ourport->port;
da121506 1685 struct s3c2410_uartcfg *cfg = ourport->cfg;
b497549a
BD		 1686 struct resource *res;
1687 int ret;
1688
1689 dbg("s3c24xx_serial_init_port: port=%p, platdev=%p\n", port, platdev);
1690
1691 if (platdev == NULL)
1692 return -ENODEV;
1693
b497549a 1694 if (port->mapbase != 0)
e51e4d8a 1695 return -EINVAL;
b497549a 1696
b497549a
BD		 1697 /* setup info for port */
1698 port->dev = &platdev->dev;
b497549a 1699
88bb4ea1
TA		 1700 /* Startup sequence is different for s3c64xx and higher SoC's */
1701 if (s3c24xx_serial_has_interrupt_mask(port))
1702 s3c24xx_serial_ops.startup = s3c64xx_serial_startup;
1703
b497549a
BD		 1704 port->uartclk = 1;
1705
1706 if (cfg->uart_flags & UPF_CONS_FLOW) {
1707 dbg("s3c24xx_serial_init_port: enabling flow control\n");
1708 port->flags |= UPF_CONS_FLOW;
1709 }
1710
1711 /* sort our the physical and virtual addresses for each UART */
1712
1713 res = platform_get_resource(platdev, IORESOURCE_MEM, 0);
1714 if (res == NULL) {
d20925e1 1715 dev_err(port->dev, "failed to find memory resource for uart\n");
b497549a
BD		 1716 return -EINVAL;
1717 }
1718
e4ac92df 1719 dbg("resource %pR)\n", res);
b497549a 1720
41147bfd
TA		 1721 port->membase = devm_ioremap(port->dev, res->start, resource_size(res));
1722 if (!port->membase) {
1723 dev_err(port->dev, "failed to remap controller address\n");
1724 return -EBUSY;
1725 }
1726
b690ace5 1727 port->mapbase = res->start;
b497549a
BD		 1728 ret = platform_get_irq(platdev, 0);
1729 if (ret < 0)
1730 port->irq = 0;
b73c289c 1731 else {
b497549a 1732 port->irq = ret;
b73c289c
BD		 1733 ourport->rx_irq = ret;
1734 ourport->tx_irq = ret + 1;
1735 }
9303ac15 1736
b73c289c
BD		 1737 ret = platform_get_irq(platdev, 1);
1738 if (ret > 0)
1739 ourport->tx_irq = ret;
658c9d2b
RB		 1740 /*
1741 * DMA is currently supported only on DT platforms, if DMA properties
1742 * are specified.
1743 */
1744 if (platdev->dev.of_node && of_find_property(platdev->dev.of_node,
1745 "dmas", NULL)) {
1746 ourport->dma = devm_kzalloc(port->dev,
1747 sizeof(*ourport->dma),
1748 GFP_KERNEL);
e51e4d8a
KK		 1749 if (!ourport->dma) {
1750 ret = -ENOMEM;
1751 goto err;
1752 }
658c9d2b 1753 }
b497549a
BD		 1754
1755 ourport->clk = clk_get(&platdev->dev, "uart");
60e93575
CK		 1756 if (IS_ERR(ourport->clk)) {
1757 pr_err("%s: Controller clock not found\n",
1758 dev_name(&platdev->dev));
e51e4d8a
KK		 1759 ret = PTR_ERR(ourport->clk);
1760 goto err;
60e93575
CK		 1761 }
1762
1763 ret = clk_prepare_enable(ourport->clk);
1764 if (ret) {
1765 pr_err("uart: clock failed to prepare+enable: %d\n", ret);
1766 clk_put(ourport->clk);
e51e4d8a 1767 goto err;
60e93575 1768 }
b497549a 1769
88bb4ea1
TA		 1770 /* Keep all interrupts masked and cleared */
1771 if (s3c24xx_serial_has_interrupt_mask(port)) {
1772 wr_regl(port, S3C64XX_UINTM, 0xf);
1773 wr_regl(port, S3C64XX_UINTP, 0xf);
1774 wr_regl(port, S3C64XX_UINTSP, 0xf);
1775 }
1776
1ff5b64d
FE		 1777 dbg("port: map=%pa, mem=%p, irq=%d (%d,%d), clock=%u\n",
1778 &port->mapbase, port->membase, port->irq,
b73c289c 1779 ourport->rx_irq, ourport->tx_irq, port->uartclk);
b497549a
BD		 1780
1781 /* reset the fifos (and setup the uart) */
1782 s3c24xx_serial_resetport(port, cfg);
e51e4d8a 1783
b497549a 1784 return 0;
e51e4d8a
KK		 1785
1786err:
1787 port->mapbase = 0;
1788 return ret;
b497549a
BD		 1789}
1790
b497549a
BD		 1791/* Device driver serial port probe */
1792
26c919e1 1793static const struct of_device_id s3c24xx_uart_dt_match[];
b497549a
BD		 1794static int probe_index;
1795
26c919e1
TA		 1796static inline struct s3c24xx_serial_drv_data *s3c24xx_get_driver_data(
1797 struct platform_device *pdev)
1798{
1799#ifdef CONFIG_OF
1800 if (pdev->dev.of_node) {
1801 const struct of_device_id *match;
1802 match = of_match_node(s3c24xx_uart_dt_match, pdev->dev.of_node);
1803 return (struct s3c24xx_serial_drv_data *)match->data;
1804 }
1805#endif
1806 return (struct s3c24xx_serial_drv_data *)
1807 platform_get_device_id(pdev)->driver_data;
1808}
1809
da121506 1810static int s3c24xx_serial_probe(struct platform_device *pdev)
b497549a 1811{
4622eb68 1812 struct device_node *np = pdev->dev.of_node;
b497549a 1813 struct s3c24xx_uart_port *ourport;
13a9f6c6 1814 int index = probe_index;
b497549a
BD		 1815 int ret;
1816
4622eb68
NKC		 1817 if (np) {
1818 ret = of_alias_get_id(np, "serial");
13a9f6c6
TF		 1819 if (ret >= 0)
1820 index = ret;
1821 }
1822
1823 dbg("s3c24xx_serial_probe(%p) %d\n", pdev, index);
b497549a 1824
13a9f6c6 1825 ourport = &s3c24xx_serial_ports[index];
da121506 1826
26c919e1
TA		 1827 ourport->drv_data = s3c24xx_get_driver_data(pdev);
1828 if (!ourport->drv_data) {
1829 dev_err(&pdev->dev, "could not find driver data\n");
1830 return -ENODEV;
1831 }
da121506 1832
7cd88831 1833 ourport->baudclk = ERR_PTR(-EINVAL);
da121506 1834 ourport->info = ourport->drv_data->info;
574de559 1835 ourport->cfg = (dev_get_platdata(&pdev->dev)) ?
d4aab206 1836 dev_get_platdata(&pdev->dev) :
da121506
TA		 1837 ourport->drv_data->def_cfg;
1838
4622eb68
NKC		 1839 if (np)
1840 of_property_read_u32(np,
135f07c3
NKC		 1841 "samsung,uart-fifosize", &ourport->port.fifosize);
1842
2f1ba72d
RB		 1843 if (ourport->drv_data->fifosize[index])
1844 ourport->port.fifosize = ourport->drv_data->fifosize[index];
1845 else if (ourport->info->fifosize)
1846 ourport->port.fifosize = ourport->info->fifosize;
da121506 1847
81ccb2a6
MS		 1848 /*
1849 * DMA transfers must be aligned at least to cache line size,
1850 * so find minimal transfer size suitable for DMA mode
1851 */
1852 ourport->min_dma_size = max_t(int, ourport->port.fifosize,
1853 dma_get_cache_alignment());
1854
b497549a
BD		 1855 dbg("%s: initialising port %p...\n", __func__, ourport);
1856
da121506 1857 ret = s3c24xx_serial_init_port(ourport, pdev);
b497549a 1858 if (ret < 0)
8ad711a9 1859 return ret;
b497549a 1860
6f134c3c
TB		 1861 if (!s3c24xx_uart_drv.state) {
1862 ret = uart_register_driver(&s3c24xx_uart_drv);
1863 if (ret < 0) {
1864 pr_err("Failed to register Samsung UART driver\n");
1865 return ret;
1866 }
1867 }
1868
b497549a
BD		 1869 dbg("%s: adding port\n", __func__);
1870 uart_add_one_port(&s3c24xx_uart_drv, &ourport->port);
da121506 1871 platform_set_drvdata(pdev, &ourport->port);
b497549a 1872
0da3336f
HS		 1873 /*
1874 * Deactivate the clock enabled in s3c24xx_serial_init_port here,
1875 * so that a potential re-enablement through the pm-callback overlaps
1876 * and keeps the clock enabled in this case.
1877 */
1878 clk_disable_unprepare(ourport->clk);
1879
30555476
BD		 1880 ret = s3c24xx_serial_cpufreq_register(ourport);
1881 if (ret < 0)
da121506 1882 dev_err(&pdev->dev, "failed to add cpufreq notifier\n");
30555476 1883
926b7b51
KK		 1884 probe_index++;
1885
b497549a 1886 return 0;
b497549a
BD		 1887}
1888
ae8d8a14 1889static int s3c24xx_serial_remove(struct platform_device *dev)
b497549a
BD		 1890{
1891 struct uart_port *port = s3c24xx_dev_to_port(&dev->dev);
1892
1893 if (port) {
30555476 1894 s3c24xx_serial_cpufreq_deregister(to_ourport(port));
b497549a
BD		 1895 uart_remove_one_port(&s3c24xx_uart_drv, port);
1896 }
1897
6f134c3c
TB		 1898 uart_unregister_driver(&s3c24xx_uart_drv);
1899
b497549a
BD		 1900 return 0;
1901}
1902
b497549a 1903/* UART power management code */
aef7fe52
MH		 1904#ifdef CONFIG_PM_SLEEP
1905static int s3c24xx_serial_suspend(struct device *dev)
b497549a 1906{
aef7fe52 1907 struct uart_port *port = s3c24xx_dev_to_port(dev);
b497549a
BD		 1908
1909 if (port)
1910 uart_suspend_port(&s3c24xx_uart_drv, port);
1911
1912 return 0;
1913}
1914
aef7fe52 1915static int s3c24xx_serial_resume(struct device *dev)
b497549a 1916{
aef7fe52 1917 struct uart_port *port = s3c24xx_dev_to_port(dev);
b497549a
BD		 1918 struct s3c24xx_uart_port *ourport = to_ourport(port);
1919
1920 if (port) {
9484b009 1921 clk_prepare_enable(ourport->clk);
b497549a 1922 s3c24xx_serial_resetport(port, s3c24xx_port_to_cfg(port));
9484b009 1923 clk_disable_unprepare(ourport->clk);
b497549a
BD		 1924
1925 uart_resume_port(&s3c24xx_uart_drv, port);
1926 }
1927
1928 return 0;
1929}
aef7fe52 1930
d09a7308
MS		 1931static int s3c24xx_serial_resume_noirq(struct device *dev)
1932{
1933 struct uart_port *port = s3c24xx_dev_to_port(dev);
a8a1781b 1934 struct s3c24xx_uart_port *ourport = to_ourport(port);
d09a7308
MS		 1935
1936 if (port) {
1937 /* restore IRQ mask */
1938 if (s3c24xx_serial_has_interrupt_mask(port)) {
1939 unsigned int uintm = 0xf;
1940 if (tx_enabled(port))
1941 uintm &= ~S3C64XX_UINTM_TXD_MSK;
1942 if (rx_enabled(port))
1943 uintm &= ~S3C64XX_UINTM_RXD_MSK;
a8a1781b 1944 clk_prepare_enable(ourport->clk);
d09a7308 1945 wr_regl(port, S3C64XX_UINTM, uintm);
a8a1781b 1946 clk_disable_unprepare(ourport->clk);
d09a7308
MS		 1947 }
1948 }
1949
1950 return 0;
1951}
1952
aef7fe52
MH		 1953static const struct dev_pm_ops s3c24xx_serial_pm_ops = {
1954 .suspend = s3c24xx_serial_suspend,
1955 .resume = s3c24xx_serial_resume,
d09a7308 1956 .resume_noirq = s3c24xx_serial_resume_noirq,
aef7fe52 1957};
b882fc1b
KK		 1958#define SERIAL_SAMSUNG_PM_OPS (&s3c24xx_serial_pm_ops)
1959
aef7fe52 1960#else /* !CONFIG_PM_SLEEP */
b882fc1b
KK		 1961
1962#define SERIAL_SAMSUNG_PM_OPS NULL
aef7fe52 1963#endif /* CONFIG_PM_SLEEP */
b497549a 1964
b497549a
BD		 1965/* Console code */
1966
1967#ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
1968
1969static struct uart_port *cons_uart;
1970
1971static int
1972s3c24xx_serial_console_txrdy(struct uart_port *port, unsigned int ufcon)
1973{
1974 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1975 unsigned long ufstat, utrstat;
1976
1977 if (ufcon & S3C2410_UFCON_FIFOMODE) {
9ddc5b6f 1978 /* fifo mode - check amount of data in fifo registers... */
b497549a
BD		 1979
1980 ufstat = rd_regl(port, S3C2410_UFSTAT);
1981 return (ufstat & info->tx_fifofull) ? 0 : 1;
1982 }
1983
1984 /* in non-fifo mode, we go and use the tx buffer empty */
1985
1986 utrstat = rd_regl(port, S3C2410_UTRSTAT);
1987 return (utrstat & S3C2410_UTRSTAT_TXE) ? 1 : 0;
1988}
1989
38adbc54
MS		 1990static bool
1991s3c24xx_port_configured(unsigned int ucon)
1992{
1993 /* consider the serial port configured if the tx/rx mode set */
1994 return (ucon & 0xf) != 0;
1995}
1996
93b5c032
JP		 1997#ifdef CONFIG_CONSOLE_POLL
1998/*
1999 * Console polling routines for writing and reading from the uart while
2000 * in an interrupt or debug context.
2001 */
2002
2003static int s3c24xx_serial_get_poll_char(struct uart_port *port)
2004{
2005 struct s3c24xx_uart_port *ourport = to_ourport(port);
2006 unsigned int ufstat;
2007
2008 ufstat = rd_regl(port, S3C2410_UFSTAT);
2009 if (s3c24xx_serial_rx_fifocnt(ourport, ufstat) == 0)
2010 return NO_POLL_CHAR;
2011
2012 return rd_regb(port, S3C2410_URXH);
2013}
2014
2015static void s3c24xx_serial_put_poll_char(struct uart_port *port,
2016 unsigned char c)
2017{
bb7f09ba
DA		 2018 unsigned int ufcon = rd_regl(port, S3C2410_UFCON);
2019 unsigned int ucon = rd_regl(port, S3C2410_UCON);
38adbc54
MS		 2020
2021 /* not possible to xmit on unconfigured port */
2022 if (!s3c24xx_port_configured(ucon))
2023 return;
93b5c032
JP		 2024
2025 while (!s3c24xx_serial_console_txrdy(port, ufcon))
2026 cpu_relax();
bb7f09ba 2027 wr_regb(port, S3C2410_UTXH, c);
93b5c032
JP		 2028}
2029
2030#endif /* CONFIG_CONSOLE_POLL */
2031
b497549a
BD		 2032static void
2033s3c24xx_serial_console_putchar(struct uart_port *port, int ch)
2034{
bb7f09ba 2035 unsigned int ufcon = rd_regl(port, S3C2410_UFCON);
38adbc54 2036
b497549a 2037 while (!s3c24xx_serial_console_txrdy(port, ufcon))
f94b0572 2038 cpu_relax();
bb7f09ba 2039 wr_regb(port, S3C2410_UTXH, ch);
b497549a
BD		 2040}
2041
2042static void
2043s3c24xx_serial_console_write(struct console *co, const char *s,
2044 unsigned int count)
2045{
ab88c8dc
DA		 2046 unsigned int ucon = rd_regl(cons_uart, S3C2410_UCON);
2047
2048 /* not possible to xmit on unconfigured port */
2049 if (!s3c24xx_port_configured(ucon))
2050 return;
2051
b497549a
BD		 2052 uart_console_write(cons_uart, s, count, s3c24xx_serial_console_putchar);
2053}
2054
2055static void __init
2056s3c24xx_serial_get_options(struct uart_port *port, int *baud,
2057 int *parity, int *bits)
2058{
b497549a
BD		 2059 struct clk *clk;
2060 unsigned int ulcon;
2061 unsigned int ucon;
2062 unsigned int ubrdiv;
2063 unsigned long rate;
5f5a7a55
TA		 2064 unsigned int clk_sel;
2065 char clk_name[MAX_CLK_NAME_LENGTH];
b497549a
BD		 2066
2067 ulcon = rd_regl(port, S3C2410_ULCON);
2068 ucon = rd_regl(port, S3C2410_UCON);
2069 ubrdiv = rd_regl(port, S3C2410_UBRDIV);
2070
2071 dbg("s3c24xx_serial_get_options: port=%p\n"
2072 "registers: ulcon=%08x, ucon=%08x, ubdriv=%08x\n",
2073 port, ulcon, ucon, ubrdiv);
2074
38adbc54 2075 if (s3c24xx_port_configured(ucon)) {
b497549a
BD		 2076 switch (ulcon & S3C2410_LCON_CSMASK) {
2077 case S3C2410_LCON_CS5:
2078 *bits = 5;
2079 break;
2080 case S3C2410_LCON_CS6:
2081 *bits = 6;
2082 break;
2083 case S3C2410_LCON_CS7:
2084 *bits = 7;
2085 break;
b497549a 2086 case S3C2410_LCON_CS8:
3bcce591 2087 default:
b497549a
BD		 2088 *bits = 8;
2089 break;
2090 }
2091
2092 switch (ulcon & S3C2410_LCON_PMASK) {
2093 case S3C2410_LCON_PEVEN:
2094 *parity = 'e';
2095 break;
2096
2097 case S3C2410_LCON_PODD:
2098 *parity = 'o';
2099 break;
2100
2101 case S3C2410_LCON_PNONE:
2102 default:
2103 *parity = 'n';
2104 }
2105
2106 /* now calculate the baud rate */
2107
5f5a7a55
TA		 2108 clk_sel = s3c24xx_serial_getsource(port);
2109 sprintf(clk_name, "clk_uart_baud%d", clk_sel);
b497549a 2110
5f5a7a55 2111 clk = clk_get(port->dev, clk_name);
7cd88831 2112 if (!IS_ERR(clk))
5f5a7a55 2113 rate = clk_get_rate(clk);
b497549a
BD		 2114 else
2115 rate = 1;
2116
b497549a
BD		 2117 *baud = rate / (16 * (ubrdiv + 1));
2118 dbg("calculated baud %d\n", *baud);
2119 }
2120
2121}
2122
b497549a
BD		 2123static int __init
2124s3c24xx_serial_console_setup(struct console *co, char *options)
2125{
2126 struct uart_port *port;
2127 int baud = 9600;
2128 int bits = 8;
2129 int parity = 'n';
2130 int flow = 'n';
2131
2132 dbg("s3c24xx_serial_console_setup: co=%p (%d), %s\n",
2133 co, co->index, options);
2134
2135 /* is this a valid port */
2136
03d5e77b 2137 if (co->index == -1 || co->index >= CONFIG_SERIAL_SAMSUNG_UARTS)
b497549a
BD		 2138 co->index = 0;
2139
2140 port = &s3c24xx_serial_ports[co->index].port;
2141
2142 /* is the port configured? */
2143
ee430f16
TA		 2144 if (port->mapbase == 0x0)
2145 return -ENODEV;
b497549a
BD		 2146
2147 cons_uart = port;
2148
2149 dbg("s3c24xx_serial_console_setup: port=%p (%d)\n", port, co->index);
2150
2151 /*
2152 * Check whether an invalid uart number has been specified, and
2153 * if so, search for the first available port that does have
2154 * console support.
2155 */
2156 if (options)
2157 uart_parse_options(options, &baud, &parity, &bits, &flow);
2158 else
2159 s3c24xx_serial_get_options(port, &baud, &parity, &bits);
2160
2161 dbg("s3c24xx_serial_console_setup: baud %d\n", baud);
2162
2163 return uart_set_options(port, co, baud, parity, bits, flow);
2164}
2165
b497549a
BD		 2166static struct console s3c24xx_serial_console = {
2167 .name = S3C24XX_SERIAL_NAME,
2168 .device = uart_console_device,
2169 .flags = CON_PRINTBUFFER,
2170 .index = -1,
2171 .write = s3c24xx_serial_console_write,
5822a5df
TA		 2172 .setup = s3c24xx_serial_console_setup,
2173 .data = &s3c24xx_uart_drv,
b497549a 2174};
da121506
TA		 2175#endif /* CONFIG_SERIAL_SAMSUNG_CONSOLE */
2176
2177#ifdef CONFIG_CPU_S3C2410
2178static struct s3c24xx_serial_drv_data s3c2410_serial_drv_data = {
2179 .info = &(struct s3c24xx_uart_info) {
2180 .name = "Samsung S3C2410 UART",
2181 .type = PORT_S3C2410,
2182 .fifosize = 16,
2183 .rx_fifomask = S3C2410_UFSTAT_RXMASK,
2184 .rx_fifoshift = S3C2410_UFSTAT_RXSHIFT,
2185 .rx_fifofull = S3C2410_UFSTAT_RXFULL,
2186 .tx_fifofull = S3C2410_UFSTAT_TXFULL,
2187 .tx_fifomask = S3C2410_UFSTAT_TXMASK,
2188 .tx_fifoshift = S3C2410_UFSTAT_TXSHIFT,
2189 .def_clk_sel = S3C2410_UCON_CLKSEL0,
2190 .num_clks = 2,
2191 .clksel_mask = S3C2410_UCON_CLKMASK,
2192 .clksel_shift = S3C2410_UCON_CLKSHIFT,
2193 },
2194 .def_cfg = &(struct s3c2410_uartcfg) {
2195 .ucon = S3C2410_UCON_DEFAULT,
2196 .ufcon = S3C2410_UFCON_DEFAULT,
2197 },
2198};
2199#define S3C2410_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2410_serial_drv_data)
2200#else
2201#define S3C2410_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2202#endif
b497549a 2203
da121506
TA		 2204#ifdef CONFIG_CPU_S3C2412
2205static struct s3c24xx_serial_drv_data s3c2412_serial_drv_data = {
2206 .info = &(struct s3c24xx_uart_info) {
2207 .name = "Samsung S3C2412 UART",
2208 .type = PORT_S3C2412,
2209 .fifosize = 64,
2210 .has_divslot = 1,
2211 .rx_fifomask = S3C2440_UFSTAT_RXMASK,
2212 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
2213 .rx_fifofull = S3C2440_UFSTAT_RXFULL,
2214 .tx_fifofull = S3C2440_UFSTAT_TXFULL,
2215 .tx_fifomask = S3C2440_UFSTAT_TXMASK,
2216 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
2217 .def_clk_sel = S3C2410_UCON_CLKSEL2,
2218 .num_clks = 4,
2219 .clksel_mask = S3C2412_UCON_CLKMASK,
2220 .clksel_shift = S3C2412_UCON_CLKSHIFT,
2221 },
2222 .def_cfg = &(struct s3c2410_uartcfg) {
2223 .ucon = S3C2410_UCON_DEFAULT,
2224 .ufcon = S3C2410_UFCON_DEFAULT,
2225 },
2226};
2227#define S3C2412_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2412_serial_drv_data)
2228#else
2229#define S3C2412_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2230#endif
b497549a 2231
da121506 2232#if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2416) || \
b26469a8 2233 defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2442)
da121506
TA		 2234static struct s3c24xx_serial_drv_data s3c2440_serial_drv_data = {
2235 .info = &(struct s3c24xx_uart_info) {
2236 .name = "Samsung S3C2440 UART",
2237 .type = PORT_S3C2440,
2238 .fifosize = 64,
2239 .has_divslot = 1,
2240 .rx_fifomask = S3C2440_UFSTAT_RXMASK,
2241 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
2242 .rx_fifofull = S3C2440_UFSTAT_RXFULL,
2243 .tx_fifofull = S3C2440_UFSTAT_TXFULL,
2244 .tx_fifomask = S3C2440_UFSTAT_TXMASK,
2245 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
2246 .def_clk_sel = S3C2410_UCON_CLKSEL2,
2247 .num_clks = 4,
2248 .clksel_mask = S3C2412_UCON_CLKMASK,
2249 .clksel_shift = S3C2412_UCON_CLKSHIFT,
2250 },
2251 .def_cfg = &(struct s3c2410_uartcfg) {
2252 .ucon = S3C2410_UCON_DEFAULT,
2253 .ufcon = S3C2410_UFCON_DEFAULT,
2254 },
2255};
2256#define S3C2440_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2440_serial_drv_data)
2257#else
2258#define S3C2440_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2259#endif
b497549a 2260
953b53a7 2261#if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
da121506
TA		 2262static struct s3c24xx_serial_drv_data s3c6400_serial_drv_data = {
2263 .info = &(struct s3c24xx_uart_info) {
2264 .name = "Samsung S3C6400 UART",
2265 .type = PORT_S3C6400,
2266 .fifosize = 64,
2267 .has_divslot = 1,
2268 .rx_fifomask = S3C2440_UFSTAT_RXMASK,
2269 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
2270 .rx_fifofull = S3C2440_UFSTAT_RXFULL,
2271 .tx_fifofull = S3C2440_UFSTAT_TXFULL,
2272 .tx_fifomask = S3C2440_UFSTAT_TXMASK,
2273 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
2274 .def_clk_sel = S3C2410_UCON_CLKSEL2,
2275 .num_clks = 4,
2276 .clksel_mask = S3C6400_UCON_CLKMASK,
2277 .clksel_shift = S3C6400_UCON_CLKSHIFT,
2278 },
2279 .def_cfg = &(struct s3c2410_uartcfg) {
2280 .ucon = S3C2410_UCON_DEFAULT,
2281 .ufcon = S3C2410_UFCON_DEFAULT,
2282 },
2283};
2284#define S3C6400_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c6400_serial_drv_data)
2285#else
2286#define S3C6400_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2287#endif
b497549a 2288
da121506
TA		 2289#ifdef CONFIG_CPU_S5PV210
2290static struct s3c24xx_serial_drv_data s5pv210_serial_drv_data = {
2291 .info = &(struct s3c24xx_uart_info) {
2292 .name = "Samsung S5PV210 UART",
2293 .type = PORT_S3C6400,
2294 .has_divslot = 1,
2295 .rx_fifomask = S5PV210_UFSTAT_RXMASK,
2296 .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT,
2297 .rx_fifofull = S5PV210_UFSTAT_RXFULL,
2298 .tx_fifofull = S5PV210_UFSTAT_TXFULL,
2299 .tx_fifomask = S5PV210_UFSTAT_TXMASK,
2300 .tx_fifoshift = S5PV210_UFSTAT_TXSHIFT,
2301 .def_clk_sel = S3C2410_UCON_CLKSEL0,
2302 .num_clks = 2,
2303 .clksel_mask = S5PV210_UCON_CLKMASK,
2304 .clksel_shift = S5PV210_UCON_CLKSHIFT,
2305 },
2306 .def_cfg = &(struct s3c2410_uartcfg) {
2307 .ucon = S5PV210_UCON_DEFAULT,
2308 .ufcon = S5PV210_UFCON_DEFAULT,
2309 },
2310 .fifosize = { 256, 64, 16, 16 },
2311};
2312#define S5PV210_SERIAL_DRV_DATA ((kernel_ulong_t)&s5pv210_serial_drv_data)
2313#else
2314#define S5PV210_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2315#endif
b497549a 2316
33f88136 2317#if defined(CONFIG_ARCH_EXYNOS)
31ec77ac
CC		 2318#define EXYNOS_COMMON_SERIAL_DRV_DATA \
2319 .info = &(struct s3c24xx_uart_info) { \
2320 .name = "Samsung Exynos UART", \
2321 .type = PORT_S3C6400, \
2322 .has_divslot = 1, \
2323 .rx_fifomask = S5PV210_UFSTAT_RXMASK, \
2324 .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT, \
2325 .rx_fifofull = S5PV210_UFSTAT_RXFULL, \
2326 .tx_fifofull = S5PV210_UFSTAT_TXFULL, \
2327 .tx_fifomask = S5PV210_UFSTAT_TXMASK, \
2328 .tx_fifoshift = S5PV210_UFSTAT_TXSHIFT, \
2329 .def_clk_sel = S3C2410_UCON_CLKSEL0, \
2330 .num_clks = 1, \
2331 .clksel_mask = 0, \
2332 .clksel_shift = 0, \
2333 }, \
2334 .def_cfg = &(struct s3c2410_uartcfg) { \
2335 .ucon = S5PV210_UCON_DEFAULT, \
2336 .ufcon = S5PV210_UFCON_DEFAULT, \
2337 .has_fracval = 1, \
2338 } \
2339
da121506 2340static struct s3c24xx_serial_drv_data exynos4210_serial_drv_data = {
31ec77ac 2341 EXYNOS_COMMON_SERIAL_DRV_DATA,
da121506
TA		 2342 .fifosize = { 256, 64, 16, 16 },
2343};
31ec77ac
CC		 2344
2345static struct s3c24xx_serial_drv_data exynos5433_serial_drv_data = {
2346 EXYNOS_COMMON_SERIAL_DRV_DATA,
2347 .fifosize = { 64, 256, 16, 256 },
2348};
2349
da121506 2350#define EXYNOS4210_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos4210_serial_drv_data)
31ec77ac 2351#define EXYNOS5433_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos5433_serial_drv_data)
da121506
TA		 2352#else
2353#define EXYNOS4210_SERIAL_DRV_DATA (kernel_ulong_t)NULL
31ec77ac 2354#define EXYNOS5433_SERIAL_DRV_DATA (kernel_ulong_t)NULL
da121506 2355#endif
b497549a 2356
24ee4df1 2357static const struct platform_device_id s3c24xx_serial_driver_ids[] = {
da121506
TA		 2358 {
2359 .name = "s3c2410-uart",
2360 .driver_data = S3C2410_SERIAL_DRV_DATA,
2361 }, {
2362 .name = "s3c2412-uart",
2363 .driver_data = S3C2412_SERIAL_DRV_DATA,
2364 }, {
2365 .name = "s3c2440-uart",
2366 .driver_data = S3C2440_SERIAL_DRV_DATA,
2367 }, {
2368 .name = "s3c6400-uart",
2369 .driver_data = S3C6400_SERIAL_DRV_DATA,
2370 }, {
2371 .name = "s5pv210-uart",
2372 .driver_data = S5PV210_SERIAL_DRV_DATA,
2373 }, {
2374 .name = "exynos4210-uart",
2375 .driver_data = EXYNOS4210_SERIAL_DRV_DATA,
31ec77ac
CC		 2376 }, {
2377 .name = "exynos5433-uart",
2378 .driver_data = EXYNOS5433_SERIAL_DRV_DATA,
da121506
TA		 2379 },
2380 { },
2381};
2382MODULE_DEVICE_TABLE(platform, s3c24xx_serial_driver_ids);
2383
26c919e1
TA		 2384#ifdef CONFIG_OF
2385static const struct of_device_id s3c24xx_uart_dt_match[] = {
666ca0b9
HS		 2386 { .compatible = "samsung,s3c2410-uart",
2387 .data = (void *)S3C2410_SERIAL_DRV_DATA },
2388 { .compatible = "samsung,s3c2412-uart",
2389 .data = (void *)S3C2412_SERIAL_DRV_DATA },
2390 { .compatible = "samsung,s3c2440-uart",
2391 .data = (void *)S3C2440_SERIAL_DRV_DATA },
2392 { .compatible = "samsung,s3c6400-uart",
2393 .data = (void *)S3C6400_SERIAL_DRV_DATA },
2394 { .compatible = "samsung,s5pv210-uart",
2395 .data = (void *)S5PV210_SERIAL_DRV_DATA },
26c919e1 2396 { .compatible = "samsung,exynos4210-uart",
a169a888 2397 .data = (void *)EXYNOS4210_SERIAL_DRV_DATA },
31ec77ac
CC		 2398 { .compatible = "samsung,exynos5433-uart",
2399 .data = (void *)EXYNOS5433_SERIAL_DRV_DATA },
26c919e1
TA		 2400 {},
2401};
2402MODULE_DEVICE_TABLE(of, s3c24xx_uart_dt_match);
26c919e1
TA		 2403#endif
2404
da121506
TA		 2405static struct platform_driver samsung_serial_driver = {
2406 .probe = s3c24xx_serial_probe,
2d47b716 2407 .remove = s3c24xx_serial_remove,
da121506
TA		 2408 .id_table = s3c24xx_serial_driver_ids,
2409 .driver = {
2410 .name = "samsung-uart",
da121506 2411 .pm = SERIAL_SAMSUNG_PM_OPS,
905f4ba2 2412 .of_match_table = of_match_ptr(s3c24xx_uart_dt_match),
da121506
TA		 2413 },
2414};
b497549a 2415
6f134c3c 2416module_platform_driver(samsung_serial_driver);
b497549a 2417
c3bda295 2418#ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
b94ba032
TF		 2419/*
2420 * Early console.
2421 */
2422
2423struct samsung_early_console_data {
2424 u32 txfull_mask;
2425};
2426
2427static void samsung_early_busyuart(struct uart_port *port)
2428{
2429 while (!(readl(port->membase + S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXFE))
2430 ;
2431}
2432
2433static void samsung_early_busyuart_fifo(struct uart_port *port)
2434{
2435 struct samsung_early_console_data *data = port->private_data;
2436
2437 while (readl(port->membase + S3C2410_UFSTAT) & data->txfull_mask)
2438 ;
2439}
2440
2441static void samsung_early_putc(struct uart_port *port, int c)
2442{
2443 if (readl(port->membase + S3C2410_UFCON) & S3C2410_UFCON_FIFOMODE)
2444 samsung_early_busyuart_fifo(port);
2445 else
2446 samsung_early_busyuart(port);
2447
2448 writeb(c, port->membase + S3C2410_UTXH);
2449}
2450
2451static void samsung_early_write(struct console *con, const char *s, unsigned n)
2452{
2453 struct earlycon_device *dev = con->data;
2454
2455 uart_console_write(&dev->port, s, n, samsung_early_putc);
2456}
2457
2458static int __init samsung_early_console_setup(struct earlycon_device *device,
2459 const char *opt)
2460{
2461 if (!device->port.membase)
2462 return -ENODEV;
2463
2464 device->con->write = samsung_early_write;
2465 return 0;
2466}
2467
2468/* S3C2410 */
2469static struct samsung_early_console_data s3c2410_early_console_data = {
2470 .txfull_mask = S3C2410_UFSTAT_TXFULL,
2471};
2472
2473static int __init s3c2410_early_console_setup(struct earlycon_device *device,
2474 const char *opt)
2475{
2476 device->port.private_data = &s3c2410_early_console_data;
2477 return samsung_early_console_setup(device, opt);
2478}
2479OF_EARLYCON_DECLARE(s3c2410, "samsung,s3c2410-uart",
2480 s3c2410_early_console_setup);
b94ba032
TF		 2481
2482/* S3C2412, S3C2440, S3C64xx */
2483static struct samsung_early_console_data s3c2440_early_console_data = {
2484 .txfull_mask = S3C2440_UFSTAT_TXFULL,
2485};
2486
2487static int __init s3c2440_early_console_setup(struct earlycon_device *device,
2488 const char *opt)
2489{
2490 device->port.private_data = &s3c2440_early_console_data;
2491 return samsung_early_console_setup(device, opt);
2492}
2493OF_EARLYCON_DECLARE(s3c2412, "samsung,s3c2412-uart",
2494 s3c2440_early_console_setup);
2495OF_EARLYCON_DECLARE(s3c2440, "samsung,s3c2440-uart",
2496 s3c2440_early_console_setup);
2497OF_EARLYCON_DECLARE(s3c6400, "samsung,s3c6400-uart",
2498 s3c2440_early_console_setup);
b94ba032
TF		 2499
2500/* S5PV210, EXYNOS */
2501static struct samsung_early_console_data s5pv210_early_console_data = {
2502 .txfull_mask = S5PV210_UFSTAT_TXFULL,
2503};
2504
2505static int __init s5pv210_early_console_setup(struct earlycon_device *device,
2506 const char *opt)
2507{
2508 device->port.private_data = &s5pv210_early_console_data;
2509 return samsung_early_console_setup(device, opt);
2510}
2511OF_EARLYCON_DECLARE(s5pv210, "samsung,s5pv210-uart",
2512 s5pv210_early_console_setup);
2513OF_EARLYCON_DECLARE(exynos4210, "samsung,exynos4210-uart",
2514 s5pv210_early_console_setup);
c3bda295 2515#endif
b94ba032 2516
da121506 2517MODULE_ALIAS("platform:samsung-uart");
b497549a
BD		 2518MODULE_DESCRIPTION("Samsung SoC Serial port driver");
2519MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
2520MODULE_LICENSE("GPL v2");
Linux 6.x block layer and io_uring tree(s)