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serial: icom: fix error return code
[linux-2.6-block.git] / drivers / tty / serial / samsung.c
CommitLineData
99edb3d1 1/*
b497549a
BD		 2 * Driver core for Samsung SoC onboard UARTs.
3 *
ccae941e 4 * Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics
b497549a
BD		 5 * http://armlinux.simtec.co.uk/
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12/* Hote on 2410 error handling
13 *
14 * The s3c2410 manual has a love/hate affair with the contents of the
15 * UERSTAT register in the UART blocks, and keeps marking some of the
16 * error bits as reserved. Having checked with the s3c2410x01,
17 * it copes with BREAKs properly, so I am happy to ignore the RESERVED
18 * feature from the latter versions of the manual.
19 *
20 * If it becomes aparrent that latter versions of the 2410 remove these
21 * bits, then action will have to be taken to differentiate the versions
22 * and change the policy on BREAK
23 *
24 * BJD, 04-Nov-2004
25*/
26
27#if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
28#define SUPPORT_SYSRQ
29#endif
30
31#include <linux/module.h>
32#include <linux/ioport.h>
33#include <linux/io.h>
34#include <linux/platform_device.h>
35#include <linux/init.h>
36#include <linux/sysrq.h>
37#include <linux/console.h>
38#include <linux/tty.h>
39#include <linux/tty_flip.h>
40#include <linux/serial_core.h>
41#include <linux/serial.h>
9ee51f01 42#include <linux/serial_s3c.h>
b497549a
BD		 43#include <linux/delay.h>
44#include <linux/clk.h>
30555476 45#include <linux/cpufreq.h>
26c919e1 46#include <linux/of.h>
b497549a
BD		 47
48#include <asm/irq.h>
49
b497549a
BD		 50#include "samsung.h"
51
e4ac92df
JP		 52#if defined(CONFIG_SERIAL_SAMSUNG_DEBUG) && \
53 defined(CONFIG_DEBUG_LL) && \
54 !defined(MODULE)
55
56extern void printascii(const char *);
57
58__printf(1, 2)
59static void dbg(const char *fmt, ...)
60{
61 va_list va;
62 char buff[256];
63
64 va_start(va, fmt);
a859c8b2 65 vscnprintf(buff, sizeof(buff), fmt, va);
e4ac92df
JP		 66 va_end(va);
67
68 printascii(buff);
69}
70
71#else
72#define dbg(fmt, ...) do { if (0) no_printk(fmt, ##__VA_ARGS__); } while (0)
73#endif
74
b497549a
BD		 75/* UART name and device definitions */
76
77#define S3C24XX_SERIAL_NAME "ttySAC"
78#define S3C24XX_SERIAL_MAJOR 204
79#define S3C24XX_SERIAL_MINOR 64
80
b497549a
BD		 81/* macros to change one thing to another */
82
83#define tx_enabled(port) ((port)->unused[0])
84#define rx_enabled(port) ((port)->unused[1])
85
25985edc 86/* flag to ignore all characters coming in */
b497549a
BD		 87#define RXSTAT_DUMMY_READ (0x10000000)
88
89static inline struct s3c24xx_uart_port *to_ourport(struct uart_port *port)
90{
91 return container_of(port, struct s3c24xx_uart_port, port);
92}
93
94/* translate a port to the device name */
95
96static inline const char *s3c24xx_serial_portname(struct uart_port *port)
97{
98 return to_platform_device(port->dev)->name;
99}
100
101static int s3c24xx_serial_txempty_nofifo(struct uart_port *port)
102{
9303ac15 103 return rd_regl(port, S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE;
b497549a
BD		 104}
105
88bb4ea1
TA		 106/*
107 * s3c64xx and later SoC's include the interrupt mask and status registers in
108 * the controller itself, unlike the s3c24xx SoC's which have these registers
109 * in the interrupt controller. Check if the port type is s3c64xx or higher.
110 */
111static int s3c24xx_serial_has_interrupt_mask(struct uart_port *port)
112{
113 return to_ourport(port)->info->type == PORT_S3C6400;
114}
115
b497549a
BD		 116static void s3c24xx_serial_rx_enable(struct uart_port *port)
117{
118 unsigned long flags;
119 unsigned int ucon, ufcon;
120 int count = 10000;
121
122 spin_lock_irqsave(&port->lock, flags);
123
124 while (--count && !s3c24xx_serial_txempty_nofifo(port))
125 udelay(100);
126
127 ufcon = rd_regl(port, S3C2410_UFCON);
128 ufcon |= S3C2410_UFCON_RESETRX;
129 wr_regl(port, S3C2410_UFCON, ufcon);
130
131 ucon = rd_regl(port, S3C2410_UCON);
132 ucon |= S3C2410_UCON_RXIRQMODE;
133 wr_regl(port, S3C2410_UCON, ucon);
134
135 rx_enabled(port) = 1;
136 spin_unlock_irqrestore(&port->lock, flags);
137}
138
139static void s3c24xx_serial_rx_disable(struct uart_port *port)
140{
141 unsigned long flags;
142 unsigned int ucon;
143
144 spin_lock_irqsave(&port->lock, flags);
145
146 ucon = rd_regl(port, S3C2410_UCON);
147 ucon &= ~S3C2410_UCON_RXIRQMODE;
148 wr_regl(port, S3C2410_UCON, ucon);
149
150 rx_enabled(port) = 0;
151 spin_unlock_irqrestore(&port->lock, flags);
152}
153
154static void s3c24xx_serial_stop_tx(struct uart_port *port)
155{
b73c289c
BD		 156 struct s3c24xx_uart_port *ourport = to_ourport(port);
157
b497549a 158 if (tx_enabled(port)) {
88bb4ea1
TA		 159 if (s3c24xx_serial_has_interrupt_mask(port))
160 __set_bit(S3C64XX_UINTM_TXD,
161 portaddrl(port, S3C64XX_UINTM));
162 else
163 disable_irq_nosync(ourport->tx_irq);
b497549a
BD		 164 tx_enabled(port) = 0;
165 if (port->flags & UPF_CONS_FLOW)
166 s3c24xx_serial_rx_enable(port);
167 }
168}
169
170static void s3c24xx_serial_start_tx(struct uart_port *port)
171{
b73c289c
BD		 172 struct s3c24xx_uart_port *ourport = to_ourport(port);
173
b497549a
BD		 174 if (!tx_enabled(port)) {
175 if (port->flags & UPF_CONS_FLOW)
176 s3c24xx_serial_rx_disable(port);
177
88bb4ea1
TA		 178 if (s3c24xx_serial_has_interrupt_mask(port))
179 __clear_bit(S3C64XX_UINTM_TXD,
180 portaddrl(port, S3C64XX_UINTM));
181 else
182 enable_irq(ourport->tx_irq);
b497549a
BD		 183 tx_enabled(port) = 1;
184 }
185}
186
b497549a
BD		 187static void s3c24xx_serial_stop_rx(struct uart_port *port)
188{
b73c289c
BD		 189 struct s3c24xx_uart_port *ourport = to_ourport(port);
190
b497549a
BD		 191 if (rx_enabled(port)) {
192 dbg("s3c24xx_serial_stop_rx: port=%p\n", port);
88bb4ea1
TA		 193 if (s3c24xx_serial_has_interrupt_mask(port))
194 __set_bit(S3C64XX_UINTM_RXD,
195 portaddrl(port, S3C64XX_UINTM));
196 else
197 disable_irq_nosync(ourport->rx_irq);
b497549a
BD		 198 rx_enabled(port) = 0;
199 }
200}
201
b497549a
BD		 202static inline struct s3c24xx_uart_info *s3c24xx_port_to_info(struct uart_port *port)
203{
204 return to_ourport(port)->info;
205}
206
207static inline struct s3c2410_uartcfg *s3c24xx_port_to_cfg(struct uart_port *port)
208{
4d84e970
TA		 209 struct s3c24xx_uart_port *ourport;
210
b497549a
BD		 211 if (port->dev == NULL)
212 return NULL;
213
4d84e970
TA		 214 ourport = container_of(port, struct s3c24xx_uart_port, port);
215 return ourport->cfg;
b497549a
BD		 216}
217
218static int s3c24xx_serial_rx_fifocnt(struct s3c24xx_uart_port *ourport,
219 unsigned long ufstat)
220{
221 struct s3c24xx_uart_info *info = ourport->info;
222
223 if (ufstat & info->rx_fifofull)
da121506 224 return ourport->port.fifosize;
b497549a
BD		 225
226 return (ufstat & info->rx_fifomask) >> info->rx_fifoshift;
227}
228
229
230/* ? - where has parity gone?? */
231#define S3C2410_UERSTAT_PARITY (0x1000)
232
233static irqreturn_t
234s3c24xx_serial_rx_chars(int irq, void *dev_id)
235{
236 struct s3c24xx_uart_port *ourport = dev_id;
237 struct uart_port *port = &ourport->port;
b497549a 238 unsigned int ufcon, ch, flag, ufstat, uerstat;
c15c3747 239 unsigned long flags;
b497549a
BD		 240 int max_count = 64;
241
c15c3747
TA		 242 spin_lock_irqsave(&port->lock, flags);
243
b497549a
BD		 244 while (max_count-- > 0) {
245 ufcon = rd_regl(port, S3C2410_UFCON);
246 ufstat = rd_regl(port, S3C2410_UFSTAT);
247
248 if (s3c24xx_serial_rx_fifocnt(ourport, ufstat) == 0)
249 break;
250
251 uerstat = rd_regl(port, S3C2410_UERSTAT);
252 ch = rd_regb(port, S3C2410_URXH);
253
254 if (port->flags & UPF_CONS_FLOW) {
255 int txe = s3c24xx_serial_txempty_nofifo(port);
256
257 if (rx_enabled(port)) {
258 if (!txe) {
259 rx_enabled(port) = 0;
260 continue;
261 }
262 } else {
263 if (txe) {
264 ufcon |= S3C2410_UFCON_RESETRX;
265 wr_regl(port, S3C2410_UFCON, ufcon);
266 rx_enabled(port) = 1;
f5693ea2
VK		 267 spin_unlock_irqrestore(&port->lock,
268 flags);
b497549a
BD		 269 goto out;
270 }
271 continue;
272 }
273 }
274
275 /* insert the character into the buffer */
276
277 flag = TTY_NORMAL;
278 port->icount.rx++;
279
280 if (unlikely(uerstat & S3C2410_UERSTAT_ANY)) {
281 dbg("rxerr: port ch=0x%02x, rxs=0x%08x\n",
282 ch, uerstat);
283
284 /* check for break */
285 if (uerstat & S3C2410_UERSTAT_BREAK) {
286 dbg("break!\n");
287 port->icount.brk++;
288 if (uart_handle_break(port))
9303ac15 289 goto ignore_char;
b497549a
BD		 290 }
291
292 if (uerstat & S3C2410_UERSTAT_FRAME)
293 port->icount.frame++;
294 if (uerstat & S3C2410_UERSTAT_OVERRUN)
295 port->icount.overrun++;
296
297 uerstat &= port->read_status_mask;
298
299 if (uerstat & S3C2410_UERSTAT_BREAK)
300 flag = TTY_BREAK;
301 else if (uerstat & S3C2410_UERSTAT_PARITY)
302 flag = TTY_PARITY;
303 else if (uerstat & (S3C2410_UERSTAT_FRAME |
304 S3C2410_UERSTAT_OVERRUN))
305 flag = TTY_FRAME;
306 }
307
308 if (uart_handle_sysrq_char(port, ch))
309 goto ignore_char;
310
311 uart_insert_char(port, uerstat, S3C2410_UERSTAT_OVERRUN,
312 ch, flag);
313
314 ignore_char:
315 continue;
316 }
f5693ea2
VK		 317
318 spin_unlock_irqrestore(&port->lock, flags);
2e124b4a 319 tty_flip_buffer_push(&port->state->port);
b497549a
BD		 320
321 out:
322 return IRQ_HANDLED;
323}
324
325static irqreturn_t s3c24xx_serial_tx_chars(int irq, void *id)
326{
327 struct s3c24xx_uart_port *ourport = id;
328 struct uart_port *port = &ourport->port;
ebd2c8f6 329 struct circ_buf *xmit = &port->state->xmit;
c15c3747 330 unsigned long flags;
b497549a
BD		 331 int count = 256;
332
c15c3747
TA		 333 spin_lock_irqsave(&port->lock, flags);
334
b497549a
BD		 335 if (port->x_char) {
336 wr_regb(port, S3C2410_UTXH, port->x_char);
337 port->icount.tx++;
338 port->x_char = 0;
339 goto out;
340 }
341
25985edc 342 /* if there isn't anything more to transmit, or the uart is now
b497549a
BD		 343 * stopped, disable the uart and exit
344 */
345
346 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
347 s3c24xx_serial_stop_tx(port);
348 goto out;
349 }
350
351 /* try and drain the buffer... */
352
353 while (!uart_circ_empty(xmit) && count-- > 0) {
354 if (rd_regl(port, S3C2410_UFSTAT) & ourport->info->tx_fifofull)
355 break;
356
357 wr_regb(port, S3C2410_UTXH, xmit->buf[xmit->tail]);
358 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
359 port->icount.tx++;
360 }
361
c15c3747
TA		 362 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) {
363 spin_unlock(&port->lock);
b497549a 364 uart_write_wakeup(port);
c15c3747
TA		 365 spin_lock(&port->lock);
366 }
b497549a
BD		 367
368 if (uart_circ_empty(xmit))
369 s3c24xx_serial_stop_tx(port);
370
371 out:
c15c3747 372 spin_unlock_irqrestore(&port->lock, flags);
b497549a
BD		 373 return IRQ_HANDLED;
374}
375
88bb4ea1
TA		 376/* interrupt handler for s3c64xx and later SoC's.*/
377static irqreturn_t s3c64xx_serial_handle_irq(int irq, void *id)
378{
379 struct s3c24xx_uart_port *ourport = id;
380 struct uart_port *port = &ourport->port;
381 unsigned int pend = rd_regl(port, S3C64XX_UINTP);
88bb4ea1
TA		 382 irqreturn_t ret = IRQ_HANDLED;
383
88bb4ea1
TA		 384 if (pend & S3C64XX_UINTM_RXD_MSK) {
385 ret = s3c24xx_serial_rx_chars(irq, id);
386 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_RXD_MSK);
387 }
388 if (pend & S3C64XX_UINTM_TXD_MSK) {
389 ret = s3c24xx_serial_tx_chars(irq, id);
390 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_TXD_MSK);
391 }
88bb4ea1
TA		 392 return ret;
393}
394
b497549a
BD		 395static unsigned int s3c24xx_serial_tx_empty(struct uart_port *port)
396{
397 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
398 unsigned long ufstat = rd_regl(port, S3C2410_UFSTAT);
399 unsigned long ufcon = rd_regl(port, S3C2410_UFCON);
400
401 if (ufcon & S3C2410_UFCON_FIFOMODE) {
402 if ((ufstat & info->tx_fifomask) != 0 ||
403 (ufstat & info->tx_fifofull))
404 return 0;
405
406 return 1;
407 }
408
409 return s3c24xx_serial_txempty_nofifo(port);
410}
411
412/* no modem control lines */
413static unsigned int s3c24xx_serial_get_mctrl(struct uart_port *port)
414{
415 unsigned int umstat = rd_regb(port, S3C2410_UMSTAT);
416
417 if (umstat & S3C2410_UMSTAT_CTS)
418 return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
419 else
420 return TIOCM_CAR | TIOCM_DSR;
421}
422
423static void s3c24xx_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
424{
2d1e5a48
JMG		 425 unsigned int umcon = rd_regl(port, S3C2410_UMCON);
426
427 if (mctrl & TIOCM_RTS)
428 umcon |= S3C2410_UMCOM_RTS_LOW;
429 else
430 umcon &= ~S3C2410_UMCOM_RTS_LOW;
431
432 wr_regl(port, S3C2410_UMCON, umcon);
b497549a
BD		 433}
434
435static void s3c24xx_serial_break_ctl(struct uart_port *port, int break_state)
436{
437 unsigned long flags;
438 unsigned int ucon;
439
440 spin_lock_irqsave(&port->lock, flags);
441
442 ucon = rd_regl(port, S3C2410_UCON);
443
444 if (break_state)
445 ucon |= S3C2410_UCON_SBREAK;
446 else
447 ucon &= ~S3C2410_UCON_SBREAK;
448
449 wr_regl(port, S3C2410_UCON, ucon);
450
451 spin_unlock_irqrestore(&port->lock, flags);
452}
453
454static void s3c24xx_serial_shutdown(struct uart_port *port)
455{
456 struct s3c24xx_uart_port *ourport = to_ourport(port);
457
458 if (ourport->tx_claimed) {
88bb4ea1
TA		 459 if (!s3c24xx_serial_has_interrupt_mask(port))
460 free_irq(ourport->tx_irq, ourport);
b497549a
BD		 461 tx_enabled(port) = 0;
462 ourport->tx_claimed = 0;
463 }
464
465 if (ourport->rx_claimed) {
88bb4ea1
TA		 466 if (!s3c24xx_serial_has_interrupt_mask(port))
467 free_irq(ourport->rx_irq, ourport);
b497549a
BD		 468 ourport->rx_claimed = 0;
469 rx_enabled(port) = 0;
470 }
b497549a 471
88bb4ea1
TA		 472 /* Clear pending interrupts and mask all interrupts */
473 if (s3c24xx_serial_has_interrupt_mask(port)) {
b6ad2935
TF		 474 free_irq(port->irq, ourport);
475
88bb4ea1
TA		 476 wr_regl(port, S3C64XX_UINTP, 0xf);
477 wr_regl(port, S3C64XX_UINTM, 0xf);
478 }
479}
b497549a
BD		 480
481static int s3c24xx_serial_startup(struct uart_port *port)
482{
483 struct s3c24xx_uart_port *ourport = to_ourport(port);
484 int ret;
485
e4ac92df
JP		 486 dbg("s3c24xx_serial_startup: port=%p (%08llx,%p)\n",
487 port, (unsigned long long)port->mapbase, port->membase);
b497549a
BD		 488
489 rx_enabled(port) = 1;
490
b73c289c 491 ret = request_irq(ourport->rx_irq, s3c24xx_serial_rx_chars, 0,
b497549a
BD		 492 s3c24xx_serial_portname(port), ourport);
493
494 if (ret != 0) {
d20925e1 495 dev_err(port->dev, "cannot get irq %d\n", ourport->rx_irq);
b497549a
BD		 496 return ret;
497 }
498
499 ourport->rx_claimed = 1;
500
501 dbg("requesting tx irq...\n");
502
503 tx_enabled(port) = 1;
504
b73c289c 505 ret = request_irq(ourport->tx_irq, s3c24xx_serial_tx_chars, 0,
b497549a
BD		 506 s3c24xx_serial_portname(port), ourport);
507
508 if (ret) {
d20925e1 509 dev_err(port->dev, "cannot get irq %d\n", ourport->tx_irq);
b497549a
BD		 510 goto err;
511 }
512
513 ourport->tx_claimed = 1;
514
515 dbg("s3c24xx_serial_startup ok\n");
516
517 /* the port reset code should have done the correct
518 * register setup for the port controls */
519
520 return ret;
521
522 err:
523 s3c24xx_serial_shutdown(port);
524 return ret;
525}
526
88bb4ea1
TA		 527static int s3c64xx_serial_startup(struct uart_port *port)
528{
529 struct s3c24xx_uart_port *ourport = to_ourport(port);
530 int ret;
531
e4ac92df
JP		 532 dbg("s3c64xx_serial_startup: port=%p (%08llx,%p)\n",
533 port, (unsigned long long)port->mapbase, port->membase);
88bb4ea1 534
b6ad2935
TF		 535 wr_regl(port, S3C64XX_UINTM, 0xf);
536
88bb4ea1
TA		 537 ret = request_irq(port->irq, s3c64xx_serial_handle_irq, IRQF_SHARED,
538 s3c24xx_serial_portname(port), ourport);
539 if (ret) {
d20925e1 540 dev_err(port->dev, "cannot get irq %d\n", port->irq);
88bb4ea1
TA		 541 return ret;
542 }
543
544 /* For compatibility with s3c24xx Soc's */
545 rx_enabled(port) = 1;
546 ourport->rx_claimed = 1;
547 tx_enabled(port) = 0;
548 ourport->tx_claimed = 1;
549
550 /* Enable Rx Interrupt */
551 __clear_bit(S3C64XX_UINTM_RXD, portaddrl(port, S3C64XX_UINTM));
552 dbg("s3c64xx_serial_startup ok\n");
553 return ret;
554}
555
b497549a
BD		 556/* power power management control */
557
558static void s3c24xx_serial_pm(struct uart_port *port, unsigned int level,
559 unsigned int old)
560{
561 struct s3c24xx_uart_port *ourport = to_ourport(port);
562
30555476
BD		 563 ourport->pm_level = level;
564
b497549a
BD		 565 switch (level) {
566 case 3:
7cd88831 567 if (!IS_ERR(ourport->baudclk))
9484b009 568 clk_disable_unprepare(ourport->baudclk);
b497549a 569
9484b009 570 clk_disable_unprepare(ourport->clk);
b497549a
BD		 571 break;
572
573 case 0:
9484b009 574 clk_prepare_enable(ourport->clk);
b497549a 575
7cd88831 576 if (!IS_ERR(ourport->baudclk))
9484b009 577 clk_prepare_enable(ourport->baudclk);
b497549a
BD		 578
579 break;
580 default:
d20925e1 581 dev_err(port->dev, "s3c24xx_serial: unknown pm %d\n", level);
b497549a
BD		 582 }
583}
584
585/* baud rate calculation
586 *
587 * The UARTs on the S3C2410/S3C2440 can take their clocks from a number
588 * of different sources, including the peripheral clock ("pclk") and an
589 * external clock ("uclk"). The S3C2440 also adds the core clock ("fclk")
590 * with a programmable extra divisor.
591 *
592 * The following code goes through the clock sources, and calculates the
593 * baud clocks (and the resultant actual baud rates) and then tries to
594 * pick the closest one and select that.
595 *
596*/
597
5f5a7a55 598#define MAX_CLK_NAME_LENGTH 15
b497549a 599
5f5a7a55 600static inline int s3c24xx_serial_getsource(struct uart_port *port)
b497549a
BD		 601{
602 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
5f5a7a55 603 unsigned int ucon;
b497549a 604
5f5a7a55
TA		 605 if (info->num_clks == 1)
606 return 0;
b497549a 607
5f5a7a55
TA		 608 ucon = rd_regl(port, S3C2410_UCON);
609 ucon &= info->clksel_mask;
610 return ucon >> info->clksel_shift;
b497549a
BD		 611}
612
5f5a7a55
TA		 613static void s3c24xx_serial_setsource(struct uart_port *port,
614 unsigned int clk_sel)
b497549a 615{
5f5a7a55
TA		 616 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
617 unsigned int ucon;
b497549a 618
5f5a7a55
TA		 619 if (info->num_clks == 1)
620 return;
090f848d 621
5f5a7a55
TA		 622 ucon = rd_regl(port, S3C2410_UCON);
623 if ((ucon & info->clksel_mask) >> info->clksel_shift == clk_sel)
624 return;
b497549a 625
5f5a7a55
TA		 626 ucon &= ~info->clksel_mask;
627 ucon |= clk_sel << info->clksel_shift;
628 wr_regl(port, S3C2410_UCON, ucon);
b497549a
BD		 629}
630
5f5a7a55
TA		 631static unsigned int s3c24xx_serial_getclk(struct s3c24xx_uart_port *ourport,
632 unsigned int req_baud, struct clk **best_clk,
633 unsigned int *clk_num)
b497549a 634{
5f5a7a55
TA		 635 struct s3c24xx_uart_info *info = ourport->info;
636 struct clk *clk;
637 unsigned long rate;
638 unsigned int cnt, baud, quot, clk_sel, best_quot = 0;
639 char clkname[MAX_CLK_NAME_LENGTH];
640 int calc_deviation, deviation = (1 << 30) - 1;
641
5f5a7a55
TA		 642 clk_sel = (ourport->cfg->clk_sel) ? ourport->cfg->clk_sel :
643 ourport->info->def_clk_sel;
644 for (cnt = 0; cnt < info->num_clks; cnt++) {
645 if (!(clk_sel & (1 << cnt)))
646 continue;
647
648 sprintf(clkname, "clk_uart_baud%d", cnt);
649 clk = clk_get(ourport->port.dev, clkname);
7cd88831 650 if (IS_ERR(clk))
5f5a7a55
TA		 651 continue;
652
653 rate = clk_get_rate(clk);
654 if (!rate)
655 continue;
656
657 if (ourport->info->has_divslot) {
658 unsigned long div = rate / req_baud;
659
660 /* The UDIVSLOT register on the newer UARTs allows us to
661 * get a divisor adjustment of 1/16th on the baud clock.
662 *
663 * We don't keep the UDIVSLOT value (the 16ths we
664 * calculated by not multiplying the baud by 16) as it
665 * is easy enough to recalculate.
666 */
667
668 quot = div / 16;
669 baud = rate / div;
670 } else {
671 quot = (rate + (8 * req_baud)) / (16 * req_baud);
672 baud = rate / (quot * 16);
b497549a 673 }
5f5a7a55 674 quot--;
b497549a 675
5f5a7a55
TA		 676 calc_deviation = req_baud - baud;
677 if (calc_deviation < 0)
678 calc_deviation = -calc_deviation;
b497549a 679
5f5a7a55
TA		 680 if (calc_deviation < deviation) {
681 *best_clk = clk;
682 best_quot = quot;
683 *clk_num = cnt;
684 deviation = calc_deviation;
b497549a
BD		 685 }
686 }
687
5f5a7a55 688 return best_quot;
b497549a
BD		 689}
690
090f848d
BD		 691/* udivslot_table[]
692 *
693 * This table takes the fractional value of the baud divisor and gives
694 * the recommended setting for the UDIVSLOT register.
695 */
696static u16 udivslot_table[16] = {
697 [0] = 0x0000,
698 [1] = 0x0080,
699 [2] = 0x0808,
700 [3] = 0x0888,
701 [4] = 0x2222,
702 [5] = 0x4924,
703 [6] = 0x4A52,
704 [7] = 0x54AA,
705 [8] = 0x5555,
706 [9] = 0xD555,
707 [10] = 0xD5D5,
708 [11] = 0xDDD5,
709 [12] = 0xDDDD,
710 [13] = 0xDFDD,
711 [14] = 0xDFDF,
712 [15] = 0xFFDF,
713};
714
b497549a
BD		 715static void s3c24xx_serial_set_termios(struct uart_port *port,
716 struct ktermios *termios,
717 struct ktermios *old)
718{
719 struct s3c2410_uartcfg *cfg = s3c24xx_port_to_cfg(port);
720 struct s3c24xx_uart_port *ourport = to_ourport(port);
7cd88831 721 struct clk *clk = ERR_PTR(-EINVAL);
b497549a 722 unsigned long flags;
5f5a7a55 723 unsigned int baud, quot, clk_sel = 0;
b497549a
BD		 724 unsigned int ulcon;
725 unsigned int umcon;
090f848d 726 unsigned int udivslot = 0;
b497549a
BD		 727
728 /*
729 * We don't support modem control lines.
730 */
731 termios->c_cflag &= ~(HUPCL | CMSPAR);
732 termios->c_cflag |= CLOCAL;
733
734 /*
735 * Ask the core to calculate the divisor for us.
736 */
737
738 baud = uart_get_baud_rate(port, termios, old, 0, 115200*8);
5f5a7a55 739 quot = s3c24xx_serial_getclk(ourport, baud, &clk, &clk_sel);
b497549a
BD		 740 if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST)
741 quot = port->custom_divisor;
7cd88831 742 if (IS_ERR(clk))
5f5a7a55 743 return;
b497549a
BD		 744
745 /* check to see if we need to change clock source */
746
5f5a7a55
TA		 747 if (ourport->baudclk != clk) {
748 s3c24xx_serial_setsource(port, clk_sel);
b497549a 749
7cd88831 750 if (!IS_ERR(ourport->baudclk)) {
9484b009 751 clk_disable_unprepare(ourport->baudclk);
7cd88831 752 ourport->baudclk = ERR_PTR(-EINVAL);
b497549a
BD		 753 }
754
9484b009 755 clk_prepare_enable(clk);
b497549a 756
b497549a 757 ourport->baudclk = clk;
30555476 758 ourport->baudclk_rate = clk ? clk_get_rate(clk) : 0;
b497549a
BD		 759 }
760
090f848d
BD		 761 if (ourport->info->has_divslot) {
762 unsigned int div = ourport->baudclk_rate / baud;
763
8b526ae4
JL		 764 if (cfg->has_fracval) {
765 udivslot = (div & 15);
766 dbg("fracval = %04x\n", udivslot);
767 } else {
768 udivslot = udivslot_table[div & 15];
769 dbg("udivslot = %04x (div %d)\n", udivslot, div & 15);
770 }
090f848d
BD		 771 }
772
b497549a
BD		 773 switch (termios->c_cflag & CSIZE) {
774 case CS5:
775 dbg("config: 5bits/char\n");
776 ulcon = S3C2410_LCON_CS5;
777 break;
778 case CS6:
779 dbg("config: 6bits/char\n");
780 ulcon = S3C2410_LCON_CS6;
781 break;
782 case CS7:
783 dbg("config: 7bits/char\n");
784 ulcon = S3C2410_LCON_CS7;
785 break;
786 case CS8:
787 default:
788 dbg("config: 8bits/char\n");
789 ulcon = S3C2410_LCON_CS8;
790 break;
791 }
792
793 /* preserve original lcon IR settings */
794 ulcon |= (cfg->ulcon & S3C2410_LCON_IRM);
795
796 if (termios->c_cflag & CSTOPB)
797 ulcon |= S3C2410_LCON_STOPB;
798
b497549a
BD		 799 if (termios->c_cflag & PARENB) {
800 if (termios->c_cflag & PARODD)
801 ulcon |= S3C2410_LCON_PODD;
802 else
803 ulcon |= S3C2410_LCON_PEVEN;
804 } else {
805 ulcon |= S3C2410_LCON_PNONE;
806 }
807
808 spin_lock_irqsave(&port->lock, flags);
809
090f848d
BD		 810 dbg("setting ulcon to %08x, brddiv to %d, udivslot %08x\n",
811 ulcon, quot, udivslot);
b497549a
BD		 812
813 wr_regl(port, S3C2410_ULCON, ulcon);
814 wr_regl(port, S3C2410_UBRDIV, quot);
2d1e5a48
JMG		 815
816 umcon = rd_regl(port, S3C2410_UMCON);
817 if (termios->c_cflag & CRTSCTS) {
818 umcon |= S3C2410_UMCOM_AFC;
819 /* Disable RTS when RX FIFO contains 63 bytes */
820 umcon &= ~S3C2412_UMCON_AFC_8;
821 } else {
822 umcon &= ~S3C2410_UMCOM_AFC;
823 }
b497549a
BD		 824 wr_regl(port, S3C2410_UMCON, umcon);
825
090f848d
BD		 826 if (ourport->info->has_divslot)
827 wr_regl(port, S3C2443_DIVSLOT, udivslot);
828
b497549a
BD		 829 dbg("uart: ulcon = 0x%08x, ucon = 0x%08x, ufcon = 0x%08x\n",
830 rd_regl(port, S3C2410_ULCON),
831 rd_regl(port, S3C2410_UCON),
832 rd_regl(port, S3C2410_UFCON));
833
834 /*
835 * Update the per-port timeout.
836 */
837 uart_update_timeout(port, termios->c_cflag, baud);
838
839 /*
840 * Which character status flags are we interested in?
841 */
842 port->read_status_mask = S3C2410_UERSTAT_OVERRUN;
843 if (termios->c_iflag & INPCK)
844 port->read_status_mask |= S3C2410_UERSTAT_FRAME | S3C2410_UERSTAT_PARITY;
845
846 /*
847 * Which character status flags should we ignore?
848 */
849 port->ignore_status_mask = 0;
850 if (termios->c_iflag & IGNPAR)
851 port->ignore_status_mask |= S3C2410_UERSTAT_OVERRUN;
852 if (termios->c_iflag & IGNBRK && termios->c_iflag & IGNPAR)
853 port->ignore_status_mask |= S3C2410_UERSTAT_FRAME;
854
855 /*
856 * Ignore all characters if CREAD is not set.
857 */
858 if ((termios->c_cflag & CREAD) == 0)
859 port->ignore_status_mask |= RXSTAT_DUMMY_READ;
860
861 spin_unlock_irqrestore(&port->lock, flags);
862}
863
864static const char *s3c24xx_serial_type(struct uart_port *port)
865{
866 switch (port->type) {
867 case PORT_S3C2410:
868 return "S3C2410";
869 case PORT_S3C2440:
870 return "S3C2440";
871 case PORT_S3C2412:
872 return "S3C2412";
b690ace5
BD		 873 case PORT_S3C6400:
874 return "S3C6400/10";
b497549a
BD		 875 default:
876 return NULL;
877 }
878}
879
880#define MAP_SIZE (0x100)
881
882static void s3c24xx_serial_release_port(struct uart_port *port)
883{
884 release_mem_region(port->mapbase, MAP_SIZE);
885}
886
887static int s3c24xx_serial_request_port(struct uart_port *port)
888{
889 const char *name = s3c24xx_serial_portname(port);
890 return request_mem_region(port->mapbase, MAP_SIZE, name) ? 0 : -EBUSY;
891}
892
893static void s3c24xx_serial_config_port(struct uart_port *port, int flags)
894{
895 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
896
897 if (flags & UART_CONFIG_TYPE &&
898 s3c24xx_serial_request_port(port) == 0)
899 port->type = info->type;
900}
901
902/*
903 * verify the new serial_struct (for TIOCSSERIAL).
904 */
905static int
906s3c24xx_serial_verify_port(struct uart_port *port, struct serial_struct *ser)
907{
908 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
909
910 if (ser->type != PORT_UNKNOWN && ser->type != info->type)
911 return -EINVAL;
912
913 return 0;
914}
915
916
917#ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
918
919static struct console s3c24xx_serial_console;
920
93b5c032
JP		 921static int __init s3c24xx_serial_console_init(void)
922{
923 register_console(&s3c24xx_serial_console);
924 return 0;
925}
926console_initcall(s3c24xx_serial_console_init);
927
b497549a
BD		 928#define S3C24XX_SERIAL_CONSOLE &s3c24xx_serial_console
929#else
930#define S3C24XX_SERIAL_CONSOLE NULL
931#endif
932
84f57d9e 933#if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
93b5c032
JP		 934static int s3c24xx_serial_get_poll_char(struct uart_port *port);
935static void s3c24xx_serial_put_poll_char(struct uart_port *port,
936 unsigned char c);
937#endif
938
b497549a
BD		 939static struct uart_ops s3c24xx_serial_ops = {
940 .pm = s3c24xx_serial_pm,
941 .tx_empty = s3c24xx_serial_tx_empty,
942 .get_mctrl = s3c24xx_serial_get_mctrl,
943 .set_mctrl = s3c24xx_serial_set_mctrl,
944 .stop_tx = s3c24xx_serial_stop_tx,
945 .start_tx = s3c24xx_serial_start_tx,
946 .stop_rx = s3c24xx_serial_stop_rx,
b497549a
BD		 947 .break_ctl = s3c24xx_serial_break_ctl,
948 .startup = s3c24xx_serial_startup,
949 .shutdown = s3c24xx_serial_shutdown,
950 .set_termios = s3c24xx_serial_set_termios,
951 .type = s3c24xx_serial_type,
952 .release_port = s3c24xx_serial_release_port,
953 .request_port = s3c24xx_serial_request_port,
954 .config_port = s3c24xx_serial_config_port,
955 .verify_port = s3c24xx_serial_verify_port,
84f57d9e 956#if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
93b5c032
JP		 957 .poll_get_char = s3c24xx_serial_get_poll_char,
958 .poll_put_char = s3c24xx_serial_put_poll_char,
959#endif
b497549a
BD		 960};
961
b497549a
BD		 962static struct uart_driver s3c24xx_uart_drv = {
963 .owner = THIS_MODULE,
2cf0c58e 964 .driver_name = "s3c2410_serial",
bdd4915a 965 .nr = CONFIG_SERIAL_SAMSUNG_UARTS,
b497549a 966 .cons = S3C24XX_SERIAL_CONSOLE,
2cf0c58e 967 .dev_name = S3C24XX_SERIAL_NAME,
b497549a
BD		 968 .major = S3C24XX_SERIAL_MAJOR,
969 .minor = S3C24XX_SERIAL_MINOR,
970};
971
03d5e77b 972static struct s3c24xx_uart_port s3c24xx_serial_ports[CONFIG_SERIAL_SAMSUNG_UARTS] = {
b497549a
BD		 973 [0] = {
974 .port = {
975 .lock = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[0].port.lock),
976 .iotype = UPIO_MEM,
b497549a
BD		 977 .uartclk = 0,
978 .fifosize = 16,
979 .ops = &s3c24xx_serial_ops,
980 .flags = UPF_BOOT_AUTOCONF,
981 .line = 0,
982 }
983 },
984 [1] = {
985 .port = {
986 .lock = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[1].port.lock),
987 .iotype = UPIO_MEM,
b497549a
BD		 988 .uartclk = 0,
989 .fifosize = 16,
990 .ops = &s3c24xx_serial_ops,
991 .flags = UPF_BOOT_AUTOCONF,
992 .line = 1,
993 }
994 },
03d5e77b 995#if CONFIG_SERIAL_SAMSUNG_UARTS > 2
b497549a
BD		 996
997 [2] = {
998 .port = {
999 .lock = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[2].port.lock),
1000 .iotype = UPIO_MEM,
b497549a
BD		 1001 .uartclk = 0,
1002 .fifosize = 16,
1003 .ops = &s3c24xx_serial_ops,
1004 .flags = UPF_BOOT_AUTOCONF,
1005 .line = 2,
1006 }
03d5e77b
BD		 1007 },
1008#endif
1009#if CONFIG_SERIAL_SAMSUNG_UARTS > 3
1010 [3] = {
1011 .port = {
1012 .lock = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[3].port.lock),
1013 .iotype = UPIO_MEM,
03d5e77b
BD		 1014 .uartclk = 0,
1015 .fifosize = 16,
1016 .ops = &s3c24xx_serial_ops,
1017 .flags = UPF_BOOT_AUTOCONF,
1018 .line = 3,
1019 }
b497549a
BD		 1020 }
1021#endif
1022};
1023
1024/* s3c24xx_serial_resetport
1025 *
0dfb3b41 1026 * reset the fifos and other the settings.
b497549a
BD		 1027*/
1028
0dfb3b41
TA		 1029static void s3c24xx_serial_resetport(struct uart_port *port,
1030 struct s3c2410_uartcfg *cfg)
b497549a
BD		 1031{
1032 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
0dfb3b41
TA		 1033 unsigned long ucon = rd_regl(port, S3C2410_UCON);
1034 unsigned int ucon_mask;
b497549a 1035
0dfb3b41
TA		 1036 ucon_mask = info->clksel_mask;
1037 if (info->type == PORT_S3C2440)
1038 ucon_mask |= S3C2440_UCON0_DIVMASK;
1039
1040 ucon &= ucon_mask;
1041 wr_regl(port, S3C2410_UCON, ucon | cfg->ucon);
1042
1043 /* reset both fifos */
1044 wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
1045 wr_regl(port, S3C2410_UFCON, cfg->ufcon);
1046
1047 /* some delay is required after fifo reset */
1048 udelay(1);
b497549a
BD		 1049}
1050
30555476
BD		 1051
1052#ifdef CONFIG_CPU_FREQ
1053
1054static int s3c24xx_serial_cpufreq_transition(struct notifier_block *nb,
1055 unsigned long val, void *data)
1056{
1057 struct s3c24xx_uart_port *port;
1058 struct uart_port *uport;
1059
1060 port = container_of(nb, struct s3c24xx_uart_port, freq_transition);
1061 uport = &port->port;
1062
1063 /* check to see if port is enabled */
1064
1065 if (port->pm_level != 0)
1066 return 0;
1067
1068 /* try and work out if the baudrate is changing, we can detect
1069 * a change in rate, but we do not have support for detecting
1070 * a disturbance in the clock-rate over the change.
1071 */
1072
25f04ad4 1073 if (IS_ERR(port->baudclk))
30555476
BD		 1074 goto exit;
1075
25f04ad4 1076 if (port->baudclk_rate == clk_get_rate(port->baudclk))
30555476
BD		 1077 goto exit;
1078
1079 if (val == CPUFREQ_PRECHANGE) {
1080 /* we should really shut the port down whilst the
1081 * frequency change is in progress. */
1082
1083 } else if (val == CPUFREQ_POSTCHANGE) {
1084 struct ktermios *termios;
1085 struct tty_struct *tty;
1086
ebd2c8f6 1087 if (uport->state == NULL)
30555476 1088 goto exit;
30555476 1089
ebd2c8f6 1090 tty = uport->state->port.tty;
30555476 1091
7de40c21 1092 if (tty == NULL)
30555476 1093 goto exit;
30555476 1094
adc8d746 1095 termios = &tty->termios;
30555476
BD		 1096
1097 if (termios == NULL) {
d20925e1 1098 dev_warn(uport->dev, "%s: no termios?\n", __func__);
30555476
BD		 1099 goto exit;
1100 }
1101
1102 s3c24xx_serial_set_termios(uport, termios, NULL);
1103 }
1104
1105 exit:
1106 return 0;
1107}
1108
1109static inline int s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port)
1110{
1111 port->freq_transition.notifier_call = s3c24xx_serial_cpufreq_transition;
1112
1113 return cpufreq_register_notifier(&port->freq_transition,
1114 CPUFREQ_TRANSITION_NOTIFIER);
1115}
1116
1117static inline void s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port)
1118{
1119 cpufreq_unregister_notifier(&port->freq_transition,
1120 CPUFREQ_TRANSITION_NOTIFIER);
1121}
1122
1123#else
1124static inline int s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port)
1125{
1126 return 0;
1127}
1128
1129static inline void s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port)
1130{
1131}
1132#endif
1133
b497549a
BD		 1134/* s3c24xx_serial_init_port
1135 *
1136 * initialise a single serial port from the platform device given
1137 */
1138
1139static int s3c24xx_serial_init_port(struct s3c24xx_uart_port *ourport,
b497549a
BD		 1140 struct platform_device *platdev)
1141{
1142 struct uart_port *port = &ourport->port;
da121506 1143 struct s3c2410_uartcfg *cfg = ourport->cfg;
b497549a
BD		 1144 struct resource *res;
1145 int ret;
1146
1147 dbg("s3c24xx_serial_init_port: port=%p, platdev=%p\n", port, platdev);
1148
1149 if (platdev == NULL)
1150 return -ENODEV;
1151
b497549a
BD		 1152 if (port->mapbase != 0)
1153 return 0;
1154
b497549a
BD		 1155 /* setup info for port */
1156 port->dev = &platdev->dev;
b497549a 1157
88bb4ea1
TA		 1158 /* Startup sequence is different for s3c64xx and higher SoC's */
1159 if (s3c24xx_serial_has_interrupt_mask(port))
1160 s3c24xx_serial_ops.startup = s3c64xx_serial_startup;
1161
b497549a
BD		 1162 port->uartclk = 1;
1163
1164 if (cfg->uart_flags & UPF_CONS_FLOW) {
1165 dbg("s3c24xx_serial_init_port: enabling flow control\n");
1166 port->flags |= UPF_CONS_FLOW;
1167 }
1168
1169 /* sort our the physical and virtual addresses for each UART */
1170
1171 res = platform_get_resource(platdev, IORESOURCE_MEM, 0);
1172 if (res == NULL) {
d20925e1 1173 dev_err(port->dev, "failed to find memory resource for uart\n");
b497549a
BD		 1174 return -EINVAL;
1175 }
1176
e4ac92df 1177 dbg("resource %pR)\n", res);
b497549a 1178
41147bfd
TA		 1179 port->membase = devm_ioremap(port->dev, res->start, resource_size(res));
1180 if (!port->membase) {
1181 dev_err(port->dev, "failed to remap controller address\n");
1182 return -EBUSY;
1183 }
1184
b690ace5 1185 port->mapbase = res->start;
b497549a
BD		 1186 ret = platform_get_irq(platdev, 0);
1187 if (ret < 0)
1188 port->irq = 0;
b73c289c 1189 else {
b497549a 1190 port->irq = ret;
b73c289c
BD		 1191 ourport->rx_irq = ret;
1192 ourport->tx_irq = ret + 1;
1193 }
9303ac15 1194
b73c289c
BD		 1195 ret = platform_get_irq(platdev, 1);
1196 if (ret > 0)
1197 ourport->tx_irq = ret;
b497549a
BD		 1198
1199 ourport->clk = clk_get(&platdev->dev, "uart");
60e93575
CK		 1200 if (IS_ERR(ourport->clk)) {
1201 pr_err("%s: Controller clock not found\n",
1202 dev_name(&platdev->dev));
1203 return PTR_ERR(ourport->clk);
1204 }
1205
1206 ret = clk_prepare_enable(ourport->clk);
1207 if (ret) {
1208 pr_err("uart: clock failed to prepare+enable: %d\n", ret);
1209 clk_put(ourport->clk);
1210 return ret;
1211 }
b497549a 1212
88bb4ea1
TA		 1213 /* Keep all interrupts masked and cleared */
1214 if (s3c24xx_serial_has_interrupt_mask(port)) {
1215 wr_regl(port, S3C64XX_UINTM, 0xf);
1216 wr_regl(port, S3C64XX_UINTP, 0xf);
1217 wr_regl(port, S3C64XX_UINTSP, 0xf);
1218 }
1219
1ff5b64d
FE		 1220 dbg("port: map=%pa, mem=%p, irq=%d (%d,%d), clock=%u\n",
1221 &port->mapbase, port->membase, port->irq,
b73c289c 1222 ourport->rx_irq, ourport->tx_irq, port->uartclk);
b497549a
BD		 1223
1224 /* reset the fifos (and setup the uart) */
1225 s3c24xx_serial_resetport(port, cfg);
1226 return 0;
1227}
1228
b497549a
BD		 1229/* Device driver serial port probe */
1230
26c919e1 1231static const struct of_device_id s3c24xx_uart_dt_match[];
b497549a
BD		 1232static int probe_index;
1233
26c919e1
TA		 1234static inline struct s3c24xx_serial_drv_data *s3c24xx_get_driver_data(
1235 struct platform_device *pdev)
1236{
1237#ifdef CONFIG_OF
1238 if (pdev->dev.of_node) {
1239 const struct of_device_id *match;
1240 match = of_match_node(s3c24xx_uart_dt_match, pdev->dev.of_node);
1241 return (struct s3c24xx_serial_drv_data *)match->data;
1242 }
1243#endif
1244 return (struct s3c24xx_serial_drv_data *)
1245 platform_get_device_id(pdev)->driver_data;
1246}
1247
da121506 1248static int s3c24xx_serial_probe(struct platform_device *pdev)
b497549a 1249{
4622eb68 1250 struct device_node *np = pdev->dev.of_node;
b497549a 1251 struct s3c24xx_uart_port *ourport;
13a9f6c6 1252 int index = probe_index;
b497549a
BD		 1253 int ret;
1254
4622eb68
NKC		 1255 if (np) {
1256 ret = of_alias_get_id(np, "serial");
13a9f6c6
TF		 1257 if (ret >= 0)
1258 index = ret;
1259 }
1260
1261 dbg("s3c24xx_serial_probe(%p) %d\n", pdev, index);
b497549a 1262
13a9f6c6 1263 ourport = &s3c24xx_serial_ports[index];
da121506 1264
26c919e1
TA		 1265 ourport->drv_data = s3c24xx_get_driver_data(pdev);
1266 if (!ourport->drv_data) {
1267 dev_err(&pdev->dev, "could not find driver data\n");
1268 return -ENODEV;
1269 }
da121506 1270
7cd88831 1271 ourport->baudclk = ERR_PTR(-EINVAL);
da121506 1272 ourport->info = ourport->drv_data->info;
574de559 1273 ourport->cfg = (dev_get_platdata(&pdev->dev)) ?
d4aab206 1274 dev_get_platdata(&pdev->dev) :
da121506
TA		 1275 ourport->drv_data->def_cfg;
1276
4622eb68
NKC		 1277 if (np)
1278 of_property_read_u32(np,
135f07c3
NKC		 1279 "samsung,uart-fifosize", &ourport->port.fifosize);
1280
1281 if (!ourport->port.fifosize) {
1282 ourport->port.fifosize = (ourport->info->fifosize) ?
1283 ourport->info->fifosize :
1284 ourport->drv_data->fifosize[index];
1285 }
da121506 1286
b497549a
BD		 1287 probe_index++;
1288
1289 dbg("%s: initialising port %p...\n", __func__, ourport);
1290
da121506 1291 ret = s3c24xx_serial_init_port(ourport, pdev);
b497549a 1292 if (ret < 0)
8ad711a9 1293 return ret;
b497549a 1294
6f134c3c
TB		 1295 if (!s3c24xx_uart_drv.state) {
1296 ret = uart_register_driver(&s3c24xx_uart_drv);
1297 if (ret < 0) {
1298 pr_err("Failed to register Samsung UART driver\n");
1299 return ret;
1300 }
1301 }
1302
b497549a
BD		 1303 dbg("%s: adding port\n", __func__);
1304 uart_add_one_port(&s3c24xx_uart_drv, &ourport->port);
da121506 1305 platform_set_drvdata(pdev, &ourport->port);
b497549a 1306
0da3336f
HS		 1307 /*
1308 * Deactivate the clock enabled in s3c24xx_serial_init_port here,
1309 * so that a potential re-enablement through the pm-callback overlaps
1310 * and keeps the clock enabled in this case.
1311 */
1312 clk_disable_unprepare(ourport->clk);
1313
30555476
BD		 1314 ret = s3c24xx_serial_cpufreq_register(ourport);
1315 if (ret < 0)
da121506 1316 dev_err(&pdev->dev, "failed to add cpufreq notifier\n");
30555476 1317
b497549a 1318 return 0;
b497549a
BD		 1319}
1320
ae8d8a14 1321static int s3c24xx_serial_remove(struct platform_device *dev)
b497549a
BD		 1322{
1323 struct uart_port *port = s3c24xx_dev_to_port(&dev->dev);
1324
1325 if (port) {
30555476 1326 s3c24xx_serial_cpufreq_deregister(to_ourport(port));
b497549a
BD		 1327 uart_remove_one_port(&s3c24xx_uart_drv, port);
1328 }
1329
6f134c3c
TB		 1330 uart_unregister_driver(&s3c24xx_uart_drv);
1331
b497549a
BD		 1332 return 0;
1333}
1334
b497549a 1335/* UART power management code */
aef7fe52
MH		 1336#ifdef CONFIG_PM_SLEEP
1337static int s3c24xx_serial_suspend(struct device *dev)
b497549a 1338{
aef7fe52 1339 struct uart_port *port = s3c24xx_dev_to_port(dev);
b497549a
BD		 1340
1341 if (port)
1342 uart_suspend_port(&s3c24xx_uart_drv, port);
1343
1344 return 0;
1345}
1346
aef7fe52 1347static int s3c24xx_serial_resume(struct device *dev)
b497549a 1348{
aef7fe52 1349 struct uart_port *port = s3c24xx_dev_to_port(dev);
b497549a
BD		 1350 struct s3c24xx_uart_port *ourport = to_ourport(port);
1351
1352 if (port) {
9484b009 1353 clk_prepare_enable(ourport->clk);
b497549a 1354 s3c24xx_serial_resetport(port, s3c24xx_port_to_cfg(port));
9484b009 1355 clk_disable_unprepare(ourport->clk);
b497549a
BD		 1356
1357 uart_resume_port(&s3c24xx_uart_drv, port);
1358 }
1359
1360 return 0;
1361}
aef7fe52 1362
d09a7308
MS		 1363static int s3c24xx_serial_resume_noirq(struct device *dev)
1364{
1365 struct uart_port *port = s3c24xx_dev_to_port(dev);
1366
1367 if (port) {
1368 /* restore IRQ mask */
1369 if (s3c24xx_serial_has_interrupt_mask(port)) {
1370 unsigned int uintm = 0xf;
1371 if (tx_enabled(port))
1372 uintm &= ~S3C64XX_UINTM_TXD_MSK;
1373 if (rx_enabled(port))
1374 uintm &= ~S3C64XX_UINTM_RXD_MSK;
1375 wr_regl(port, S3C64XX_UINTM, uintm);
1376 }
1377 }
1378
1379 return 0;
1380}
1381
aef7fe52
MH		 1382static const struct dev_pm_ops s3c24xx_serial_pm_ops = {
1383 .suspend = s3c24xx_serial_suspend,
1384 .resume = s3c24xx_serial_resume,
d09a7308 1385 .resume_noirq = s3c24xx_serial_resume_noirq,
aef7fe52 1386};
b882fc1b
KK		 1387#define SERIAL_SAMSUNG_PM_OPS (&s3c24xx_serial_pm_ops)
1388
aef7fe52 1389#else /* !CONFIG_PM_SLEEP */
b882fc1b
KK		 1390
1391#define SERIAL_SAMSUNG_PM_OPS NULL
aef7fe52 1392#endif /* CONFIG_PM_SLEEP */
b497549a 1393
b497549a
BD		 1394/* Console code */
1395
1396#ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
1397
1398static struct uart_port *cons_uart;
1399
1400static int
1401s3c24xx_serial_console_txrdy(struct uart_port *port, unsigned int ufcon)
1402{
1403 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1404 unsigned long ufstat, utrstat;
1405
1406 if (ufcon & S3C2410_UFCON_FIFOMODE) {
9ddc5b6f 1407 /* fifo mode - check amount of data in fifo registers... */
b497549a
BD		 1408
1409 ufstat = rd_regl(port, S3C2410_UFSTAT);
1410 return (ufstat & info->tx_fifofull) ? 0 : 1;
1411 }
1412
1413 /* in non-fifo mode, we go and use the tx buffer empty */
1414
1415 utrstat = rd_regl(port, S3C2410_UTRSTAT);
1416 return (utrstat & S3C2410_UTRSTAT_TXE) ? 1 : 0;
1417}
1418
38adbc54
MS		 1419static bool
1420s3c24xx_port_configured(unsigned int ucon)
1421{
1422 /* consider the serial port configured if the tx/rx mode set */
1423 return (ucon & 0xf) != 0;
1424}
1425
93b5c032
JP		 1426#ifdef CONFIG_CONSOLE_POLL
1427/*
1428 * Console polling routines for writing and reading from the uart while
1429 * in an interrupt or debug context.
1430 */
1431
1432static int s3c24xx_serial_get_poll_char(struct uart_port *port)
1433{
1434 struct s3c24xx_uart_port *ourport = to_ourport(port);
1435 unsigned int ufstat;
1436
1437 ufstat = rd_regl(port, S3C2410_UFSTAT);
1438 if (s3c24xx_serial_rx_fifocnt(ourport, ufstat) == 0)
1439 return NO_POLL_CHAR;
1440
1441 return rd_regb(port, S3C2410_URXH);
1442}
1443
1444static void s3c24xx_serial_put_poll_char(struct uart_port *port,
1445 unsigned char c)
1446{
bb7f09ba
DA		 1447 unsigned int ufcon = rd_regl(port, S3C2410_UFCON);
1448 unsigned int ucon = rd_regl(port, S3C2410_UCON);
38adbc54
MS		 1449
1450 /* not possible to xmit on unconfigured port */
1451 if (!s3c24xx_port_configured(ucon))
1452 return;
93b5c032
JP		 1453
1454 while (!s3c24xx_serial_console_txrdy(port, ufcon))
1455 cpu_relax();
bb7f09ba 1456 wr_regb(port, S3C2410_UTXH, c);
93b5c032
JP		 1457}
1458
1459#endif /* CONFIG_CONSOLE_POLL */
1460
b497549a
BD		 1461static void
1462s3c24xx_serial_console_putchar(struct uart_port *port, int ch)
1463{
bb7f09ba 1464 unsigned int ufcon = rd_regl(port, S3C2410_UFCON);
38adbc54 1465
b497549a 1466 while (!s3c24xx_serial_console_txrdy(port, ufcon))
f94b0572 1467 cpu_relax();
bb7f09ba 1468 wr_regb(port, S3C2410_UTXH, ch);
b497549a
BD		 1469}
1470
1471static void
1472s3c24xx_serial_console_write(struct console *co, const char *s,
1473 unsigned int count)
1474{
ab88c8dc
DA		 1475 unsigned int ucon = rd_regl(cons_uart, S3C2410_UCON);
1476
1477 /* not possible to xmit on unconfigured port */
1478 if (!s3c24xx_port_configured(ucon))
1479 return;
1480
b497549a
BD		 1481 uart_console_write(cons_uart, s, count, s3c24xx_serial_console_putchar);
1482}
1483
1484static void __init
1485s3c24xx_serial_get_options(struct uart_port *port, int *baud,
1486 int *parity, int *bits)
1487{
b497549a
BD		 1488 struct clk *clk;
1489 unsigned int ulcon;
1490 unsigned int ucon;
1491 unsigned int ubrdiv;
1492 unsigned long rate;
5f5a7a55
TA		 1493 unsigned int clk_sel;
1494 char clk_name[MAX_CLK_NAME_LENGTH];
b497549a
BD		 1495
1496 ulcon = rd_regl(port, S3C2410_ULCON);
1497 ucon = rd_regl(port, S3C2410_UCON);
1498 ubrdiv = rd_regl(port, S3C2410_UBRDIV);
1499
1500 dbg("s3c24xx_serial_get_options: port=%p\n"
1501 "registers: ulcon=%08x, ucon=%08x, ubdriv=%08x\n",
1502 port, ulcon, ucon, ubrdiv);
1503
38adbc54 1504 if (s3c24xx_port_configured(ucon)) {
b497549a
BD		 1505 switch (ulcon & S3C2410_LCON_CSMASK) {
1506 case S3C2410_LCON_CS5:
1507 *bits = 5;
1508 break;
1509 case S3C2410_LCON_CS6:
1510 *bits = 6;
1511 break;
1512 case S3C2410_LCON_CS7:
1513 *bits = 7;
1514 break;
b497549a 1515 case S3C2410_LCON_CS8:
3bcce591 1516 default:
b497549a
BD		 1517 *bits = 8;
1518 break;
1519 }
1520
1521 switch (ulcon & S3C2410_LCON_PMASK) {
1522 case S3C2410_LCON_PEVEN:
1523 *parity = 'e';
1524 break;
1525
1526 case S3C2410_LCON_PODD:
1527 *parity = 'o';
1528 break;
1529
1530 case S3C2410_LCON_PNONE:
1531 default:
1532 *parity = 'n';
1533 }
1534
1535 /* now calculate the baud rate */
1536
5f5a7a55
TA		 1537 clk_sel = s3c24xx_serial_getsource(port);
1538 sprintf(clk_name, "clk_uart_baud%d", clk_sel);
b497549a 1539
5f5a7a55 1540 clk = clk_get(port->dev, clk_name);
7cd88831 1541 if (!IS_ERR(clk))
5f5a7a55 1542 rate = clk_get_rate(clk);
b497549a
BD		 1543 else
1544 rate = 1;
1545
b497549a
BD		 1546 *baud = rate / (16 * (ubrdiv + 1));
1547 dbg("calculated baud %d\n", *baud);
1548 }
1549
1550}
1551
b497549a
BD		 1552static int __init
1553s3c24xx_serial_console_setup(struct console *co, char *options)
1554{
1555 struct uart_port *port;
1556 int baud = 9600;
1557 int bits = 8;
1558 int parity = 'n';
1559 int flow = 'n';
1560
1561 dbg("s3c24xx_serial_console_setup: co=%p (%d), %s\n",
1562 co, co->index, options);
1563
1564 /* is this a valid port */
1565
03d5e77b 1566 if (co->index == -1 || co->index >= CONFIG_SERIAL_SAMSUNG_UARTS)
b497549a
BD		 1567 co->index = 0;
1568
1569 port = &s3c24xx_serial_ports[co->index].port;
1570
1571 /* is the port configured? */
1572
ee430f16
TA		 1573 if (port->mapbase == 0x0)
1574 return -ENODEV;
b497549a
BD		 1575
1576 cons_uart = port;
1577
1578 dbg("s3c24xx_serial_console_setup: port=%p (%d)\n", port, co->index);
1579
1580 /*
1581 * Check whether an invalid uart number has been specified, and
1582 * if so, search for the first available port that does have
1583 * console support.
1584 */
1585 if (options)
1586 uart_parse_options(options, &baud, &parity, &bits, &flow);
1587 else
1588 s3c24xx_serial_get_options(port, &baud, &parity, &bits);
1589
1590 dbg("s3c24xx_serial_console_setup: baud %d\n", baud);
1591
1592 return uart_set_options(port, co, baud, parity, bits, flow);
1593}
1594
b497549a
BD		 1595static struct console s3c24xx_serial_console = {
1596 .name = S3C24XX_SERIAL_NAME,
1597 .device = uart_console_device,
1598 .flags = CON_PRINTBUFFER,
1599 .index = -1,
1600 .write = s3c24xx_serial_console_write,
5822a5df
TA		 1601 .setup = s3c24xx_serial_console_setup,
1602 .data = &s3c24xx_uart_drv,
b497549a 1603};
da121506
TA		 1604#endif /* CONFIG_SERIAL_SAMSUNG_CONSOLE */
1605
1606#ifdef CONFIG_CPU_S3C2410
1607static struct s3c24xx_serial_drv_data s3c2410_serial_drv_data = {
1608 .info = &(struct s3c24xx_uart_info) {
1609 .name = "Samsung S3C2410 UART",
1610 .type = PORT_S3C2410,
1611 .fifosize = 16,
1612 .rx_fifomask = S3C2410_UFSTAT_RXMASK,
1613 .rx_fifoshift = S3C2410_UFSTAT_RXSHIFT,
1614 .rx_fifofull = S3C2410_UFSTAT_RXFULL,
1615 .tx_fifofull = S3C2410_UFSTAT_TXFULL,
1616 .tx_fifomask = S3C2410_UFSTAT_TXMASK,
1617 .tx_fifoshift = S3C2410_UFSTAT_TXSHIFT,
1618 .def_clk_sel = S3C2410_UCON_CLKSEL0,
1619 .num_clks = 2,
1620 .clksel_mask = S3C2410_UCON_CLKMASK,
1621 .clksel_shift = S3C2410_UCON_CLKSHIFT,
1622 },
1623 .def_cfg = &(struct s3c2410_uartcfg) {
1624 .ucon = S3C2410_UCON_DEFAULT,
1625 .ufcon = S3C2410_UFCON_DEFAULT,
1626 },
1627};
1628#define S3C2410_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2410_serial_drv_data)
1629#else
1630#define S3C2410_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1631#endif
b497549a 1632
da121506
TA		 1633#ifdef CONFIG_CPU_S3C2412
1634static struct s3c24xx_serial_drv_data s3c2412_serial_drv_data = {
1635 .info = &(struct s3c24xx_uart_info) {
1636 .name = "Samsung S3C2412 UART",
1637 .type = PORT_S3C2412,
1638 .fifosize = 64,
1639 .has_divslot = 1,
1640 .rx_fifomask = S3C2440_UFSTAT_RXMASK,
1641 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
1642 .rx_fifofull = S3C2440_UFSTAT_RXFULL,
1643 .tx_fifofull = S3C2440_UFSTAT_TXFULL,
1644 .tx_fifomask = S3C2440_UFSTAT_TXMASK,
1645 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
1646 .def_clk_sel = S3C2410_UCON_CLKSEL2,
1647 .num_clks = 4,
1648 .clksel_mask = S3C2412_UCON_CLKMASK,
1649 .clksel_shift = S3C2412_UCON_CLKSHIFT,
1650 },
1651 .def_cfg = &(struct s3c2410_uartcfg) {
1652 .ucon = S3C2410_UCON_DEFAULT,
1653 .ufcon = S3C2410_UFCON_DEFAULT,
1654 },
1655};
1656#define S3C2412_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2412_serial_drv_data)
1657#else
1658#define S3C2412_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1659#endif
b497549a 1660
da121506 1661#if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2416) || \
b26469a8 1662 defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2442)
da121506
TA		 1663static struct s3c24xx_serial_drv_data s3c2440_serial_drv_data = {
1664 .info = &(struct s3c24xx_uart_info) {
1665 .name = "Samsung S3C2440 UART",
1666 .type = PORT_S3C2440,
1667 .fifosize = 64,
1668 .has_divslot = 1,
1669 .rx_fifomask = S3C2440_UFSTAT_RXMASK,
1670 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
1671 .rx_fifofull = S3C2440_UFSTAT_RXFULL,
1672 .tx_fifofull = S3C2440_UFSTAT_TXFULL,
1673 .tx_fifomask = S3C2440_UFSTAT_TXMASK,
1674 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
1675 .def_clk_sel = S3C2410_UCON_CLKSEL2,
1676 .num_clks = 4,
1677 .clksel_mask = S3C2412_UCON_CLKMASK,
1678 .clksel_shift = S3C2412_UCON_CLKSHIFT,
1679 },
1680 .def_cfg = &(struct s3c2410_uartcfg) {
1681 .ucon = S3C2410_UCON_DEFAULT,
1682 .ufcon = S3C2410_UFCON_DEFAULT,
1683 },
1684};
1685#define S3C2440_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2440_serial_drv_data)
1686#else
1687#define S3C2440_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1688#endif
b497549a 1689
953b53a7 1690#if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
da121506
TA		 1691static struct s3c24xx_serial_drv_data s3c6400_serial_drv_data = {
1692 .info = &(struct s3c24xx_uart_info) {
1693 .name = "Samsung S3C6400 UART",
1694 .type = PORT_S3C6400,
1695 .fifosize = 64,
1696 .has_divslot = 1,
1697 .rx_fifomask = S3C2440_UFSTAT_RXMASK,
1698 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
1699 .rx_fifofull = S3C2440_UFSTAT_RXFULL,
1700 .tx_fifofull = S3C2440_UFSTAT_TXFULL,
1701 .tx_fifomask = S3C2440_UFSTAT_TXMASK,
1702 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
1703 .def_clk_sel = S3C2410_UCON_CLKSEL2,
1704 .num_clks = 4,
1705 .clksel_mask = S3C6400_UCON_CLKMASK,
1706 .clksel_shift = S3C6400_UCON_CLKSHIFT,
1707 },
1708 .def_cfg = &(struct s3c2410_uartcfg) {
1709 .ucon = S3C2410_UCON_DEFAULT,
1710 .ufcon = S3C2410_UFCON_DEFAULT,
1711 },
1712};
1713#define S3C6400_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c6400_serial_drv_data)
1714#else
1715#define S3C6400_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1716#endif
b497549a 1717
da121506
TA		 1718#ifdef CONFIG_CPU_S5PV210
1719static struct s3c24xx_serial_drv_data s5pv210_serial_drv_data = {
1720 .info = &(struct s3c24xx_uart_info) {
1721 .name = "Samsung S5PV210 UART",
1722 .type = PORT_S3C6400,
1723 .has_divslot = 1,
1724 .rx_fifomask = S5PV210_UFSTAT_RXMASK,
1725 .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT,
1726 .rx_fifofull = S5PV210_UFSTAT_RXFULL,
1727 .tx_fifofull = S5PV210_UFSTAT_TXFULL,
1728 .tx_fifomask = S5PV210_UFSTAT_TXMASK,
1729 .tx_fifoshift = S5PV210_UFSTAT_TXSHIFT,
1730 .def_clk_sel = S3C2410_UCON_CLKSEL0,
1731 .num_clks = 2,
1732 .clksel_mask = S5PV210_UCON_CLKMASK,
1733 .clksel_shift = S5PV210_UCON_CLKSHIFT,
1734 },
1735 .def_cfg = &(struct s3c2410_uartcfg) {
1736 .ucon = S5PV210_UCON_DEFAULT,
1737 .ufcon = S5PV210_UFCON_DEFAULT,
1738 },
1739 .fifosize = { 256, 64, 16, 16 },
1740};
1741#define S5PV210_SERIAL_DRV_DATA ((kernel_ulong_t)&s5pv210_serial_drv_data)
1742#else
1743#define S5PV210_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1744#endif
b497549a 1745
33f88136 1746#if defined(CONFIG_ARCH_EXYNOS)
da121506
TA		 1747static struct s3c24xx_serial_drv_data exynos4210_serial_drv_data = {
1748 .info = &(struct s3c24xx_uart_info) {
1749 .name = "Samsung Exynos4 UART",
1750 .type = PORT_S3C6400,
1751 .has_divslot = 1,
1752 .rx_fifomask = S5PV210_UFSTAT_RXMASK,
1753 .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT,
1754 .rx_fifofull = S5PV210_UFSTAT_RXFULL,
1755 .tx_fifofull = S5PV210_UFSTAT_TXFULL,
1756 .tx_fifomask = S5PV210_UFSTAT_TXMASK,
1757 .tx_fifoshift = S5PV210_UFSTAT_TXSHIFT,
1758 .def_clk_sel = S3C2410_UCON_CLKSEL0,
1759 .num_clks = 1,
1760 .clksel_mask = 0,
1761 .clksel_shift = 0,
1762 },
1763 .def_cfg = &(struct s3c2410_uartcfg) {
1764 .ucon = S5PV210_UCON_DEFAULT,
1765 .ufcon = S5PV210_UFCON_DEFAULT,
1766 .has_fracval = 1,
1767 },
1768 .fifosize = { 256, 64, 16, 16 },
1769};
1770#define EXYNOS4210_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos4210_serial_drv_data)
1771#else
1772#define EXYNOS4210_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1773#endif
b497549a 1774
da121506
TA		 1775static struct platform_device_id s3c24xx_serial_driver_ids[] = {
1776 {
1777 .name = "s3c2410-uart",
1778 .driver_data = S3C2410_SERIAL_DRV_DATA,
1779 }, {
1780 .name = "s3c2412-uart",
1781 .driver_data = S3C2412_SERIAL_DRV_DATA,
1782 }, {
1783 .name = "s3c2440-uart",
1784 .driver_data = S3C2440_SERIAL_DRV_DATA,
1785 }, {
1786 .name = "s3c6400-uart",
1787 .driver_data = S3C6400_SERIAL_DRV_DATA,
1788 }, {
1789 .name = "s5pv210-uart",
1790 .driver_data = S5PV210_SERIAL_DRV_DATA,
1791 }, {
1792 .name = "exynos4210-uart",
1793 .driver_data = EXYNOS4210_SERIAL_DRV_DATA,
1794 },
1795 { },
1796};
1797MODULE_DEVICE_TABLE(platform, s3c24xx_serial_driver_ids);
1798
26c919e1
TA		 1799#ifdef CONFIG_OF
1800static const struct of_device_id s3c24xx_uart_dt_match[] = {
666ca0b9
HS		 1801 { .compatible = "samsung,s3c2410-uart",
1802 .data = (void *)S3C2410_SERIAL_DRV_DATA },
1803 { .compatible = "samsung,s3c2412-uart",
1804 .data = (void *)S3C2412_SERIAL_DRV_DATA },
1805 { .compatible = "samsung,s3c2440-uart",
1806 .data = (void *)S3C2440_SERIAL_DRV_DATA },
1807 { .compatible = "samsung,s3c6400-uart",
1808 .data = (void *)S3C6400_SERIAL_DRV_DATA },
1809 { .compatible = "samsung,s5pv210-uart",
1810 .data = (void *)S5PV210_SERIAL_DRV_DATA },
26c919e1 1811 { .compatible = "samsung,exynos4210-uart",
a169a888 1812 .data = (void *)EXYNOS4210_SERIAL_DRV_DATA },
26c919e1
TA		 1813 {},
1814};
1815MODULE_DEVICE_TABLE(of, s3c24xx_uart_dt_match);
26c919e1
TA		 1816#endif
1817
da121506
TA		 1818static struct platform_driver samsung_serial_driver = {
1819 .probe = s3c24xx_serial_probe,
2d47b716 1820 .remove = s3c24xx_serial_remove,
da121506
TA		 1821 .id_table = s3c24xx_serial_driver_ids,
1822 .driver = {
1823 .name = "samsung-uart",
1824 .owner = THIS_MODULE,
1825 .pm = SERIAL_SAMSUNG_PM_OPS,
905f4ba2 1826 .of_match_table = of_match_ptr(s3c24xx_uart_dt_match),
da121506
TA		 1827 },
1828};
b497549a 1829
6f134c3c 1830module_platform_driver(samsung_serial_driver);
b497549a 1831
da121506 1832MODULE_ALIAS("platform:samsung-uart");
b497549a
BD		 1833MODULE_DESCRIPTION("Samsung SoC Serial port driver");
1834MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
1835MODULE_LICENSE("GPL v2");
Linux 6.x block layer and io_uring tree(s)