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serial: samsung: merge probe() function from all SoC specific extensions
[linux-block.git] / drivers / tty / serial / samsung.c
CommitLineData
99edb3d1 1/*
b497549a
BD		 2 * Driver core for Samsung SoC onboard UARTs.
3 *
ccae941e 4 * Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics
b497549a
BD		 5 * http://armlinux.simtec.co.uk/
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12/* Hote on 2410 error handling
13 *
14 * The s3c2410 manual has a love/hate affair with the contents of the
15 * UERSTAT register in the UART blocks, and keeps marking some of the
16 * error bits as reserved. Having checked with the s3c2410x01,
17 * it copes with BREAKs properly, so I am happy to ignore the RESERVED
18 * feature from the latter versions of the manual.
19 *
20 * If it becomes aparrent that latter versions of the 2410 remove these
21 * bits, then action will have to be taken to differentiate the versions
22 * and change the policy on BREAK
23 *
24 * BJD, 04-Nov-2004
25*/
26
27#if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
28#define SUPPORT_SYSRQ
29#endif
30
31#include <linux/module.h>
32#include <linux/ioport.h>
33#include <linux/io.h>
34#include <linux/platform_device.h>
35#include <linux/init.h>
36#include <linux/sysrq.h>
37#include <linux/console.h>
38#include <linux/tty.h>
39#include <linux/tty_flip.h>
40#include <linux/serial_core.h>
41#include <linux/serial.h>
42#include <linux/delay.h>
43#include <linux/clk.h>
30555476 44#include <linux/cpufreq.h>
b497549a
BD		 45
46#include <asm/irq.h>
47
a09e64fb 48#include <mach/hardware.h>
b690ace5 49#include <mach/map.h>
b497549a 50
a2b7ba9c 51#include <plat/regs-serial.h>
5f5a7a55 52#include <plat/clock.h>
b497549a
BD		 53
54#include "samsung.h"
55
56/* UART name and device definitions */
57
58#define S3C24XX_SERIAL_NAME "ttySAC"
59#define S3C24XX_SERIAL_MAJOR 204
60#define S3C24XX_SERIAL_MINOR 64
61
b497549a
BD		 62/* macros to change one thing to another */
63
64#define tx_enabled(port) ((port)->unused[0])
65#define rx_enabled(port) ((port)->unused[1])
66
25985edc 67/* flag to ignore all characters coming in */
b497549a
BD		 68#define RXSTAT_DUMMY_READ (0x10000000)
69
70static inline struct s3c24xx_uart_port *to_ourport(struct uart_port *port)
71{
72 return container_of(port, struct s3c24xx_uart_port, port);
73}
74
75/* translate a port to the device name */
76
77static inline const char *s3c24xx_serial_portname(struct uart_port *port)
78{
79 return to_platform_device(port->dev)->name;
80}
81
82static int s3c24xx_serial_txempty_nofifo(struct uart_port *port)
83{
84 return (rd_regl(port, S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE);
85}
86
88bb4ea1
TA		 87/*
88 * s3c64xx and later SoC's include the interrupt mask and status registers in
89 * the controller itself, unlike the s3c24xx SoC's which have these registers
90 * in the interrupt controller. Check if the port type is s3c64xx or higher.
91 */
92static int s3c24xx_serial_has_interrupt_mask(struct uart_port *port)
93{
94 return to_ourport(port)->info->type == PORT_S3C6400;
95}
96
b497549a
BD		 97static void s3c24xx_serial_rx_enable(struct uart_port *port)
98{
99 unsigned long flags;
100 unsigned int ucon, ufcon;
101 int count = 10000;
102
103 spin_lock_irqsave(&port->lock, flags);
104
105 while (--count && !s3c24xx_serial_txempty_nofifo(port))
106 udelay(100);
107
108 ufcon = rd_regl(port, S3C2410_UFCON);
109 ufcon |= S3C2410_UFCON_RESETRX;
110 wr_regl(port, S3C2410_UFCON, ufcon);
111
112 ucon = rd_regl(port, S3C2410_UCON);
113 ucon |= S3C2410_UCON_RXIRQMODE;
114 wr_regl(port, S3C2410_UCON, ucon);
115
116 rx_enabled(port) = 1;
117 spin_unlock_irqrestore(&port->lock, flags);
118}
119
120static void s3c24xx_serial_rx_disable(struct uart_port *port)
121{
122 unsigned long flags;
123 unsigned int ucon;
124
125 spin_lock_irqsave(&port->lock, flags);
126
127 ucon = rd_regl(port, S3C2410_UCON);
128 ucon &= ~S3C2410_UCON_RXIRQMODE;
129 wr_regl(port, S3C2410_UCON, ucon);
130
131 rx_enabled(port) = 0;
132 spin_unlock_irqrestore(&port->lock, flags);
133}
134
135static void s3c24xx_serial_stop_tx(struct uart_port *port)
136{
b73c289c
BD		 137 struct s3c24xx_uart_port *ourport = to_ourport(port);
138
b497549a 139 if (tx_enabled(port)) {
88bb4ea1
TA		 140 if (s3c24xx_serial_has_interrupt_mask(port))
141 __set_bit(S3C64XX_UINTM_TXD,
142 portaddrl(port, S3C64XX_UINTM));
143 else
144 disable_irq_nosync(ourport->tx_irq);
b497549a
BD		 145 tx_enabled(port) = 0;
146 if (port->flags & UPF_CONS_FLOW)
147 s3c24xx_serial_rx_enable(port);
148 }
149}
150
151static void s3c24xx_serial_start_tx(struct uart_port *port)
152{
b73c289c
BD		 153 struct s3c24xx_uart_port *ourport = to_ourport(port);
154
b497549a
BD		 155 if (!tx_enabled(port)) {
156 if (port->flags & UPF_CONS_FLOW)
157 s3c24xx_serial_rx_disable(port);
158
88bb4ea1
TA		 159 if (s3c24xx_serial_has_interrupt_mask(port))
160 __clear_bit(S3C64XX_UINTM_TXD,
161 portaddrl(port, S3C64XX_UINTM));
162 else
163 enable_irq(ourport->tx_irq);
b497549a
BD		 164 tx_enabled(port) = 1;
165 }
166}
167
b497549a
BD		 168static void s3c24xx_serial_stop_rx(struct uart_port *port)
169{
b73c289c
BD		 170 struct s3c24xx_uart_port *ourport = to_ourport(port);
171
b497549a
BD		 172 if (rx_enabled(port)) {
173 dbg("s3c24xx_serial_stop_rx: port=%p\n", port);
88bb4ea1
TA		 174 if (s3c24xx_serial_has_interrupt_mask(port))
175 __set_bit(S3C64XX_UINTM_RXD,
176 portaddrl(port, S3C64XX_UINTM));
177 else
178 disable_irq_nosync(ourport->rx_irq);
b497549a
BD		 179 rx_enabled(port) = 0;
180 }
181}
182
183static void s3c24xx_serial_enable_ms(struct uart_port *port)
184{
185}
186
187static inline struct s3c24xx_uart_info *s3c24xx_port_to_info(struct uart_port *port)
188{
189 return to_ourport(port)->info;
190}
191
192static inline struct s3c2410_uartcfg *s3c24xx_port_to_cfg(struct uart_port *port)
193{
4d84e970
TA		 194 struct s3c24xx_uart_port *ourport;
195
b497549a
BD		 196 if (port->dev == NULL)
197 return NULL;
198
4d84e970
TA		 199 ourport = container_of(port, struct s3c24xx_uart_port, port);
200 return ourport->cfg;
b497549a
BD		 201}
202
203static int s3c24xx_serial_rx_fifocnt(struct s3c24xx_uart_port *ourport,
204 unsigned long ufstat)
205{
206 struct s3c24xx_uart_info *info = ourport->info;
207
208 if (ufstat & info->rx_fifofull)
da121506 209 return ourport->port.fifosize;
b497549a
BD		 210
211 return (ufstat & info->rx_fifomask) >> info->rx_fifoshift;
212}
213
214
215/* ? - where has parity gone?? */
216#define S3C2410_UERSTAT_PARITY (0x1000)
217
218static irqreturn_t
219s3c24xx_serial_rx_chars(int irq, void *dev_id)
220{
221 struct s3c24xx_uart_port *ourport = dev_id;
222 struct uart_port *port = &ourport->port;
ebd2c8f6 223 struct tty_struct *tty = port->state->port.tty;
b497549a
BD		 224 unsigned int ufcon, ch, flag, ufstat, uerstat;
225 int max_count = 64;
226
227 while (max_count-- > 0) {
228 ufcon = rd_regl(port, S3C2410_UFCON);
229 ufstat = rd_regl(port, S3C2410_UFSTAT);
230
231 if (s3c24xx_serial_rx_fifocnt(ourport, ufstat) == 0)
232 break;
233
234 uerstat = rd_regl(port, S3C2410_UERSTAT);
235 ch = rd_regb(port, S3C2410_URXH);
236
237 if (port->flags & UPF_CONS_FLOW) {
238 int txe = s3c24xx_serial_txempty_nofifo(port);
239
240 if (rx_enabled(port)) {
241 if (!txe) {
242 rx_enabled(port) = 0;
243 continue;
244 }
245 } else {
246 if (txe) {
247 ufcon |= S3C2410_UFCON_RESETRX;
248 wr_regl(port, S3C2410_UFCON, ufcon);
249 rx_enabled(port) = 1;
250 goto out;
251 }
252 continue;
253 }
254 }
255
256 /* insert the character into the buffer */
257
258 flag = TTY_NORMAL;
259 port->icount.rx++;
260
261 if (unlikely(uerstat & S3C2410_UERSTAT_ANY)) {
262 dbg("rxerr: port ch=0x%02x, rxs=0x%08x\n",
263 ch, uerstat);
264
265 /* check for break */
266 if (uerstat & S3C2410_UERSTAT_BREAK) {
267 dbg("break!\n");
268 port->icount.brk++;
269 if (uart_handle_break(port))
270 goto ignore_char;
271 }
272
273 if (uerstat & S3C2410_UERSTAT_FRAME)
274 port->icount.frame++;
275 if (uerstat & S3C2410_UERSTAT_OVERRUN)
276 port->icount.overrun++;
277
278 uerstat &= port->read_status_mask;
279
280 if (uerstat & S3C2410_UERSTAT_BREAK)
281 flag = TTY_BREAK;
282 else if (uerstat & S3C2410_UERSTAT_PARITY)
283 flag = TTY_PARITY;
284 else if (uerstat & (S3C2410_UERSTAT_FRAME |
285 S3C2410_UERSTAT_OVERRUN))
286 flag = TTY_FRAME;
287 }
288
289 if (uart_handle_sysrq_char(port, ch))
290 goto ignore_char;
291
292 uart_insert_char(port, uerstat, S3C2410_UERSTAT_OVERRUN,
293 ch, flag);
294
295 ignore_char:
296 continue;
297 }
298 tty_flip_buffer_push(tty);
299
300 out:
301 return IRQ_HANDLED;
302}
303
304static irqreturn_t s3c24xx_serial_tx_chars(int irq, void *id)
305{
306 struct s3c24xx_uart_port *ourport = id;
307 struct uart_port *port = &ourport->port;
ebd2c8f6 308 struct circ_buf *xmit = &port->state->xmit;
b497549a
BD		 309 int count = 256;
310
311 if (port->x_char) {
312 wr_regb(port, S3C2410_UTXH, port->x_char);
313 port->icount.tx++;
314 port->x_char = 0;
315 goto out;
316 }
317
25985edc 318 /* if there isn't anything more to transmit, or the uart is now
b497549a
BD		 319 * stopped, disable the uart and exit
320 */
321
322 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
323 s3c24xx_serial_stop_tx(port);
324 goto out;
325 }
326
327 /* try and drain the buffer... */
328
329 while (!uart_circ_empty(xmit) && count-- > 0) {
330 if (rd_regl(port, S3C2410_UFSTAT) & ourport->info->tx_fifofull)
331 break;
332
333 wr_regb(port, S3C2410_UTXH, xmit->buf[xmit->tail]);
334 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
335 port->icount.tx++;
336 }
337
338 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
339 uart_write_wakeup(port);
340
341 if (uart_circ_empty(xmit))
342 s3c24xx_serial_stop_tx(port);
343
344 out:
345 return IRQ_HANDLED;
346}
347
88bb4ea1
TA		 348/* interrupt handler for s3c64xx and later SoC's.*/
349static irqreturn_t s3c64xx_serial_handle_irq(int irq, void *id)
350{
351 struct s3c24xx_uart_port *ourport = id;
352 struct uart_port *port = &ourport->port;
353 unsigned int pend = rd_regl(port, S3C64XX_UINTP);
354 unsigned long flags;
355 irqreturn_t ret = IRQ_HANDLED;
356
357 spin_lock_irqsave(&port->lock, flags);
358 if (pend & S3C64XX_UINTM_RXD_MSK) {
359 ret = s3c24xx_serial_rx_chars(irq, id);
360 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_RXD_MSK);
361 }
362 if (pend & S3C64XX_UINTM_TXD_MSK) {
363 ret = s3c24xx_serial_tx_chars(irq, id);
364 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_TXD_MSK);
365 }
366 spin_unlock_irqrestore(&port->lock, flags);
367 return ret;
368}
369
b497549a
BD		 370static unsigned int s3c24xx_serial_tx_empty(struct uart_port *port)
371{
372 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
373 unsigned long ufstat = rd_regl(port, S3C2410_UFSTAT);
374 unsigned long ufcon = rd_regl(port, S3C2410_UFCON);
375
376 if (ufcon & S3C2410_UFCON_FIFOMODE) {
377 if ((ufstat & info->tx_fifomask) != 0 ||
378 (ufstat & info->tx_fifofull))
379 return 0;
380
381 return 1;
382 }
383
384 return s3c24xx_serial_txempty_nofifo(port);
385}
386
387/* no modem control lines */
388static unsigned int s3c24xx_serial_get_mctrl(struct uart_port *port)
389{
390 unsigned int umstat = rd_regb(port, S3C2410_UMSTAT);
391
392 if (umstat & S3C2410_UMSTAT_CTS)
393 return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
394 else
395 return TIOCM_CAR | TIOCM_DSR;
396}
397
398static void s3c24xx_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
399{
400 /* todo - possibly remove AFC and do manual CTS */
401}
402
403static void s3c24xx_serial_break_ctl(struct uart_port *port, int break_state)
404{
405 unsigned long flags;
406 unsigned int ucon;
407
408 spin_lock_irqsave(&port->lock, flags);
409
410 ucon = rd_regl(port, S3C2410_UCON);
411
412 if (break_state)
413 ucon |= S3C2410_UCON_SBREAK;
414 else
415 ucon &= ~S3C2410_UCON_SBREAK;
416
417 wr_regl(port, S3C2410_UCON, ucon);
418
419 spin_unlock_irqrestore(&port->lock, flags);
420}
421
422static void s3c24xx_serial_shutdown(struct uart_port *port)
423{
424 struct s3c24xx_uart_port *ourport = to_ourport(port);
425
426 if (ourport->tx_claimed) {
88bb4ea1
TA		 427 if (!s3c24xx_serial_has_interrupt_mask(port))
428 free_irq(ourport->tx_irq, ourport);
b497549a
BD		 429 tx_enabled(port) = 0;
430 ourport->tx_claimed = 0;
431 }
432
433 if (ourport->rx_claimed) {
88bb4ea1
TA		 434 if (!s3c24xx_serial_has_interrupt_mask(port))
435 free_irq(ourport->rx_irq, ourport);
b497549a
BD		 436 ourport->rx_claimed = 0;
437 rx_enabled(port) = 0;
438 }
b497549a 439
88bb4ea1
TA		 440 /* Clear pending interrupts and mask all interrupts */
441 if (s3c24xx_serial_has_interrupt_mask(port)) {
442 wr_regl(port, S3C64XX_UINTP, 0xf);
443 wr_regl(port, S3C64XX_UINTM, 0xf);
444 }
445}
b497549a
BD		 446
447static int s3c24xx_serial_startup(struct uart_port *port)
448{
449 struct s3c24xx_uart_port *ourport = to_ourport(port);
450 int ret;
451
452 dbg("s3c24xx_serial_startup: port=%p (%08lx,%p)\n",
453 port->mapbase, port->membase);
454
455 rx_enabled(port) = 1;
456
b73c289c 457 ret = request_irq(ourport->rx_irq, s3c24xx_serial_rx_chars, 0,
b497549a
BD		 458 s3c24xx_serial_portname(port), ourport);
459
460 if (ret != 0) {
b73c289c 461 printk(KERN_ERR "cannot get irq %d\n", ourport->rx_irq);
b497549a
BD		 462 return ret;
463 }
464
465 ourport->rx_claimed = 1;
466
467 dbg("requesting tx irq...\n");
468
469 tx_enabled(port) = 1;
470
b73c289c 471 ret = request_irq(ourport->tx_irq, s3c24xx_serial_tx_chars, 0,
b497549a
BD		 472 s3c24xx_serial_portname(port), ourport);
473
474 if (ret) {
b73c289c 475 printk(KERN_ERR "cannot get irq %d\n", ourport->tx_irq);
b497549a
BD		 476 goto err;
477 }
478
479 ourport->tx_claimed = 1;
480
481 dbg("s3c24xx_serial_startup ok\n");
482
483 /* the port reset code should have done the correct
484 * register setup for the port controls */
485
486 return ret;
487
488 err:
489 s3c24xx_serial_shutdown(port);
490 return ret;
491}
492
88bb4ea1
TA		 493static int s3c64xx_serial_startup(struct uart_port *port)
494{
495 struct s3c24xx_uart_port *ourport = to_ourport(port);
496 int ret;
497
498 dbg("s3c64xx_serial_startup: port=%p (%08lx,%p)\n",
499 port->mapbase, port->membase);
500
501 ret = request_irq(port->irq, s3c64xx_serial_handle_irq, IRQF_SHARED,
502 s3c24xx_serial_portname(port), ourport);
503 if (ret) {
504 printk(KERN_ERR "cannot get irq %d\n", port->irq);
505 return ret;
506 }
507
508 /* For compatibility with s3c24xx Soc's */
509 rx_enabled(port) = 1;
510 ourport->rx_claimed = 1;
511 tx_enabled(port) = 0;
512 ourport->tx_claimed = 1;
513
514 /* Enable Rx Interrupt */
515 __clear_bit(S3C64XX_UINTM_RXD, portaddrl(port, S3C64XX_UINTM));
516 dbg("s3c64xx_serial_startup ok\n");
517 return ret;
518}
519
b497549a
BD		 520/* power power management control */
521
522static void s3c24xx_serial_pm(struct uart_port *port, unsigned int level,
523 unsigned int old)
524{
525 struct s3c24xx_uart_port *ourport = to_ourport(port);
526
30555476
BD		 527 ourport->pm_level = level;
528
b497549a
BD		 529 switch (level) {
530 case 3:
531 if (!IS_ERR(ourport->baudclk) && ourport->baudclk != NULL)
532 clk_disable(ourport->baudclk);
533
534 clk_disable(ourport->clk);
535 break;
536
537 case 0:
538 clk_enable(ourport->clk);
539
540 if (!IS_ERR(ourport->baudclk) && ourport->baudclk != NULL)
541 clk_enable(ourport->baudclk);
542
543 break;
544 default:
545 printk(KERN_ERR "s3c24xx_serial: unknown pm %d\n", level);
546 }
547}
548
549/* baud rate calculation
550 *
551 * The UARTs on the S3C2410/S3C2440 can take their clocks from a number
552 * of different sources, including the peripheral clock ("pclk") and an
553 * external clock ("uclk"). The S3C2440 also adds the core clock ("fclk")
554 * with a programmable extra divisor.
555 *
556 * The following code goes through the clock sources, and calculates the
557 * baud clocks (and the resultant actual baud rates) and then tries to
558 * pick the closest one and select that.
559 *
560*/
561
5f5a7a55 562#define MAX_CLK_NAME_LENGTH 15
b497549a 563
5f5a7a55 564static inline int s3c24xx_serial_getsource(struct uart_port *port)
b497549a
BD		 565{
566 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
5f5a7a55 567 unsigned int ucon;
b497549a 568
5f5a7a55
TA		 569 if (info->num_clks == 1)
570 return 0;
b497549a 571
5f5a7a55
TA		 572 ucon = rd_regl(port, S3C2410_UCON);
573 ucon &= info->clksel_mask;
574 return ucon >> info->clksel_shift;
b497549a
BD		 575}
576
5f5a7a55
TA		 577static void s3c24xx_serial_setsource(struct uart_port *port,
578 unsigned int clk_sel)
b497549a 579{
5f5a7a55
TA		 580 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
581 unsigned int ucon;
b497549a 582
5f5a7a55
TA		 583 if (info->num_clks == 1)
584 return;
090f848d 585
5f5a7a55
TA		 586 ucon = rd_regl(port, S3C2410_UCON);
587 if ((ucon & info->clksel_mask) >> info->clksel_shift == clk_sel)
588 return;
b497549a 589
5f5a7a55
TA		 590 ucon &= ~info->clksel_mask;
591 ucon |= clk_sel << info->clksel_shift;
592 wr_regl(port, S3C2410_UCON, ucon);
b497549a
BD		 593}
594
5f5a7a55
TA		 595static unsigned int s3c24xx_serial_getclk(struct s3c24xx_uart_port *ourport,
596 unsigned int req_baud, struct clk **best_clk,
597 unsigned int *clk_num)
b497549a 598{
5f5a7a55
TA		 599 struct s3c24xx_uart_info *info = ourport->info;
600 struct clk *clk;
601 unsigned long rate;
602 unsigned int cnt, baud, quot, clk_sel, best_quot = 0;
603 char clkname[MAX_CLK_NAME_LENGTH];
604 int calc_deviation, deviation = (1 << 30) - 1;
605
606 *best_clk = NULL;
607 clk_sel = (ourport->cfg->clk_sel) ? ourport->cfg->clk_sel :
608 ourport->info->def_clk_sel;
609 for (cnt = 0; cnt < info->num_clks; cnt++) {
610 if (!(clk_sel & (1 << cnt)))
611 continue;
612
613 sprintf(clkname, "clk_uart_baud%d", cnt);
614 clk = clk_get(ourport->port.dev, clkname);
615 if (IS_ERR_OR_NULL(clk))
616 continue;
617
618 rate = clk_get_rate(clk);
619 if (!rate)
620 continue;
621
622 if (ourport->info->has_divslot) {
623 unsigned long div = rate / req_baud;
624
625 /* The UDIVSLOT register on the newer UARTs allows us to
626 * get a divisor adjustment of 1/16th on the baud clock.
627 *
628 * We don't keep the UDIVSLOT value (the 16ths we
629 * calculated by not multiplying the baud by 16) as it
630 * is easy enough to recalculate.
631 */
632
633 quot = div / 16;
634 baud = rate / div;
635 } else {
636 quot = (rate + (8 * req_baud)) / (16 * req_baud);
637 baud = rate / (quot * 16);
b497549a 638 }
5f5a7a55 639 quot--;
b497549a 640
5f5a7a55
TA		 641 calc_deviation = req_baud - baud;
642 if (calc_deviation < 0)
643 calc_deviation = -calc_deviation;
b497549a 644
5f5a7a55
TA		 645 if (calc_deviation < deviation) {
646 *best_clk = clk;
647 best_quot = quot;
648 *clk_num = cnt;
649 deviation = calc_deviation;
b497549a
BD		 650 }
651 }
652
5f5a7a55 653 return best_quot;
b497549a
BD		 654}
655
090f848d
BD		 656/* udivslot_table[]
657 *
658 * This table takes the fractional value of the baud divisor and gives
659 * the recommended setting for the UDIVSLOT register.
660 */
661static u16 udivslot_table[16] = {
662 [0] = 0x0000,
663 [1] = 0x0080,
664 [2] = 0x0808,
665 [3] = 0x0888,
666 [4] = 0x2222,
667 [5] = 0x4924,
668 [6] = 0x4A52,
669 [7] = 0x54AA,
670 [8] = 0x5555,
671 [9] = 0xD555,
672 [10] = 0xD5D5,
673 [11] = 0xDDD5,
674 [12] = 0xDDDD,
675 [13] = 0xDFDD,
676 [14] = 0xDFDF,
677 [15] = 0xFFDF,
678};
679
b497549a
BD		 680static void s3c24xx_serial_set_termios(struct uart_port *port,
681 struct ktermios *termios,
682 struct ktermios *old)
683{
684 struct s3c2410_uartcfg *cfg = s3c24xx_port_to_cfg(port);
685 struct s3c24xx_uart_port *ourport = to_ourport(port);
b497549a
BD		 686 struct clk *clk = NULL;
687 unsigned long flags;
5f5a7a55 688 unsigned int baud, quot, clk_sel = 0;
b497549a
BD		 689 unsigned int ulcon;
690 unsigned int umcon;
090f848d 691 unsigned int udivslot = 0;
b497549a
BD		 692
693 /*
694 * We don't support modem control lines.
695 */
696 termios->c_cflag &= ~(HUPCL | CMSPAR);
697 termios->c_cflag |= CLOCAL;
698
699 /*
700 * Ask the core to calculate the divisor for us.
701 */
702
703 baud = uart_get_baud_rate(port, termios, old, 0, 115200*8);
5f5a7a55 704 quot = s3c24xx_serial_getclk(ourport, baud, &clk, &clk_sel);
b497549a
BD		 705 if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST)
706 quot = port->custom_divisor;
5f5a7a55
TA		 707 if (!clk)
708 return;
b497549a
BD		 709
710 /* check to see if we need to change clock source */
711
5f5a7a55
TA		 712 if (ourport->baudclk != clk) {
713 s3c24xx_serial_setsource(port, clk_sel);
b497549a
BD		 714
715 if (ourport->baudclk != NULL && !IS_ERR(ourport->baudclk)) {
716 clk_disable(ourport->baudclk);
717 ourport->baudclk = NULL;
718 }
719
720 clk_enable(clk);
721
b497549a 722 ourport->baudclk = clk;
30555476 723 ourport->baudclk_rate = clk ? clk_get_rate(clk) : 0;
b497549a
BD		 724 }
725
090f848d
BD		 726 if (ourport->info->has_divslot) {
727 unsigned int div = ourport->baudclk_rate / baud;
728
8b526ae4
JL		 729 if (cfg->has_fracval) {
730 udivslot = (div & 15);
731 dbg("fracval = %04x\n", udivslot);
732 } else {
733 udivslot = udivslot_table[div & 15];
734 dbg("udivslot = %04x (div %d)\n", udivslot, div & 15);
735 }
090f848d
BD		 736 }
737
b497549a
BD		 738 switch (termios->c_cflag & CSIZE) {
739 case CS5:
740 dbg("config: 5bits/char\n");
741 ulcon = S3C2410_LCON_CS5;
742 break;
743 case CS6:
744 dbg("config: 6bits/char\n");
745 ulcon = S3C2410_LCON_CS6;
746 break;
747 case CS7:
748 dbg("config: 7bits/char\n");
749 ulcon = S3C2410_LCON_CS7;
750 break;
751 case CS8:
752 default:
753 dbg("config: 8bits/char\n");
754 ulcon = S3C2410_LCON_CS8;
755 break;
756 }
757
758 /* preserve original lcon IR settings */
759 ulcon |= (cfg->ulcon & S3C2410_LCON_IRM);
760
761 if (termios->c_cflag & CSTOPB)
762 ulcon |= S3C2410_LCON_STOPB;
763
764 umcon = (termios->c_cflag & CRTSCTS) ? S3C2410_UMCOM_AFC : 0;
765
766 if (termios->c_cflag & PARENB) {
767 if (termios->c_cflag & PARODD)
768 ulcon |= S3C2410_LCON_PODD;
769 else
770 ulcon |= S3C2410_LCON_PEVEN;
771 } else {
772 ulcon |= S3C2410_LCON_PNONE;
773 }
774
775 spin_lock_irqsave(&port->lock, flags);
776
090f848d
BD		 777 dbg("setting ulcon to %08x, brddiv to %d, udivslot %08x\n",
778 ulcon, quot, udivslot);
b497549a
BD		 779
780 wr_regl(port, S3C2410_ULCON, ulcon);
781 wr_regl(port, S3C2410_UBRDIV, quot);
782 wr_regl(port, S3C2410_UMCON, umcon);
783
090f848d
BD		 784 if (ourport->info->has_divslot)
785 wr_regl(port, S3C2443_DIVSLOT, udivslot);
786
b497549a
BD		 787 dbg("uart: ulcon = 0x%08x, ucon = 0x%08x, ufcon = 0x%08x\n",
788 rd_regl(port, S3C2410_ULCON),
789 rd_regl(port, S3C2410_UCON),
790 rd_regl(port, S3C2410_UFCON));
791
792 /*
793 * Update the per-port timeout.
794 */
795 uart_update_timeout(port, termios->c_cflag, baud);
796
797 /*
798 * Which character status flags are we interested in?
799 */
800 port->read_status_mask = S3C2410_UERSTAT_OVERRUN;
801 if (termios->c_iflag & INPCK)
802 port->read_status_mask |= S3C2410_UERSTAT_FRAME | S3C2410_UERSTAT_PARITY;
803
804 /*
805 * Which character status flags should we ignore?
806 */
807 port->ignore_status_mask = 0;
808 if (termios->c_iflag & IGNPAR)
809 port->ignore_status_mask |= S3C2410_UERSTAT_OVERRUN;
810 if (termios->c_iflag & IGNBRK && termios->c_iflag & IGNPAR)
811 port->ignore_status_mask |= S3C2410_UERSTAT_FRAME;
812
813 /*
814 * Ignore all characters if CREAD is not set.
815 */
816 if ((termios->c_cflag & CREAD) == 0)
817 port->ignore_status_mask |= RXSTAT_DUMMY_READ;
818
819 spin_unlock_irqrestore(&port->lock, flags);
820}
821
822static const char *s3c24xx_serial_type(struct uart_port *port)
823{
824 switch (port->type) {
825 case PORT_S3C2410:
826 return "S3C2410";
827 case PORT_S3C2440:
828 return "S3C2440";
829 case PORT_S3C2412:
830 return "S3C2412";
b690ace5
BD		 831 case PORT_S3C6400:
832 return "S3C6400/10";
b497549a
BD		 833 default:
834 return NULL;
835 }
836}
837
838#define MAP_SIZE (0x100)
839
840static void s3c24xx_serial_release_port(struct uart_port *port)
841{
842 release_mem_region(port->mapbase, MAP_SIZE);
843}
844
845static int s3c24xx_serial_request_port(struct uart_port *port)
846{
847 const char *name = s3c24xx_serial_portname(port);
848 return request_mem_region(port->mapbase, MAP_SIZE, name) ? 0 : -EBUSY;
849}
850
851static void s3c24xx_serial_config_port(struct uart_port *port, int flags)
852{
853 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
854
855 if (flags & UART_CONFIG_TYPE &&
856 s3c24xx_serial_request_port(port) == 0)
857 port->type = info->type;
858}
859
860/*
861 * verify the new serial_struct (for TIOCSSERIAL).
862 */
863static int
864s3c24xx_serial_verify_port(struct uart_port *port, struct serial_struct *ser)
865{
866 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
867
868 if (ser->type != PORT_UNKNOWN && ser->type != info->type)
869 return -EINVAL;
870
871 return 0;
872}
873
874
875#ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
876
877static struct console s3c24xx_serial_console;
878
879#define S3C24XX_SERIAL_CONSOLE &s3c24xx_serial_console
880#else
881#define S3C24XX_SERIAL_CONSOLE NULL
882#endif
883
884static struct uart_ops s3c24xx_serial_ops = {
885 .pm = s3c24xx_serial_pm,
886 .tx_empty = s3c24xx_serial_tx_empty,
887 .get_mctrl = s3c24xx_serial_get_mctrl,
888 .set_mctrl = s3c24xx_serial_set_mctrl,
889 .stop_tx = s3c24xx_serial_stop_tx,
890 .start_tx = s3c24xx_serial_start_tx,
891 .stop_rx = s3c24xx_serial_stop_rx,
892 .enable_ms = s3c24xx_serial_enable_ms,
893 .break_ctl = s3c24xx_serial_break_ctl,
894 .startup = s3c24xx_serial_startup,
895 .shutdown = s3c24xx_serial_shutdown,
896 .set_termios = s3c24xx_serial_set_termios,
897 .type = s3c24xx_serial_type,
898 .release_port = s3c24xx_serial_release_port,
899 .request_port = s3c24xx_serial_request_port,
900 .config_port = s3c24xx_serial_config_port,
901 .verify_port = s3c24xx_serial_verify_port,
902};
903
b497549a
BD		 904static struct uart_driver s3c24xx_uart_drv = {
905 .owner = THIS_MODULE,
2cf0c58e 906 .driver_name = "s3c2410_serial",
bdd4915a 907 .nr = CONFIG_SERIAL_SAMSUNG_UARTS,
b497549a 908 .cons = S3C24XX_SERIAL_CONSOLE,
2cf0c58e 909 .dev_name = S3C24XX_SERIAL_NAME,
b497549a
BD		 910 .major = S3C24XX_SERIAL_MAJOR,
911 .minor = S3C24XX_SERIAL_MINOR,
912};
913
03d5e77b 914static struct s3c24xx_uart_port s3c24xx_serial_ports[CONFIG_SERIAL_SAMSUNG_UARTS] = {
b497549a
BD		 915 [0] = {
916 .port = {
917 .lock = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[0].port.lock),
918 .iotype = UPIO_MEM,
b497549a
BD		 919 .uartclk = 0,
920 .fifosize = 16,
921 .ops = &s3c24xx_serial_ops,
922 .flags = UPF_BOOT_AUTOCONF,
923 .line = 0,
924 }
925 },
926 [1] = {
927 .port = {
928 .lock = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[1].port.lock),
929 .iotype = UPIO_MEM,
b497549a
BD		 930 .uartclk = 0,
931 .fifosize = 16,
932 .ops = &s3c24xx_serial_ops,
933 .flags = UPF_BOOT_AUTOCONF,
934 .line = 1,
935 }
936 },
03d5e77b 937#if CONFIG_SERIAL_SAMSUNG_UARTS > 2
b497549a
BD		 938
939 [2] = {
940 .port = {
941 .lock = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[2].port.lock),
942 .iotype = UPIO_MEM,
b497549a
BD		 943 .uartclk = 0,
944 .fifosize = 16,
945 .ops = &s3c24xx_serial_ops,
946 .flags = UPF_BOOT_AUTOCONF,
947 .line = 2,
948 }
03d5e77b
BD		 949 },
950#endif
951#if CONFIG_SERIAL_SAMSUNG_UARTS > 3
952 [3] = {
953 .port = {
954 .lock = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[3].port.lock),
955 .iotype = UPIO_MEM,
03d5e77b
BD		 956 .uartclk = 0,
957 .fifosize = 16,
958 .ops = &s3c24xx_serial_ops,
959 .flags = UPF_BOOT_AUTOCONF,
960 .line = 3,
961 }
b497549a
BD		 962 }
963#endif
964};
965
966/* s3c24xx_serial_resetport
967 *
0dfb3b41 968 * reset the fifos and other the settings.
b497549a
BD		 969*/
970
0dfb3b41
TA		 971static void s3c24xx_serial_resetport(struct uart_port *port,
972 struct s3c2410_uartcfg *cfg)
b497549a
BD		 973{
974 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
0dfb3b41
TA		 975 unsigned long ucon = rd_regl(port, S3C2410_UCON);
976 unsigned int ucon_mask;
b497549a 977
0dfb3b41
TA		 978 ucon_mask = info->clksel_mask;
979 if (info->type == PORT_S3C2440)
980 ucon_mask |= S3C2440_UCON0_DIVMASK;
981
982 ucon &= ucon_mask;
983 wr_regl(port, S3C2410_UCON, ucon | cfg->ucon);
984
985 /* reset both fifos */
986 wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
987 wr_regl(port, S3C2410_UFCON, cfg->ufcon);
988
989 /* some delay is required after fifo reset */
990 udelay(1);
b497549a
BD		 991}
992
30555476
BD		 993
994#ifdef CONFIG_CPU_FREQ
995
996static int s3c24xx_serial_cpufreq_transition(struct notifier_block *nb,
997 unsigned long val, void *data)
998{
999 struct s3c24xx_uart_port *port;
1000 struct uart_port *uport;
1001
1002 port = container_of(nb, struct s3c24xx_uart_port, freq_transition);
1003 uport = &port->port;
1004
1005 /* check to see if port is enabled */
1006
1007 if (port->pm_level != 0)
1008 return 0;
1009
1010 /* try and work out if the baudrate is changing, we can detect
1011 * a change in rate, but we do not have support for detecting
1012 * a disturbance in the clock-rate over the change.
1013 */
1014
1015 if (IS_ERR(port->clk))
1016 goto exit;
1017
1018 if (port->baudclk_rate == clk_get_rate(port->clk))
1019 goto exit;
1020
1021 if (val == CPUFREQ_PRECHANGE) {
1022 /* we should really shut the port down whilst the
1023 * frequency change is in progress. */
1024
1025 } else if (val == CPUFREQ_POSTCHANGE) {
1026 struct ktermios *termios;
1027 struct tty_struct *tty;
1028
ebd2c8f6 1029 if (uport->state == NULL)
30555476 1030 goto exit;
30555476 1031
ebd2c8f6 1032 tty = uport->state->port.tty;
30555476 1033
7de40c21 1034 if (tty == NULL)
30555476 1035 goto exit;
30555476
BD		 1036
1037 termios = tty->termios;
1038
1039 if (termios == NULL) {
1040 printk(KERN_WARNING "%s: no termios?\n", __func__);
1041 goto exit;
1042 }
1043
1044 s3c24xx_serial_set_termios(uport, termios, NULL);
1045 }
1046
1047 exit:
1048 return 0;
1049}
1050
1051static inline int s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port)
1052{
1053 port->freq_transition.notifier_call = s3c24xx_serial_cpufreq_transition;
1054
1055 return cpufreq_register_notifier(&port->freq_transition,
1056 CPUFREQ_TRANSITION_NOTIFIER);
1057}
1058
1059static inline void s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port)
1060{
1061 cpufreq_unregister_notifier(&port->freq_transition,
1062 CPUFREQ_TRANSITION_NOTIFIER);
1063}
1064
1065#else
1066static inline int s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port)
1067{
1068 return 0;
1069}
1070
1071static inline void s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port)
1072{
1073}
1074#endif
1075
b497549a
BD		 1076/* s3c24xx_serial_init_port
1077 *
1078 * initialise a single serial port from the platform device given
1079 */
1080
1081static int s3c24xx_serial_init_port(struct s3c24xx_uart_port *ourport,
b497549a
BD		 1082 struct platform_device *platdev)
1083{
1084 struct uart_port *port = &ourport->port;
da121506 1085 struct s3c2410_uartcfg *cfg = ourport->cfg;
b497549a
BD		 1086 struct resource *res;
1087 int ret;
1088
1089 dbg("s3c24xx_serial_init_port: port=%p, platdev=%p\n", port, platdev);
1090
1091 if (platdev == NULL)
1092 return -ENODEV;
1093
b497549a
BD		 1094 if (port->mapbase != 0)
1095 return 0;
1096
b497549a
BD		 1097 /* setup info for port */
1098 port->dev = &platdev->dev;
b497549a 1099
88bb4ea1
TA		 1100 /* Startup sequence is different for s3c64xx and higher SoC's */
1101 if (s3c24xx_serial_has_interrupt_mask(port))
1102 s3c24xx_serial_ops.startup = s3c64xx_serial_startup;
1103
b497549a
BD		 1104 port->uartclk = 1;
1105
1106 if (cfg->uart_flags & UPF_CONS_FLOW) {
1107 dbg("s3c24xx_serial_init_port: enabling flow control\n");
1108 port->flags |= UPF_CONS_FLOW;
1109 }
1110
1111 /* sort our the physical and virtual addresses for each UART */
1112
1113 res = platform_get_resource(platdev, IORESOURCE_MEM, 0);
1114 if (res == NULL) {
1115 printk(KERN_ERR "failed to find memory resource for uart\n");
1116 return -EINVAL;
1117 }
1118
1119 dbg("resource %p (%lx..%lx)\n", res, res->start, res->end);
1120
b690ace5 1121 port->mapbase = res->start;
2555e663 1122 port->membase = S3C_VA_UART + (res->start & 0xfffff);
b497549a
BD		 1123 ret = platform_get_irq(platdev, 0);
1124 if (ret < 0)
1125 port->irq = 0;
b73c289c 1126 else {
b497549a 1127 port->irq = ret;
b73c289c
BD		 1128 ourport->rx_irq = ret;
1129 ourport->tx_irq = ret + 1;
1130 }
1131
1132 ret = platform_get_irq(platdev, 1);
1133 if (ret > 0)
1134 ourport->tx_irq = ret;
b497549a
BD		 1135
1136 ourport->clk = clk_get(&platdev->dev, "uart");
1137
88bb4ea1
TA		 1138 /* Keep all interrupts masked and cleared */
1139 if (s3c24xx_serial_has_interrupt_mask(port)) {
1140 wr_regl(port, S3C64XX_UINTM, 0xf);
1141 wr_regl(port, S3C64XX_UINTP, 0xf);
1142 wr_regl(port, S3C64XX_UINTSP, 0xf);
1143 }
1144
b73c289c
BD		 1145 dbg("port: map=%08x, mem=%08x, irq=%d (%d,%d), clock=%ld\n",
1146 port->mapbase, port->membase, port->irq,
1147 ourport->rx_irq, ourport->tx_irq, port->uartclk);
b497549a
BD		 1148
1149 /* reset the fifos (and setup the uart) */
1150 s3c24xx_serial_resetport(port, cfg);
1151 return 0;
1152}
1153
1154static ssize_t s3c24xx_serial_show_clksrc(struct device *dev,
1155 struct device_attribute *attr,
1156 char *buf)
1157{
1158 struct uart_port *port = s3c24xx_dev_to_port(dev);
1159 struct s3c24xx_uart_port *ourport = to_ourport(port);
1160
5f5a7a55 1161 return snprintf(buf, PAGE_SIZE, "* %s\n", ourport->baudclk->name);
b497549a
BD		 1162}
1163
1164static DEVICE_ATTR(clock_source, S_IRUGO, s3c24xx_serial_show_clksrc, NULL);
1165
1166/* Device driver serial port probe */
1167
1168static int probe_index;
1169
da121506 1170static int s3c24xx_serial_probe(struct platform_device *pdev)
b497549a
BD		 1171{
1172 struct s3c24xx_uart_port *ourport;
1173 int ret;
1174
da121506 1175 dbg("s3c24xx_serial_probe(%p) %d\n", pdev, probe_index);
b497549a
BD		 1176
1177 ourport = &s3c24xx_serial_ports[probe_index];
da121506
TA		 1178
1179 ourport->drv_data = (struct s3c24xx_serial_drv_data *)
1180 platform_get_device_id(pdev)->driver_data;
1181
1182 ourport->info = ourport->drv_data->info;
1183 ourport->cfg = (pdev->dev.platform_data) ?
1184 (struct s3c2410_uartcfg *)pdev->dev.platform_data :
1185 ourport->drv_data->def_cfg;
1186
1187 ourport->port.fifosize = (ourport->info->fifosize) ?
1188 ourport->info->fifosize :
1189 ourport->drv_data->fifosize[probe_index];
1190
b497549a
BD		 1191 probe_index++;
1192
1193 dbg("%s: initialising port %p...\n", __func__, ourport);
1194
da121506 1195 ret = s3c24xx_serial_init_port(ourport, pdev);
b497549a
BD		 1196 if (ret < 0)
1197 goto probe_err;
1198
1199 dbg("%s: adding port\n", __func__);
1200 uart_add_one_port(&s3c24xx_uart_drv, &ourport->port);
da121506 1201 platform_set_drvdata(pdev, &ourport->port);
b497549a 1202
da121506 1203 ret = device_create_file(&pdev->dev, &dev_attr_clock_source);
b497549a 1204 if (ret < 0)
da121506 1205 dev_err(&pdev->dev, "failed to add clock source attr.\n");
b497549a 1206
30555476
BD		 1207 ret = s3c24xx_serial_cpufreq_register(ourport);
1208 if (ret < 0)
da121506 1209 dev_err(&pdev->dev, "failed to add cpufreq notifier\n");
30555476 1210
b497549a
BD		 1211 return 0;
1212
1213 probe_err:
1214 return ret;
1215}
1216
da121506 1217static int __devexit s3c24xx_serial_remove(struct platform_device *dev)
b497549a
BD		 1218{
1219 struct uart_port *port = s3c24xx_dev_to_port(&dev->dev);
1220
1221 if (port) {
30555476 1222 s3c24xx_serial_cpufreq_deregister(to_ourport(port));
b497549a
BD		 1223 device_remove_file(&dev->dev, &dev_attr_clock_source);
1224 uart_remove_one_port(&s3c24xx_uart_drv, port);
1225 }
1226
1227 return 0;
1228}
1229
b497549a 1230/* UART power management code */
aef7fe52
MH		 1231#ifdef CONFIG_PM_SLEEP
1232static int s3c24xx_serial_suspend(struct device *dev)
b497549a 1233{
aef7fe52 1234 struct uart_port *port = s3c24xx_dev_to_port(dev);
b497549a
BD		 1235
1236 if (port)
1237 uart_suspend_port(&s3c24xx_uart_drv, port);
1238
1239 return 0;
1240}
1241
aef7fe52 1242static int s3c24xx_serial_resume(struct device *dev)
b497549a 1243{
aef7fe52 1244 struct uart_port *port = s3c24xx_dev_to_port(dev);
b497549a
BD		 1245 struct s3c24xx_uart_port *ourport = to_ourport(port);
1246
1247 if (port) {
1248 clk_enable(ourport->clk);
1249 s3c24xx_serial_resetport(port, s3c24xx_port_to_cfg(port));
1250 clk_disable(ourport->clk);
1251
1252 uart_resume_port(&s3c24xx_uart_drv, port);
1253 }
1254
1255 return 0;
1256}
aef7fe52
MH		 1257
1258static const struct dev_pm_ops s3c24xx_serial_pm_ops = {
1259 .suspend = s3c24xx_serial_suspend,
1260 .resume = s3c24xx_serial_resume,
1261};
b882fc1b
KK		 1262#define SERIAL_SAMSUNG_PM_OPS (&s3c24xx_serial_pm_ops)
1263
aef7fe52 1264#else /* !CONFIG_PM_SLEEP */
b882fc1b
KK		 1265
1266#define SERIAL_SAMSUNG_PM_OPS NULL
aef7fe52 1267#endif /* CONFIG_PM_SLEEP */
b497549a 1268
b497549a
BD		 1269/* Console code */
1270
1271#ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
1272
1273static struct uart_port *cons_uart;
1274
1275static int
1276s3c24xx_serial_console_txrdy(struct uart_port *port, unsigned int ufcon)
1277{
1278 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1279 unsigned long ufstat, utrstat;
1280
1281 if (ufcon & S3C2410_UFCON_FIFOMODE) {
9ddc5b6f 1282 /* fifo mode - check amount of data in fifo registers... */
b497549a
BD		 1283
1284 ufstat = rd_regl(port, S3C2410_UFSTAT);
1285 return (ufstat & info->tx_fifofull) ? 0 : 1;
1286 }
1287
1288 /* in non-fifo mode, we go and use the tx buffer empty */
1289
1290 utrstat = rd_regl(port, S3C2410_UTRSTAT);
1291 return (utrstat & S3C2410_UTRSTAT_TXE) ? 1 : 0;
1292}
1293
1294static void
1295s3c24xx_serial_console_putchar(struct uart_port *port, int ch)
1296{
1297 unsigned int ufcon = rd_regl(cons_uart, S3C2410_UFCON);
1298 while (!s3c24xx_serial_console_txrdy(port, ufcon))
1299 barrier();
1300 wr_regb(cons_uart, S3C2410_UTXH, ch);
1301}
1302
1303static void
1304s3c24xx_serial_console_write(struct console *co, const char *s,
1305 unsigned int count)
1306{
1307 uart_console_write(cons_uart, s, count, s3c24xx_serial_console_putchar);
1308}
1309
1310static void __init
1311s3c24xx_serial_get_options(struct uart_port *port, int *baud,
1312 int *parity, int *bits)
1313{
b497549a
BD		 1314 struct clk *clk;
1315 unsigned int ulcon;
1316 unsigned int ucon;
1317 unsigned int ubrdiv;
1318 unsigned long rate;
5f5a7a55
TA		 1319 unsigned int clk_sel;
1320 char clk_name[MAX_CLK_NAME_LENGTH];
b497549a
BD		 1321
1322 ulcon = rd_regl(port, S3C2410_ULCON);
1323 ucon = rd_regl(port, S3C2410_UCON);
1324 ubrdiv = rd_regl(port, S3C2410_UBRDIV);
1325
1326 dbg("s3c24xx_serial_get_options: port=%p\n"
1327 "registers: ulcon=%08x, ucon=%08x, ubdriv=%08x\n",
1328 port, ulcon, ucon, ubrdiv);
1329
1330 if ((ucon & 0xf) != 0) {
1331 /* consider the serial port configured if the tx/rx mode set */
1332
1333 switch (ulcon & S3C2410_LCON_CSMASK) {
1334 case S3C2410_LCON_CS5:
1335 *bits = 5;
1336 break;
1337 case S3C2410_LCON_CS6:
1338 *bits = 6;
1339 break;
1340 case S3C2410_LCON_CS7:
1341 *bits = 7;
1342 break;
1343 default:
1344 case S3C2410_LCON_CS8:
1345 *bits = 8;
1346 break;
1347 }
1348
1349 switch (ulcon & S3C2410_LCON_PMASK) {
1350 case S3C2410_LCON_PEVEN:
1351 *parity = 'e';
1352 break;
1353
1354 case S3C2410_LCON_PODD:
1355 *parity = 'o';
1356 break;
1357
1358 case S3C2410_LCON_PNONE:
1359 default:
1360 *parity = 'n';
1361 }
1362
1363 /* now calculate the baud rate */
1364
5f5a7a55
TA		 1365 clk_sel = s3c24xx_serial_getsource(port);
1366 sprintf(clk_name, "clk_uart_baud%d", clk_sel);
b497549a 1367
5f5a7a55 1368 clk = clk_get(port->dev, clk_name);
b497549a 1369 if (!IS_ERR(clk) && clk != NULL)
5f5a7a55 1370 rate = clk_get_rate(clk);
b497549a
BD		 1371 else
1372 rate = 1;
1373
b497549a
BD		 1374 *baud = rate / (16 * (ubrdiv + 1));
1375 dbg("calculated baud %d\n", *baud);
1376 }
1377
1378}
1379
b497549a
BD		 1380static int __init
1381s3c24xx_serial_console_setup(struct console *co, char *options)
1382{
1383 struct uart_port *port;
1384 int baud = 9600;
1385 int bits = 8;
1386 int parity = 'n';
1387 int flow = 'n';
1388
1389 dbg("s3c24xx_serial_console_setup: co=%p (%d), %s\n",
1390 co, co->index, options);
1391
1392 /* is this a valid port */
1393
03d5e77b 1394 if (co->index == -1 || co->index >= CONFIG_SERIAL_SAMSUNG_UARTS)
b497549a
BD		 1395 co->index = 0;
1396
1397 port = &s3c24xx_serial_ports[co->index].port;
1398
1399 /* is the port configured? */
1400
ee430f16
TA		 1401 if (port->mapbase == 0x0)
1402 return -ENODEV;
b497549a
BD		 1403
1404 cons_uart = port;
1405
1406 dbg("s3c24xx_serial_console_setup: port=%p (%d)\n", port, co->index);
1407
1408 /*
1409 * Check whether an invalid uart number has been specified, and
1410 * if so, search for the first available port that does have
1411 * console support.
1412 */
1413 if (options)
1414 uart_parse_options(options, &baud, &parity, &bits, &flow);
1415 else
1416 s3c24xx_serial_get_options(port, &baud, &parity, &bits);
1417
1418 dbg("s3c24xx_serial_console_setup: baud %d\n", baud);
1419
1420 return uart_set_options(port, co, baud, parity, bits, flow);
1421}
1422
b497549a
BD		 1423static struct console s3c24xx_serial_console = {
1424 .name = S3C24XX_SERIAL_NAME,
1425 .device = uart_console_device,
1426 .flags = CON_PRINTBUFFER,
1427 .index = -1,
1428 .write = s3c24xx_serial_console_write,
5822a5df
TA		 1429 .setup = s3c24xx_serial_console_setup,
1430 .data = &s3c24xx_uart_drv,
b497549a 1431};
da121506
TA		 1432#endif /* CONFIG_SERIAL_SAMSUNG_CONSOLE */
1433
1434#ifdef CONFIG_CPU_S3C2410
1435static struct s3c24xx_serial_drv_data s3c2410_serial_drv_data = {
1436 .info = &(struct s3c24xx_uart_info) {
1437 .name = "Samsung S3C2410 UART",
1438 .type = PORT_S3C2410,
1439 .fifosize = 16,
1440 .rx_fifomask = S3C2410_UFSTAT_RXMASK,
1441 .rx_fifoshift = S3C2410_UFSTAT_RXSHIFT,
1442 .rx_fifofull = S3C2410_UFSTAT_RXFULL,
1443 .tx_fifofull = S3C2410_UFSTAT_TXFULL,
1444 .tx_fifomask = S3C2410_UFSTAT_TXMASK,
1445 .tx_fifoshift = S3C2410_UFSTAT_TXSHIFT,
1446 .def_clk_sel = S3C2410_UCON_CLKSEL0,
1447 .num_clks = 2,
1448 .clksel_mask = S3C2410_UCON_CLKMASK,
1449 .clksel_shift = S3C2410_UCON_CLKSHIFT,
1450 },
1451 .def_cfg = &(struct s3c2410_uartcfg) {
1452 .ucon = S3C2410_UCON_DEFAULT,
1453 .ufcon = S3C2410_UFCON_DEFAULT,
1454 },
1455};
1456#define S3C2410_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2410_serial_drv_data)
1457#else
1458#define S3C2410_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1459#endif
b497549a 1460
da121506
TA		 1461#ifdef CONFIG_CPU_S3C2412
1462static struct s3c24xx_serial_drv_data s3c2412_serial_drv_data = {
1463 .info = &(struct s3c24xx_uart_info) {
1464 .name = "Samsung S3C2412 UART",
1465 .type = PORT_S3C2412,
1466 .fifosize = 64,
1467 .has_divslot = 1,
1468 .rx_fifomask = S3C2440_UFSTAT_RXMASK,
1469 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
1470 .rx_fifofull = S3C2440_UFSTAT_RXFULL,
1471 .tx_fifofull = S3C2440_UFSTAT_TXFULL,
1472 .tx_fifomask = S3C2440_UFSTAT_TXMASK,
1473 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
1474 .def_clk_sel = S3C2410_UCON_CLKSEL2,
1475 .num_clks = 4,
1476 .clksel_mask = S3C2412_UCON_CLKMASK,
1477 .clksel_shift = S3C2412_UCON_CLKSHIFT,
1478 },
1479 .def_cfg = &(struct s3c2410_uartcfg) {
1480 .ucon = S3C2410_UCON_DEFAULT,
1481 .ufcon = S3C2410_UFCON_DEFAULT,
1482 },
1483};
1484#define S3C2412_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2412_serial_drv_data)
1485#else
1486#define S3C2412_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1487#endif
b497549a 1488
da121506
TA		 1489#if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2416) || \
1490 defined(CONFIG_CPU_S3C2443)
1491static struct s3c24xx_serial_drv_data s3c2440_serial_drv_data = {
1492 .info = &(struct s3c24xx_uart_info) {
1493 .name = "Samsung S3C2440 UART",
1494 .type = PORT_S3C2440,
1495 .fifosize = 64,
1496 .has_divslot = 1,
1497 .rx_fifomask = S3C2440_UFSTAT_RXMASK,
1498 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
1499 .rx_fifofull = S3C2440_UFSTAT_RXFULL,
1500 .tx_fifofull = S3C2440_UFSTAT_TXFULL,
1501 .tx_fifomask = S3C2440_UFSTAT_TXMASK,
1502 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
1503 .def_clk_sel = S3C2410_UCON_CLKSEL2,
1504 .num_clks = 4,
1505 .clksel_mask = S3C2412_UCON_CLKMASK,
1506 .clksel_shift = S3C2412_UCON_CLKSHIFT,
1507 },
1508 .def_cfg = &(struct s3c2410_uartcfg) {
1509 .ucon = S3C2410_UCON_DEFAULT,
1510 .ufcon = S3C2410_UFCON_DEFAULT,
1511 },
1512};
1513#define S3C2440_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2440_serial_drv_data)
1514#else
1515#define S3C2440_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1516#endif
b497549a 1517
da121506
TA		 1518#if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410) || \
1519 defined(CONFIG_CPU_S5P6440) || defined(CONFIG_CPU_S5P6450) || \
1520 defined(CONFIG_CPU_S5PC100)
1521static struct s3c24xx_serial_drv_data s3c6400_serial_drv_data = {
1522 .info = &(struct s3c24xx_uart_info) {
1523 .name = "Samsung S3C6400 UART",
1524 .type = PORT_S3C6400,
1525 .fifosize = 64,
1526 .has_divslot = 1,
1527 .rx_fifomask = S3C2440_UFSTAT_RXMASK,
1528 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
1529 .rx_fifofull = S3C2440_UFSTAT_RXFULL,
1530 .tx_fifofull = S3C2440_UFSTAT_TXFULL,
1531 .tx_fifomask = S3C2440_UFSTAT_TXMASK,
1532 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
1533 .def_clk_sel = S3C2410_UCON_CLKSEL2,
1534 .num_clks = 4,
1535 .clksel_mask = S3C6400_UCON_CLKMASK,
1536 .clksel_shift = S3C6400_UCON_CLKSHIFT,
1537 },
1538 .def_cfg = &(struct s3c2410_uartcfg) {
1539 .ucon = S3C2410_UCON_DEFAULT,
1540 .ufcon = S3C2410_UFCON_DEFAULT,
1541 },
1542};
1543#define S3C6400_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c6400_serial_drv_data)
1544#else
1545#define S3C6400_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1546#endif
b497549a 1547
da121506
TA		 1548#ifdef CONFIG_CPU_S5PV210
1549static struct s3c24xx_serial_drv_data s5pv210_serial_drv_data = {
1550 .info = &(struct s3c24xx_uart_info) {
1551 .name = "Samsung S5PV210 UART",
1552 .type = PORT_S3C6400,
1553 .has_divslot = 1,
1554 .rx_fifomask = S5PV210_UFSTAT_RXMASK,
1555 .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT,
1556 .rx_fifofull = S5PV210_UFSTAT_RXFULL,
1557 .tx_fifofull = S5PV210_UFSTAT_TXFULL,
1558 .tx_fifomask = S5PV210_UFSTAT_TXMASK,
1559 .tx_fifoshift = S5PV210_UFSTAT_TXSHIFT,
1560 .def_clk_sel = S3C2410_UCON_CLKSEL0,
1561 .num_clks = 2,
1562 .clksel_mask = S5PV210_UCON_CLKMASK,
1563 .clksel_shift = S5PV210_UCON_CLKSHIFT,
1564 },
1565 .def_cfg = &(struct s3c2410_uartcfg) {
1566 .ucon = S5PV210_UCON_DEFAULT,
1567 .ufcon = S5PV210_UFCON_DEFAULT,
1568 },
1569 .fifosize = { 256, 64, 16, 16 },
1570};
1571#define S5PV210_SERIAL_DRV_DATA ((kernel_ulong_t)&s5pv210_serial_drv_data)
1572#else
1573#define S5PV210_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1574#endif
b497549a 1575
da121506
TA		 1576#ifdef CONFIG_CPU_EXYNOS4210
1577static struct s3c24xx_serial_drv_data exynos4210_serial_drv_data = {
1578 .info = &(struct s3c24xx_uart_info) {
1579 .name = "Samsung Exynos4 UART",
1580 .type = PORT_S3C6400,
1581 .has_divslot = 1,
1582 .rx_fifomask = S5PV210_UFSTAT_RXMASK,
1583 .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT,
1584 .rx_fifofull = S5PV210_UFSTAT_RXFULL,
1585 .tx_fifofull = S5PV210_UFSTAT_TXFULL,
1586 .tx_fifomask = S5PV210_UFSTAT_TXMASK,
1587 .tx_fifoshift = S5PV210_UFSTAT_TXSHIFT,
1588 .def_clk_sel = S3C2410_UCON_CLKSEL0,
1589 .num_clks = 1,
1590 .clksel_mask = 0,
1591 .clksel_shift = 0,
1592 },
1593 .def_cfg = &(struct s3c2410_uartcfg) {
1594 .ucon = S5PV210_UCON_DEFAULT,
1595 .ufcon = S5PV210_UFCON_DEFAULT,
1596 .has_fracval = 1,
1597 },
1598 .fifosize = { 256, 64, 16, 16 },
1599};
1600#define EXYNOS4210_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos4210_serial_drv_data)
1601#else
1602#define EXYNOS4210_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1603#endif
b497549a 1604
da121506
TA		 1605static struct platform_device_id s3c24xx_serial_driver_ids[] = {
1606 {
1607 .name = "s3c2410-uart",
1608 .driver_data = S3C2410_SERIAL_DRV_DATA,
1609 }, {
1610 .name = "s3c2412-uart",
1611 .driver_data = S3C2412_SERIAL_DRV_DATA,
1612 }, {
1613 .name = "s3c2440-uart",
1614 .driver_data = S3C2440_SERIAL_DRV_DATA,
1615 }, {
1616 .name = "s3c6400-uart",
1617 .driver_data = S3C6400_SERIAL_DRV_DATA,
1618 }, {
1619 .name = "s5pv210-uart",
1620 .driver_data = S5PV210_SERIAL_DRV_DATA,
1621 }, {
1622 .name = "exynos4210-uart",
1623 .driver_data = EXYNOS4210_SERIAL_DRV_DATA,
1624 },
1625 { },
1626};
1627MODULE_DEVICE_TABLE(platform, s3c24xx_serial_driver_ids);
1628
1629static struct platform_driver samsung_serial_driver = {
1630 .probe = s3c24xx_serial_probe,
1631 .remove = __devexit_p(s3c24xx_serial_remove),
1632 .id_table = s3c24xx_serial_driver_ids,
1633 .driver = {
1634 .name = "samsung-uart",
1635 .owner = THIS_MODULE,
1636 .pm = SERIAL_SAMSUNG_PM_OPS,
1637 },
1638};
b497549a 1639
da121506 1640/* module initialisation code */
b497549a 1641
da121506
TA		 1642static int __init s3c24xx_serial_modinit(void)
1643{
1644 int ret;
1645
1646 ret = uart_register_driver(&s3c24xx_uart_drv);
1647 if (ret < 0) {
1648 printk(KERN_ERR "failed to register UART driver\n");
1649 return -1;
1650 }
1651
1652 return platform_driver_register(&samsung_serial_driver);
b497549a
BD		 1653}
1654
da121506
TA		 1655static void __exit s3c24xx_serial_modexit(void)
1656{
1657 uart_unregister_driver(&s3c24xx_uart_drv);
1658}
1659
1660module_init(s3c24xx_serial_modinit);
1661module_exit(s3c24xx_serial_modexit);
b497549a 1662
da121506 1663MODULE_ALIAS("platform:samsung-uart");
b497549a
BD		 1664MODULE_DESCRIPTION("Samsung SoC Serial port driver");
1665MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
1666MODULE_LICENSE("GPL v2");
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