projects / linux-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
TTY: move low_latency to tty_port
[linux-block.git] / drivers / tty / serial / samsung.c
CommitLineData
99edb3d1 1/*
b497549a
BD		 2 * Driver core for Samsung SoC onboard UARTs.
3 *
ccae941e 4 * Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics
b497549a
BD		 5 * http://armlinux.simtec.co.uk/
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12/* Hote on 2410 error handling
13 *
14 * The s3c2410 manual has a love/hate affair with the contents of the
15 * UERSTAT register in the UART blocks, and keeps marking some of the
16 * error bits as reserved. Having checked with the s3c2410x01,
17 * it copes with BREAKs properly, so I am happy to ignore the RESERVED
18 * feature from the latter versions of the manual.
19 *
20 * If it becomes aparrent that latter versions of the 2410 remove these
21 * bits, then action will have to be taken to differentiate the versions
22 * and change the policy on BREAK
23 *
24 * BJD, 04-Nov-2004
25*/
26
27#if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
28#define SUPPORT_SYSRQ
29#endif
30
31#include <linux/module.h>
32#include <linux/ioport.h>
33#include <linux/io.h>
34#include <linux/platform_device.h>
35#include <linux/init.h>
36#include <linux/sysrq.h>
37#include <linux/console.h>
38#include <linux/tty.h>
39#include <linux/tty_flip.h>
40#include <linux/serial_core.h>
41#include <linux/serial.h>
42#include <linux/delay.h>
43#include <linux/clk.h>
30555476 44#include <linux/cpufreq.h>
26c919e1 45#include <linux/of.h>
b497549a
BD		 46
47#include <asm/irq.h>
48
a09e64fb 49#include <mach/hardware.h>
b497549a 50
a2b7ba9c 51#include <plat/regs-serial.h>
5f5a7a55 52#include <plat/clock.h>
b497549a
BD		 53
54#include "samsung.h"
55
56/* UART name and device definitions */
57
58#define S3C24XX_SERIAL_NAME "ttySAC"
59#define S3C24XX_SERIAL_MAJOR 204
60#define S3C24XX_SERIAL_MINOR 64
61
b497549a
BD		 62/* macros to change one thing to another */
63
64#define tx_enabled(port) ((port)->unused[0])
65#define rx_enabled(port) ((port)->unused[1])
66
25985edc 67/* flag to ignore all characters coming in */
b497549a
BD		 68#define RXSTAT_DUMMY_READ (0x10000000)
69
70static inline struct s3c24xx_uart_port *to_ourport(struct uart_port *port)
71{
72 return container_of(port, struct s3c24xx_uart_port, port);
73}
74
75/* translate a port to the device name */
76
77static inline const char *s3c24xx_serial_portname(struct uart_port *port)
78{
79 return to_platform_device(port->dev)->name;
80}
81
82static int s3c24xx_serial_txempty_nofifo(struct uart_port *port)
83{
9303ac15 84 return rd_regl(port, S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE;
b497549a
BD		 85}
86
88bb4ea1
TA		 87/*
88 * s3c64xx and later SoC's include the interrupt mask and status registers in
89 * the controller itself, unlike the s3c24xx SoC's which have these registers
90 * in the interrupt controller. Check if the port type is s3c64xx or higher.
91 */
92static int s3c24xx_serial_has_interrupt_mask(struct uart_port *port)
93{
94 return to_ourport(port)->info->type == PORT_S3C6400;
95}
96
b497549a
BD		 97static void s3c24xx_serial_rx_enable(struct uart_port *port)
98{
99 unsigned long flags;
100 unsigned int ucon, ufcon;
101 int count = 10000;
102
103 spin_lock_irqsave(&port->lock, flags);
104
105 while (--count && !s3c24xx_serial_txempty_nofifo(port))
106 udelay(100);
107
108 ufcon = rd_regl(port, S3C2410_UFCON);
109 ufcon |= S3C2410_UFCON_RESETRX;
110 wr_regl(port, S3C2410_UFCON, ufcon);
111
112 ucon = rd_regl(port, S3C2410_UCON);
113 ucon |= S3C2410_UCON_RXIRQMODE;
114 wr_regl(port, S3C2410_UCON, ucon);
115
116 rx_enabled(port) = 1;
117 spin_unlock_irqrestore(&port->lock, flags);
118}
119
120static void s3c24xx_serial_rx_disable(struct uart_port *port)
121{
122 unsigned long flags;
123 unsigned int ucon;
124
125 spin_lock_irqsave(&port->lock, flags);
126
127 ucon = rd_regl(port, S3C2410_UCON);
128 ucon &= ~S3C2410_UCON_RXIRQMODE;
129 wr_regl(port, S3C2410_UCON, ucon);
130
131 rx_enabled(port) = 0;
132 spin_unlock_irqrestore(&port->lock, flags);
133}
134
135static void s3c24xx_serial_stop_tx(struct uart_port *port)
136{
b73c289c
BD		 137 struct s3c24xx_uart_port *ourport = to_ourport(port);
138
b497549a 139 if (tx_enabled(port)) {
88bb4ea1
TA		 140 if (s3c24xx_serial_has_interrupt_mask(port))
141 __set_bit(S3C64XX_UINTM_TXD,
142 portaddrl(port, S3C64XX_UINTM));
143 else
144 disable_irq_nosync(ourport->tx_irq);
b497549a
BD		 145 tx_enabled(port) = 0;
146 if (port->flags & UPF_CONS_FLOW)
147 s3c24xx_serial_rx_enable(port);
148 }
149}
150
151static void s3c24xx_serial_start_tx(struct uart_port *port)
152{
b73c289c
BD		 153 struct s3c24xx_uart_port *ourport = to_ourport(port);
154
b497549a
BD		 155 if (!tx_enabled(port)) {
156 if (port->flags & UPF_CONS_FLOW)
157 s3c24xx_serial_rx_disable(port);
158
88bb4ea1
TA		 159 if (s3c24xx_serial_has_interrupt_mask(port))
160 __clear_bit(S3C64XX_UINTM_TXD,
161 portaddrl(port, S3C64XX_UINTM));
162 else
163 enable_irq(ourport->tx_irq);
b497549a
BD		 164 tx_enabled(port) = 1;
165 }
166}
167
b497549a
BD		 168static void s3c24xx_serial_stop_rx(struct uart_port *port)
169{
b73c289c
BD		 170 struct s3c24xx_uart_port *ourport = to_ourport(port);
171
b497549a
BD		 172 if (rx_enabled(port)) {
173 dbg("s3c24xx_serial_stop_rx: port=%p\n", port);
88bb4ea1
TA		 174 if (s3c24xx_serial_has_interrupt_mask(port))
175 __set_bit(S3C64XX_UINTM_RXD,
176 portaddrl(port, S3C64XX_UINTM));
177 else
178 disable_irq_nosync(ourport->rx_irq);
b497549a
BD		 179 rx_enabled(port) = 0;
180 }
181}
182
183static void s3c24xx_serial_enable_ms(struct uart_port *port)
184{
185}
186
187static inline struct s3c24xx_uart_info *s3c24xx_port_to_info(struct uart_port *port)
188{
189 return to_ourport(port)->info;
190}
191
192static inline struct s3c2410_uartcfg *s3c24xx_port_to_cfg(struct uart_port *port)
193{
4d84e970
TA		 194 struct s3c24xx_uart_port *ourport;
195
b497549a
BD		 196 if (port->dev == NULL)
197 return NULL;
198
4d84e970
TA		 199 ourport = container_of(port, struct s3c24xx_uart_port, port);
200 return ourport->cfg;
b497549a
BD		 201}
202
203static int s3c24xx_serial_rx_fifocnt(struct s3c24xx_uart_port *ourport,
204 unsigned long ufstat)
205{
206 struct s3c24xx_uart_info *info = ourport->info;
207
208 if (ufstat & info->rx_fifofull)
da121506 209 return ourport->port.fifosize;
b497549a
BD		 210
211 return (ufstat & info->rx_fifomask) >> info->rx_fifoshift;
212}
213
214
215/* ? - where has parity gone?? */
216#define S3C2410_UERSTAT_PARITY (0x1000)
217
218static irqreturn_t
219s3c24xx_serial_rx_chars(int irq, void *dev_id)
220{
221 struct s3c24xx_uart_port *ourport = dev_id;
222 struct uart_port *port = &ourport->port;
ebd2c8f6 223 struct tty_struct *tty = port->state->port.tty;
b497549a 224 unsigned int ufcon, ch, flag, ufstat, uerstat;
c15c3747 225 unsigned long flags;
b497549a
BD		 226 int max_count = 64;
227
c15c3747
TA		 228 spin_lock_irqsave(&port->lock, flags);
229
b497549a
BD		 230 while (max_count-- > 0) {
231 ufcon = rd_regl(port, S3C2410_UFCON);
232 ufstat = rd_regl(port, S3C2410_UFSTAT);
233
234 if (s3c24xx_serial_rx_fifocnt(ourport, ufstat) == 0)
235 break;
236
237 uerstat = rd_regl(port, S3C2410_UERSTAT);
238 ch = rd_regb(port, S3C2410_URXH);
239
240 if (port->flags & UPF_CONS_FLOW) {
241 int txe = s3c24xx_serial_txempty_nofifo(port);
242
243 if (rx_enabled(port)) {
244 if (!txe) {
245 rx_enabled(port) = 0;
246 continue;
247 }
248 } else {
249 if (txe) {
250 ufcon |= S3C2410_UFCON_RESETRX;
251 wr_regl(port, S3C2410_UFCON, ufcon);
252 rx_enabled(port) = 1;
253 goto out;
254 }
255 continue;
256 }
257 }
258
259 /* insert the character into the buffer */
260
261 flag = TTY_NORMAL;
262 port->icount.rx++;
263
264 if (unlikely(uerstat & S3C2410_UERSTAT_ANY)) {
265 dbg("rxerr: port ch=0x%02x, rxs=0x%08x\n",
266 ch, uerstat);
267
268 /* check for break */
269 if (uerstat & S3C2410_UERSTAT_BREAK) {
270 dbg("break!\n");
271 port->icount.brk++;
272 if (uart_handle_break(port))
9303ac15 273 goto ignore_char;
b497549a
BD		 274 }
275
276 if (uerstat & S3C2410_UERSTAT_FRAME)
277 port->icount.frame++;
278 if (uerstat & S3C2410_UERSTAT_OVERRUN)
279 port->icount.overrun++;
280
281 uerstat &= port->read_status_mask;
282
283 if (uerstat & S3C2410_UERSTAT_BREAK)
284 flag = TTY_BREAK;
285 else if (uerstat & S3C2410_UERSTAT_PARITY)
286 flag = TTY_PARITY;
287 else if (uerstat & (S3C2410_UERSTAT_FRAME |
288 S3C2410_UERSTAT_OVERRUN))
289 flag = TTY_FRAME;
290 }
291
292 if (uart_handle_sysrq_char(port, ch))
293 goto ignore_char;
294
295 uart_insert_char(port, uerstat, S3C2410_UERSTAT_OVERRUN,
296 ch, flag);
297
298 ignore_char:
299 continue;
300 }
301 tty_flip_buffer_push(tty);
302
303 out:
c15c3747 304 spin_unlock_irqrestore(&port->lock, flags);
b497549a
BD		 305 return IRQ_HANDLED;
306}
307
308static irqreturn_t s3c24xx_serial_tx_chars(int irq, void *id)
309{
310 struct s3c24xx_uart_port *ourport = id;
311 struct uart_port *port = &ourport->port;
ebd2c8f6 312 struct circ_buf *xmit = &port->state->xmit;
c15c3747 313 unsigned long flags;
b497549a
BD		 314 int count = 256;
315
c15c3747
TA		 316 spin_lock_irqsave(&port->lock, flags);
317
b497549a
BD		 318 if (port->x_char) {
319 wr_regb(port, S3C2410_UTXH, port->x_char);
320 port->icount.tx++;
321 port->x_char = 0;
322 goto out;
323 }
324
25985edc 325 /* if there isn't anything more to transmit, or the uart is now
b497549a
BD		 326 * stopped, disable the uart and exit
327 */
328
329 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
330 s3c24xx_serial_stop_tx(port);
331 goto out;
332 }
333
334 /* try and drain the buffer... */
335
336 while (!uart_circ_empty(xmit) && count-- > 0) {
337 if (rd_regl(port, S3C2410_UFSTAT) & ourport->info->tx_fifofull)
338 break;
339
340 wr_regb(port, S3C2410_UTXH, xmit->buf[xmit->tail]);
341 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
342 port->icount.tx++;
343 }
344
c15c3747
TA		 345 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) {
346 spin_unlock(&port->lock);
b497549a 347 uart_write_wakeup(port);
c15c3747
TA		 348 spin_lock(&port->lock);
349 }
b497549a
BD		 350
351 if (uart_circ_empty(xmit))
352 s3c24xx_serial_stop_tx(port);
353
354 out:
c15c3747 355 spin_unlock_irqrestore(&port->lock, flags);
b497549a
BD		 356 return IRQ_HANDLED;
357}
358
88bb4ea1
TA		 359/* interrupt handler for s3c64xx and later SoC's.*/
360static irqreturn_t s3c64xx_serial_handle_irq(int irq, void *id)
361{
362 struct s3c24xx_uart_port *ourport = id;
363 struct uart_port *port = &ourport->port;
364 unsigned int pend = rd_regl(port, S3C64XX_UINTP);
88bb4ea1
TA		 365 irqreturn_t ret = IRQ_HANDLED;
366
88bb4ea1
TA		 367 if (pend & S3C64XX_UINTM_RXD_MSK) {
368 ret = s3c24xx_serial_rx_chars(irq, id);
369 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_RXD_MSK);
370 }
371 if (pend & S3C64XX_UINTM_TXD_MSK) {
372 ret = s3c24xx_serial_tx_chars(irq, id);
373 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_TXD_MSK);
374 }
88bb4ea1
TA		 375 return ret;
376}
377
b497549a
BD		 378static unsigned int s3c24xx_serial_tx_empty(struct uart_port *port)
379{
380 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
381 unsigned long ufstat = rd_regl(port, S3C2410_UFSTAT);
382 unsigned long ufcon = rd_regl(port, S3C2410_UFCON);
383
384 if (ufcon & S3C2410_UFCON_FIFOMODE) {
385 if ((ufstat & info->tx_fifomask) != 0 ||
386 (ufstat & info->tx_fifofull))
387 return 0;
388
389 return 1;
390 }
391
392 return s3c24xx_serial_txempty_nofifo(port);
393}
394
395/* no modem control lines */
396static unsigned int s3c24xx_serial_get_mctrl(struct uart_port *port)
397{
398 unsigned int umstat = rd_regb(port, S3C2410_UMSTAT);
399
400 if (umstat & S3C2410_UMSTAT_CTS)
401 return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
402 else
403 return TIOCM_CAR | TIOCM_DSR;
404}
405
406static void s3c24xx_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
407{
408 /* todo - possibly remove AFC and do manual CTS */
409}
410
411static void s3c24xx_serial_break_ctl(struct uart_port *port, int break_state)
412{
413 unsigned long flags;
414 unsigned int ucon;
415
416 spin_lock_irqsave(&port->lock, flags);
417
418 ucon = rd_regl(port, S3C2410_UCON);
419
420 if (break_state)
421 ucon |= S3C2410_UCON_SBREAK;
422 else
423 ucon &= ~S3C2410_UCON_SBREAK;
424
425 wr_regl(port, S3C2410_UCON, ucon);
426
427 spin_unlock_irqrestore(&port->lock, flags);
428}
429
430static void s3c24xx_serial_shutdown(struct uart_port *port)
431{
432 struct s3c24xx_uart_port *ourport = to_ourport(port);
433
434 if (ourport->tx_claimed) {
88bb4ea1
TA		 435 if (!s3c24xx_serial_has_interrupt_mask(port))
436 free_irq(ourport->tx_irq, ourport);
b497549a
BD		 437 tx_enabled(port) = 0;
438 ourport->tx_claimed = 0;
439 }
440
441 if (ourport->rx_claimed) {
88bb4ea1
TA		 442 if (!s3c24xx_serial_has_interrupt_mask(port))
443 free_irq(ourport->rx_irq, ourport);
b497549a
BD		 444 ourport->rx_claimed = 0;
445 rx_enabled(port) = 0;
446 }
b497549a 447
88bb4ea1
TA		 448 /* Clear pending interrupts and mask all interrupts */
449 if (s3c24xx_serial_has_interrupt_mask(port)) {
450 wr_regl(port, S3C64XX_UINTP, 0xf);
451 wr_regl(port, S3C64XX_UINTM, 0xf);
452 }
453}
b497549a
BD		 454
455static int s3c24xx_serial_startup(struct uart_port *port)
456{
457 struct s3c24xx_uart_port *ourport = to_ourport(port);
458 int ret;
459
460 dbg("s3c24xx_serial_startup: port=%p (%08lx,%p)\n",
461 port->mapbase, port->membase);
462
463 rx_enabled(port) = 1;
464
b73c289c 465 ret = request_irq(ourport->rx_irq, s3c24xx_serial_rx_chars, 0,
b497549a
BD		 466 s3c24xx_serial_portname(port), ourport);
467
468 if (ret != 0) {
d20925e1 469 dev_err(port->dev, "cannot get irq %d\n", ourport->rx_irq);
b497549a
BD		 470 return ret;
471 }
472
473 ourport->rx_claimed = 1;
474
475 dbg("requesting tx irq...\n");
476
477 tx_enabled(port) = 1;
478
b73c289c 479 ret = request_irq(ourport->tx_irq, s3c24xx_serial_tx_chars, 0,
b497549a
BD		 480 s3c24xx_serial_portname(port), ourport);
481
482 if (ret) {
d20925e1 483 dev_err(port->dev, "cannot get irq %d\n", ourport->tx_irq);
b497549a
BD		 484 goto err;
485 }
486
487 ourport->tx_claimed = 1;
488
489 dbg("s3c24xx_serial_startup ok\n");
490
491 /* the port reset code should have done the correct
492 * register setup for the port controls */
493
494 return ret;
495
496 err:
497 s3c24xx_serial_shutdown(port);
498 return ret;
499}
500
88bb4ea1
TA		 501static int s3c64xx_serial_startup(struct uart_port *port)
502{
503 struct s3c24xx_uart_port *ourport = to_ourport(port);
504 int ret;
505
506 dbg("s3c64xx_serial_startup: port=%p (%08lx,%p)\n",
507 port->mapbase, port->membase);
508
509 ret = request_irq(port->irq, s3c64xx_serial_handle_irq, IRQF_SHARED,
510 s3c24xx_serial_portname(port), ourport);
511 if (ret) {
d20925e1 512 dev_err(port->dev, "cannot get irq %d\n", port->irq);
88bb4ea1
TA		 513 return ret;
514 }
515
516 /* For compatibility with s3c24xx Soc's */
517 rx_enabled(port) = 1;
518 ourport->rx_claimed = 1;
519 tx_enabled(port) = 0;
520 ourport->tx_claimed = 1;
521
522 /* Enable Rx Interrupt */
523 __clear_bit(S3C64XX_UINTM_RXD, portaddrl(port, S3C64XX_UINTM));
524 dbg("s3c64xx_serial_startup ok\n");
525 return ret;
526}
527
b497549a
BD		 528/* power power management control */
529
530static void s3c24xx_serial_pm(struct uart_port *port, unsigned int level,
531 unsigned int old)
532{
533 struct s3c24xx_uart_port *ourport = to_ourport(port);
534
30555476
BD		 535 ourport->pm_level = level;
536
b497549a
BD		 537 switch (level) {
538 case 3:
7cd88831 539 if (!IS_ERR(ourport->baudclk))
9484b009 540 clk_disable_unprepare(ourport->baudclk);
b497549a 541
9484b009 542 clk_disable_unprepare(ourport->clk);
b497549a
BD		 543 break;
544
545 case 0:
9484b009 546 clk_prepare_enable(ourport->clk);
b497549a 547
7cd88831 548 if (!IS_ERR(ourport->baudclk))
9484b009 549 clk_prepare_enable(ourport->baudclk);
b497549a
BD		 550
551 break;
552 default:
d20925e1 553 dev_err(port->dev, "s3c24xx_serial: unknown pm %d\n", level);
b497549a
BD		 554 }
555}
556
557/* baud rate calculation
558 *
559 * The UARTs on the S3C2410/S3C2440 can take their clocks from a number
560 * of different sources, including the peripheral clock ("pclk") and an
561 * external clock ("uclk"). The S3C2440 also adds the core clock ("fclk")
562 * with a programmable extra divisor.
563 *
564 * The following code goes through the clock sources, and calculates the
565 * baud clocks (and the resultant actual baud rates) and then tries to
566 * pick the closest one and select that.
567 *
568*/
569
5f5a7a55 570#define MAX_CLK_NAME_LENGTH 15
b497549a 571
5f5a7a55 572static inline int s3c24xx_serial_getsource(struct uart_port *port)
b497549a
BD		 573{
574 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
5f5a7a55 575 unsigned int ucon;
b497549a 576
5f5a7a55
TA		 577 if (info->num_clks == 1)
578 return 0;
b497549a 579
5f5a7a55
TA		 580 ucon = rd_regl(port, S3C2410_UCON);
581 ucon &= info->clksel_mask;
582 return ucon >> info->clksel_shift;
b497549a
BD		 583}
584
5f5a7a55
TA		 585static void s3c24xx_serial_setsource(struct uart_port *port,
586 unsigned int clk_sel)
b497549a 587{
5f5a7a55
TA		 588 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
589 unsigned int ucon;
b497549a 590
5f5a7a55
TA		 591 if (info->num_clks == 1)
592 return;
090f848d 593
5f5a7a55
TA		 594 ucon = rd_regl(port, S3C2410_UCON);
595 if ((ucon & info->clksel_mask) >> info->clksel_shift == clk_sel)
596 return;
b497549a 597
5f5a7a55
TA		 598 ucon &= ~info->clksel_mask;
599 ucon |= clk_sel << info->clksel_shift;
600 wr_regl(port, S3C2410_UCON, ucon);
b497549a
BD		 601}
602
5f5a7a55
TA		 603static unsigned int s3c24xx_serial_getclk(struct s3c24xx_uart_port *ourport,
604 unsigned int req_baud, struct clk **best_clk,
605 unsigned int *clk_num)
b497549a 606{
5f5a7a55
TA		 607 struct s3c24xx_uart_info *info = ourport->info;
608 struct clk *clk;
609 unsigned long rate;
610 unsigned int cnt, baud, quot, clk_sel, best_quot = 0;
611 char clkname[MAX_CLK_NAME_LENGTH];
612 int calc_deviation, deviation = (1 << 30) - 1;
613
5f5a7a55
TA		 614 clk_sel = (ourport->cfg->clk_sel) ? ourport->cfg->clk_sel :
615 ourport->info->def_clk_sel;
616 for (cnt = 0; cnt < info->num_clks; cnt++) {
617 if (!(clk_sel & (1 << cnt)))
618 continue;
619
620 sprintf(clkname, "clk_uart_baud%d", cnt);
621 clk = clk_get(ourport->port.dev, clkname);
7cd88831 622 if (IS_ERR(clk))
5f5a7a55
TA		 623 continue;
624
625 rate = clk_get_rate(clk);
626 if (!rate)
627 continue;
628
629 if (ourport->info->has_divslot) {
630 unsigned long div = rate / req_baud;
631
632 /* The UDIVSLOT register on the newer UARTs allows us to
633 * get a divisor adjustment of 1/16th on the baud clock.
634 *
635 * We don't keep the UDIVSLOT value (the 16ths we
636 * calculated by not multiplying the baud by 16) as it
637 * is easy enough to recalculate.
638 */
639
640 quot = div / 16;
641 baud = rate / div;
642 } else {
643 quot = (rate + (8 * req_baud)) / (16 * req_baud);
644 baud = rate / (quot * 16);
b497549a 645 }
5f5a7a55 646 quot--;
b497549a 647
5f5a7a55
TA		 648 calc_deviation = req_baud - baud;
649 if (calc_deviation < 0)
650 calc_deviation = -calc_deviation;
b497549a 651
5f5a7a55
TA		 652 if (calc_deviation < deviation) {
653 *best_clk = clk;
654 best_quot = quot;
655 *clk_num = cnt;
656 deviation = calc_deviation;
b497549a
BD		 657 }
658 }
659
5f5a7a55 660 return best_quot;
b497549a
BD		 661}
662
090f848d
BD		 663/* udivslot_table[]
664 *
665 * This table takes the fractional value of the baud divisor and gives
666 * the recommended setting for the UDIVSLOT register.
667 */
668static u16 udivslot_table[16] = {
669 [0] = 0x0000,
670 [1] = 0x0080,
671 [2] = 0x0808,
672 [3] = 0x0888,
673 [4] = 0x2222,
674 [5] = 0x4924,
675 [6] = 0x4A52,
676 [7] = 0x54AA,
677 [8] = 0x5555,
678 [9] = 0xD555,
679 [10] = 0xD5D5,
680 [11] = 0xDDD5,
681 [12] = 0xDDDD,
682 [13] = 0xDFDD,
683 [14] = 0xDFDF,
684 [15] = 0xFFDF,
685};
686
b497549a
BD		 687static void s3c24xx_serial_set_termios(struct uart_port *port,
688 struct ktermios *termios,
689 struct ktermios *old)
690{
691 struct s3c2410_uartcfg *cfg = s3c24xx_port_to_cfg(port);
692 struct s3c24xx_uart_port *ourport = to_ourport(port);
7cd88831 693 struct clk *clk = ERR_PTR(-EINVAL);
b497549a 694 unsigned long flags;
5f5a7a55 695 unsigned int baud, quot, clk_sel = 0;
b497549a
BD		 696 unsigned int ulcon;
697 unsigned int umcon;
090f848d 698 unsigned int udivslot = 0;
b497549a
BD		 699
700 /*
701 * We don't support modem control lines.
702 */
703 termios->c_cflag &= ~(HUPCL | CMSPAR);
704 termios->c_cflag |= CLOCAL;
705
706 /*
707 * Ask the core to calculate the divisor for us.
708 */
709
710 baud = uart_get_baud_rate(port, termios, old, 0, 115200*8);
5f5a7a55 711 quot = s3c24xx_serial_getclk(ourport, baud, &clk, &clk_sel);
b497549a
BD		 712 if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST)
713 quot = port->custom_divisor;
7cd88831 714 if (IS_ERR(clk))
5f5a7a55 715 return;
b497549a
BD		 716
717 /* check to see if we need to change clock source */
718
5f5a7a55
TA		 719 if (ourport->baudclk != clk) {
720 s3c24xx_serial_setsource(port, clk_sel);
b497549a 721
7cd88831 722 if (!IS_ERR(ourport->baudclk)) {
9484b009 723 clk_disable_unprepare(ourport->baudclk);
7cd88831 724 ourport->baudclk = ERR_PTR(-EINVAL);
b497549a
BD		 725 }
726
9484b009 727 clk_prepare_enable(clk);
b497549a 728
b497549a 729 ourport->baudclk = clk;
30555476 730 ourport->baudclk_rate = clk ? clk_get_rate(clk) : 0;
b497549a
BD		 731 }
732
090f848d
BD		 733 if (ourport->info->has_divslot) {
734 unsigned int div = ourport->baudclk_rate / baud;
735
8b526ae4
JL		 736 if (cfg->has_fracval) {
737 udivslot = (div & 15);
738 dbg("fracval = %04x\n", udivslot);
739 } else {
740 udivslot = udivslot_table[div & 15];
741 dbg("udivslot = %04x (div %d)\n", udivslot, div & 15);
742 }
090f848d
BD		 743 }
744
b497549a
BD		 745 switch (termios->c_cflag & CSIZE) {
746 case CS5:
747 dbg("config: 5bits/char\n");
748 ulcon = S3C2410_LCON_CS5;
749 break;
750 case CS6:
751 dbg("config: 6bits/char\n");
752 ulcon = S3C2410_LCON_CS6;
753 break;
754 case CS7:
755 dbg("config: 7bits/char\n");
756 ulcon = S3C2410_LCON_CS7;
757 break;
758 case CS8:
759 default:
760 dbg("config: 8bits/char\n");
761 ulcon = S3C2410_LCON_CS8;
762 break;
763 }
764
765 /* preserve original lcon IR settings */
766 ulcon |= (cfg->ulcon & S3C2410_LCON_IRM);
767
768 if (termios->c_cflag & CSTOPB)
769 ulcon |= S3C2410_LCON_STOPB;
770
771 umcon = (termios->c_cflag & CRTSCTS) ? S3C2410_UMCOM_AFC : 0;
772
773 if (termios->c_cflag & PARENB) {
774 if (termios->c_cflag & PARODD)
775 ulcon |= S3C2410_LCON_PODD;
776 else
777 ulcon |= S3C2410_LCON_PEVEN;
778 } else {
779 ulcon |= S3C2410_LCON_PNONE;
780 }
781
782 spin_lock_irqsave(&port->lock, flags);
783
090f848d
BD		 784 dbg("setting ulcon to %08x, brddiv to %d, udivslot %08x\n",
785 ulcon, quot, udivslot);
b497549a
BD		 786
787 wr_regl(port, S3C2410_ULCON, ulcon);
788 wr_regl(port, S3C2410_UBRDIV, quot);
789 wr_regl(port, S3C2410_UMCON, umcon);
790
090f848d
BD		 791 if (ourport->info->has_divslot)
792 wr_regl(port, S3C2443_DIVSLOT, udivslot);
793
b497549a
BD		 794 dbg("uart: ulcon = 0x%08x, ucon = 0x%08x, ufcon = 0x%08x\n",
795 rd_regl(port, S3C2410_ULCON),
796 rd_regl(port, S3C2410_UCON),
797 rd_regl(port, S3C2410_UFCON));
798
799 /*
800 * Update the per-port timeout.
801 */
802 uart_update_timeout(port, termios->c_cflag, baud);
803
804 /*
805 * Which character status flags are we interested in?
806 */
807 port->read_status_mask = S3C2410_UERSTAT_OVERRUN;
808 if (termios->c_iflag & INPCK)
809 port->read_status_mask |= S3C2410_UERSTAT_FRAME | S3C2410_UERSTAT_PARITY;
810
811 /*
812 * Which character status flags should we ignore?
813 */
814 port->ignore_status_mask = 0;
815 if (termios->c_iflag & IGNPAR)
816 port->ignore_status_mask |= S3C2410_UERSTAT_OVERRUN;
817 if (termios->c_iflag & IGNBRK && termios->c_iflag & IGNPAR)
818 port->ignore_status_mask |= S3C2410_UERSTAT_FRAME;
819
820 /*
821 * Ignore all characters if CREAD is not set.
822 */
823 if ((termios->c_cflag & CREAD) == 0)
824 port->ignore_status_mask |= RXSTAT_DUMMY_READ;
825
826 spin_unlock_irqrestore(&port->lock, flags);
827}
828
829static const char *s3c24xx_serial_type(struct uart_port *port)
830{
831 switch (port->type) {
832 case PORT_S3C2410:
833 return "S3C2410";
834 case PORT_S3C2440:
835 return "S3C2440";
836 case PORT_S3C2412:
837 return "S3C2412";
b690ace5
BD		 838 case PORT_S3C6400:
839 return "S3C6400/10";
b497549a
BD		 840 default:
841 return NULL;
842 }
843}
844
845#define MAP_SIZE (0x100)
846
847static void s3c24xx_serial_release_port(struct uart_port *port)
848{
849 release_mem_region(port->mapbase, MAP_SIZE);
850}
851
852static int s3c24xx_serial_request_port(struct uart_port *port)
853{
854 const char *name = s3c24xx_serial_portname(port);
855 return request_mem_region(port->mapbase, MAP_SIZE, name) ? 0 : -EBUSY;
856}
857
858static void s3c24xx_serial_config_port(struct uart_port *port, int flags)
859{
860 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
861
862 if (flags & UART_CONFIG_TYPE &&
863 s3c24xx_serial_request_port(port) == 0)
864 port->type = info->type;
865}
866
867/*
868 * verify the new serial_struct (for TIOCSSERIAL).
869 */
870static int
871s3c24xx_serial_verify_port(struct uart_port *port, struct serial_struct *ser)
872{
873 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
874
875 if (ser->type != PORT_UNKNOWN && ser->type != info->type)
876 return -EINVAL;
877
878 return 0;
879}
880
881
882#ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
883
884static struct console s3c24xx_serial_console;
885
93b5c032
JP		 886static int __init s3c24xx_serial_console_init(void)
887{
888 register_console(&s3c24xx_serial_console);
889 return 0;
890}
891console_initcall(s3c24xx_serial_console_init);
892
b497549a
BD		 893#define S3C24XX_SERIAL_CONSOLE &s3c24xx_serial_console
894#else
895#define S3C24XX_SERIAL_CONSOLE NULL
896#endif
897
93b5c032
JP		 898#ifdef CONFIG_CONSOLE_POLL
899static int s3c24xx_serial_get_poll_char(struct uart_port *port);
900static void s3c24xx_serial_put_poll_char(struct uart_port *port,
901 unsigned char c);
902#endif
903
b497549a
BD		 904static struct uart_ops s3c24xx_serial_ops = {
905 .pm = s3c24xx_serial_pm,
906 .tx_empty = s3c24xx_serial_tx_empty,
907 .get_mctrl = s3c24xx_serial_get_mctrl,
908 .set_mctrl = s3c24xx_serial_set_mctrl,
909 .stop_tx = s3c24xx_serial_stop_tx,
910 .start_tx = s3c24xx_serial_start_tx,
911 .stop_rx = s3c24xx_serial_stop_rx,
912 .enable_ms = s3c24xx_serial_enable_ms,
913 .break_ctl = s3c24xx_serial_break_ctl,
914 .startup = s3c24xx_serial_startup,
915 .shutdown = s3c24xx_serial_shutdown,
916 .set_termios = s3c24xx_serial_set_termios,
917 .type = s3c24xx_serial_type,
918 .release_port = s3c24xx_serial_release_port,
919 .request_port = s3c24xx_serial_request_port,
920 .config_port = s3c24xx_serial_config_port,
921 .verify_port = s3c24xx_serial_verify_port,
93b5c032
JP		 922#ifdef CONFIG_CONSOLE_POLL
923 .poll_get_char = s3c24xx_serial_get_poll_char,
924 .poll_put_char = s3c24xx_serial_put_poll_char,
925#endif
b497549a
BD		 926};
927
b497549a
BD		 928static struct uart_driver s3c24xx_uart_drv = {
929 .owner = THIS_MODULE,
2cf0c58e 930 .driver_name = "s3c2410_serial",
bdd4915a 931 .nr = CONFIG_SERIAL_SAMSUNG_UARTS,
b497549a 932 .cons = S3C24XX_SERIAL_CONSOLE,
2cf0c58e 933 .dev_name = S3C24XX_SERIAL_NAME,
b497549a
BD		 934 .major = S3C24XX_SERIAL_MAJOR,
935 .minor = S3C24XX_SERIAL_MINOR,
936};
937
03d5e77b 938static struct s3c24xx_uart_port s3c24xx_serial_ports[CONFIG_SERIAL_SAMSUNG_UARTS] = {
b497549a
BD		 939 [0] = {
940 .port = {
941 .lock = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[0].port.lock),
942 .iotype = UPIO_MEM,
b497549a
BD		 943 .uartclk = 0,
944 .fifosize = 16,
945 .ops = &s3c24xx_serial_ops,
946 .flags = UPF_BOOT_AUTOCONF,
947 .line = 0,
948 }
949 },
950 [1] = {
951 .port = {
952 .lock = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[1].port.lock),
953 .iotype = UPIO_MEM,
b497549a
BD		 954 .uartclk = 0,
955 .fifosize = 16,
956 .ops = &s3c24xx_serial_ops,
957 .flags = UPF_BOOT_AUTOCONF,
958 .line = 1,
959 }
960 },
03d5e77b 961#if CONFIG_SERIAL_SAMSUNG_UARTS > 2
b497549a
BD		 962
963 [2] = {
964 .port = {
965 .lock = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[2].port.lock),
966 .iotype = UPIO_MEM,
b497549a
BD		 967 .uartclk = 0,
968 .fifosize = 16,
969 .ops = &s3c24xx_serial_ops,
970 .flags = UPF_BOOT_AUTOCONF,
971 .line = 2,
972 }
03d5e77b
BD		 973 },
974#endif
975#if CONFIG_SERIAL_SAMSUNG_UARTS > 3
976 [3] = {
977 .port = {
978 .lock = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[3].port.lock),
979 .iotype = UPIO_MEM,
03d5e77b
BD		 980 .uartclk = 0,
981 .fifosize = 16,
982 .ops = &s3c24xx_serial_ops,
983 .flags = UPF_BOOT_AUTOCONF,
984 .line = 3,
985 }
b497549a
BD		 986 }
987#endif
988};
989
990/* s3c24xx_serial_resetport
991 *
0dfb3b41 992 * reset the fifos and other the settings.
b497549a
BD		 993*/
994
0dfb3b41
TA		 995static void s3c24xx_serial_resetport(struct uart_port *port,
996 struct s3c2410_uartcfg *cfg)
b497549a
BD		 997{
998 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
0dfb3b41
TA		 999 unsigned long ucon = rd_regl(port, S3C2410_UCON);
1000 unsigned int ucon_mask;
b497549a 1001
0dfb3b41
TA		 1002 ucon_mask = info->clksel_mask;
1003 if (info->type == PORT_S3C2440)
1004 ucon_mask |= S3C2440_UCON0_DIVMASK;
1005
1006 ucon &= ucon_mask;
1007 wr_regl(port, S3C2410_UCON, ucon | cfg->ucon);
7b246a1d 1008 wr_regl(port, S3C2410_ULCON, cfg->ulcon);
0dfb3b41
TA		 1009
1010 /* reset both fifos */
1011 wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
1012 wr_regl(port, S3C2410_UFCON, cfg->ufcon);
1013
1014 /* some delay is required after fifo reset */
1015 udelay(1);
b497549a
BD		 1016}
1017
30555476
BD		 1018
1019#ifdef CONFIG_CPU_FREQ
1020
1021static int s3c24xx_serial_cpufreq_transition(struct notifier_block *nb,
1022 unsigned long val, void *data)
1023{
1024 struct s3c24xx_uart_port *port;
1025 struct uart_port *uport;
1026
1027 port = container_of(nb, struct s3c24xx_uart_port, freq_transition);
1028 uport = &port->port;
1029
1030 /* check to see if port is enabled */
1031
1032 if (port->pm_level != 0)
1033 return 0;
1034
1035 /* try and work out if the baudrate is changing, we can detect
1036 * a change in rate, but we do not have support for detecting
1037 * a disturbance in the clock-rate over the change.
1038 */
1039
25f04ad4 1040 if (IS_ERR(port->baudclk))
30555476
BD		 1041 goto exit;
1042
25f04ad4 1043 if (port->baudclk_rate == clk_get_rate(port->baudclk))
30555476
BD		 1044 goto exit;
1045
1046 if (val == CPUFREQ_PRECHANGE) {
1047 /* we should really shut the port down whilst the
1048 * frequency change is in progress. */
1049
1050 } else if (val == CPUFREQ_POSTCHANGE) {
1051 struct ktermios *termios;
1052 struct tty_struct *tty;
1053
ebd2c8f6 1054 if (uport->state == NULL)
30555476 1055 goto exit;
30555476 1056
ebd2c8f6 1057 tty = uport->state->port.tty;
30555476 1058
7de40c21 1059 if (tty == NULL)
30555476 1060 goto exit;
30555476 1061
adc8d746 1062 termios = &tty->termios;
30555476
BD		 1063
1064 if (termios == NULL) {
d20925e1 1065 dev_warn(uport->dev, "%s: no termios?\n", __func__);
30555476
BD		 1066 goto exit;
1067 }
1068
1069 s3c24xx_serial_set_termios(uport, termios, NULL);
1070 }
1071
1072 exit:
1073 return 0;
1074}
1075
1076static inline int s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port)
1077{
1078 port->freq_transition.notifier_call = s3c24xx_serial_cpufreq_transition;
1079
1080 return cpufreq_register_notifier(&port->freq_transition,
1081 CPUFREQ_TRANSITION_NOTIFIER);
1082}
1083
1084static inline void s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port)
1085{
1086 cpufreq_unregister_notifier(&port->freq_transition,
1087 CPUFREQ_TRANSITION_NOTIFIER);
1088}
1089
1090#else
1091static inline int s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port)
1092{
1093 return 0;
1094}
1095
1096static inline void s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port)
1097{
1098}
1099#endif
1100
b497549a
BD		 1101/* s3c24xx_serial_init_port
1102 *
1103 * initialise a single serial port from the platform device given
1104 */
1105
1106static int s3c24xx_serial_init_port(struct s3c24xx_uart_port *ourport,
b497549a
BD		 1107 struct platform_device *platdev)
1108{
1109 struct uart_port *port = &ourport->port;
da121506 1110 struct s3c2410_uartcfg *cfg = ourport->cfg;
b497549a
BD		 1111 struct resource *res;
1112 int ret;
1113
1114 dbg("s3c24xx_serial_init_port: port=%p, platdev=%p\n", port, platdev);
1115
1116 if (platdev == NULL)
1117 return -ENODEV;
1118
b497549a
BD		 1119 if (port->mapbase != 0)
1120 return 0;
1121
b497549a
BD		 1122 /* setup info for port */
1123 port->dev = &platdev->dev;
b497549a 1124
88bb4ea1
TA		 1125 /* Startup sequence is different for s3c64xx and higher SoC's */
1126 if (s3c24xx_serial_has_interrupt_mask(port))
1127 s3c24xx_serial_ops.startup = s3c64xx_serial_startup;
1128
b497549a
BD		 1129 port->uartclk = 1;
1130
1131 if (cfg->uart_flags & UPF_CONS_FLOW) {
1132 dbg("s3c24xx_serial_init_port: enabling flow control\n");
1133 port->flags |= UPF_CONS_FLOW;
1134 }
1135
1136 /* sort our the physical and virtual addresses for each UART */
1137
1138 res = platform_get_resource(platdev, IORESOURCE_MEM, 0);
1139 if (res == NULL) {
d20925e1 1140 dev_err(port->dev, "failed to find memory resource for uart\n");
b497549a
BD		 1141 return -EINVAL;
1142 }
1143
1144 dbg("resource %p (%lx..%lx)\n", res, res->start, res->end);
1145
41147bfd
TA		 1146 port->membase = devm_ioremap(port->dev, res->start, resource_size(res));
1147 if (!port->membase) {
1148 dev_err(port->dev, "failed to remap controller address\n");
1149 return -EBUSY;
1150 }
1151
b690ace5 1152 port->mapbase = res->start;
b497549a
BD		 1153 ret = platform_get_irq(platdev, 0);
1154 if (ret < 0)
1155 port->irq = 0;
b73c289c 1156 else {
b497549a 1157 port->irq = ret;
b73c289c
BD		 1158 ourport->rx_irq = ret;
1159 ourport->tx_irq = ret + 1;
1160 }
9303ac15 1161
b73c289c
BD		 1162 ret = platform_get_irq(platdev, 1);
1163 if (ret > 0)
1164 ourport->tx_irq = ret;
b497549a
BD		 1165
1166 ourport->clk = clk_get(&platdev->dev, "uart");
1167
88bb4ea1
TA		 1168 /* Keep all interrupts masked and cleared */
1169 if (s3c24xx_serial_has_interrupt_mask(port)) {
1170 wr_regl(port, S3C64XX_UINTM, 0xf);
1171 wr_regl(port, S3C64XX_UINTP, 0xf);
1172 wr_regl(port, S3C64XX_UINTSP, 0xf);
1173 }
1174
b73c289c
BD		 1175 dbg("port: map=%08x, mem=%08x, irq=%d (%d,%d), clock=%ld\n",
1176 port->mapbase, port->membase, port->irq,
1177 ourport->rx_irq, ourport->tx_irq, port->uartclk);
b497549a
BD		 1178
1179 /* reset the fifos (and setup the uart) */
1180 s3c24xx_serial_resetport(port, cfg);
1181 return 0;
1182}
1183
1184static ssize_t s3c24xx_serial_show_clksrc(struct device *dev,
1185 struct device_attribute *attr,
1186 char *buf)
1187{
1188 struct uart_port *port = s3c24xx_dev_to_port(dev);
1189 struct s3c24xx_uart_port *ourport = to_ourport(port);
1190
7cd88831
KK		 1191 if (IS_ERR(ourport->baudclk))
1192 return -EINVAL;
1193
7b15e1d9
KP		 1194 return snprintf(buf, PAGE_SIZE, "* %s\n",
1195 ourport->baudclk->name ?: "(null)");
b497549a
BD		 1196}
1197
1198static DEVICE_ATTR(clock_source, S_IRUGO, s3c24xx_serial_show_clksrc, NULL);
1199
26c919e1 1200
b497549a
BD		 1201/* Device driver serial port probe */
1202
26c919e1 1203static const struct of_device_id s3c24xx_uart_dt_match[];
b497549a
BD		 1204static int probe_index;
1205
26c919e1
TA		 1206static inline struct s3c24xx_serial_drv_data *s3c24xx_get_driver_data(
1207 struct platform_device *pdev)
1208{
1209#ifdef CONFIG_OF
1210 if (pdev->dev.of_node) {
1211 const struct of_device_id *match;
1212 match = of_match_node(s3c24xx_uart_dt_match, pdev->dev.of_node);
1213 return (struct s3c24xx_serial_drv_data *)match->data;
1214 }
1215#endif
1216 return (struct s3c24xx_serial_drv_data *)
1217 platform_get_device_id(pdev)->driver_data;
1218}
1219
da121506 1220static int s3c24xx_serial_probe(struct platform_device *pdev)
b497549a
BD		 1221{
1222 struct s3c24xx_uart_port *ourport;
1223 int ret;
1224
da121506 1225 dbg("s3c24xx_serial_probe(%p) %d\n", pdev, probe_index);
b497549a
BD		 1226
1227 ourport = &s3c24xx_serial_ports[probe_index];
da121506 1228
26c919e1
TA		 1229 ourport->drv_data = s3c24xx_get_driver_data(pdev);
1230 if (!ourport->drv_data) {
1231 dev_err(&pdev->dev, "could not find driver data\n");
1232 return -ENODEV;
1233 }
da121506 1234
7cd88831 1235 ourport->baudclk = ERR_PTR(-EINVAL);
da121506
TA		 1236 ourport->info = ourport->drv_data->info;
1237 ourport->cfg = (pdev->dev.platform_data) ?
1238 (struct s3c2410_uartcfg *)pdev->dev.platform_data :
1239 ourport->drv_data->def_cfg;
1240
1241 ourport->port.fifosize = (ourport->info->fifosize) ?
1242 ourport->info->fifosize :
1243 ourport->drv_data->fifosize[probe_index];
1244
b497549a
BD		 1245 probe_index++;
1246
1247 dbg("%s: initialising port %p...\n", __func__, ourport);
1248
da121506 1249 ret = s3c24xx_serial_init_port(ourport, pdev);
b497549a
BD		 1250 if (ret < 0)
1251 goto probe_err;
1252
1253 dbg("%s: adding port\n", __func__);
1254 uart_add_one_port(&s3c24xx_uart_drv, &ourport->port);
da121506 1255 platform_set_drvdata(pdev, &ourport->port);
b497549a 1256
da121506 1257 ret = device_create_file(&pdev->dev, &dev_attr_clock_source);
b497549a 1258 if (ret < 0)
da121506 1259 dev_err(&pdev->dev, "failed to add clock source attr.\n");
b497549a 1260
30555476
BD		 1261 ret = s3c24xx_serial_cpufreq_register(ourport);
1262 if (ret < 0)
da121506 1263 dev_err(&pdev->dev, "failed to add cpufreq notifier\n");
30555476 1264
b497549a
BD		 1265 return 0;
1266
1267 probe_err:
1268 return ret;
1269}
1270
ae8d8a14 1271static int s3c24xx_serial_remove(struct platform_device *dev)
b497549a
BD		 1272{
1273 struct uart_port *port = s3c24xx_dev_to_port(&dev->dev);
1274
1275 if (port) {
30555476 1276 s3c24xx_serial_cpufreq_deregister(to_ourport(port));
b497549a
BD		 1277 device_remove_file(&dev->dev, &dev_attr_clock_source);
1278 uart_remove_one_port(&s3c24xx_uart_drv, port);
1279 }
1280
1281 return 0;
1282}
1283
b497549a 1284/* UART power management code */
aef7fe52
MH		 1285#ifdef CONFIG_PM_SLEEP
1286static int s3c24xx_serial_suspend(struct device *dev)
b497549a 1287{
aef7fe52 1288 struct uart_port *port = s3c24xx_dev_to_port(dev);
b497549a
BD		 1289
1290 if (port)
1291 uart_suspend_port(&s3c24xx_uart_drv, port);
1292
1293 return 0;
1294}
1295
aef7fe52 1296static int s3c24xx_serial_resume(struct device *dev)
b497549a 1297{
aef7fe52 1298 struct uart_port *port = s3c24xx_dev_to_port(dev);
b497549a
BD		 1299 struct s3c24xx_uart_port *ourport = to_ourport(port);
1300
1301 if (port) {
9484b009 1302 clk_prepare_enable(ourport->clk);
b497549a 1303 s3c24xx_serial_resetport(port, s3c24xx_port_to_cfg(port));
9484b009 1304 clk_disable_unprepare(ourport->clk);
b497549a
BD		 1305
1306 uart_resume_port(&s3c24xx_uart_drv, port);
1307 }
1308
1309 return 0;
1310}
aef7fe52
MH		 1311
1312static const struct dev_pm_ops s3c24xx_serial_pm_ops = {
1313 .suspend = s3c24xx_serial_suspend,
1314 .resume = s3c24xx_serial_resume,
1315};
b882fc1b
KK		 1316#define SERIAL_SAMSUNG_PM_OPS (&s3c24xx_serial_pm_ops)
1317
aef7fe52 1318#else /* !CONFIG_PM_SLEEP */
b882fc1b
KK		 1319
1320#define SERIAL_SAMSUNG_PM_OPS NULL
aef7fe52 1321#endif /* CONFIG_PM_SLEEP */
b497549a 1322
b497549a
BD		 1323/* Console code */
1324
1325#ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
1326
1327static struct uart_port *cons_uart;
1328
1329static int
1330s3c24xx_serial_console_txrdy(struct uart_port *port, unsigned int ufcon)
1331{
1332 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1333 unsigned long ufstat, utrstat;
1334
1335 if (ufcon & S3C2410_UFCON_FIFOMODE) {
9ddc5b6f 1336 /* fifo mode - check amount of data in fifo registers... */
b497549a
BD		 1337
1338 ufstat = rd_regl(port, S3C2410_UFSTAT);
1339 return (ufstat & info->tx_fifofull) ? 0 : 1;
1340 }
1341
1342 /* in non-fifo mode, we go and use the tx buffer empty */
1343
1344 utrstat = rd_regl(port, S3C2410_UTRSTAT);
1345 return (utrstat & S3C2410_UTRSTAT_TXE) ? 1 : 0;
1346}
1347
93b5c032
JP		 1348#ifdef CONFIG_CONSOLE_POLL
1349/*
1350 * Console polling routines for writing and reading from the uart while
1351 * in an interrupt or debug context.
1352 */
1353
1354static int s3c24xx_serial_get_poll_char(struct uart_port *port)
1355{
1356 struct s3c24xx_uart_port *ourport = to_ourport(port);
1357 unsigned int ufstat;
1358
1359 ufstat = rd_regl(port, S3C2410_UFSTAT);
1360 if (s3c24xx_serial_rx_fifocnt(ourport, ufstat) == 0)
1361 return NO_POLL_CHAR;
1362
1363 return rd_regb(port, S3C2410_URXH);
1364}
1365
1366static void s3c24xx_serial_put_poll_char(struct uart_port *port,
1367 unsigned char c)
1368{
1369 unsigned int ufcon = rd_regl(cons_uart, S3C2410_UFCON);
1370
1371 while (!s3c24xx_serial_console_txrdy(port, ufcon))
1372 cpu_relax();
1373 wr_regb(cons_uart, S3C2410_UTXH, c);
1374}
1375
1376#endif /* CONFIG_CONSOLE_POLL */
1377
b497549a
BD		 1378static void
1379s3c24xx_serial_console_putchar(struct uart_port *port, int ch)
1380{
1381 unsigned int ufcon = rd_regl(cons_uart, S3C2410_UFCON);
1382 while (!s3c24xx_serial_console_txrdy(port, ufcon))
1383 barrier();
1384 wr_regb(cons_uart, S3C2410_UTXH, ch);
1385}
1386
1387static void
1388s3c24xx_serial_console_write(struct console *co, const char *s,
1389 unsigned int count)
1390{
1391 uart_console_write(cons_uart, s, count, s3c24xx_serial_console_putchar);
1392}
1393
1394static void __init
1395s3c24xx_serial_get_options(struct uart_port *port, int *baud,
1396 int *parity, int *bits)
1397{
b497549a
BD		 1398 struct clk *clk;
1399 unsigned int ulcon;
1400 unsigned int ucon;
1401 unsigned int ubrdiv;
1402 unsigned long rate;
5f5a7a55
TA		 1403 unsigned int clk_sel;
1404 char clk_name[MAX_CLK_NAME_LENGTH];
b497549a
BD		 1405
1406 ulcon = rd_regl(port, S3C2410_ULCON);
1407 ucon = rd_regl(port, S3C2410_UCON);
1408 ubrdiv = rd_regl(port, S3C2410_UBRDIV);
1409
1410 dbg("s3c24xx_serial_get_options: port=%p\n"
1411 "registers: ulcon=%08x, ucon=%08x, ubdriv=%08x\n",
1412 port, ulcon, ucon, ubrdiv);
1413
1414 if ((ucon & 0xf) != 0) {
1415 /* consider the serial port configured if the tx/rx mode set */
1416
1417 switch (ulcon & S3C2410_LCON_CSMASK) {
1418 case S3C2410_LCON_CS5:
1419 *bits = 5;
1420 break;
1421 case S3C2410_LCON_CS6:
1422 *bits = 6;
1423 break;
1424 case S3C2410_LCON_CS7:
1425 *bits = 7;
1426 break;
1427 default:
1428 case S3C2410_LCON_CS8:
1429 *bits = 8;
1430 break;
1431 }
1432
1433 switch (ulcon & S3C2410_LCON_PMASK) {
1434 case S3C2410_LCON_PEVEN:
1435 *parity = 'e';
1436 break;
1437
1438 case S3C2410_LCON_PODD:
1439 *parity = 'o';
1440 break;
1441
1442 case S3C2410_LCON_PNONE:
1443 default:
1444 *parity = 'n';
1445 }
1446
1447 /* now calculate the baud rate */
1448
5f5a7a55
TA		 1449 clk_sel = s3c24xx_serial_getsource(port);
1450 sprintf(clk_name, "clk_uart_baud%d", clk_sel);
b497549a 1451
5f5a7a55 1452 clk = clk_get(port->dev, clk_name);
7cd88831 1453 if (!IS_ERR(clk))
5f5a7a55 1454 rate = clk_get_rate(clk);
b497549a
BD		 1455 else
1456 rate = 1;
1457
b497549a
BD		 1458 *baud = rate / (16 * (ubrdiv + 1));
1459 dbg("calculated baud %d\n", *baud);
1460 }
1461
1462}
1463
b497549a
BD		 1464static int __init
1465s3c24xx_serial_console_setup(struct console *co, char *options)
1466{
1467 struct uart_port *port;
1468 int baud = 9600;
1469 int bits = 8;
1470 int parity = 'n';
1471 int flow = 'n';
1472
1473 dbg("s3c24xx_serial_console_setup: co=%p (%d), %s\n",
1474 co, co->index, options);
1475
1476 /* is this a valid port */
1477
03d5e77b 1478 if (co->index == -1 || co->index >= CONFIG_SERIAL_SAMSUNG_UARTS)
b497549a
BD		 1479 co->index = 0;
1480
1481 port = &s3c24xx_serial_ports[co->index].port;
1482
1483 /* is the port configured? */
1484
ee430f16
TA		 1485 if (port->mapbase == 0x0)
1486 return -ENODEV;
b497549a
BD		 1487
1488 cons_uart = port;
1489
1490 dbg("s3c24xx_serial_console_setup: port=%p (%d)\n", port, co->index);
1491
1492 /*
1493 * Check whether an invalid uart number has been specified, and
1494 * if so, search for the first available port that does have
1495 * console support.
1496 */
1497 if (options)
1498 uart_parse_options(options, &baud, &parity, &bits, &flow);
1499 else
1500 s3c24xx_serial_get_options(port, &baud, &parity, &bits);
1501
1502 dbg("s3c24xx_serial_console_setup: baud %d\n", baud);
1503
1504 return uart_set_options(port, co, baud, parity, bits, flow);
1505}
1506
b497549a
BD		 1507static struct console s3c24xx_serial_console = {
1508 .name = S3C24XX_SERIAL_NAME,
1509 .device = uart_console_device,
1510 .flags = CON_PRINTBUFFER,
1511 .index = -1,
1512 .write = s3c24xx_serial_console_write,
5822a5df
TA		 1513 .setup = s3c24xx_serial_console_setup,
1514 .data = &s3c24xx_uart_drv,
b497549a 1515};
da121506
TA		 1516#endif /* CONFIG_SERIAL_SAMSUNG_CONSOLE */
1517
1518#ifdef CONFIG_CPU_S3C2410
1519static struct s3c24xx_serial_drv_data s3c2410_serial_drv_data = {
1520 .info = &(struct s3c24xx_uart_info) {
1521 .name = "Samsung S3C2410 UART",
1522 .type = PORT_S3C2410,
1523 .fifosize = 16,
1524 .rx_fifomask = S3C2410_UFSTAT_RXMASK,
1525 .rx_fifoshift = S3C2410_UFSTAT_RXSHIFT,
1526 .rx_fifofull = S3C2410_UFSTAT_RXFULL,
1527 .tx_fifofull = S3C2410_UFSTAT_TXFULL,
1528 .tx_fifomask = S3C2410_UFSTAT_TXMASK,
1529 .tx_fifoshift = S3C2410_UFSTAT_TXSHIFT,
1530 .def_clk_sel = S3C2410_UCON_CLKSEL0,
1531 .num_clks = 2,
1532 .clksel_mask = S3C2410_UCON_CLKMASK,
1533 .clksel_shift = S3C2410_UCON_CLKSHIFT,
1534 },
1535 .def_cfg = &(struct s3c2410_uartcfg) {
1536 .ucon = S3C2410_UCON_DEFAULT,
1537 .ufcon = S3C2410_UFCON_DEFAULT,
1538 },
1539};
1540#define S3C2410_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2410_serial_drv_data)
1541#else
1542#define S3C2410_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1543#endif
b497549a 1544
da121506
TA		 1545#ifdef CONFIG_CPU_S3C2412
1546static struct s3c24xx_serial_drv_data s3c2412_serial_drv_data = {
1547 .info = &(struct s3c24xx_uart_info) {
1548 .name = "Samsung S3C2412 UART",
1549 .type = PORT_S3C2412,
1550 .fifosize = 64,
1551 .has_divslot = 1,
1552 .rx_fifomask = S3C2440_UFSTAT_RXMASK,
1553 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
1554 .rx_fifofull = S3C2440_UFSTAT_RXFULL,
1555 .tx_fifofull = S3C2440_UFSTAT_TXFULL,
1556 .tx_fifomask = S3C2440_UFSTAT_TXMASK,
1557 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
1558 .def_clk_sel = S3C2410_UCON_CLKSEL2,
1559 .num_clks = 4,
1560 .clksel_mask = S3C2412_UCON_CLKMASK,
1561 .clksel_shift = S3C2412_UCON_CLKSHIFT,
1562 },
1563 .def_cfg = &(struct s3c2410_uartcfg) {
1564 .ucon = S3C2410_UCON_DEFAULT,
1565 .ufcon = S3C2410_UFCON_DEFAULT,
1566 },
1567};
1568#define S3C2412_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2412_serial_drv_data)
1569#else
1570#define S3C2412_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1571#endif
b497549a 1572
da121506 1573#if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2416) || \
b26469a8 1574 defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2442)
da121506
TA		 1575static struct s3c24xx_serial_drv_data s3c2440_serial_drv_data = {
1576 .info = &(struct s3c24xx_uart_info) {
1577 .name = "Samsung S3C2440 UART",
1578 .type = PORT_S3C2440,
1579 .fifosize = 64,
1580 .has_divslot = 1,
1581 .rx_fifomask = S3C2440_UFSTAT_RXMASK,
1582 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
1583 .rx_fifofull = S3C2440_UFSTAT_RXFULL,
1584 .tx_fifofull = S3C2440_UFSTAT_TXFULL,
1585 .tx_fifomask = S3C2440_UFSTAT_TXMASK,
1586 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
1587 .def_clk_sel = S3C2410_UCON_CLKSEL2,
1588 .num_clks = 4,
1589 .clksel_mask = S3C2412_UCON_CLKMASK,
1590 .clksel_shift = S3C2412_UCON_CLKSHIFT,
1591 },
1592 .def_cfg = &(struct s3c2410_uartcfg) {
1593 .ucon = S3C2410_UCON_DEFAULT,
1594 .ufcon = S3C2410_UFCON_DEFAULT,
1595 },
1596};
1597#define S3C2440_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2440_serial_drv_data)
1598#else
1599#define S3C2440_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1600#endif
b497549a 1601
da121506
TA		 1602#if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410) || \
1603 defined(CONFIG_CPU_S5P6440) || defined(CONFIG_CPU_S5P6450) || \
1604 defined(CONFIG_CPU_S5PC100)
1605static struct s3c24xx_serial_drv_data s3c6400_serial_drv_data = {
1606 .info = &(struct s3c24xx_uart_info) {
1607 .name = "Samsung S3C6400 UART",
1608 .type = PORT_S3C6400,
1609 .fifosize = 64,
1610 .has_divslot = 1,
1611 .rx_fifomask = S3C2440_UFSTAT_RXMASK,
1612 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
1613 .rx_fifofull = S3C2440_UFSTAT_RXFULL,
1614 .tx_fifofull = S3C2440_UFSTAT_TXFULL,
1615 .tx_fifomask = S3C2440_UFSTAT_TXMASK,
1616 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
1617 .def_clk_sel = S3C2410_UCON_CLKSEL2,
1618 .num_clks = 4,
1619 .clksel_mask = S3C6400_UCON_CLKMASK,
1620 .clksel_shift = S3C6400_UCON_CLKSHIFT,
1621 },
1622 .def_cfg = &(struct s3c2410_uartcfg) {
1623 .ucon = S3C2410_UCON_DEFAULT,
1624 .ufcon = S3C2410_UFCON_DEFAULT,
1625 },
1626};
1627#define S3C6400_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c6400_serial_drv_data)
1628#else
1629#define S3C6400_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1630#endif
b497549a 1631
da121506
TA		 1632#ifdef CONFIG_CPU_S5PV210
1633static struct s3c24xx_serial_drv_data s5pv210_serial_drv_data = {
1634 .info = &(struct s3c24xx_uart_info) {
1635 .name = "Samsung S5PV210 UART",
1636 .type = PORT_S3C6400,
1637 .has_divslot = 1,
1638 .rx_fifomask = S5PV210_UFSTAT_RXMASK,
1639 .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT,
1640 .rx_fifofull = S5PV210_UFSTAT_RXFULL,
1641 .tx_fifofull = S5PV210_UFSTAT_TXFULL,
1642 .tx_fifomask = S5PV210_UFSTAT_TXMASK,
1643 .tx_fifoshift = S5PV210_UFSTAT_TXSHIFT,
1644 .def_clk_sel = S3C2410_UCON_CLKSEL0,
1645 .num_clks = 2,
1646 .clksel_mask = S5PV210_UCON_CLKMASK,
1647 .clksel_shift = S5PV210_UCON_CLKSHIFT,
1648 },
1649 .def_cfg = &(struct s3c2410_uartcfg) {
1650 .ucon = S5PV210_UCON_DEFAULT,
1651 .ufcon = S5PV210_UFCON_DEFAULT,
1652 },
1653 .fifosize = { 256, 64, 16, 16 },
1654};
1655#define S5PV210_SERIAL_DRV_DATA ((kernel_ulong_t)&s5pv210_serial_drv_data)
1656#else
1657#define S5PV210_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1658#endif
b497549a 1659
5f7b6d19 1660#if defined(CONFIG_CPU_EXYNOS4210) || defined(CONFIG_SOC_EXYNOS4212) || \
2edb36c4
KK		 1661 defined(CONFIG_SOC_EXYNOS4412) || defined(CONFIG_SOC_EXYNOS5250) || \
1662 defined(CONFIG_SOC_EXYNOS5440)
da121506
TA		 1663static struct s3c24xx_serial_drv_data exynos4210_serial_drv_data = {
1664 .info = &(struct s3c24xx_uart_info) {
1665 .name = "Samsung Exynos4 UART",
1666 .type = PORT_S3C6400,
1667 .has_divslot = 1,
1668 .rx_fifomask = S5PV210_UFSTAT_RXMASK,
1669 .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT,
1670 .rx_fifofull = S5PV210_UFSTAT_RXFULL,
1671 .tx_fifofull = S5PV210_UFSTAT_TXFULL,
1672 .tx_fifomask = S5PV210_UFSTAT_TXMASK,
1673 .tx_fifoshift = S5PV210_UFSTAT_TXSHIFT,
1674 .def_clk_sel = S3C2410_UCON_CLKSEL0,
1675 .num_clks = 1,
1676 .clksel_mask = 0,
1677 .clksel_shift = 0,
1678 },
1679 .def_cfg = &(struct s3c2410_uartcfg) {
1680 .ucon = S5PV210_UCON_DEFAULT,
1681 .ufcon = S5PV210_UFCON_DEFAULT,
1682 .has_fracval = 1,
1683 },
1684 .fifosize = { 256, 64, 16, 16 },
1685};
1686#define EXYNOS4210_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos4210_serial_drv_data)
1687#else
1688#define EXYNOS4210_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1689#endif
b497549a 1690
da121506
TA		 1691static struct platform_device_id s3c24xx_serial_driver_ids[] = {
1692 {
1693 .name = "s3c2410-uart",
1694 .driver_data = S3C2410_SERIAL_DRV_DATA,
1695 }, {
1696 .name = "s3c2412-uart",
1697 .driver_data = S3C2412_SERIAL_DRV_DATA,
1698 }, {
1699 .name = "s3c2440-uart",
1700 .driver_data = S3C2440_SERIAL_DRV_DATA,
1701 }, {
1702 .name = "s3c6400-uart",
1703 .driver_data = S3C6400_SERIAL_DRV_DATA,
1704 }, {
1705 .name = "s5pv210-uart",
1706 .driver_data = S5PV210_SERIAL_DRV_DATA,
1707 }, {
1708 .name = "exynos4210-uart",
1709 .driver_data = EXYNOS4210_SERIAL_DRV_DATA,
1710 },
1711 { },
1712};
1713MODULE_DEVICE_TABLE(platform, s3c24xx_serial_driver_ids);
1714
26c919e1
TA		 1715#ifdef CONFIG_OF
1716static const struct of_device_id s3c24xx_uart_dt_match[] = {
666ca0b9
HS		 1717 { .compatible = "samsung,s3c2410-uart",
1718 .data = (void *)S3C2410_SERIAL_DRV_DATA },
1719 { .compatible = "samsung,s3c2412-uart",
1720 .data = (void *)S3C2412_SERIAL_DRV_DATA },
1721 { .compatible = "samsung,s3c2440-uart",
1722 .data = (void *)S3C2440_SERIAL_DRV_DATA },
1723 { .compatible = "samsung,s3c6400-uart",
1724 .data = (void *)S3C6400_SERIAL_DRV_DATA },
1725 { .compatible = "samsung,s5pv210-uart",
1726 .data = (void *)S5PV210_SERIAL_DRV_DATA },
26c919e1 1727 { .compatible = "samsung,exynos4210-uart",
a169a888 1728 .data = (void *)EXYNOS4210_SERIAL_DRV_DATA },
26c919e1
TA		 1729 {},
1730};
1731MODULE_DEVICE_TABLE(of, s3c24xx_uart_dt_match);
26c919e1
TA		 1732#endif
1733
da121506
TA		 1734static struct platform_driver samsung_serial_driver = {
1735 .probe = s3c24xx_serial_probe,
2d47b716 1736 .remove = s3c24xx_serial_remove,
da121506
TA		 1737 .id_table = s3c24xx_serial_driver_ids,
1738 .driver = {
1739 .name = "samsung-uart",
1740 .owner = THIS_MODULE,
1741 .pm = SERIAL_SAMSUNG_PM_OPS,
905f4ba2 1742 .of_match_table = of_match_ptr(s3c24xx_uart_dt_match),
da121506
TA		 1743 },
1744};
b497549a 1745
da121506 1746/* module initialisation code */
b497549a 1747
da121506
TA		 1748static int __init s3c24xx_serial_modinit(void)
1749{
1750 int ret;
1751
1752 ret = uart_register_driver(&s3c24xx_uart_drv);
1753 if (ret < 0) {
d20925e1 1754 pr_err("Failed to register Samsung UART driver\n");
e740d8f1 1755 return ret;
da121506
TA		 1756 }
1757
1758 return platform_driver_register(&samsung_serial_driver);
b497549a
BD		 1759}
1760
da121506
TA		 1761static void __exit s3c24xx_serial_modexit(void)
1762{
1763 uart_unregister_driver(&s3c24xx_uart_drv);
1764}
1765
1766module_init(s3c24xx_serial_modinit);
1767module_exit(s3c24xx_serial_modexit);
b497549a 1768
da121506 1769MODULE_ALIAS("platform:samsung-uart");
b497549a
BD		 1770MODULE_DESCRIPTION("Samsung SoC Serial port driver");
1771MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
1772MODULE_LICENSE("GPL v2");
Linux 6.x block layer and io_uring tree(s)