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serial: samsung: fix DMA mode enter condition for small FIFO sizes
[linux-block.git] / drivers / tty / serial / samsung.c
CommitLineData
99edb3d1 1/*
b497549a
BD		 2 * Driver core for Samsung SoC onboard UARTs.
3 *
ccae941e 4 * Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics
b497549a
BD		 5 * http://armlinux.simtec.co.uk/
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12/* Hote on 2410 error handling
13 *
14 * The s3c2410 manual has a love/hate affair with the contents of the
15 * UERSTAT register in the UART blocks, and keeps marking some of the
16 * error bits as reserved. Having checked with the s3c2410x01,
17 * it copes with BREAKs properly, so I am happy to ignore the RESERVED
18 * feature from the latter versions of the manual.
19 *
20 * If it becomes aparrent that latter versions of the 2410 remove these
21 * bits, then action will have to be taken to differentiate the versions
22 * and change the policy on BREAK
23 *
24 * BJD, 04-Nov-2004
25*/
26
27#if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
28#define SUPPORT_SYSRQ
29#endif
30
62c37eed
RB		 31#include <linux/dmaengine.h>
32#include <linux/dma-mapping.h>
33#include <linux/slab.h>
b497549a
BD		 34#include <linux/module.h>
35#include <linux/ioport.h>
36#include <linux/io.h>
37#include <linux/platform_device.h>
38#include <linux/init.h>
39#include <linux/sysrq.h>
40#include <linux/console.h>
41#include <linux/tty.h>
42#include <linux/tty_flip.h>
43#include <linux/serial_core.h>
44#include <linux/serial.h>
9ee51f01 45#include <linux/serial_s3c.h>
b497549a
BD		 46#include <linux/delay.h>
47#include <linux/clk.h>
30555476 48#include <linux/cpufreq.h>
26c919e1 49#include <linux/of.h>
b497549a
BD		 50
51#include <asm/irq.h>
52
b497549a
BD		 53#include "samsung.h"
54
e4ac92df 55#if defined(CONFIG_SERIAL_SAMSUNG_DEBUG) && \
e4ac92df
JP		 56 !defined(MODULE)
57
58extern void printascii(const char *);
59
60__printf(1, 2)
61static void dbg(const char *fmt, ...)
62{
63 va_list va;
64 char buff[256];
65
66 va_start(va, fmt);
a859c8b2 67 vscnprintf(buff, sizeof(buff), fmt, va);
e4ac92df
JP		 68 va_end(va);
69
70 printascii(buff);
71}
72
73#else
74#define dbg(fmt, ...) do { if (0) no_printk(fmt, ##__VA_ARGS__); } while (0)
75#endif
76
b497549a
BD		 77/* UART name and device definitions */
78
79#define S3C24XX_SERIAL_NAME "ttySAC"
80#define S3C24XX_SERIAL_MAJOR 204
81#define S3C24XX_SERIAL_MINOR 64
82
29bef799
RB		 83#define S3C24XX_TX_PIO 1
84#define S3C24XX_TX_DMA 2
b543c301
RB		 85#define S3C24XX_RX_PIO 1
86#define S3C24XX_RX_DMA 2
b497549a
BD		 87/* macros to change one thing to another */
88
89#define tx_enabled(port) ((port)->unused[0])
90#define rx_enabled(port) ((port)->unused[1])
91
25985edc 92/* flag to ignore all characters coming in */
b497549a
BD		 93#define RXSTAT_DUMMY_READ (0x10000000)
94
95static inline struct s3c24xx_uart_port *to_ourport(struct uart_port *port)
96{
97 return container_of(port, struct s3c24xx_uart_port, port);
98}
99
100/* translate a port to the device name */
101
102static inline const char *s3c24xx_serial_portname(struct uart_port *port)
103{
104 return to_platform_device(port->dev)->name;
105}
106
107static int s3c24xx_serial_txempty_nofifo(struct uart_port *port)
108{
9303ac15 109 return rd_regl(port, S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE;
b497549a
BD		 110}
111
88bb4ea1
TA		 112/*
113 * s3c64xx and later SoC's include the interrupt mask and status registers in
114 * the controller itself, unlike the s3c24xx SoC's which have these registers
115 * in the interrupt controller. Check if the port type is s3c64xx or higher.
116 */
117static int s3c24xx_serial_has_interrupt_mask(struct uart_port *port)
118{
119 return to_ourport(port)->info->type == PORT_S3C6400;
120}
121
b497549a
BD		 122static void s3c24xx_serial_rx_enable(struct uart_port *port)
123{
124 unsigned long flags;
125 unsigned int ucon, ufcon;
126 int count = 10000;
127
128 spin_lock_irqsave(&port->lock, flags);
129
130 while (--count && !s3c24xx_serial_txempty_nofifo(port))
131 udelay(100);
132
133 ufcon = rd_regl(port, S3C2410_UFCON);
134 ufcon |= S3C2410_UFCON_RESETRX;
135 wr_regl(port, S3C2410_UFCON, ufcon);
136
137 ucon = rd_regl(port, S3C2410_UCON);
138 ucon |= S3C2410_UCON_RXIRQMODE;
139 wr_regl(port, S3C2410_UCON, ucon);
140
141 rx_enabled(port) = 1;
142 spin_unlock_irqrestore(&port->lock, flags);
143}
144
145static void s3c24xx_serial_rx_disable(struct uart_port *port)
146{
147 unsigned long flags;
148 unsigned int ucon;
149
150 spin_lock_irqsave(&port->lock, flags);
151
152 ucon = rd_regl(port, S3C2410_UCON);
153 ucon &= ~S3C2410_UCON_RXIRQMODE;
154 wr_regl(port, S3C2410_UCON, ucon);
155
156 rx_enabled(port) = 0;
157 spin_unlock_irqrestore(&port->lock, flags);
158}
159
160static void s3c24xx_serial_stop_tx(struct uart_port *port)
161{
b73c289c 162 struct s3c24xx_uart_port *ourport = to_ourport(port);
29bef799
RB		 163 struct s3c24xx_uart_dma *dma = ourport->dma;
164 struct circ_buf *xmit = &port->state->xmit;
165 struct dma_tx_state state;
166 int count;
b73c289c 167
29bef799
RB		 168 if (!tx_enabled(port))
169 return;
170
171 if (s3c24xx_serial_has_interrupt_mask(port))
172 __set_bit(S3C64XX_UINTM_TXD,
173 portaddrl(port, S3C64XX_UINTM));
174 else
175 disable_irq_nosync(ourport->tx_irq);
176
177 if (dma && dma->tx_chan && ourport->tx_in_progress == S3C24XX_TX_DMA) {
178 dmaengine_pause(dma->tx_chan);
179 dmaengine_tx_status(dma->tx_chan, dma->tx_cookie, &state);
180 dmaengine_terminate_all(dma->tx_chan);
181 dma_sync_single_for_cpu(ourport->port.dev,
182 dma->tx_transfer_addr, dma->tx_size, DMA_TO_DEVICE);
183 async_tx_ack(dma->tx_desc);
184 count = dma->tx_bytes_requested - state.residue;
185 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
186 port->icount.tx += count;
b497549a 187 }
29bef799
RB		 188
189 tx_enabled(port) = 0;
190 ourport->tx_in_progress = 0;
191
192 if (port->flags & UPF_CONS_FLOW)
193 s3c24xx_serial_rx_enable(port);
194
195 ourport->tx_mode = 0;
196}
197
198static void s3c24xx_serial_start_next_tx(struct s3c24xx_uart_port *ourport);
199
200static void s3c24xx_serial_tx_dma_complete(void *args)
201{
202 struct s3c24xx_uart_port *ourport = args;
203 struct uart_port *port = &ourport->port;
204 struct circ_buf *xmit = &port->state->xmit;
205 struct s3c24xx_uart_dma *dma = ourport->dma;
206 struct dma_tx_state state;
207 unsigned long flags;
208 int count;
209
210
211 dmaengine_tx_status(dma->tx_chan, dma->tx_cookie, &state);
212 count = dma->tx_bytes_requested - state.residue;
213 async_tx_ack(dma->tx_desc);
214
215 dma_sync_single_for_cpu(ourport->port.dev, dma->tx_transfer_addr,
216 dma->tx_size, DMA_TO_DEVICE);
217
218 spin_lock_irqsave(&port->lock, flags);
219
220 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
221 port->icount.tx += count;
222 ourport->tx_in_progress = 0;
223
224 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
225 uart_write_wakeup(port);
226
227 s3c24xx_serial_start_next_tx(ourport);
228 spin_unlock_irqrestore(&port->lock, flags);
229}
230
231static void enable_tx_dma(struct s3c24xx_uart_port *ourport)
232{
233 struct uart_port *port = &ourport->port;
234 u32 ucon;
235
236 /* Mask Tx interrupt */
237 if (s3c24xx_serial_has_interrupt_mask(port))
238 __set_bit(S3C64XX_UINTM_TXD,
239 portaddrl(port, S3C64XX_UINTM));
240 else
241 disable_irq_nosync(ourport->tx_irq);
242
243 /* Enable tx dma mode */
244 ucon = rd_regl(port, S3C2410_UCON);
245 ucon &= ~(S3C64XX_UCON_TXBURST_MASK | S3C64XX_UCON_TXMODE_MASK);
246 ucon |= (dma_get_cache_alignment() >= 16) ?
247 S3C64XX_UCON_TXBURST_16 : S3C64XX_UCON_TXBURST_1;
248 ucon |= S3C64XX_UCON_TXMODE_DMA;
249 wr_regl(port, S3C2410_UCON, ucon);
250
251 ourport->tx_mode = S3C24XX_TX_DMA;
252}
253
254static void enable_tx_pio(struct s3c24xx_uart_port *ourport)
255{
256 struct uart_port *port = &ourport->port;
257 u32 ucon, ufcon;
258
259 /* Set ufcon txtrig */
260 ourport->tx_in_progress = S3C24XX_TX_PIO;
261 ufcon = rd_regl(port, S3C2410_UFCON);
262 wr_regl(port, S3C2410_UFCON, ufcon);
263
264 /* Enable tx pio mode */
265 ucon = rd_regl(port, S3C2410_UCON);
266 ucon &= ~(S3C64XX_UCON_TXMODE_MASK);
267 ucon |= S3C64XX_UCON_TXMODE_CPU;
268 wr_regl(port, S3C2410_UCON, ucon);
269
270 /* Unmask Tx interrupt */
271 if (s3c24xx_serial_has_interrupt_mask(port))
272 __clear_bit(S3C64XX_UINTM_TXD,
273 portaddrl(port, S3C64XX_UINTM));
274 else
275 enable_irq(ourport->tx_irq);
276
277 ourport->tx_mode = S3C24XX_TX_PIO;
278}
279
280static void s3c24xx_serial_start_tx_pio(struct s3c24xx_uart_port *ourport)
281{
282 if (ourport->tx_mode != S3C24XX_TX_PIO)
283 enable_tx_pio(ourport);
b497549a
BD		 284}
285
29bef799
RB		 286static int s3c24xx_serial_start_tx_dma(struct s3c24xx_uart_port *ourport,
287 unsigned int count)
288{
289 struct uart_port *port = &ourport->port;
290 struct circ_buf *xmit = &port->state->xmit;
291 struct s3c24xx_uart_dma *dma = ourport->dma;
292
293
294 if (ourport->tx_mode != S3C24XX_TX_DMA)
295 enable_tx_dma(ourport);
296
297 while (xmit->tail & (dma_get_cache_alignment() - 1)) {
298 if (rd_regl(port, S3C2410_UFSTAT) & ourport->info->tx_fifofull)
299 return 0;
300 wr_regb(port, S3C2410_UTXH, xmit->buf[xmit->tail]);
301 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
302 port->icount.tx++;
303 count--;
304 }
305
306 dma->tx_size = count & ~(dma_get_cache_alignment() - 1);
307 dma->tx_transfer_addr = dma->tx_addr + xmit->tail;
308
309 dma_sync_single_for_device(ourport->port.dev, dma->tx_transfer_addr,
310 dma->tx_size, DMA_TO_DEVICE);
311
312 dma->tx_desc = dmaengine_prep_slave_single(dma->tx_chan,
313 dma->tx_transfer_addr, dma->tx_size,
314 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
315 if (!dma->tx_desc) {
316 dev_err(ourport->port.dev, "Unable to get desc for Tx\n");
317 return -EIO;
318 }
319
320 dma->tx_desc->callback = s3c24xx_serial_tx_dma_complete;
321 dma->tx_desc->callback_param = ourport;
322 dma->tx_bytes_requested = dma->tx_size;
323
324 ourport->tx_in_progress = S3C24XX_TX_DMA;
325 dma->tx_cookie = dmaengine_submit(dma->tx_desc);
326 dma_async_issue_pending(dma->tx_chan);
327 return 0;
328}
329
330static void s3c24xx_serial_start_next_tx(struct s3c24xx_uart_port *ourport)
331{
332 struct uart_port *port = &ourport->port;
333 struct circ_buf *xmit = &port->state->xmit;
334 unsigned long count;
335
336 /* Get data size up to the end of buffer */
337 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
338
339 if (!count) {
340 s3c24xx_serial_stop_tx(port);
341 return;
342 }
343
81ccb2a6
MS		 344 if (!ourport->dma || !ourport->dma->tx_chan ||
345 count < ourport->min_dma_size)
29bef799
RB		 346 s3c24xx_serial_start_tx_pio(ourport);
347 else
348 s3c24xx_serial_start_tx_dma(ourport, count);
349}
350
75781979 351static void s3c24xx_serial_start_tx(struct uart_port *port)
b497549a 352{
b73c289c 353 struct s3c24xx_uart_port *ourport = to_ourport(port);
29bef799 354 struct circ_buf *xmit = &port->state->xmit;
b73c289c 355
b497549a
BD		 356 if (!tx_enabled(port)) {
357 if (port->flags & UPF_CONS_FLOW)
358 s3c24xx_serial_rx_disable(port);
359
b497549a 360 tx_enabled(port) = 1;
ba019a3e 361 if (!ourport->dma || !ourport->dma->tx_chan)
29bef799 362 s3c24xx_serial_start_tx_pio(ourport);
29bef799
RB		 363 }
364
365 if (ourport->dma && ourport->dma->tx_chan) {
366 if (!uart_circ_empty(xmit) && !ourport->tx_in_progress)
367 s3c24xx_serial_start_next_tx(ourport);
b497549a
BD		 368 }
369}
370
b543c301
RB		 371static void s3c24xx_uart_copy_rx_to_tty(struct s3c24xx_uart_port *ourport,
372 struct tty_port *tty, int count)
373{
374 struct s3c24xx_uart_dma *dma = ourport->dma;
375 int copied;
376
377 if (!count)
378 return;
379
380 dma_sync_single_for_cpu(ourport->port.dev, dma->rx_addr,
381 dma->rx_size, DMA_FROM_DEVICE);
382
383 ourport->port.icount.rx += count;
384 if (!tty) {
385 dev_err(ourport->port.dev, "No tty port\n");
386 return;
387 }
388 copied = tty_insert_flip_string(tty,
389 ((unsigned char *)(ourport->dma->rx_buf)), count);
390 if (copied != count) {
391 WARN_ON(1);
392 dev_err(ourport->port.dev, "RxData copy to tty layer failed\n");
393 }
394}
395
396static int s3c24xx_serial_rx_fifocnt(struct s3c24xx_uart_port *ourport,
397 unsigned long ufstat);
398
399static void uart_rx_drain_fifo(struct s3c24xx_uart_port *ourport)
400{
401 struct uart_port *port = &ourport->port;
402 struct tty_port *tty = &port->state->port;
403 unsigned int ch, ufstat;
404 unsigned int count;
405
406 ufstat = rd_regl(port, S3C2410_UFSTAT);
407 count = s3c24xx_serial_rx_fifocnt(ourport, ufstat);
408
409 if (!count)
410 return;
411
412 while (count-- > 0) {
413 ch = rd_regb(port, S3C2410_URXH);
414
415 ourport->port.icount.rx++;
416 tty_insert_flip_char(tty, ch, TTY_NORMAL);
417 }
418
419 tty_flip_buffer_push(tty);
420}
421
b497549a
BD		 422static void s3c24xx_serial_stop_rx(struct uart_port *port)
423{
b73c289c 424 struct s3c24xx_uart_port *ourport = to_ourport(port);
b543c301
RB		 425 struct s3c24xx_uart_dma *dma = ourport->dma;
426 struct tty_port *t = &port->state->port;
427 struct dma_tx_state state;
428 enum dma_status dma_status;
429 unsigned int received;
b73c289c 430
b497549a
BD		 431 if (rx_enabled(port)) {
432 dbg("s3c24xx_serial_stop_rx: port=%p\n", port);
88bb4ea1
TA		 433 if (s3c24xx_serial_has_interrupt_mask(port))
434 __set_bit(S3C64XX_UINTM_RXD,
435 portaddrl(port, S3C64XX_UINTM));
436 else
437 disable_irq_nosync(ourport->rx_irq);
b497549a
BD		 438 rx_enabled(port) = 0;
439 }
b543c301
RB		 440 if (dma && dma->rx_chan) {
441 dmaengine_pause(dma->tx_chan);
442 dma_status = dmaengine_tx_status(dma->rx_chan,
443 dma->rx_cookie, &state);
444 if (dma_status == DMA_IN_PROGRESS ||
445 dma_status == DMA_PAUSED) {
446 received = dma->rx_bytes_requested - state.residue;
447 dmaengine_terminate_all(dma->rx_chan);
448 s3c24xx_uart_copy_rx_to_tty(ourport, t, received);
449 }
450 }
b497549a
BD		 451}
452
ef4aca70
RB		 453static inline struct s3c24xx_uart_info
454 *s3c24xx_port_to_info(struct uart_port *port)
b497549a
BD		 455{
456 return to_ourport(port)->info;
457}
458
ef4aca70
RB		 459static inline struct s3c2410_uartcfg
460 *s3c24xx_port_to_cfg(struct uart_port *port)
b497549a 461{
4d84e970
TA		 462 struct s3c24xx_uart_port *ourport;
463
b497549a
BD		 464 if (port->dev == NULL)
465 return NULL;
466
4d84e970
TA		 467 ourport = container_of(port, struct s3c24xx_uart_port, port);
468 return ourport->cfg;
b497549a
BD		 469}
470
471static int s3c24xx_serial_rx_fifocnt(struct s3c24xx_uart_port *ourport,
472 unsigned long ufstat)
473{
474 struct s3c24xx_uart_info *info = ourport->info;
475
476 if (ufstat & info->rx_fifofull)
da121506 477 return ourport->port.fifosize;
b497549a
BD		 478
479 return (ufstat & info->rx_fifomask) >> info->rx_fifoshift;
480}
481
b543c301
RB		 482static void s3c64xx_start_rx_dma(struct s3c24xx_uart_port *ourport);
483static void s3c24xx_serial_rx_dma_complete(void *args)
484{
485 struct s3c24xx_uart_port *ourport = args;
486 struct uart_port *port = &ourport->port;
487
488 struct s3c24xx_uart_dma *dma = ourport->dma;
489 struct tty_port *t = &port->state->port;
490 struct tty_struct *tty = tty_port_tty_get(&ourport->port.state->port);
491
492 struct dma_tx_state state;
493 unsigned long flags;
494 int received;
495
496 dmaengine_tx_status(dma->rx_chan, dma->rx_cookie, &state);
497 received = dma->rx_bytes_requested - state.residue;
498 async_tx_ack(dma->rx_desc);
499
500 spin_lock_irqsave(&port->lock, flags);
501
502 if (received)
503 s3c24xx_uart_copy_rx_to_tty(ourport, t, received);
504
505 if (tty) {
506 tty_flip_buffer_push(t);
507 tty_kref_put(tty);
508 }
509
510 s3c64xx_start_rx_dma(ourport);
511
512 spin_unlock_irqrestore(&port->lock, flags);
513}
514
515static void s3c64xx_start_rx_dma(struct s3c24xx_uart_port *ourport)
516{
517 struct s3c24xx_uart_dma *dma = ourport->dma;
518
519 dma_sync_single_for_device(ourport->port.dev, dma->rx_addr,
520 dma->rx_size, DMA_FROM_DEVICE);
521
522 dma->rx_desc = dmaengine_prep_slave_single(dma->rx_chan,
523 dma->rx_addr, dma->rx_size, DMA_DEV_TO_MEM,
524 DMA_PREP_INTERRUPT);
525 if (!dma->rx_desc) {
526 dev_err(ourport->port.dev, "Unable to get desc for Rx\n");
527 return;
528 }
529
530 dma->rx_desc->callback = s3c24xx_serial_rx_dma_complete;
531 dma->rx_desc->callback_param = ourport;
532 dma->rx_bytes_requested = dma->rx_size;
533
534 dma->rx_cookie = dmaengine_submit(dma->rx_desc);
535 dma_async_issue_pending(dma->rx_chan);
536}
b497549a
BD		 537
538/* ? - where has parity gone?? */
539#define S3C2410_UERSTAT_PARITY (0x1000)
540
b543c301
RB		 541static void enable_rx_dma(struct s3c24xx_uart_port *ourport)
542{
543 struct uart_port *port = &ourport->port;
544 unsigned int ucon;
545
546 /* set Rx mode to DMA mode */
547 ucon = rd_regl(port, S3C2410_UCON);
548 ucon &= ~(S3C64XX_UCON_RXBURST_MASK |
549 S3C64XX_UCON_TIMEOUT_MASK |
550 S3C64XX_UCON_EMPTYINT_EN |
551 S3C64XX_UCON_DMASUS_EN |
552 S3C64XX_UCON_TIMEOUT_EN |
553 S3C64XX_UCON_RXMODE_MASK);
554 ucon |= S3C64XX_UCON_RXBURST_16 |
555 0xf << S3C64XX_UCON_TIMEOUT_SHIFT |
556 S3C64XX_UCON_EMPTYINT_EN |
557 S3C64XX_UCON_TIMEOUT_EN |
558 S3C64XX_UCON_RXMODE_DMA;
559 wr_regl(port, S3C2410_UCON, ucon);
560
561 ourport->rx_mode = S3C24XX_RX_DMA;
562}
563
564static void enable_rx_pio(struct s3c24xx_uart_port *ourport)
565{
566 struct uart_port *port = &ourport->port;
567 unsigned int ucon;
568
569 /* set Rx mode to DMA mode */
570 ucon = rd_regl(port, S3C2410_UCON);
571 ucon &= ~(S3C64XX_UCON_TIMEOUT_MASK |
572 S3C64XX_UCON_EMPTYINT_EN |
573 S3C64XX_UCON_DMASUS_EN |
574 S3C64XX_UCON_TIMEOUT_EN |
575 S3C64XX_UCON_RXMODE_MASK);
576 ucon |= 0xf << S3C64XX_UCON_TIMEOUT_SHIFT |
577 S3C64XX_UCON_TIMEOUT_EN |
578 S3C64XX_UCON_RXMODE_CPU;
579 wr_regl(port, S3C2410_UCON, ucon);
580
581 ourport->rx_mode = S3C24XX_RX_PIO;
582}
583
584static irqreturn_t s3c24xx_serial_rx_chars_dma(int irq, void *dev_id)
585{
586 unsigned int utrstat, ufstat, received;
587 struct s3c24xx_uart_port *ourport = dev_id;
588 struct uart_port *port = &ourport->port;
589 struct s3c24xx_uart_dma *dma = ourport->dma;
590 struct tty_struct *tty = tty_port_tty_get(&ourport->port.state->port);
591 struct tty_port *t = &port->state->port;
592 unsigned long flags;
593 struct dma_tx_state state;
594
595 utrstat = rd_regl(port, S3C2410_UTRSTAT);
596 ufstat = rd_regl(port, S3C2410_UFSTAT);
597
598 spin_lock_irqsave(&port->lock, flags);
599
600 if (!(utrstat & S3C2410_UTRSTAT_TIMEOUT)) {
601 s3c64xx_start_rx_dma(ourport);
602 if (ourport->rx_mode == S3C24XX_RX_PIO)
603 enable_rx_dma(ourport);
604 goto finish;
605 }
606
607 if (ourport->rx_mode == S3C24XX_RX_DMA) {
608 dmaengine_pause(dma->rx_chan);
609 dmaengine_tx_status(dma->rx_chan, dma->rx_cookie, &state);
610 dmaengine_terminate_all(dma->rx_chan);
611 received = dma->rx_bytes_requested - state.residue;
612 s3c24xx_uart_copy_rx_to_tty(ourport, t, received);
613
614 enable_rx_pio(ourport);
615 }
616
617 uart_rx_drain_fifo(ourport);
618
619 if (tty) {
620 tty_flip_buffer_push(t);
621 tty_kref_put(tty);
622 }
623
624 wr_regl(port, S3C2410_UTRSTAT, S3C2410_UTRSTAT_TIMEOUT);
625
626finish:
627 spin_unlock_irqrestore(&port->lock, flags);
628
629 return IRQ_HANDLED;
630}
631
632static irqreturn_t s3c24xx_serial_rx_chars_pio(int irq, void *dev_id)
b497549a
BD		 633{
634 struct s3c24xx_uart_port *ourport = dev_id;
635 struct uart_port *port = &ourport->port;
b497549a 636 unsigned int ufcon, ch, flag, ufstat, uerstat;
c15c3747 637 unsigned long flags;
57850a50 638 int max_count = port->fifosize;
b497549a 639
c15c3747
TA		 640 spin_lock_irqsave(&port->lock, flags);
641
b497549a
BD		 642 while (max_count-- > 0) {
643 ufcon = rd_regl(port, S3C2410_UFCON);
644 ufstat = rd_regl(port, S3C2410_UFSTAT);
645
646 if (s3c24xx_serial_rx_fifocnt(ourport, ufstat) == 0)
647 break;
648
649 uerstat = rd_regl(port, S3C2410_UERSTAT);
650 ch = rd_regb(port, S3C2410_URXH);
651
652 if (port->flags & UPF_CONS_FLOW) {
653 int txe = s3c24xx_serial_txempty_nofifo(port);
654
655 if (rx_enabled(port)) {
656 if (!txe) {
657 rx_enabled(port) = 0;
658 continue;
659 }
660 } else {
661 if (txe) {
662 ufcon |= S3C2410_UFCON_RESETRX;
663 wr_regl(port, S3C2410_UFCON, ufcon);
664 rx_enabled(port) = 1;
f5693ea2
VK		 665 spin_unlock_irqrestore(&port->lock,
666 flags);
b497549a
BD		 667 goto out;
668 }
669 continue;
670 }
671 }
672
673 /* insert the character into the buffer */
674
675 flag = TTY_NORMAL;
676 port->icount.rx++;
677
678 if (unlikely(uerstat & S3C2410_UERSTAT_ANY)) {
679 dbg("rxerr: port ch=0x%02x, rxs=0x%08x\n",
680 ch, uerstat);
681
682 /* check for break */
683 if (uerstat & S3C2410_UERSTAT_BREAK) {
684 dbg("break!\n");
685 port->icount.brk++;
686 if (uart_handle_break(port))
9303ac15 687 goto ignore_char;
b497549a
BD		 688 }
689
690 if (uerstat & S3C2410_UERSTAT_FRAME)
691 port->icount.frame++;
692 if (uerstat & S3C2410_UERSTAT_OVERRUN)
693 port->icount.overrun++;
694
695 uerstat &= port->read_status_mask;
696
697 if (uerstat & S3C2410_UERSTAT_BREAK)
698 flag = TTY_BREAK;
699 else if (uerstat & S3C2410_UERSTAT_PARITY)
700 flag = TTY_PARITY;
701 else if (uerstat & (S3C2410_UERSTAT_FRAME |
702 S3C2410_UERSTAT_OVERRUN))
703 flag = TTY_FRAME;
704 }
705
706 if (uart_handle_sysrq_char(port, ch))
707 goto ignore_char;
708
709 uart_insert_char(port, uerstat, S3C2410_UERSTAT_OVERRUN,
710 ch, flag);
711
ef4aca70 712ignore_char:
b497549a
BD		 713 continue;
714 }
f5693ea2
VK		 715
716 spin_unlock_irqrestore(&port->lock, flags);
2e124b4a 717 tty_flip_buffer_push(&port->state->port);
b497549a 718
ef4aca70 719out:
b497549a
BD		 720 return IRQ_HANDLED;
721}
722
b543c301
RB		 723
724static irqreturn_t s3c24xx_serial_rx_chars(int irq, void *dev_id)
725{
726 struct s3c24xx_uart_port *ourport = dev_id;
727
728 if (ourport->dma && ourport->dma->rx_chan)
729 return s3c24xx_serial_rx_chars_dma(irq, dev_id);
730 return s3c24xx_serial_rx_chars_pio(irq, dev_id);
731}
732
b497549a
BD		 733static irqreturn_t s3c24xx_serial_tx_chars(int irq, void *id)
734{
735 struct s3c24xx_uart_port *ourport = id;
736 struct uart_port *port = &ourport->port;
ebd2c8f6 737 struct circ_buf *xmit = &port->state->xmit;
c15c3747 738 unsigned long flags;
29bef799 739 int count;
b497549a 740
c15c3747
TA		 741 spin_lock_irqsave(&port->lock, flags);
742
29bef799
RB		 743 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
744
81ccb2a6
MS		 745 if (ourport->dma && ourport->dma->tx_chan &&
746 count >= ourport->min_dma_size) {
29bef799
RB		 747 s3c24xx_serial_start_tx_dma(ourport, count);
748 goto out;
749 }
750
b497549a
BD		 751 if (port->x_char) {
752 wr_regb(port, S3C2410_UTXH, port->x_char);
753 port->icount.tx++;
754 port->x_char = 0;
755 goto out;
756 }
757
25985edc 758 /* if there isn't anything more to transmit, or the uart is now
b497549a
BD		 759 * stopped, disable the uart and exit
760 */
761
762 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
763 s3c24xx_serial_stop_tx(port);
764 goto out;
765 }
766
767 /* try and drain the buffer... */
768
29bef799 769 count = port->fifosize;
b497549a
BD		 770 while (!uart_circ_empty(xmit) && count-- > 0) {
771 if (rd_regl(port, S3C2410_UFSTAT) & ourport->info->tx_fifofull)
772 break;
773
774 wr_regb(port, S3C2410_UTXH, xmit->buf[xmit->tail]);
775 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
776 port->icount.tx++;
777 }
778
c15c3747
TA		 779 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) {
780 spin_unlock(&port->lock);
b497549a 781 uart_write_wakeup(port);
c15c3747
TA		 782 spin_lock(&port->lock);
783 }
b497549a
BD		 784
785 if (uart_circ_empty(xmit))
786 s3c24xx_serial_stop_tx(port);
787
ef4aca70 788out:
c15c3747 789 spin_unlock_irqrestore(&port->lock, flags);
b497549a
BD		 790 return IRQ_HANDLED;
791}
792
88bb4ea1
TA		 793/* interrupt handler for s3c64xx and later SoC's.*/
794static irqreturn_t s3c64xx_serial_handle_irq(int irq, void *id)
795{
796 struct s3c24xx_uart_port *ourport = id;
797 struct uart_port *port = &ourport->port;
798 unsigned int pend = rd_regl(port, S3C64XX_UINTP);
88bb4ea1
TA		 799 irqreturn_t ret = IRQ_HANDLED;
800
88bb4ea1
TA		 801 if (pend & S3C64XX_UINTM_RXD_MSK) {
802 ret = s3c24xx_serial_rx_chars(irq, id);
803 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_RXD_MSK);
804 }
805 if (pend & S3C64XX_UINTM_TXD_MSK) {
806 ret = s3c24xx_serial_tx_chars(irq, id);
807 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_TXD_MSK);
808 }
88bb4ea1
TA		 809 return ret;
810}
811
b497549a
BD		 812static unsigned int s3c24xx_serial_tx_empty(struct uart_port *port)
813{
814 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
815 unsigned long ufstat = rd_regl(port, S3C2410_UFSTAT);
816 unsigned long ufcon = rd_regl(port, S3C2410_UFCON);
817
818 if (ufcon & S3C2410_UFCON_FIFOMODE) {
819 if ((ufstat & info->tx_fifomask) != 0 ||
820 (ufstat & info->tx_fifofull))
821 return 0;
822
823 return 1;
824 }
825
826 return s3c24xx_serial_txempty_nofifo(port);
827}
828
829/* no modem control lines */
830static unsigned int s3c24xx_serial_get_mctrl(struct uart_port *port)
831{
832 unsigned int umstat = rd_regb(port, S3C2410_UMSTAT);
833
834 if (umstat & S3C2410_UMSTAT_CTS)
835 return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
836 else
837 return TIOCM_CAR | TIOCM_DSR;
838}
839
840static void s3c24xx_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
841{
2d1e5a48
JMG		 842 unsigned int umcon = rd_regl(port, S3C2410_UMCON);
843
844 if (mctrl & TIOCM_RTS)
845 umcon |= S3C2410_UMCOM_RTS_LOW;
846 else
847 umcon &= ~S3C2410_UMCOM_RTS_LOW;
848
849 wr_regl(port, S3C2410_UMCON, umcon);
b497549a
BD		 850}
851
852static void s3c24xx_serial_break_ctl(struct uart_port *port, int break_state)
853{
854 unsigned long flags;
855 unsigned int ucon;
856
857 spin_lock_irqsave(&port->lock, flags);
858
859 ucon = rd_regl(port, S3C2410_UCON);
860
861 if (break_state)
862 ucon |= S3C2410_UCON_SBREAK;
863 else
864 ucon &= ~S3C2410_UCON_SBREAK;
865
866 wr_regl(port, S3C2410_UCON, ucon);
867
868 spin_unlock_irqrestore(&port->lock, flags);
869}
870
62c37eed
RB		 871static int s3c24xx_serial_request_dma(struct s3c24xx_uart_port *p)
872{
873 struct s3c24xx_uart_dma *dma = p->dma;
874 dma_cap_mask_t mask;
875 unsigned long flags;
876
877 /* Default slave configuration parameters */
878 dma->rx_conf.direction = DMA_DEV_TO_MEM;
879 dma->rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
880 dma->rx_conf.src_addr = p->port.mapbase + S3C2410_URXH;
881 dma->rx_conf.src_maxburst = 16;
882
883 dma->tx_conf.direction = DMA_MEM_TO_DEV;
884 dma->tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
885 dma->tx_conf.dst_addr = p->port.mapbase + S3C2410_UTXH;
886 if (dma_get_cache_alignment() >= 16)
887 dma->tx_conf.dst_maxburst = 16;
888 else
889 dma->tx_conf.dst_maxburst = 1;
890
891 dma_cap_zero(mask);
892 dma_cap_set(DMA_SLAVE, mask);
893
894 dma->rx_chan = dma_request_slave_channel_compat(mask, dma->fn,
895 dma->rx_param, p->port.dev, "rx");
896 if (!dma->rx_chan)
897 return -ENODEV;
898
899 dmaengine_slave_config(dma->rx_chan, &dma->rx_conf);
900
901 dma->tx_chan = dma_request_slave_channel_compat(mask, dma->fn,
902 dma->tx_param, p->port.dev, "tx");
903 if (!dma->tx_chan) {
904 dma_release_channel(dma->rx_chan);
905 return -ENODEV;
906 }
907
908 dmaengine_slave_config(dma->tx_chan, &dma->tx_conf);
909
910 /* RX buffer */
911 dma->rx_size = PAGE_SIZE;
912
913 dma->rx_buf = kmalloc(dma->rx_size, GFP_KERNEL);
914
915 if (!dma->rx_buf) {
916 dma_release_channel(dma->rx_chan);
917 dma_release_channel(dma->tx_chan);
918 return -ENOMEM;
919 }
920
921 dma->rx_addr = dma_map_single(dma->rx_chan->device->dev, dma->rx_buf,
922 dma->rx_size, DMA_FROM_DEVICE);
923
924 spin_lock_irqsave(&p->port.lock, flags);
925
926 /* TX buffer */
927 dma->tx_addr = dma_map_single(dma->tx_chan->device->dev,
928 p->port.state->xmit.buf,
929 UART_XMIT_SIZE, DMA_TO_DEVICE);
930
931 spin_unlock_irqrestore(&p->port.lock, flags);
932
933 return 0;
934}
935
936static void s3c24xx_serial_release_dma(struct s3c24xx_uart_port *p)
937{
938 struct s3c24xx_uart_dma *dma = p->dma;
939
940 if (dma->rx_chan) {
941 dmaengine_terminate_all(dma->rx_chan);
942 dma_unmap_single(dma->rx_chan->device->dev, dma->rx_addr,
943 dma->rx_size, DMA_FROM_DEVICE);
944 kfree(dma->rx_buf);
945 dma_release_channel(dma->rx_chan);
946 dma->rx_chan = NULL;
947 }
948
949 if (dma->tx_chan) {
950 dmaengine_terminate_all(dma->tx_chan);
951 dma_unmap_single(dma->tx_chan->device->dev, dma->tx_addr,
952 UART_XMIT_SIZE, DMA_TO_DEVICE);
953 dma_release_channel(dma->tx_chan);
954 dma->tx_chan = NULL;
955 }
956}
957
b497549a
BD		 958static void s3c24xx_serial_shutdown(struct uart_port *port)
959{
960 struct s3c24xx_uart_port *ourport = to_ourport(port);
961
962 if (ourport->tx_claimed) {
88bb4ea1
TA		 963 if (!s3c24xx_serial_has_interrupt_mask(port))
964 free_irq(ourport->tx_irq, ourport);
b497549a
BD		 965 tx_enabled(port) = 0;
966 ourport->tx_claimed = 0;
e91d863d 967 ourport->tx_mode = 0;
b497549a
BD		 968 }
969
970 if (ourport->rx_claimed) {
88bb4ea1
TA		 971 if (!s3c24xx_serial_has_interrupt_mask(port))
972 free_irq(ourport->rx_irq, ourport);
b497549a
BD		 973 ourport->rx_claimed = 0;
974 rx_enabled(port) = 0;
975 }
b497549a 976
88bb4ea1
TA		 977 /* Clear pending interrupts and mask all interrupts */
978 if (s3c24xx_serial_has_interrupt_mask(port)) {
b6ad2935
TF		 979 free_irq(port->irq, ourport);
980
88bb4ea1
TA		 981 wr_regl(port, S3C64XX_UINTP, 0xf);
982 wr_regl(port, S3C64XX_UINTM, 0xf);
983 }
62c37eed
RB		 984
985 if (ourport->dma)
986 s3c24xx_serial_release_dma(ourport);
987
29bef799 988 ourport->tx_in_progress = 0;
88bb4ea1 989}
b497549a
BD		 990
991static int s3c24xx_serial_startup(struct uart_port *port)
992{
993 struct s3c24xx_uart_port *ourport = to_ourport(port);
994 int ret;
995
e4ac92df
JP		 996 dbg("s3c24xx_serial_startup: port=%p (%08llx,%p)\n",
997 port, (unsigned long long)port->mapbase, port->membase);
b497549a
BD		 998
999 rx_enabled(port) = 1;
1000
b73c289c 1001 ret = request_irq(ourport->rx_irq, s3c24xx_serial_rx_chars, 0,
b497549a
BD		 1002 s3c24xx_serial_portname(port), ourport);
1003
1004 if (ret != 0) {
d20925e1 1005 dev_err(port->dev, "cannot get irq %d\n", ourport->rx_irq);
b497549a
BD		 1006 return ret;
1007 }
1008
1009 ourport->rx_claimed = 1;
1010
1011 dbg("requesting tx irq...\n");
1012
1013 tx_enabled(port) = 1;
1014
b73c289c 1015 ret = request_irq(ourport->tx_irq, s3c24xx_serial_tx_chars, 0,
b497549a
BD		 1016 s3c24xx_serial_portname(port), ourport);
1017
1018 if (ret) {
d20925e1 1019 dev_err(port->dev, "cannot get irq %d\n", ourport->tx_irq);
b497549a
BD		 1020 goto err;
1021 }
1022
1023 ourport->tx_claimed = 1;
1024
1025 dbg("s3c24xx_serial_startup ok\n");
1026
1027 /* the port reset code should have done the correct
1028 * register setup for the port controls */
1029
1030 return ret;
1031
ef4aca70 1032err:
b497549a
BD		 1033 s3c24xx_serial_shutdown(port);
1034 return ret;
1035}
1036
88bb4ea1
TA		 1037static int s3c64xx_serial_startup(struct uart_port *port)
1038{
1039 struct s3c24xx_uart_port *ourport = to_ourport(port);
b543c301
RB		 1040 unsigned long flags;
1041 unsigned int ufcon;
88bb4ea1
TA		 1042 int ret;
1043
e4ac92df
JP		 1044 dbg("s3c64xx_serial_startup: port=%p (%08llx,%p)\n",
1045 port, (unsigned long long)port->mapbase, port->membase);
88bb4ea1 1046
b6ad2935 1047 wr_regl(port, S3C64XX_UINTM, 0xf);
62c37eed
RB		 1048 if (ourport->dma) {
1049 ret = s3c24xx_serial_request_dma(ourport);
1050 if (ret < 0) {
1051 dev_warn(port->dev, "DMA request failed\n");
1052 return ret;
1053 }
1054 }
b6ad2935 1055
88bb4ea1
TA		 1056 ret = request_irq(port->irq, s3c64xx_serial_handle_irq, IRQF_SHARED,
1057 s3c24xx_serial_portname(port), ourport);
1058 if (ret) {
d20925e1 1059 dev_err(port->dev, "cannot get irq %d\n", port->irq);
88bb4ea1
TA		 1060 return ret;
1061 }
1062
1063 /* For compatibility with s3c24xx Soc's */
1064 rx_enabled(port) = 1;
1065 ourport->rx_claimed = 1;
1066 tx_enabled(port) = 0;
1067 ourport->tx_claimed = 1;
1068
29bef799
RB		 1069 spin_lock_irqsave(&port->lock, flags);
1070
1071 ufcon = rd_regl(port, S3C2410_UFCON);
31c6ba97
RB		 1072 ufcon |= S3C2410_UFCON_RESETRX | S5PV210_UFCON_RXTRIG8;
1073 if (!uart_console(port))
1074 ufcon |= S3C2410_UFCON_RESETTX;
29bef799
RB		 1075 wr_regl(port, S3C2410_UFCON, ufcon);
1076
1077 enable_rx_pio(ourport);
1078
1079 spin_unlock_irqrestore(&port->lock, flags);
1080
88bb4ea1
TA		 1081 /* Enable Rx Interrupt */
1082 __clear_bit(S3C64XX_UINTM_RXD, portaddrl(port, S3C64XX_UINTM));
29bef799 1083
88bb4ea1
TA		 1084 dbg("s3c64xx_serial_startup ok\n");
1085 return ret;
1086}
1087
b497549a
BD		 1088/* power power management control */
1089
1090static void s3c24xx_serial_pm(struct uart_port *port, unsigned int level,
1091 unsigned int old)
1092{
1093 struct s3c24xx_uart_port *ourport = to_ourport(port);
1ff383a4 1094 int timeout = 10000;
b497549a 1095
30555476
BD		 1096 ourport->pm_level = level;
1097
b497549a
BD		 1098 switch (level) {
1099 case 3:
1ff383a4
RB		 1100 while (--timeout && !s3c24xx_serial_txempty_nofifo(port))
1101 udelay(100);
1102
7cd88831 1103 if (!IS_ERR(ourport->baudclk))
9484b009 1104 clk_disable_unprepare(ourport->baudclk);
b497549a 1105
9484b009 1106 clk_disable_unprepare(ourport->clk);
b497549a
BD		 1107 break;
1108
1109 case 0:
9484b009 1110 clk_prepare_enable(ourport->clk);
b497549a 1111
7cd88831 1112 if (!IS_ERR(ourport->baudclk))
9484b009 1113 clk_prepare_enable(ourport->baudclk);
b497549a
BD		 1114
1115 break;
1116 default:
d20925e1 1117 dev_err(port->dev, "s3c24xx_serial: unknown pm %d\n", level);
b497549a
BD		 1118 }
1119}
1120
1121/* baud rate calculation
1122 *
1123 * The UARTs on the S3C2410/S3C2440 can take their clocks from a number
1124 * of different sources, including the peripheral clock ("pclk") and an
1125 * external clock ("uclk"). The S3C2440 also adds the core clock ("fclk")
1126 * with a programmable extra divisor.
1127 *
1128 * The following code goes through the clock sources, and calculates the
1129 * baud clocks (and the resultant actual baud rates) and then tries to
1130 * pick the closest one and select that.
1131 *
1132*/
1133
5f5a7a55 1134#define MAX_CLK_NAME_LENGTH 15
b497549a 1135
5f5a7a55 1136static inline int s3c24xx_serial_getsource(struct uart_port *port)
b497549a
BD		 1137{
1138 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
5f5a7a55 1139 unsigned int ucon;
b497549a 1140
5f5a7a55
TA		 1141 if (info->num_clks == 1)
1142 return 0;
b497549a 1143
5f5a7a55
TA		 1144 ucon = rd_regl(port, S3C2410_UCON);
1145 ucon &= info->clksel_mask;
1146 return ucon >> info->clksel_shift;
b497549a
BD		 1147}
1148
5f5a7a55
TA		 1149static void s3c24xx_serial_setsource(struct uart_port *port,
1150 unsigned int clk_sel)
b497549a 1151{
5f5a7a55
TA		 1152 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1153 unsigned int ucon;
b497549a 1154
5f5a7a55
TA		 1155 if (info->num_clks == 1)
1156 return;
090f848d 1157
5f5a7a55
TA		 1158 ucon = rd_regl(port, S3C2410_UCON);
1159 if ((ucon & info->clksel_mask) >> info->clksel_shift == clk_sel)
1160 return;
b497549a 1161
5f5a7a55
TA		 1162 ucon &= ~info->clksel_mask;
1163 ucon |= clk_sel << info->clksel_shift;
1164 wr_regl(port, S3C2410_UCON, ucon);
b497549a
BD		 1165}
1166
5f5a7a55
TA		 1167static unsigned int s3c24xx_serial_getclk(struct s3c24xx_uart_port *ourport,
1168 unsigned int req_baud, struct clk **best_clk,
1169 unsigned int *clk_num)
b497549a 1170{
5f5a7a55
TA		 1171 struct s3c24xx_uart_info *info = ourport->info;
1172 struct clk *clk;
1173 unsigned long rate;
1174 unsigned int cnt, baud, quot, clk_sel, best_quot = 0;
1175 char clkname[MAX_CLK_NAME_LENGTH];
1176 int calc_deviation, deviation = (1 << 30) - 1;
1177
5f5a7a55
TA		 1178 clk_sel = (ourport->cfg->clk_sel) ? ourport->cfg->clk_sel :
1179 ourport->info->def_clk_sel;
1180 for (cnt = 0; cnt < info->num_clks; cnt++) {
1181 if (!(clk_sel & (1 << cnt)))
1182 continue;
1183
1184 sprintf(clkname, "clk_uart_baud%d", cnt);
1185 clk = clk_get(ourport->port.dev, clkname);
7cd88831 1186 if (IS_ERR(clk))
5f5a7a55
TA		 1187 continue;
1188
1189 rate = clk_get_rate(clk);
1190 if (!rate)
1191 continue;
1192
1193 if (ourport->info->has_divslot) {
1194 unsigned long div = rate / req_baud;
1195
1196 /* The UDIVSLOT register on the newer UARTs allows us to
1197 * get a divisor adjustment of 1/16th on the baud clock.
1198 *
1199 * We don't keep the UDIVSLOT value (the 16ths we
1200 * calculated by not multiplying the baud by 16) as it
1201 * is easy enough to recalculate.
1202 */
1203
1204 quot = div / 16;
1205 baud = rate / div;
1206 } else {
1207 quot = (rate + (8 * req_baud)) / (16 * req_baud);
1208 baud = rate / (quot * 16);
b497549a 1209 }
5f5a7a55 1210 quot--;
b497549a 1211
5f5a7a55
TA		 1212 calc_deviation = req_baud - baud;
1213 if (calc_deviation < 0)
1214 calc_deviation = -calc_deviation;
b497549a 1215
5f5a7a55
TA		 1216 if (calc_deviation < deviation) {
1217 *best_clk = clk;
1218 best_quot = quot;
1219 *clk_num = cnt;
1220 deviation = calc_deviation;
b497549a
BD		 1221 }
1222 }
1223
5f5a7a55 1224 return best_quot;
b497549a
BD		 1225}
1226
090f848d
BD		 1227/* udivslot_table[]
1228 *
1229 * This table takes the fractional value of the baud divisor and gives
1230 * the recommended setting for the UDIVSLOT register.
1231 */
1232static u16 udivslot_table[16] = {
1233 [0] = 0x0000,
1234 [1] = 0x0080,
1235 [2] = 0x0808,
1236 [3] = 0x0888,
1237 [4] = 0x2222,
1238 [5] = 0x4924,
1239 [6] = 0x4A52,
1240 [7] = 0x54AA,
1241 [8] = 0x5555,
1242 [9] = 0xD555,
1243 [10] = 0xD5D5,
1244 [11] = 0xDDD5,
1245 [12] = 0xDDDD,
1246 [13] = 0xDFDD,
1247 [14] = 0xDFDF,
1248 [15] = 0xFFDF,
1249};
1250
b497549a
BD		 1251static void s3c24xx_serial_set_termios(struct uart_port *port,
1252 struct ktermios *termios,
1253 struct ktermios *old)
1254{
1255 struct s3c2410_uartcfg *cfg = s3c24xx_port_to_cfg(port);
1256 struct s3c24xx_uart_port *ourport = to_ourport(port);
7cd88831 1257 struct clk *clk = ERR_PTR(-EINVAL);
b497549a 1258 unsigned long flags;
5f5a7a55 1259 unsigned int baud, quot, clk_sel = 0;
b497549a
BD		 1260 unsigned int ulcon;
1261 unsigned int umcon;
090f848d 1262 unsigned int udivslot = 0;
b497549a
BD		 1263
1264 /*
1265 * We don't support modem control lines.
1266 */
1267 termios->c_cflag &= ~(HUPCL | CMSPAR);
1268 termios->c_cflag |= CLOCAL;
1269
1270 /*
1271 * Ask the core to calculate the divisor for us.
1272 */
1273
1274 baud = uart_get_baud_rate(port, termios, old, 0, 115200*8);
5f5a7a55 1275 quot = s3c24xx_serial_getclk(ourport, baud, &clk, &clk_sel);
b497549a
BD		 1276 if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST)
1277 quot = port->custom_divisor;
7cd88831 1278 if (IS_ERR(clk))
5f5a7a55 1279 return;
b497549a
BD		 1280
1281 /* check to see if we need to change clock source */
1282
5f5a7a55
TA		 1283 if (ourport->baudclk != clk) {
1284 s3c24xx_serial_setsource(port, clk_sel);
b497549a 1285
7cd88831 1286 if (!IS_ERR(ourport->baudclk)) {
9484b009 1287 clk_disable_unprepare(ourport->baudclk);
7cd88831 1288 ourport->baudclk = ERR_PTR(-EINVAL);
b497549a
BD		 1289 }
1290
9484b009 1291 clk_prepare_enable(clk);
b497549a 1292
b497549a 1293 ourport->baudclk = clk;
30555476 1294 ourport->baudclk_rate = clk ? clk_get_rate(clk) : 0;
b497549a
BD		 1295 }
1296
090f848d
BD		 1297 if (ourport->info->has_divslot) {
1298 unsigned int div = ourport->baudclk_rate / baud;
1299
8b526ae4
JL		 1300 if (cfg->has_fracval) {
1301 udivslot = (div & 15);
1302 dbg("fracval = %04x\n", udivslot);
1303 } else {
1304 udivslot = udivslot_table[div & 15];
1305 dbg("udivslot = %04x (div %d)\n", udivslot, div & 15);
1306 }
090f848d
BD		 1307 }
1308
b497549a
BD		 1309 switch (termios->c_cflag & CSIZE) {
1310 case CS5:
1311 dbg("config: 5bits/char\n");
1312 ulcon = S3C2410_LCON_CS5;
1313 break;
1314 case CS6:
1315 dbg("config: 6bits/char\n");
1316 ulcon = S3C2410_LCON_CS6;
1317 break;
1318 case CS7:
1319 dbg("config: 7bits/char\n");
1320 ulcon = S3C2410_LCON_CS7;
1321 break;
1322 case CS8:
1323 default:
1324 dbg("config: 8bits/char\n");
1325 ulcon = S3C2410_LCON_CS8;
1326 break;
1327 }
1328
1329 /* preserve original lcon IR settings */
1330 ulcon |= (cfg->ulcon & S3C2410_LCON_IRM);
1331
1332 if (termios->c_cflag & CSTOPB)
1333 ulcon |= S3C2410_LCON_STOPB;
1334
b497549a
BD		 1335 if (termios->c_cflag & PARENB) {
1336 if (termios->c_cflag & PARODD)
1337 ulcon |= S3C2410_LCON_PODD;
1338 else
1339 ulcon |= S3C2410_LCON_PEVEN;
1340 } else {
1341 ulcon |= S3C2410_LCON_PNONE;
1342 }
1343
1344 spin_lock_irqsave(&port->lock, flags);
1345
090f848d
BD		 1346 dbg("setting ulcon to %08x, brddiv to %d, udivslot %08x\n",
1347 ulcon, quot, udivslot);
b497549a
BD		 1348
1349 wr_regl(port, S3C2410_ULCON, ulcon);
1350 wr_regl(port, S3C2410_UBRDIV, quot);
2d1e5a48
JMG		 1351
1352 umcon = rd_regl(port, S3C2410_UMCON);
1353 if (termios->c_cflag & CRTSCTS) {
1354 umcon |= S3C2410_UMCOM_AFC;
1355 /* Disable RTS when RX FIFO contains 63 bytes */
1356 umcon &= ~S3C2412_UMCON_AFC_8;
1357 } else {
1358 umcon &= ~S3C2410_UMCOM_AFC;
1359 }
b497549a
BD		 1360 wr_regl(port, S3C2410_UMCON, umcon);
1361
090f848d
BD		 1362 if (ourport->info->has_divslot)
1363 wr_regl(port, S3C2443_DIVSLOT, udivslot);
1364
b497549a
BD		 1365 dbg("uart: ulcon = 0x%08x, ucon = 0x%08x, ufcon = 0x%08x\n",
1366 rd_regl(port, S3C2410_ULCON),
1367 rd_regl(port, S3C2410_UCON),
1368 rd_regl(port, S3C2410_UFCON));
1369
1370 /*
1371 * Update the per-port timeout.
1372 */
1373 uart_update_timeout(port, termios->c_cflag, baud);
1374
1375 /*
1376 * Which character status flags are we interested in?
1377 */
1378 port->read_status_mask = S3C2410_UERSTAT_OVERRUN;
1379 if (termios->c_iflag & INPCK)
ef4aca70
RB		 1380 port->read_status_mask |= S3C2410_UERSTAT_FRAME |
1381 S3C2410_UERSTAT_PARITY;
b497549a
BD		 1382 /*
1383 * Which character status flags should we ignore?
1384 */
1385 port->ignore_status_mask = 0;
1386 if (termios->c_iflag & IGNPAR)
1387 port->ignore_status_mask |= S3C2410_UERSTAT_OVERRUN;
1388 if (termios->c_iflag & IGNBRK && termios->c_iflag & IGNPAR)
1389 port->ignore_status_mask |= S3C2410_UERSTAT_FRAME;
1390
1391 /*
1392 * Ignore all characters if CREAD is not set.
1393 */
1394 if ((termios->c_cflag & CREAD) == 0)
1395 port->ignore_status_mask |= RXSTAT_DUMMY_READ;
1396
1397 spin_unlock_irqrestore(&port->lock, flags);
1398}
1399
1400static const char *s3c24xx_serial_type(struct uart_port *port)
1401{
1402 switch (port->type) {
1403 case PORT_S3C2410:
1404 return "S3C2410";
1405 case PORT_S3C2440:
1406 return "S3C2440";
1407 case PORT_S3C2412:
1408 return "S3C2412";
b690ace5
BD		 1409 case PORT_S3C6400:
1410 return "S3C6400/10";
b497549a
BD		 1411 default:
1412 return NULL;
1413 }
1414}
1415
1416#define MAP_SIZE (0x100)
1417
1418static void s3c24xx_serial_release_port(struct uart_port *port)
1419{
1420 release_mem_region(port->mapbase, MAP_SIZE);
1421}
1422
1423static int s3c24xx_serial_request_port(struct uart_port *port)
1424{
1425 const char *name = s3c24xx_serial_portname(port);
1426 return request_mem_region(port->mapbase, MAP_SIZE, name) ? 0 : -EBUSY;
1427}
1428
1429static void s3c24xx_serial_config_port(struct uart_port *port, int flags)
1430{
1431 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1432
1433 if (flags & UART_CONFIG_TYPE &&
1434 s3c24xx_serial_request_port(port) == 0)
1435 port->type = info->type;
1436}
1437
1438/*
1439 * verify the new serial_struct (for TIOCSSERIAL).
1440 */
1441static int
1442s3c24xx_serial_verify_port(struct uart_port *port, struct serial_struct *ser)
1443{
1444 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1445
1446 if (ser->type != PORT_UNKNOWN && ser->type != info->type)
1447 return -EINVAL;
1448
1449 return 0;
1450}
1451
1452
1453#ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
1454
1455static struct console s3c24xx_serial_console;
1456
93b5c032
JP		 1457static int __init s3c24xx_serial_console_init(void)
1458{
1459 register_console(&s3c24xx_serial_console);
1460 return 0;
1461}
1462console_initcall(s3c24xx_serial_console_init);
1463
b497549a
BD		 1464#define S3C24XX_SERIAL_CONSOLE &s3c24xx_serial_console
1465#else
1466#define S3C24XX_SERIAL_CONSOLE NULL
1467#endif
1468
84f57d9e 1469#if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
93b5c032
JP		 1470static int s3c24xx_serial_get_poll_char(struct uart_port *port);
1471static void s3c24xx_serial_put_poll_char(struct uart_port *port,
1472 unsigned char c);
1473#endif
1474
b497549a
BD		 1475static struct uart_ops s3c24xx_serial_ops = {
1476 .pm = s3c24xx_serial_pm,
1477 .tx_empty = s3c24xx_serial_tx_empty,
1478 .get_mctrl = s3c24xx_serial_get_mctrl,
1479 .set_mctrl = s3c24xx_serial_set_mctrl,
1480 .stop_tx = s3c24xx_serial_stop_tx,
1481 .start_tx = s3c24xx_serial_start_tx,
1482 .stop_rx = s3c24xx_serial_stop_rx,
b497549a
BD		 1483 .break_ctl = s3c24xx_serial_break_ctl,
1484 .startup = s3c24xx_serial_startup,
1485 .shutdown = s3c24xx_serial_shutdown,
1486 .set_termios = s3c24xx_serial_set_termios,
1487 .type = s3c24xx_serial_type,
1488 .release_port = s3c24xx_serial_release_port,
1489 .request_port = s3c24xx_serial_request_port,
1490 .config_port = s3c24xx_serial_config_port,
1491 .verify_port = s3c24xx_serial_verify_port,
84f57d9e 1492#if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
93b5c032
JP		 1493 .poll_get_char = s3c24xx_serial_get_poll_char,
1494 .poll_put_char = s3c24xx_serial_put_poll_char,
1495#endif
b497549a
BD		 1496};
1497
b497549a
BD		 1498static struct uart_driver s3c24xx_uart_drv = {
1499 .owner = THIS_MODULE,
2cf0c58e 1500 .driver_name = "s3c2410_serial",
bdd4915a 1501 .nr = CONFIG_SERIAL_SAMSUNG_UARTS,
b497549a 1502 .cons = S3C24XX_SERIAL_CONSOLE,
2cf0c58e 1503 .dev_name = S3C24XX_SERIAL_NAME,
b497549a
BD		 1504 .major = S3C24XX_SERIAL_MAJOR,
1505 .minor = S3C24XX_SERIAL_MINOR,
1506};
1507
ef4aca70
RB		 1508#define __PORT_LOCK_UNLOCKED(i) \
1509 __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[i].port.lock)
1510static struct s3c24xx_uart_port
1511s3c24xx_serial_ports[CONFIG_SERIAL_SAMSUNG_UARTS] = {
b497549a
BD		 1512 [0] = {
1513 .port = {
ef4aca70 1514 .lock = __PORT_LOCK_UNLOCKED(0),
b497549a 1515 .iotype = UPIO_MEM,
b497549a
BD		 1516 .uartclk = 0,
1517 .fifosize = 16,
1518 .ops = &s3c24xx_serial_ops,
1519 .flags = UPF_BOOT_AUTOCONF,
1520 .line = 0,
1521 }
1522 },
1523 [1] = {
1524 .port = {
ef4aca70 1525 .lock = __PORT_LOCK_UNLOCKED(1),
b497549a 1526 .iotype = UPIO_MEM,
b497549a
BD		 1527 .uartclk = 0,
1528 .fifosize = 16,
1529 .ops = &s3c24xx_serial_ops,
1530 .flags = UPF_BOOT_AUTOCONF,
1531 .line = 1,
1532 }
1533 },
03d5e77b 1534#if CONFIG_SERIAL_SAMSUNG_UARTS > 2
b497549a
BD		 1535
1536 [2] = {
1537 .port = {
ef4aca70 1538 .lock = __PORT_LOCK_UNLOCKED(2),
b497549a 1539 .iotype = UPIO_MEM,
b497549a
BD		 1540 .uartclk = 0,
1541 .fifosize = 16,
1542 .ops = &s3c24xx_serial_ops,
1543 .flags = UPF_BOOT_AUTOCONF,
1544 .line = 2,
1545 }
03d5e77b
BD		 1546 },
1547#endif
1548#if CONFIG_SERIAL_SAMSUNG_UARTS > 3
1549 [3] = {
1550 .port = {
ef4aca70 1551 .lock = __PORT_LOCK_UNLOCKED(3),
03d5e77b 1552 .iotype = UPIO_MEM,
03d5e77b
BD		 1553 .uartclk = 0,
1554 .fifosize = 16,
1555 .ops = &s3c24xx_serial_ops,
1556 .flags = UPF_BOOT_AUTOCONF,
1557 .line = 3,
1558 }
b497549a
BD		 1559 }
1560#endif
1561};
ef4aca70 1562#undef __PORT_LOCK_UNLOCKED
b497549a
BD		 1563
1564/* s3c24xx_serial_resetport
1565 *
0dfb3b41 1566 * reset the fifos and other the settings.
b497549a
BD		 1567*/
1568
0dfb3b41
TA		 1569static void s3c24xx_serial_resetport(struct uart_port *port,
1570 struct s3c2410_uartcfg *cfg)
b497549a
BD		 1571{
1572 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
0dfb3b41
TA		 1573 unsigned long ucon = rd_regl(port, S3C2410_UCON);
1574 unsigned int ucon_mask;
b497549a 1575
0dfb3b41
TA		 1576 ucon_mask = info->clksel_mask;
1577 if (info->type == PORT_S3C2440)
1578 ucon_mask |= S3C2440_UCON0_DIVMASK;
1579
1580 ucon &= ucon_mask;
1581 wr_regl(port, S3C2410_UCON, ucon | cfg->ucon);
1582
1583 /* reset both fifos */
1584 wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
1585 wr_regl(port, S3C2410_UFCON, cfg->ufcon);
1586
1587 /* some delay is required after fifo reset */
1588 udelay(1);
b497549a
BD		 1589}
1590
30555476
BD		 1591
1592#ifdef CONFIG_CPU_FREQ
1593
1594static int s3c24xx_serial_cpufreq_transition(struct notifier_block *nb,
1595 unsigned long val, void *data)
1596{
1597 struct s3c24xx_uart_port *port;
1598 struct uart_port *uport;
1599
1600 port = container_of(nb, struct s3c24xx_uart_port, freq_transition);
1601 uport = &port->port;
1602
1603 /* check to see if port is enabled */
1604
1605 if (port->pm_level != 0)
1606 return 0;
1607
1608 /* try and work out if the baudrate is changing, we can detect
1609 * a change in rate, but we do not have support for detecting
1610 * a disturbance in the clock-rate over the change.
1611 */
1612
25f04ad4 1613 if (IS_ERR(port->baudclk))
30555476
BD		 1614 goto exit;
1615
25f04ad4 1616 if (port->baudclk_rate == clk_get_rate(port->baudclk))
30555476
BD		 1617 goto exit;
1618
1619 if (val == CPUFREQ_PRECHANGE) {
1620 /* we should really shut the port down whilst the
1621 * frequency change is in progress. */
1622
1623 } else if (val == CPUFREQ_POSTCHANGE) {
1624 struct ktermios *termios;
1625 struct tty_struct *tty;
1626
ebd2c8f6 1627 if (uport->state == NULL)
30555476 1628 goto exit;
30555476 1629
ebd2c8f6 1630 tty = uport->state->port.tty;
30555476 1631
7de40c21 1632 if (tty == NULL)
30555476 1633 goto exit;
30555476 1634
adc8d746 1635 termios = &tty->termios;
30555476
BD		 1636
1637 if (termios == NULL) {
d20925e1 1638 dev_warn(uport->dev, "%s: no termios?\n", __func__);
30555476
BD		 1639 goto exit;
1640 }
1641
1642 s3c24xx_serial_set_termios(uport, termios, NULL);
1643 }
1644
ef4aca70 1645exit:
30555476
BD		 1646 return 0;
1647}
1648
ef4aca70
RB		 1649static inline int
1650s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port)
30555476
BD		 1651{
1652 port->freq_transition.notifier_call = s3c24xx_serial_cpufreq_transition;
1653
1654 return cpufreq_register_notifier(&port->freq_transition,
1655 CPUFREQ_TRANSITION_NOTIFIER);
1656}
1657
ef4aca70
RB		 1658static inline void
1659s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port)
30555476
BD		 1660{
1661 cpufreq_unregister_notifier(&port->freq_transition,
1662 CPUFREQ_TRANSITION_NOTIFIER);
1663}
1664
1665#else
ef4aca70
RB		 1666static inline int
1667s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port)
30555476
BD		 1668{
1669 return 0;
1670}
1671
ef4aca70
RB		 1672static inline void
1673s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port)
30555476
BD		 1674{
1675}
1676#endif
1677
b497549a
BD		 1678/* s3c24xx_serial_init_port
1679 *
1680 * initialise a single serial port from the platform device given
1681 */
1682
1683static int s3c24xx_serial_init_port(struct s3c24xx_uart_port *ourport,
b497549a
BD		 1684 struct platform_device *platdev)
1685{
1686 struct uart_port *port = &ourport->port;
da121506 1687 struct s3c2410_uartcfg *cfg = ourport->cfg;
b497549a
BD		 1688 struct resource *res;
1689 int ret;
1690
1691 dbg("s3c24xx_serial_init_port: port=%p, platdev=%p\n", port, platdev);
1692
1693 if (platdev == NULL)
1694 return -ENODEV;
1695
b497549a
BD		 1696 if (port->mapbase != 0)
1697 return 0;
1698
b497549a
BD		 1699 /* setup info for port */
1700 port->dev = &platdev->dev;
b497549a 1701
88bb4ea1
TA		 1702 /* Startup sequence is different for s3c64xx and higher SoC's */
1703 if (s3c24xx_serial_has_interrupt_mask(port))
1704 s3c24xx_serial_ops.startup = s3c64xx_serial_startup;
1705
b497549a
BD		 1706 port->uartclk = 1;
1707
1708 if (cfg->uart_flags & UPF_CONS_FLOW) {
1709 dbg("s3c24xx_serial_init_port: enabling flow control\n");
1710 port->flags |= UPF_CONS_FLOW;
1711 }
1712
1713 /* sort our the physical and virtual addresses for each UART */
1714
1715 res = platform_get_resource(platdev, IORESOURCE_MEM, 0);
1716 if (res == NULL) {
d20925e1 1717 dev_err(port->dev, "failed to find memory resource for uart\n");
b497549a
BD		 1718 return -EINVAL;
1719 }
1720
e4ac92df 1721 dbg("resource %pR)\n", res);
b497549a 1722
41147bfd
TA		 1723 port->membase = devm_ioremap(port->dev, res->start, resource_size(res));
1724 if (!port->membase) {
1725 dev_err(port->dev, "failed to remap controller address\n");
1726 return -EBUSY;
1727 }
1728
b690ace5 1729 port->mapbase = res->start;
b497549a
BD		 1730 ret = platform_get_irq(platdev, 0);
1731 if (ret < 0)
1732 port->irq = 0;
b73c289c 1733 else {
b497549a 1734 port->irq = ret;
b73c289c
BD		 1735 ourport->rx_irq = ret;
1736 ourport->tx_irq = ret + 1;
1737 }
9303ac15 1738
b73c289c
BD		 1739 ret = platform_get_irq(platdev, 1);
1740 if (ret > 0)
1741 ourport->tx_irq = ret;
658c9d2b
RB		 1742 /*
1743 * DMA is currently supported only on DT platforms, if DMA properties
1744 * are specified.
1745 */
1746 if (platdev->dev.of_node && of_find_property(platdev->dev.of_node,
1747 "dmas", NULL)) {
1748 ourport->dma = devm_kzalloc(port->dev,
1749 sizeof(*ourport->dma),
1750 GFP_KERNEL);
1751 if (!ourport->dma)
1752 return -ENOMEM;
1753 }
b497549a
BD		 1754
1755 ourport->clk = clk_get(&platdev->dev, "uart");
60e93575
CK		 1756 if (IS_ERR(ourport->clk)) {
1757 pr_err("%s: Controller clock not found\n",
1758 dev_name(&platdev->dev));
1759 return PTR_ERR(ourport->clk);
1760 }
1761
1762 ret = clk_prepare_enable(ourport->clk);
1763 if (ret) {
1764 pr_err("uart: clock failed to prepare+enable: %d\n", ret);
1765 clk_put(ourport->clk);
1766 return ret;
1767 }
b497549a 1768
88bb4ea1
TA		 1769 /* Keep all interrupts masked and cleared */
1770 if (s3c24xx_serial_has_interrupt_mask(port)) {
1771 wr_regl(port, S3C64XX_UINTM, 0xf);
1772 wr_regl(port, S3C64XX_UINTP, 0xf);
1773 wr_regl(port, S3C64XX_UINTSP, 0xf);
1774 }
1775
1ff5b64d
FE		 1776 dbg("port: map=%pa, mem=%p, irq=%d (%d,%d), clock=%u\n",
1777 &port->mapbase, port->membase, port->irq,
b73c289c 1778 ourport->rx_irq, ourport->tx_irq, port->uartclk);
b497549a
BD		 1779
1780 /* reset the fifos (and setup the uart) */
1781 s3c24xx_serial_resetport(port, cfg);
1782 return 0;
1783}
1784
b497549a
BD		 1785/* Device driver serial port probe */
1786
26c919e1 1787static const struct of_device_id s3c24xx_uart_dt_match[];
b497549a
BD		 1788static int probe_index;
1789
26c919e1
TA		 1790static inline struct s3c24xx_serial_drv_data *s3c24xx_get_driver_data(
1791 struct platform_device *pdev)
1792{
1793#ifdef CONFIG_OF
1794 if (pdev->dev.of_node) {
1795 const struct of_device_id *match;
1796 match = of_match_node(s3c24xx_uart_dt_match, pdev->dev.of_node);
1797 return (struct s3c24xx_serial_drv_data *)match->data;
1798 }
1799#endif
1800 return (struct s3c24xx_serial_drv_data *)
1801 platform_get_device_id(pdev)->driver_data;
1802}
1803
da121506 1804static int s3c24xx_serial_probe(struct platform_device *pdev)
b497549a 1805{
4622eb68 1806 struct device_node *np = pdev->dev.of_node;
b497549a 1807 struct s3c24xx_uart_port *ourport;
13a9f6c6 1808 int index = probe_index;
b497549a
BD		 1809 int ret;
1810
4622eb68
NKC		 1811 if (np) {
1812 ret = of_alias_get_id(np, "serial");
13a9f6c6
TF		 1813 if (ret >= 0)
1814 index = ret;
1815 }
1816
1817 dbg("s3c24xx_serial_probe(%p) %d\n", pdev, index);
b497549a 1818
13a9f6c6 1819 ourport = &s3c24xx_serial_ports[index];
da121506 1820
26c919e1
TA		 1821 ourport->drv_data = s3c24xx_get_driver_data(pdev);
1822 if (!ourport->drv_data) {
1823 dev_err(&pdev->dev, "could not find driver data\n");
1824 return -ENODEV;
1825 }
da121506 1826
7cd88831 1827 ourport->baudclk = ERR_PTR(-EINVAL);
da121506 1828 ourport->info = ourport->drv_data->info;
574de559 1829 ourport->cfg = (dev_get_platdata(&pdev->dev)) ?
d4aab206 1830 dev_get_platdata(&pdev->dev) :
da121506
TA		 1831 ourport->drv_data->def_cfg;
1832
4622eb68
NKC		 1833 if (np)
1834 of_property_read_u32(np,
135f07c3
NKC		 1835 "samsung,uart-fifosize", &ourport->port.fifosize);
1836
2f1ba72d
RB		 1837 if (ourport->drv_data->fifosize[index])
1838 ourport->port.fifosize = ourport->drv_data->fifosize[index];
1839 else if (ourport->info->fifosize)
1840 ourport->port.fifosize = ourport->info->fifosize;
da121506 1841
81ccb2a6
MS		 1842 /*
1843 * DMA transfers must be aligned at least to cache line size,
1844 * so find minimal transfer size suitable for DMA mode
1845 */
1846 ourport->min_dma_size = max_t(int, ourport->port.fifosize,
1847 dma_get_cache_alignment());
1848
b497549a
BD		 1849 probe_index++;
1850
1851 dbg("%s: initialising port %p...\n", __func__, ourport);
1852
da121506 1853 ret = s3c24xx_serial_init_port(ourport, pdev);
b497549a 1854 if (ret < 0)
8ad711a9 1855 return ret;
b497549a 1856
6f134c3c
TB		 1857 if (!s3c24xx_uart_drv.state) {
1858 ret = uart_register_driver(&s3c24xx_uart_drv);
1859 if (ret < 0) {
1860 pr_err("Failed to register Samsung UART driver\n");
1861 return ret;
1862 }
1863 }
1864
b497549a
BD		 1865 dbg("%s: adding port\n", __func__);
1866 uart_add_one_port(&s3c24xx_uart_drv, &ourport->port);
da121506 1867 platform_set_drvdata(pdev, &ourport->port);
b497549a 1868
0da3336f
HS		 1869 /*
1870 * Deactivate the clock enabled in s3c24xx_serial_init_port here,
1871 * so that a potential re-enablement through the pm-callback overlaps
1872 * and keeps the clock enabled in this case.
1873 */
1874 clk_disable_unprepare(ourport->clk);
1875
30555476
BD		 1876 ret = s3c24xx_serial_cpufreq_register(ourport);
1877 if (ret < 0)
da121506 1878 dev_err(&pdev->dev, "failed to add cpufreq notifier\n");
30555476 1879
b497549a 1880 return 0;
b497549a
BD		 1881}
1882
ae8d8a14 1883static int s3c24xx_serial_remove(struct platform_device *dev)
b497549a
BD		 1884{
1885 struct uart_port *port = s3c24xx_dev_to_port(&dev->dev);
1886
1887 if (port) {
30555476 1888 s3c24xx_serial_cpufreq_deregister(to_ourport(port));
b497549a
BD		 1889 uart_remove_one_port(&s3c24xx_uart_drv, port);
1890 }
1891
6f134c3c
TB		 1892 uart_unregister_driver(&s3c24xx_uart_drv);
1893
b497549a
BD		 1894 return 0;
1895}
1896
b497549a 1897/* UART power management code */
aef7fe52
MH		 1898#ifdef CONFIG_PM_SLEEP
1899static int s3c24xx_serial_suspend(struct device *dev)
b497549a 1900{
aef7fe52 1901 struct uart_port *port = s3c24xx_dev_to_port(dev);
b497549a
BD		 1902
1903 if (port)
1904 uart_suspend_port(&s3c24xx_uart_drv, port);
1905
1906 return 0;
1907}
1908
aef7fe52 1909static int s3c24xx_serial_resume(struct device *dev)
b497549a 1910{
aef7fe52 1911 struct uart_port *port = s3c24xx_dev_to_port(dev);
b497549a
BD		 1912 struct s3c24xx_uart_port *ourport = to_ourport(port);
1913
1914 if (port) {
9484b009 1915 clk_prepare_enable(ourport->clk);
b497549a 1916 s3c24xx_serial_resetport(port, s3c24xx_port_to_cfg(port));
9484b009 1917 clk_disable_unprepare(ourport->clk);
b497549a
BD		 1918
1919 uart_resume_port(&s3c24xx_uart_drv, port);
1920 }
1921
1922 return 0;
1923}
aef7fe52 1924
d09a7308
MS		 1925static int s3c24xx_serial_resume_noirq(struct device *dev)
1926{
1927 struct uart_port *port = s3c24xx_dev_to_port(dev);
1928
1929 if (port) {
1930 /* restore IRQ mask */
1931 if (s3c24xx_serial_has_interrupt_mask(port)) {
1932 unsigned int uintm = 0xf;
1933 if (tx_enabled(port))
1934 uintm &= ~S3C64XX_UINTM_TXD_MSK;
1935 if (rx_enabled(port))
1936 uintm &= ~S3C64XX_UINTM_RXD_MSK;
1937 wr_regl(port, S3C64XX_UINTM, uintm);
1938 }
1939 }
1940
1941 return 0;
1942}
1943
aef7fe52
MH		 1944static const struct dev_pm_ops s3c24xx_serial_pm_ops = {
1945 .suspend = s3c24xx_serial_suspend,
1946 .resume = s3c24xx_serial_resume,
d09a7308 1947 .resume_noirq = s3c24xx_serial_resume_noirq,
aef7fe52 1948};
b882fc1b
KK		 1949#define SERIAL_SAMSUNG_PM_OPS (&s3c24xx_serial_pm_ops)
1950
aef7fe52 1951#else /* !CONFIG_PM_SLEEP */
b882fc1b
KK		 1952
1953#define SERIAL_SAMSUNG_PM_OPS NULL
aef7fe52 1954#endif /* CONFIG_PM_SLEEP */
b497549a 1955
b497549a
BD		 1956/* Console code */
1957
1958#ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
1959
1960static struct uart_port *cons_uart;
1961
1962static int
1963s3c24xx_serial_console_txrdy(struct uart_port *port, unsigned int ufcon)
1964{
1965 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1966 unsigned long ufstat, utrstat;
1967
1968 if (ufcon & S3C2410_UFCON_FIFOMODE) {
9ddc5b6f 1969 /* fifo mode - check amount of data in fifo registers... */
b497549a
BD		 1970
1971 ufstat = rd_regl(port, S3C2410_UFSTAT);
1972 return (ufstat & info->tx_fifofull) ? 0 : 1;
1973 }
1974
1975 /* in non-fifo mode, we go and use the tx buffer empty */
1976
1977 utrstat = rd_regl(port, S3C2410_UTRSTAT);
1978 return (utrstat & S3C2410_UTRSTAT_TXE) ? 1 : 0;
1979}
1980
38adbc54
MS		 1981static bool
1982s3c24xx_port_configured(unsigned int ucon)
1983{
1984 /* consider the serial port configured if the tx/rx mode set */
1985 return (ucon & 0xf) != 0;
1986}
1987
93b5c032
JP		 1988#ifdef CONFIG_CONSOLE_POLL
1989/*
1990 * Console polling routines for writing and reading from the uart while
1991 * in an interrupt or debug context.
1992 */
1993
1994static int s3c24xx_serial_get_poll_char(struct uart_port *port)
1995{
1996 struct s3c24xx_uart_port *ourport = to_ourport(port);
1997 unsigned int ufstat;
1998
1999 ufstat = rd_regl(port, S3C2410_UFSTAT);
2000 if (s3c24xx_serial_rx_fifocnt(ourport, ufstat) == 0)
2001 return NO_POLL_CHAR;
2002
2003 return rd_regb(port, S3C2410_URXH);
2004}
2005
2006static void s3c24xx_serial_put_poll_char(struct uart_port *port,
2007 unsigned char c)
2008{
bb7f09ba
DA		 2009 unsigned int ufcon = rd_regl(port, S3C2410_UFCON);
2010 unsigned int ucon = rd_regl(port, S3C2410_UCON);
38adbc54
MS		 2011
2012 /* not possible to xmit on unconfigured port */
2013 if (!s3c24xx_port_configured(ucon))
2014 return;
93b5c032
JP		 2015
2016 while (!s3c24xx_serial_console_txrdy(port, ufcon))
2017 cpu_relax();
bb7f09ba 2018 wr_regb(port, S3C2410_UTXH, c);
93b5c032
JP		 2019}
2020
2021#endif /* CONFIG_CONSOLE_POLL */
2022
b497549a
BD		 2023static void
2024s3c24xx_serial_console_putchar(struct uart_port *port, int ch)
2025{
bb7f09ba 2026 unsigned int ufcon = rd_regl(port, S3C2410_UFCON);
38adbc54 2027
b497549a 2028 while (!s3c24xx_serial_console_txrdy(port, ufcon))
f94b0572 2029 cpu_relax();
bb7f09ba 2030 wr_regb(port, S3C2410_UTXH, ch);
b497549a
BD		 2031}
2032
2033static void
2034s3c24xx_serial_console_write(struct console *co, const char *s,
2035 unsigned int count)
2036{
ab88c8dc
DA		 2037 unsigned int ucon = rd_regl(cons_uart, S3C2410_UCON);
2038
2039 /* not possible to xmit on unconfigured port */
2040 if (!s3c24xx_port_configured(ucon))
2041 return;
2042
b497549a
BD		 2043 uart_console_write(cons_uart, s, count, s3c24xx_serial_console_putchar);
2044}
2045
2046static void __init
2047s3c24xx_serial_get_options(struct uart_port *port, int *baud,
2048 int *parity, int *bits)
2049{
b497549a
BD		 2050 struct clk *clk;
2051 unsigned int ulcon;
2052 unsigned int ucon;
2053 unsigned int ubrdiv;
2054 unsigned long rate;
5f5a7a55
TA		 2055 unsigned int clk_sel;
2056 char clk_name[MAX_CLK_NAME_LENGTH];
b497549a
BD		 2057
2058 ulcon = rd_regl(port, S3C2410_ULCON);
2059 ucon = rd_regl(port, S3C2410_UCON);
2060 ubrdiv = rd_regl(port, S3C2410_UBRDIV);
2061
2062 dbg("s3c24xx_serial_get_options: port=%p\n"
2063 "registers: ulcon=%08x, ucon=%08x, ubdriv=%08x\n",
2064 port, ulcon, ucon, ubrdiv);
2065
38adbc54 2066 if (s3c24xx_port_configured(ucon)) {
b497549a
BD		 2067 switch (ulcon & S3C2410_LCON_CSMASK) {
2068 case S3C2410_LCON_CS5:
2069 *bits = 5;
2070 break;
2071 case S3C2410_LCON_CS6:
2072 *bits = 6;
2073 break;
2074 case S3C2410_LCON_CS7:
2075 *bits = 7;
2076 break;
b497549a 2077 case S3C2410_LCON_CS8:
3bcce591 2078 default:
b497549a
BD		 2079 *bits = 8;
2080 break;
2081 }
2082
2083 switch (ulcon & S3C2410_LCON_PMASK) {
2084 case S3C2410_LCON_PEVEN:
2085 *parity = 'e';
2086 break;
2087
2088 case S3C2410_LCON_PODD:
2089 *parity = 'o';
2090 break;
2091
2092 case S3C2410_LCON_PNONE:
2093 default:
2094 *parity = 'n';
2095 }
2096
2097 /* now calculate the baud rate */
2098
5f5a7a55
TA		 2099 clk_sel = s3c24xx_serial_getsource(port);
2100 sprintf(clk_name, "clk_uart_baud%d", clk_sel);
b497549a 2101
5f5a7a55 2102 clk = clk_get(port->dev, clk_name);
7cd88831 2103 if (!IS_ERR(clk))
5f5a7a55 2104 rate = clk_get_rate(clk);
b497549a
BD		 2105 else
2106 rate = 1;
2107
b497549a
BD		 2108 *baud = rate / (16 * (ubrdiv + 1));
2109 dbg("calculated baud %d\n", *baud);
2110 }
2111
2112}
2113
b497549a
BD		 2114static int __init
2115s3c24xx_serial_console_setup(struct console *co, char *options)
2116{
2117 struct uart_port *port;
2118 int baud = 9600;
2119 int bits = 8;
2120 int parity = 'n';
2121 int flow = 'n';
2122
2123 dbg("s3c24xx_serial_console_setup: co=%p (%d), %s\n",
2124 co, co->index, options);
2125
2126 /* is this a valid port */
2127
03d5e77b 2128 if (co->index == -1 || co->index >= CONFIG_SERIAL_SAMSUNG_UARTS)
b497549a
BD		 2129 co->index = 0;
2130
2131 port = &s3c24xx_serial_ports[co->index].port;
2132
2133 /* is the port configured? */
2134
ee430f16
TA		 2135 if (port->mapbase == 0x0)
2136 return -ENODEV;
b497549a
BD		 2137
2138 cons_uart = port;
2139
2140 dbg("s3c24xx_serial_console_setup: port=%p (%d)\n", port, co->index);
2141
2142 /*
2143 * Check whether an invalid uart number has been specified, and
2144 * if so, search for the first available port that does have
2145 * console support.
2146 */
2147 if (options)
2148 uart_parse_options(options, &baud, &parity, &bits, &flow);
2149 else
2150 s3c24xx_serial_get_options(port, &baud, &parity, &bits);
2151
2152 dbg("s3c24xx_serial_console_setup: baud %d\n", baud);
2153
2154 return uart_set_options(port, co, baud, parity, bits, flow);
2155}
2156
b497549a
BD		 2157static struct console s3c24xx_serial_console = {
2158 .name = S3C24XX_SERIAL_NAME,
2159 .device = uart_console_device,
2160 .flags = CON_PRINTBUFFER,
2161 .index = -1,
2162 .write = s3c24xx_serial_console_write,
5822a5df
TA		 2163 .setup = s3c24xx_serial_console_setup,
2164 .data = &s3c24xx_uart_drv,
b497549a 2165};
da121506
TA		 2166#endif /* CONFIG_SERIAL_SAMSUNG_CONSOLE */
2167
2168#ifdef CONFIG_CPU_S3C2410
2169static struct s3c24xx_serial_drv_data s3c2410_serial_drv_data = {
2170 .info = &(struct s3c24xx_uart_info) {
2171 .name = "Samsung S3C2410 UART",
2172 .type = PORT_S3C2410,
2173 .fifosize = 16,
2174 .rx_fifomask = S3C2410_UFSTAT_RXMASK,
2175 .rx_fifoshift = S3C2410_UFSTAT_RXSHIFT,
2176 .rx_fifofull = S3C2410_UFSTAT_RXFULL,
2177 .tx_fifofull = S3C2410_UFSTAT_TXFULL,
2178 .tx_fifomask = S3C2410_UFSTAT_TXMASK,
2179 .tx_fifoshift = S3C2410_UFSTAT_TXSHIFT,
2180 .def_clk_sel = S3C2410_UCON_CLKSEL0,
2181 .num_clks = 2,
2182 .clksel_mask = S3C2410_UCON_CLKMASK,
2183 .clksel_shift = S3C2410_UCON_CLKSHIFT,
2184 },
2185 .def_cfg = &(struct s3c2410_uartcfg) {
2186 .ucon = S3C2410_UCON_DEFAULT,
2187 .ufcon = S3C2410_UFCON_DEFAULT,
2188 },
2189};
2190#define S3C2410_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2410_serial_drv_data)
2191#else
2192#define S3C2410_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2193#endif
b497549a 2194
da121506
TA		 2195#ifdef CONFIG_CPU_S3C2412
2196static struct s3c24xx_serial_drv_data s3c2412_serial_drv_data = {
2197 .info = &(struct s3c24xx_uart_info) {
2198 .name = "Samsung S3C2412 UART",
2199 .type = PORT_S3C2412,
2200 .fifosize = 64,
2201 .has_divslot = 1,
2202 .rx_fifomask = S3C2440_UFSTAT_RXMASK,
2203 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
2204 .rx_fifofull = S3C2440_UFSTAT_RXFULL,
2205 .tx_fifofull = S3C2440_UFSTAT_TXFULL,
2206 .tx_fifomask = S3C2440_UFSTAT_TXMASK,
2207 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
2208 .def_clk_sel = S3C2410_UCON_CLKSEL2,
2209 .num_clks = 4,
2210 .clksel_mask = S3C2412_UCON_CLKMASK,
2211 .clksel_shift = S3C2412_UCON_CLKSHIFT,
2212 },
2213 .def_cfg = &(struct s3c2410_uartcfg) {
2214 .ucon = S3C2410_UCON_DEFAULT,
2215 .ufcon = S3C2410_UFCON_DEFAULT,
2216 },
2217};
2218#define S3C2412_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2412_serial_drv_data)
2219#else
2220#define S3C2412_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2221#endif
b497549a 2222
da121506 2223#if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2416) || \
b26469a8 2224 defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2442)
da121506
TA		 2225static struct s3c24xx_serial_drv_data s3c2440_serial_drv_data = {
2226 .info = &(struct s3c24xx_uart_info) {
2227 .name = "Samsung S3C2440 UART",
2228 .type = PORT_S3C2440,
2229 .fifosize = 64,
2230 .has_divslot = 1,
2231 .rx_fifomask = S3C2440_UFSTAT_RXMASK,
2232 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
2233 .rx_fifofull = S3C2440_UFSTAT_RXFULL,
2234 .tx_fifofull = S3C2440_UFSTAT_TXFULL,
2235 .tx_fifomask = S3C2440_UFSTAT_TXMASK,
2236 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
2237 .def_clk_sel = S3C2410_UCON_CLKSEL2,
2238 .num_clks = 4,
2239 .clksel_mask = S3C2412_UCON_CLKMASK,
2240 .clksel_shift = S3C2412_UCON_CLKSHIFT,
2241 },
2242 .def_cfg = &(struct s3c2410_uartcfg) {
2243 .ucon = S3C2410_UCON_DEFAULT,
2244 .ufcon = S3C2410_UFCON_DEFAULT,
2245 },
2246};
2247#define S3C2440_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2440_serial_drv_data)
2248#else
2249#define S3C2440_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2250#endif
b497549a 2251
953b53a7 2252#if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
da121506
TA		 2253static struct s3c24xx_serial_drv_data s3c6400_serial_drv_data = {
2254 .info = &(struct s3c24xx_uart_info) {
2255 .name = "Samsung S3C6400 UART",
2256 .type = PORT_S3C6400,
2257 .fifosize = 64,
2258 .has_divslot = 1,
2259 .rx_fifomask = S3C2440_UFSTAT_RXMASK,
2260 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
2261 .rx_fifofull = S3C2440_UFSTAT_RXFULL,
2262 .tx_fifofull = S3C2440_UFSTAT_TXFULL,
2263 .tx_fifomask = S3C2440_UFSTAT_TXMASK,
2264 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
2265 .def_clk_sel = S3C2410_UCON_CLKSEL2,
2266 .num_clks = 4,
2267 .clksel_mask = S3C6400_UCON_CLKMASK,
2268 .clksel_shift = S3C6400_UCON_CLKSHIFT,
2269 },
2270 .def_cfg = &(struct s3c2410_uartcfg) {
2271 .ucon = S3C2410_UCON_DEFAULT,
2272 .ufcon = S3C2410_UFCON_DEFAULT,
2273 },
2274};
2275#define S3C6400_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c6400_serial_drv_data)
2276#else
2277#define S3C6400_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2278#endif
b497549a 2279
da121506
TA		 2280#ifdef CONFIG_CPU_S5PV210
2281static struct s3c24xx_serial_drv_data s5pv210_serial_drv_data = {
2282 .info = &(struct s3c24xx_uart_info) {
2283 .name = "Samsung S5PV210 UART",
2284 .type = PORT_S3C6400,
2285 .has_divslot = 1,
2286 .rx_fifomask = S5PV210_UFSTAT_RXMASK,
2287 .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT,
2288 .rx_fifofull = S5PV210_UFSTAT_RXFULL,
2289 .tx_fifofull = S5PV210_UFSTAT_TXFULL,
2290 .tx_fifomask = S5PV210_UFSTAT_TXMASK,
2291 .tx_fifoshift = S5PV210_UFSTAT_TXSHIFT,
2292 .def_clk_sel = S3C2410_UCON_CLKSEL0,
2293 .num_clks = 2,
2294 .clksel_mask = S5PV210_UCON_CLKMASK,
2295 .clksel_shift = S5PV210_UCON_CLKSHIFT,
2296 },
2297 .def_cfg = &(struct s3c2410_uartcfg) {
2298 .ucon = S5PV210_UCON_DEFAULT,
2299 .ufcon = S5PV210_UFCON_DEFAULT,
2300 },
2301 .fifosize = { 256, 64, 16, 16 },
2302};
2303#define S5PV210_SERIAL_DRV_DATA ((kernel_ulong_t)&s5pv210_serial_drv_data)
2304#else
2305#define S5PV210_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2306#endif
b497549a 2307
33f88136 2308#if defined(CONFIG_ARCH_EXYNOS)
31ec77ac
CC		 2309#define EXYNOS_COMMON_SERIAL_DRV_DATA \
2310 .info = &(struct s3c24xx_uart_info) { \
2311 .name = "Samsung Exynos UART", \
2312 .type = PORT_S3C6400, \
2313 .has_divslot = 1, \
2314 .rx_fifomask = S5PV210_UFSTAT_RXMASK, \
2315 .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT, \
2316 .rx_fifofull = S5PV210_UFSTAT_RXFULL, \
2317 .tx_fifofull = S5PV210_UFSTAT_TXFULL, \
2318 .tx_fifomask = S5PV210_UFSTAT_TXMASK, \
2319 .tx_fifoshift = S5PV210_UFSTAT_TXSHIFT, \
2320 .def_clk_sel = S3C2410_UCON_CLKSEL0, \
2321 .num_clks = 1, \
2322 .clksel_mask = 0, \
2323 .clksel_shift = 0, \
2324 }, \
2325 .def_cfg = &(struct s3c2410_uartcfg) { \
2326 .ucon = S5PV210_UCON_DEFAULT, \
2327 .ufcon = S5PV210_UFCON_DEFAULT, \
2328 .has_fracval = 1, \
2329 } \
2330
da121506 2331static struct s3c24xx_serial_drv_data exynos4210_serial_drv_data = {
31ec77ac 2332 EXYNOS_COMMON_SERIAL_DRV_DATA,
da121506
TA		 2333 .fifosize = { 256, 64, 16, 16 },
2334};
31ec77ac
CC		 2335
2336static struct s3c24xx_serial_drv_data exynos5433_serial_drv_data = {
2337 EXYNOS_COMMON_SERIAL_DRV_DATA,
2338 .fifosize = { 64, 256, 16, 256 },
2339};
2340
da121506 2341#define EXYNOS4210_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos4210_serial_drv_data)
31ec77ac 2342#define EXYNOS5433_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos5433_serial_drv_data)
da121506
TA		 2343#else
2344#define EXYNOS4210_SERIAL_DRV_DATA (kernel_ulong_t)NULL
31ec77ac 2345#define EXYNOS5433_SERIAL_DRV_DATA (kernel_ulong_t)NULL
da121506 2346#endif
b497549a 2347
24ee4df1 2348static const struct platform_device_id s3c24xx_serial_driver_ids[] = {
da121506
TA		 2349 {
2350 .name = "s3c2410-uart",
2351 .driver_data = S3C2410_SERIAL_DRV_DATA,
2352 }, {
2353 .name = "s3c2412-uart",
2354 .driver_data = S3C2412_SERIAL_DRV_DATA,
2355 }, {
2356 .name = "s3c2440-uart",
2357 .driver_data = S3C2440_SERIAL_DRV_DATA,
2358 }, {
2359 .name = "s3c6400-uart",
2360 .driver_data = S3C6400_SERIAL_DRV_DATA,
2361 }, {
2362 .name = "s5pv210-uart",
2363 .driver_data = S5PV210_SERIAL_DRV_DATA,
2364 }, {
2365 .name = "exynos4210-uart",
2366 .driver_data = EXYNOS4210_SERIAL_DRV_DATA,
31ec77ac
CC		 2367 }, {
2368 .name = "exynos5433-uart",
2369 .driver_data = EXYNOS5433_SERIAL_DRV_DATA,
da121506
TA		 2370 },
2371 { },
2372};
2373MODULE_DEVICE_TABLE(platform, s3c24xx_serial_driver_ids);
2374
26c919e1
TA		 2375#ifdef CONFIG_OF
2376static const struct of_device_id s3c24xx_uart_dt_match[] = {
666ca0b9
HS		 2377 { .compatible = "samsung,s3c2410-uart",
2378 .data = (void *)S3C2410_SERIAL_DRV_DATA },
2379 { .compatible = "samsung,s3c2412-uart",
2380 .data = (void *)S3C2412_SERIAL_DRV_DATA },
2381 { .compatible = "samsung,s3c2440-uart",
2382 .data = (void *)S3C2440_SERIAL_DRV_DATA },
2383 { .compatible = "samsung,s3c6400-uart",
2384 .data = (void *)S3C6400_SERIAL_DRV_DATA },
2385 { .compatible = "samsung,s5pv210-uart",
2386 .data = (void *)S5PV210_SERIAL_DRV_DATA },
26c919e1 2387 { .compatible = "samsung,exynos4210-uart",
a169a888 2388 .data = (void *)EXYNOS4210_SERIAL_DRV_DATA },
31ec77ac
CC		 2389 { .compatible = "samsung,exynos5433-uart",
2390 .data = (void *)EXYNOS5433_SERIAL_DRV_DATA },
26c919e1
TA		 2391 {},
2392};
2393MODULE_DEVICE_TABLE(of, s3c24xx_uart_dt_match);
26c919e1
TA		 2394#endif
2395
da121506
TA		 2396static struct platform_driver samsung_serial_driver = {
2397 .probe = s3c24xx_serial_probe,
2d47b716 2398 .remove = s3c24xx_serial_remove,
da121506
TA		 2399 .id_table = s3c24xx_serial_driver_ids,
2400 .driver = {
2401 .name = "samsung-uart",
da121506 2402 .pm = SERIAL_SAMSUNG_PM_OPS,
905f4ba2 2403 .of_match_table = of_match_ptr(s3c24xx_uart_dt_match),
da121506
TA		 2404 },
2405};
b497549a 2406
6f134c3c 2407module_platform_driver(samsung_serial_driver);
b497549a 2408
c3bda295 2409#ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
b94ba032
TF		 2410/*
2411 * Early console.
2412 */
2413
2414struct samsung_early_console_data {
2415 u32 txfull_mask;
2416};
2417
2418static void samsung_early_busyuart(struct uart_port *port)
2419{
2420 while (!(readl(port->membase + S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXFE))
2421 ;
2422}
2423
2424static void samsung_early_busyuart_fifo(struct uart_port *port)
2425{
2426 struct samsung_early_console_data *data = port->private_data;
2427
2428 while (readl(port->membase + S3C2410_UFSTAT) & data->txfull_mask)
2429 ;
2430}
2431
2432static void samsung_early_putc(struct uart_port *port, int c)
2433{
2434 if (readl(port->membase + S3C2410_UFCON) & S3C2410_UFCON_FIFOMODE)
2435 samsung_early_busyuart_fifo(port);
2436 else
2437 samsung_early_busyuart(port);
2438
2439 writeb(c, port->membase + S3C2410_UTXH);
2440}
2441
2442static void samsung_early_write(struct console *con, const char *s, unsigned n)
2443{
2444 struct earlycon_device *dev = con->data;
2445
2446 uart_console_write(&dev->port, s, n, samsung_early_putc);
2447}
2448
2449static int __init samsung_early_console_setup(struct earlycon_device *device,
2450 const char *opt)
2451{
2452 if (!device->port.membase)
2453 return -ENODEV;
2454
2455 device->con->write = samsung_early_write;
2456 return 0;
2457}
2458
2459/* S3C2410 */
2460static struct samsung_early_console_data s3c2410_early_console_data = {
2461 .txfull_mask = S3C2410_UFSTAT_TXFULL,
2462};
2463
2464static int __init s3c2410_early_console_setup(struct earlycon_device *device,
2465 const char *opt)
2466{
2467 device->port.private_data = &s3c2410_early_console_data;
2468 return samsung_early_console_setup(device, opt);
2469}
2470OF_EARLYCON_DECLARE(s3c2410, "samsung,s3c2410-uart",
2471 s3c2410_early_console_setup);
2472EARLYCON_DECLARE(s3c2410, s3c2410_early_console_setup);
2473
2474/* S3C2412, S3C2440, S3C64xx */
2475static struct samsung_early_console_data s3c2440_early_console_data = {
2476 .txfull_mask = S3C2440_UFSTAT_TXFULL,
2477};
2478
2479static int __init s3c2440_early_console_setup(struct earlycon_device *device,
2480 const char *opt)
2481{
2482 device->port.private_data = &s3c2440_early_console_data;
2483 return samsung_early_console_setup(device, opt);
2484}
2485OF_EARLYCON_DECLARE(s3c2412, "samsung,s3c2412-uart",
2486 s3c2440_early_console_setup);
2487OF_EARLYCON_DECLARE(s3c2440, "samsung,s3c2440-uart",
2488 s3c2440_early_console_setup);
2489OF_EARLYCON_DECLARE(s3c6400, "samsung,s3c6400-uart",
2490 s3c2440_early_console_setup);
2491EARLYCON_DECLARE(s3c2412, s3c2440_early_console_setup);
2492EARLYCON_DECLARE(s3c2440, s3c2440_early_console_setup);
2493EARLYCON_DECLARE(s3c6400, s3c2440_early_console_setup);
2494
2495/* S5PV210, EXYNOS */
2496static struct samsung_early_console_data s5pv210_early_console_data = {
2497 .txfull_mask = S5PV210_UFSTAT_TXFULL,
2498};
2499
2500static int __init s5pv210_early_console_setup(struct earlycon_device *device,
2501 const char *opt)
2502{
2503 device->port.private_data = &s5pv210_early_console_data;
2504 return samsung_early_console_setup(device, opt);
2505}
2506OF_EARLYCON_DECLARE(s5pv210, "samsung,s5pv210-uart",
2507 s5pv210_early_console_setup);
2508OF_EARLYCON_DECLARE(exynos4210, "samsung,exynos4210-uart",
2509 s5pv210_early_console_setup);
2510EARLYCON_DECLARE(s5pv210, s5pv210_early_console_setup);
2511EARLYCON_DECLARE(exynos4210, s5pv210_early_console_setup);
c3bda295 2512#endif
b94ba032 2513
da121506 2514MODULE_ALIAS("platform:samsung-uart");
b497549a
BD		 2515MODULE_DESCRIPTION("Samsung SoC Serial port driver");
2516MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
2517MODULE_LICENSE("GPL v2");
Linux 6.x block layer and io_uring tree(s)