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serial: samsung: add dma reqest/release functions
[linux-2.6-block.git] / drivers / tty / serial / samsung.c
CommitLineData
99edb3d1 1/*
b497549a
BD		 2 * Driver core for Samsung SoC onboard UARTs.
3 *
ccae941e 4 * Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics
b497549a
BD		 5 * http://armlinux.simtec.co.uk/
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12/* Hote on 2410 error handling
13 *
14 * The s3c2410 manual has a love/hate affair with the contents of the
15 * UERSTAT register in the UART blocks, and keeps marking some of the
16 * error bits as reserved. Having checked with the s3c2410x01,
17 * it copes with BREAKs properly, so I am happy to ignore the RESERVED
18 * feature from the latter versions of the manual.
19 *
20 * If it becomes aparrent that latter versions of the 2410 remove these
21 * bits, then action will have to be taken to differentiate the versions
22 * and change the policy on BREAK
23 *
24 * BJD, 04-Nov-2004
25*/
26
27#if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
28#define SUPPORT_SYSRQ
29#endif
30
62c37eed
RB		 31#include <linux/dmaengine.h>
32#include <linux/dma-mapping.h>
33#include <linux/slab.h>
b497549a
BD		 34#include <linux/module.h>
35#include <linux/ioport.h>
36#include <linux/io.h>
37#include <linux/platform_device.h>
38#include <linux/init.h>
39#include <linux/sysrq.h>
40#include <linux/console.h>
41#include <linux/tty.h>
42#include <linux/tty_flip.h>
43#include <linux/serial_core.h>
44#include <linux/serial.h>
9ee51f01 45#include <linux/serial_s3c.h>
b497549a
BD		 46#include <linux/delay.h>
47#include <linux/clk.h>
30555476 48#include <linux/cpufreq.h>
26c919e1 49#include <linux/of.h>
b497549a
BD		 50
51#include <asm/irq.h>
52
b497549a
BD		 53#include "samsung.h"
54
e4ac92df
JP		 55#if defined(CONFIG_SERIAL_SAMSUNG_DEBUG) && \
56 defined(CONFIG_DEBUG_LL) && \
57 !defined(MODULE)
58
59extern void printascii(const char *);
60
61__printf(1, 2)
62static void dbg(const char *fmt, ...)
63{
64 va_list va;
65 char buff[256];
66
67 va_start(va, fmt);
a859c8b2 68 vscnprintf(buff, sizeof(buff), fmt, va);
e4ac92df
JP		 69 va_end(va);
70
71 printascii(buff);
72}
73
74#else
75#define dbg(fmt, ...) do { if (0) no_printk(fmt, ##__VA_ARGS__); } while (0)
76#endif
77
b497549a
BD		 78/* UART name and device definitions */
79
80#define S3C24XX_SERIAL_NAME "ttySAC"
81#define S3C24XX_SERIAL_MAJOR 204
82#define S3C24XX_SERIAL_MINOR 64
83
b497549a
BD		 84/* macros to change one thing to another */
85
86#define tx_enabled(port) ((port)->unused[0])
87#define rx_enabled(port) ((port)->unused[1])
88
25985edc 89/* flag to ignore all characters coming in */
b497549a
BD		 90#define RXSTAT_DUMMY_READ (0x10000000)
91
92static inline struct s3c24xx_uart_port *to_ourport(struct uart_port *port)
93{
94 return container_of(port, struct s3c24xx_uart_port, port);
95}
96
97/* translate a port to the device name */
98
99static inline const char *s3c24xx_serial_portname(struct uart_port *port)
100{
101 return to_platform_device(port->dev)->name;
102}
103
104static int s3c24xx_serial_txempty_nofifo(struct uart_port *port)
105{
9303ac15 106 return rd_regl(port, S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE;
b497549a
BD		 107}
108
88bb4ea1
TA		 109/*
110 * s3c64xx and later SoC's include the interrupt mask and status registers in
111 * the controller itself, unlike the s3c24xx SoC's which have these registers
112 * in the interrupt controller. Check if the port type is s3c64xx or higher.
113 */
114static int s3c24xx_serial_has_interrupt_mask(struct uart_port *port)
115{
116 return to_ourport(port)->info->type == PORT_S3C6400;
117}
118
b497549a
BD		 119static void s3c24xx_serial_rx_enable(struct uart_port *port)
120{
121 unsigned long flags;
122 unsigned int ucon, ufcon;
123 int count = 10000;
124
125 spin_lock_irqsave(&port->lock, flags);
126
127 while (--count && !s3c24xx_serial_txempty_nofifo(port))
128 udelay(100);
129
130 ufcon = rd_regl(port, S3C2410_UFCON);
131 ufcon |= S3C2410_UFCON_RESETRX;
132 wr_regl(port, S3C2410_UFCON, ufcon);
133
134 ucon = rd_regl(port, S3C2410_UCON);
135 ucon |= S3C2410_UCON_RXIRQMODE;
136 wr_regl(port, S3C2410_UCON, ucon);
137
138 rx_enabled(port) = 1;
139 spin_unlock_irqrestore(&port->lock, flags);
140}
141
142static void s3c24xx_serial_rx_disable(struct uart_port *port)
143{
144 unsigned long flags;
145 unsigned int ucon;
146
147 spin_lock_irqsave(&port->lock, flags);
148
149 ucon = rd_regl(port, S3C2410_UCON);
150 ucon &= ~S3C2410_UCON_RXIRQMODE;
151 wr_regl(port, S3C2410_UCON, ucon);
152
153 rx_enabled(port) = 0;
154 spin_unlock_irqrestore(&port->lock, flags);
155}
156
157static void s3c24xx_serial_stop_tx(struct uart_port *port)
158{
b73c289c
BD		 159 struct s3c24xx_uart_port *ourport = to_ourport(port);
160
b497549a 161 if (tx_enabled(port)) {
88bb4ea1
TA		 162 if (s3c24xx_serial_has_interrupt_mask(port))
163 __set_bit(S3C64XX_UINTM_TXD,
164 portaddrl(port, S3C64XX_UINTM));
165 else
166 disable_irq_nosync(ourport->tx_irq);
b497549a
BD		 167 tx_enabled(port) = 0;
168 if (port->flags & UPF_CONS_FLOW)
169 s3c24xx_serial_rx_enable(port);
170 }
171}
172
173static void s3c24xx_serial_start_tx(struct uart_port *port)
174{
b73c289c
BD		 175 struct s3c24xx_uart_port *ourport = to_ourport(port);
176
b497549a
BD		 177 if (!tx_enabled(port)) {
178 if (port->flags & UPF_CONS_FLOW)
179 s3c24xx_serial_rx_disable(port);
180
88bb4ea1
TA		 181 if (s3c24xx_serial_has_interrupt_mask(port))
182 __clear_bit(S3C64XX_UINTM_TXD,
183 portaddrl(port, S3C64XX_UINTM));
184 else
185 enable_irq(ourport->tx_irq);
b497549a
BD		 186 tx_enabled(port) = 1;
187 }
188}
189
b497549a
BD		 190static void s3c24xx_serial_stop_rx(struct uart_port *port)
191{
b73c289c
BD		 192 struct s3c24xx_uart_port *ourport = to_ourport(port);
193
b497549a
BD		 194 if (rx_enabled(port)) {
195 dbg("s3c24xx_serial_stop_rx: port=%p\n", port);
88bb4ea1
TA		 196 if (s3c24xx_serial_has_interrupt_mask(port))
197 __set_bit(S3C64XX_UINTM_RXD,
198 portaddrl(port, S3C64XX_UINTM));
199 else
200 disable_irq_nosync(ourport->rx_irq);
b497549a
BD		 201 rx_enabled(port) = 0;
202 }
203}
204
ef4aca70
RB		 205static inline struct s3c24xx_uart_info
206 *s3c24xx_port_to_info(struct uart_port *port)
b497549a
BD		 207{
208 return to_ourport(port)->info;
209}
210
ef4aca70
RB		 211static inline struct s3c2410_uartcfg
212 *s3c24xx_port_to_cfg(struct uart_port *port)
b497549a 213{
4d84e970
TA		 214 struct s3c24xx_uart_port *ourport;
215
b497549a
BD		 216 if (port->dev == NULL)
217 return NULL;
218
4d84e970
TA		 219 ourport = container_of(port, struct s3c24xx_uart_port, port);
220 return ourport->cfg;
b497549a
BD		 221}
222
223static int s3c24xx_serial_rx_fifocnt(struct s3c24xx_uart_port *ourport,
224 unsigned long ufstat)
225{
226 struct s3c24xx_uart_info *info = ourport->info;
227
228 if (ufstat & info->rx_fifofull)
da121506 229 return ourport->port.fifosize;
b497549a
BD		 230
231 return (ufstat & info->rx_fifomask) >> info->rx_fifoshift;
232}
233
234
235/* ? - where has parity gone?? */
236#define S3C2410_UERSTAT_PARITY (0x1000)
237
238static irqreturn_t
239s3c24xx_serial_rx_chars(int irq, void *dev_id)
240{
241 struct s3c24xx_uart_port *ourport = dev_id;
242 struct uart_port *port = &ourport->port;
b497549a 243 unsigned int ufcon, ch, flag, ufstat, uerstat;
c15c3747 244 unsigned long flags;
57850a50 245 int max_count = port->fifosize;
b497549a 246
c15c3747
TA		 247 spin_lock_irqsave(&port->lock, flags);
248
b497549a
BD		 249 while (max_count-- > 0) {
250 ufcon = rd_regl(port, S3C2410_UFCON);
251 ufstat = rd_regl(port, S3C2410_UFSTAT);
252
253 if (s3c24xx_serial_rx_fifocnt(ourport, ufstat) == 0)
254 break;
255
256 uerstat = rd_regl(port, S3C2410_UERSTAT);
257 ch = rd_regb(port, S3C2410_URXH);
258
259 if (port->flags & UPF_CONS_FLOW) {
260 int txe = s3c24xx_serial_txempty_nofifo(port);
261
262 if (rx_enabled(port)) {
263 if (!txe) {
264 rx_enabled(port) = 0;
265 continue;
266 }
267 } else {
268 if (txe) {
269 ufcon |= S3C2410_UFCON_RESETRX;
270 wr_regl(port, S3C2410_UFCON, ufcon);
271 rx_enabled(port) = 1;
f5693ea2
VK		 272 spin_unlock_irqrestore(&port->lock,
273 flags);
b497549a
BD		 274 goto out;
275 }
276 continue;
277 }
278 }
279
280 /* insert the character into the buffer */
281
282 flag = TTY_NORMAL;
283 port->icount.rx++;
284
285 if (unlikely(uerstat & S3C2410_UERSTAT_ANY)) {
286 dbg("rxerr: port ch=0x%02x, rxs=0x%08x\n",
287 ch, uerstat);
288
289 /* check for break */
290 if (uerstat & S3C2410_UERSTAT_BREAK) {
291 dbg("break!\n");
292 port->icount.brk++;
293 if (uart_handle_break(port))
9303ac15 294 goto ignore_char;
b497549a
BD		 295 }
296
297 if (uerstat & S3C2410_UERSTAT_FRAME)
298 port->icount.frame++;
299 if (uerstat & S3C2410_UERSTAT_OVERRUN)
300 port->icount.overrun++;
301
302 uerstat &= port->read_status_mask;
303
304 if (uerstat & S3C2410_UERSTAT_BREAK)
305 flag = TTY_BREAK;
306 else if (uerstat & S3C2410_UERSTAT_PARITY)
307 flag = TTY_PARITY;
308 else if (uerstat & (S3C2410_UERSTAT_FRAME |
309 S3C2410_UERSTAT_OVERRUN))
310 flag = TTY_FRAME;
311 }
312
313 if (uart_handle_sysrq_char(port, ch))
314 goto ignore_char;
315
316 uart_insert_char(port, uerstat, S3C2410_UERSTAT_OVERRUN,
317 ch, flag);
318
ef4aca70 319ignore_char:
b497549a
BD		 320 continue;
321 }
f5693ea2
VK		 322
323 spin_unlock_irqrestore(&port->lock, flags);
2e124b4a 324 tty_flip_buffer_push(&port->state->port);
b497549a 325
ef4aca70 326out:
b497549a
BD		 327 return IRQ_HANDLED;
328}
329
330static irqreturn_t s3c24xx_serial_tx_chars(int irq, void *id)
331{
332 struct s3c24xx_uart_port *ourport = id;
333 struct uart_port *port = &ourport->port;
ebd2c8f6 334 struct circ_buf *xmit = &port->state->xmit;
c15c3747 335 unsigned long flags;
57850a50 336 int count = port->fifosize;
b497549a 337
c15c3747
TA		 338 spin_lock_irqsave(&port->lock, flags);
339
b497549a
BD		 340 if (port->x_char) {
341 wr_regb(port, S3C2410_UTXH, port->x_char);
342 port->icount.tx++;
343 port->x_char = 0;
344 goto out;
345 }
346
25985edc 347 /* if there isn't anything more to transmit, or the uart is now
b497549a
BD		 348 * stopped, disable the uart and exit
349 */
350
351 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
352 s3c24xx_serial_stop_tx(port);
353 goto out;
354 }
355
356 /* try and drain the buffer... */
357
358 while (!uart_circ_empty(xmit) && count-- > 0) {
359 if (rd_regl(port, S3C2410_UFSTAT) & ourport->info->tx_fifofull)
360 break;
361
362 wr_regb(port, S3C2410_UTXH, xmit->buf[xmit->tail]);
363 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
364 port->icount.tx++;
365 }
366
c15c3747
TA		 367 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) {
368 spin_unlock(&port->lock);
b497549a 369 uart_write_wakeup(port);
c15c3747
TA		 370 spin_lock(&port->lock);
371 }
b497549a
BD		 372
373 if (uart_circ_empty(xmit))
374 s3c24xx_serial_stop_tx(port);
375
ef4aca70 376out:
c15c3747 377 spin_unlock_irqrestore(&port->lock, flags);
b497549a
BD		 378 return IRQ_HANDLED;
379}
380
88bb4ea1
TA		 381/* interrupt handler for s3c64xx and later SoC's.*/
382static irqreturn_t s3c64xx_serial_handle_irq(int irq, void *id)
383{
384 struct s3c24xx_uart_port *ourport = id;
385 struct uart_port *port = &ourport->port;
386 unsigned int pend = rd_regl(port, S3C64XX_UINTP);
88bb4ea1
TA		 387 irqreturn_t ret = IRQ_HANDLED;
388
88bb4ea1
TA		 389 if (pend & S3C64XX_UINTM_RXD_MSK) {
390 ret = s3c24xx_serial_rx_chars(irq, id);
391 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_RXD_MSK);
392 }
393 if (pend & S3C64XX_UINTM_TXD_MSK) {
394 ret = s3c24xx_serial_tx_chars(irq, id);
395 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_TXD_MSK);
396 }
88bb4ea1
TA		 397 return ret;
398}
399
b497549a
BD		 400static unsigned int s3c24xx_serial_tx_empty(struct uart_port *port)
401{
402 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
403 unsigned long ufstat = rd_regl(port, S3C2410_UFSTAT);
404 unsigned long ufcon = rd_regl(port, S3C2410_UFCON);
405
406 if (ufcon & S3C2410_UFCON_FIFOMODE) {
407 if ((ufstat & info->tx_fifomask) != 0 ||
408 (ufstat & info->tx_fifofull))
409 return 0;
410
411 return 1;
412 }
413
414 return s3c24xx_serial_txempty_nofifo(port);
415}
416
417/* no modem control lines */
418static unsigned int s3c24xx_serial_get_mctrl(struct uart_port *port)
419{
420 unsigned int umstat = rd_regb(port, S3C2410_UMSTAT);
421
422 if (umstat & S3C2410_UMSTAT_CTS)
423 return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
424 else
425 return TIOCM_CAR | TIOCM_DSR;
426}
427
428static void s3c24xx_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
429{
2d1e5a48
JMG		 430 unsigned int umcon = rd_regl(port, S3C2410_UMCON);
431
432 if (mctrl & TIOCM_RTS)
433 umcon |= S3C2410_UMCOM_RTS_LOW;
434 else
435 umcon &= ~S3C2410_UMCOM_RTS_LOW;
436
437 wr_regl(port, S3C2410_UMCON, umcon);
b497549a
BD		 438}
439
440static void s3c24xx_serial_break_ctl(struct uart_port *port, int break_state)
441{
442 unsigned long flags;
443 unsigned int ucon;
444
445 spin_lock_irqsave(&port->lock, flags);
446
447 ucon = rd_regl(port, S3C2410_UCON);
448
449 if (break_state)
450 ucon |= S3C2410_UCON_SBREAK;
451 else
452 ucon &= ~S3C2410_UCON_SBREAK;
453
454 wr_regl(port, S3C2410_UCON, ucon);
455
456 spin_unlock_irqrestore(&port->lock, flags);
457}
458
62c37eed
RB		 459static int s3c24xx_serial_request_dma(struct s3c24xx_uart_port *p)
460{
461 struct s3c24xx_uart_dma *dma = p->dma;
462 dma_cap_mask_t mask;
463 unsigned long flags;
464
465 /* Default slave configuration parameters */
466 dma->rx_conf.direction = DMA_DEV_TO_MEM;
467 dma->rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
468 dma->rx_conf.src_addr = p->port.mapbase + S3C2410_URXH;
469 dma->rx_conf.src_maxburst = 16;
470
471 dma->tx_conf.direction = DMA_MEM_TO_DEV;
472 dma->tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
473 dma->tx_conf.dst_addr = p->port.mapbase + S3C2410_UTXH;
474 if (dma_get_cache_alignment() >= 16)
475 dma->tx_conf.dst_maxburst = 16;
476 else
477 dma->tx_conf.dst_maxburst = 1;
478
479 dma_cap_zero(mask);
480 dma_cap_set(DMA_SLAVE, mask);
481
482 dma->rx_chan = dma_request_slave_channel_compat(mask, dma->fn,
483 dma->rx_param, p->port.dev, "rx");
484 if (!dma->rx_chan)
485 return -ENODEV;
486
487 dmaengine_slave_config(dma->rx_chan, &dma->rx_conf);
488
489 dma->tx_chan = dma_request_slave_channel_compat(mask, dma->fn,
490 dma->tx_param, p->port.dev, "tx");
491 if (!dma->tx_chan) {
492 dma_release_channel(dma->rx_chan);
493 return -ENODEV;
494 }
495
496 dmaengine_slave_config(dma->tx_chan, &dma->tx_conf);
497
498 /* RX buffer */
499 dma->rx_size = PAGE_SIZE;
500
501 dma->rx_buf = kmalloc(dma->rx_size, GFP_KERNEL);
502
503 if (!dma->rx_buf) {
504 dma_release_channel(dma->rx_chan);
505 dma_release_channel(dma->tx_chan);
506 return -ENOMEM;
507 }
508
509 dma->rx_addr = dma_map_single(dma->rx_chan->device->dev, dma->rx_buf,
510 dma->rx_size, DMA_FROM_DEVICE);
511
512 spin_lock_irqsave(&p->port.lock, flags);
513
514 /* TX buffer */
515 dma->tx_addr = dma_map_single(dma->tx_chan->device->dev,
516 p->port.state->xmit.buf,
517 UART_XMIT_SIZE, DMA_TO_DEVICE);
518
519 spin_unlock_irqrestore(&p->port.lock, flags);
520
521 return 0;
522}
523
524static void s3c24xx_serial_release_dma(struct s3c24xx_uart_port *p)
525{
526 struct s3c24xx_uart_dma *dma = p->dma;
527
528 if (dma->rx_chan) {
529 dmaengine_terminate_all(dma->rx_chan);
530 dma_unmap_single(dma->rx_chan->device->dev, dma->rx_addr,
531 dma->rx_size, DMA_FROM_DEVICE);
532 kfree(dma->rx_buf);
533 dma_release_channel(dma->rx_chan);
534 dma->rx_chan = NULL;
535 }
536
537 if (dma->tx_chan) {
538 dmaengine_terminate_all(dma->tx_chan);
539 dma_unmap_single(dma->tx_chan->device->dev, dma->tx_addr,
540 UART_XMIT_SIZE, DMA_TO_DEVICE);
541 dma_release_channel(dma->tx_chan);
542 dma->tx_chan = NULL;
543 }
544}
545
b497549a
BD		 546static void s3c24xx_serial_shutdown(struct uart_port *port)
547{
548 struct s3c24xx_uart_port *ourport = to_ourport(port);
549
550 if (ourport->tx_claimed) {
88bb4ea1
TA		 551 if (!s3c24xx_serial_has_interrupt_mask(port))
552 free_irq(ourport->tx_irq, ourport);
b497549a
BD		 553 tx_enabled(port) = 0;
554 ourport->tx_claimed = 0;
555 }
556
557 if (ourport->rx_claimed) {
88bb4ea1
TA		 558 if (!s3c24xx_serial_has_interrupt_mask(port))
559 free_irq(ourport->rx_irq, ourport);
b497549a
BD		 560 ourport->rx_claimed = 0;
561 rx_enabled(port) = 0;
562 }
b497549a 563
88bb4ea1
TA		 564 /* Clear pending interrupts and mask all interrupts */
565 if (s3c24xx_serial_has_interrupt_mask(port)) {
b6ad2935
TF		 566 free_irq(port->irq, ourport);
567
88bb4ea1
TA		 568 wr_regl(port, S3C64XX_UINTP, 0xf);
569 wr_regl(port, S3C64XX_UINTM, 0xf);
570 }
62c37eed
RB		 571
572 if (ourport->dma)
573 s3c24xx_serial_release_dma(ourport);
574
88bb4ea1 575}
b497549a
BD		 576
577static int s3c24xx_serial_startup(struct uart_port *port)
578{
579 struct s3c24xx_uart_port *ourport = to_ourport(port);
580 int ret;
581
e4ac92df
JP		 582 dbg("s3c24xx_serial_startup: port=%p (%08llx,%p)\n",
583 port, (unsigned long long)port->mapbase, port->membase);
b497549a
BD		 584
585 rx_enabled(port) = 1;
586
b73c289c 587 ret = request_irq(ourport->rx_irq, s3c24xx_serial_rx_chars, 0,
b497549a
BD		 588 s3c24xx_serial_portname(port), ourport);
589
590 if (ret != 0) {
d20925e1 591 dev_err(port->dev, "cannot get irq %d\n", ourport->rx_irq);
b497549a
BD		 592 return ret;
593 }
594
595 ourport->rx_claimed = 1;
596
597 dbg("requesting tx irq...\n");
598
599 tx_enabled(port) = 1;
600
b73c289c 601 ret = request_irq(ourport->tx_irq, s3c24xx_serial_tx_chars, 0,
b497549a
BD		 602 s3c24xx_serial_portname(port), ourport);
603
604 if (ret) {
d20925e1 605 dev_err(port->dev, "cannot get irq %d\n", ourport->tx_irq);
b497549a
BD		 606 goto err;
607 }
608
609 ourport->tx_claimed = 1;
610
611 dbg("s3c24xx_serial_startup ok\n");
612
613 /* the port reset code should have done the correct
614 * register setup for the port controls */
615
616 return ret;
617
ef4aca70 618err:
b497549a
BD		 619 s3c24xx_serial_shutdown(port);
620 return ret;
621}
622
88bb4ea1
TA		 623static int s3c64xx_serial_startup(struct uart_port *port)
624{
625 struct s3c24xx_uart_port *ourport = to_ourport(port);
626 int ret;
627
e4ac92df
JP		 628 dbg("s3c64xx_serial_startup: port=%p (%08llx,%p)\n",
629 port, (unsigned long long)port->mapbase, port->membase);
88bb4ea1 630
b6ad2935 631 wr_regl(port, S3C64XX_UINTM, 0xf);
62c37eed
RB		 632 if (ourport->dma) {
633 ret = s3c24xx_serial_request_dma(ourport);
634 if (ret < 0) {
635 dev_warn(port->dev, "DMA request failed\n");
636 return ret;
637 }
638 }
b6ad2935 639
88bb4ea1
TA		 640 ret = request_irq(port->irq, s3c64xx_serial_handle_irq, IRQF_SHARED,
641 s3c24xx_serial_portname(port), ourport);
642 if (ret) {
d20925e1 643 dev_err(port->dev, "cannot get irq %d\n", port->irq);
88bb4ea1
TA		 644 return ret;
645 }
646
647 /* For compatibility with s3c24xx Soc's */
648 rx_enabled(port) = 1;
649 ourport->rx_claimed = 1;
650 tx_enabled(port) = 0;
651 ourport->tx_claimed = 1;
652
653 /* Enable Rx Interrupt */
654 __clear_bit(S3C64XX_UINTM_RXD, portaddrl(port, S3C64XX_UINTM));
655 dbg("s3c64xx_serial_startup ok\n");
656 return ret;
657}
658
b497549a
BD		 659/* power power management control */
660
661static void s3c24xx_serial_pm(struct uart_port *port, unsigned int level,
662 unsigned int old)
663{
664 struct s3c24xx_uart_port *ourport = to_ourport(port);
1ff383a4 665 int timeout = 10000;
b497549a 666
30555476
BD		 667 ourport->pm_level = level;
668
b497549a
BD		 669 switch (level) {
670 case 3:
1ff383a4
RB		 671 while (--timeout && !s3c24xx_serial_txempty_nofifo(port))
672 udelay(100);
673
7cd88831 674 if (!IS_ERR(ourport->baudclk))
9484b009 675 clk_disable_unprepare(ourport->baudclk);
b497549a 676
9484b009 677 clk_disable_unprepare(ourport->clk);
b497549a
BD		 678 break;
679
680 case 0:
9484b009 681 clk_prepare_enable(ourport->clk);
b497549a 682
7cd88831 683 if (!IS_ERR(ourport->baudclk))
9484b009 684 clk_prepare_enable(ourport->baudclk);
b497549a
BD		 685
686 break;
687 default:
d20925e1 688 dev_err(port->dev, "s3c24xx_serial: unknown pm %d\n", level);
b497549a
BD		 689 }
690}
691
692/* baud rate calculation
693 *
694 * The UARTs on the S3C2410/S3C2440 can take their clocks from a number
695 * of different sources, including the peripheral clock ("pclk") and an
696 * external clock ("uclk"). The S3C2440 also adds the core clock ("fclk")
697 * with a programmable extra divisor.
698 *
699 * The following code goes through the clock sources, and calculates the
700 * baud clocks (and the resultant actual baud rates) and then tries to
701 * pick the closest one and select that.
702 *
703*/
704
5f5a7a55 705#define MAX_CLK_NAME_LENGTH 15
b497549a 706
5f5a7a55 707static inline int s3c24xx_serial_getsource(struct uart_port *port)
b497549a
BD		 708{
709 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
5f5a7a55 710 unsigned int ucon;
b497549a 711
5f5a7a55
TA		 712 if (info->num_clks == 1)
713 return 0;
b497549a 714
5f5a7a55
TA		 715 ucon = rd_regl(port, S3C2410_UCON);
716 ucon &= info->clksel_mask;
717 return ucon >> info->clksel_shift;
b497549a
BD		 718}
719
5f5a7a55
TA		 720static void s3c24xx_serial_setsource(struct uart_port *port,
721 unsigned int clk_sel)
b497549a 722{
5f5a7a55
TA		 723 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
724 unsigned int ucon;
b497549a 725
5f5a7a55
TA		 726 if (info->num_clks == 1)
727 return;
090f848d 728
5f5a7a55
TA		 729 ucon = rd_regl(port, S3C2410_UCON);
730 if ((ucon & info->clksel_mask) >> info->clksel_shift == clk_sel)
731 return;
b497549a 732
5f5a7a55
TA		 733 ucon &= ~info->clksel_mask;
734 ucon |= clk_sel << info->clksel_shift;
735 wr_regl(port, S3C2410_UCON, ucon);
b497549a
BD		 736}
737
5f5a7a55
TA		 738static unsigned int s3c24xx_serial_getclk(struct s3c24xx_uart_port *ourport,
739 unsigned int req_baud, struct clk **best_clk,
740 unsigned int *clk_num)
b497549a 741{
5f5a7a55
TA		 742 struct s3c24xx_uart_info *info = ourport->info;
743 struct clk *clk;
744 unsigned long rate;
745 unsigned int cnt, baud, quot, clk_sel, best_quot = 0;
746 char clkname[MAX_CLK_NAME_LENGTH];
747 int calc_deviation, deviation = (1 << 30) - 1;
748
5f5a7a55
TA		 749 clk_sel = (ourport->cfg->clk_sel) ? ourport->cfg->clk_sel :
750 ourport->info->def_clk_sel;
751 for (cnt = 0; cnt < info->num_clks; cnt++) {
752 if (!(clk_sel & (1 << cnt)))
753 continue;
754
755 sprintf(clkname, "clk_uart_baud%d", cnt);
756 clk = clk_get(ourport->port.dev, clkname);
7cd88831 757 if (IS_ERR(clk))
5f5a7a55
TA		 758 continue;
759
760 rate = clk_get_rate(clk);
761 if (!rate)
762 continue;
763
764 if (ourport->info->has_divslot) {
765 unsigned long div = rate / req_baud;
766
767 /* The UDIVSLOT register on the newer UARTs allows us to
768 * get a divisor adjustment of 1/16th on the baud clock.
769 *
770 * We don't keep the UDIVSLOT value (the 16ths we
771 * calculated by not multiplying the baud by 16) as it
772 * is easy enough to recalculate.
773 */
774
775 quot = div / 16;
776 baud = rate / div;
777 } else {
778 quot = (rate + (8 * req_baud)) / (16 * req_baud);
779 baud = rate / (quot * 16);
b497549a 780 }
5f5a7a55 781 quot--;
b497549a 782
5f5a7a55
TA		 783 calc_deviation = req_baud - baud;
784 if (calc_deviation < 0)
785 calc_deviation = -calc_deviation;
b497549a 786
5f5a7a55
TA		 787 if (calc_deviation < deviation) {
788 *best_clk = clk;
789 best_quot = quot;
790 *clk_num = cnt;
791 deviation = calc_deviation;
b497549a
BD		 792 }
793 }
794
5f5a7a55 795 return best_quot;
b497549a
BD		 796}
797
090f848d
BD		 798/* udivslot_table[]
799 *
800 * This table takes the fractional value of the baud divisor and gives
801 * the recommended setting for the UDIVSLOT register.
802 */
803static u16 udivslot_table[16] = {
804 [0] = 0x0000,
805 [1] = 0x0080,
806 [2] = 0x0808,
807 [3] = 0x0888,
808 [4] = 0x2222,
809 [5] = 0x4924,
810 [6] = 0x4A52,
811 [7] = 0x54AA,
812 [8] = 0x5555,
813 [9] = 0xD555,
814 [10] = 0xD5D5,
815 [11] = 0xDDD5,
816 [12] = 0xDDDD,
817 [13] = 0xDFDD,
818 [14] = 0xDFDF,
819 [15] = 0xFFDF,
820};
821
b497549a
BD		 822static void s3c24xx_serial_set_termios(struct uart_port *port,
823 struct ktermios *termios,
824 struct ktermios *old)
825{
826 struct s3c2410_uartcfg *cfg = s3c24xx_port_to_cfg(port);
827 struct s3c24xx_uart_port *ourport = to_ourport(port);
7cd88831 828 struct clk *clk = ERR_PTR(-EINVAL);
b497549a 829 unsigned long flags;
5f5a7a55 830 unsigned int baud, quot, clk_sel = 0;
b497549a
BD		 831 unsigned int ulcon;
832 unsigned int umcon;
090f848d 833 unsigned int udivslot = 0;
b497549a
BD		 834
835 /*
836 * We don't support modem control lines.
837 */
838 termios->c_cflag &= ~(HUPCL | CMSPAR);
839 termios->c_cflag |= CLOCAL;
840
841 /*
842 * Ask the core to calculate the divisor for us.
843 */
844
845 baud = uart_get_baud_rate(port, termios, old, 0, 115200*8);
5f5a7a55 846 quot = s3c24xx_serial_getclk(ourport, baud, &clk, &clk_sel);
b497549a
BD		 847 if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST)
848 quot = port->custom_divisor;
7cd88831 849 if (IS_ERR(clk))
5f5a7a55 850 return;
b497549a
BD		 851
852 /* check to see if we need to change clock source */
853
5f5a7a55
TA		 854 if (ourport->baudclk != clk) {
855 s3c24xx_serial_setsource(port, clk_sel);
b497549a 856
7cd88831 857 if (!IS_ERR(ourport->baudclk)) {
9484b009 858 clk_disable_unprepare(ourport->baudclk);
7cd88831 859 ourport->baudclk = ERR_PTR(-EINVAL);
b497549a
BD		 860 }
861
9484b009 862 clk_prepare_enable(clk);
b497549a 863
b497549a 864 ourport->baudclk = clk;
30555476 865 ourport->baudclk_rate = clk ? clk_get_rate(clk) : 0;
b497549a
BD		 866 }
867
090f848d
BD		 868 if (ourport->info->has_divslot) {
869 unsigned int div = ourport->baudclk_rate / baud;
870
8b526ae4
JL		 871 if (cfg->has_fracval) {
872 udivslot = (div & 15);
873 dbg("fracval = %04x\n", udivslot);
874 } else {
875 udivslot = udivslot_table[div & 15];
876 dbg("udivslot = %04x (div %d)\n", udivslot, div & 15);
877 }
090f848d
BD		 878 }
879
b497549a
BD		 880 switch (termios->c_cflag & CSIZE) {
881 case CS5:
882 dbg("config: 5bits/char\n");
883 ulcon = S3C2410_LCON_CS5;
884 break;
885 case CS6:
886 dbg("config: 6bits/char\n");
887 ulcon = S3C2410_LCON_CS6;
888 break;
889 case CS7:
890 dbg("config: 7bits/char\n");
891 ulcon = S3C2410_LCON_CS7;
892 break;
893 case CS8:
894 default:
895 dbg("config: 8bits/char\n");
896 ulcon = S3C2410_LCON_CS8;
897 break;
898 }
899
900 /* preserve original lcon IR settings */
901 ulcon |= (cfg->ulcon & S3C2410_LCON_IRM);
902
903 if (termios->c_cflag & CSTOPB)
904 ulcon |= S3C2410_LCON_STOPB;
905
b497549a
BD		 906 if (termios->c_cflag & PARENB) {
907 if (termios->c_cflag & PARODD)
908 ulcon |= S3C2410_LCON_PODD;
909 else
910 ulcon |= S3C2410_LCON_PEVEN;
911 } else {
912 ulcon |= S3C2410_LCON_PNONE;
913 }
914
915 spin_lock_irqsave(&port->lock, flags);
916
090f848d
BD		 917 dbg("setting ulcon to %08x, brddiv to %d, udivslot %08x\n",
918 ulcon, quot, udivslot);
b497549a
BD		 919
920 wr_regl(port, S3C2410_ULCON, ulcon);
921 wr_regl(port, S3C2410_UBRDIV, quot);
2d1e5a48
JMG		 922
923 umcon = rd_regl(port, S3C2410_UMCON);
924 if (termios->c_cflag & CRTSCTS) {
925 umcon |= S3C2410_UMCOM_AFC;
926 /* Disable RTS when RX FIFO contains 63 bytes */
927 umcon &= ~S3C2412_UMCON_AFC_8;
928 } else {
929 umcon &= ~S3C2410_UMCOM_AFC;
930 }
b497549a
BD		 931 wr_regl(port, S3C2410_UMCON, umcon);
932
090f848d
BD		 933 if (ourport->info->has_divslot)
934 wr_regl(port, S3C2443_DIVSLOT, udivslot);
935
b497549a
BD		 936 dbg("uart: ulcon = 0x%08x, ucon = 0x%08x, ufcon = 0x%08x\n",
937 rd_regl(port, S3C2410_ULCON),
938 rd_regl(port, S3C2410_UCON),
939 rd_regl(port, S3C2410_UFCON));
940
941 /*
942 * Update the per-port timeout.
943 */
944 uart_update_timeout(port, termios->c_cflag, baud);
945
946 /*
947 * Which character status flags are we interested in?
948 */
949 port->read_status_mask = S3C2410_UERSTAT_OVERRUN;
950 if (termios->c_iflag & INPCK)
ef4aca70
RB		 951 port->read_status_mask |= S3C2410_UERSTAT_FRAME |
952 S3C2410_UERSTAT_PARITY;
b497549a
BD		 953 /*
954 * Which character status flags should we ignore?
955 */
956 port->ignore_status_mask = 0;
957 if (termios->c_iflag & IGNPAR)
958 port->ignore_status_mask |= S3C2410_UERSTAT_OVERRUN;
959 if (termios->c_iflag & IGNBRK && termios->c_iflag & IGNPAR)
960 port->ignore_status_mask |= S3C2410_UERSTAT_FRAME;
961
962 /*
963 * Ignore all characters if CREAD is not set.
964 */
965 if ((termios->c_cflag & CREAD) == 0)
966 port->ignore_status_mask |= RXSTAT_DUMMY_READ;
967
968 spin_unlock_irqrestore(&port->lock, flags);
969}
970
971static const char *s3c24xx_serial_type(struct uart_port *port)
972{
973 switch (port->type) {
974 case PORT_S3C2410:
975 return "S3C2410";
976 case PORT_S3C2440:
977 return "S3C2440";
978 case PORT_S3C2412:
979 return "S3C2412";
b690ace5
BD		 980 case PORT_S3C6400:
981 return "S3C6400/10";
b497549a
BD		 982 default:
983 return NULL;
984 }
985}
986
987#define MAP_SIZE (0x100)
988
989static void s3c24xx_serial_release_port(struct uart_port *port)
990{
991 release_mem_region(port->mapbase, MAP_SIZE);
992}
993
994static int s3c24xx_serial_request_port(struct uart_port *port)
995{
996 const char *name = s3c24xx_serial_portname(port);
997 return request_mem_region(port->mapbase, MAP_SIZE, name) ? 0 : -EBUSY;
998}
999
1000static void s3c24xx_serial_config_port(struct uart_port *port, int flags)
1001{
1002 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1003
1004 if (flags & UART_CONFIG_TYPE &&
1005 s3c24xx_serial_request_port(port) == 0)
1006 port->type = info->type;
1007}
1008
1009/*
1010 * verify the new serial_struct (for TIOCSSERIAL).
1011 */
1012static int
1013s3c24xx_serial_verify_port(struct uart_port *port, struct serial_struct *ser)
1014{
1015 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1016
1017 if (ser->type != PORT_UNKNOWN && ser->type != info->type)
1018 return -EINVAL;
1019
1020 return 0;
1021}
1022
1023
1024#ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
1025
1026static struct console s3c24xx_serial_console;
1027
93b5c032
JP		 1028static int __init s3c24xx_serial_console_init(void)
1029{
1030 register_console(&s3c24xx_serial_console);
1031 return 0;
1032}
1033console_initcall(s3c24xx_serial_console_init);
1034
b497549a
BD		 1035#define S3C24XX_SERIAL_CONSOLE &s3c24xx_serial_console
1036#else
1037#define S3C24XX_SERIAL_CONSOLE NULL
1038#endif
1039
84f57d9e 1040#if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
93b5c032
JP		 1041static int s3c24xx_serial_get_poll_char(struct uart_port *port);
1042static void s3c24xx_serial_put_poll_char(struct uart_port *port,
1043 unsigned char c);
1044#endif
1045
b497549a
BD		 1046static struct uart_ops s3c24xx_serial_ops = {
1047 .pm = s3c24xx_serial_pm,
1048 .tx_empty = s3c24xx_serial_tx_empty,
1049 .get_mctrl = s3c24xx_serial_get_mctrl,
1050 .set_mctrl = s3c24xx_serial_set_mctrl,
1051 .stop_tx = s3c24xx_serial_stop_tx,
1052 .start_tx = s3c24xx_serial_start_tx,
1053 .stop_rx = s3c24xx_serial_stop_rx,
b497549a
BD		 1054 .break_ctl = s3c24xx_serial_break_ctl,
1055 .startup = s3c24xx_serial_startup,
1056 .shutdown = s3c24xx_serial_shutdown,
1057 .set_termios = s3c24xx_serial_set_termios,
1058 .type = s3c24xx_serial_type,
1059 .release_port = s3c24xx_serial_release_port,
1060 .request_port = s3c24xx_serial_request_port,
1061 .config_port = s3c24xx_serial_config_port,
1062 .verify_port = s3c24xx_serial_verify_port,
84f57d9e 1063#if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
93b5c032
JP		 1064 .poll_get_char = s3c24xx_serial_get_poll_char,
1065 .poll_put_char = s3c24xx_serial_put_poll_char,
1066#endif
b497549a
BD		 1067};
1068
b497549a
BD		 1069static struct uart_driver s3c24xx_uart_drv = {
1070 .owner = THIS_MODULE,
2cf0c58e 1071 .driver_name = "s3c2410_serial",
bdd4915a 1072 .nr = CONFIG_SERIAL_SAMSUNG_UARTS,
b497549a 1073 .cons = S3C24XX_SERIAL_CONSOLE,
2cf0c58e 1074 .dev_name = S3C24XX_SERIAL_NAME,
b497549a
BD		 1075 .major = S3C24XX_SERIAL_MAJOR,
1076 .minor = S3C24XX_SERIAL_MINOR,
1077};
1078
ef4aca70
RB		 1079#define __PORT_LOCK_UNLOCKED(i) \
1080 __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[i].port.lock)
1081static struct s3c24xx_uart_port
1082s3c24xx_serial_ports[CONFIG_SERIAL_SAMSUNG_UARTS] = {
b497549a
BD		 1083 [0] = {
1084 .port = {
ef4aca70 1085 .lock = __PORT_LOCK_UNLOCKED(0),
b497549a 1086 .iotype = UPIO_MEM,
b497549a
BD		 1087 .uartclk = 0,
1088 .fifosize = 16,
1089 .ops = &s3c24xx_serial_ops,
1090 .flags = UPF_BOOT_AUTOCONF,
1091 .line = 0,
1092 }
1093 },
1094 [1] = {
1095 .port = {
ef4aca70 1096 .lock = __PORT_LOCK_UNLOCKED(1),
b497549a 1097 .iotype = UPIO_MEM,
b497549a
BD		 1098 .uartclk = 0,
1099 .fifosize = 16,
1100 .ops = &s3c24xx_serial_ops,
1101 .flags = UPF_BOOT_AUTOCONF,
1102 .line = 1,
1103 }
1104 },
03d5e77b 1105#if CONFIG_SERIAL_SAMSUNG_UARTS > 2
b497549a
BD		 1106
1107 [2] = {
1108 .port = {
ef4aca70 1109 .lock = __PORT_LOCK_UNLOCKED(2),
b497549a 1110 .iotype = UPIO_MEM,
b497549a
BD		 1111 .uartclk = 0,
1112 .fifosize = 16,
1113 .ops = &s3c24xx_serial_ops,
1114 .flags = UPF_BOOT_AUTOCONF,
1115 .line = 2,
1116 }
03d5e77b
BD		 1117 },
1118#endif
1119#if CONFIG_SERIAL_SAMSUNG_UARTS > 3
1120 [3] = {
1121 .port = {
ef4aca70 1122 .lock = __PORT_LOCK_UNLOCKED(3),
03d5e77b 1123 .iotype = UPIO_MEM,
03d5e77b
BD		 1124 .uartclk = 0,
1125 .fifosize = 16,
1126 .ops = &s3c24xx_serial_ops,
1127 .flags = UPF_BOOT_AUTOCONF,
1128 .line = 3,
1129 }
b497549a
BD		 1130 }
1131#endif
1132};
ef4aca70 1133#undef __PORT_LOCK_UNLOCKED
b497549a
BD		 1134
1135/* s3c24xx_serial_resetport
1136 *
0dfb3b41 1137 * reset the fifos and other the settings.
b497549a
BD		 1138*/
1139
0dfb3b41
TA		 1140static void s3c24xx_serial_resetport(struct uart_port *port,
1141 struct s3c2410_uartcfg *cfg)
b497549a
BD		 1142{
1143 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
0dfb3b41
TA		 1144 unsigned long ucon = rd_regl(port, S3C2410_UCON);
1145 unsigned int ucon_mask;
b497549a 1146
0dfb3b41
TA		 1147 ucon_mask = info->clksel_mask;
1148 if (info->type == PORT_S3C2440)
1149 ucon_mask |= S3C2440_UCON0_DIVMASK;
1150
1151 ucon &= ucon_mask;
1152 wr_regl(port, S3C2410_UCON, ucon | cfg->ucon);
1153
1154 /* reset both fifos */
1155 wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
1156 wr_regl(port, S3C2410_UFCON, cfg->ufcon);
1157
1158 /* some delay is required after fifo reset */
1159 udelay(1);
b497549a
BD		 1160}
1161
30555476
BD		 1162
1163#ifdef CONFIG_CPU_FREQ
1164
1165static int s3c24xx_serial_cpufreq_transition(struct notifier_block *nb,
1166 unsigned long val, void *data)
1167{
1168 struct s3c24xx_uart_port *port;
1169 struct uart_port *uport;
1170
1171 port = container_of(nb, struct s3c24xx_uart_port, freq_transition);
1172 uport = &port->port;
1173
1174 /* check to see if port is enabled */
1175
1176 if (port->pm_level != 0)
1177 return 0;
1178
1179 /* try and work out if the baudrate is changing, we can detect
1180 * a change in rate, but we do not have support for detecting
1181 * a disturbance in the clock-rate over the change.
1182 */
1183
25f04ad4 1184 if (IS_ERR(port->baudclk))
30555476
BD		 1185 goto exit;
1186
25f04ad4 1187 if (port->baudclk_rate == clk_get_rate(port->baudclk))
30555476
BD		 1188 goto exit;
1189
1190 if (val == CPUFREQ_PRECHANGE) {
1191 /* we should really shut the port down whilst the
1192 * frequency change is in progress. */
1193
1194 } else if (val == CPUFREQ_POSTCHANGE) {
1195 struct ktermios *termios;
1196 struct tty_struct *tty;
1197
ebd2c8f6 1198 if (uport->state == NULL)
30555476 1199 goto exit;
30555476 1200
ebd2c8f6 1201 tty = uport->state->port.tty;
30555476 1202
7de40c21 1203 if (tty == NULL)
30555476 1204 goto exit;
30555476 1205
adc8d746 1206 termios = &tty->termios;
30555476
BD		 1207
1208 if (termios == NULL) {
d20925e1 1209 dev_warn(uport->dev, "%s: no termios?\n", __func__);
30555476
BD		 1210 goto exit;
1211 }
1212
1213 s3c24xx_serial_set_termios(uport, termios, NULL);
1214 }
1215
ef4aca70 1216exit:
30555476
BD		 1217 return 0;
1218}
1219
ef4aca70
RB		 1220static inline int
1221s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port)
30555476
BD		 1222{
1223 port->freq_transition.notifier_call = s3c24xx_serial_cpufreq_transition;
1224
1225 return cpufreq_register_notifier(&port->freq_transition,
1226 CPUFREQ_TRANSITION_NOTIFIER);
1227}
1228
ef4aca70
RB		 1229static inline void
1230s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port)
30555476
BD		 1231{
1232 cpufreq_unregister_notifier(&port->freq_transition,
1233 CPUFREQ_TRANSITION_NOTIFIER);
1234}
1235
1236#else
ef4aca70
RB		 1237static inline int
1238s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port)
30555476
BD		 1239{
1240 return 0;
1241}
1242
ef4aca70
RB		 1243static inline void
1244s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port)
30555476
BD		 1245{
1246}
1247#endif
1248
b497549a
BD		 1249/* s3c24xx_serial_init_port
1250 *
1251 * initialise a single serial port from the platform device given
1252 */
1253
1254static int s3c24xx_serial_init_port(struct s3c24xx_uart_port *ourport,
b497549a
BD		 1255 struct platform_device *platdev)
1256{
1257 struct uart_port *port = &ourport->port;
da121506 1258 struct s3c2410_uartcfg *cfg = ourport->cfg;
b497549a
BD		 1259 struct resource *res;
1260 int ret;
1261
1262 dbg("s3c24xx_serial_init_port: port=%p, platdev=%p\n", port, platdev);
1263
1264 if (platdev == NULL)
1265 return -ENODEV;
1266
b497549a
BD		 1267 if (port->mapbase != 0)
1268 return 0;
1269
b497549a
BD		 1270 /* setup info for port */
1271 port->dev = &platdev->dev;
b497549a 1272
88bb4ea1
TA		 1273 /* Startup sequence is different for s3c64xx and higher SoC's */
1274 if (s3c24xx_serial_has_interrupt_mask(port))
1275 s3c24xx_serial_ops.startup = s3c64xx_serial_startup;
1276
b497549a
BD		 1277 port->uartclk = 1;
1278
1279 if (cfg->uart_flags & UPF_CONS_FLOW) {
1280 dbg("s3c24xx_serial_init_port: enabling flow control\n");
1281 port->flags |= UPF_CONS_FLOW;
1282 }
1283
1284 /* sort our the physical and virtual addresses for each UART */
1285
1286 res = platform_get_resource(platdev, IORESOURCE_MEM, 0);
1287 if (res == NULL) {
d20925e1 1288 dev_err(port->dev, "failed to find memory resource for uart\n");
b497549a
BD		 1289 return -EINVAL;
1290 }
1291
e4ac92df 1292 dbg("resource %pR)\n", res);
b497549a 1293
41147bfd
TA		 1294 port->membase = devm_ioremap(port->dev, res->start, resource_size(res));
1295 if (!port->membase) {
1296 dev_err(port->dev, "failed to remap controller address\n");
1297 return -EBUSY;
1298 }
1299
b690ace5 1300 port->mapbase = res->start;
b497549a
BD		 1301 ret = platform_get_irq(platdev, 0);
1302 if (ret < 0)
1303 port->irq = 0;
b73c289c 1304 else {
b497549a 1305 port->irq = ret;
b73c289c
BD		 1306 ourport->rx_irq = ret;
1307 ourport->tx_irq = ret + 1;
1308 }
9303ac15 1309
b73c289c
BD		 1310 ret = platform_get_irq(platdev, 1);
1311 if (ret > 0)
1312 ourport->tx_irq = ret;
658c9d2b
RB		 1313 /*
1314 * DMA is currently supported only on DT platforms, if DMA properties
1315 * are specified.
1316 */
1317 if (platdev->dev.of_node && of_find_property(platdev->dev.of_node,
1318 "dmas", NULL)) {
1319 ourport->dma = devm_kzalloc(port->dev,
1320 sizeof(*ourport->dma),
1321 GFP_KERNEL);
1322 if (!ourport->dma)
1323 return -ENOMEM;
1324 }
b497549a
BD		 1325
1326 ourport->clk = clk_get(&platdev->dev, "uart");
60e93575
CK		 1327 if (IS_ERR(ourport->clk)) {
1328 pr_err("%s: Controller clock not found\n",
1329 dev_name(&platdev->dev));
1330 return PTR_ERR(ourport->clk);
1331 }
1332
1333 ret = clk_prepare_enable(ourport->clk);
1334 if (ret) {
1335 pr_err("uart: clock failed to prepare+enable: %d\n", ret);
1336 clk_put(ourport->clk);
1337 return ret;
1338 }
b497549a 1339
88bb4ea1
TA		 1340 /* Keep all interrupts masked and cleared */
1341 if (s3c24xx_serial_has_interrupt_mask(port)) {
1342 wr_regl(port, S3C64XX_UINTM, 0xf);
1343 wr_regl(port, S3C64XX_UINTP, 0xf);
1344 wr_regl(port, S3C64XX_UINTSP, 0xf);
1345 }
1346
1ff5b64d
FE		 1347 dbg("port: map=%pa, mem=%p, irq=%d (%d,%d), clock=%u\n",
1348 &port->mapbase, port->membase, port->irq,
b73c289c 1349 ourport->rx_irq, ourport->tx_irq, port->uartclk);
b497549a
BD		 1350
1351 /* reset the fifos (and setup the uart) */
1352 s3c24xx_serial_resetport(port, cfg);
1353 return 0;
1354}
1355
b497549a
BD		 1356/* Device driver serial port probe */
1357
26c919e1 1358static const struct of_device_id s3c24xx_uart_dt_match[];
b497549a
BD		 1359static int probe_index;
1360
26c919e1
TA		 1361static inline struct s3c24xx_serial_drv_data *s3c24xx_get_driver_data(
1362 struct platform_device *pdev)
1363{
1364#ifdef CONFIG_OF
1365 if (pdev->dev.of_node) {
1366 const struct of_device_id *match;
1367 match = of_match_node(s3c24xx_uart_dt_match, pdev->dev.of_node);
1368 return (struct s3c24xx_serial_drv_data *)match->data;
1369 }
1370#endif
1371 return (struct s3c24xx_serial_drv_data *)
1372 platform_get_device_id(pdev)->driver_data;
1373}
1374
da121506 1375static int s3c24xx_serial_probe(struct platform_device *pdev)
b497549a 1376{
4622eb68 1377 struct device_node *np = pdev->dev.of_node;
b497549a 1378 struct s3c24xx_uart_port *ourport;
13a9f6c6 1379 int index = probe_index;
b497549a
BD		 1380 int ret;
1381
4622eb68
NKC		 1382 if (np) {
1383 ret = of_alias_get_id(np, "serial");
13a9f6c6
TF		 1384 if (ret >= 0)
1385 index = ret;
1386 }
1387
1388 dbg("s3c24xx_serial_probe(%p) %d\n", pdev, index);
b497549a 1389
13a9f6c6 1390 ourport = &s3c24xx_serial_ports[index];
da121506 1391
26c919e1
TA		 1392 ourport->drv_data = s3c24xx_get_driver_data(pdev);
1393 if (!ourport->drv_data) {
1394 dev_err(&pdev->dev, "could not find driver data\n");
1395 return -ENODEV;
1396 }
da121506 1397
7cd88831 1398 ourport->baudclk = ERR_PTR(-EINVAL);
da121506 1399 ourport->info = ourport->drv_data->info;
574de559 1400 ourport->cfg = (dev_get_platdata(&pdev->dev)) ?
d4aab206 1401 dev_get_platdata(&pdev->dev) :
da121506
TA		 1402 ourport->drv_data->def_cfg;
1403
4622eb68
NKC		 1404 if (np)
1405 of_property_read_u32(np,
135f07c3
NKC		 1406 "samsung,uart-fifosize", &ourport->port.fifosize);
1407
2f1ba72d
RB		 1408 if (ourport->drv_data->fifosize[index])
1409 ourport->port.fifosize = ourport->drv_data->fifosize[index];
1410 else if (ourport->info->fifosize)
1411 ourport->port.fifosize = ourport->info->fifosize;
da121506 1412
b497549a
BD		 1413 probe_index++;
1414
1415 dbg("%s: initialising port %p...\n", __func__, ourport);
1416
da121506 1417 ret = s3c24xx_serial_init_port(ourport, pdev);
b497549a 1418 if (ret < 0)
8ad711a9 1419 return ret;
b497549a 1420
6f134c3c
TB		 1421 if (!s3c24xx_uart_drv.state) {
1422 ret = uart_register_driver(&s3c24xx_uart_drv);
1423 if (ret < 0) {
1424 pr_err("Failed to register Samsung UART driver\n");
1425 return ret;
1426 }
1427 }
1428
b497549a
BD		 1429 dbg("%s: adding port\n", __func__);
1430 uart_add_one_port(&s3c24xx_uart_drv, &ourport->port);
da121506 1431 platform_set_drvdata(pdev, &ourport->port);
b497549a 1432
0da3336f
HS		 1433 /*
1434 * Deactivate the clock enabled in s3c24xx_serial_init_port here,
1435 * so that a potential re-enablement through the pm-callback overlaps
1436 * and keeps the clock enabled in this case.
1437 */
1438 clk_disable_unprepare(ourport->clk);
1439
30555476
BD		 1440 ret = s3c24xx_serial_cpufreq_register(ourport);
1441 if (ret < 0)
da121506 1442 dev_err(&pdev->dev, "failed to add cpufreq notifier\n");
30555476 1443
b497549a 1444 return 0;
b497549a
BD		 1445}
1446
ae8d8a14 1447static int s3c24xx_serial_remove(struct platform_device *dev)
b497549a
BD		 1448{
1449 struct uart_port *port = s3c24xx_dev_to_port(&dev->dev);
1450
1451 if (port) {
30555476 1452 s3c24xx_serial_cpufreq_deregister(to_ourport(port));
b497549a
BD		 1453 uart_remove_one_port(&s3c24xx_uart_drv, port);
1454 }
1455
6f134c3c
TB		 1456 uart_unregister_driver(&s3c24xx_uart_drv);
1457
b497549a
BD		 1458 return 0;
1459}
1460
b497549a 1461/* UART power management code */
aef7fe52
MH		 1462#ifdef CONFIG_PM_SLEEP
1463static int s3c24xx_serial_suspend(struct device *dev)
b497549a 1464{
aef7fe52 1465 struct uart_port *port = s3c24xx_dev_to_port(dev);
b497549a
BD		 1466
1467 if (port)
1468 uart_suspend_port(&s3c24xx_uart_drv, port);
1469
1470 return 0;
1471}
1472
aef7fe52 1473static int s3c24xx_serial_resume(struct device *dev)
b497549a 1474{
aef7fe52 1475 struct uart_port *port = s3c24xx_dev_to_port(dev);
b497549a
BD		 1476 struct s3c24xx_uart_port *ourport = to_ourport(port);
1477
1478 if (port) {
9484b009 1479 clk_prepare_enable(ourport->clk);
b497549a 1480 s3c24xx_serial_resetport(port, s3c24xx_port_to_cfg(port));
9484b009 1481 clk_disable_unprepare(ourport->clk);
b497549a
BD		 1482
1483 uart_resume_port(&s3c24xx_uart_drv, port);
1484 }
1485
1486 return 0;
1487}
aef7fe52 1488
d09a7308
MS		 1489static int s3c24xx_serial_resume_noirq(struct device *dev)
1490{
1491 struct uart_port *port = s3c24xx_dev_to_port(dev);
1492
1493 if (port) {
1494 /* restore IRQ mask */
1495 if (s3c24xx_serial_has_interrupt_mask(port)) {
1496 unsigned int uintm = 0xf;
1497 if (tx_enabled(port))
1498 uintm &= ~S3C64XX_UINTM_TXD_MSK;
1499 if (rx_enabled(port))
1500 uintm &= ~S3C64XX_UINTM_RXD_MSK;
1501 wr_regl(port, S3C64XX_UINTM, uintm);
1502 }
1503 }
1504
1505 return 0;
1506}
1507
aef7fe52
MH		 1508static const struct dev_pm_ops s3c24xx_serial_pm_ops = {
1509 .suspend = s3c24xx_serial_suspend,
1510 .resume = s3c24xx_serial_resume,
d09a7308 1511 .resume_noirq = s3c24xx_serial_resume_noirq,
aef7fe52 1512};
b882fc1b
KK		 1513#define SERIAL_SAMSUNG_PM_OPS (&s3c24xx_serial_pm_ops)
1514
aef7fe52 1515#else /* !CONFIG_PM_SLEEP */
b882fc1b
KK		 1516
1517#define SERIAL_SAMSUNG_PM_OPS NULL
aef7fe52 1518#endif /* CONFIG_PM_SLEEP */
b497549a 1519
b497549a
BD		 1520/* Console code */
1521
1522#ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
1523
1524static struct uart_port *cons_uart;
1525
1526static int
1527s3c24xx_serial_console_txrdy(struct uart_port *port, unsigned int ufcon)
1528{
1529 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1530 unsigned long ufstat, utrstat;
1531
1532 if (ufcon & S3C2410_UFCON_FIFOMODE) {
9ddc5b6f 1533 /* fifo mode - check amount of data in fifo registers... */
b497549a
BD		 1534
1535 ufstat = rd_regl(port, S3C2410_UFSTAT);
1536 return (ufstat & info->tx_fifofull) ? 0 : 1;
1537 }
1538
1539 /* in non-fifo mode, we go and use the tx buffer empty */
1540
1541 utrstat = rd_regl(port, S3C2410_UTRSTAT);
1542 return (utrstat & S3C2410_UTRSTAT_TXE) ? 1 : 0;
1543}
1544
38adbc54
MS		 1545static bool
1546s3c24xx_port_configured(unsigned int ucon)
1547{
1548 /* consider the serial port configured if the tx/rx mode set */
1549 return (ucon & 0xf) != 0;
1550}
1551
93b5c032
JP		 1552#ifdef CONFIG_CONSOLE_POLL
1553/*
1554 * Console polling routines for writing and reading from the uart while
1555 * in an interrupt or debug context.
1556 */
1557
1558static int s3c24xx_serial_get_poll_char(struct uart_port *port)
1559{
1560 struct s3c24xx_uart_port *ourport = to_ourport(port);
1561 unsigned int ufstat;
1562
1563 ufstat = rd_regl(port, S3C2410_UFSTAT);
1564 if (s3c24xx_serial_rx_fifocnt(ourport, ufstat) == 0)
1565 return NO_POLL_CHAR;
1566
1567 return rd_regb(port, S3C2410_URXH);
1568}
1569
1570static void s3c24xx_serial_put_poll_char(struct uart_port *port,
1571 unsigned char c)
1572{
bb7f09ba
DA		 1573 unsigned int ufcon = rd_regl(port, S3C2410_UFCON);
1574 unsigned int ucon = rd_regl(port, S3C2410_UCON);
38adbc54
MS		 1575
1576 /* not possible to xmit on unconfigured port */
1577 if (!s3c24xx_port_configured(ucon))
1578 return;
93b5c032
JP		 1579
1580 while (!s3c24xx_serial_console_txrdy(port, ufcon))
1581 cpu_relax();
bb7f09ba 1582 wr_regb(port, S3C2410_UTXH, c);
93b5c032
JP		 1583}
1584
1585#endif /* CONFIG_CONSOLE_POLL */
1586
b497549a
BD		 1587static void
1588s3c24xx_serial_console_putchar(struct uart_port *port, int ch)
1589{
bb7f09ba 1590 unsigned int ufcon = rd_regl(port, S3C2410_UFCON);
38adbc54 1591
b497549a 1592 while (!s3c24xx_serial_console_txrdy(port, ufcon))
f94b0572 1593 cpu_relax();
bb7f09ba 1594 wr_regb(port, S3C2410_UTXH, ch);
b497549a
BD		 1595}
1596
1597static void
1598s3c24xx_serial_console_write(struct console *co, const char *s,
1599 unsigned int count)
1600{
ab88c8dc
DA		 1601 unsigned int ucon = rd_regl(cons_uart, S3C2410_UCON);
1602
1603 /* not possible to xmit on unconfigured port */
1604 if (!s3c24xx_port_configured(ucon))
1605 return;
1606
b497549a
BD		 1607 uart_console_write(cons_uart, s, count, s3c24xx_serial_console_putchar);
1608}
1609
1610static void __init
1611s3c24xx_serial_get_options(struct uart_port *port, int *baud,
1612 int *parity, int *bits)
1613{
b497549a
BD		 1614 struct clk *clk;
1615 unsigned int ulcon;
1616 unsigned int ucon;
1617 unsigned int ubrdiv;
1618 unsigned long rate;
5f5a7a55
TA		 1619 unsigned int clk_sel;
1620 char clk_name[MAX_CLK_NAME_LENGTH];
b497549a
BD		 1621
1622 ulcon = rd_regl(port, S3C2410_ULCON);
1623 ucon = rd_regl(port, S3C2410_UCON);
1624 ubrdiv = rd_regl(port, S3C2410_UBRDIV);
1625
1626 dbg("s3c24xx_serial_get_options: port=%p\n"
1627 "registers: ulcon=%08x, ucon=%08x, ubdriv=%08x\n",
1628 port, ulcon, ucon, ubrdiv);
1629
38adbc54 1630 if (s3c24xx_port_configured(ucon)) {
b497549a
BD		 1631 switch (ulcon & S3C2410_LCON_CSMASK) {
1632 case S3C2410_LCON_CS5:
1633 *bits = 5;
1634 break;
1635 case S3C2410_LCON_CS6:
1636 *bits = 6;
1637 break;
1638 case S3C2410_LCON_CS7:
1639 *bits = 7;
1640 break;
b497549a 1641 case S3C2410_LCON_CS8:
3bcce591 1642 default:
b497549a
BD		 1643 *bits = 8;
1644 break;
1645 }
1646
1647 switch (ulcon & S3C2410_LCON_PMASK) {
1648 case S3C2410_LCON_PEVEN:
1649 *parity = 'e';
1650 break;
1651
1652 case S3C2410_LCON_PODD:
1653 *parity = 'o';
1654 break;
1655
1656 case S3C2410_LCON_PNONE:
1657 default:
1658 *parity = 'n';
1659 }
1660
1661 /* now calculate the baud rate */
1662
5f5a7a55
TA		 1663 clk_sel = s3c24xx_serial_getsource(port);
1664 sprintf(clk_name, "clk_uart_baud%d", clk_sel);
b497549a 1665
5f5a7a55 1666 clk = clk_get(port->dev, clk_name);
7cd88831 1667 if (!IS_ERR(clk))
5f5a7a55 1668 rate = clk_get_rate(clk);
b497549a
BD		 1669 else
1670 rate = 1;
1671
b497549a
BD		 1672 *baud = rate / (16 * (ubrdiv + 1));
1673 dbg("calculated baud %d\n", *baud);
1674 }
1675
1676}
1677
b497549a
BD		 1678static int __init
1679s3c24xx_serial_console_setup(struct console *co, char *options)
1680{
1681 struct uart_port *port;
1682 int baud = 9600;
1683 int bits = 8;
1684 int parity = 'n';
1685 int flow = 'n';
1686
1687 dbg("s3c24xx_serial_console_setup: co=%p (%d), %s\n",
1688 co, co->index, options);
1689
1690 /* is this a valid port */
1691
03d5e77b 1692 if (co->index == -1 || co->index >= CONFIG_SERIAL_SAMSUNG_UARTS)
b497549a
BD		 1693 co->index = 0;
1694
1695 port = &s3c24xx_serial_ports[co->index].port;
1696
1697 /* is the port configured? */
1698
ee430f16
TA		 1699 if (port->mapbase == 0x0)
1700 return -ENODEV;
b497549a
BD		 1701
1702 cons_uart = port;
1703
1704 dbg("s3c24xx_serial_console_setup: port=%p (%d)\n", port, co->index);
1705
1706 /*
1707 * Check whether an invalid uart number has been specified, and
1708 * if so, search for the first available port that does have
1709 * console support.
1710 */
1711 if (options)
1712 uart_parse_options(options, &baud, &parity, &bits, &flow);
1713 else
1714 s3c24xx_serial_get_options(port, &baud, &parity, &bits);
1715
1716 dbg("s3c24xx_serial_console_setup: baud %d\n", baud);
1717
1718 return uart_set_options(port, co, baud, parity, bits, flow);
1719}
1720
b497549a
BD		 1721static struct console s3c24xx_serial_console = {
1722 .name = S3C24XX_SERIAL_NAME,
1723 .device = uart_console_device,
1724 .flags = CON_PRINTBUFFER,
1725 .index = -1,
1726 .write = s3c24xx_serial_console_write,
5822a5df
TA		 1727 .setup = s3c24xx_serial_console_setup,
1728 .data = &s3c24xx_uart_drv,
b497549a 1729};
da121506
TA		 1730#endif /* CONFIG_SERIAL_SAMSUNG_CONSOLE */
1731
1732#ifdef CONFIG_CPU_S3C2410
1733static struct s3c24xx_serial_drv_data s3c2410_serial_drv_data = {
1734 .info = &(struct s3c24xx_uart_info) {
1735 .name = "Samsung S3C2410 UART",
1736 .type = PORT_S3C2410,
1737 .fifosize = 16,
1738 .rx_fifomask = S3C2410_UFSTAT_RXMASK,
1739 .rx_fifoshift = S3C2410_UFSTAT_RXSHIFT,
1740 .rx_fifofull = S3C2410_UFSTAT_RXFULL,
1741 .tx_fifofull = S3C2410_UFSTAT_TXFULL,
1742 .tx_fifomask = S3C2410_UFSTAT_TXMASK,
1743 .tx_fifoshift = S3C2410_UFSTAT_TXSHIFT,
1744 .def_clk_sel = S3C2410_UCON_CLKSEL0,
1745 .num_clks = 2,
1746 .clksel_mask = S3C2410_UCON_CLKMASK,
1747 .clksel_shift = S3C2410_UCON_CLKSHIFT,
1748 },
1749 .def_cfg = &(struct s3c2410_uartcfg) {
1750 .ucon = S3C2410_UCON_DEFAULT,
1751 .ufcon = S3C2410_UFCON_DEFAULT,
1752 },
1753};
1754#define S3C2410_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2410_serial_drv_data)
1755#else
1756#define S3C2410_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1757#endif
b497549a 1758
da121506
TA		 1759#ifdef CONFIG_CPU_S3C2412
1760static struct s3c24xx_serial_drv_data s3c2412_serial_drv_data = {
1761 .info = &(struct s3c24xx_uart_info) {
1762 .name = "Samsung S3C2412 UART",
1763 .type = PORT_S3C2412,
1764 .fifosize = 64,
1765 .has_divslot = 1,
1766 .rx_fifomask = S3C2440_UFSTAT_RXMASK,
1767 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
1768 .rx_fifofull = S3C2440_UFSTAT_RXFULL,
1769 .tx_fifofull = S3C2440_UFSTAT_TXFULL,
1770 .tx_fifomask = S3C2440_UFSTAT_TXMASK,
1771 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
1772 .def_clk_sel = S3C2410_UCON_CLKSEL2,
1773 .num_clks = 4,
1774 .clksel_mask = S3C2412_UCON_CLKMASK,
1775 .clksel_shift = S3C2412_UCON_CLKSHIFT,
1776 },
1777 .def_cfg = &(struct s3c2410_uartcfg) {
1778 .ucon = S3C2410_UCON_DEFAULT,
1779 .ufcon = S3C2410_UFCON_DEFAULT,
1780 },
1781};
1782#define S3C2412_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2412_serial_drv_data)
1783#else
1784#define S3C2412_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1785#endif
b497549a 1786
da121506 1787#if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2416) || \
b26469a8 1788 defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2442)
da121506
TA		 1789static struct s3c24xx_serial_drv_data s3c2440_serial_drv_data = {
1790 .info = &(struct s3c24xx_uart_info) {
1791 .name = "Samsung S3C2440 UART",
1792 .type = PORT_S3C2440,
1793 .fifosize = 64,
1794 .has_divslot = 1,
1795 .rx_fifomask = S3C2440_UFSTAT_RXMASK,
1796 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
1797 .rx_fifofull = S3C2440_UFSTAT_RXFULL,
1798 .tx_fifofull = S3C2440_UFSTAT_TXFULL,
1799 .tx_fifomask = S3C2440_UFSTAT_TXMASK,
1800 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
1801 .def_clk_sel = S3C2410_UCON_CLKSEL2,
1802 .num_clks = 4,
1803 .clksel_mask = S3C2412_UCON_CLKMASK,
1804 .clksel_shift = S3C2412_UCON_CLKSHIFT,
1805 },
1806 .def_cfg = &(struct s3c2410_uartcfg) {
1807 .ucon = S3C2410_UCON_DEFAULT,
1808 .ufcon = S3C2410_UFCON_DEFAULT,
1809 },
1810};
1811#define S3C2440_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2440_serial_drv_data)
1812#else
1813#define S3C2440_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1814#endif
b497549a 1815
953b53a7 1816#if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
da121506
TA		 1817static struct s3c24xx_serial_drv_data s3c6400_serial_drv_data = {
1818 .info = &(struct s3c24xx_uart_info) {
1819 .name = "Samsung S3C6400 UART",
1820 .type = PORT_S3C6400,
1821 .fifosize = 64,
1822 .has_divslot = 1,
1823 .rx_fifomask = S3C2440_UFSTAT_RXMASK,
1824 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
1825 .rx_fifofull = S3C2440_UFSTAT_RXFULL,
1826 .tx_fifofull = S3C2440_UFSTAT_TXFULL,
1827 .tx_fifomask = S3C2440_UFSTAT_TXMASK,
1828 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
1829 .def_clk_sel = S3C2410_UCON_CLKSEL2,
1830 .num_clks = 4,
1831 .clksel_mask = S3C6400_UCON_CLKMASK,
1832 .clksel_shift = S3C6400_UCON_CLKSHIFT,
1833 },
1834 .def_cfg = &(struct s3c2410_uartcfg) {
1835 .ucon = S3C2410_UCON_DEFAULT,
1836 .ufcon = S3C2410_UFCON_DEFAULT,
1837 },
1838};
1839#define S3C6400_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c6400_serial_drv_data)
1840#else
1841#define S3C6400_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1842#endif
b497549a 1843
da121506
TA		 1844#ifdef CONFIG_CPU_S5PV210
1845static struct s3c24xx_serial_drv_data s5pv210_serial_drv_data = {
1846 .info = &(struct s3c24xx_uart_info) {
1847 .name = "Samsung S5PV210 UART",
1848 .type = PORT_S3C6400,
1849 .has_divslot = 1,
1850 .rx_fifomask = S5PV210_UFSTAT_RXMASK,
1851 .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT,
1852 .rx_fifofull = S5PV210_UFSTAT_RXFULL,
1853 .tx_fifofull = S5PV210_UFSTAT_TXFULL,
1854 .tx_fifomask = S5PV210_UFSTAT_TXMASK,
1855 .tx_fifoshift = S5PV210_UFSTAT_TXSHIFT,
1856 .def_clk_sel = S3C2410_UCON_CLKSEL0,
1857 .num_clks = 2,
1858 .clksel_mask = S5PV210_UCON_CLKMASK,
1859 .clksel_shift = S5PV210_UCON_CLKSHIFT,
1860 },
1861 .def_cfg = &(struct s3c2410_uartcfg) {
1862 .ucon = S5PV210_UCON_DEFAULT,
1863 .ufcon = S5PV210_UFCON_DEFAULT,
1864 },
1865 .fifosize = { 256, 64, 16, 16 },
1866};
1867#define S5PV210_SERIAL_DRV_DATA ((kernel_ulong_t)&s5pv210_serial_drv_data)
1868#else
1869#define S5PV210_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1870#endif
b497549a 1871
33f88136 1872#if defined(CONFIG_ARCH_EXYNOS)
da121506
TA		 1873static struct s3c24xx_serial_drv_data exynos4210_serial_drv_data = {
1874 .info = &(struct s3c24xx_uart_info) {
1875 .name = "Samsung Exynos4 UART",
1876 .type = PORT_S3C6400,
1877 .has_divslot = 1,
1878 .rx_fifomask = S5PV210_UFSTAT_RXMASK,
1879 .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT,
1880 .rx_fifofull = S5PV210_UFSTAT_RXFULL,
1881 .tx_fifofull = S5PV210_UFSTAT_TXFULL,
1882 .tx_fifomask = S5PV210_UFSTAT_TXMASK,
1883 .tx_fifoshift = S5PV210_UFSTAT_TXSHIFT,
1884 .def_clk_sel = S3C2410_UCON_CLKSEL0,
1885 .num_clks = 1,
1886 .clksel_mask = 0,
1887 .clksel_shift = 0,
1888 },
1889 .def_cfg = &(struct s3c2410_uartcfg) {
1890 .ucon = S5PV210_UCON_DEFAULT,
1891 .ufcon = S5PV210_UFCON_DEFAULT,
1892 .has_fracval = 1,
1893 },
1894 .fifosize = { 256, 64, 16, 16 },
1895};
1896#define EXYNOS4210_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos4210_serial_drv_data)
1897#else
1898#define EXYNOS4210_SERIAL_DRV_DATA (kernel_ulong_t)NULL
1899#endif
b497549a 1900
da121506
TA		 1901static struct platform_device_id s3c24xx_serial_driver_ids[] = {
1902 {
1903 .name = "s3c2410-uart",
1904 .driver_data = S3C2410_SERIAL_DRV_DATA,
1905 }, {
1906 .name = "s3c2412-uart",
1907 .driver_data = S3C2412_SERIAL_DRV_DATA,
1908 }, {
1909 .name = "s3c2440-uart",
1910 .driver_data = S3C2440_SERIAL_DRV_DATA,
1911 }, {
1912 .name = "s3c6400-uart",
1913 .driver_data = S3C6400_SERIAL_DRV_DATA,
1914 }, {
1915 .name = "s5pv210-uart",
1916 .driver_data = S5PV210_SERIAL_DRV_DATA,
1917 }, {
1918 .name = "exynos4210-uart",
1919 .driver_data = EXYNOS4210_SERIAL_DRV_DATA,
1920 },
1921 { },
1922};
1923MODULE_DEVICE_TABLE(platform, s3c24xx_serial_driver_ids);
1924
26c919e1
TA		 1925#ifdef CONFIG_OF
1926static const struct of_device_id s3c24xx_uart_dt_match[] = {
666ca0b9
HS		 1927 { .compatible = "samsung,s3c2410-uart",
1928 .data = (void *)S3C2410_SERIAL_DRV_DATA },
1929 { .compatible = "samsung,s3c2412-uart",
1930 .data = (void *)S3C2412_SERIAL_DRV_DATA },
1931 { .compatible = "samsung,s3c2440-uart",
1932 .data = (void *)S3C2440_SERIAL_DRV_DATA },
1933 { .compatible = "samsung,s3c6400-uart",
1934 .data = (void *)S3C6400_SERIAL_DRV_DATA },
1935 { .compatible = "samsung,s5pv210-uart",
1936 .data = (void *)S5PV210_SERIAL_DRV_DATA },
26c919e1 1937 { .compatible = "samsung,exynos4210-uart",
a169a888 1938 .data = (void *)EXYNOS4210_SERIAL_DRV_DATA },
26c919e1
TA		 1939 {},
1940};
1941MODULE_DEVICE_TABLE(of, s3c24xx_uart_dt_match);
26c919e1
TA		 1942#endif
1943
da121506
TA		 1944static struct platform_driver samsung_serial_driver = {
1945 .probe = s3c24xx_serial_probe,
2d47b716 1946 .remove = s3c24xx_serial_remove,
da121506
TA		 1947 .id_table = s3c24xx_serial_driver_ids,
1948 .driver = {
1949 .name = "samsung-uart",
da121506 1950 .pm = SERIAL_SAMSUNG_PM_OPS,
905f4ba2 1951 .of_match_table = of_match_ptr(s3c24xx_uart_dt_match),
da121506
TA		 1952 },
1953};
b497549a 1954
6f134c3c 1955module_platform_driver(samsung_serial_driver);
b497549a 1956
da121506 1957MODULE_ALIAS("platform:samsung-uart");
b497549a
BD		 1958MODULE_DESCRIPTION("Samsung SoC Serial port driver");
1959MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
1960MODULE_LICENSE("GPL v2");
Linux 6.x block layer and io_uring tree(s)