Commit | Line | Data |
---|---|---|
99edb3d1 | 1 | /* |
b497549a BD |
2 | * Driver core for Samsung SoC onboard UARTs. |
3 | * | |
ccae941e | 4 | * Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics |
b497549a BD |
5 | * http://armlinux.simtec.co.uk/ |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | ||
12 | /* Hote on 2410 error handling | |
13 | * | |
14 | * The s3c2410 manual has a love/hate affair with the contents of the | |
15 | * UERSTAT register in the UART blocks, and keeps marking some of the | |
16 | * error bits as reserved. Having checked with the s3c2410x01, | |
17 | * it copes with BREAKs properly, so I am happy to ignore the RESERVED | |
18 | * feature from the latter versions of the manual. | |
19 | * | |
20 | * If it becomes aparrent that latter versions of the 2410 remove these | |
21 | * bits, then action will have to be taken to differentiate the versions | |
22 | * and change the policy on BREAK | |
23 | * | |
24 | * BJD, 04-Nov-2004 | |
25 | */ | |
26 | ||
27 | #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) | |
28 | #define SUPPORT_SYSRQ | |
29 | #endif | |
30 | ||
31 | #include <linux/module.h> | |
32 | #include <linux/ioport.h> | |
33 | #include <linux/io.h> | |
34 | #include <linux/platform_device.h> | |
35 | #include <linux/init.h> | |
36 | #include <linux/sysrq.h> | |
37 | #include <linux/console.h> | |
38 | #include <linux/tty.h> | |
39 | #include <linux/tty_flip.h> | |
40 | #include <linux/serial_core.h> | |
41 | #include <linux/serial.h> | |
9ee51f01 | 42 | #include <linux/serial_s3c.h> |
b497549a BD |
43 | #include <linux/delay.h> |
44 | #include <linux/clk.h> | |
30555476 | 45 | #include <linux/cpufreq.h> |
26c919e1 | 46 | #include <linux/of.h> |
b497549a BD |
47 | |
48 | #include <asm/irq.h> | |
49 | ||
9ee51f01 | 50 | #ifdef CONFIG_SAMSUNG_CLOCK |
5f5a7a55 | 51 | #include <plat/clock.h> |
9ee51f01 | 52 | #endif |
b497549a BD |
53 | |
54 | #include "samsung.h" | |
55 | ||
56 | /* UART name and device definitions */ | |
57 | ||
58 | #define S3C24XX_SERIAL_NAME "ttySAC" | |
59 | #define S3C24XX_SERIAL_MAJOR 204 | |
60 | #define S3C24XX_SERIAL_MINOR 64 | |
61 | ||
b497549a BD |
62 | /* macros to change one thing to another */ |
63 | ||
64 | #define tx_enabled(port) ((port)->unused[0]) | |
65 | #define rx_enabled(port) ((port)->unused[1]) | |
66 | ||
25985edc | 67 | /* flag to ignore all characters coming in */ |
b497549a BD |
68 | #define RXSTAT_DUMMY_READ (0x10000000) |
69 | ||
70 | static inline struct s3c24xx_uart_port *to_ourport(struct uart_port *port) | |
71 | { | |
72 | return container_of(port, struct s3c24xx_uart_port, port); | |
73 | } | |
74 | ||
75 | /* translate a port to the device name */ | |
76 | ||
77 | static inline const char *s3c24xx_serial_portname(struct uart_port *port) | |
78 | { | |
79 | return to_platform_device(port->dev)->name; | |
80 | } | |
81 | ||
82 | static int s3c24xx_serial_txempty_nofifo(struct uart_port *port) | |
83 | { | |
9303ac15 | 84 | return rd_regl(port, S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE; |
b497549a BD |
85 | } |
86 | ||
88bb4ea1 TA |
87 | /* |
88 | * s3c64xx and later SoC's include the interrupt mask and status registers in | |
89 | * the controller itself, unlike the s3c24xx SoC's which have these registers | |
90 | * in the interrupt controller. Check if the port type is s3c64xx or higher. | |
91 | */ | |
92 | static int s3c24xx_serial_has_interrupt_mask(struct uart_port *port) | |
93 | { | |
94 | return to_ourport(port)->info->type == PORT_S3C6400; | |
95 | } | |
96 | ||
b497549a BD |
97 | static void s3c24xx_serial_rx_enable(struct uart_port *port) |
98 | { | |
99 | unsigned long flags; | |
100 | unsigned int ucon, ufcon; | |
101 | int count = 10000; | |
102 | ||
103 | spin_lock_irqsave(&port->lock, flags); | |
104 | ||
105 | while (--count && !s3c24xx_serial_txempty_nofifo(port)) | |
106 | udelay(100); | |
107 | ||
108 | ufcon = rd_regl(port, S3C2410_UFCON); | |
109 | ufcon |= S3C2410_UFCON_RESETRX; | |
110 | wr_regl(port, S3C2410_UFCON, ufcon); | |
111 | ||
112 | ucon = rd_regl(port, S3C2410_UCON); | |
113 | ucon |= S3C2410_UCON_RXIRQMODE; | |
114 | wr_regl(port, S3C2410_UCON, ucon); | |
115 | ||
116 | rx_enabled(port) = 1; | |
117 | spin_unlock_irqrestore(&port->lock, flags); | |
118 | } | |
119 | ||
120 | static void s3c24xx_serial_rx_disable(struct uart_port *port) | |
121 | { | |
122 | unsigned long flags; | |
123 | unsigned int ucon; | |
124 | ||
125 | spin_lock_irqsave(&port->lock, flags); | |
126 | ||
127 | ucon = rd_regl(port, S3C2410_UCON); | |
128 | ucon &= ~S3C2410_UCON_RXIRQMODE; | |
129 | wr_regl(port, S3C2410_UCON, ucon); | |
130 | ||
131 | rx_enabled(port) = 0; | |
132 | spin_unlock_irqrestore(&port->lock, flags); | |
133 | } | |
134 | ||
135 | static void s3c24xx_serial_stop_tx(struct uart_port *port) | |
136 | { | |
b73c289c BD |
137 | struct s3c24xx_uart_port *ourport = to_ourport(port); |
138 | ||
b497549a | 139 | if (tx_enabled(port)) { |
88bb4ea1 TA |
140 | if (s3c24xx_serial_has_interrupt_mask(port)) |
141 | __set_bit(S3C64XX_UINTM_TXD, | |
142 | portaddrl(port, S3C64XX_UINTM)); | |
143 | else | |
144 | disable_irq_nosync(ourport->tx_irq); | |
b497549a BD |
145 | tx_enabled(port) = 0; |
146 | if (port->flags & UPF_CONS_FLOW) | |
147 | s3c24xx_serial_rx_enable(port); | |
148 | } | |
149 | } | |
150 | ||
151 | static void s3c24xx_serial_start_tx(struct uart_port *port) | |
152 | { | |
b73c289c BD |
153 | struct s3c24xx_uart_port *ourport = to_ourport(port); |
154 | ||
b497549a BD |
155 | if (!tx_enabled(port)) { |
156 | if (port->flags & UPF_CONS_FLOW) | |
157 | s3c24xx_serial_rx_disable(port); | |
158 | ||
88bb4ea1 TA |
159 | if (s3c24xx_serial_has_interrupt_mask(port)) |
160 | __clear_bit(S3C64XX_UINTM_TXD, | |
161 | portaddrl(port, S3C64XX_UINTM)); | |
162 | else | |
163 | enable_irq(ourport->tx_irq); | |
b497549a BD |
164 | tx_enabled(port) = 1; |
165 | } | |
166 | } | |
167 | ||
b497549a BD |
168 | static void s3c24xx_serial_stop_rx(struct uart_port *port) |
169 | { | |
b73c289c BD |
170 | struct s3c24xx_uart_port *ourport = to_ourport(port); |
171 | ||
b497549a BD |
172 | if (rx_enabled(port)) { |
173 | dbg("s3c24xx_serial_stop_rx: port=%p\n", port); | |
88bb4ea1 TA |
174 | if (s3c24xx_serial_has_interrupt_mask(port)) |
175 | __set_bit(S3C64XX_UINTM_RXD, | |
176 | portaddrl(port, S3C64XX_UINTM)); | |
177 | else | |
178 | disable_irq_nosync(ourport->rx_irq); | |
b497549a BD |
179 | rx_enabled(port) = 0; |
180 | } | |
181 | } | |
182 | ||
183 | static void s3c24xx_serial_enable_ms(struct uart_port *port) | |
184 | { | |
185 | } | |
186 | ||
187 | static inline struct s3c24xx_uart_info *s3c24xx_port_to_info(struct uart_port *port) | |
188 | { | |
189 | return to_ourport(port)->info; | |
190 | } | |
191 | ||
192 | static inline struct s3c2410_uartcfg *s3c24xx_port_to_cfg(struct uart_port *port) | |
193 | { | |
4d84e970 TA |
194 | struct s3c24xx_uart_port *ourport; |
195 | ||
b497549a BD |
196 | if (port->dev == NULL) |
197 | return NULL; | |
198 | ||
4d84e970 TA |
199 | ourport = container_of(port, struct s3c24xx_uart_port, port); |
200 | return ourport->cfg; | |
b497549a BD |
201 | } |
202 | ||
203 | static int s3c24xx_serial_rx_fifocnt(struct s3c24xx_uart_port *ourport, | |
204 | unsigned long ufstat) | |
205 | { | |
206 | struct s3c24xx_uart_info *info = ourport->info; | |
207 | ||
208 | if (ufstat & info->rx_fifofull) | |
da121506 | 209 | return ourport->port.fifosize; |
b497549a BD |
210 | |
211 | return (ufstat & info->rx_fifomask) >> info->rx_fifoshift; | |
212 | } | |
213 | ||
214 | ||
215 | /* ? - where has parity gone?? */ | |
216 | #define S3C2410_UERSTAT_PARITY (0x1000) | |
217 | ||
218 | static irqreturn_t | |
219 | s3c24xx_serial_rx_chars(int irq, void *dev_id) | |
220 | { | |
221 | struct s3c24xx_uart_port *ourport = dev_id; | |
222 | struct uart_port *port = &ourport->port; | |
b497549a | 223 | unsigned int ufcon, ch, flag, ufstat, uerstat; |
c15c3747 | 224 | unsigned long flags; |
b497549a BD |
225 | int max_count = 64; |
226 | ||
c15c3747 TA |
227 | spin_lock_irqsave(&port->lock, flags); |
228 | ||
b497549a BD |
229 | while (max_count-- > 0) { |
230 | ufcon = rd_regl(port, S3C2410_UFCON); | |
231 | ufstat = rd_regl(port, S3C2410_UFSTAT); | |
232 | ||
233 | if (s3c24xx_serial_rx_fifocnt(ourport, ufstat) == 0) | |
234 | break; | |
235 | ||
236 | uerstat = rd_regl(port, S3C2410_UERSTAT); | |
237 | ch = rd_regb(port, S3C2410_URXH); | |
238 | ||
239 | if (port->flags & UPF_CONS_FLOW) { | |
240 | int txe = s3c24xx_serial_txempty_nofifo(port); | |
241 | ||
242 | if (rx_enabled(port)) { | |
243 | if (!txe) { | |
244 | rx_enabled(port) = 0; | |
245 | continue; | |
246 | } | |
247 | } else { | |
248 | if (txe) { | |
249 | ufcon |= S3C2410_UFCON_RESETRX; | |
250 | wr_regl(port, S3C2410_UFCON, ufcon); | |
251 | rx_enabled(port) = 1; | |
252 | goto out; | |
253 | } | |
254 | continue; | |
255 | } | |
256 | } | |
257 | ||
258 | /* insert the character into the buffer */ | |
259 | ||
260 | flag = TTY_NORMAL; | |
261 | port->icount.rx++; | |
262 | ||
263 | if (unlikely(uerstat & S3C2410_UERSTAT_ANY)) { | |
264 | dbg("rxerr: port ch=0x%02x, rxs=0x%08x\n", | |
265 | ch, uerstat); | |
266 | ||
267 | /* check for break */ | |
268 | if (uerstat & S3C2410_UERSTAT_BREAK) { | |
269 | dbg("break!\n"); | |
270 | port->icount.brk++; | |
271 | if (uart_handle_break(port)) | |
9303ac15 | 272 | goto ignore_char; |
b497549a BD |
273 | } |
274 | ||
275 | if (uerstat & S3C2410_UERSTAT_FRAME) | |
276 | port->icount.frame++; | |
277 | if (uerstat & S3C2410_UERSTAT_OVERRUN) | |
278 | port->icount.overrun++; | |
279 | ||
280 | uerstat &= port->read_status_mask; | |
281 | ||
282 | if (uerstat & S3C2410_UERSTAT_BREAK) | |
283 | flag = TTY_BREAK; | |
284 | else if (uerstat & S3C2410_UERSTAT_PARITY) | |
285 | flag = TTY_PARITY; | |
286 | else if (uerstat & (S3C2410_UERSTAT_FRAME | | |
287 | S3C2410_UERSTAT_OVERRUN)) | |
288 | flag = TTY_FRAME; | |
289 | } | |
290 | ||
291 | if (uart_handle_sysrq_char(port, ch)) | |
292 | goto ignore_char; | |
293 | ||
294 | uart_insert_char(port, uerstat, S3C2410_UERSTAT_OVERRUN, | |
295 | ch, flag); | |
296 | ||
297 | ignore_char: | |
298 | continue; | |
299 | } | |
2e124b4a | 300 | tty_flip_buffer_push(&port->state->port); |
b497549a BD |
301 | |
302 | out: | |
c15c3747 | 303 | spin_unlock_irqrestore(&port->lock, flags); |
b497549a BD |
304 | return IRQ_HANDLED; |
305 | } | |
306 | ||
307 | static irqreturn_t s3c24xx_serial_tx_chars(int irq, void *id) | |
308 | { | |
309 | struct s3c24xx_uart_port *ourport = id; | |
310 | struct uart_port *port = &ourport->port; | |
ebd2c8f6 | 311 | struct circ_buf *xmit = &port->state->xmit; |
c15c3747 | 312 | unsigned long flags; |
b497549a BD |
313 | int count = 256; |
314 | ||
c15c3747 TA |
315 | spin_lock_irqsave(&port->lock, flags); |
316 | ||
b497549a BD |
317 | if (port->x_char) { |
318 | wr_regb(port, S3C2410_UTXH, port->x_char); | |
319 | port->icount.tx++; | |
320 | port->x_char = 0; | |
321 | goto out; | |
322 | } | |
323 | ||
25985edc | 324 | /* if there isn't anything more to transmit, or the uart is now |
b497549a BD |
325 | * stopped, disable the uart and exit |
326 | */ | |
327 | ||
328 | if (uart_circ_empty(xmit) || uart_tx_stopped(port)) { | |
329 | s3c24xx_serial_stop_tx(port); | |
330 | goto out; | |
331 | } | |
332 | ||
333 | /* try and drain the buffer... */ | |
334 | ||
335 | while (!uart_circ_empty(xmit) && count-- > 0) { | |
336 | if (rd_regl(port, S3C2410_UFSTAT) & ourport->info->tx_fifofull) | |
337 | break; | |
338 | ||
339 | wr_regb(port, S3C2410_UTXH, xmit->buf[xmit->tail]); | |
340 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); | |
341 | port->icount.tx++; | |
342 | } | |
343 | ||
c15c3747 TA |
344 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) { |
345 | spin_unlock(&port->lock); | |
b497549a | 346 | uart_write_wakeup(port); |
c15c3747 TA |
347 | spin_lock(&port->lock); |
348 | } | |
b497549a BD |
349 | |
350 | if (uart_circ_empty(xmit)) | |
351 | s3c24xx_serial_stop_tx(port); | |
352 | ||
353 | out: | |
c15c3747 | 354 | spin_unlock_irqrestore(&port->lock, flags); |
b497549a BD |
355 | return IRQ_HANDLED; |
356 | } | |
357 | ||
88bb4ea1 TA |
358 | /* interrupt handler for s3c64xx and later SoC's.*/ |
359 | static irqreturn_t s3c64xx_serial_handle_irq(int irq, void *id) | |
360 | { | |
361 | struct s3c24xx_uart_port *ourport = id; | |
362 | struct uart_port *port = &ourport->port; | |
363 | unsigned int pend = rd_regl(port, S3C64XX_UINTP); | |
88bb4ea1 TA |
364 | irqreturn_t ret = IRQ_HANDLED; |
365 | ||
88bb4ea1 TA |
366 | if (pend & S3C64XX_UINTM_RXD_MSK) { |
367 | ret = s3c24xx_serial_rx_chars(irq, id); | |
368 | wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_RXD_MSK); | |
369 | } | |
370 | if (pend & S3C64XX_UINTM_TXD_MSK) { | |
371 | ret = s3c24xx_serial_tx_chars(irq, id); | |
372 | wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_TXD_MSK); | |
373 | } | |
88bb4ea1 TA |
374 | return ret; |
375 | } | |
376 | ||
b497549a BD |
377 | static unsigned int s3c24xx_serial_tx_empty(struct uart_port *port) |
378 | { | |
379 | struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port); | |
380 | unsigned long ufstat = rd_regl(port, S3C2410_UFSTAT); | |
381 | unsigned long ufcon = rd_regl(port, S3C2410_UFCON); | |
382 | ||
383 | if (ufcon & S3C2410_UFCON_FIFOMODE) { | |
384 | if ((ufstat & info->tx_fifomask) != 0 || | |
385 | (ufstat & info->tx_fifofull)) | |
386 | return 0; | |
387 | ||
388 | return 1; | |
389 | } | |
390 | ||
391 | return s3c24xx_serial_txempty_nofifo(port); | |
392 | } | |
393 | ||
394 | /* no modem control lines */ | |
395 | static unsigned int s3c24xx_serial_get_mctrl(struct uart_port *port) | |
396 | { | |
397 | unsigned int umstat = rd_regb(port, S3C2410_UMSTAT); | |
398 | ||
399 | if (umstat & S3C2410_UMSTAT_CTS) | |
400 | return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS; | |
401 | else | |
402 | return TIOCM_CAR | TIOCM_DSR; | |
403 | } | |
404 | ||
405 | static void s3c24xx_serial_set_mctrl(struct uart_port *port, unsigned int mctrl) | |
406 | { | |
407 | /* todo - possibly remove AFC and do manual CTS */ | |
408 | } | |
409 | ||
410 | static void s3c24xx_serial_break_ctl(struct uart_port *port, int break_state) | |
411 | { | |
412 | unsigned long flags; | |
413 | unsigned int ucon; | |
414 | ||
415 | spin_lock_irqsave(&port->lock, flags); | |
416 | ||
417 | ucon = rd_regl(port, S3C2410_UCON); | |
418 | ||
419 | if (break_state) | |
420 | ucon |= S3C2410_UCON_SBREAK; | |
421 | else | |
422 | ucon &= ~S3C2410_UCON_SBREAK; | |
423 | ||
424 | wr_regl(port, S3C2410_UCON, ucon); | |
425 | ||
426 | spin_unlock_irqrestore(&port->lock, flags); | |
427 | } | |
428 | ||
429 | static void s3c24xx_serial_shutdown(struct uart_port *port) | |
430 | { | |
431 | struct s3c24xx_uart_port *ourport = to_ourport(port); | |
432 | ||
433 | if (ourport->tx_claimed) { | |
88bb4ea1 TA |
434 | if (!s3c24xx_serial_has_interrupt_mask(port)) |
435 | free_irq(ourport->tx_irq, ourport); | |
b497549a BD |
436 | tx_enabled(port) = 0; |
437 | ourport->tx_claimed = 0; | |
438 | } | |
439 | ||
440 | if (ourport->rx_claimed) { | |
88bb4ea1 TA |
441 | if (!s3c24xx_serial_has_interrupt_mask(port)) |
442 | free_irq(ourport->rx_irq, ourport); | |
b497549a BD |
443 | ourport->rx_claimed = 0; |
444 | rx_enabled(port) = 0; | |
445 | } | |
b497549a | 446 | |
88bb4ea1 TA |
447 | /* Clear pending interrupts and mask all interrupts */ |
448 | if (s3c24xx_serial_has_interrupt_mask(port)) { | |
b6ad2935 TF |
449 | free_irq(port->irq, ourport); |
450 | ||
88bb4ea1 TA |
451 | wr_regl(port, S3C64XX_UINTP, 0xf); |
452 | wr_regl(port, S3C64XX_UINTM, 0xf); | |
453 | } | |
454 | } | |
b497549a BD |
455 | |
456 | static int s3c24xx_serial_startup(struct uart_port *port) | |
457 | { | |
458 | struct s3c24xx_uart_port *ourport = to_ourport(port); | |
459 | int ret; | |
460 | ||
461 | dbg("s3c24xx_serial_startup: port=%p (%08lx,%p)\n", | |
462 | port->mapbase, port->membase); | |
463 | ||
464 | rx_enabled(port) = 1; | |
465 | ||
b73c289c | 466 | ret = request_irq(ourport->rx_irq, s3c24xx_serial_rx_chars, 0, |
b497549a BD |
467 | s3c24xx_serial_portname(port), ourport); |
468 | ||
469 | if (ret != 0) { | |
d20925e1 | 470 | dev_err(port->dev, "cannot get irq %d\n", ourport->rx_irq); |
b497549a BD |
471 | return ret; |
472 | } | |
473 | ||
474 | ourport->rx_claimed = 1; | |
475 | ||
476 | dbg("requesting tx irq...\n"); | |
477 | ||
478 | tx_enabled(port) = 1; | |
479 | ||
b73c289c | 480 | ret = request_irq(ourport->tx_irq, s3c24xx_serial_tx_chars, 0, |
b497549a BD |
481 | s3c24xx_serial_portname(port), ourport); |
482 | ||
483 | if (ret) { | |
d20925e1 | 484 | dev_err(port->dev, "cannot get irq %d\n", ourport->tx_irq); |
b497549a BD |
485 | goto err; |
486 | } | |
487 | ||
488 | ourport->tx_claimed = 1; | |
489 | ||
490 | dbg("s3c24xx_serial_startup ok\n"); | |
491 | ||
492 | /* the port reset code should have done the correct | |
493 | * register setup for the port controls */ | |
494 | ||
495 | return ret; | |
496 | ||
497 | err: | |
498 | s3c24xx_serial_shutdown(port); | |
499 | return ret; | |
500 | } | |
501 | ||
88bb4ea1 TA |
502 | static int s3c64xx_serial_startup(struct uart_port *port) |
503 | { | |
504 | struct s3c24xx_uart_port *ourport = to_ourport(port); | |
505 | int ret; | |
506 | ||
507 | dbg("s3c64xx_serial_startup: port=%p (%08lx,%p)\n", | |
508 | port->mapbase, port->membase); | |
509 | ||
b6ad2935 TF |
510 | wr_regl(port, S3C64XX_UINTM, 0xf); |
511 | ||
88bb4ea1 TA |
512 | ret = request_irq(port->irq, s3c64xx_serial_handle_irq, IRQF_SHARED, |
513 | s3c24xx_serial_portname(port), ourport); | |
514 | if (ret) { | |
d20925e1 | 515 | dev_err(port->dev, "cannot get irq %d\n", port->irq); |
88bb4ea1 TA |
516 | return ret; |
517 | } | |
518 | ||
519 | /* For compatibility with s3c24xx Soc's */ | |
520 | rx_enabled(port) = 1; | |
521 | ourport->rx_claimed = 1; | |
522 | tx_enabled(port) = 0; | |
523 | ourport->tx_claimed = 1; | |
524 | ||
525 | /* Enable Rx Interrupt */ | |
526 | __clear_bit(S3C64XX_UINTM_RXD, portaddrl(port, S3C64XX_UINTM)); | |
527 | dbg("s3c64xx_serial_startup ok\n"); | |
528 | return ret; | |
529 | } | |
530 | ||
b497549a BD |
531 | /* power power management control */ |
532 | ||
533 | static void s3c24xx_serial_pm(struct uart_port *port, unsigned int level, | |
534 | unsigned int old) | |
535 | { | |
536 | struct s3c24xx_uart_port *ourport = to_ourport(port); | |
537 | ||
30555476 BD |
538 | ourport->pm_level = level; |
539 | ||
b497549a BD |
540 | switch (level) { |
541 | case 3: | |
7cd88831 | 542 | if (!IS_ERR(ourport->baudclk)) |
9484b009 | 543 | clk_disable_unprepare(ourport->baudclk); |
b497549a | 544 | |
9484b009 | 545 | clk_disable_unprepare(ourport->clk); |
b497549a BD |
546 | break; |
547 | ||
548 | case 0: | |
9484b009 | 549 | clk_prepare_enable(ourport->clk); |
b497549a | 550 | |
7cd88831 | 551 | if (!IS_ERR(ourport->baudclk)) |
9484b009 | 552 | clk_prepare_enable(ourport->baudclk); |
b497549a BD |
553 | |
554 | break; | |
555 | default: | |
d20925e1 | 556 | dev_err(port->dev, "s3c24xx_serial: unknown pm %d\n", level); |
b497549a BD |
557 | } |
558 | } | |
559 | ||
560 | /* baud rate calculation | |
561 | * | |
562 | * The UARTs on the S3C2410/S3C2440 can take their clocks from a number | |
563 | * of different sources, including the peripheral clock ("pclk") and an | |
564 | * external clock ("uclk"). The S3C2440 also adds the core clock ("fclk") | |
565 | * with a programmable extra divisor. | |
566 | * | |
567 | * The following code goes through the clock sources, and calculates the | |
568 | * baud clocks (and the resultant actual baud rates) and then tries to | |
569 | * pick the closest one and select that. | |
570 | * | |
571 | */ | |
572 | ||
5f5a7a55 | 573 | #define MAX_CLK_NAME_LENGTH 15 |
b497549a | 574 | |
5f5a7a55 | 575 | static inline int s3c24xx_serial_getsource(struct uart_port *port) |
b497549a BD |
576 | { |
577 | struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port); | |
5f5a7a55 | 578 | unsigned int ucon; |
b497549a | 579 | |
5f5a7a55 TA |
580 | if (info->num_clks == 1) |
581 | return 0; | |
b497549a | 582 | |
5f5a7a55 TA |
583 | ucon = rd_regl(port, S3C2410_UCON); |
584 | ucon &= info->clksel_mask; | |
585 | return ucon >> info->clksel_shift; | |
b497549a BD |
586 | } |
587 | ||
5f5a7a55 TA |
588 | static void s3c24xx_serial_setsource(struct uart_port *port, |
589 | unsigned int clk_sel) | |
b497549a | 590 | { |
5f5a7a55 TA |
591 | struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port); |
592 | unsigned int ucon; | |
b497549a | 593 | |
5f5a7a55 TA |
594 | if (info->num_clks == 1) |
595 | return; | |
090f848d | 596 | |
5f5a7a55 TA |
597 | ucon = rd_regl(port, S3C2410_UCON); |
598 | if ((ucon & info->clksel_mask) >> info->clksel_shift == clk_sel) | |
599 | return; | |
b497549a | 600 | |
5f5a7a55 TA |
601 | ucon &= ~info->clksel_mask; |
602 | ucon |= clk_sel << info->clksel_shift; | |
603 | wr_regl(port, S3C2410_UCON, ucon); | |
b497549a BD |
604 | } |
605 | ||
5f5a7a55 TA |
606 | static unsigned int s3c24xx_serial_getclk(struct s3c24xx_uart_port *ourport, |
607 | unsigned int req_baud, struct clk **best_clk, | |
608 | unsigned int *clk_num) | |
b497549a | 609 | { |
5f5a7a55 TA |
610 | struct s3c24xx_uart_info *info = ourport->info; |
611 | struct clk *clk; | |
612 | unsigned long rate; | |
613 | unsigned int cnt, baud, quot, clk_sel, best_quot = 0; | |
614 | char clkname[MAX_CLK_NAME_LENGTH]; | |
615 | int calc_deviation, deviation = (1 << 30) - 1; | |
616 | ||
5f5a7a55 TA |
617 | clk_sel = (ourport->cfg->clk_sel) ? ourport->cfg->clk_sel : |
618 | ourport->info->def_clk_sel; | |
619 | for (cnt = 0; cnt < info->num_clks; cnt++) { | |
620 | if (!(clk_sel & (1 << cnt))) | |
621 | continue; | |
622 | ||
623 | sprintf(clkname, "clk_uart_baud%d", cnt); | |
624 | clk = clk_get(ourport->port.dev, clkname); | |
7cd88831 | 625 | if (IS_ERR(clk)) |
5f5a7a55 TA |
626 | continue; |
627 | ||
628 | rate = clk_get_rate(clk); | |
629 | if (!rate) | |
630 | continue; | |
631 | ||
632 | if (ourport->info->has_divslot) { | |
633 | unsigned long div = rate / req_baud; | |
634 | ||
635 | /* The UDIVSLOT register on the newer UARTs allows us to | |
636 | * get a divisor adjustment of 1/16th on the baud clock. | |
637 | * | |
638 | * We don't keep the UDIVSLOT value (the 16ths we | |
639 | * calculated by not multiplying the baud by 16) as it | |
640 | * is easy enough to recalculate. | |
641 | */ | |
642 | ||
643 | quot = div / 16; | |
644 | baud = rate / div; | |
645 | } else { | |
646 | quot = (rate + (8 * req_baud)) / (16 * req_baud); | |
647 | baud = rate / (quot * 16); | |
b497549a | 648 | } |
5f5a7a55 | 649 | quot--; |
b497549a | 650 | |
5f5a7a55 TA |
651 | calc_deviation = req_baud - baud; |
652 | if (calc_deviation < 0) | |
653 | calc_deviation = -calc_deviation; | |
b497549a | 654 | |
5f5a7a55 TA |
655 | if (calc_deviation < deviation) { |
656 | *best_clk = clk; | |
657 | best_quot = quot; | |
658 | *clk_num = cnt; | |
659 | deviation = calc_deviation; | |
b497549a BD |
660 | } |
661 | } | |
662 | ||
5f5a7a55 | 663 | return best_quot; |
b497549a BD |
664 | } |
665 | ||
090f848d BD |
666 | /* udivslot_table[] |
667 | * | |
668 | * This table takes the fractional value of the baud divisor and gives | |
669 | * the recommended setting for the UDIVSLOT register. | |
670 | */ | |
671 | static u16 udivslot_table[16] = { | |
672 | [0] = 0x0000, | |
673 | [1] = 0x0080, | |
674 | [2] = 0x0808, | |
675 | [3] = 0x0888, | |
676 | [4] = 0x2222, | |
677 | [5] = 0x4924, | |
678 | [6] = 0x4A52, | |
679 | [7] = 0x54AA, | |
680 | [8] = 0x5555, | |
681 | [9] = 0xD555, | |
682 | [10] = 0xD5D5, | |
683 | [11] = 0xDDD5, | |
684 | [12] = 0xDDDD, | |
685 | [13] = 0xDFDD, | |
686 | [14] = 0xDFDF, | |
687 | [15] = 0xFFDF, | |
688 | }; | |
689 | ||
b497549a BD |
690 | static void s3c24xx_serial_set_termios(struct uart_port *port, |
691 | struct ktermios *termios, | |
692 | struct ktermios *old) | |
693 | { | |
694 | struct s3c2410_uartcfg *cfg = s3c24xx_port_to_cfg(port); | |
695 | struct s3c24xx_uart_port *ourport = to_ourport(port); | |
7cd88831 | 696 | struct clk *clk = ERR_PTR(-EINVAL); |
b497549a | 697 | unsigned long flags; |
5f5a7a55 | 698 | unsigned int baud, quot, clk_sel = 0; |
b497549a BD |
699 | unsigned int ulcon; |
700 | unsigned int umcon; | |
090f848d | 701 | unsigned int udivslot = 0; |
b497549a BD |
702 | |
703 | /* | |
704 | * We don't support modem control lines. | |
705 | */ | |
706 | termios->c_cflag &= ~(HUPCL | CMSPAR); | |
707 | termios->c_cflag |= CLOCAL; | |
708 | ||
709 | /* | |
710 | * Ask the core to calculate the divisor for us. | |
711 | */ | |
712 | ||
713 | baud = uart_get_baud_rate(port, termios, old, 0, 115200*8); | |
5f5a7a55 | 714 | quot = s3c24xx_serial_getclk(ourport, baud, &clk, &clk_sel); |
b497549a BD |
715 | if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST) |
716 | quot = port->custom_divisor; | |
7cd88831 | 717 | if (IS_ERR(clk)) |
5f5a7a55 | 718 | return; |
b497549a BD |
719 | |
720 | /* check to see if we need to change clock source */ | |
721 | ||
5f5a7a55 TA |
722 | if (ourport->baudclk != clk) { |
723 | s3c24xx_serial_setsource(port, clk_sel); | |
b497549a | 724 | |
7cd88831 | 725 | if (!IS_ERR(ourport->baudclk)) { |
9484b009 | 726 | clk_disable_unprepare(ourport->baudclk); |
7cd88831 | 727 | ourport->baudclk = ERR_PTR(-EINVAL); |
b497549a BD |
728 | } |
729 | ||
9484b009 | 730 | clk_prepare_enable(clk); |
b497549a | 731 | |
b497549a | 732 | ourport->baudclk = clk; |
30555476 | 733 | ourport->baudclk_rate = clk ? clk_get_rate(clk) : 0; |
b497549a BD |
734 | } |
735 | ||
090f848d BD |
736 | if (ourport->info->has_divslot) { |
737 | unsigned int div = ourport->baudclk_rate / baud; | |
738 | ||
8b526ae4 JL |
739 | if (cfg->has_fracval) { |
740 | udivslot = (div & 15); | |
741 | dbg("fracval = %04x\n", udivslot); | |
742 | } else { | |
743 | udivslot = udivslot_table[div & 15]; | |
744 | dbg("udivslot = %04x (div %d)\n", udivslot, div & 15); | |
745 | } | |
090f848d BD |
746 | } |
747 | ||
b497549a BD |
748 | switch (termios->c_cflag & CSIZE) { |
749 | case CS5: | |
750 | dbg("config: 5bits/char\n"); | |
751 | ulcon = S3C2410_LCON_CS5; | |
752 | break; | |
753 | case CS6: | |
754 | dbg("config: 6bits/char\n"); | |
755 | ulcon = S3C2410_LCON_CS6; | |
756 | break; | |
757 | case CS7: | |
758 | dbg("config: 7bits/char\n"); | |
759 | ulcon = S3C2410_LCON_CS7; | |
760 | break; | |
761 | case CS8: | |
762 | default: | |
763 | dbg("config: 8bits/char\n"); | |
764 | ulcon = S3C2410_LCON_CS8; | |
765 | break; | |
766 | } | |
767 | ||
768 | /* preserve original lcon IR settings */ | |
769 | ulcon |= (cfg->ulcon & S3C2410_LCON_IRM); | |
770 | ||
771 | if (termios->c_cflag & CSTOPB) | |
772 | ulcon |= S3C2410_LCON_STOPB; | |
773 | ||
774 | umcon = (termios->c_cflag & CRTSCTS) ? S3C2410_UMCOM_AFC : 0; | |
775 | ||
776 | if (termios->c_cflag & PARENB) { | |
777 | if (termios->c_cflag & PARODD) | |
778 | ulcon |= S3C2410_LCON_PODD; | |
779 | else | |
780 | ulcon |= S3C2410_LCON_PEVEN; | |
781 | } else { | |
782 | ulcon |= S3C2410_LCON_PNONE; | |
783 | } | |
784 | ||
785 | spin_lock_irqsave(&port->lock, flags); | |
786 | ||
090f848d BD |
787 | dbg("setting ulcon to %08x, brddiv to %d, udivslot %08x\n", |
788 | ulcon, quot, udivslot); | |
b497549a BD |
789 | |
790 | wr_regl(port, S3C2410_ULCON, ulcon); | |
791 | wr_regl(port, S3C2410_UBRDIV, quot); | |
792 | wr_regl(port, S3C2410_UMCON, umcon); | |
793 | ||
090f848d BD |
794 | if (ourport->info->has_divslot) |
795 | wr_regl(port, S3C2443_DIVSLOT, udivslot); | |
796 | ||
b497549a BD |
797 | dbg("uart: ulcon = 0x%08x, ucon = 0x%08x, ufcon = 0x%08x\n", |
798 | rd_regl(port, S3C2410_ULCON), | |
799 | rd_regl(port, S3C2410_UCON), | |
800 | rd_regl(port, S3C2410_UFCON)); | |
801 | ||
802 | /* | |
803 | * Update the per-port timeout. | |
804 | */ | |
805 | uart_update_timeout(port, termios->c_cflag, baud); | |
806 | ||
807 | /* | |
808 | * Which character status flags are we interested in? | |
809 | */ | |
810 | port->read_status_mask = S3C2410_UERSTAT_OVERRUN; | |
811 | if (termios->c_iflag & INPCK) | |
812 | port->read_status_mask |= S3C2410_UERSTAT_FRAME | S3C2410_UERSTAT_PARITY; | |
813 | ||
814 | /* | |
815 | * Which character status flags should we ignore? | |
816 | */ | |
817 | port->ignore_status_mask = 0; | |
818 | if (termios->c_iflag & IGNPAR) | |
819 | port->ignore_status_mask |= S3C2410_UERSTAT_OVERRUN; | |
820 | if (termios->c_iflag & IGNBRK && termios->c_iflag & IGNPAR) | |
821 | port->ignore_status_mask |= S3C2410_UERSTAT_FRAME; | |
822 | ||
823 | /* | |
824 | * Ignore all characters if CREAD is not set. | |
825 | */ | |
826 | if ((termios->c_cflag & CREAD) == 0) | |
827 | port->ignore_status_mask |= RXSTAT_DUMMY_READ; | |
828 | ||
829 | spin_unlock_irqrestore(&port->lock, flags); | |
830 | } | |
831 | ||
832 | static const char *s3c24xx_serial_type(struct uart_port *port) | |
833 | { | |
834 | switch (port->type) { | |
835 | case PORT_S3C2410: | |
836 | return "S3C2410"; | |
837 | case PORT_S3C2440: | |
838 | return "S3C2440"; | |
839 | case PORT_S3C2412: | |
840 | return "S3C2412"; | |
b690ace5 BD |
841 | case PORT_S3C6400: |
842 | return "S3C6400/10"; | |
b497549a BD |
843 | default: |
844 | return NULL; | |
845 | } | |
846 | } | |
847 | ||
848 | #define MAP_SIZE (0x100) | |
849 | ||
850 | static void s3c24xx_serial_release_port(struct uart_port *port) | |
851 | { | |
852 | release_mem_region(port->mapbase, MAP_SIZE); | |
853 | } | |
854 | ||
855 | static int s3c24xx_serial_request_port(struct uart_port *port) | |
856 | { | |
857 | const char *name = s3c24xx_serial_portname(port); | |
858 | return request_mem_region(port->mapbase, MAP_SIZE, name) ? 0 : -EBUSY; | |
859 | } | |
860 | ||
861 | static void s3c24xx_serial_config_port(struct uart_port *port, int flags) | |
862 | { | |
863 | struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port); | |
864 | ||
865 | if (flags & UART_CONFIG_TYPE && | |
866 | s3c24xx_serial_request_port(port) == 0) | |
867 | port->type = info->type; | |
868 | } | |
869 | ||
870 | /* | |
871 | * verify the new serial_struct (for TIOCSSERIAL). | |
872 | */ | |
873 | static int | |
874 | s3c24xx_serial_verify_port(struct uart_port *port, struct serial_struct *ser) | |
875 | { | |
876 | struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port); | |
877 | ||
878 | if (ser->type != PORT_UNKNOWN && ser->type != info->type) | |
879 | return -EINVAL; | |
880 | ||
881 | return 0; | |
882 | } | |
883 | ||
884 | ||
885 | #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE | |
886 | ||
887 | static struct console s3c24xx_serial_console; | |
888 | ||
93b5c032 JP |
889 | static int __init s3c24xx_serial_console_init(void) |
890 | { | |
891 | register_console(&s3c24xx_serial_console); | |
892 | return 0; | |
893 | } | |
894 | console_initcall(s3c24xx_serial_console_init); | |
895 | ||
b497549a BD |
896 | #define S3C24XX_SERIAL_CONSOLE &s3c24xx_serial_console |
897 | #else | |
898 | #define S3C24XX_SERIAL_CONSOLE NULL | |
899 | #endif | |
900 | ||
84f57d9e | 901 | #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL) |
93b5c032 JP |
902 | static int s3c24xx_serial_get_poll_char(struct uart_port *port); |
903 | static void s3c24xx_serial_put_poll_char(struct uart_port *port, | |
904 | unsigned char c); | |
905 | #endif | |
906 | ||
b497549a BD |
907 | static struct uart_ops s3c24xx_serial_ops = { |
908 | .pm = s3c24xx_serial_pm, | |
909 | .tx_empty = s3c24xx_serial_tx_empty, | |
910 | .get_mctrl = s3c24xx_serial_get_mctrl, | |
911 | .set_mctrl = s3c24xx_serial_set_mctrl, | |
912 | .stop_tx = s3c24xx_serial_stop_tx, | |
913 | .start_tx = s3c24xx_serial_start_tx, | |
914 | .stop_rx = s3c24xx_serial_stop_rx, | |
915 | .enable_ms = s3c24xx_serial_enable_ms, | |
916 | .break_ctl = s3c24xx_serial_break_ctl, | |
917 | .startup = s3c24xx_serial_startup, | |
918 | .shutdown = s3c24xx_serial_shutdown, | |
919 | .set_termios = s3c24xx_serial_set_termios, | |
920 | .type = s3c24xx_serial_type, | |
921 | .release_port = s3c24xx_serial_release_port, | |
922 | .request_port = s3c24xx_serial_request_port, | |
923 | .config_port = s3c24xx_serial_config_port, | |
924 | .verify_port = s3c24xx_serial_verify_port, | |
84f57d9e | 925 | #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL) |
93b5c032 JP |
926 | .poll_get_char = s3c24xx_serial_get_poll_char, |
927 | .poll_put_char = s3c24xx_serial_put_poll_char, | |
928 | #endif | |
b497549a BD |
929 | }; |
930 | ||
b497549a BD |
931 | static struct uart_driver s3c24xx_uart_drv = { |
932 | .owner = THIS_MODULE, | |
2cf0c58e | 933 | .driver_name = "s3c2410_serial", |
bdd4915a | 934 | .nr = CONFIG_SERIAL_SAMSUNG_UARTS, |
b497549a | 935 | .cons = S3C24XX_SERIAL_CONSOLE, |
2cf0c58e | 936 | .dev_name = S3C24XX_SERIAL_NAME, |
b497549a BD |
937 | .major = S3C24XX_SERIAL_MAJOR, |
938 | .minor = S3C24XX_SERIAL_MINOR, | |
939 | }; | |
940 | ||
03d5e77b | 941 | static struct s3c24xx_uart_port s3c24xx_serial_ports[CONFIG_SERIAL_SAMSUNG_UARTS] = { |
b497549a BD |
942 | [0] = { |
943 | .port = { | |
944 | .lock = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[0].port.lock), | |
945 | .iotype = UPIO_MEM, | |
b497549a BD |
946 | .uartclk = 0, |
947 | .fifosize = 16, | |
948 | .ops = &s3c24xx_serial_ops, | |
949 | .flags = UPF_BOOT_AUTOCONF, | |
950 | .line = 0, | |
951 | } | |
952 | }, | |
953 | [1] = { | |
954 | .port = { | |
955 | .lock = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[1].port.lock), | |
956 | .iotype = UPIO_MEM, | |
b497549a BD |
957 | .uartclk = 0, |
958 | .fifosize = 16, | |
959 | .ops = &s3c24xx_serial_ops, | |
960 | .flags = UPF_BOOT_AUTOCONF, | |
961 | .line = 1, | |
962 | } | |
963 | }, | |
03d5e77b | 964 | #if CONFIG_SERIAL_SAMSUNG_UARTS > 2 |
b497549a BD |
965 | |
966 | [2] = { | |
967 | .port = { | |
968 | .lock = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[2].port.lock), | |
969 | .iotype = UPIO_MEM, | |
b497549a BD |
970 | .uartclk = 0, |
971 | .fifosize = 16, | |
972 | .ops = &s3c24xx_serial_ops, | |
973 | .flags = UPF_BOOT_AUTOCONF, | |
974 | .line = 2, | |
975 | } | |
03d5e77b BD |
976 | }, |
977 | #endif | |
978 | #if CONFIG_SERIAL_SAMSUNG_UARTS > 3 | |
979 | [3] = { | |
980 | .port = { | |
981 | .lock = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[3].port.lock), | |
982 | .iotype = UPIO_MEM, | |
03d5e77b BD |
983 | .uartclk = 0, |
984 | .fifosize = 16, | |
985 | .ops = &s3c24xx_serial_ops, | |
986 | .flags = UPF_BOOT_AUTOCONF, | |
987 | .line = 3, | |
988 | } | |
b497549a BD |
989 | } |
990 | #endif | |
991 | }; | |
992 | ||
993 | /* s3c24xx_serial_resetport | |
994 | * | |
0dfb3b41 | 995 | * reset the fifos and other the settings. |
b497549a BD |
996 | */ |
997 | ||
0dfb3b41 TA |
998 | static void s3c24xx_serial_resetport(struct uart_port *port, |
999 | struct s3c2410_uartcfg *cfg) | |
b497549a BD |
1000 | { |
1001 | struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port); | |
0dfb3b41 TA |
1002 | unsigned long ucon = rd_regl(port, S3C2410_UCON); |
1003 | unsigned int ucon_mask; | |
b497549a | 1004 | |
0dfb3b41 TA |
1005 | ucon_mask = info->clksel_mask; |
1006 | if (info->type == PORT_S3C2440) | |
1007 | ucon_mask |= S3C2440_UCON0_DIVMASK; | |
1008 | ||
1009 | ucon &= ucon_mask; | |
1010 | wr_regl(port, S3C2410_UCON, ucon | cfg->ucon); | |
1011 | ||
1012 | /* reset both fifos */ | |
1013 | wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH); | |
1014 | wr_regl(port, S3C2410_UFCON, cfg->ufcon); | |
1015 | ||
1016 | /* some delay is required after fifo reset */ | |
1017 | udelay(1); | |
b497549a BD |
1018 | } |
1019 | ||
30555476 BD |
1020 | |
1021 | #ifdef CONFIG_CPU_FREQ | |
1022 | ||
1023 | static int s3c24xx_serial_cpufreq_transition(struct notifier_block *nb, | |
1024 | unsigned long val, void *data) | |
1025 | { | |
1026 | struct s3c24xx_uart_port *port; | |
1027 | struct uart_port *uport; | |
1028 | ||
1029 | port = container_of(nb, struct s3c24xx_uart_port, freq_transition); | |
1030 | uport = &port->port; | |
1031 | ||
1032 | /* check to see if port is enabled */ | |
1033 | ||
1034 | if (port->pm_level != 0) | |
1035 | return 0; | |
1036 | ||
1037 | /* try and work out if the baudrate is changing, we can detect | |
1038 | * a change in rate, but we do not have support for detecting | |
1039 | * a disturbance in the clock-rate over the change. | |
1040 | */ | |
1041 | ||
25f04ad4 | 1042 | if (IS_ERR(port->baudclk)) |
30555476 BD |
1043 | goto exit; |
1044 | ||
25f04ad4 | 1045 | if (port->baudclk_rate == clk_get_rate(port->baudclk)) |
30555476 BD |
1046 | goto exit; |
1047 | ||
1048 | if (val == CPUFREQ_PRECHANGE) { | |
1049 | /* we should really shut the port down whilst the | |
1050 | * frequency change is in progress. */ | |
1051 | ||
1052 | } else if (val == CPUFREQ_POSTCHANGE) { | |
1053 | struct ktermios *termios; | |
1054 | struct tty_struct *tty; | |
1055 | ||
ebd2c8f6 | 1056 | if (uport->state == NULL) |
30555476 | 1057 | goto exit; |
30555476 | 1058 | |
ebd2c8f6 | 1059 | tty = uport->state->port.tty; |
30555476 | 1060 | |
7de40c21 | 1061 | if (tty == NULL) |
30555476 | 1062 | goto exit; |
30555476 | 1063 | |
adc8d746 | 1064 | termios = &tty->termios; |
30555476 BD |
1065 | |
1066 | if (termios == NULL) { | |
d20925e1 | 1067 | dev_warn(uport->dev, "%s: no termios?\n", __func__); |
30555476 BD |
1068 | goto exit; |
1069 | } | |
1070 | ||
1071 | s3c24xx_serial_set_termios(uport, termios, NULL); | |
1072 | } | |
1073 | ||
1074 | exit: | |
1075 | return 0; | |
1076 | } | |
1077 | ||
1078 | static inline int s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port) | |
1079 | { | |
1080 | port->freq_transition.notifier_call = s3c24xx_serial_cpufreq_transition; | |
1081 | ||
1082 | return cpufreq_register_notifier(&port->freq_transition, | |
1083 | CPUFREQ_TRANSITION_NOTIFIER); | |
1084 | } | |
1085 | ||
1086 | static inline void s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port) | |
1087 | { | |
1088 | cpufreq_unregister_notifier(&port->freq_transition, | |
1089 | CPUFREQ_TRANSITION_NOTIFIER); | |
1090 | } | |
1091 | ||
1092 | #else | |
1093 | static inline int s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port) | |
1094 | { | |
1095 | return 0; | |
1096 | } | |
1097 | ||
1098 | static inline void s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port) | |
1099 | { | |
1100 | } | |
1101 | #endif | |
1102 | ||
b497549a BD |
1103 | /* s3c24xx_serial_init_port |
1104 | * | |
1105 | * initialise a single serial port from the platform device given | |
1106 | */ | |
1107 | ||
1108 | static int s3c24xx_serial_init_port(struct s3c24xx_uart_port *ourport, | |
b497549a BD |
1109 | struct platform_device *platdev) |
1110 | { | |
1111 | struct uart_port *port = &ourport->port; | |
da121506 | 1112 | struct s3c2410_uartcfg *cfg = ourport->cfg; |
b497549a BD |
1113 | struct resource *res; |
1114 | int ret; | |
1115 | ||
1116 | dbg("s3c24xx_serial_init_port: port=%p, platdev=%p\n", port, platdev); | |
1117 | ||
1118 | if (platdev == NULL) | |
1119 | return -ENODEV; | |
1120 | ||
b497549a BD |
1121 | if (port->mapbase != 0) |
1122 | return 0; | |
1123 | ||
b497549a BD |
1124 | /* setup info for port */ |
1125 | port->dev = &platdev->dev; | |
b497549a | 1126 | |
88bb4ea1 TA |
1127 | /* Startup sequence is different for s3c64xx and higher SoC's */ |
1128 | if (s3c24xx_serial_has_interrupt_mask(port)) | |
1129 | s3c24xx_serial_ops.startup = s3c64xx_serial_startup; | |
1130 | ||
b497549a BD |
1131 | port->uartclk = 1; |
1132 | ||
1133 | if (cfg->uart_flags & UPF_CONS_FLOW) { | |
1134 | dbg("s3c24xx_serial_init_port: enabling flow control\n"); | |
1135 | port->flags |= UPF_CONS_FLOW; | |
1136 | } | |
1137 | ||
1138 | /* sort our the physical and virtual addresses for each UART */ | |
1139 | ||
1140 | res = platform_get_resource(platdev, IORESOURCE_MEM, 0); | |
1141 | if (res == NULL) { | |
d20925e1 | 1142 | dev_err(port->dev, "failed to find memory resource for uart\n"); |
b497549a BD |
1143 | return -EINVAL; |
1144 | } | |
1145 | ||
1146 | dbg("resource %p (%lx..%lx)\n", res, res->start, res->end); | |
1147 | ||
41147bfd TA |
1148 | port->membase = devm_ioremap(port->dev, res->start, resource_size(res)); |
1149 | if (!port->membase) { | |
1150 | dev_err(port->dev, "failed to remap controller address\n"); | |
1151 | return -EBUSY; | |
1152 | } | |
1153 | ||
b690ace5 | 1154 | port->mapbase = res->start; |
b497549a BD |
1155 | ret = platform_get_irq(platdev, 0); |
1156 | if (ret < 0) | |
1157 | port->irq = 0; | |
b73c289c | 1158 | else { |
b497549a | 1159 | port->irq = ret; |
b73c289c BD |
1160 | ourport->rx_irq = ret; |
1161 | ourport->tx_irq = ret + 1; | |
1162 | } | |
9303ac15 | 1163 | |
b73c289c BD |
1164 | ret = platform_get_irq(platdev, 1); |
1165 | if (ret > 0) | |
1166 | ourport->tx_irq = ret; | |
b497549a BD |
1167 | |
1168 | ourport->clk = clk_get(&platdev->dev, "uart"); | |
60e93575 CK |
1169 | if (IS_ERR(ourport->clk)) { |
1170 | pr_err("%s: Controller clock not found\n", | |
1171 | dev_name(&platdev->dev)); | |
1172 | return PTR_ERR(ourport->clk); | |
1173 | } | |
1174 | ||
1175 | ret = clk_prepare_enable(ourport->clk); | |
1176 | if (ret) { | |
1177 | pr_err("uart: clock failed to prepare+enable: %d\n", ret); | |
1178 | clk_put(ourport->clk); | |
1179 | return ret; | |
1180 | } | |
b497549a | 1181 | |
88bb4ea1 TA |
1182 | /* Keep all interrupts masked and cleared */ |
1183 | if (s3c24xx_serial_has_interrupt_mask(port)) { | |
1184 | wr_regl(port, S3C64XX_UINTM, 0xf); | |
1185 | wr_regl(port, S3C64XX_UINTP, 0xf); | |
1186 | wr_regl(port, S3C64XX_UINTSP, 0xf); | |
1187 | } | |
1188 | ||
b73c289c BD |
1189 | dbg("port: map=%08x, mem=%08x, irq=%d (%d,%d), clock=%ld\n", |
1190 | port->mapbase, port->membase, port->irq, | |
1191 | ourport->rx_irq, ourport->tx_irq, port->uartclk); | |
b497549a BD |
1192 | |
1193 | /* reset the fifos (and setup the uart) */ | |
1194 | s3c24xx_serial_resetport(port, cfg); | |
60e93575 | 1195 | clk_disable_unprepare(ourport->clk); |
b497549a BD |
1196 | return 0; |
1197 | } | |
1198 | ||
17efd2b7 | 1199 | #ifdef CONFIG_SAMSUNG_CLOCK |
b497549a BD |
1200 | static ssize_t s3c24xx_serial_show_clksrc(struct device *dev, |
1201 | struct device_attribute *attr, | |
1202 | char *buf) | |
1203 | { | |
1204 | struct uart_port *port = s3c24xx_dev_to_port(dev); | |
1205 | struct s3c24xx_uart_port *ourport = to_ourport(port); | |
1206 | ||
7cd88831 KK |
1207 | if (IS_ERR(ourport->baudclk)) |
1208 | return -EINVAL; | |
1209 | ||
7b15e1d9 KP |
1210 | return snprintf(buf, PAGE_SIZE, "* %s\n", |
1211 | ourport->baudclk->name ?: "(null)"); | |
b497549a BD |
1212 | } |
1213 | ||
1214 | static DEVICE_ATTR(clock_source, S_IRUGO, s3c24xx_serial_show_clksrc, NULL); | |
17efd2b7 | 1215 | #endif |
26c919e1 | 1216 | |
b497549a BD |
1217 | /* Device driver serial port probe */ |
1218 | ||
26c919e1 | 1219 | static const struct of_device_id s3c24xx_uart_dt_match[]; |
b497549a BD |
1220 | static int probe_index; |
1221 | ||
26c919e1 TA |
1222 | static inline struct s3c24xx_serial_drv_data *s3c24xx_get_driver_data( |
1223 | struct platform_device *pdev) | |
1224 | { | |
1225 | #ifdef CONFIG_OF | |
1226 | if (pdev->dev.of_node) { | |
1227 | const struct of_device_id *match; | |
1228 | match = of_match_node(s3c24xx_uart_dt_match, pdev->dev.of_node); | |
1229 | return (struct s3c24xx_serial_drv_data *)match->data; | |
1230 | } | |
1231 | #endif | |
1232 | return (struct s3c24xx_serial_drv_data *) | |
1233 | platform_get_device_id(pdev)->driver_data; | |
1234 | } | |
1235 | ||
da121506 | 1236 | static int s3c24xx_serial_probe(struct platform_device *pdev) |
b497549a BD |
1237 | { |
1238 | struct s3c24xx_uart_port *ourport; | |
1239 | int ret; | |
1240 | ||
da121506 | 1241 | dbg("s3c24xx_serial_probe(%p) %d\n", pdev, probe_index); |
b497549a BD |
1242 | |
1243 | ourport = &s3c24xx_serial_ports[probe_index]; | |
da121506 | 1244 | |
26c919e1 TA |
1245 | ourport->drv_data = s3c24xx_get_driver_data(pdev); |
1246 | if (!ourport->drv_data) { | |
1247 | dev_err(&pdev->dev, "could not find driver data\n"); | |
1248 | return -ENODEV; | |
1249 | } | |
da121506 | 1250 | |
7cd88831 | 1251 | ourport->baudclk = ERR_PTR(-EINVAL); |
da121506 | 1252 | ourport->info = ourport->drv_data->info; |
574de559 JH |
1253 | ourport->cfg = (dev_get_platdata(&pdev->dev)) ? |
1254 | (struct s3c2410_uartcfg *)dev_get_platdata(&pdev->dev) : | |
da121506 TA |
1255 | ourport->drv_data->def_cfg; |
1256 | ||
1257 | ourport->port.fifosize = (ourport->info->fifosize) ? | |
1258 | ourport->info->fifosize : | |
1259 | ourport->drv_data->fifosize[probe_index]; | |
1260 | ||
b497549a BD |
1261 | probe_index++; |
1262 | ||
1263 | dbg("%s: initialising port %p...\n", __func__, ourport); | |
1264 | ||
da121506 | 1265 | ret = s3c24xx_serial_init_port(ourport, pdev); |
b497549a BD |
1266 | if (ret < 0) |
1267 | goto probe_err; | |
1268 | ||
1269 | dbg("%s: adding port\n", __func__); | |
1270 | uart_add_one_port(&s3c24xx_uart_drv, &ourport->port); | |
da121506 | 1271 | platform_set_drvdata(pdev, &ourport->port); |
b497549a | 1272 | |
17efd2b7 | 1273 | #ifdef CONFIG_SAMSUNG_CLOCK |
da121506 | 1274 | ret = device_create_file(&pdev->dev, &dev_attr_clock_source); |
b497549a | 1275 | if (ret < 0) |
da121506 | 1276 | dev_err(&pdev->dev, "failed to add clock source attr.\n"); |
17efd2b7 | 1277 | #endif |
b497549a | 1278 | |
30555476 BD |
1279 | ret = s3c24xx_serial_cpufreq_register(ourport); |
1280 | if (ret < 0) | |
da121506 | 1281 | dev_err(&pdev->dev, "failed to add cpufreq notifier\n"); |
30555476 | 1282 | |
b497549a BD |
1283 | return 0; |
1284 | ||
1285 | probe_err: | |
1286 | return ret; | |
1287 | } | |
1288 | ||
ae8d8a14 | 1289 | static int s3c24xx_serial_remove(struct platform_device *dev) |
b497549a BD |
1290 | { |
1291 | struct uart_port *port = s3c24xx_dev_to_port(&dev->dev); | |
1292 | ||
1293 | if (port) { | |
30555476 | 1294 | s3c24xx_serial_cpufreq_deregister(to_ourport(port)); |
17efd2b7 | 1295 | #ifdef CONFIG_SAMSUNG_CLOCK |
b497549a | 1296 | device_remove_file(&dev->dev, &dev_attr_clock_source); |
17efd2b7 | 1297 | #endif |
b497549a BD |
1298 | uart_remove_one_port(&s3c24xx_uart_drv, port); |
1299 | } | |
1300 | ||
1301 | return 0; | |
1302 | } | |
1303 | ||
b497549a | 1304 | /* UART power management code */ |
aef7fe52 MH |
1305 | #ifdef CONFIG_PM_SLEEP |
1306 | static int s3c24xx_serial_suspend(struct device *dev) | |
b497549a | 1307 | { |
aef7fe52 | 1308 | struct uart_port *port = s3c24xx_dev_to_port(dev); |
b497549a BD |
1309 | |
1310 | if (port) | |
1311 | uart_suspend_port(&s3c24xx_uart_drv, port); | |
1312 | ||
1313 | return 0; | |
1314 | } | |
1315 | ||
aef7fe52 | 1316 | static int s3c24xx_serial_resume(struct device *dev) |
b497549a | 1317 | { |
aef7fe52 | 1318 | struct uart_port *port = s3c24xx_dev_to_port(dev); |
b497549a BD |
1319 | struct s3c24xx_uart_port *ourport = to_ourport(port); |
1320 | ||
1321 | if (port) { | |
9484b009 | 1322 | clk_prepare_enable(ourport->clk); |
b497549a | 1323 | s3c24xx_serial_resetport(port, s3c24xx_port_to_cfg(port)); |
9484b009 | 1324 | clk_disable_unprepare(ourport->clk); |
b497549a BD |
1325 | |
1326 | uart_resume_port(&s3c24xx_uart_drv, port); | |
1327 | } | |
1328 | ||
1329 | return 0; | |
1330 | } | |
aef7fe52 | 1331 | |
d09a7308 MS |
1332 | static int s3c24xx_serial_resume_noirq(struct device *dev) |
1333 | { | |
1334 | struct uart_port *port = s3c24xx_dev_to_port(dev); | |
1335 | ||
1336 | if (port) { | |
1337 | /* restore IRQ mask */ | |
1338 | if (s3c24xx_serial_has_interrupt_mask(port)) { | |
1339 | unsigned int uintm = 0xf; | |
1340 | if (tx_enabled(port)) | |
1341 | uintm &= ~S3C64XX_UINTM_TXD_MSK; | |
1342 | if (rx_enabled(port)) | |
1343 | uintm &= ~S3C64XX_UINTM_RXD_MSK; | |
1344 | wr_regl(port, S3C64XX_UINTM, uintm); | |
1345 | } | |
1346 | } | |
1347 | ||
1348 | return 0; | |
1349 | } | |
1350 | ||
aef7fe52 MH |
1351 | static const struct dev_pm_ops s3c24xx_serial_pm_ops = { |
1352 | .suspend = s3c24xx_serial_suspend, | |
1353 | .resume = s3c24xx_serial_resume, | |
d09a7308 | 1354 | .resume_noirq = s3c24xx_serial_resume_noirq, |
aef7fe52 | 1355 | }; |
b882fc1b KK |
1356 | #define SERIAL_SAMSUNG_PM_OPS (&s3c24xx_serial_pm_ops) |
1357 | ||
aef7fe52 | 1358 | #else /* !CONFIG_PM_SLEEP */ |
b882fc1b KK |
1359 | |
1360 | #define SERIAL_SAMSUNG_PM_OPS NULL | |
aef7fe52 | 1361 | #endif /* CONFIG_PM_SLEEP */ |
b497549a | 1362 | |
b497549a BD |
1363 | /* Console code */ |
1364 | ||
1365 | #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE | |
1366 | ||
1367 | static struct uart_port *cons_uart; | |
1368 | ||
1369 | static int | |
1370 | s3c24xx_serial_console_txrdy(struct uart_port *port, unsigned int ufcon) | |
1371 | { | |
1372 | struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port); | |
1373 | unsigned long ufstat, utrstat; | |
1374 | ||
1375 | if (ufcon & S3C2410_UFCON_FIFOMODE) { | |
9ddc5b6f | 1376 | /* fifo mode - check amount of data in fifo registers... */ |
b497549a BD |
1377 | |
1378 | ufstat = rd_regl(port, S3C2410_UFSTAT); | |
1379 | return (ufstat & info->tx_fifofull) ? 0 : 1; | |
1380 | } | |
1381 | ||
1382 | /* in non-fifo mode, we go and use the tx buffer empty */ | |
1383 | ||
1384 | utrstat = rd_regl(port, S3C2410_UTRSTAT); | |
1385 | return (utrstat & S3C2410_UTRSTAT_TXE) ? 1 : 0; | |
1386 | } | |
1387 | ||
38adbc54 MS |
1388 | static bool |
1389 | s3c24xx_port_configured(unsigned int ucon) | |
1390 | { | |
1391 | /* consider the serial port configured if the tx/rx mode set */ | |
1392 | return (ucon & 0xf) != 0; | |
1393 | } | |
1394 | ||
93b5c032 JP |
1395 | #ifdef CONFIG_CONSOLE_POLL |
1396 | /* | |
1397 | * Console polling routines for writing and reading from the uart while | |
1398 | * in an interrupt or debug context. | |
1399 | */ | |
1400 | ||
1401 | static int s3c24xx_serial_get_poll_char(struct uart_port *port) | |
1402 | { | |
1403 | struct s3c24xx_uart_port *ourport = to_ourport(port); | |
1404 | unsigned int ufstat; | |
1405 | ||
1406 | ufstat = rd_regl(port, S3C2410_UFSTAT); | |
1407 | if (s3c24xx_serial_rx_fifocnt(ourport, ufstat) == 0) | |
1408 | return NO_POLL_CHAR; | |
1409 | ||
1410 | return rd_regb(port, S3C2410_URXH); | |
1411 | } | |
1412 | ||
1413 | static void s3c24xx_serial_put_poll_char(struct uart_port *port, | |
1414 | unsigned char c) | |
1415 | { | |
1416 | unsigned int ufcon = rd_regl(cons_uart, S3C2410_UFCON); | |
38adbc54 MS |
1417 | unsigned int ucon = rd_regl(cons_uart, S3C2410_UCON); |
1418 | ||
1419 | /* not possible to xmit on unconfigured port */ | |
1420 | if (!s3c24xx_port_configured(ucon)) | |
1421 | return; | |
93b5c032 JP |
1422 | |
1423 | while (!s3c24xx_serial_console_txrdy(port, ufcon)) | |
1424 | cpu_relax(); | |
1425 | wr_regb(cons_uart, S3C2410_UTXH, c); | |
1426 | } | |
1427 | ||
1428 | #endif /* CONFIG_CONSOLE_POLL */ | |
1429 | ||
b497549a BD |
1430 | static void |
1431 | s3c24xx_serial_console_putchar(struct uart_port *port, int ch) | |
1432 | { | |
1433 | unsigned int ufcon = rd_regl(cons_uart, S3C2410_UFCON); | |
38adbc54 MS |
1434 | unsigned int ucon = rd_regl(cons_uart, S3C2410_UCON); |
1435 | ||
1436 | /* not possible to xmit on unconfigured port */ | |
1437 | if (!s3c24xx_port_configured(ucon)) | |
1438 | return; | |
1439 | ||
b497549a BD |
1440 | while (!s3c24xx_serial_console_txrdy(port, ufcon)) |
1441 | barrier(); | |
1442 | wr_regb(cons_uart, S3C2410_UTXH, ch); | |
1443 | } | |
1444 | ||
1445 | static void | |
1446 | s3c24xx_serial_console_write(struct console *co, const char *s, | |
1447 | unsigned int count) | |
1448 | { | |
1449 | uart_console_write(cons_uart, s, count, s3c24xx_serial_console_putchar); | |
1450 | } | |
1451 | ||
1452 | static void __init | |
1453 | s3c24xx_serial_get_options(struct uart_port *port, int *baud, | |
1454 | int *parity, int *bits) | |
1455 | { | |
b497549a BD |
1456 | struct clk *clk; |
1457 | unsigned int ulcon; | |
1458 | unsigned int ucon; | |
1459 | unsigned int ubrdiv; | |
1460 | unsigned long rate; | |
5f5a7a55 TA |
1461 | unsigned int clk_sel; |
1462 | char clk_name[MAX_CLK_NAME_LENGTH]; | |
b497549a BD |
1463 | |
1464 | ulcon = rd_regl(port, S3C2410_ULCON); | |
1465 | ucon = rd_regl(port, S3C2410_UCON); | |
1466 | ubrdiv = rd_regl(port, S3C2410_UBRDIV); | |
1467 | ||
1468 | dbg("s3c24xx_serial_get_options: port=%p\n" | |
1469 | "registers: ulcon=%08x, ucon=%08x, ubdriv=%08x\n", | |
1470 | port, ulcon, ucon, ubrdiv); | |
1471 | ||
38adbc54 | 1472 | if (s3c24xx_port_configured(ucon)) { |
b497549a BD |
1473 | switch (ulcon & S3C2410_LCON_CSMASK) { |
1474 | case S3C2410_LCON_CS5: | |
1475 | *bits = 5; | |
1476 | break; | |
1477 | case S3C2410_LCON_CS6: | |
1478 | *bits = 6; | |
1479 | break; | |
1480 | case S3C2410_LCON_CS7: | |
1481 | *bits = 7; | |
1482 | break; | |
1483 | default: | |
1484 | case S3C2410_LCON_CS8: | |
1485 | *bits = 8; | |
1486 | break; | |
1487 | } | |
1488 | ||
1489 | switch (ulcon & S3C2410_LCON_PMASK) { | |
1490 | case S3C2410_LCON_PEVEN: | |
1491 | *parity = 'e'; | |
1492 | break; | |
1493 | ||
1494 | case S3C2410_LCON_PODD: | |
1495 | *parity = 'o'; | |
1496 | break; | |
1497 | ||
1498 | case S3C2410_LCON_PNONE: | |
1499 | default: | |
1500 | *parity = 'n'; | |
1501 | } | |
1502 | ||
1503 | /* now calculate the baud rate */ | |
1504 | ||
5f5a7a55 TA |
1505 | clk_sel = s3c24xx_serial_getsource(port); |
1506 | sprintf(clk_name, "clk_uart_baud%d", clk_sel); | |
b497549a | 1507 | |
5f5a7a55 | 1508 | clk = clk_get(port->dev, clk_name); |
7cd88831 | 1509 | if (!IS_ERR(clk)) |
5f5a7a55 | 1510 | rate = clk_get_rate(clk); |
b497549a BD |
1511 | else |
1512 | rate = 1; | |
1513 | ||
b497549a BD |
1514 | *baud = rate / (16 * (ubrdiv + 1)); |
1515 | dbg("calculated baud %d\n", *baud); | |
1516 | } | |
1517 | ||
1518 | } | |
1519 | ||
b497549a BD |
1520 | static int __init |
1521 | s3c24xx_serial_console_setup(struct console *co, char *options) | |
1522 | { | |
1523 | struct uart_port *port; | |
1524 | int baud = 9600; | |
1525 | int bits = 8; | |
1526 | int parity = 'n'; | |
1527 | int flow = 'n'; | |
1528 | ||
1529 | dbg("s3c24xx_serial_console_setup: co=%p (%d), %s\n", | |
1530 | co, co->index, options); | |
1531 | ||
1532 | /* is this a valid port */ | |
1533 | ||
03d5e77b | 1534 | if (co->index == -1 || co->index >= CONFIG_SERIAL_SAMSUNG_UARTS) |
b497549a BD |
1535 | co->index = 0; |
1536 | ||
1537 | port = &s3c24xx_serial_ports[co->index].port; | |
1538 | ||
1539 | /* is the port configured? */ | |
1540 | ||
ee430f16 TA |
1541 | if (port->mapbase == 0x0) |
1542 | return -ENODEV; | |
b497549a BD |
1543 | |
1544 | cons_uart = port; | |
1545 | ||
1546 | dbg("s3c24xx_serial_console_setup: port=%p (%d)\n", port, co->index); | |
1547 | ||
1548 | /* | |
1549 | * Check whether an invalid uart number has been specified, and | |
1550 | * if so, search for the first available port that does have | |
1551 | * console support. | |
1552 | */ | |
1553 | if (options) | |
1554 | uart_parse_options(options, &baud, &parity, &bits, &flow); | |
1555 | else | |
1556 | s3c24xx_serial_get_options(port, &baud, &parity, &bits); | |
1557 | ||
1558 | dbg("s3c24xx_serial_console_setup: baud %d\n", baud); | |
1559 | ||
1560 | return uart_set_options(port, co, baud, parity, bits, flow); | |
1561 | } | |
1562 | ||
b497549a BD |
1563 | static struct console s3c24xx_serial_console = { |
1564 | .name = S3C24XX_SERIAL_NAME, | |
1565 | .device = uart_console_device, | |
1566 | .flags = CON_PRINTBUFFER, | |
1567 | .index = -1, | |
1568 | .write = s3c24xx_serial_console_write, | |
5822a5df TA |
1569 | .setup = s3c24xx_serial_console_setup, |
1570 | .data = &s3c24xx_uart_drv, | |
b497549a | 1571 | }; |
da121506 TA |
1572 | #endif /* CONFIG_SERIAL_SAMSUNG_CONSOLE */ |
1573 | ||
1574 | #ifdef CONFIG_CPU_S3C2410 | |
1575 | static struct s3c24xx_serial_drv_data s3c2410_serial_drv_data = { | |
1576 | .info = &(struct s3c24xx_uart_info) { | |
1577 | .name = "Samsung S3C2410 UART", | |
1578 | .type = PORT_S3C2410, | |
1579 | .fifosize = 16, | |
1580 | .rx_fifomask = S3C2410_UFSTAT_RXMASK, | |
1581 | .rx_fifoshift = S3C2410_UFSTAT_RXSHIFT, | |
1582 | .rx_fifofull = S3C2410_UFSTAT_RXFULL, | |
1583 | .tx_fifofull = S3C2410_UFSTAT_TXFULL, | |
1584 | .tx_fifomask = S3C2410_UFSTAT_TXMASK, | |
1585 | .tx_fifoshift = S3C2410_UFSTAT_TXSHIFT, | |
1586 | .def_clk_sel = S3C2410_UCON_CLKSEL0, | |
1587 | .num_clks = 2, | |
1588 | .clksel_mask = S3C2410_UCON_CLKMASK, | |
1589 | .clksel_shift = S3C2410_UCON_CLKSHIFT, | |
1590 | }, | |
1591 | .def_cfg = &(struct s3c2410_uartcfg) { | |
1592 | .ucon = S3C2410_UCON_DEFAULT, | |
1593 | .ufcon = S3C2410_UFCON_DEFAULT, | |
1594 | }, | |
1595 | }; | |
1596 | #define S3C2410_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2410_serial_drv_data) | |
1597 | #else | |
1598 | #define S3C2410_SERIAL_DRV_DATA (kernel_ulong_t)NULL | |
1599 | #endif | |
b497549a | 1600 | |
da121506 TA |
1601 | #ifdef CONFIG_CPU_S3C2412 |
1602 | static struct s3c24xx_serial_drv_data s3c2412_serial_drv_data = { | |
1603 | .info = &(struct s3c24xx_uart_info) { | |
1604 | .name = "Samsung S3C2412 UART", | |
1605 | .type = PORT_S3C2412, | |
1606 | .fifosize = 64, | |
1607 | .has_divslot = 1, | |
1608 | .rx_fifomask = S3C2440_UFSTAT_RXMASK, | |
1609 | .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT, | |
1610 | .rx_fifofull = S3C2440_UFSTAT_RXFULL, | |
1611 | .tx_fifofull = S3C2440_UFSTAT_TXFULL, | |
1612 | .tx_fifomask = S3C2440_UFSTAT_TXMASK, | |
1613 | .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT, | |
1614 | .def_clk_sel = S3C2410_UCON_CLKSEL2, | |
1615 | .num_clks = 4, | |
1616 | .clksel_mask = S3C2412_UCON_CLKMASK, | |
1617 | .clksel_shift = S3C2412_UCON_CLKSHIFT, | |
1618 | }, | |
1619 | .def_cfg = &(struct s3c2410_uartcfg) { | |
1620 | .ucon = S3C2410_UCON_DEFAULT, | |
1621 | .ufcon = S3C2410_UFCON_DEFAULT, | |
1622 | }, | |
1623 | }; | |
1624 | #define S3C2412_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2412_serial_drv_data) | |
1625 | #else | |
1626 | #define S3C2412_SERIAL_DRV_DATA (kernel_ulong_t)NULL | |
1627 | #endif | |
b497549a | 1628 | |
da121506 | 1629 | #if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2416) || \ |
b26469a8 | 1630 | defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2442) |
da121506 TA |
1631 | static struct s3c24xx_serial_drv_data s3c2440_serial_drv_data = { |
1632 | .info = &(struct s3c24xx_uart_info) { | |
1633 | .name = "Samsung S3C2440 UART", | |
1634 | .type = PORT_S3C2440, | |
1635 | .fifosize = 64, | |
1636 | .has_divslot = 1, | |
1637 | .rx_fifomask = S3C2440_UFSTAT_RXMASK, | |
1638 | .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT, | |
1639 | .rx_fifofull = S3C2440_UFSTAT_RXFULL, | |
1640 | .tx_fifofull = S3C2440_UFSTAT_TXFULL, | |
1641 | .tx_fifomask = S3C2440_UFSTAT_TXMASK, | |
1642 | .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT, | |
1643 | .def_clk_sel = S3C2410_UCON_CLKSEL2, | |
1644 | .num_clks = 4, | |
1645 | .clksel_mask = S3C2412_UCON_CLKMASK, | |
1646 | .clksel_shift = S3C2412_UCON_CLKSHIFT, | |
1647 | }, | |
1648 | .def_cfg = &(struct s3c2410_uartcfg) { | |
1649 | .ucon = S3C2410_UCON_DEFAULT, | |
1650 | .ufcon = S3C2410_UFCON_DEFAULT, | |
1651 | }, | |
1652 | }; | |
1653 | #define S3C2440_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2440_serial_drv_data) | |
1654 | #else | |
1655 | #define S3C2440_SERIAL_DRV_DATA (kernel_ulong_t)NULL | |
1656 | #endif | |
b497549a | 1657 | |
da121506 TA |
1658 | #if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410) || \ |
1659 | defined(CONFIG_CPU_S5P6440) || defined(CONFIG_CPU_S5P6450) || \ | |
1660 | defined(CONFIG_CPU_S5PC100) | |
1661 | static struct s3c24xx_serial_drv_data s3c6400_serial_drv_data = { | |
1662 | .info = &(struct s3c24xx_uart_info) { | |
1663 | .name = "Samsung S3C6400 UART", | |
1664 | .type = PORT_S3C6400, | |
1665 | .fifosize = 64, | |
1666 | .has_divslot = 1, | |
1667 | .rx_fifomask = S3C2440_UFSTAT_RXMASK, | |
1668 | .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT, | |
1669 | .rx_fifofull = S3C2440_UFSTAT_RXFULL, | |
1670 | .tx_fifofull = S3C2440_UFSTAT_TXFULL, | |
1671 | .tx_fifomask = S3C2440_UFSTAT_TXMASK, | |
1672 | .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT, | |
1673 | .def_clk_sel = S3C2410_UCON_CLKSEL2, | |
1674 | .num_clks = 4, | |
1675 | .clksel_mask = S3C6400_UCON_CLKMASK, | |
1676 | .clksel_shift = S3C6400_UCON_CLKSHIFT, | |
1677 | }, | |
1678 | .def_cfg = &(struct s3c2410_uartcfg) { | |
1679 | .ucon = S3C2410_UCON_DEFAULT, | |
1680 | .ufcon = S3C2410_UFCON_DEFAULT, | |
1681 | }, | |
1682 | }; | |
1683 | #define S3C6400_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c6400_serial_drv_data) | |
1684 | #else | |
1685 | #define S3C6400_SERIAL_DRV_DATA (kernel_ulong_t)NULL | |
1686 | #endif | |
b497549a | 1687 | |
da121506 TA |
1688 | #ifdef CONFIG_CPU_S5PV210 |
1689 | static struct s3c24xx_serial_drv_data s5pv210_serial_drv_data = { | |
1690 | .info = &(struct s3c24xx_uart_info) { | |
1691 | .name = "Samsung S5PV210 UART", | |
1692 | .type = PORT_S3C6400, | |
1693 | .has_divslot = 1, | |
1694 | .rx_fifomask = S5PV210_UFSTAT_RXMASK, | |
1695 | .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT, | |
1696 | .rx_fifofull = S5PV210_UFSTAT_RXFULL, | |
1697 | .tx_fifofull = S5PV210_UFSTAT_TXFULL, | |
1698 | .tx_fifomask = S5PV210_UFSTAT_TXMASK, | |
1699 | .tx_fifoshift = S5PV210_UFSTAT_TXSHIFT, | |
1700 | .def_clk_sel = S3C2410_UCON_CLKSEL0, | |
1701 | .num_clks = 2, | |
1702 | .clksel_mask = S5PV210_UCON_CLKMASK, | |
1703 | .clksel_shift = S5PV210_UCON_CLKSHIFT, | |
1704 | }, | |
1705 | .def_cfg = &(struct s3c2410_uartcfg) { | |
1706 | .ucon = S5PV210_UCON_DEFAULT, | |
1707 | .ufcon = S5PV210_UFCON_DEFAULT, | |
1708 | }, | |
1709 | .fifosize = { 256, 64, 16, 16 }, | |
1710 | }; | |
1711 | #define S5PV210_SERIAL_DRV_DATA ((kernel_ulong_t)&s5pv210_serial_drv_data) | |
1712 | #else | |
1713 | #define S5PV210_SERIAL_DRV_DATA (kernel_ulong_t)NULL | |
1714 | #endif | |
b497549a | 1715 | |
33f88136 | 1716 | #if defined(CONFIG_ARCH_EXYNOS) |
da121506 TA |
1717 | static struct s3c24xx_serial_drv_data exynos4210_serial_drv_data = { |
1718 | .info = &(struct s3c24xx_uart_info) { | |
1719 | .name = "Samsung Exynos4 UART", | |
1720 | .type = PORT_S3C6400, | |
1721 | .has_divslot = 1, | |
1722 | .rx_fifomask = S5PV210_UFSTAT_RXMASK, | |
1723 | .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT, | |
1724 | .rx_fifofull = S5PV210_UFSTAT_RXFULL, | |
1725 | .tx_fifofull = S5PV210_UFSTAT_TXFULL, | |
1726 | .tx_fifomask = S5PV210_UFSTAT_TXMASK, | |
1727 | .tx_fifoshift = S5PV210_UFSTAT_TXSHIFT, | |
1728 | .def_clk_sel = S3C2410_UCON_CLKSEL0, | |
1729 | .num_clks = 1, | |
1730 | .clksel_mask = 0, | |
1731 | .clksel_shift = 0, | |
1732 | }, | |
1733 | .def_cfg = &(struct s3c2410_uartcfg) { | |
1734 | .ucon = S5PV210_UCON_DEFAULT, | |
1735 | .ufcon = S5PV210_UFCON_DEFAULT, | |
1736 | .has_fracval = 1, | |
1737 | }, | |
1738 | .fifosize = { 256, 64, 16, 16 }, | |
1739 | }; | |
1740 | #define EXYNOS4210_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos4210_serial_drv_data) | |
1741 | #else | |
1742 | #define EXYNOS4210_SERIAL_DRV_DATA (kernel_ulong_t)NULL | |
1743 | #endif | |
b497549a | 1744 | |
da121506 TA |
1745 | static struct platform_device_id s3c24xx_serial_driver_ids[] = { |
1746 | { | |
1747 | .name = "s3c2410-uart", | |
1748 | .driver_data = S3C2410_SERIAL_DRV_DATA, | |
1749 | }, { | |
1750 | .name = "s3c2412-uart", | |
1751 | .driver_data = S3C2412_SERIAL_DRV_DATA, | |
1752 | }, { | |
1753 | .name = "s3c2440-uart", | |
1754 | .driver_data = S3C2440_SERIAL_DRV_DATA, | |
1755 | }, { | |
1756 | .name = "s3c6400-uart", | |
1757 | .driver_data = S3C6400_SERIAL_DRV_DATA, | |
1758 | }, { | |
1759 | .name = "s5pv210-uart", | |
1760 | .driver_data = S5PV210_SERIAL_DRV_DATA, | |
1761 | }, { | |
1762 | .name = "exynos4210-uart", | |
1763 | .driver_data = EXYNOS4210_SERIAL_DRV_DATA, | |
1764 | }, | |
1765 | { }, | |
1766 | }; | |
1767 | MODULE_DEVICE_TABLE(platform, s3c24xx_serial_driver_ids); | |
1768 | ||
26c919e1 TA |
1769 | #ifdef CONFIG_OF |
1770 | static const struct of_device_id s3c24xx_uart_dt_match[] = { | |
666ca0b9 HS |
1771 | { .compatible = "samsung,s3c2410-uart", |
1772 | .data = (void *)S3C2410_SERIAL_DRV_DATA }, | |
1773 | { .compatible = "samsung,s3c2412-uart", | |
1774 | .data = (void *)S3C2412_SERIAL_DRV_DATA }, | |
1775 | { .compatible = "samsung,s3c2440-uart", | |
1776 | .data = (void *)S3C2440_SERIAL_DRV_DATA }, | |
1777 | { .compatible = "samsung,s3c6400-uart", | |
1778 | .data = (void *)S3C6400_SERIAL_DRV_DATA }, | |
1779 | { .compatible = "samsung,s5pv210-uart", | |
1780 | .data = (void *)S5PV210_SERIAL_DRV_DATA }, | |
26c919e1 | 1781 | { .compatible = "samsung,exynos4210-uart", |
a169a888 | 1782 | .data = (void *)EXYNOS4210_SERIAL_DRV_DATA }, |
26c919e1 TA |
1783 | {}, |
1784 | }; | |
1785 | MODULE_DEVICE_TABLE(of, s3c24xx_uart_dt_match); | |
26c919e1 TA |
1786 | #endif |
1787 | ||
da121506 TA |
1788 | static struct platform_driver samsung_serial_driver = { |
1789 | .probe = s3c24xx_serial_probe, | |
2d47b716 | 1790 | .remove = s3c24xx_serial_remove, |
da121506 TA |
1791 | .id_table = s3c24xx_serial_driver_ids, |
1792 | .driver = { | |
1793 | .name = "samsung-uart", | |
1794 | .owner = THIS_MODULE, | |
1795 | .pm = SERIAL_SAMSUNG_PM_OPS, | |
905f4ba2 | 1796 | .of_match_table = of_match_ptr(s3c24xx_uart_dt_match), |
da121506 TA |
1797 | }, |
1798 | }; | |
b497549a | 1799 | |
da121506 | 1800 | /* module initialisation code */ |
b497549a | 1801 | |
da121506 TA |
1802 | static int __init s3c24xx_serial_modinit(void) |
1803 | { | |
1804 | int ret; | |
1805 | ||
1806 | ret = uart_register_driver(&s3c24xx_uart_drv); | |
1807 | if (ret < 0) { | |
d20925e1 | 1808 | pr_err("Failed to register Samsung UART driver\n"); |
e740d8f1 | 1809 | return ret; |
da121506 TA |
1810 | } |
1811 | ||
14727598 WY |
1812 | ret = platform_driver_register(&samsung_serial_driver); |
1813 | if (ret < 0) { | |
1814 | pr_err("Failed to register platform driver\n"); | |
1815 | uart_unregister_driver(&s3c24xx_uart_drv); | |
1816 | } | |
1817 | ||
1818 | return ret; | |
b497549a BD |
1819 | } |
1820 | ||
da121506 TA |
1821 | static void __exit s3c24xx_serial_modexit(void) |
1822 | { | |
a82ea439 | 1823 | platform_driver_unregister(&samsung_serial_driver); |
da121506 TA |
1824 | uart_unregister_driver(&s3c24xx_uart_drv); |
1825 | } | |
1826 | ||
1827 | module_init(s3c24xx_serial_modinit); | |
1828 | module_exit(s3c24xx_serial_modexit); | |
b497549a | 1829 | |
da121506 | 1830 | MODULE_ALIAS("platform:samsung-uart"); |
b497549a BD |
1831 | MODULE_DESCRIPTION("Samsung SoC Serial port driver"); |
1832 | MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>"); | |
1833 | MODULE_LICENSE("GPL v2"); |