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e3b3d0f5 | 1 | // SPDX-License-Identifier: GPL-2.0 |
99edb3d1 | 2 | /* |
b497549a BD |
3 | * Driver core for Samsung SoC onboard UARTs. |
4 | * | |
ccae941e | 5 | * Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics |
b497549a | 6 | * http://armlinux.simtec.co.uk/ |
b497549a BD |
7 | */ |
8 | ||
9 | /* Hote on 2410 error handling | |
10 | * | |
11 | * The s3c2410 manual has a love/hate affair with the contents of the | |
12 | * UERSTAT register in the UART blocks, and keeps marking some of the | |
13 | * error bits as reserved. Having checked with the s3c2410x01, | |
14 | * it copes with BREAKs properly, so I am happy to ignore the RESERVED | |
15 | * feature from the latter versions of the manual. | |
16 | * | |
17 | * If it becomes aparrent that latter versions of the 2410 remove these | |
18 | * bits, then action will have to be taken to differentiate the versions | |
19 | * and change the policy on BREAK | |
20 | * | |
21 | * BJD, 04-Nov-2004 | |
22 | */ | |
23 | ||
24 | #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) | |
25 | #define SUPPORT_SYSRQ | |
26 | #endif | |
27 | ||
62c37eed RB |
28 | #include <linux/dmaengine.h> |
29 | #include <linux/dma-mapping.h> | |
30 | #include <linux/slab.h> | |
b497549a BD |
31 | #include <linux/module.h> |
32 | #include <linux/ioport.h> | |
33 | #include <linux/io.h> | |
34 | #include <linux/platform_device.h> | |
35 | #include <linux/init.h> | |
36 | #include <linux/sysrq.h> | |
37 | #include <linux/console.h> | |
38 | #include <linux/tty.h> | |
39 | #include <linux/tty_flip.h> | |
40 | #include <linux/serial_core.h> | |
41 | #include <linux/serial.h> | |
9ee51f01 | 42 | #include <linux/serial_s3c.h> |
b497549a BD |
43 | #include <linux/delay.h> |
44 | #include <linux/clk.h> | |
30555476 | 45 | #include <linux/cpufreq.h> |
26c919e1 | 46 | #include <linux/of.h> |
b497549a BD |
47 | |
48 | #include <asm/irq.h> | |
49 | ||
b497549a BD |
50 | #include "samsung.h" |
51 | ||
e4ac92df | 52 | #if defined(CONFIG_SERIAL_SAMSUNG_DEBUG) && \ |
e4ac92df JP |
53 | !defined(MODULE) |
54 | ||
55 | extern void printascii(const char *); | |
56 | ||
57 | __printf(1, 2) | |
58 | static void dbg(const char *fmt, ...) | |
59 | { | |
60 | va_list va; | |
61 | char buff[256]; | |
62 | ||
63 | va_start(va, fmt); | |
a859c8b2 | 64 | vscnprintf(buff, sizeof(buff), fmt, va); |
e4ac92df JP |
65 | va_end(va); |
66 | ||
67 | printascii(buff); | |
68 | } | |
69 | ||
70 | #else | |
71 | #define dbg(fmt, ...) do { if (0) no_printk(fmt, ##__VA_ARGS__); } while (0) | |
72 | #endif | |
73 | ||
b497549a BD |
74 | /* UART name and device definitions */ |
75 | ||
76 | #define S3C24XX_SERIAL_NAME "ttySAC" | |
77 | #define S3C24XX_SERIAL_MAJOR 204 | |
78 | #define S3C24XX_SERIAL_MINOR 64 | |
79 | ||
29bef799 RB |
80 | #define S3C24XX_TX_PIO 1 |
81 | #define S3C24XX_TX_DMA 2 | |
b543c301 RB |
82 | #define S3C24XX_RX_PIO 1 |
83 | #define S3C24XX_RX_DMA 2 | |
b497549a BD |
84 | /* macros to change one thing to another */ |
85 | ||
86 | #define tx_enabled(port) ((port)->unused[0]) | |
87 | #define rx_enabled(port) ((port)->unused[1]) | |
88 | ||
25985edc | 89 | /* flag to ignore all characters coming in */ |
b497549a BD |
90 | #define RXSTAT_DUMMY_READ (0x10000000) |
91 | ||
92 | static inline struct s3c24xx_uart_port *to_ourport(struct uart_port *port) | |
93 | { | |
94 | return container_of(port, struct s3c24xx_uart_port, port); | |
95 | } | |
96 | ||
97 | /* translate a port to the device name */ | |
98 | ||
99 | static inline const char *s3c24xx_serial_portname(struct uart_port *port) | |
100 | { | |
101 | return to_platform_device(port->dev)->name; | |
102 | } | |
103 | ||
104 | static int s3c24xx_serial_txempty_nofifo(struct uart_port *port) | |
105 | { | |
9303ac15 | 106 | return rd_regl(port, S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE; |
b497549a BD |
107 | } |
108 | ||
88bb4ea1 TA |
109 | /* |
110 | * s3c64xx and later SoC's include the interrupt mask and status registers in | |
111 | * the controller itself, unlike the s3c24xx SoC's which have these registers | |
112 | * in the interrupt controller. Check if the port type is s3c64xx or higher. | |
113 | */ | |
114 | static int s3c24xx_serial_has_interrupt_mask(struct uart_port *port) | |
115 | { | |
116 | return to_ourport(port)->info->type == PORT_S3C6400; | |
117 | } | |
118 | ||
b497549a BD |
119 | static void s3c24xx_serial_rx_enable(struct uart_port *port) |
120 | { | |
121 | unsigned long flags; | |
122 | unsigned int ucon, ufcon; | |
123 | int count = 10000; | |
124 | ||
125 | spin_lock_irqsave(&port->lock, flags); | |
126 | ||
127 | while (--count && !s3c24xx_serial_txempty_nofifo(port)) | |
128 | udelay(100); | |
129 | ||
130 | ufcon = rd_regl(port, S3C2410_UFCON); | |
131 | ufcon |= S3C2410_UFCON_RESETRX; | |
132 | wr_regl(port, S3C2410_UFCON, ufcon); | |
133 | ||
134 | ucon = rd_regl(port, S3C2410_UCON); | |
135 | ucon |= S3C2410_UCON_RXIRQMODE; | |
136 | wr_regl(port, S3C2410_UCON, ucon); | |
137 | ||
138 | rx_enabled(port) = 1; | |
139 | spin_unlock_irqrestore(&port->lock, flags); | |
140 | } | |
141 | ||
142 | static void s3c24xx_serial_rx_disable(struct uart_port *port) | |
143 | { | |
144 | unsigned long flags; | |
145 | unsigned int ucon; | |
146 | ||
147 | spin_lock_irqsave(&port->lock, flags); | |
148 | ||
149 | ucon = rd_regl(port, S3C2410_UCON); | |
150 | ucon &= ~S3C2410_UCON_RXIRQMODE; | |
151 | wr_regl(port, S3C2410_UCON, ucon); | |
152 | ||
153 | rx_enabled(port) = 0; | |
154 | spin_unlock_irqrestore(&port->lock, flags); | |
155 | } | |
156 | ||
157 | static void s3c24xx_serial_stop_tx(struct uart_port *port) | |
158 | { | |
b73c289c | 159 | struct s3c24xx_uart_port *ourport = to_ourport(port); |
29bef799 RB |
160 | struct s3c24xx_uart_dma *dma = ourport->dma; |
161 | struct circ_buf *xmit = &port->state->xmit; | |
162 | struct dma_tx_state state; | |
163 | int count; | |
b73c289c | 164 | |
29bef799 RB |
165 | if (!tx_enabled(port)) |
166 | return; | |
167 | ||
168 | if (s3c24xx_serial_has_interrupt_mask(port)) | |
bbb5ff91 | 169 | s3c24xx_set_bit(port, S3C64XX_UINTM_TXD, S3C64XX_UINTM); |
29bef799 RB |
170 | else |
171 | disable_irq_nosync(ourport->tx_irq); | |
172 | ||
173 | if (dma && dma->tx_chan && ourport->tx_in_progress == S3C24XX_TX_DMA) { | |
174 | dmaengine_pause(dma->tx_chan); | |
175 | dmaengine_tx_status(dma->tx_chan, dma->tx_cookie, &state); | |
176 | dmaengine_terminate_all(dma->tx_chan); | |
177 | dma_sync_single_for_cpu(ourport->port.dev, | |
178 | dma->tx_transfer_addr, dma->tx_size, DMA_TO_DEVICE); | |
179 | async_tx_ack(dma->tx_desc); | |
180 | count = dma->tx_bytes_requested - state.residue; | |
181 | xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1); | |
182 | port->icount.tx += count; | |
b497549a | 183 | } |
29bef799 RB |
184 | |
185 | tx_enabled(port) = 0; | |
186 | ourport->tx_in_progress = 0; | |
187 | ||
188 | if (port->flags & UPF_CONS_FLOW) | |
189 | s3c24xx_serial_rx_enable(port); | |
190 | ||
191 | ourport->tx_mode = 0; | |
192 | } | |
193 | ||
194 | static void s3c24xx_serial_start_next_tx(struct s3c24xx_uart_port *ourport); | |
195 | ||
196 | static void s3c24xx_serial_tx_dma_complete(void *args) | |
197 | { | |
198 | struct s3c24xx_uart_port *ourport = args; | |
199 | struct uart_port *port = &ourport->port; | |
200 | struct circ_buf *xmit = &port->state->xmit; | |
201 | struct s3c24xx_uart_dma *dma = ourport->dma; | |
202 | struct dma_tx_state state; | |
203 | unsigned long flags; | |
204 | int count; | |
205 | ||
206 | ||
207 | dmaengine_tx_status(dma->tx_chan, dma->tx_cookie, &state); | |
208 | count = dma->tx_bytes_requested - state.residue; | |
209 | async_tx_ack(dma->tx_desc); | |
210 | ||
211 | dma_sync_single_for_cpu(ourport->port.dev, dma->tx_transfer_addr, | |
212 | dma->tx_size, DMA_TO_DEVICE); | |
213 | ||
214 | spin_lock_irqsave(&port->lock, flags); | |
215 | ||
216 | xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1); | |
217 | port->icount.tx += count; | |
218 | ourport->tx_in_progress = 0; | |
219 | ||
220 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
221 | uart_write_wakeup(port); | |
222 | ||
223 | s3c24xx_serial_start_next_tx(ourport); | |
224 | spin_unlock_irqrestore(&port->lock, flags); | |
225 | } | |
226 | ||
227 | static void enable_tx_dma(struct s3c24xx_uart_port *ourport) | |
228 | { | |
229 | struct uart_port *port = &ourport->port; | |
230 | u32 ucon; | |
231 | ||
232 | /* Mask Tx interrupt */ | |
233 | if (s3c24xx_serial_has_interrupt_mask(port)) | |
bbb5ff91 | 234 | s3c24xx_set_bit(port, S3C64XX_UINTM_TXD, S3C64XX_UINTM); |
29bef799 RB |
235 | else |
236 | disable_irq_nosync(ourport->tx_irq); | |
237 | ||
238 | /* Enable tx dma mode */ | |
239 | ucon = rd_regl(port, S3C2410_UCON); | |
240 | ucon &= ~(S3C64XX_UCON_TXBURST_MASK | S3C64XX_UCON_TXMODE_MASK); | |
241 | ucon |= (dma_get_cache_alignment() >= 16) ? | |
242 | S3C64XX_UCON_TXBURST_16 : S3C64XX_UCON_TXBURST_1; | |
243 | ucon |= S3C64XX_UCON_TXMODE_DMA; | |
244 | wr_regl(port, S3C2410_UCON, ucon); | |
245 | ||
246 | ourport->tx_mode = S3C24XX_TX_DMA; | |
247 | } | |
248 | ||
249 | static void enable_tx_pio(struct s3c24xx_uart_port *ourport) | |
250 | { | |
251 | struct uart_port *port = &ourport->port; | |
252 | u32 ucon, ufcon; | |
253 | ||
254 | /* Set ufcon txtrig */ | |
255 | ourport->tx_in_progress = S3C24XX_TX_PIO; | |
256 | ufcon = rd_regl(port, S3C2410_UFCON); | |
257 | wr_regl(port, S3C2410_UFCON, ufcon); | |
258 | ||
259 | /* Enable tx pio mode */ | |
260 | ucon = rd_regl(port, S3C2410_UCON); | |
261 | ucon &= ~(S3C64XX_UCON_TXMODE_MASK); | |
262 | ucon |= S3C64XX_UCON_TXMODE_CPU; | |
263 | wr_regl(port, S3C2410_UCON, ucon); | |
264 | ||
265 | /* Unmask Tx interrupt */ | |
266 | if (s3c24xx_serial_has_interrupt_mask(port)) | |
bbb5ff91 ML |
267 | s3c24xx_clear_bit(port, S3C64XX_UINTM_TXD, |
268 | S3C64XX_UINTM); | |
29bef799 RB |
269 | else |
270 | enable_irq(ourport->tx_irq); | |
271 | ||
272 | ourport->tx_mode = S3C24XX_TX_PIO; | |
273 | } | |
274 | ||
275 | static void s3c24xx_serial_start_tx_pio(struct s3c24xx_uart_port *ourport) | |
276 | { | |
277 | if (ourport->tx_mode != S3C24XX_TX_PIO) | |
278 | enable_tx_pio(ourport); | |
b497549a BD |
279 | } |
280 | ||
29bef799 RB |
281 | static int s3c24xx_serial_start_tx_dma(struct s3c24xx_uart_port *ourport, |
282 | unsigned int count) | |
283 | { | |
284 | struct uart_port *port = &ourport->port; | |
285 | struct circ_buf *xmit = &port->state->xmit; | |
286 | struct s3c24xx_uart_dma *dma = ourport->dma; | |
287 | ||
288 | ||
289 | if (ourport->tx_mode != S3C24XX_TX_DMA) | |
290 | enable_tx_dma(ourport); | |
291 | ||
29bef799 RB |
292 | dma->tx_size = count & ~(dma_get_cache_alignment() - 1); |
293 | dma->tx_transfer_addr = dma->tx_addr + xmit->tail; | |
294 | ||
295 | dma_sync_single_for_device(ourport->port.dev, dma->tx_transfer_addr, | |
296 | dma->tx_size, DMA_TO_DEVICE); | |
297 | ||
298 | dma->tx_desc = dmaengine_prep_slave_single(dma->tx_chan, | |
299 | dma->tx_transfer_addr, dma->tx_size, | |
300 | DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT); | |
301 | if (!dma->tx_desc) { | |
302 | dev_err(ourport->port.dev, "Unable to get desc for Tx\n"); | |
303 | return -EIO; | |
304 | } | |
305 | ||
306 | dma->tx_desc->callback = s3c24xx_serial_tx_dma_complete; | |
307 | dma->tx_desc->callback_param = ourport; | |
308 | dma->tx_bytes_requested = dma->tx_size; | |
309 | ||
310 | ourport->tx_in_progress = S3C24XX_TX_DMA; | |
311 | dma->tx_cookie = dmaengine_submit(dma->tx_desc); | |
312 | dma_async_issue_pending(dma->tx_chan); | |
313 | return 0; | |
314 | } | |
315 | ||
316 | static void s3c24xx_serial_start_next_tx(struct s3c24xx_uart_port *ourport) | |
317 | { | |
318 | struct uart_port *port = &ourport->port; | |
319 | struct circ_buf *xmit = &port->state->xmit; | |
320 | unsigned long count; | |
321 | ||
322 | /* Get data size up to the end of buffer */ | |
323 | count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE); | |
324 | ||
325 | if (!count) { | |
326 | s3c24xx_serial_stop_tx(port); | |
327 | return; | |
328 | } | |
329 | ||
81ccb2a6 | 330 | if (!ourport->dma || !ourport->dma->tx_chan || |
736cd79f RB |
331 | count < ourport->min_dma_size || |
332 | xmit->tail & (dma_get_cache_alignment() - 1)) | |
29bef799 RB |
333 | s3c24xx_serial_start_tx_pio(ourport); |
334 | else | |
335 | s3c24xx_serial_start_tx_dma(ourport, count); | |
336 | } | |
337 | ||
75781979 | 338 | static void s3c24xx_serial_start_tx(struct uart_port *port) |
b497549a | 339 | { |
b73c289c | 340 | struct s3c24xx_uart_port *ourport = to_ourport(port); |
29bef799 | 341 | struct circ_buf *xmit = &port->state->xmit; |
b73c289c | 342 | |
b497549a BD |
343 | if (!tx_enabled(port)) { |
344 | if (port->flags & UPF_CONS_FLOW) | |
345 | s3c24xx_serial_rx_disable(port); | |
346 | ||
b497549a | 347 | tx_enabled(port) = 1; |
ba019a3e | 348 | if (!ourport->dma || !ourport->dma->tx_chan) |
29bef799 | 349 | s3c24xx_serial_start_tx_pio(ourport); |
29bef799 RB |
350 | } |
351 | ||
352 | if (ourport->dma && ourport->dma->tx_chan) { | |
353 | if (!uart_circ_empty(xmit) && !ourport->tx_in_progress) | |
354 | s3c24xx_serial_start_next_tx(ourport); | |
b497549a BD |
355 | } |
356 | } | |
357 | ||
b543c301 RB |
358 | static void s3c24xx_uart_copy_rx_to_tty(struct s3c24xx_uart_port *ourport, |
359 | struct tty_port *tty, int count) | |
360 | { | |
361 | struct s3c24xx_uart_dma *dma = ourport->dma; | |
362 | int copied; | |
363 | ||
364 | if (!count) | |
365 | return; | |
366 | ||
367 | dma_sync_single_for_cpu(ourport->port.dev, dma->rx_addr, | |
368 | dma->rx_size, DMA_FROM_DEVICE); | |
369 | ||
370 | ourport->port.icount.rx += count; | |
371 | if (!tty) { | |
372 | dev_err(ourport->port.dev, "No tty port\n"); | |
373 | return; | |
374 | } | |
375 | copied = tty_insert_flip_string(tty, | |
376 | ((unsigned char *)(ourport->dma->rx_buf)), count); | |
377 | if (copied != count) { | |
378 | WARN_ON(1); | |
379 | dev_err(ourport->port.dev, "RxData copy to tty layer failed\n"); | |
380 | } | |
381 | } | |
382 | ||
b497549a BD |
383 | static void s3c24xx_serial_stop_rx(struct uart_port *port) |
384 | { | |
b73c289c | 385 | struct s3c24xx_uart_port *ourport = to_ourport(port); |
b543c301 RB |
386 | struct s3c24xx_uart_dma *dma = ourport->dma; |
387 | struct tty_port *t = &port->state->port; | |
388 | struct dma_tx_state state; | |
389 | enum dma_status dma_status; | |
390 | unsigned int received; | |
b73c289c | 391 | |
b497549a BD |
392 | if (rx_enabled(port)) { |
393 | dbg("s3c24xx_serial_stop_rx: port=%p\n", port); | |
88bb4ea1 | 394 | if (s3c24xx_serial_has_interrupt_mask(port)) |
bbb5ff91 ML |
395 | s3c24xx_set_bit(port, S3C64XX_UINTM_RXD, |
396 | S3C64XX_UINTM); | |
88bb4ea1 TA |
397 | else |
398 | disable_irq_nosync(ourport->rx_irq); | |
b497549a BD |
399 | rx_enabled(port) = 0; |
400 | } | |
b543c301 RB |
401 | if (dma && dma->rx_chan) { |
402 | dmaengine_pause(dma->tx_chan); | |
403 | dma_status = dmaengine_tx_status(dma->rx_chan, | |
404 | dma->rx_cookie, &state); | |
405 | if (dma_status == DMA_IN_PROGRESS || | |
406 | dma_status == DMA_PAUSED) { | |
407 | received = dma->rx_bytes_requested - state.residue; | |
408 | dmaengine_terminate_all(dma->rx_chan); | |
409 | s3c24xx_uart_copy_rx_to_tty(ourport, t, received); | |
410 | } | |
411 | } | |
b497549a BD |
412 | } |
413 | ||
ef4aca70 RB |
414 | static inline struct s3c24xx_uart_info |
415 | *s3c24xx_port_to_info(struct uart_port *port) | |
b497549a BD |
416 | { |
417 | return to_ourport(port)->info; | |
418 | } | |
419 | ||
ef4aca70 RB |
420 | static inline struct s3c2410_uartcfg |
421 | *s3c24xx_port_to_cfg(struct uart_port *port) | |
b497549a | 422 | { |
4d84e970 TA |
423 | struct s3c24xx_uart_port *ourport; |
424 | ||
b497549a BD |
425 | if (port->dev == NULL) |
426 | return NULL; | |
427 | ||
4d84e970 TA |
428 | ourport = container_of(port, struct s3c24xx_uart_port, port); |
429 | return ourport->cfg; | |
b497549a BD |
430 | } |
431 | ||
432 | static int s3c24xx_serial_rx_fifocnt(struct s3c24xx_uart_port *ourport, | |
433 | unsigned long ufstat) | |
434 | { | |
435 | struct s3c24xx_uart_info *info = ourport->info; | |
436 | ||
437 | if (ufstat & info->rx_fifofull) | |
da121506 | 438 | return ourport->port.fifosize; |
b497549a BD |
439 | |
440 | return (ufstat & info->rx_fifomask) >> info->rx_fifoshift; | |
441 | } | |
442 | ||
b543c301 RB |
443 | static void s3c64xx_start_rx_dma(struct s3c24xx_uart_port *ourport); |
444 | static void s3c24xx_serial_rx_dma_complete(void *args) | |
445 | { | |
446 | struct s3c24xx_uart_port *ourport = args; | |
447 | struct uart_port *port = &ourport->port; | |
448 | ||
449 | struct s3c24xx_uart_dma *dma = ourport->dma; | |
450 | struct tty_port *t = &port->state->port; | |
451 | struct tty_struct *tty = tty_port_tty_get(&ourport->port.state->port); | |
452 | ||
453 | struct dma_tx_state state; | |
454 | unsigned long flags; | |
455 | int received; | |
456 | ||
457 | dmaengine_tx_status(dma->rx_chan, dma->rx_cookie, &state); | |
458 | received = dma->rx_bytes_requested - state.residue; | |
459 | async_tx_ack(dma->rx_desc); | |
460 | ||
461 | spin_lock_irqsave(&port->lock, flags); | |
462 | ||
463 | if (received) | |
464 | s3c24xx_uart_copy_rx_to_tty(ourport, t, received); | |
465 | ||
466 | if (tty) { | |
467 | tty_flip_buffer_push(t); | |
468 | tty_kref_put(tty); | |
469 | } | |
470 | ||
471 | s3c64xx_start_rx_dma(ourport); | |
472 | ||
473 | spin_unlock_irqrestore(&port->lock, flags); | |
474 | } | |
475 | ||
476 | static void s3c64xx_start_rx_dma(struct s3c24xx_uart_port *ourport) | |
477 | { | |
478 | struct s3c24xx_uart_dma *dma = ourport->dma; | |
479 | ||
480 | dma_sync_single_for_device(ourport->port.dev, dma->rx_addr, | |
481 | dma->rx_size, DMA_FROM_DEVICE); | |
482 | ||
483 | dma->rx_desc = dmaengine_prep_slave_single(dma->rx_chan, | |
484 | dma->rx_addr, dma->rx_size, DMA_DEV_TO_MEM, | |
485 | DMA_PREP_INTERRUPT); | |
486 | if (!dma->rx_desc) { | |
487 | dev_err(ourport->port.dev, "Unable to get desc for Rx\n"); | |
488 | return; | |
489 | } | |
490 | ||
491 | dma->rx_desc->callback = s3c24xx_serial_rx_dma_complete; | |
492 | dma->rx_desc->callback_param = ourport; | |
493 | dma->rx_bytes_requested = dma->rx_size; | |
494 | ||
495 | dma->rx_cookie = dmaengine_submit(dma->rx_desc); | |
496 | dma_async_issue_pending(dma->rx_chan); | |
497 | } | |
b497549a BD |
498 | |
499 | /* ? - where has parity gone?? */ | |
500 | #define S3C2410_UERSTAT_PARITY (0x1000) | |
501 | ||
b543c301 RB |
502 | static void enable_rx_dma(struct s3c24xx_uart_port *ourport) |
503 | { | |
504 | struct uart_port *port = &ourport->port; | |
505 | unsigned int ucon; | |
506 | ||
507 | /* set Rx mode to DMA mode */ | |
508 | ucon = rd_regl(port, S3C2410_UCON); | |
509 | ucon &= ~(S3C64XX_UCON_RXBURST_MASK | | |
510 | S3C64XX_UCON_TIMEOUT_MASK | | |
511 | S3C64XX_UCON_EMPTYINT_EN | | |
512 | S3C64XX_UCON_DMASUS_EN | | |
513 | S3C64XX_UCON_TIMEOUT_EN | | |
514 | S3C64XX_UCON_RXMODE_MASK); | |
515 | ucon |= S3C64XX_UCON_RXBURST_16 | | |
516 | 0xf << S3C64XX_UCON_TIMEOUT_SHIFT | | |
517 | S3C64XX_UCON_EMPTYINT_EN | | |
518 | S3C64XX_UCON_TIMEOUT_EN | | |
519 | S3C64XX_UCON_RXMODE_DMA; | |
520 | wr_regl(port, S3C2410_UCON, ucon); | |
521 | ||
522 | ourport->rx_mode = S3C24XX_RX_DMA; | |
523 | } | |
524 | ||
525 | static void enable_rx_pio(struct s3c24xx_uart_port *ourport) | |
526 | { | |
527 | struct uart_port *port = &ourport->port; | |
528 | unsigned int ucon; | |
529 | ||
530 | /* set Rx mode to DMA mode */ | |
531 | ucon = rd_regl(port, S3C2410_UCON); | |
532 | ucon &= ~(S3C64XX_UCON_TIMEOUT_MASK | | |
533 | S3C64XX_UCON_EMPTYINT_EN | | |
534 | S3C64XX_UCON_DMASUS_EN | | |
535 | S3C64XX_UCON_TIMEOUT_EN | | |
536 | S3C64XX_UCON_RXMODE_MASK); | |
537 | ucon |= 0xf << S3C64XX_UCON_TIMEOUT_SHIFT | | |
538 | S3C64XX_UCON_TIMEOUT_EN | | |
539 | S3C64XX_UCON_RXMODE_CPU; | |
540 | wr_regl(port, S3C2410_UCON, ucon); | |
541 | ||
542 | ourport->rx_mode = S3C24XX_RX_PIO; | |
543 | } | |
544 | ||
09557c01 RB |
545 | static void s3c24xx_serial_rx_drain_fifo(struct s3c24xx_uart_port *ourport); |
546 | ||
e4678afe | 547 | static irqreturn_t s3c24xx_serial_rx_chars_dma(void *dev_id) |
b543c301 RB |
548 | { |
549 | unsigned int utrstat, ufstat, received; | |
550 | struct s3c24xx_uart_port *ourport = dev_id; | |
551 | struct uart_port *port = &ourport->port; | |
552 | struct s3c24xx_uart_dma *dma = ourport->dma; | |
553 | struct tty_struct *tty = tty_port_tty_get(&ourport->port.state->port); | |
554 | struct tty_port *t = &port->state->port; | |
555 | unsigned long flags; | |
556 | struct dma_tx_state state; | |
557 | ||
558 | utrstat = rd_regl(port, S3C2410_UTRSTAT); | |
559 | ufstat = rd_regl(port, S3C2410_UFSTAT); | |
560 | ||
561 | spin_lock_irqsave(&port->lock, flags); | |
562 | ||
563 | if (!(utrstat & S3C2410_UTRSTAT_TIMEOUT)) { | |
564 | s3c64xx_start_rx_dma(ourport); | |
565 | if (ourport->rx_mode == S3C24XX_RX_PIO) | |
566 | enable_rx_dma(ourport); | |
567 | goto finish; | |
568 | } | |
569 | ||
570 | if (ourport->rx_mode == S3C24XX_RX_DMA) { | |
571 | dmaengine_pause(dma->rx_chan); | |
572 | dmaengine_tx_status(dma->rx_chan, dma->rx_cookie, &state); | |
573 | dmaengine_terminate_all(dma->rx_chan); | |
574 | received = dma->rx_bytes_requested - state.residue; | |
575 | s3c24xx_uart_copy_rx_to_tty(ourport, t, received); | |
576 | ||
577 | enable_rx_pio(ourport); | |
578 | } | |
579 | ||
09557c01 | 580 | s3c24xx_serial_rx_drain_fifo(ourport); |
b543c301 RB |
581 | |
582 | if (tty) { | |
583 | tty_flip_buffer_push(t); | |
584 | tty_kref_put(tty); | |
585 | } | |
586 | ||
587 | wr_regl(port, S3C2410_UTRSTAT, S3C2410_UTRSTAT_TIMEOUT); | |
588 | ||
589 | finish: | |
590 | spin_unlock_irqrestore(&port->lock, flags); | |
591 | ||
592 | return IRQ_HANDLED; | |
593 | } | |
594 | ||
01732dd2 | 595 | static void s3c24xx_serial_rx_drain_fifo(struct s3c24xx_uart_port *ourport) |
b497549a | 596 | { |
b497549a | 597 | struct uart_port *port = &ourport->port; |
b497549a | 598 | unsigned int ufcon, ch, flag, ufstat, uerstat; |
aba06e92 | 599 | unsigned int fifocnt = 0; |
57850a50 | 600 | int max_count = port->fifosize; |
b497549a BD |
601 | |
602 | while (max_count-- > 0) { | |
aba06e92 YN |
603 | /* |
604 | * Receive all characters known to be in FIFO | |
605 | * before reading FIFO level again | |
606 | */ | |
607 | if (fifocnt == 0) { | |
608 | ufstat = rd_regl(port, S3C2410_UFSTAT); | |
609 | fifocnt = s3c24xx_serial_rx_fifocnt(ourport, ufstat); | |
610 | if (fifocnt == 0) | |
611 | break; | |
612 | } | |
613 | fifocnt--; | |
b497549a BD |
614 | |
615 | uerstat = rd_regl(port, S3C2410_UERSTAT); | |
616 | ch = rd_regb(port, S3C2410_URXH); | |
617 | ||
618 | if (port->flags & UPF_CONS_FLOW) { | |
619 | int txe = s3c24xx_serial_txempty_nofifo(port); | |
620 | ||
621 | if (rx_enabled(port)) { | |
622 | if (!txe) { | |
623 | rx_enabled(port) = 0; | |
624 | continue; | |
625 | } | |
626 | } else { | |
627 | if (txe) { | |
aba06e92 | 628 | ufcon = rd_regl(port, S3C2410_UFCON); |
b497549a BD |
629 | ufcon |= S3C2410_UFCON_RESETRX; |
630 | wr_regl(port, S3C2410_UFCON, ufcon); | |
631 | rx_enabled(port) = 1; | |
01732dd2 | 632 | return; |
b497549a BD |
633 | } |
634 | continue; | |
635 | } | |
636 | } | |
637 | ||
638 | /* insert the character into the buffer */ | |
639 | ||
640 | flag = TTY_NORMAL; | |
641 | port->icount.rx++; | |
642 | ||
643 | if (unlikely(uerstat & S3C2410_UERSTAT_ANY)) { | |
644 | dbg("rxerr: port ch=0x%02x, rxs=0x%08x\n", | |
645 | ch, uerstat); | |
646 | ||
647 | /* check for break */ | |
648 | if (uerstat & S3C2410_UERSTAT_BREAK) { | |
649 | dbg("break!\n"); | |
650 | port->icount.brk++; | |
651 | if (uart_handle_break(port)) | |
620bb214 | 652 | continue; /* Ignore character */ |
b497549a BD |
653 | } |
654 | ||
655 | if (uerstat & S3C2410_UERSTAT_FRAME) | |
656 | port->icount.frame++; | |
657 | if (uerstat & S3C2410_UERSTAT_OVERRUN) | |
658 | port->icount.overrun++; | |
659 | ||
660 | uerstat &= port->read_status_mask; | |
661 | ||
662 | if (uerstat & S3C2410_UERSTAT_BREAK) | |
663 | flag = TTY_BREAK; | |
664 | else if (uerstat & S3C2410_UERSTAT_PARITY) | |
665 | flag = TTY_PARITY; | |
666 | else if (uerstat & (S3C2410_UERSTAT_FRAME | | |
667 | S3C2410_UERSTAT_OVERRUN)) | |
668 | flag = TTY_FRAME; | |
669 | } | |
670 | ||
671 | if (uart_handle_sysrq_char(port, ch)) | |
620bb214 | 672 | continue; /* Ignore character */ |
b497549a BD |
673 | |
674 | uart_insert_char(port, uerstat, S3C2410_UERSTAT_OVERRUN, | |
675 | ch, flag); | |
b497549a | 676 | } |
f5693ea2 | 677 | |
2e124b4a | 678 | tty_flip_buffer_push(&port->state->port); |
01732dd2 RB |
679 | } |
680 | ||
681 | static irqreturn_t s3c24xx_serial_rx_chars_pio(void *dev_id) | |
682 | { | |
683 | struct s3c24xx_uart_port *ourport = dev_id; | |
684 | struct uart_port *port = &ourport->port; | |
685 | unsigned long flags; | |
686 | ||
687 | spin_lock_irqsave(&port->lock, flags); | |
688 | s3c24xx_serial_rx_drain_fifo(ourport); | |
689 | spin_unlock_irqrestore(&port->lock, flags); | |
b497549a | 690 | |
b497549a BD |
691 | return IRQ_HANDLED; |
692 | } | |
693 | ||
b543c301 RB |
694 | |
695 | static irqreturn_t s3c24xx_serial_rx_chars(int irq, void *dev_id) | |
696 | { | |
697 | struct s3c24xx_uart_port *ourport = dev_id; | |
698 | ||
699 | if (ourport->dma && ourport->dma->rx_chan) | |
e4678afe RB |
700 | return s3c24xx_serial_rx_chars_dma(dev_id); |
701 | return s3c24xx_serial_rx_chars_pio(dev_id); | |
b543c301 RB |
702 | } |
703 | ||
b497549a BD |
704 | static irqreturn_t s3c24xx_serial_tx_chars(int irq, void *id) |
705 | { | |
706 | struct s3c24xx_uart_port *ourport = id; | |
707 | struct uart_port *port = &ourport->port; | |
ebd2c8f6 | 708 | struct circ_buf *xmit = &port->state->xmit; |
c15c3747 | 709 | unsigned long flags; |
736cd79f | 710 | int count, dma_count = 0; |
b497549a | 711 | |
c15c3747 TA |
712 | spin_lock_irqsave(&port->lock, flags); |
713 | ||
29bef799 RB |
714 | count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE); |
715 | ||
81ccb2a6 MS |
716 | if (ourport->dma && ourport->dma->tx_chan && |
717 | count >= ourport->min_dma_size) { | |
736cd79f RB |
718 | int align = dma_get_cache_alignment() - |
719 | (xmit->tail & (dma_get_cache_alignment() - 1)); | |
720 | if (count-align >= ourport->min_dma_size) { | |
721 | dma_count = count-align; | |
722 | count = align; | |
723 | } | |
29bef799 RB |
724 | } |
725 | ||
b497549a BD |
726 | if (port->x_char) { |
727 | wr_regb(port, S3C2410_UTXH, port->x_char); | |
728 | port->icount.tx++; | |
729 | port->x_char = 0; | |
730 | goto out; | |
731 | } | |
732 | ||
25985edc | 733 | /* if there isn't anything more to transmit, or the uart is now |
b497549a BD |
734 | * stopped, disable the uart and exit |
735 | */ | |
736 | ||
737 | if (uart_circ_empty(xmit) || uart_tx_stopped(port)) { | |
738 | s3c24xx_serial_stop_tx(port); | |
739 | goto out; | |
740 | } | |
741 | ||
742 | /* try and drain the buffer... */ | |
743 | ||
736cd79f RB |
744 | if (count > port->fifosize) { |
745 | count = port->fifosize; | |
746 | dma_count = 0; | |
747 | } | |
748 | ||
749 | while (!uart_circ_empty(xmit) && count > 0) { | |
b497549a BD |
750 | if (rd_regl(port, S3C2410_UFSTAT) & ourport->info->tx_fifofull) |
751 | break; | |
752 | ||
753 | wr_regb(port, S3C2410_UTXH, xmit->buf[xmit->tail]); | |
754 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); | |
755 | port->icount.tx++; | |
736cd79f RB |
756 | count--; |
757 | } | |
758 | ||
759 | if (!count && dma_count) { | |
760 | s3c24xx_serial_start_tx_dma(ourport, dma_count); | |
761 | goto out; | |
b497549a BD |
762 | } |
763 | ||
c15c3747 TA |
764 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) { |
765 | spin_unlock(&port->lock); | |
b497549a | 766 | uart_write_wakeup(port); |
c15c3747 TA |
767 | spin_lock(&port->lock); |
768 | } | |
b497549a BD |
769 | |
770 | if (uart_circ_empty(xmit)) | |
771 | s3c24xx_serial_stop_tx(port); | |
772 | ||
ef4aca70 | 773 | out: |
c15c3747 | 774 | spin_unlock_irqrestore(&port->lock, flags); |
b497549a BD |
775 | return IRQ_HANDLED; |
776 | } | |
777 | ||
88bb4ea1 TA |
778 | /* interrupt handler for s3c64xx and later SoC's.*/ |
779 | static irqreturn_t s3c64xx_serial_handle_irq(int irq, void *id) | |
780 | { | |
781 | struct s3c24xx_uart_port *ourport = id; | |
782 | struct uart_port *port = &ourport->port; | |
783 | unsigned int pend = rd_regl(port, S3C64XX_UINTP); | |
88bb4ea1 TA |
784 | irqreturn_t ret = IRQ_HANDLED; |
785 | ||
88bb4ea1 TA |
786 | if (pend & S3C64XX_UINTM_RXD_MSK) { |
787 | ret = s3c24xx_serial_rx_chars(irq, id); | |
788 | wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_RXD_MSK); | |
789 | } | |
790 | if (pend & S3C64XX_UINTM_TXD_MSK) { | |
791 | ret = s3c24xx_serial_tx_chars(irq, id); | |
792 | wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_TXD_MSK); | |
793 | } | |
88bb4ea1 TA |
794 | return ret; |
795 | } | |
796 | ||
b497549a BD |
797 | static unsigned int s3c24xx_serial_tx_empty(struct uart_port *port) |
798 | { | |
799 | struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port); | |
800 | unsigned long ufstat = rd_regl(port, S3C2410_UFSTAT); | |
801 | unsigned long ufcon = rd_regl(port, S3C2410_UFCON); | |
802 | ||
803 | if (ufcon & S3C2410_UFCON_FIFOMODE) { | |
804 | if ((ufstat & info->tx_fifomask) != 0 || | |
805 | (ufstat & info->tx_fifofull)) | |
806 | return 0; | |
807 | ||
808 | return 1; | |
809 | } | |
810 | ||
811 | return s3c24xx_serial_txempty_nofifo(port); | |
812 | } | |
813 | ||
814 | /* no modem control lines */ | |
815 | static unsigned int s3c24xx_serial_get_mctrl(struct uart_port *port) | |
816 | { | |
817 | unsigned int umstat = rd_regb(port, S3C2410_UMSTAT); | |
818 | ||
819 | if (umstat & S3C2410_UMSTAT_CTS) | |
820 | return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS; | |
821 | else | |
822 | return TIOCM_CAR | TIOCM_DSR; | |
823 | } | |
824 | ||
825 | static void s3c24xx_serial_set_mctrl(struct uart_port *port, unsigned int mctrl) | |
826 | { | |
2d1e5a48 JMG |
827 | unsigned int umcon = rd_regl(port, S3C2410_UMCON); |
828 | ||
829 | if (mctrl & TIOCM_RTS) | |
830 | umcon |= S3C2410_UMCOM_RTS_LOW; | |
831 | else | |
832 | umcon &= ~S3C2410_UMCOM_RTS_LOW; | |
833 | ||
834 | wr_regl(port, S3C2410_UMCON, umcon); | |
b497549a BD |
835 | } |
836 | ||
837 | static void s3c24xx_serial_break_ctl(struct uart_port *port, int break_state) | |
838 | { | |
839 | unsigned long flags; | |
840 | unsigned int ucon; | |
841 | ||
842 | spin_lock_irqsave(&port->lock, flags); | |
843 | ||
844 | ucon = rd_regl(port, S3C2410_UCON); | |
845 | ||
846 | if (break_state) | |
847 | ucon |= S3C2410_UCON_SBREAK; | |
848 | else | |
849 | ucon &= ~S3C2410_UCON_SBREAK; | |
850 | ||
851 | wr_regl(port, S3C2410_UCON, ucon); | |
852 | ||
853 | spin_unlock_irqrestore(&port->lock, flags); | |
854 | } | |
855 | ||
62c37eed RB |
856 | static int s3c24xx_serial_request_dma(struct s3c24xx_uart_port *p) |
857 | { | |
858 | struct s3c24xx_uart_dma *dma = p->dma; | |
d8db840d MS |
859 | struct dma_slave_caps dma_caps; |
860 | const char *reason = NULL; | |
500fcc08 | 861 | int ret; |
62c37eed RB |
862 | |
863 | /* Default slave configuration parameters */ | |
864 | dma->rx_conf.direction = DMA_DEV_TO_MEM; | |
865 | dma->rx_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; | |
866 | dma->rx_conf.src_addr = p->port.mapbase + S3C2410_URXH; | |
aa2f80e7 | 867 | dma->rx_conf.src_maxburst = 1; |
62c37eed RB |
868 | |
869 | dma->tx_conf.direction = DMA_MEM_TO_DEV; | |
870 | dma->tx_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; | |
871 | dma->tx_conf.dst_addr = p->port.mapbase + S3C2410_UTXH; | |
aa2f80e7 | 872 | dma->tx_conf.dst_maxburst = 1; |
62c37eed | 873 | |
ba3d6f8f | 874 | dma->rx_chan = dma_request_chan(p->port.dev, "rx"); |
62c37eed | 875 | |
d8db840d MS |
876 | if (IS_ERR(dma->rx_chan)) { |
877 | reason = "DMA RX channel request failed"; | |
878 | ret = PTR_ERR(dma->rx_chan); | |
879 | goto err_warn; | |
880 | } | |
881 | ||
882 | ret = dma_get_slave_caps(dma->rx_chan, &dma_caps); | |
883 | if (ret < 0 || | |
884 | dma_caps.residue_granularity < DMA_RESIDUE_GRANULARITY_BURST) { | |
885 | reason = "insufficient DMA RX engine capabilities"; | |
886 | ret = -EOPNOTSUPP; | |
887 | goto err_release_rx; | |
888 | } | |
62c37eed RB |
889 | |
890 | dmaengine_slave_config(dma->rx_chan, &dma->rx_conf); | |
891 | ||
ba3d6f8f MS |
892 | dma->tx_chan = dma_request_chan(p->port.dev, "tx"); |
893 | if (IS_ERR(dma->tx_chan)) { | |
d8db840d | 894 | reason = "DMA TX channel request failed"; |
500fcc08 MS |
895 | ret = PTR_ERR(dma->tx_chan); |
896 | goto err_release_rx; | |
62c37eed RB |
897 | } |
898 | ||
d8db840d MS |
899 | ret = dma_get_slave_caps(dma->tx_chan, &dma_caps); |
900 | if (ret < 0 || | |
901 | dma_caps.residue_granularity < DMA_RESIDUE_GRANULARITY_BURST) { | |
902 | reason = "insufficient DMA TX engine capabilities"; | |
903 | ret = -EOPNOTSUPP; | |
904 | goto err_release_tx; | |
905 | } | |
906 | ||
62c37eed RB |
907 | dmaengine_slave_config(dma->tx_chan, &dma->tx_conf); |
908 | ||
909 | /* RX buffer */ | |
910 | dma->rx_size = PAGE_SIZE; | |
911 | ||
912 | dma->rx_buf = kmalloc(dma->rx_size, GFP_KERNEL); | |
62c37eed | 913 | if (!dma->rx_buf) { |
500fcc08 MS |
914 | ret = -ENOMEM; |
915 | goto err_release_tx; | |
62c37eed RB |
916 | } |
917 | ||
768d64f4 | 918 | dma->rx_addr = dma_map_single(p->port.dev, dma->rx_buf, |
62c37eed | 919 | dma->rx_size, DMA_FROM_DEVICE); |
500fcc08 | 920 | if (dma_mapping_error(p->port.dev, dma->rx_addr)) { |
d8db840d | 921 | reason = "DMA mapping error for RX buffer"; |
500fcc08 MS |
922 | ret = -EIO; |
923 | goto err_free_rx; | |
924 | } | |
62c37eed | 925 | |
62c37eed | 926 | /* TX buffer */ |
768d64f4 | 927 | dma->tx_addr = dma_map_single(p->port.dev, p->port.state->xmit.buf, |
62c37eed | 928 | UART_XMIT_SIZE, DMA_TO_DEVICE); |
500fcc08 | 929 | if (dma_mapping_error(p->port.dev, dma->tx_addr)) { |
d8db840d | 930 | reason = "DMA mapping error for TX buffer"; |
500fcc08 MS |
931 | ret = -EIO; |
932 | goto err_unmap_rx; | |
933 | } | |
62c37eed RB |
934 | |
935 | return 0; | |
500fcc08 MS |
936 | |
937 | err_unmap_rx: | |
938 | dma_unmap_single(p->port.dev, dma->rx_addr, dma->rx_size, | |
939 | DMA_FROM_DEVICE); | |
940 | err_free_rx: | |
941 | kfree(dma->rx_buf); | |
942 | err_release_tx: | |
943 | dma_release_channel(dma->tx_chan); | |
944 | err_release_rx: | |
945 | dma_release_channel(dma->rx_chan); | |
d8db840d MS |
946 | err_warn: |
947 | if (reason) | |
948 | dev_warn(p->port.dev, "%s, DMA will not be used\n", reason); | |
500fcc08 | 949 | return ret; |
62c37eed RB |
950 | } |
951 | ||
952 | static void s3c24xx_serial_release_dma(struct s3c24xx_uart_port *p) | |
953 | { | |
954 | struct s3c24xx_uart_dma *dma = p->dma; | |
955 | ||
956 | if (dma->rx_chan) { | |
957 | dmaengine_terminate_all(dma->rx_chan); | |
768d64f4 | 958 | dma_unmap_single(p->port.dev, dma->rx_addr, |
62c37eed RB |
959 | dma->rx_size, DMA_FROM_DEVICE); |
960 | kfree(dma->rx_buf); | |
961 | dma_release_channel(dma->rx_chan); | |
962 | dma->rx_chan = NULL; | |
963 | } | |
964 | ||
965 | if (dma->tx_chan) { | |
966 | dmaengine_terminate_all(dma->tx_chan); | |
768d64f4 | 967 | dma_unmap_single(p->port.dev, dma->tx_addr, |
62c37eed RB |
968 | UART_XMIT_SIZE, DMA_TO_DEVICE); |
969 | dma_release_channel(dma->tx_chan); | |
970 | dma->tx_chan = NULL; | |
971 | } | |
972 | } | |
973 | ||
b497549a BD |
974 | static void s3c24xx_serial_shutdown(struct uart_port *port) |
975 | { | |
976 | struct s3c24xx_uart_port *ourport = to_ourport(port); | |
977 | ||
978 | if (ourport->tx_claimed) { | |
88bb4ea1 TA |
979 | if (!s3c24xx_serial_has_interrupt_mask(port)) |
980 | free_irq(ourport->tx_irq, ourport); | |
b497549a BD |
981 | tx_enabled(port) = 0; |
982 | ourport->tx_claimed = 0; | |
e91d863d | 983 | ourport->tx_mode = 0; |
b497549a BD |
984 | } |
985 | ||
986 | if (ourport->rx_claimed) { | |
88bb4ea1 TA |
987 | if (!s3c24xx_serial_has_interrupt_mask(port)) |
988 | free_irq(ourport->rx_irq, ourport); | |
b497549a BD |
989 | ourport->rx_claimed = 0; |
990 | rx_enabled(port) = 0; | |
991 | } | |
b497549a | 992 | |
88bb4ea1 TA |
993 | /* Clear pending interrupts and mask all interrupts */ |
994 | if (s3c24xx_serial_has_interrupt_mask(port)) { | |
b6ad2935 TF |
995 | free_irq(port->irq, ourport); |
996 | ||
88bb4ea1 TA |
997 | wr_regl(port, S3C64XX_UINTP, 0xf); |
998 | wr_regl(port, S3C64XX_UINTM, 0xf); | |
999 | } | |
62c37eed RB |
1000 | |
1001 | if (ourport->dma) | |
1002 | s3c24xx_serial_release_dma(ourport); | |
1003 | ||
29bef799 | 1004 | ourport->tx_in_progress = 0; |
88bb4ea1 | 1005 | } |
b497549a BD |
1006 | |
1007 | static int s3c24xx_serial_startup(struct uart_port *port) | |
1008 | { | |
1009 | struct s3c24xx_uart_port *ourport = to_ourport(port); | |
1010 | int ret; | |
1011 | ||
e4ac92df JP |
1012 | dbg("s3c24xx_serial_startup: port=%p (%08llx,%p)\n", |
1013 | port, (unsigned long long)port->mapbase, port->membase); | |
b497549a BD |
1014 | |
1015 | rx_enabled(port) = 1; | |
1016 | ||
b73c289c | 1017 | ret = request_irq(ourport->rx_irq, s3c24xx_serial_rx_chars, 0, |
b497549a BD |
1018 | s3c24xx_serial_portname(port), ourport); |
1019 | ||
1020 | if (ret != 0) { | |
d20925e1 | 1021 | dev_err(port->dev, "cannot get irq %d\n", ourport->rx_irq); |
b497549a BD |
1022 | return ret; |
1023 | } | |
1024 | ||
1025 | ourport->rx_claimed = 1; | |
1026 | ||
1027 | dbg("requesting tx irq...\n"); | |
1028 | ||
1029 | tx_enabled(port) = 1; | |
1030 | ||
b73c289c | 1031 | ret = request_irq(ourport->tx_irq, s3c24xx_serial_tx_chars, 0, |
b497549a BD |
1032 | s3c24xx_serial_portname(port), ourport); |
1033 | ||
1034 | if (ret) { | |
d20925e1 | 1035 | dev_err(port->dev, "cannot get irq %d\n", ourport->tx_irq); |
b497549a BD |
1036 | goto err; |
1037 | } | |
1038 | ||
1039 | ourport->tx_claimed = 1; | |
1040 | ||
1041 | dbg("s3c24xx_serial_startup ok\n"); | |
1042 | ||
1043 | /* the port reset code should have done the correct | |
1044 | * register setup for the port controls */ | |
1045 | ||
1046 | return ret; | |
1047 | ||
ef4aca70 | 1048 | err: |
b497549a BD |
1049 | s3c24xx_serial_shutdown(port); |
1050 | return ret; | |
1051 | } | |
1052 | ||
88bb4ea1 TA |
1053 | static int s3c64xx_serial_startup(struct uart_port *port) |
1054 | { | |
1055 | struct s3c24xx_uart_port *ourport = to_ourport(port); | |
b543c301 RB |
1056 | unsigned long flags; |
1057 | unsigned int ufcon; | |
88bb4ea1 TA |
1058 | int ret; |
1059 | ||
e4ac92df JP |
1060 | dbg("s3c64xx_serial_startup: port=%p (%08llx,%p)\n", |
1061 | port, (unsigned long long)port->mapbase, port->membase); | |
88bb4ea1 | 1062 | |
b6ad2935 | 1063 | wr_regl(port, S3C64XX_UINTM, 0xf); |
62c37eed RB |
1064 | if (ourport->dma) { |
1065 | ret = s3c24xx_serial_request_dma(ourport); | |
1066 | if (ret < 0) { | |
f98c7bce KK |
1067 | devm_kfree(port->dev, ourport->dma); |
1068 | ourport->dma = NULL; | |
62c37eed RB |
1069 | } |
1070 | } | |
b6ad2935 | 1071 | |
88bb4ea1 TA |
1072 | ret = request_irq(port->irq, s3c64xx_serial_handle_irq, IRQF_SHARED, |
1073 | s3c24xx_serial_portname(port), ourport); | |
1074 | if (ret) { | |
d20925e1 | 1075 | dev_err(port->dev, "cannot get irq %d\n", port->irq); |
88bb4ea1 TA |
1076 | return ret; |
1077 | } | |
1078 | ||
1079 | /* For compatibility with s3c24xx Soc's */ | |
1080 | rx_enabled(port) = 1; | |
1081 | ourport->rx_claimed = 1; | |
1082 | tx_enabled(port) = 0; | |
1083 | ourport->tx_claimed = 1; | |
1084 | ||
29bef799 RB |
1085 | spin_lock_irqsave(&port->lock, flags); |
1086 | ||
1087 | ufcon = rd_regl(port, S3C2410_UFCON); | |
31c6ba97 RB |
1088 | ufcon |= S3C2410_UFCON_RESETRX | S5PV210_UFCON_RXTRIG8; |
1089 | if (!uart_console(port)) | |
1090 | ufcon |= S3C2410_UFCON_RESETTX; | |
29bef799 RB |
1091 | wr_regl(port, S3C2410_UFCON, ufcon); |
1092 | ||
1093 | enable_rx_pio(ourport); | |
1094 | ||
1095 | spin_unlock_irqrestore(&port->lock, flags); | |
1096 | ||
88bb4ea1 | 1097 | /* Enable Rx Interrupt */ |
bbb5ff91 | 1098 | s3c24xx_clear_bit(port, S3C64XX_UINTM_RXD, S3C64XX_UINTM); |
29bef799 | 1099 | |
88bb4ea1 TA |
1100 | dbg("s3c64xx_serial_startup ok\n"); |
1101 | return ret; | |
1102 | } | |
1103 | ||
b497549a BD |
1104 | /* power power management control */ |
1105 | ||
1106 | static void s3c24xx_serial_pm(struct uart_port *port, unsigned int level, | |
1107 | unsigned int old) | |
1108 | { | |
1109 | struct s3c24xx_uart_port *ourport = to_ourport(port); | |
1ff383a4 | 1110 | int timeout = 10000; |
b497549a | 1111 | |
30555476 BD |
1112 | ourport->pm_level = level; |
1113 | ||
b497549a BD |
1114 | switch (level) { |
1115 | case 3: | |
1ff383a4 RB |
1116 | while (--timeout && !s3c24xx_serial_txempty_nofifo(port)) |
1117 | udelay(100); | |
1118 | ||
7cd88831 | 1119 | if (!IS_ERR(ourport->baudclk)) |
9484b009 | 1120 | clk_disable_unprepare(ourport->baudclk); |
b497549a | 1121 | |
9484b009 | 1122 | clk_disable_unprepare(ourport->clk); |
b497549a BD |
1123 | break; |
1124 | ||
1125 | case 0: | |
9484b009 | 1126 | clk_prepare_enable(ourport->clk); |
b497549a | 1127 | |
7cd88831 | 1128 | if (!IS_ERR(ourport->baudclk)) |
9484b009 | 1129 | clk_prepare_enable(ourport->baudclk); |
b497549a BD |
1130 | |
1131 | break; | |
1132 | default: | |
d20925e1 | 1133 | dev_err(port->dev, "s3c24xx_serial: unknown pm %d\n", level); |
b497549a BD |
1134 | } |
1135 | } | |
1136 | ||
1137 | /* baud rate calculation | |
1138 | * | |
1139 | * The UARTs on the S3C2410/S3C2440 can take their clocks from a number | |
1140 | * of different sources, including the peripheral clock ("pclk") and an | |
1141 | * external clock ("uclk"). The S3C2440 also adds the core clock ("fclk") | |
1142 | * with a programmable extra divisor. | |
1143 | * | |
1144 | * The following code goes through the clock sources, and calculates the | |
1145 | * baud clocks (and the resultant actual baud rates) and then tries to | |
1146 | * pick the closest one and select that. | |
1147 | * | |
1148 | */ | |
1149 | ||
5f5a7a55 | 1150 | #define MAX_CLK_NAME_LENGTH 15 |
b497549a | 1151 | |
5f5a7a55 | 1152 | static inline int s3c24xx_serial_getsource(struct uart_port *port) |
b497549a BD |
1153 | { |
1154 | struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port); | |
5f5a7a55 | 1155 | unsigned int ucon; |
b497549a | 1156 | |
5f5a7a55 TA |
1157 | if (info->num_clks == 1) |
1158 | return 0; | |
b497549a | 1159 | |
5f5a7a55 TA |
1160 | ucon = rd_regl(port, S3C2410_UCON); |
1161 | ucon &= info->clksel_mask; | |
1162 | return ucon >> info->clksel_shift; | |
b497549a BD |
1163 | } |
1164 | ||
5f5a7a55 TA |
1165 | static void s3c24xx_serial_setsource(struct uart_port *port, |
1166 | unsigned int clk_sel) | |
b497549a | 1167 | { |
5f5a7a55 TA |
1168 | struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port); |
1169 | unsigned int ucon; | |
b497549a | 1170 | |
5f5a7a55 TA |
1171 | if (info->num_clks == 1) |
1172 | return; | |
090f848d | 1173 | |
5f5a7a55 TA |
1174 | ucon = rd_regl(port, S3C2410_UCON); |
1175 | if ((ucon & info->clksel_mask) >> info->clksel_shift == clk_sel) | |
1176 | return; | |
b497549a | 1177 | |
5f5a7a55 TA |
1178 | ucon &= ~info->clksel_mask; |
1179 | ucon |= clk_sel << info->clksel_shift; | |
1180 | wr_regl(port, S3C2410_UCON, ucon); | |
b497549a BD |
1181 | } |
1182 | ||
5f5a7a55 TA |
1183 | static unsigned int s3c24xx_serial_getclk(struct s3c24xx_uart_port *ourport, |
1184 | unsigned int req_baud, struct clk **best_clk, | |
1185 | unsigned int *clk_num) | |
b497549a | 1186 | { |
5f5a7a55 TA |
1187 | struct s3c24xx_uart_info *info = ourport->info; |
1188 | struct clk *clk; | |
1189 | unsigned long rate; | |
1190 | unsigned int cnt, baud, quot, clk_sel, best_quot = 0; | |
1191 | char clkname[MAX_CLK_NAME_LENGTH]; | |
1192 | int calc_deviation, deviation = (1 << 30) - 1; | |
1193 | ||
5f5a7a55 TA |
1194 | clk_sel = (ourport->cfg->clk_sel) ? ourport->cfg->clk_sel : |
1195 | ourport->info->def_clk_sel; | |
1196 | for (cnt = 0; cnt < info->num_clks; cnt++) { | |
1197 | if (!(clk_sel & (1 << cnt))) | |
1198 | continue; | |
1199 | ||
1200 | sprintf(clkname, "clk_uart_baud%d", cnt); | |
1201 | clk = clk_get(ourport->port.dev, clkname); | |
7cd88831 | 1202 | if (IS_ERR(clk)) |
5f5a7a55 TA |
1203 | continue; |
1204 | ||
1205 | rate = clk_get_rate(clk); | |
1206 | if (!rate) | |
1207 | continue; | |
1208 | ||
1209 | if (ourport->info->has_divslot) { | |
1210 | unsigned long div = rate / req_baud; | |
1211 | ||
1212 | /* The UDIVSLOT register on the newer UARTs allows us to | |
1213 | * get a divisor adjustment of 1/16th on the baud clock. | |
1214 | * | |
1215 | * We don't keep the UDIVSLOT value (the 16ths we | |
1216 | * calculated by not multiplying the baud by 16) as it | |
1217 | * is easy enough to recalculate. | |
1218 | */ | |
1219 | ||
1220 | quot = div / 16; | |
1221 | baud = rate / div; | |
1222 | } else { | |
1223 | quot = (rate + (8 * req_baud)) / (16 * req_baud); | |
1224 | baud = rate / (quot * 16); | |
b497549a | 1225 | } |
5f5a7a55 | 1226 | quot--; |
b497549a | 1227 | |
5f5a7a55 TA |
1228 | calc_deviation = req_baud - baud; |
1229 | if (calc_deviation < 0) | |
1230 | calc_deviation = -calc_deviation; | |
b497549a | 1231 | |
5f5a7a55 TA |
1232 | if (calc_deviation < deviation) { |
1233 | *best_clk = clk; | |
1234 | best_quot = quot; | |
1235 | *clk_num = cnt; | |
1236 | deviation = calc_deviation; | |
b497549a BD |
1237 | } |
1238 | } | |
1239 | ||
5f5a7a55 | 1240 | return best_quot; |
b497549a BD |
1241 | } |
1242 | ||
090f848d BD |
1243 | /* udivslot_table[] |
1244 | * | |
1245 | * This table takes the fractional value of the baud divisor and gives | |
1246 | * the recommended setting for the UDIVSLOT register. | |
1247 | */ | |
1248 | static u16 udivslot_table[16] = { | |
1249 | [0] = 0x0000, | |
1250 | [1] = 0x0080, | |
1251 | [2] = 0x0808, | |
1252 | [3] = 0x0888, | |
1253 | [4] = 0x2222, | |
1254 | [5] = 0x4924, | |
1255 | [6] = 0x4A52, | |
1256 | [7] = 0x54AA, | |
1257 | [8] = 0x5555, | |
1258 | [9] = 0xD555, | |
1259 | [10] = 0xD5D5, | |
1260 | [11] = 0xDDD5, | |
1261 | [12] = 0xDDDD, | |
1262 | [13] = 0xDFDD, | |
1263 | [14] = 0xDFDF, | |
1264 | [15] = 0xFFDF, | |
1265 | }; | |
1266 | ||
b497549a BD |
1267 | static void s3c24xx_serial_set_termios(struct uart_port *port, |
1268 | struct ktermios *termios, | |
1269 | struct ktermios *old) | |
1270 | { | |
1271 | struct s3c2410_uartcfg *cfg = s3c24xx_port_to_cfg(port); | |
1272 | struct s3c24xx_uart_port *ourport = to_ourport(port); | |
7cd88831 | 1273 | struct clk *clk = ERR_PTR(-EINVAL); |
b497549a | 1274 | unsigned long flags; |
5f5a7a55 | 1275 | unsigned int baud, quot, clk_sel = 0; |
b497549a BD |
1276 | unsigned int ulcon; |
1277 | unsigned int umcon; | |
090f848d | 1278 | unsigned int udivslot = 0; |
b497549a BD |
1279 | |
1280 | /* | |
1281 | * We don't support modem control lines. | |
1282 | */ | |
1283 | termios->c_cflag &= ~(HUPCL | CMSPAR); | |
1284 | termios->c_cflag |= CLOCAL; | |
1285 | ||
1286 | /* | |
1287 | * Ask the core to calculate the divisor for us. | |
1288 | */ | |
1289 | ||
1290 | baud = uart_get_baud_rate(port, termios, old, 0, 115200*8); | |
5f5a7a55 | 1291 | quot = s3c24xx_serial_getclk(ourport, baud, &clk, &clk_sel); |
b497549a BD |
1292 | if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST) |
1293 | quot = port->custom_divisor; | |
7cd88831 | 1294 | if (IS_ERR(clk)) |
5f5a7a55 | 1295 | return; |
b497549a BD |
1296 | |
1297 | /* check to see if we need to change clock source */ | |
1298 | ||
5f5a7a55 | 1299 | if (ourport->baudclk != clk) { |
b8995f52 CC |
1300 | clk_prepare_enable(clk); |
1301 | ||
5f5a7a55 | 1302 | s3c24xx_serial_setsource(port, clk_sel); |
b497549a | 1303 | |
7cd88831 | 1304 | if (!IS_ERR(ourport->baudclk)) { |
9484b009 | 1305 | clk_disable_unprepare(ourport->baudclk); |
7cd88831 | 1306 | ourport->baudclk = ERR_PTR(-EINVAL); |
b497549a BD |
1307 | } |
1308 | ||
b497549a | 1309 | ourport->baudclk = clk; |
30555476 | 1310 | ourport->baudclk_rate = clk ? clk_get_rate(clk) : 0; |
b497549a BD |
1311 | } |
1312 | ||
090f848d BD |
1313 | if (ourport->info->has_divslot) { |
1314 | unsigned int div = ourport->baudclk_rate / baud; | |
1315 | ||
8b526ae4 JL |
1316 | if (cfg->has_fracval) { |
1317 | udivslot = (div & 15); | |
1318 | dbg("fracval = %04x\n", udivslot); | |
1319 | } else { | |
1320 | udivslot = udivslot_table[div & 15]; | |
1321 | dbg("udivslot = %04x (div %d)\n", udivslot, div & 15); | |
1322 | } | |
090f848d BD |
1323 | } |
1324 | ||
b497549a BD |
1325 | switch (termios->c_cflag & CSIZE) { |
1326 | case CS5: | |
1327 | dbg("config: 5bits/char\n"); | |
1328 | ulcon = S3C2410_LCON_CS5; | |
1329 | break; | |
1330 | case CS6: | |
1331 | dbg("config: 6bits/char\n"); | |
1332 | ulcon = S3C2410_LCON_CS6; | |
1333 | break; | |
1334 | case CS7: | |
1335 | dbg("config: 7bits/char\n"); | |
1336 | ulcon = S3C2410_LCON_CS7; | |
1337 | break; | |
1338 | case CS8: | |
1339 | default: | |
1340 | dbg("config: 8bits/char\n"); | |
1341 | ulcon = S3C2410_LCON_CS8; | |
1342 | break; | |
1343 | } | |
1344 | ||
1345 | /* preserve original lcon IR settings */ | |
1346 | ulcon |= (cfg->ulcon & S3C2410_LCON_IRM); | |
1347 | ||
1348 | if (termios->c_cflag & CSTOPB) | |
1349 | ulcon |= S3C2410_LCON_STOPB; | |
1350 | ||
b497549a BD |
1351 | if (termios->c_cflag & PARENB) { |
1352 | if (termios->c_cflag & PARODD) | |
1353 | ulcon |= S3C2410_LCON_PODD; | |
1354 | else | |
1355 | ulcon |= S3C2410_LCON_PEVEN; | |
1356 | } else { | |
1357 | ulcon |= S3C2410_LCON_PNONE; | |
1358 | } | |
1359 | ||
1360 | spin_lock_irqsave(&port->lock, flags); | |
1361 | ||
090f848d BD |
1362 | dbg("setting ulcon to %08x, brddiv to %d, udivslot %08x\n", |
1363 | ulcon, quot, udivslot); | |
b497549a BD |
1364 | |
1365 | wr_regl(port, S3C2410_ULCON, ulcon); | |
1366 | wr_regl(port, S3C2410_UBRDIV, quot); | |
2d1e5a48 JMG |
1367 | |
1368 | umcon = rd_regl(port, S3C2410_UMCON); | |
1369 | if (termios->c_cflag & CRTSCTS) { | |
1370 | umcon |= S3C2410_UMCOM_AFC; | |
1371 | /* Disable RTS when RX FIFO contains 63 bytes */ | |
1372 | umcon &= ~S3C2412_UMCON_AFC_8; | |
1373 | } else { | |
1374 | umcon &= ~S3C2410_UMCOM_AFC; | |
1375 | } | |
b497549a BD |
1376 | wr_regl(port, S3C2410_UMCON, umcon); |
1377 | ||
090f848d BD |
1378 | if (ourport->info->has_divslot) |
1379 | wr_regl(port, S3C2443_DIVSLOT, udivslot); | |
1380 | ||
b497549a BD |
1381 | dbg("uart: ulcon = 0x%08x, ucon = 0x%08x, ufcon = 0x%08x\n", |
1382 | rd_regl(port, S3C2410_ULCON), | |
1383 | rd_regl(port, S3C2410_UCON), | |
1384 | rd_regl(port, S3C2410_UFCON)); | |
1385 | ||
1386 | /* | |
1387 | * Update the per-port timeout. | |
1388 | */ | |
1389 | uart_update_timeout(port, termios->c_cflag, baud); | |
1390 | ||
1391 | /* | |
1392 | * Which character status flags are we interested in? | |
1393 | */ | |
1394 | port->read_status_mask = S3C2410_UERSTAT_OVERRUN; | |
1395 | if (termios->c_iflag & INPCK) | |
ef4aca70 RB |
1396 | port->read_status_mask |= S3C2410_UERSTAT_FRAME | |
1397 | S3C2410_UERSTAT_PARITY; | |
b497549a BD |
1398 | /* |
1399 | * Which character status flags should we ignore? | |
1400 | */ | |
1401 | port->ignore_status_mask = 0; | |
1402 | if (termios->c_iflag & IGNPAR) | |
1403 | port->ignore_status_mask |= S3C2410_UERSTAT_OVERRUN; | |
1404 | if (termios->c_iflag & IGNBRK && termios->c_iflag & IGNPAR) | |
1405 | port->ignore_status_mask |= S3C2410_UERSTAT_FRAME; | |
1406 | ||
1407 | /* | |
1408 | * Ignore all characters if CREAD is not set. | |
1409 | */ | |
1410 | if ((termios->c_cflag & CREAD) == 0) | |
1411 | port->ignore_status_mask |= RXSTAT_DUMMY_READ; | |
1412 | ||
1413 | spin_unlock_irqrestore(&port->lock, flags); | |
1414 | } | |
1415 | ||
1416 | static const char *s3c24xx_serial_type(struct uart_port *port) | |
1417 | { | |
1418 | switch (port->type) { | |
1419 | case PORT_S3C2410: | |
1420 | return "S3C2410"; | |
1421 | case PORT_S3C2440: | |
1422 | return "S3C2440"; | |
1423 | case PORT_S3C2412: | |
1424 | return "S3C2412"; | |
b690ace5 BD |
1425 | case PORT_S3C6400: |
1426 | return "S3C6400/10"; | |
b497549a BD |
1427 | default: |
1428 | return NULL; | |
1429 | } | |
1430 | } | |
1431 | ||
1432 | #define MAP_SIZE (0x100) | |
1433 | ||
1434 | static void s3c24xx_serial_release_port(struct uart_port *port) | |
1435 | { | |
1436 | release_mem_region(port->mapbase, MAP_SIZE); | |
1437 | } | |
1438 | ||
1439 | static int s3c24xx_serial_request_port(struct uart_port *port) | |
1440 | { | |
1441 | const char *name = s3c24xx_serial_portname(port); | |
1442 | return request_mem_region(port->mapbase, MAP_SIZE, name) ? 0 : -EBUSY; | |
1443 | } | |
1444 | ||
1445 | static void s3c24xx_serial_config_port(struct uart_port *port, int flags) | |
1446 | { | |
1447 | struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port); | |
1448 | ||
1449 | if (flags & UART_CONFIG_TYPE && | |
1450 | s3c24xx_serial_request_port(port) == 0) | |
1451 | port->type = info->type; | |
1452 | } | |
1453 | ||
1454 | /* | |
1455 | * verify the new serial_struct (for TIOCSSERIAL). | |
1456 | */ | |
1457 | static int | |
1458 | s3c24xx_serial_verify_port(struct uart_port *port, struct serial_struct *ser) | |
1459 | { | |
1460 | struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port); | |
1461 | ||
1462 | if (ser->type != PORT_UNKNOWN && ser->type != info->type) | |
1463 | return -EINVAL; | |
1464 | ||
1465 | return 0; | |
1466 | } | |
1467 | ||
1468 | ||
1469 | #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE | |
1470 | ||
1471 | static struct console s3c24xx_serial_console; | |
1472 | ||
93b5c032 JP |
1473 | static int __init s3c24xx_serial_console_init(void) |
1474 | { | |
1475 | register_console(&s3c24xx_serial_console); | |
1476 | return 0; | |
1477 | } | |
1478 | console_initcall(s3c24xx_serial_console_init); | |
1479 | ||
b497549a BD |
1480 | #define S3C24XX_SERIAL_CONSOLE &s3c24xx_serial_console |
1481 | #else | |
1482 | #define S3C24XX_SERIAL_CONSOLE NULL | |
1483 | #endif | |
1484 | ||
84f57d9e | 1485 | #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL) |
93b5c032 JP |
1486 | static int s3c24xx_serial_get_poll_char(struct uart_port *port); |
1487 | static void s3c24xx_serial_put_poll_char(struct uart_port *port, | |
1488 | unsigned char c); | |
1489 | #endif | |
1490 | ||
b497549a BD |
1491 | static struct uart_ops s3c24xx_serial_ops = { |
1492 | .pm = s3c24xx_serial_pm, | |
1493 | .tx_empty = s3c24xx_serial_tx_empty, | |
1494 | .get_mctrl = s3c24xx_serial_get_mctrl, | |
1495 | .set_mctrl = s3c24xx_serial_set_mctrl, | |
1496 | .stop_tx = s3c24xx_serial_stop_tx, | |
1497 | .start_tx = s3c24xx_serial_start_tx, | |
1498 | .stop_rx = s3c24xx_serial_stop_rx, | |
b497549a BD |
1499 | .break_ctl = s3c24xx_serial_break_ctl, |
1500 | .startup = s3c24xx_serial_startup, | |
1501 | .shutdown = s3c24xx_serial_shutdown, | |
1502 | .set_termios = s3c24xx_serial_set_termios, | |
1503 | .type = s3c24xx_serial_type, | |
1504 | .release_port = s3c24xx_serial_release_port, | |
1505 | .request_port = s3c24xx_serial_request_port, | |
1506 | .config_port = s3c24xx_serial_config_port, | |
1507 | .verify_port = s3c24xx_serial_verify_port, | |
84f57d9e | 1508 | #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL) |
93b5c032 JP |
1509 | .poll_get_char = s3c24xx_serial_get_poll_char, |
1510 | .poll_put_char = s3c24xx_serial_put_poll_char, | |
1511 | #endif | |
b497549a BD |
1512 | }; |
1513 | ||
b497549a BD |
1514 | static struct uart_driver s3c24xx_uart_drv = { |
1515 | .owner = THIS_MODULE, | |
2cf0c58e | 1516 | .driver_name = "s3c2410_serial", |
bdd4915a | 1517 | .nr = CONFIG_SERIAL_SAMSUNG_UARTS, |
b497549a | 1518 | .cons = S3C24XX_SERIAL_CONSOLE, |
2cf0c58e | 1519 | .dev_name = S3C24XX_SERIAL_NAME, |
b497549a BD |
1520 | .major = S3C24XX_SERIAL_MAJOR, |
1521 | .minor = S3C24XX_SERIAL_MINOR, | |
1522 | }; | |
1523 | ||
ef4aca70 RB |
1524 | #define __PORT_LOCK_UNLOCKED(i) \ |
1525 | __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[i].port.lock) | |
1526 | static struct s3c24xx_uart_port | |
1527 | s3c24xx_serial_ports[CONFIG_SERIAL_SAMSUNG_UARTS] = { | |
b497549a BD |
1528 | [0] = { |
1529 | .port = { | |
ef4aca70 | 1530 | .lock = __PORT_LOCK_UNLOCKED(0), |
b497549a | 1531 | .iotype = UPIO_MEM, |
b497549a BD |
1532 | .uartclk = 0, |
1533 | .fifosize = 16, | |
1534 | .ops = &s3c24xx_serial_ops, | |
1535 | .flags = UPF_BOOT_AUTOCONF, | |
1536 | .line = 0, | |
1537 | } | |
1538 | }, | |
1539 | [1] = { | |
1540 | .port = { | |
ef4aca70 | 1541 | .lock = __PORT_LOCK_UNLOCKED(1), |
b497549a | 1542 | .iotype = UPIO_MEM, |
b497549a BD |
1543 | .uartclk = 0, |
1544 | .fifosize = 16, | |
1545 | .ops = &s3c24xx_serial_ops, | |
1546 | .flags = UPF_BOOT_AUTOCONF, | |
1547 | .line = 1, | |
1548 | } | |
1549 | }, | |
03d5e77b | 1550 | #if CONFIG_SERIAL_SAMSUNG_UARTS > 2 |
b497549a BD |
1551 | |
1552 | [2] = { | |
1553 | .port = { | |
ef4aca70 | 1554 | .lock = __PORT_LOCK_UNLOCKED(2), |
b497549a | 1555 | .iotype = UPIO_MEM, |
b497549a BD |
1556 | .uartclk = 0, |
1557 | .fifosize = 16, | |
1558 | .ops = &s3c24xx_serial_ops, | |
1559 | .flags = UPF_BOOT_AUTOCONF, | |
1560 | .line = 2, | |
1561 | } | |
03d5e77b BD |
1562 | }, |
1563 | #endif | |
1564 | #if CONFIG_SERIAL_SAMSUNG_UARTS > 3 | |
1565 | [3] = { | |
1566 | .port = { | |
ef4aca70 | 1567 | .lock = __PORT_LOCK_UNLOCKED(3), |
03d5e77b | 1568 | .iotype = UPIO_MEM, |
03d5e77b BD |
1569 | .uartclk = 0, |
1570 | .fifosize = 16, | |
1571 | .ops = &s3c24xx_serial_ops, | |
1572 | .flags = UPF_BOOT_AUTOCONF, | |
1573 | .line = 3, | |
1574 | } | |
b497549a BD |
1575 | } |
1576 | #endif | |
1577 | }; | |
ef4aca70 | 1578 | #undef __PORT_LOCK_UNLOCKED |
b497549a BD |
1579 | |
1580 | /* s3c24xx_serial_resetport | |
1581 | * | |
0dfb3b41 | 1582 | * reset the fifos and other the settings. |
b497549a BD |
1583 | */ |
1584 | ||
0dfb3b41 TA |
1585 | static void s3c24xx_serial_resetport(struct uart_port *port, |
1586 | struct s3c2410_uartcfg *cfg) | |
b497549a BD |
1587 | { |
1588 | struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port); | |
0dfb3b41 TA |
1589 | unsigned long ucon = rd_regl(port, S3C2410_UCON); |
1590 | unsigned int ucon_mask; | |
b497549a | 1591 | |
0dfb3b41 TA |
1592 | ucon_mask = info->clksel_mask; |
1593 | if (info->type == PORT_S3C2440) | |
1594 | ucon_mask |= S3C2440_UCON0_DIVMASK; | |
1595 | ||
1596 | ucon &= ucon_mask; | |
1597 | wr_regl(port, S3C2410_UCON, ucon | cfg->ucon); | |
1598 | ||
1599 | /* reset both fifos */ | |
1600 | wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH); | |
1601 | wr_regl(port, S3C2410_UFCON, cfg->ufcon); | |
1602 | ||
1603 | /* some delay is required after fifo reset */ | |
1604 | udelay(1); | |
b497549a BD |
1605 | } |
1606 | ||
30555476 | 1607 | |
ebaa81c7 | 1608 | #ifdef CONFIG_ARM_S3C24XX_CPUFREQ |
30555476 BD |
1609 | |
1610 | static int s3c24xx_serial_cpufreq_transition(struct notifier_block *nb, | |
1611 | unsigned long val, void *data) | |
1612 | { | |
1613 | struct s3c24xx_uart_port *port; | |
1614 | struct uart_port *uport; | |
1615 | ||
1616 | port = container_of(nb, struct s3c24xx_uart_port, freq_transition); | |
1617 | uport = &port->port; | |
1618 | ||
1619 | /* check to see if port is enabled */ | |
1620 | ||
1621 | if (port->pm_level != 0) | |
1622 | return 0; | |
1623 | ||
1624 | /* try and work out if the baudrate is changing, we can detect | |
1625 | * a change in rate, but we do not have support for detecting | |
1626 | * a disturbance in the clock-rate over the change. | |
1627 | */ | |
1628 | ||
25f04ad4 | 1629 | if (IS_ERR(port->baudclk)) |
30555476 BD |
1630 | goto exit; |
1631 | ||
25f04ad4 | 1632 | if (port->baudclk_rate == clk_get_rate(port->baudclk)) |
30555476 BD |
1633 | goto exit; |
1634 | ||
1635 | if (val == CPUFREQ_PRECHANGE) { | |
1636 | /* we should really shut the port down whilst the | |
1637 | * frequency change is in progress. */ | |
1638 | ||
1639 | } else if (val == CPUFREQ_POSTCHANGE) { | |
1640 | struct ktermios *termios; | |
1641 | struct tty_struct *tty; | |
1642 | ||
ebd2c8f6 | 1643 | if (uport->state == NULL) |
30555476 | 1644 | goto exit; |
30555476 | 1645 | |
ebd2c8f6 | 1646 | tty = uport->state->port.tty; |
30555476 | 1647 | |
7de40c21 | 1648 | if (tty == NULL) |
30555476 | 1649 | goto exit; |
30555476 | 1650 | |
adc8d746 | 1651 | termios = &tty->termios; |
30555476 BD |
1652 | |
1653 | if (termios == NULL) { | |
d20925e1 | 1654 | dev_warn(uport->dev, "%s: no termios?\n", __func__); |
30555476 BD |
1655 | goto exit; |
1656 | } | |
1657 | ||
1658 | s3c24xx_serial_set_termios(uport, termios, NULL); | |
1659 | } | |
1660 | ||
ef4aca70 | 1661 | exit: |
30555476 BD |
1662 | return 0; |
1663 | } | |
1664 | ||
ef4aca70 RB |
1665 | static inline int |
1666 | s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port) | |
30555476 BD |
1667 | { |
1668 | port->freq_transition.notifier_call = s3c24xx_serial_cpufreq_transition; | |
1669 | ||
1670 | return cpufreq_register_notifier(&port->freq_transition, | |
1671 | CPUFREQ_TRANSITION_NOTIFIER); | |
1672 | } | |
1673 | ||
ef4aca70 RB |
1674 | static inline void |
1675 | s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port) | |
30555476 BD |
1676 | { |
1677 | cpufreq_unregister_notifier(&port->freq_transition, | |
1678 | CPUFREQ_TRANSITION_NOTIFIER); | |
1679 | } | |
1680 | ||
1681 | #else | |
ef4aca70 RB |
1682 | static inline int |
1683 | s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port) | |
30555476 BD |
1684 | { |
1685 | return 0; | |
1686 | } | |
1687 | ||
ef4aca70 RB |
1688 | static inline void |
1689 | s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port) | |
30555476 BD |
1690 | { |
1691 | } | |
1692 | #endif | |
1693 | ||
b497549a BD |
1694 | /* s3c24xx_serial_init_port |
1695 | * | |
1696 | * initialise a single serial port from the platform device given | |
1697 | */ | |
1698 | ||
1699 | static int s3c24xx_serial_init_port(struct s3c24xx_uart_port *ourport, | |
b497549a BD |
1700 | struct platform_device *platdev) |
1701 | { | |
1702 | struct uart_port *port = &ourport->port; | |
da121506 | 1703 | struct s3c2410_uartcfg *cfg = ourport->cfg; |
b497549a BD |
1704 | struct resource *res; |
1705 | int ret; | |
1706 | ||
1707 | dbg("s3c24xx_serial_init_port: port=%p, platdev=%p\n", port, platdev); | |
1708 | ||
1709 | if (platdev == NULL) | |
1710 | return -ENODEV; | |
1711 | ||
b497549a | 1712 | if (port->mapbase != 0) |
e51e4d8a | 1713 | return -EINVAL; |
b497549a | 1714 | |
b497549a BD |
1715 | /* setup info for port */ |
1716 | port->dev = &platdev->dev; | |
b497549a | 1717 | |
88bb4ea1 TA |
1718 | /* Startup sequence is different for s3c64xx and higher SoC's */ |
1719 | if (s3c24xx_serial_has_interrupt_mask(port)) | |
1720 | s3c24xx_serial_ops.startup = s3c64xx_serial_startup; | |
1721 | ||
b497549a BD |
1722 | port->uartclk = 1; |
1723 | ||
1724 | if (cfg->uart_flags & UPF_CONS_FLOW) { | |
1725 | dbg("s3c24xx_serial_init_port: enabling flow control\n"); | |
1726 | port->flags |= UPF_CONS_FLOW; | |
1727 | } | |
1728 | ||
1729 | /* sort our the physical and virtual addresses for each UART */ | |
1730 | ||
1731 | res = platform_get_resource(platdev, IORESOURCE_MEM, 0); | |
1732 | if (res == NULL) { | |
d20925e1 | 1733 | dev_err(port->dev, "failed to find memory resource for uart\n"); |
b497549a BD |
1734 | return -EINVAL; |
1735 | } | |
1736 | ||
e4ac92df | 1737 | dbg("resource %pR)\n", res); |
b497549a | 1738 | |
41147bfd TA |
1739 | port->membase = devm_ioremap(port->dev, res->start, resource_size(res)); |
1740 | if (!port->membase) { | |
1741 | dev_err(port->dev, "failed to remap controller address\n"); | |
1742 | return -EBUSY; | |
1743 | } | |
1744 | ||
b690ace5 | 1745 | port->mapbase = res->start; |
b497549a BD |
1746 | ret = platform_get_irq(platdev, 0); |
1747 | if (ret < 0) | |
1748 | port->irq = 0; | |
b73c289c | 1749 | else { |
b497549a | 1750 | port->irq = ret; |
b73c289c BD |
1751 | ourport->rx_irq = ret; |
1752 | ourport->tx_irq = ret + 1; | |
1753 | } | |
9303ac15 | 1754 | |
b73c289c BD |
1755 | ret = platform_get_irq(platdev, 1); |
1756 | if (ret > 0) | |
1757 | ourport->tx_irq = ret; | |
658c9d2b RB |
1758 | /* |
1759 | * DMA is currently supported only on DT platforms, if DMA properties | |
1760 | * are specified. | |
1761 | */ | |
1762 | if (platdev->dev.of_node && of_find_property(platdev->dev.of_node, | |
1763 | "dmas", NULL)) { | |
1764 | ourport->dma = devm_kzalloc(port->dev, | |
1765 | sizeof(*ourport->dma), | |
1766 | GFP_KERNEL); | |
e51e4d8a KK |
1767 | if (!ourport->dma) { |
1768 | ret = -ENOMEM; | |
1769 | goto err; | |
1770 | } | |
658c9d2b | 1771 | } |
b497549a BD |
1772 | |
1773 | ourport->clk = clk_get(&platdev->dev, "uart"); | |
60e93575 CK |
1774 | if (IS_ERR(ourport->clk)) { |
1775 | pr_err("%s: Controller clock not found\n", | |
1776 | dev_name(&platdev->dev)); | |
e51e4d8a KK |
1777 | ret = PTR_ERR(ourport->clk); |
1778 | goto err; | |
60e93575 CK |
1779 | } |
1780 | ||
1781 | ret = clk_prepare_enable(ourport->clk); | |
1782 | if (ret) { | |
1783 | pr_err("uart: clock failed to prepare+enable: %d\n", ret); | |
1784 | clk_put(ourport->clk); | |
e51e4d8a | 1785 | goto err; |
60e93575 | 1786 | } |
b497549a | 1787 | |
88bb4ea1 TA |
1788 | /* Keep all interrupts masked and cleared */ |
1789 | if (s3c24xx_serial_has_interrupt_mask(port)) { | |
1790 | wr_regl(port, S3C64XX_UINTM, 0xf); | |
1791 | wr_regl(port, S3C64XX_UINTP, 0xf); | |
1792 | wr_regl(port, S3C64XX_UINTSP, 0xf); | |
1793 | } | |
1794 | ||
1ff5b64d FE |
1795 | dbg("port: map=%pa, mem=%p, irq=%d (%d,%d), clock=%u\n", |
1796 | &port->mapbase, port->membase, port->irq, | |
b73c289c | 1797 | ourport->rx_irq, ourport->tx_irq, port->uartclk); |
b497549a BD |
1798 | |
1799 | /* reset the fifos (and setup the uart) */ | |
1800 | s3c24xx_serial_resetport(port, cfg); | |
e51e4d8a | 1801 | |
b497549a | 1802 | return 0; |
e51e4d8a KK |
1803 | |
1804 | err: | |
1805 | port->mapbase = 0; | |
1806 | return ret; | |
b497549a BD |
1807 | } |
1808 | ||
b497549a BD |
1809 | /* Device driver serial port probe */ |
1810 | ||
26c919e1 | 1811 | static const struct of_device_id s3c24xx_uart_dt_match[]; |
b497549a BD |
1812 | static int probe_index; |
1813 | ||
26c919e1 TA |
1814 | static inline struct s3c24xx_serial_drv_data *s3c24xx_get_driver_data( |
1815 | struct platform_device *pdev) | |
1816 | { | |
1817 | #ifdef CONFIG_OF | |
1818 | if (pdev->dev.of_node) { | |
1819 | const struct of_device_id *match; | |
1820 | match = of_match_node(s3c24xx_uart_dt_match, pdev->dev.of_node); | |
1821 | return (struct s3c24xx_serial_drv_data *)match->data; | |
1822 | } | |
1823 | #endif | |
1824 | return (struct s3c24xx_serial_drv_data *) | |
1825 | platform_get_device_id(pdev)->driver_data; | |
1826 | } | |
1827 | ||
da121506 | 1828 | static int s3c24xx_serial_probe(struct platform_device *pdev) |
b497549a | 1829 | { |
4622eb68 | 1830 | struct device_node *np = pdev->dev.of_node; |
b497549a | 1831 | struct s3c24xx_uart_port *ourport; |
13a9f6c6 | 1832 | int index = probe_index; |
b497549a BD |
1833 | int ret; |
1834 | ||
4622eb68 NKC |
1835 | if (np) { |
1836 | ret = of_alias_get_id(np, "serial"); | |
13a9f6c6 TF |
1837 | if (ret >= 0) |
1838 | index = ret; | |
1839 | } | |
1840 | ||
1841 | dbg("s3c24xx_serial_probe(%p) %d\n", pdev, index); | |
b497549a | 1842 | |
49ee23b7 GU |
1843 | if (index >= ARRAY_SIZE(s3c24xx_serial_ports)) { |
1844 | dev_err(&pdev->dev, "serial%d out of range\n", index); | |
1845 | return -EINVAL; | |
1846 | } | |
13a9f6c6 | 1847 | ourport = &s3c24xx_serial_ports[index]; |
da121506 | 1848 | |
26c919e1 TA |
1849 | ourport->drv_data = s3c24xx_get_driver_data(pdev); |
1850 | if (!ourport->drv_data) { | |
1851 | dev_err(&pdev->dev, "could not find driver data\n"); | |
1852 | return -ENODEV; | |
1853 | } | |
da121506 | 1854 | |
7cd88831 | 1855 | ourport->baudclk = ERR_PTR(-EINVAL); |
da121506 | 1856 | ourport->info = ourport->drv_data->info; |
574de559 | 1857 | ourport->cfg = (dev_get_platdata(&pdev->dev)) ? |
d4aab206 | 1858 | dev_get_platdata(&pdev->dev) : |
da121506 TA |
1859 | ourport->drv_data->def_cfg; |
1860 | ||
4622eb68 NKC |
1861 | if (np) |
1862 | of_property_read_u32(np, | |
135f07c3 NKC |
1863 | "samsung,uart-fifosize", &ourport->port.fifosize); |
1864 | ||
2f1ba72d RB |
1865 | if (ourport->drv_data->fifosize[index]) |
1866 | ourport->port.fifosize = ourport->drv_data->fifosize[index]; | |
1867 | else if (ourport->info->fifosize) | |
1868 | ourport->port.fifosize = ourport->info->fifosize; | |
da121506 | 1869 | |
81ccb2a6 MS |
1870 | /* |
1871 | * DMA transfers must be aligned at least to cache line size, | |
1872 | * so find minimal transfer size suitable for DMA mode | |
1873 | */ | |
1874 | ourport->min_dma_size = max_t(int, ourport->port.fifosize, | |
1875 | dma_get_cache_alignment()); | |
1876 | ||
b497549a BD |
1877 | dbg("%s: initialising port %p...\n", __func__, ourport); |
1878 | ||
da121506 | 1879 | ret = s3c24xx_serial_init_port(ourport, pdev); |
b497549a | 1880 | if (ret < 0) |
8ad711a9 | 1881 | return ret; |
b497549a | 1882 | |
6f134c3c TB |
1883 | if (!s3c24xx_uart_drv.state) { |
1884 | ret = uart_register_driver(&s3c24xx_uart_drv); | |
1885 | if (ret < 0) { | |
1886 | pr_err("Failed to register Samsung UART driver\n"); | |
1887 | return ret; | |
1888 | } | |
1889 | } | |
1890 | ||
b497549a BD |
1891 | dbg("%s: adding port\n", __func__); |
1892 | uart_add_one_port(&s3c24xx_uart_drv, &ourport->port); | |
da121506 | 1893 | platform_set_drvdata(pdev, &ourport->port); |
b497549a | 1894 | |
0da3336f HS |
1895 | /* |
1896 | * Deactivate the clock enabled in s3c24xx_serial_init_port here, | |
1897 | * so that a potential re-enablement through the pm-callback overlaps | |
1898 | * and keeps the clock enabled in this case. | |
1899 | */ | |
1900 | clk_disable_unprepare(ourport->clk); | |
1901 | ||
30555476 BD |
1902 | ret = s3c24xx_serial_cpufreq_register(ourport); |
1903 | if (ret < 0) | |
da121506 | 1904 | dev_err(&pdev->dev, "failed to add cpufreq notifier\n"); |
30555476 | 1905 | |
926b7b51 KK |
1906 | probe_index++; |
1907 | ||
b497549a | 1908 | return 0; |
b497549a BD |
1909 | } |
1910 | ||
ae8d8a14 | 1911 | static int s3c24xx_serial_remove(struct platform_device *dev) |
b497549a BD |
1912 | { |
1913 | struct uart_port *port = s3c24xx_dev_to_port(&dev->dev); | |
1914 | ||
1915 | if (port) { | |
30555476 | 1916 | s3c24xx_serial_cpufreq_deregister(to_ourport(port)); |
b497549a BD |
1917 | uart_remove_one_port(&s3c24xx_uart_drv, port); |
1918 | } | |
1919 | ||
6f134c3c TB |
1920 | uart_unregister_driver(&s3c24xx_uart_drv); |
1921 | ||
b497549a BD |
1922 | return 0; |
1923 | } | |
1924 | ||
b497549a | 1925 | /* UART power management code */ |
aef7fe52 MH |
1926 | #ifdef CONFIG_PM_SLEEP |
1927 | static int s3c24xx_serial_suspend(struct device *dev) | |
b497549a | 1928 | { |
aef7fe52 | 1929 | struct uart_port *port = s3c24xx_dev_to_port(dev); |
b497549a BD |
1930 | |
1931 | if (port) | |
1932 | uart_suspend_port(&s3c24xx_uart_drv, port); | |
1933 | ||
1934 | return 0; | |
1935 | } | |
1936 | ||
aef7fe52 | 1937 | static int s3c24xx_serial_resume(struct device *dev) |
b497549a | 1938 | { |
aef7fe52 | 1939 | struct uart_port *port = s3c24xx_dev_to_port(dev); |
b497549a BD |
1940 | struct s3c24xx_uart_port *ourport = to_ourport(port); |
1941 | ||
1942 | if (port) { | |
9484b009 | 1943 | clk_prepare_enable(ourport->clk); |
b497549a | 1944 | s3c24xx_serial_resetport(port, s3c24xx_port_to_cfg(port)); |
9484b009 | 1945 | clk_disable_unprepare(ourport->clk); |
b497549a BD |
1946 | |
1947 | uart_resume_port(&s3c24xx_uart_drv, port); | |
1948 | } | |
1949 | ||
1950 | return 0; | |
1951 | } | |
aef7fe52 | 1952 | |
d09a7308 MS |
1953 | static int s3c24xx_serial_resume_noirq(struct device *dev) |
1954 | { | |
1955 | struct uart_port *port = s3c24xx_dev_to_port(dev); | |
a8a1781b | 1956 | struct s3c24xx_uart_port *ourport = to_ourport(port); |
d09a7308 MS |
1957 | |
1958 | if (port) { | |
1959 | /* restore IRQ mask */ | |
1960 | if (s3c24xx_serial_has_interrupt_mask(port)) { | |
1961 | unsigned int uintm = 0xf; | |
1962 | if (tx_enabled(port)) | |
1963 | uintm &= ~S3C64XX_UINTM_TXD_MSK; | |
1964 | if (rx_enabled(port)) | |
1965 | uintm &= ~S3C64XX_UINTM_RXD_MSK; | |
a8a1781b | 1966 | clk_prepare_enable(ourport->clk); |
d09a7308 | 1967 | wr_regl(port, S3C64XX_UINTM, uintm); |
a8a1781b | 1968 | clk_disable_unprepare(ourport->clk); |
d09a7308 MS |
1969 | } |
1970 | } | |
1971 | ||
1972 | return 0; | |
1973 | } | |
1974 | ||
aef7fe52 MH |
1975 | static const struct dev_pm_ops s3c24xx_serial_pm_ops = { |
1976 | .suspend = s3c24xx_serial_suspend, | |
1977 | .resume = s3c24xx_serial_resume, | |
d09a7308 | 1978 | .resume_noirq = s3c24xx_serial_resume_noirq, |
aef7fe52 | 1979 | }; |
b882fc1b KK |
1980 | #define SERIAL_SAMSUNG_PM_OPS (&s3c24xx_serial_pm_ops) |
1981 | ||
aef7fe52 | 1982 | #else /* !CONFIG_PM_SLEEP */ |
b882fc1b KK |
1983 | |
1984 | #define SERIAL_SAMSUNG_PM_OPS NULL | |
aef7fe52 | 1985 | #endif /* CONFIG_PM_SLEEP */ |
b497549a | 1986 | |
b497549a BD |
1987 | /* Console code */ |
1988 | ||
1989 | #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE | |
1990 | ||
1991 | static struct uart_port *cons_uart; | |
1992 | ||
1993 | static int | |
1994 | s3c24xx_serial_console_txrdy(struct uart_port *port, unsigned int ufcon) | |
1995 | { | |
1996 | struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port); | |
1997 | unsigned long ufstat, utrstat; | |
1998 | ||
1999 | if (ufcon & S3C2410_UFCON_FIFOMODE) { | |
9ddc5b6f | 2000 | /* fifo mode - check amount of data in fifo registers... */ |
b497549a BD |
2001 | |
2002 | ufstat = rd_regl(port, S3C2410_UFSTAT); | |
2003 | return (ufstat & info->tx_fifofull) ? 0 : 1; | |
2004 | } | |
2005 | ||
2006 | /* in non-fifo mode, we go and use the tx buffer empty */ | |
2007 | ||
2008 | utrstat = rd_regl(port, S3C2410_UTRSTAT); | |
2009 | return (utrstat & S3C2410_UTRSTAT_TXE) ? 1 : 0; | |
2010 | } | |
2011 | ||
38adbc54 MS |
2012 | static bool |
2013 | s3c24xx_port_configured(unsigned int ucon) | |
2014 | { | |
2015 | /* consider the serial port configured if the tx/rx mode set */ | |
2016 | return (ucon & 0xf) != 0; | |
2017 | } | |
2018 | ||
93b5c032 JP |
2019 | #ifdef CONFIG_CONSOLE_POLL |
2020 | /* | |
2021 | * Console polling routines for writing and reading from the uart while | |
2022 | * in an interrupt or debug context. | |
2023 | */ | |
2024 | ||
2025 | static int s3c24xx_serial_get_poll_char(struct uart_port *port) | |
2026 | { | |
2027 | struct s3c24xx_uart_port *ourport = to_ourport(port); | |
2028 | unsigned int ufstat; | |
2029 | ||
2030 | ufstat = rd_regl(port, S3C2410_UFSTAT); | |
2031 | if (s3c24xx_serial_rx_fifocnt(ourport, ufstat) == 0) | |
2032 | return NO_POLL_CHAR; | |
2033 | ||
2034 | return rd_regb(port, S3C2410_URXH); | |
2035 | } | |
2036 | ||
2037 | static void s3c24xx_serial_put_poll_char(struct uart_port *port, | |
2038 | unsigned char c) | |
2039 | { | |
bb7f09ba DA |
2040 | unsigned int ufcon = rd_regl(port, S3C2410_UFCON); |
2041 | unsigned int ucon = rd_regl(port, S3C2410_UCON); | |
38adbc54 MS |
2042 | |
2043 | /* not possible to xmit on unconfigured port */ | |
2044 | if (!s3c24xx_port_configured(ucon)) | |
2045 | return; | |
93b5c032 JP |
2046 | |
2047 | while (!s3c24xx_serial_console_txrdy(port, ufcon)) | |
2048 | cpu_relax(); | |
bb7f09ba | 2049 | wr_regb(port, S3C2410_UTXH, c); |
93b5c032 JP |
2050 | } |
2051 | ||
2052 | #endif /* CONFIG_CONSOLE_POLL */ | |
2053 | ||
b497549a BD |
2054 | static void |
2055 | s3c24xx_serial_console_putchar(struct uart_port *port, int ch) | |
2056 | { | |
bb7f09ba | 2057 | unsigned int ufcon = rd_regl(port, S3C2410_UFCON); |
38adbc54 | 2058 | |
b497549a | 2059 | while (!s3c24xx_serial_console_txrdy(port, ufcon)) |
f94b0572 | 2060 | cpu_relax(); |
bb7f09ba | 2061 | wr_regb(port, S3C2410_UTXH, ch); |
b497549a BD |
2062 | } |
2063 | ||
2064 | static void | |
2065 | s3c24xx_serial_console_write(struct console *co, const char *s, | |
2066 | unsigned int count) | |
2067 | { | |
ab88c8dc DA |
2068 | unsigned int ucon = rd_regl(cons_uart, S3C2410_UCON); |
2069 | ||
2070 | /* not possible to xmit on unconfigured port */ | |
2071 | if (!s3c24xx_port_configured(ucon)) | |
2072 | return; | |
2073 | ||
b497549a BD |
2074 | uart_console_write(cons_uart, s, count, s3c24xx_serial_console_putchar); |
2075 | } | |
2076 | ||
2077 | static void __init | |
2078 | s3c24xx_serial_get_options(struct uart_port *port, int *baud, | |
2079 | int *parity, int *bits) | |
2080 | { | |
b497549a BD |
2081 | struct clk *clk; |
2082 | unsigned int ulcon; | |
2083 | unsigned int ucon; | |
2084 | unsigned int ubrdiv; | |
2085 | unsigned long rate; | |
5f5a7a55 TA |
2086 | unsigned int clk_sel; |
2087 | char clk_name[MAX_CLK_NAME_LENGTH]; | |
b497549a BD |
2088 | |
2089 | ulcon = rd_regl(port, S3C2410_ULCON); | |
2090 | ucon = rd_regl(port, S3C2410_UCON); | |
2091 | ubrdiv = rd_regl(port, S3C2410_UBRDIV); | |
2092 | ||
2093 | dbg("s3c24xx_serial_get_options: port=%p\n" | |
2094 | "registers: ulcon=%08x, ucon=%08x, ubdriv=%08x\n", | |
2095 | port, ulcon, ucon, ubrdiv); | |
2096 | ||
38adbc54 | 2097 | if (s3c24xx_port_configured(ucon)) { |
b497549a BD |
2098 | switch (ulcon & S3C2410_LCON_CSMASK) { |
2099 | case S3C2410_LCON_CS5: | |
2100 | *bits = 5; | |
2101 | break; | |
2102 | case S3C2410_LCON_CS6: | |
2103 | *bits = 6; | |
2104 | break; | |
2105 | case S3C2410_LCON_CS7: | |
2106 | *bits = 7; | |
2107 | break; | |
b497549a | 2108 | case S3C2410_LCON_CS8: |
3bcce591 | 2109 | default: |
b497549a BD |
2110 | *bits = 8; |
2111 | break; | |
2112 | } | |
2113 | ||
2114 | switch (ulcon & S3C2410_LCON_PMASK) { | |
2115 | case S3C2410_LCON_PEVEN: | |
2116 | *parity = 'e'; | |
2117 | break; | |
2118 | ||
2119 | case S3C2410_LCON_PODD: | |
2120 | *parity = 'o'; | |
2121 | break; | |
2122 | ||
2123 | case S3C2410_LCON_PNONE: | |
2124 | default: | |
2125 | *parity = 'n'; | |
2126 | } | |
2127 | ||
2128 | /* now calculate the baud rate */ | |
2129 | ||
5f5a7a55 TA |
2130 | clk_sel = s3c24xx_serial_getsource(port); |
2131 | sprintf(clk_name, "clk_uart_baud%d", clk_sel); | |
b497549a | 2132 | |
5f5a7a55 | 2133 | clk = clk_get(port->dev, clk_name); |
7cd88831 | 2134 | if (!IS_ERR(clk)) |
5f5a7a55 | 2135 | rate = clk_get_rate(clk); |
b497549a BD |
2136 | else |
2137 | rate = 1; | |
2138 | ||
b497549a BD |
2139 | *baud = rate / (16 * (ubrdiv + 1)); |
2140 | dbg("calculated baud %d\n", *baud); | |
2141 | } | |
2142 | ||
2143 | } | |
2144 | ||
b497549a BD |
2145 | static int __init |
2146 | s3c24xx_serial_console_setup(struct console *co, char *options) | |
2147 | { | |
2148 | struct uart_port *port; | |
2149 | int baud = 9600; | |
2150 | int bits = 8; | |
2151 | int parity = 'n'; | |
2152 | int flow = 'n'; | |
2153 | ||
2154 | dbg("s3c24xx_serial_console_setup: co=%p (%d), %s\n", | |
2155 | co, co->index, options); | |
2156 | ||
2157 | /* is this a valid port */ | |
2158 | ||
03d5e77b | 2159 | if (co->index == -1 || co->index >= CONFIG_SERIAL_SAMSUNG_UARTS) |
b497549a BD |
2160 | co->index = 0; |
2161 | ||
2162 | port = &s3c24xx_serial_ports[co->index].port; | |
2163 | ||
2164 | /* is the port configured? */ | |
2165 | ||
ee430f16 TA |
2166 | if (port->mapbase == 0x0) |
2167 | return -ENODEV; | |
b497549a BD |
2168 | |
2169 | cons_uart = port; | |
2170 | ||
2171 | dbg("s3c24xx_serial_console_setup: port=%p (%d)\n", port, co->index); | |
2172 | ||
2173 | /* | |
2174 | * Check whether an invalid uart number has been specified, and | |
2175 | * if so, search for the first available port that does have | |
2176 | * console support. | |
2177 | */ | |
2178 | if (options) | |
2179 | uart_parse_options(options, &baud, &parity, &bits, &flow); | |
2180 | else | |
2181 | s3c24xx_serial_get_options(port, &baud, &parity, &bits); | |
2182 | ||
2183 | dbg("s3c24xx_serial_console_setup: baud %d\n", baud); | |
2184 | ||
2185 | return uart_set_options(port, co, baud, parity, bits, flow); | |
2186 | } | |
2187 | ||
b497549a BD |
2188 | static struct console s3c24xx_serial_console = { |
2189 | .name = S3C24XX_SERIAL_NAME, | |
2190 | .device = uart_console_device, | |
2191 | .flags = CON_PRINTBUFFER, | |
2192 | .index = -1, | |
2193 | .write = s3c24xx_serial_console_write, | |
5822a5df TA |
2194 | .setup = s3c24xx_serial_console_setup, |
2195 | .data = &s3c24xx_uart_drv, | |
b497549a | 2196 | }; |
da121506 TA |
2197 | #endif /* CONFIG_SERIAL_SAMSUNG_CONSOLE */ |
2198 | ||
2199 | #ifdef CONFIG_CPU_S3C2410 | |
2200 | static struct s3c24xx_serial_drv_data s3c2410_serial_drv_data = { | |
2201 | .info = &(struct s3c24xx_uart_info) { | |
2202 | .name = "Samsung S3C2410 UART", | |
2203 | .type = PORT_S3C2410, | |
2204 | .fifosize = 16, | |
2205 | .rx_fifomask = S3C2410_UFSTAT_RXMASK, | |
2206 | .rx_fifoshift = S3C2410_UFSTAT_RXSHIFT, | |
2207 | .rx_fifofull = S3C2410_UFSTAT_RXFULL, | |
2208 | .tx_fifofull = S3C2410_UFSTAT_TXFULL, | |
2209 | .tx_fifomask = S3C2410_UFSTAT_TXMASK, | |
2210 | .tx_fifoshift = S3C2410_UFSTAT_TXSHIFT, | |
2211 | .def_clk_sel = S3C2410_UCON_CLKSEL0, | |
2212 | .num_clks = 2, | |
2213 | .clksel_mask = S3C2410_UCON_CLKMASK, | |
2214 | .clksel_shift = S3C2410_UCON_CLKSHIFT, | |
2215 | }, | |
2216 | .def_cfg = &(struct s3c2410_uartcfg) { | |
2217 | .ucon = S3C2410_UCON_DEFAULT, | |
2218 | .ufcon = S3C2410_UFCON_DEFAULT, | |
2219 | }, | |
2220 | }; | |
2221 | #define S3C2410_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2410_serial_drv_data) | |
2222 | #else | |
2223 | #define S3C2410_SERIAL_DRV_DATA (kernel_ulong_t)NULL | |
2224 | #endif | |
b497549a | 2225 | |
da121506 TA |
2226 | #ifdef CONFIG_CPU_S3C2412 |
2227 | static struct s3c24xx_serial_drv_data s3c2412_serial_drv_data = { | |
2228 | .info = &(struct s3c24xx_uart_info) { | |
2229 | .name = "Samsung S3C2412 UART", | |
2230 | .type = PORT_S3C2412, | |
2231 | .fifosize = 64, | |
2232 | .has_divslot = 1, | |
2233 | .rx_fifomask = S3C2440_UFSTAT_RXMASK, | |
2234 | .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT, | |
2235 | .rx_fifofull = S3C2440_UFSTAT_RXFULL, | |
2236 | .tx_fifofull = S3C2440_UFSTAT_TXFULL, | |
2237 | .tx_fifomask = S3C2440_UFSTAT_TXMASK, | |
2238 | .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT, | |
2239 | .def_clk_sel = S3C2410_UCON_CLKSEL2, | |
2240 | .num_clks = 4, | |
2241 | .clksel_mask = S3C2412_UCON_CLKMASK, | |
2242 | .clksel_shift = S3C2412_UCON_CLKSHIFT, | |
2243 | }, | |
2244 | .def_cfg = &(struct s3c2410_uartcfg) { | |
2245 | .ucon = S3C2410_UCON_DEFAULT, | |
2246 | .ufcon = S3C2410_UFCON_DEFAULT, | |
2247 | }, | |
2248 | }; | |
2249 | #define S3C2412_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2412_serial_drv_data) | |
2250 | #else | |
2251 | #define S3C2412_SERIAL_DRV_DATA (kernel_ulong_t)NULL | |
2252 | #endif | |
b497549a | 2253 | |
da121506 | 2254 | #if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2416) || \ |
b26469a8 | 2255 | defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2442) |
da121506 TA |
2256 | static struct s3c24xx_serial_drv_data s3c2440_serial_drv_data = { |
2257 | .info = &(struct s3c24xx_uart_info) { | |
2258 | .name = "Samsung S3C2440 UART", | |
2259 | .type = PORT_S3C2440, | |
2260 | .fifosize = 64, | |
2261 | .has_divslot = 1, | |
2262 | .rx_fifomask = S3C2440_UFSTAT_RXMASK, | |
2263 | .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT, | |
2264 | .rx_fifofull = S3C2440_UFSTAT_RXFULL, | |
2265 | .tx_fifofull = S3C2440_UFSTAT_TXFULL, | |
2266 | .tx_fifomask = S3C2440_UFSTAT_TXMASK, | |
2267 | .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT, | |
2268 | .def_clk_sel = S3C2410_UCON_CLKSEL2, | |
2269 | .num_clks = 4, | |
2270 | .clksel_mask = S3C2412_UCON_CLKMASK, | |
2271 | .clksel_shift = S3C2412_UCON_CLKSHIFT, | |
2272 | }, | |
2273 | .def_cfg = &(struct s3c2410_uartcfg) { | |
2274 | .ucon = S3C2410_UCON_DEFAULT, | |
2275 | .ufcon = S3C2410_UFCON_DEFAULT, | |
2276 | }, | |
2277 | }; | |
2278 | #define S3C2440_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2440_serial_drv_data) | |
2279 | #else | |
2280 | #define S3C2440_SERIAL_DRV_DATA (kernel_ulong_t)NULL | |
2281 | #endif | |
b497549a | 2282 | |
953b53a7 | 2283 | #if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410) |
da121506 TA |
2284 | static struct s3c24xx_serial_drv_data s3c6400_serial_drv_data = { |
2285 | .info = &(struct s3c24xx_uart_info) { | |
2286 | .name = "Samsung S3C6400 UART", | |
2287 | .type = PORT_S3C6400, | |
2288 | .fifosize = 64, | |
2289 | .has_divslot = 1, | |
2290 | .rx_fifomask = S3C2440_UFSTAT_RXMASK, | |
2291 | .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT, | |
2292 | .rx_fifofull = S3C2440_UFSTAT_RXFULL, | |
2293 | .tx_fifofull = S3C2440_UFSTAT_TXFULL, | |
2294 | .tx_fifomask = S3C2440_UFSTAT_TXMASK, | |
2295 | .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT, | |
2296 | .def_clk_sel = S3C2410_UCON_CLKSEL2, | |
2297 | .num_clks = 4, | |
2298 | .clksel_mask = S3C6400_UCON_CLKMASK, | |
2299 | .clksel_shift = S3C6400_UCON_CLKSHIFT, | |
2300 | }, | |
2301 | .def_cfg = &(struct s3c2410_uartcfg) { | |
2302 | .ucon = S3C2410_UCON_DEFAULT, | |
2303 | .ufcon = S3C2410_UFCON_DEFAULT, | |
2304 | }, | |
2305 | }; | |
2306 | #define S3C6400_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c6400_serial_drv_data) | |
2307 | #else | |
2308 | #define S3C6400_SERIAL_DRV_DATA (kernel_ulong_t)NULL | |
2309 | #endif | |
b497549a | 2310 | |
da121506 TA |
2311 | #ifdef CONFIG_CPU_S5PV210 |
2312 | static struct s3c24xx_serial_drv_data s5pv210_serial_drv_data = { | |
2313 | .info = &(struct s3c24xx_uart_info) { | |
2314 | .name = "Samsung S5PV210 UART", | |
2315 | .type = PORT_S3C6400, | |
2316 | .has_divslot = 1, | |
2317 | .rx_fifomask = S5PV210_UFSTAT_RXMASK, | |
2318 | .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT, | |
2319 | .rx_fifofull = S5PV210_UFSTAT_RXFULL, | |
2320 | .tx_fifofull = S5PV210_UFSTAT_TXFULL, | |
2321 | .tx_fifomask = S5PV210_UFSTAT_TXMASK, | |
2322 | .tx_fifoshift = S5PV210_UFSTAT_TXSHIFT, | |
2323 | .def_clk_sel = S3C2410_UCON_CLKSEL0, | |
2324 | .num_clks = 2, | |
2325 | .clksel_mask = S5PV210_UCON_CLKMASK, | |
2326 | .clksel_shift = S5PV210_UCON_CLKSHIFT, | |
2327 | }, | |
2328 | .def_cfg = &(struct s3c2410_uartcfg) { | |
2329 | .ucon = S5PV210_UCON_DEFAULT, | |
2330 | .ufcon = S5PV210_UFCON_DEFAULT, | |
2331 | }, | |
2332 | .fifosize = { 256, 64, 16, 16 }, | |
2333 | }; | |
2334 | #define S5PV210_SERIAL_DRV_DATA ((kernel_ulong_t)&s5pv210_serial_drv_data) | |
2335 | #else | |
2336 | #define S5PV210_SERIAL_DRV_DATA (kernel_ulong_t)NULL | |
2337 | #endif | |
b497549a | 2338 | |
33f88136 | 2339 | #if defined(CONFIG_ARCH_EXYNOS) |
31ec77ac CC |
2340 | #define EXYNOS_COMMON_SERIAL_DRV_DATA \ |
2341 | .info = &(struct s3c24xx_uart_info) { \ | |
2342 | .name = "Samsung Exynos UART", \ | |
2343 | .type = PORT_S3C6400, \ | |
2344 | .has_divslot = 1, \ | |
2345 | .rx_fifomask = S5PV210_UFSTAT_RXMASK, \ | |
2346 | .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT, \ | |
2347 | .rx_fifofull = S5PV210_UFSTAT_RXFULL, \ | |
2348 | .tx_fifofull = S5PV210_UFSTAT_TXFULL, \ | |
2349 | .tx_fifomask = S5PV210_UFSTAT_TXMASK, \ | |
2350 | .tx_fifoshift = S5PV210_UFSTAT_TXSHIFT, \ | |
2351 | .def_clk_sel = S3C2410_UCON_CLKSEL0, \ | |
2352 | .num_clks = 1, \ | |
2353 | .clksel_mask = 0, \ | |
2354 | .clksel_shift = 0, \ | |
2355 | }, \ | |
2356 | .def_cfg = &(struct s3c2410_uartcfg) { \ | |
2357 | .ucon = S5PV210_UCON_DEFAULT, \ | |
2358 | .ufcon = S5PV210_UFCON_DEFAULT, \ | |
2359 | .has_fracval = 1, \ | |
2360 | } \ | |
2361 | ||
da121506 | 2362 | static struct s3c24xx_serial_drv_data exynos4210_serial_drv_data = { |
31ec77ac | 2363 | EXYNOS_COMMON_SERIAL_DRV_DATA, |
da121506 TA |
2364 | .fifosize = { 256, 64, 16, 16 }, |
2365 | }; | |
31ec77ac CC |
2366 | |
2367 | static struct s3c24xx_serial_drv_data exynos5433_serial_drv_data = { | |
2368 | EXYNOS_COMMON_SERIAL_DRV_DATA, | |
2369 | .fifosize = { 64, 256, 16, 256 }, | |
2370 | }; | |
2371 | ||
da121506 | 2372 | #define EXYNOS4210_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos4210_serial_drv_data) |
31ec77ac | 2373 | #define EXYNOS5433_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos5433_serial_drv_data) |
da121506 TA |
2374 | #else |
2375 | #define EXYNOS4210_SERIAL_DRV_DATA (kernel_ulong_t)NULL | |
31ec77ac | 2376 | #define EXYNOS5433_SERIAL_DRV_DATA (kernel_ulong_t)NULL |
da121506 | 2377 | #endif |
b497549a | 2378 | |
24ee4df1 | 2379 | static const struct platform_device_id s3c24xx_serial_driver_ids[] = { |
da121506 TA |
2380 | { |
2381 | .name = "s3c2410-uart", | |
2382 | .driver_data = S3C2410_SERIAL_DRV_DATA, | |
2383 | }, { | |
2384 | .name = "s3c2412-uart", | |
2385 | .driver_data = S3C2412_SERIAL_DRV_DATA, | |
2386 | }, { | |
2387 | .name = "s3c2440-uart", | |
2388 | .driver_data = S3C2440_SERIAL_DRV_DATA, | |
2389 | }, { | |
2390 | .name = "s3c6400-uart", | |
2391 | .driver_data = S3C6400_SERIAL_DRV_DATA, | |
2392 | }, { | |
2393 | .name = "s5pv210-uart", | |
2394 | .driver_data = S5PV210_SERIAL_DRV_DATA, | |
2395 | }, { | |
2396 | .name = "exynos4210-uart", | |
2397 | .driver_data = EXYNOS4210_SERIAL_DRV_DATA, | |
31ec77ac CC |
2398 | }, { |
2399 | .name = "exynos5433-uart", | |
2400 | .driver_data = EXYNOS5433_SERIAL_DRV_DATA, | |
da121506 TA |
2401 | }, |
2402 | { }, | |
2403 | }; | |
2404 | MODULE_DEVICE_TABLE(platform, s3c24xx_serial_driver_ids); | |
2405 | ||
26c919e1 TA |
2406 | #ifdef CONFIG_OF |
2407 | static const struct of_device_id s3c24xx_uart_dt_match[] = { | |
666ca0b9 HS |
2408 | { .compatible = "samsung,s3c2410-uart", |
2409 | .data = (void *)S3C2410_SERIAL_DRV_DATA }, | |
2410 | { .compatible = "samsung,s3c2412-uart", | |
2411 | .data = (void *)S3C2412_SERIAL_DRV_DATA }, | |
2412 | { .compatible = "samsung,s3c2440-uart", | |
2413 | .data = (void *)S3C2440_SERIAL_DRV_DATA }, | |
2414 | { .compatible = "samsung,s3c6400-uart", | |
2415 | .data = (void *)S3C6400_SERIAL_DRV_DATA }, | |
2416 | { .compatible = "samsung,s5pv210-uart", | |
2417 | .data = (void *)S5PV210_SERIAL_DRV_DATA }, | |
26c919e1 | 2418 | { .compatible = "samsung,exynos4210-uart", |
a169a888 | 2419 | .data = (void *)EXYNOS4210_SERIAL_DRV_DATA }, |
31ec77ac CC |
2420 | { .compatible = "samsung,exynos5433-uart", |
2421 | .data = (void *)EXYNOS5433_SERIAL_DRV_DATA }, | |
26c919e1 TA |
2422 | {}, |
2423 | }; | |
2424 | MODULE_DEVICE_TABLE(of, s3c24xx_uart_dt_match); | |
26c919e1 TA |
2425 | #endif |
2426 | ||
da121506 TA |
2427 | static struct platform_driver samsung_serial_driver = { |
2428 | .probe = s3c24xx_serial_probe, | |
2d47b716 | 2429 | .remove = s3c24xx_serial_remove, |
da121506 TA |
2430 | .id_table = s3c24xx_serial_driver_ids, |
2431 | .driver = { | |
2432 | .name = "samsung-uart", | |
da121506 | 2433 | .pm = SERIAL_SAMSUNG_PM_OPS, |
905f4ba2 | 2434 | .of_match_table = of_match_ptr(s3c24xx_uart_dt_match), |
da121506 TA |
2435 | }, |
2436 | }; | |
b497549a | 2437 | |
6f134c3c | 2438 | module_platform_driver(samsung_serial_driver); |
b497549a | 2439 | |
c3bda295 | 2440 | #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE |
b94ba032 TF |
2441 | /* |
2442 | * Early console. | |
2443 | */ | |
2444 | ||
2445 | struct samsung_early_console_data { | |
2446 | u32 txfull_mask; | |
2447 | }; | |
2448 | ||
2449 | static void samsung_early_busyuart(struct uart_port *port) | |
2450 | { | |
2451 | while (!(readl(port->membase + S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXFE)) | |
2452 | ; | |
2453 | } | |
2454 | ||
2455 | static void samsung_early_busyuart_fifo(struct uart_port *port) | |
2456 | { | |
2457 | struct samsung_early_console_data *data = port->private_data; | |
2458 | ||
2459 | while (readl(port->membase + S3C2410_UFSTAT) & data->txfull_mask) | |
2460 | ; | |
2461 | } | |
2462 | ||
2463 | static void samsung_early_putc(struct uart_port *port, int c) | |
2464 | { | |
2465 | if (readl(port->membase + S3C2410_UFCON) & S3C2410_UFCON_FIFOMODE) | |
2466 | samsung_early_busyuart_fifo(port); | |
2467 | else | |
2468 | samsung_early_busyuart(port); | |
2469 | ||
2470 | writeb(c, port->membase + S3C2410_UTXH); | |
2471 | } | |
2472 | ||
2473 | static void samsung_early_write(struct console *con, const char *s, unsigned n) | |
2474 | { | |
2475 | struct earlycon_device *dev = con->data; | |
2476 | ||
2477 | uart_console_write(&dev->port, s, n, samsung_early_putc); | |
2478 | } | |
2479 | ||
2480 | static int __init samsung_early_console_setup(struct earlycon_device *device, | |
2481 | const char *opt) | |
2482 | { | |
2483 | if (!device->port.membase) | |
2484 | return -ENODEV; | |
2485 | ||
2486 | device->con->write = samsung_early_write; | |
2487 | return 0; | |
2488 | } | |
2489 | ||
2490 | /* S3C2410 */ | |
2491 | static struct samsung_early_console_data s3c2410_early_console_data = { | |
2492 | .txfull_mask = S3C2410_UFSTAT_TXFULL, | |
2493 | }; | |
2494 | ||
2495 | static int __init s3c2410_early_console_setup(struct earlycon_device *device, | |
2496 | const char *opt) | |
2497 | { | |
2498 | device->port.private_data = &s3c2410_early_console_data; | |
2499 | return samsung_early_console_setup(device, opt); | |
2500 | } | |
2501 | OF_EARLYCON_DECLARE(s3c2410, "samsung,s3c2410-uart", | |
2502 | s3c2410_early_console_setup); | |
b94ba032 TF |
2503 | |
2504 | /* S3C2412, S3C2440, S3C64xx */ | |
2505 | static struct samsung_early_console_data s3c2440_early_console_data = { | |
2506 | .txfull_mask = S3C2440_UFSTAT_TXFULL, | |
2507 | }; | |
2508 | ||
2509 | static int __init s3c2440_early_console_setup(struct earlycon_device *device, | |
2510 | const char *opt) | |
2511 | { | |
2512 | device->port.private_data = &s3c2440_early_console_data; | |
2513 | return samsung_early_console_setup(device, opt); | |
2514 | } | |
2515 | OF_EARLYCON_DECLARE(s3c2412, "samsung,s3c2412-uart", | |
2516 | s3c2440_early_console_setup); | |
2517 | OF_EARLYCON_DECLARE(s3c2440, "samsung,s3c2440-uart", | |
2518 | s3c2440_early_console_setup); | |
2519 | OF_EARLYCON_DECLARE(s3c6400, "samsung,s3c6400-uart", | |
2520 | s3c2440_early_console_setup); | |
b94ba032 TF |
2521 | |
2522 | /* S5PV210, EXYNOS */ | |
2523 | static struct samsung_early_console_data s5pv210_early_console_data = { | |
2524 | .txfull_mask = S5PV210_UFSTAT_TXFULL, | |
2525 | }; | |
2526 | ||
2527 | static int __init s5pv210_early_console_setup(struct earlycon_device *device, | |
2528 | const char *opt) | |
2529 | { | |
2530 | device->port.private_data = &s5pv210_early_console_data; | |
2531 | return samsung_early_console_setup(device, opt); | |
2532 | } | |
2533 | OF_EARLYCON_DECLARE(s5pv210, "samsung,s5pv210-uart", | |
2534 | s5pv210_early_console_setup); | |
2535 | OF_EARLYCON_DECLARE(exynos4210, "samsung,exynos4210-uart", | |
2536 | s5pv210_early_console_setup); | |
c3bda295 | 2537 | #endif |
b94ba032 | 2538 | |
da121506 | 2539 | MODULE_ALIAS("platform:samsung-uart"); |
b497549a BD |
2540 | MODULE_DESCRIPTION("Samsung SoC Serial port driver"); |
2541 | MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>"); | |
2542 | MODULE_LICENSE("GPL v2"); |