Commit | Line | Data |
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e3b3d0f5 | 1 | // SPDX-License-Identifier: GPL-2.0+ |
1da177e4 | 2 | /* |
1da177e4 LT |
3 | * Driver for SA11x0 serial ports |
4 | * | |
5 | * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. | |
6 | * | |
7 | * Copyright (C) 2000 Deep Blue Solutions Ltd. | |
1da177e4 | 8 | */ |
1da177e4 | 9 | |
1da177e4 LT |
10 | #include <linux/module.h> |
11 | #include <linux/ioport.h> | |
12 | #include <linux/init.h> | |
13 | #include <linux/console.h> | |
14 | #include <linux/sysrq.h> | |
6920b5a7 | 15 | #include <linux/platform_data/sa11x0-serial.h> |
d052d1be | 16 | #include <linux/platform_device.h> |
1da177e4 LT |
17 | #include <linux/tty.h> |
18 | #include <linux/tty_flip.h> | |
19 | #include <linux/serial_core.h> | |
20 | #include <linux/serial.h> | |
99730225 | 21 | #include <linux/io.h> |
1da177e4 | 22 | |
1da177e4 | 23 | #include <asm/irq.h> |
a09e64fb | 24 | #include <mach/hardware.h> |
f314f33b | 25 | #include <mach/irqs.h> |
1da177e4 | 26 | |
d9d03e2c RK |
27 | #include "serial_mctrl_gpio.h" |
28 | ||
1da177e4 LT |
29 | /* We've been assigned a range on the "Low-density serial ports" major */ |
30 | #define SERIAL_SA1100_MAJOR 204 | |
31 | #define MINOR_START 5 | |
32 | ||
33 | #define NR_PORTS 3 | |
34 | ||
35 | #define SA1100_ISR_PASS_LIMIT 256 | |
36 | ||
37 | /* | |
38 | * Convert from ignore_status_mask or read_status_mask to UTSR[01] | |
39 | */ | |
40 | #define SM_TO_UTSR0(x) ((x) & 0xff) | |
41 | #define SM_TO_UTSR1(x) ((x) >> 8) | |
42 | #define UTSR0_TO_SM(x) ((x)) | |
43 | #define UTSR1_TO_SM(x) ((x) << 8) | |
44 | ||
45 | #define UART_GET_UTCR0(sport) __raw_readl((sport)->port.membase + UTCR0) | |
46 | #define UART_GET_UTCR1(sport) __raw_readl((sport)->port.membase + UTCR1) | |
47 | #define UART_GET_UTCR2(sport) __raw_readl((sport)->port.membase + UTCR2) | |
48 | #define UART_GET_UTCR3(sport) __raw_readl((sport)->port.membase + UTCR3) | |
49 | #define UART_GET_UTSR0(sport) __raw_readl((sport)->port.membase + UTSR0) | |
50 | #define UART_GET_UTSR1(sport) __raw_readl((sport)->port.membase + UTSR1) | |
51 | #define UART_GET_CHAR(sport) __raw_readl((sport)->port.membase + UTDR) | |
52 | ||
53 | #define UART_PUT_UTCR0(sport,v) __raw_writel((v),(sport)->port.membase + UTCR0) | |
54 | #define UART_PUT_UTCR1(sport,v) __raw_writel((v),(sport)->port.membase + UTCR1) | |
55 | #define UART_PUT_UTCR2(sport,v) __raw_writel((v),(sport)->port.membase + UTCR2) | |
56 | #define UART_PUT_UTCR3(sport,v) __raw_writel((v),(sport)->port.membase + UTCR3) | |
57 | #define UART_PUT_UTSR0(sport,v) __raw_writel((v),(sport)->port.membase + UTSR0) | |
58 | #define UART_PUT_UTSR1(sport,v) __raw_writel((v),(sport)->port.membase + UTSR1) | |
59 | #define UART_PUT_CHAR(sport,v) __raw_writel((v),(sport)->port.membase + UTDR) | |
60 | ||
61 | /* | |
62 | * This is the size of our serial port register set. | |
63 | */ | |
64 | #define UART_PORT_SIZE 0x24 | |
65 | ||
66 | /* | |
67 | * This determines how often we check the modem status signals | |
68 | * for any change. They generally aren't connected to an IRQ | |
69 | * so we have to poll them. We also check immediately before | |
70 | * filling the TX fifo incase CTS has been dropped. | |
71 | */ | |
72 | #define MCTRL_TIMEOUT (250*HZ/1000) | |
73 | ||
74 | struct sa1100_port { | |
75 | struct uart_port port; | |
76 | struct timer_list timer; | |
77 | unsigned int old_status; | |
d9d03e2c | 78 | struct mctrl_gpios *gpios; |
1da177e4 LT |
79 | }; |
80 | ||
81 | /* | |
82 | * Handle any change of modem status signal since we were last called. | |
83 | */ | |
84 | static void sa1100_mctrl_check(struct sa1100_port *sport) | |
85 | { | |
86 | unsigned int status, changed; | |
87 | ||
88 | status = sport->port.ops->get_mctrl(&sport->port); | |
89 | changed = status ^ sport->old_status; | |
90 | ||
91 | if (changed == 0) | |
92 | return; | |
93 | ||
94 | sport->old_status = status; | |
95 | ||
96 | if (changed & TIOCM_RI) | |
97 | sport->port.icount.rng++; | |
98 | if (changed & TIOCM_DSR) | |
99 | sport->port.icount.dsr++; | |
100 | if (changed & TIOCM_CAR) | |
101 | uart_handle_dcd_change(&sport->port, status & TIOCM_CAR); | |
102 | if (changed & TIOCM_CTS) | |
103 | uart_handle_cts_change(&sport->port, status & TIOCM_CTS); | |
104 | ||
bdc04e31 | 105 | wake_up_interruptible(&sport->port.state->port.delta_msr_wait); |
1da177e4 LT |
106 | } |
107 | ||
108 | /* | |
109 | * This is our per-port timeout handler, for checking the | |
110 | * modem status signals. | |
111 | */ | |
e99e88a9 | 112 | static void sa1100_timeout(struct timer_list *t) |
1da177e4 | 113 | { |
e99e88a9 | 114 | struct sa1100_port *sport = from_timer(sport, t, timer); |
1da177e4 LT |
115 | unsigned long flags; |
116 | ||
ebd2c8f6 | 117 | if (sport->port.state) { |
b9cedc02 | 118 | uart_port_lock_irqsave(&sport->port, &flags); |
1da177e4 | 119 | sa1100_mctrl_check(sport); |
b9cedc02 | 120 | uart_port_unlock_irqrestore(&sport->port, flags); |
1da177e4 LT |
121 | |
122 | mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT); | |
123 | } | |
124 | } | |
125 | ||
126 | /* | |
127 | * interrupts disabled on entry | |
128 | */ | |
b129a8cc | 129 | static void sa1100_stop_tx(struct uart_port *port) |
1da177e4 | 130 | { |
c9db776b FF |
131 | struct sa1100_port *sport = |
132 | container_of(port, struct sa1100_port, port); | |
1da177e4 LT |
133 | u32 utcr3; |
134 | ||
135 | utcr3 = UART_GET_UTCR3(sport); | |
136 | UART_PUT_UTCR3(sport, utcr3 & ~UTCR3_TIE); | |
137 | sport->port.read_status_mask &= ~UTSR0_TO_SM(UTSR0_TFS); | |
138 | } | |
139 | ||
140 | /* | |
270c7a72 | 141 | * port locked and interrupts disabled |
1da177e4 | 142 | */ |
b129a8cc | 143 | static void sa1100_start_tx(struct uart_port *port) |
1da177e4 | 144 | { |
c9db776b FF |
145 | struct sa1100_port *sport = |
146 | container_of(port, struct sa1100_port, port); | |
1da177e4 LT |
147 | u32 utcr3; |
148 | ||
1da177e4 LT |
149 | utcr3 = UART_GET_UTCR3(sport); |
150 | sport->port.read_status_mask |= UTSR0_TO_SM(UTSR0_TFS); | |
151 | UART_PUT_UTCR3(sport, utcr3 | UTCR3_TIE); | |
1da177e4 LT |
152 | } |
153 | ||
154 | /* | |
155 | * Interrupts enabled | |
156 | */ | |
157 | static void sa1100_stop_rx(struct uart_port *port) | |
158 | { | |
c9db776b FF |
159 | struct sa1100_port *sport = |
160 | container_of(port, struct sa1100_port, port); | |
1da177e4 LT |
161 | u32 utcr3; |
162 | ||
163 | utcr3 = UART_GET_UTCR3(sport); | |
164 | UART_PUT_UTCR3(sport, utcr3 & ~UTCR3_RIE); | |
165 | } | |
166 | ||
167 | /* | |
168 | * Set the modem control timer to fire immediately. | |
169 | */ | |
170 | static void sa1100_enable_ms(struct uart_port *port) | |
171 | { | |
c9db776b FF |
172 | struct sa1100_port *sport = |
173 | container_of(port, struct sa1100_port, port); | |
1da177e4 LT |
174 | |
175 | mod_timer(&sport->timer, jiffies); | |
d9d03e2c RK |
176 | |
177 | mctrl_gpio_enable_ms(sport->gpios); | |
1da177e4 LT |
178 | } |
179 | ||
180 | static void | |
7d12e780 | 181 | sa1100_rx_chars(struct sa1100_port *sport) |
1da177e4 | 182 | { |
fd2b55f8 JS |
183 | unsigned int status; |
184 | u8 ch, flg; | |
1da177e4 LT |
185 | |
186 | status = UTSR1_TO_SM(UART_GET_UTSR1(sport)) | | |
187 | UTSR0_TO_SM(UART_GET_UTSR0(sport)); | |
188 | while (status & UTSR1_TO_SM(UTSR1_RNE)) { | |
189 | ch = UART_GET_CHAR(sport); | |
190 | ||
1da177e4 LT |
191 | sport->port.icount.rx++; |
192 | ||
193 | flg = TTY_NORMAL; | |
194 | ||
195 | /* | |
196 | * note that the error handling code is | |
197 | * out of the main execution path | |
198 | */ | |
2a9604b8 RK |
199 | if (status & UTSR1_TO_SM(UTSR1_PRE | UTSR1_FRE | UTSR1_ROR)) { |
200 | if (status & UTSR1_TO_SM(UTSR1_PRE)) | |
201 | sport->port.icount.parity++; | |
202 | else if (status & UTSR1_TO_SM(UTSR1_FRE)) | |
203 | sport->port.icount.frame++; | |
204 | if (status & UTSR1_TO_SM(UTSR1_ROR)) | |
205 | sport->port.icount.overrun++; | |
206 | ||
207 | status &= sport->port.read_status_mask; | |
208 | ||
209 | if (status & UTSR1_TO_SM(UTSR1_PRE)) | |
210 | flg = TTY_PARITY; | |
211 | else if (status & UTSR1_TO_SM(UTSR1_FRE)) | |
212 | flg = TTY_FRAME; | |
213 | ||
2a9604b8 | 214 | sport->port.sysrq = 0; |
2a9604b8 | 215 | } |
1da177e4 | 216 | |
7d12e780 | 217 | if (uart_handle_sysrq_char(&sport->port, ch)) |
1da177e4 LT |
218 | goto ignore_char; |
219 | ||
05ab3014 | 220 | uart_insert_char(&sport->port, status, UTSR1_TO_SM(UTSR1_ROR), ch, flg); |
2a9604b8 | 221 | |
1da177e4 LT |
222 | ignore_char: |
223 | status = UTSR1_TO_SM(UART_GET_UTSR1(sport)) | | |
224 | UTSR0_TO_SM(UART_GET_UTSR0(sport)); | |
225 | } | |
53e0e670 | 226 | |
2e124b4a | 227 | tty_flip_buffer_push(&sport->port.state->port); |
1da177e4 LT |
228 | } |
229 | ||
230 | static void sa1100_tx_chars(struct sa1100_port *sport) | |
231 | { | |
2d141e68 | 232 | u8 ch; |
1da177e4 LT |
233 | |
234 | /* | |
235 | * Check the modem control lines before | |
236 | * transmitting anything. | |
237 | */ | |
238 | sa1100_mctrl_check(sport); | |
239 | ||
2d141e68 JSS |
240 | uart_port_tx(&sport->port, ch, |
241 | UART_GET_UTSR1(sport) & UTSR1_TNF, | |
242 | UART_PUT_CHAR(sport, ch)); | |
1da177e4 LT |
243 | } |
244 | ||
7d12e780 | 245 | static irqreturn_t sa1100_int(int irq, void *dev_id) |
1da177e4 LT |
246 | { |
247 | struct sa1100_port *sport = dev_id; | |
248 | unsigned int status, pass_counter = 0; | |
249 | ||
b9cedc02 | 250 | uart_port_lock(&sport->port); |
1da177e4 LT |
251 | status = UART_GET_UTSR0(sport); |
252 | status &= SM_TO_UTSR0(sport->port.read_status_mask) | ~UTSR0_TFS; | |
253 | do { | |
254 | if (status & (UTSR0_RFS | UTSR0_RID)) { | |
255 | /* Clear the receiver idle bit, if set */ | |
256 | if (status & UTSR0_RID) | |
257 | UART_PUT_UTSR0(sport, UTSR0_RID); | |
7d12e780 | 258 | sa1100_rx_chars(sport); |
1da177e4 LT |
259 | } |
260 | ||
261 | /* Clear the relevant break bits */ | |
262 | if (status & (UTSR0_RBB | UTSR0_REB)) | |
263 | UART_PUT_UTSR0(sport, status & (UTSR0_RBB | UTSR0_REB)); | |
264 | ||
265 | if (status & UTSR0_RBB) | |
266 | sport->port.icount.brk++; | |
267 | ||
268 | if (status & UTSR0_REB) | |
269 | uart_handle_break(&sport->port); | |
270 | ||
271 | if (status & UTSR0_TFS) | |
272 | sa1100_tx_chars(sport); | |
273 | if (pass_counter++ > SA1100_ISR_PASS_LIMIT) | |
274 | break; | |
275 | status = UART_GET_UTSR0(sport); | |
276 | status &= SM_TO_UTSR0(sport->port.read_status_mask) | | |
277 | ~UTSR0_TFS; | |
278 | } while (status & (UTSR0_TFS | UTSR0_RFS | UTSR0_RID)); | |
b9cedc02 | 279 | uart_port_unlock(&sport->port); |
1da177e4 LT |
280 | |
281 | return IRQ_HANDLED; | |
282 | } | |
283 | ||
284 | /* | |
285 | * Return TIOCSER_TEMT when transmitter is not busy. | |
286 | */ | |
287 | static unsigned int sa1100_tx_empty(struct uart_port *port) | |
288 | { | |
c9db776b FF |
289 | struct sa1100_port *sport = |
290 | container_of(port, struct sa1100_port, port); | |
1da177e4 LT |
291 | |
292 | return UART_GET_UTSR1(sport) & UTSR1_TBY ? 0 : TIOCSER_TEMT; | |
293 | } | |
294 | ||
295 | static unsigned int sa1100_get_mctrl(struct uart_port *port) | |
296 | { | |
d9d03e2c RK |
297 | struct sa1100_port *sport = |
298 | container_of(port, struct sa1100_port, port); | |
299 | int ret = TIOCM_CTS | TIOCM_DSR | TIOCM_CAR; | |
300 | ||
301 | mctrl_gpio_get(sport->gpios, &ret); | |
302 | ||
303 | return ret; | |
1da177e4 LT |
304 | } |
305 | ||
306 | static void sa1100_set_mctrl(struct uart_port *port, unsigned int mctrl) | |
307 | { | |
d9d03e2c RK |
308 | struct sa1100_port *sport = |
309 | container_of(port, struct sa1100_port, port); | |
310 | ||
311 | mctrl_gpio_set(sport->gpios, mctrl); | |
1da177e4 LT |
312 | } |
313 | ||
314 | /* | |
315 | * Interrupts always disabled. | |
316 | */ | |
317 | static void sa1100_break_ctl(struct uart_port *port, int break_state) | |
318 | { | |
c9db776b FF |
319 | struct sa1100_port *sport = |
320 | container_of(port, struct sa1100_port, port); | |
1da177e4 LT |
321 | unsigned long flags; |
322 | unsigned int utcr3; | |
323 | ||
b9cedc02 | 324 | uart_port_lock_irqsave(&sport->port, &flags); |
1da177e4 LT |
325 | utcr3 = UART_GET_UTCR3(sport); |
326 | if (break_state == -1) | |
327 | utcr3 |= UTCR3_BRK; | |
328 | else | |
329 | utcr3 &= ~UTCR3_BRK; | |
330 | UART_PUT_UTCR3(sport, utcr3); | |
b9cedc02 | 331 | uart_port_unlock_irqrestore(&sport->port, flags); |
1da177e4 LT |
332 | } |
333 | ||
334 | static int sa1100_startup(struct uart_port *port) | |
335 | { | |
c9db776b FF |
336 | struct sa1100_port *sport = |
337 | container_of(port, struct sa1100_port, port); | |
1da177e4 LT |
338 | int retval; |
339 | ||
340 | /* | |
341 | * Allocate the IRQ | |
342 | */ | |
343 | retval = request_irq(sport->port.irq, sa1100_int, 0, | |
344 | "sa11x0-uart", sport); | |
345 | if (retval) | |
346 | return retval; | |
347 | ||
348 | /* | |
349 | * Finally, clear and enable interrupts | |
350 | */ | |
351 | UART_PUT_UTSR0(sport, -1); | |
352 | UART_PUT_UTCR3(sport, UTCR3_RXE | UTCR3_TXE | UTCR3_RIE); | |
353 | ||
354 | /* | |
355 | * Enable modem status interrupts | |
356 | */ | |
b9cedc02 | 357 | uart_port_lock_irq(&sport->port); |
1da177e4 | 358 | sa1100_enable_ms(&sport->port); |
b9cedc02 | 359 | uart_port_unlock_irq(&sport->port); |
1da177e4 LT |
360 | |
361 | return 0; | |
362 | } | |
363 | ||
364 | static void sa1100_shutdown(struct uart_port *port) | |
365 | { | |
c9db776b FF |
366 | struct sa1100_port *sport = |
367 | container_of(port, struct sa1100_port, port); | |
1da177e4 LT |
368 | |
369 | /* | |
370 | * Stop our timer. | |
371 | */ | |
372 | del_timer_sync(&sport->timer); | |
373 | ||
374 | /* | |
375 | * Free the interrupt | |
376 | */ | |
377 | free_irq(sport->port.irq, sport); | |
378 | ||
379 | /* | |
380 | * Disable all interrupts, port and break condition. | |
381 | */ | |
382 | UART_PUT_UTCR3(sport, 0); | |
383 | } | |
384 | ||
385 | static void | |
606d099c | 386 | sa1100_set_termios(struct uart_port *port, struct ktermios *termios, |
bec5b814 | 387 | const struct ktermios *old) |
1da177e4 | 388 | { |
c9db776b FF |
389 | struct sa1100_port *sport = |
390 | container_of(port, struct sa1100_port, port); | |
1da177e4 LT |
391 | unsigned long flags; |
392 | unsigned int utcr0, old_utcr3, baud, quot; | |
393 | unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8; | |
394 | ||
395 | /* | |
396 | * We only support CS7 and CS8. | |
397 | */ | |
398 | while ((termios->c_cflag & CSIZE) != CS7 && | |
399 | (termios->c_cflag & CSIZE) != CS8) { | |
400 | termios->c_cflag &= ~CSIZE; | |
401 | termios->c_cflag |= old_csize; | |
402 | old_csize = CS8; | |
403 | } | |
404 | ||
405 | if ((termios->c_cflag & CSIZE) == CS8) | |
406 | utcr0 = UTCR0_DSS; | |
407 | else | |
408 | utcr0 = 0; | |
409 | ||
410 | if (termios->c_cflag & CSTOPB) | |
411 | utcr0 |= UTCR0_SBS; | |
412 | if (termios->c_cflag & PARENB) { | |
413 | utcr0 |= UTCR0_PE; | |
414 | if (!(termios->c_cflag & PARODD)) | |
415 | utcr0 |= UTCR0_OES; | |
416 | } | |
417 | ||
418 | /* | |
419 | * Ask the core to calculate the divisor for us. | |
420 | */ | |
421 | baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16); | |
422 | quot = uart_get_divisor(port, baud); | |
423 | ||
62b2caef DZ |
424 | del_timer_sync(&sport->timer); |
425 | ||
b9cedc02 | 426 | uart_port_lock_irqsave(&sport->port, &flags); |
1da177e4 LT |
427 | |
428 | sport->port.read_status_mask &= UTSR0_TO_SM(UTSR0_TFS); | |
429 | sport->port.read_status_mask |= UTSR1_TO_SM(UTSR1_ROR); | |
430 | if (termios->c_iflag & INPCK) | |
431 | sport->port.read_status_mask |= | |
432 | UTSR1_TO_SM(UTSR1_FRE | UTSR1_PRE); | |
433 | if (termios->c_iflag & (BRKINT | PARMRK)) | |
434 | sport->port.read_status_mask |= | |
435 | UTSR0_TO_SM(UTSR0_RBB | UTSR0_REB); | |
436 | ||
437 | /* | |
438 | * Characters to ignore | |
439 | */ | |
440 | sport->port.ignore_status_mask = 0; | |
441 | if (termios->c_iflag & IGNPAR) | |
442 | sport->port.ignore_status_mask |= | |
443 | UTSR1_TO_SM(UTSR1_FRE | UTSR1_PRE); | |
444 | if (termios->c_iflag & IGNBRK) { | |
445 | sport->port.ignore_status_mask |= | |
446 | UTSR0_TO_SM(UTSR0_RBB | UTSR0_REB); | |
447 | /* | |
448 | * If we're ignoring parity and break indicators, | |
449 | * ignore overruns too (for real raw support). | |
450 | */ | |
451 | if (termios->c_iflag & IGNPAR) | |
452 | sport->port.ignore_status_mask |= | |
453 | UTSR1_TO_SM(UTSR1_ROR); | |
454 | } | |
455 | ||
1da177e4 LT |
456 | /* |
457 | * Update the per-port timeout. | |
458 | */ | |
459 | uart_update_timeout(port, termios->c_cflag, baud); | |
460 | ||
461 | /* | |
462 | * disable interrupts and drain transmitter | |
463 | */ | |
464 | old_utcr3 = UART_GET_UTCR3(sport); | |
465 | UART_PUT_UTCR3(sport, old_utcr3 & ~(UTCR3_RIE | UTCR3_TIE)); | |
466 | ||
467 | while (UART_GET_UTSR1(sport) & UTSR1_TBY) | |
468 | barrier(); | |
469 | ||
470 | /* then, disable everything */ | |
471 | UART_PUT_UTCR3(sport, 0); | |
472 | ||
473 | /* set the parity, stop bits and data size */ | |
474 | UART_PUT_UTCR0(sport, utcr0); | |
475 | ||
476 | /* set the baud rate */ | |
477 | quot -= 1; | |
478 | UART_PUT_UTCR1(sport, ((quot & 0xf00) >> 8)); | |
479 | UART_PUT_UTCR2(sport, (quot & 0xff)); | |
480 | ||
481 | UART_PUT_UTSR0(sport, -1); | |
482 | ||
483 | UART_PUT_UTCR3(sport, old_utcr3); | |
484 | ||
485 | if (UART_ENABLE_MS(&sport->port, termios->c_cflag)) | |
486 | sa1100_enable_ms(&sport->port); | |
487 | ||
b9cedc02 | 488 | uart_port_unlock_irqrestore(&sport->port, flags); |
1da177e4 LT |
489 | } |
490 | ||
491 | static const char *sa1100_type(struct uart_port *port) | |
492 | { | |
c9db776b FF |
493 | struct sa1100_port *sport = |
494 | container_of(port, struct sa1100_port, port); | |
1da177e4 LT |
495 | |
496 | return sport->port.type == PORT_SA1100 ? "SA1100" : NULL; | |
497 | } | |
498 | ||
499 | /* | |
500 | * Release the memory region(s) being used by 'port'. | |
501 | */ | |
502 | static void sa1100_release_port(struct uart_port *port) | |
503 | { | |
c9db776b FF |
504 | struct sa1100_port *sport = |
505 | container_of(port, struct sa1100_port, port); | |
1da177e4 LT |
506 | |
507 | release_mem_region(sport->port.mapbase, UART_PORT_SIZE); | |
508 | } | |
509 | ||
510 | /* | |
511 | * Request the memory region(s) being used by 'port'. | |
512 | */ | |
513 | static int sa1100_request_port(struct uart_port *port) | |
514 | { | |
c9db776b FF |
515 | struct sa1100_port *sport = |
516 | container_of(port, struct sa1100_port, port); | |
1da177e4 LT |
517 | |
518 | return request_mem_region(sport->port.mapbase, UART_PORT_SIZE, | |
519 | "sa11x0-uart") != NULL ? 0 : -EBUSY; | |
520 | } | |
521 | ||
522 | /* | |
523 | * Configure/autoconfigure the port. | |
524 | */ | |
525 | static void sa1100_config_port(struct uart_port *port, int flags) | |
526 | { | |
c9db776b FF |
527 | struct sa1100_port *sport = |
528 | container_of(port, struct sa1100_port, port); | |
1da177e4 LT |
529 | |
530 | if (flags & UART_CONFIG_TYPE && | |
531 | sa1100_request_port(&sport->port) == 0) | |
532 | sport->port.type = PORT_SA1100; | |
533 | } | |
534 | ||
535 | /* | |
536 | * Verify the new serial_struct (for TIOCSSERIAL). | |
537 | * The only change we allow are to the flags and type, and | |
538 | * even then only between PORT_SA1100 and PORT_UNKNOWN | |
539 | */ | |
540 | static int | |
541 | sa1100_verify_port(struct uart_port *port, struct serial_struct *ser) | |
542 | { | |
c9db776b FF |
543 | struct sa1100_port *sport = |
544 | container_of(port, struct sa1100_port, port); | |
1da177e4 LT |
545 | int ret = 0; |
546 | ||
547 | if (ser->type != PORT_UNKNOWN && ser->type != PORT_SA1100) | |
548 | ret = -EINVAL; | |
549 | if (sport->port.irq != ser->irq) | |
550 | ret = -EINVAL; | |
551 | if (ser->io_type != SERIAL_IO_MEM) | |
552 | ret = -EINVAL; | |
553 | if (sport->port.uartclk / 16 != ser->baud_base) | |
554 | ret = -EINVAL; | |
555 | if ((void *)sport->port.mapbase != ser->iomem_base) | |
556 | ret = -EINVAL; | |
557 | if (sport->port.iobase != ser->port) | |
558 | ret = -EINVAL; | |
559 | if (ser->hub6 != 0) | |
560 | ret = -EINVAL; | |
561 | return ret; | |
562 | } | |
563 | ||
564 | static struct uart_ops sa1100_pops = { | |
565 | .tx_empty = sa1100_tx_empty, | |
566 | .set_mctrl = sa1100_set_mctrl, | |
567 | .get_mctrl = sa1100_get_mctrl, | |
568 | .stop_tx = sa1100_stop_tx, | |
569 | .start_tx = sa1100_start_tx, | |
570 | .stop_rx = sa1100_stop_rx, | |
571 | .enable_ms = sa1100_enable_ms, | |
572 | .break_ctl = sa1100_break_ctl, | |
573 | .startup = sa1100_startup, | |
574 | .shutdown = sa1100_shutdown, | |
575 | .set_termios = sa1100_set_termios, | |
576 | .type = sa1100_type, | |
577 | .release_port = sa1100_release_port, | |
578 | .request_port = sa1100_request_port, | |
579 | .config_port = sa1100_config_port, | |
580 | .verify_port = sa1100_verify_port, | |
581 | }; | |
582 | ||
583 | static struct sa1100_port sa1100_ports[NR_PORTS]; | |
584 | ||
585 | /* | |
586 | * Setup the SA1100 serial ports. Note that we don't include the IrDA | |
587 | * port here since we have our own SIR/FIR driver (see drivers/net/irda) | |
588 | * | |
589 | * Note also that we support "console=ttySAx" where "x" is either 0 or 1. | |
590 | * Which serial port this ends up being depends on the machine you're | |
591 | * running this kernel on. I'm not convinced that this is a good idea, | |
592 | * but that's the way it traditionally works. | |
593 | * | |
594 | * Note that NanoEngine UART3 becomes UART2, and UART2 is no longer | |
595 | * used here. | |
596 | */ | |
597 | static void __init sa1100_init_ports(void) | |
598 | { | |
599 | static int first = 1; | |
600 | int i; | |
601 | ||
602 | if (!first) | |
603 | return; | |
604 | first = 0; | |
605 | ||
606 | for (i = 0; i < NR_PORTS; i++) { | |
607 | sa1100_ports[i].port.uartclk = 3686400; | |
608 | sa1100_ports[i].port.ops = &sa1100_pops; | |
609 | sa1100_ports[i].port.fifosize = 8; | |
610 | sa1100_ports[i].port.line = i; | |
9b4a1617 | 611 | sa1100_ports[i].port.iotype = UPIO_MEM; |
e99e88a9 | 612 | timer_setup(&sa1100_ports[i].timer, sa1100_timeout, 0); |
1da177e4 LT |
613 | } |
614 | ||
615 | /* | |
616 | * make transmit lines outputs, so that when the port | |
617 | * is closed, the output is in the MARK state. | |
618 | */ | |
619 | PPDR |= PPC_TXD1 | PPC_TXD3; | |
620 | PPSR |= PPC_TXD1 | PPC_TXD3; | |
621 | } | |
622 | ||
9671f099 | 623 | void sa1100_register_uart_fns(struct sa1100_port_fns *fns) |
1da177e4 LT |
624 | { |
625 | if (fns->get_mctrl) | |
626 | sa1100_pops.get_mctrl = fns->get_mctrl; | |
627 | if (fns->set_mctrl) | |
628 | sa1100_pops.set_mctrl = fns->set_mctrl; | |
629 | ||
630 | sa1100_pops.pm = fns->pm; | |
adedb750 LW |
631 | /* |
632 | * FIXME: fns->set_wake is unused - this should be called from | |
633 | * the suspend() callback if device_may_wakeup(dev)) is set. | |
634 | */ | |
1da177e4 LT |
635 | } |
636 | ||
637 | void __init sa1100_register_uart(int idx, int port) | |
638 | { | |
639 | if (idx >= NR_PORTS) { | |
71cc2c21 | 640 | printk(KERN_ERR "%s: bad index number %d\n", __func__, idx); |
1da177e4 LT |
641 | return; |
642 | } | |
643 | ||
644 | switch (port) { | |
645 | case 1: | |
646 | sa1100_ports[idx].port.membase = (void __iomem *)&Ser1UTCR0; | |
647 | sa1100_ports[idx].port.mapbase = _Ser1UTCR0; | |
648 | sa1100_ports[idx].port.irq = IRQ_Ser1UART; | |
ce8337cb | 649 | sa1100_ports[idx].port.flags = UPF_BOOT_AUTOCONF; |
1da177e4 LT |
650 | break; |
651 | ||
652 | case 2: | |
653 | sa1100_ports[idx].port.membase = (void __iomem *)&Ser2UTCR0; | |
654 | sa1100_ports[idx].port.mapbase = _Ser2UTCR0; | |
655 | sa1100_ports[idx].port.irq = IRQ_Ser2ICP; | |
ce8337cb | 656 | sa1100_ports[idx].port.flags = UPF_BOOT_AUTOCONF; |
1da177e4 LT |
657 | break; |
658 | ||
659 | case 3: | |
660 | sa1100_ports[idx].port.membase = (void __iomem *)&Ser3UTCR0; | |
661 | sa1100_ports[idx].port.mapbase = _Ser3UTCR0; | |
662 | sa1100_ports[idx].port.irq = IRQ_Ser3UART; | |
ce8337cb | 663 | sa1100_ports[idx].port.flags = UPF_BOOT_AUTOCONF; |
1da177e4 LT |
664 | break; |
665 | ||
666 | default: | |
71cc2c21 | 667 | printk(KERN_ERR "%s: bad port number %d\n", __func__, port); |
1da177e4 LT |
668 | } |
669 | } | |
670 | ||
671 | ||
672 | #ifdef CONFIG_SERIAL_SA1100_CONSOLE | |
3f8bab17 | 673 | static void sa1100_console_putchar(struct uart_port *port, unsigned char ch) |
d358788f | 674 | { |
c9db776b FF |
675 | struct sa1100_port *sport = |
676 | container_of(port, struct sa1100_port, port); | |
d358788f RK |
677 | |
678 | while (!(UART_GET_UTSR1(sport) & UTSR1_TNF)) | |
679 | barrier(); | |
680 | UART_PUT_CHAR(sport, ch); | |
681 | } | |
1da177e4 LT |
682 | |
683 | /* | |
684 | * Interrupts are disabled on entering | |
685 | */ | |
686 | static void | |
687 | sa1100_console_write(struct console *co, const char *s, unsigned int count) | |
688 | { | |
689 | struct sa1100_port *sport = &sa1100_ports[co->index]; | |
d358788f | 690 | unsigned int old_utcr3, status; |
1da177e4 LT |
691 | |
692 | /* | |
693 | * First, save UTCR3 and then disable interrupts | |
694 | */ | |
695 | old_utcr3 = UART_GET_UTCR3(sport); | |
696 | UART_PUT_UTCR3(sport, (old_utcr3 & ~(UTCR3_RIE | UTCR3_TIE)) | | |
697 | UTCR3_TXE); | |
698 | ||
d358788f | 699 | uart_console_write(&sport->port, s, count, sa1100_console_putchar); |
1da177e4 LT |
700 | |
701 | /* | |
702 | * Finally, wait for transmitter to become empty | |
703 | * and restore UTCR3 | |
704 | */ | |
705 | do { | |
706 | status = UART_GET_UTSR1(sport); | |
707 | } while (status & UTSR1_TBY); | |
708 | UART_PUT_UTCR3(sport, old_utcr3); | |
709 | } | |
710 | ||
711 | /* | |
712 | * If the port was already initialised (eg, by a boot loader), | |
713 | * try to determine the current setup. | |
714 | */ | |
715 | static void __init | |
716 | sa1100_console_get_options(struct sa1100_port *sport, int *baud, | |
717 | int *parity, int *bits) | |
718 | { | |
719 | unsigned int utcr3; | |
720 | ||
721 | utcr3 = UART_GET_UTCR3(sport) & (UTCR3_RXE | UTCR3_TXE); | |
722 | if (utcr3 == (UTCR3_RXE | UTCR3_TXE)) { | |
723 | /* ok, the port was enabled */ | |
724 | unsigned int utcr0, quot; | |
725 | ||
726 | utcr0 = UART_GET_UTCR0(sport); | |
727 | ||
728 | *parity = 'n'; | |
729 | if (utcr0 & UTCR0_PE) { | |
730 | if (utcr0 & UTCR0_OES) | |
731 | *parity = 'e'; | |
732 | else | |
733 | *parity = 'o'; | |
734 | } | |
735 | ||
736 | if (utcr0 & UTCR0_DSS) | |
737 | *bits = 8; | |
738 | else | |
739 | *bits = 7; | |
740 | ||
741 | quot = UART_GET_UTCR2(sport) | UART_GET_UTCR1(sport) << 8; | |
742 | quot &= 0xfff; | |
743 | *baud = sport->port.uartclk / (16 * (quot + 1)); | |
744 | } | |
745 | } | |
746 | ||
747 | static int __init | |
748 | sa1100_console_setup(struct console *co, char *options) | |
749 | { | |
750 | struct sa1100_port *sport; | |
751 | int baud = 9600; | |
752 | int bits = 8; | |
753 | int parity = 'n'; | |
754 | int flow = 'n'; | |
755 | ||
756 | /* | |
757 | * Check whether an invalid uart number has been specified, and | |
758 | * if so, search for the first available port that does have | |
759 | * console support. | |
760 | */ | |
761 | if (co->index == -1 || co->index >= NR_PORTS) | |
762 | co->index = 0; | |
763 | sport = &sa1100_ports[co->index]; | |
764 | ||
765 | if (options) | |
766 | uart_parse_options(options, &baud, &parity, &bits, &flow); | |
767 | else | |
768 | sa1100_console_get_options(sport, &baud, &parity, &bits); | |
769 | ||
770 | return uart_set_options(&sport->port, co, baud, parity, bits, flow); | |
771 | } | |
772 | ||
2d93486c | 773 | static struct uart_driver sa1100_reg; |
1da177e4 LT |
774 | static struct console sa1100_console = { |
775 | .name = "ttySA", | |
776 | .write = sa1100_console_write, | |
777 | .device = uart_console_device, | |
778 | .setup = sa1100_console_setup, | |
779 | .flags = CON_PRINTBUFFER, | |
780 | .index = -1, | |
781 | .data = &sa1100_reg, | |
782 | }; | |
783 | ||
784 | static int __init sa1100_rs_console_init(void) | |
785 | { | |
786 | sa1100_init_ports(); | |
787 | register_console(&sa1100_console); | |
788 | return 0; | |
789 | } | |
790 | console_initcall(sa1100_rs_console_init); | |
791 | ||
792 | #define SA1100_CONSOLE &sa1100_console | |
793 | #else | |
794 | #define SA1100_CONSOLE NULL | |
795 | #endif | |
796 | ||
797 | static struct uart_driver sa1100_reg = { | |
798 | .owner = THIS_MODULE, | |
799 | .driver_name = "ttySA", | |
800 | .dev_name = "ttySA", | |
1da177e4 LT |
801 | .major = SERIAL_SA1100_MAJOR, |
802 | .minor = MINOR_START, | |
803 | .nr = NR_PORTS, | |
804 | .cons = SA1100_CONSOLE, | |
805 | }; | |
806 | ||
3ae5eaec | 807 | static int sa1100_serial_suspend(struct platform_device *dev, pm_message_t state) |
1da177e4 | 808 | { |
3ae5eaec | 809 | struct sa1100_port *sport = platform_get_drvdata(dev); |
1da177e4 | 810 | |
9480e307 | 811 | if (sport) |
1da177e4 LT |
812 | uart_suspend_port(&sa1100_reg, &sport->port); |
813 | ||
814 | return 0; | |
815 | } | |
816 | ||
3ae5eaec | 817 | static int sa1100_serial_resume(struct platform_device *dev) |
1da177e4 | 818 | { |
3ae5eaec | 819 | struct sa1100_port *sport = platform_get_drvdata(dev); |
1da177e4 | 820 | |
9480e307 | 821 | if (sport) |
1da177e4 LT |
822 | uart_resume_port(&sa1100_reg, &sport->port); |
823 | ||
824 | return 0; | |
825 | } | |
826 | ||
d9d03e2c RK |
827 | static int sa1100_serial_add_one_port(struct sa1100_port *sport, struct platform_device *dev) |
828 | { | |
829 | sport->port.dev = &dev->dev; | |
386ae3b7 | 830 | sport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_SA1100_CONSOLE); |
0faf70ca RK |
831 | |
832 | // mctrl_gpio_init() requires that the GPIO driver supports interrupts, | |
833 | // but we need to support GPIO drivers for hardware that has no such | |
834 | // interrupts. Use mctrl_gpio_init_noauto() instead. | |
d9d03e2c RK |
835 | sport->gpios = mctrl_gpio_init_noauto(sport->port.dev, 0); |
836 | if (IS_ERR(sport->gpios)) { | |
837 | int err = PTR_ERR(sport->gpios); | |
838 | ||
839 | dev_err(sport->port.dev, "failed to get mctrl gpios: %d\n", | |
840 | err); | |
841 | ||
842 | if (err == -EPROBE_DEFER) | |
843 | return err; | |
844 | ||
845 | sport->gpios = NULL; | |
846 | } | |
847 | ||
848 | platform_set_drvdata(dev, sport); | |
849 | ||
850 | return uart_add_one_port(&sa1100_reg, &sport->port); | |
851 | } | |
852 | ||
3ae5eaec | 853 | static int sa1100_serial_probe(struct platform_device *dev) |
1da177e4 | 854 | { |
465ddff7 | 855 | struct resource *res; |
1da177e4 LT |
856 | int i; |
857 | ||
465ddff7 AS |
858 | res = platform_get_resource(dev, IORESOURCE_MEM, 0); |
859 | if (!res) | |
860 | return -EINVAL; | |
1da177e4 | 861 | |
465ddff7 AS |
862 | for (i = 0; i < NR_PORTS; i++) |
863 | if (sa1100_ports[i].port.mapbase == res->start) | |
1da177e4 | 864 | break; |
465ddff7 AS |
865 | if (i == NR_PORTS) |
866 | return -ENODEV; | |
867 | ||
868 | sa1100_serial_add_one_port(&sa1100_ports[i], dev); | |
1da177e4 LT |
869 | |
870 | return 0; | |
871 | } | |
872 | ||
1158e40b | 873 | static void sa1100_serial_remove(struct platform_device *pdev) |
1da177e4 | 874 | { |
3ae5eaec | 875 | struct sa1100_port *sport = platform_get_drvdata(pdev); |
1da177e4 | 876 | |
1da177e4 LT |
877 | if (sport) |
878 | uart_remove_one_port(&sa1100_reg, &sport->port); | |
1da177e4 LT |
879 | } |
880 | ||
3ae5eaec | 881 | static struct platform_driver sa11x0_serial_driver = { |
1da177e4 | 882 | .probe = sa1100_serial_probe, |
1158e40b | 883 | .remove_new = sa1100_serial_remove, |
1da177e4 LT |
884 | .suspend = sa1100_serial_suspend, |
885 | .resume = sa1100_serial_resume, | |
3ae5eaec RK |
886 | .driver = { |
887 | .name = "sa11x0-uart", | |
888 | }, | |
1da177e4 LT |
889 | }; |
890 | ||
891 | static int __init sa1100_serial_init(void) | |
892 | { | |
893 | int ret; | |
894 | ||
d87a6d95 | 895 | printk(KERN_INFO "Serial: SA11x0 driver\n"); |
1da177e4 LT |
896 | |
897 | sa1100_init_ports(); | |
898 | ||
899 | ret = uart_register_driver(&sa1100_reg); | |
900 | if (ret == 0) { | |
3ae5eaec | 901 | ret = platform_driver_register(&sa11x0_serial_driver); |
1da177e4 LT |
902 | if (ret) |
903 | uart_unregister_driver(&sa1100_reg); | |
904 | } | |
905 | return ret; | |
906 | } | |
907 | ||
908 | static void __exit sa1100_serial_exit(void) | |
909 | { | |
3ae5eaec | 910 | platform_driver_unregister(&sa11x0_serial_driver); |
1da177e4 LT |
911 | uart_unregister_driver(&sa1100_reg); |
912 | } | |
913 | ||
914 | module_init(sa1100_serial_init); | |
915 | module_exit(sa1100_serial_exit); | |
916 | ||
917 | MODULE_AUTHOR("Deep Blue Solutions Ltd"); | |
d87a6d95 | 918 | MODULE_DESCRIPTION("SA1100 generic serial port driver"); |
1da177e4 LT |
919 | MODULE_LICENSE("GPL"); |
920 | MODULE_ALIAS_CHARDEV_MAJOR(SERIAL_SA1100_MAJOR); | |
e169c139 | 921 | MODULE_ALIAS("platform:sa11x0-uart"); |