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tty: add SPDX identifiers to all remaining files in drivers/tty/
[linux-block.git] / drivers / tty / serial / rp2.c
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e3b3d0f5 1// SPDX-License-Identifier: GPL-2.0
7d9f49af
KC		 2/*
3 * Driver for Comtrol RocketPort EXPRESS/INFINITY cards
4 *
5 * Copyright (C) 2012 Kevin Cernekee <cernekee@gmail.com>
6 *
7 * Inspired by, and loosely based on:
8 *
9 * ar933x_uart.c
10 * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
11 *
12 * rocketport_infinity_express-linux-1.20.tar.gz
13 * Copyright (C) 2004-2011 Comtrol, Inc.
14 *
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License version 2 as published
17 * by the Free Software Foundation.
18 */
19
20#include <linux/bitops.h>
21#include <linux/compiler.h>
22#include <linux/completion.h>
23#include <linux/console.h>
24#include <linux/delay.h>
25#include <linux/firmware.h>
26#include <linux/init.h>
27#include <linux/io.h>
28#include <linux/ioport.h>
29#include <linux/irq.h>
30#include <linux/kernel.h>
31#include <linux/log2.h>
32#include <linux/module.h>
33#include <linux/pci.h>
34#include <linux/serial.h>
35#include <linux/serial_core.h>
36#include <linux/slab.h>
37#include <linux/sysrq.h>
38#include <linux/tty.h>
39#include <linux/tty_flip.h>
40#include <linux/types.h>
41
42#define DRV_NAME "rp2"
43
44#define RP2_FW_NAME "rp2.fw"
45#define RP2_UCODE_BYTES 0x3f
46
47#define PORTS_PER_ASIC 16
48#define ALL_PORTS_MASK (BIT(PORTS_PER_ASIC) - 1)
49
50#define UART_CLOCK 44236800
51#define DEFAULT_BAUD_DIV (UART_CLOCK / (9600 * 16))
52#define FIFO_SIZE 512
53
54/* BAR0 registers */
55#define RP2_FPGA_CTL0 0x110
56#define RP2_FPGA_CTL1 0x11c
57#define RP2_IRQ_MASK 0x1ec
58#define RP2_IRQ_MASK_EN_m BIT(0)
59#define RP2_IRQ_STATUS 0x1f0
60
61/* BAR1 registers */
62#define RP2_ASIC_SPACING 0x1000
63#define RP2_ASIC_OFFSET(i) ((i) << ilog2(RP2_ASIC_SPACING))
64
65#define RP2_PORT_BASE 0x000
66#define RP2_PORT_SPACING 0x040
67
68#define RP2_UCODE_BASE 0x400
69#define RP2_UCODE_SPACING 0x80
70
71#define RP2_CLK_PRESCALER 0xc00
72#define RP2_CH_IRQ_STAT 0xc04
73#define RP2_CH_IRQ_MASK 0xc08
74#define RP2_ASIC_IRQ 0xd00
75#define RP2_ASIC_IRQ_EN_m BIT(20)
76#define RP2_GLOBAL_CMD 0xd0c
77#define RP2_ASIC_CFG 0xd04
78
79/* port registers */
80#define RP2_DATA_DWORD 0x000
81
82#define RP2_DATA_BYTE 0x008
83#define RP2_DATA_BYTE_ERR_PARITY_m BIT(8)
84#define RP2_DATA_BYTE_ERR_OVERRUN_m BIT(9)
85#define RP2_DATA_BYTE_ERR_FRAMING_m BIT(10)
86#define RP2_DATA_BYTE_BREAK_m BIT(11)
87
88/* This lets uart_insert_char() drop bytes received on a !CREAD port */
89#define RP2_DUMMY_READ BIT(16)
90
91#define RP2_DATA_BYTE_EXCEPTION_MASK (RP2_DATA_BYTE_ERR_PARITY_m | \
92 RP2_DATA_BYTE_ERR_OVERRUN_m | \
93 RP2_DATA_BYTE_ERR_FRAMING_m | \
94 RP2_DATA_BYTE_BREAK_m)
95
96#define RP2_RX_FIFO_COUNT 0x00c
97#define RP2_TX_FIFO_COUNT 0x00e
98
99#define RP2_CHAN_STAT 0x010
100#define RP2_CHAN_STAT_RXDATA_m BIT(0)
101#define RP2_CHAN_STAT_DCD_m BIT(3)
102#define RP2_CHAN_STAT_DSR_m BIT(4)
103#define RP2_CHAN_STAT_CTS_m BIT(5)
104#define RP2_CHAN_STAT_RI_m BIT(6)
105#define RP2_CHAN_STAT_OVERRUN_m BIT(13)
106#define RP2_CHAN_STAT_DSR_CHANGED_m BIT(16)
107#define RP2_CHAN_STAT_CTS_CHANGED_m BIT(17)
108#define RP2_CHAN_STAT_CD_CHANGED_m BIT(18)
109#define RP2_CHAN_STAT_RI_CHANGED_m BIT(22)
110#define RP2_CHAN_STAT_TXEMPTY_m BIT(25)
111
112#define RP2_CHAN_STAT_MS_CHANGED_MASK (RP2_CHAN_STAT_DSR_CHANGED_m | \
113 RP2_CHAN_STAT_CTS_CHANGED_m | \
114 RP2_CHAN_STAT_CD_CHANGED_m | \
115 RP2_CHAN_STAT_RI_CHANGED_m)
116
117#define RP2_TXRX_CTL 0x014
118#define RP2_TXRX_CTL_MSRIRQ_m BIT(0)
119#define RP2_TXRX_CTL_RXIRQ_m BIT(2)
120#define RP2_TXRX_CTL_RX_TRIG_s 3
121#define RP2_TXRX_CTL_RX_TRIG_m (0x3 << RP2_TXRX_CTL_RX_TRIG_s)
122#define RP2_TXRX_CTL_RX_TRIG_1 (0x1 << RP2_TXRX_CTL_RX_TRIG_s)
123#define RP2_TXRX_CTL_RX_TRIG_256 (0x2 << RP2_TXRX_CTL_RX_TRIG_s)
124#define RP2_TXRX_CTL_RX_TRIG_448 (0x3 << RP2_TXRX_CTL_RX_TRIG_s)
125#define RP2_TXRX_CTL_RX_EN_m BIT(5)
126#define RP2_TXRX_CTL_RTSFLOW_m BIT(6)
127#define RP2_TXRX_CTL_DTRFLOW_m BIT(7)
128#define RP2_TXRX_CTL_TX_TRIG_s 16
129#define RP2_TXRX_CTL_TX_TRIG_m (0x3 << RP2_TXRX_CTL_RX_TRIG_s)
130#define RP2_TXRX_CTL_DSRFLOW_m BIT(18)
131#define RP2_TXRX_CTL_TXIRQ_m BIT(19)
132#define RP2_TXRX_CTL_CTSFLOW_m BIT(23)
133#define RP2_TXRX_CTL_TX_EN_m BIT(24)
134#define RP2_TXRX_CTL_RTS_m BIT(25)
135#define RP2_TXRX_CTL_DTR_m BIT(26)
136#define RP2_TXRX_CTL_LOOP_m BIT(27)
137#define RP2_TXRX_CTL_BREAK_m BIT(28)
138#define RP2_TXRX_CTL_CMSPAR_m BIT(29)
139#define RP2_TXRX_CTL_nPARODD_m BIT(30)
140#define RP2_TXRX_CTL_PARENB_m BIT(31)
141
142#define RP2_UART_CTL 0x018
143#define RP2_UART_CTL_MODE_s 0
144#define RP2_UART_CTL_MODE_m (0x7 << RP2_UART_CTL_MODE_s)
145#define RP2_UART_CTL_MODE_rs232 (0x1 << RP2_UART_CTL_MODE_s)
146#define RP2_UART_CTL_FLUSH_RX_m BIT(3)
147#define RP2_UART_CTL_FLUSH_TX_m BIT(4)
148#define RP2_UART_CTL_RESET_CH_m BIT(5)
149#define RP2_UART_CTL_XMIT_EN_m BIT(6)
150#define RP2_UART_CTL_DATABITS_s 8
151#define RP2_UART_CTL_DATABITS_m (0x3 << RP2_UART_CTL_DATABITS_s)
152#define RP2_UART_CTL_DATABITS_8 (0x3 << RP2_UART_CTL_DATABITS_s)
153#define RP2_UART_CTL_DATABITS_7 (0x2 << RP2_UART_CTL_DATABITS_s)
154#define RP2_UART_CTL_DATABITS_6 (0x1 << RP2_UART_CTL_DATABITS_s)
155#define RP2_UART_CTL_DATABITS_5 (0x0 << RP2_UART_CTL_DATABITS_s)
156#define RP2_UART_CTL_STOPBITS_m BIT(10)
157
158#define RP2_BAUD 0x01c
159
160/* ucode registers */
161#define RP2_TX_SWFLOW 0x02
162#define RP2_TX_SWFLOW_ena 0x81
163#define RP2_TX_SWFLOW_dis 0x9d
164
165#define RP2_RX_SWFLOW 0x0c
166#define RP2_RX_SWFLOW_ena 0x81
167#define RP2_RX_SWFLOW_dis 0x8d
168
169#define RP2_RX_FIFO 0x37
170#define RP2_RX_FIFO_ena 0x08
171#define RP2_RX_FIFO_dis 0x81
172
173static struct uart_driver rp2_uart_driver = {
174 .owner = THIS_MODULE,
175 .driver_name = DRV_NAME,
176 .dev_name = "ttyRP",
177 .nr = CONFIG_SERIAL_RP2_NR_UARTS,
178};
179
180struct rp2_card;
181
182struct rp2_uart_port {
183 struct uart_port port;
184 int idx;
185 int ignore_rx;
186 struct rp2_card *card;
187 void __iomem *asic_base;
188 void __iomem *base;
189 void __iomem *ucode;
190};
191
192struct rp2_card {
193 struct pci_dev *pdev;
194 struct rp2_uart_port *ports;
195 int n_ports;
196 int initialized_ports;
197 int minor_start;
198 int smpte;
199 void __iomem *bar0;
200 void __iomem *bar1;
201 spinlock_t card_lock;
202 struct completion fw_loaded;
203};
204
205#define RP_ID(prod) PCI_VDEVICE(RP, (prod))
206#define RP_CAP(ports, smpte) (((ports) << 8) | ((smpte) << 0))
207
208static inline void rp2_decode_cap(const struct pci_device_id *id,
209 int *ports, int *smpte)
210{
211 *ports = id->driver_data >> 8;
212 *smpte = id->driver_data & 0xff;
213}
214
215static DEFINE_SPINLOCK(rp2_minor_lock);
216static int rp2_minor_next;
217
218static int rp2_alloc_ports(int n_ports)
219{
220 int ret = -ENOSPC;
221
222 spin_lock(&rp2_minor_lock);
223 if (rp2_minor_next + n_ports <= CONFIG_SERIAL_RP2_NR_UARTS) {
224 /* sorry, no support for hot unplugging individual cards */
225 ret = rp2_minor_next;
226 rp2_minor_next += n_ports;
227 }
228 spin_unlock(&rp2_minor_lock);
229
230 return ret;
231}
232
233static inline struct rp2_uart_port *port_to_up(struct uart_port *port)
234{
235 return container_of(port, struct rp2_uart_port, port);
236}
237
238static void rp2_rmw(struct rp2_uart_port *up, int reg,
239 u32 clr_bits, u32 set_bits)
240{
241 u32 tmp = readl(up->base + reg);
242 tmp &= ~clr_bits;
243 tmp |= set_bits;
244 writel(tmp, up->base + reg);
245}
246
247static void rp2_rmw_clr(struct rp2_uart_port *up, int reg, u32 val)
248{
249 rp2_rmw(up, reg, val, 0);
250}
251
252static void rp2_rmw_set(struct rp2_uart_port *up, int reg, u32 val)
253{
254 rp2_rmw(up, reg, 0, val);
255}
256
257static void rp2_mask_ch_irq(struct rp2_uart_port *up, int ch_num,
258 int is_enabled)
259{
260 unsigned long flags, irq_mask;
261
262 spin_lock_irqsave(&up->card->card_lock, flags);
263
264 irq_mask = readl(up->asic_base + RP2_CH_IRQ_MASK);
265 if (is_enabled)
266 irq_mask &= ~BIT(ch_num);
267 else
268 irq_mask |= BIT(ch_num);
269 writel(irq_mask, up->asic_base + RP2_CH_IRQ_MASK);
270
271 spin_unlock_irqrestore(&up->card->card_lock, flags);
272}
273
274static unsigned int rp2_uart_tx_empty(struct uart_port *port)
275{
276 struct rp2_uart_port *up = port_to_up(port);
277 unsigned long tx_fifo_bytes, flags;
278
279 /*
280 * This should probably check the transmitter, not the FIFO.
281 * But the TXEMPTY bit doesn't seem to work unless the TX IRQ is
282 * enabled.
283 */
284 spin_lock_irqsave(&up->port.lock, flags);
285 tx_fifo_bytes = readw(up->base + RP2_TX_FIFO_COUNT);
286 spin_unlock_irqrestore(&up->port.lock, flags);
287
288 return tx_fifo_bytes ? 0 : TIOCSER_TEMT;
289}
290
291static unsigned int rp2_uart_get_mctrl(struct uart_port *port)
292{
293 struct rp2_uart_port *up = port_to_up(port);
294 u32 status;
295
296 status = readl(up->base + RP2_CHAN_STAT);
297 return ((status & RP2_CHAN_STAT_DCD_m) ? TIOCM_CAR : 0) |
298 ((status & RP2_CHAN_STAT_DSR_m) ? TIOCM_DSR : 0) |
299 ((status & RP2_CHAN_STAT_CTS_m) ? TIOCM_CTS : 0) |
300 ((status & RP2_CHAN_STAT_RI_m) ? TIOCM_RI : 0);
301}
302
303static void rp2_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
304{
305 rp2_rmw(port_to_up(port), RP2_TXRX_CTL,
306 RP2_TXRX_CTL_DTR_m | RP2_TXRX_CTL_RTS_m | RP2_TXRX_CTL_LOOP_m,
307 ((mctrl & TIOCM_DTR) ? RP2_TXRX_CTL_DTR_m : 0) |
308 ((mctrl & TIOCM_RTS) ? RP2_TXRX_CTL_RTS_m : 0) |
309 ((mctrl & TIOCM_LOOP) ? RP2_TXRX_CTL_LOOP_m : 0));
310}
311
312static void rp2_uart_start_tx(struct uart_port *port)
313{
314 rp2_rmw_set(port_to_up(port), RP2_TXRX_CTL, RP2_TXRX_CTL_TXIRQ_m);
315}
316
317static void rp2_uart_stop_tx(struct uart_port *port)
318{
319 rp2_rmw_clr(port_to_up(port), RP2_TXRX_CTL, RP2_TXRX_CTL_TXIRQ_m);
320}
321
322static void rp2_uart_stop_rx(struct uart_port *port)
323{
324 rp2_rmw_clr(port_to_up(port), RP2_TXRX_CTL, RP2_TXRX_CTL_RXIRQ_m);
325}
326
327static void rp2_uart_break_ctl(struct uart_port *port, int break_state)
328{
329 unsigned long flags;
330
331 spin_lock_irqsave(&port->lock, flags);
332 rp2_rmw(port_to_up(port), RP2_TXRX_CTL, RP2_TXRX_CTL_BREAK_m,
333 break_state ? RP2_TXRX_CTL_BREAK_m : 0);
334 spin_unlock_irqrestore(&port->lock, flags);
335}
336
337static void rp2_uart_enable_ms(struct uart_port *port)
338{
339 rp2_rmw_set(port_to_up(port), RP2_TXRX_CTL, RP2_TXRX_CTL_MSRIRQ_m);
340}
341
342static void __rp2_uart_set_termios(struct rp2_uart_port *up,
343 unsigned long cfl,
344 unsigned long ifl,
345 unsigned int baud_div)
346{
347 /* baud rate divisor (calculated elsewhere). 0 = divide-by-1 */
348 writew(baud_div - 1, up->base + RP2_BAUD);
349
350 /* data bits and stop bits */
351 rp2_rmw(up, RP2_UART_CTL,
352 RP2_UART_CTL_STOPBITS_m | RP2_UART_CTL_DATABITS_m,
353 ((cfl & CSTOPB) ? RP2_UART_CTL_STOPBITS_m : 0) |
354 (((cfl & CSIZE) == CS8) ? RP2_UART_CTL_DATABITS_8 : 0) |
355 (((cfl & CSIZE) == CS7) ? RP2_UART_CTL_DATABITS_7 : 0) |
356 (((cfl & CSIZE) == CS6) ? RP2_UART_CTL_DATABITS_6 : 0) |
357 (((cfl & CSIZE) == CS5) ? RP2_UART_CTL_DATABITS_5 : 0));
358
359 /* parity and hardware flow control */
360 rp2_rmw(up, RP2_TXRX_CTL,
361 RP2_TXRX_CTL_PARENB_m | RP2_TXRX_CTL_nPARODD_m |
362 RP2_TXRX_CTL_CMSPAR_m | RP2_TXRX_CTL_DTRFLOW_m |
363 RP2_TXRX_CTL_DSRFLOW_m | RP2_TXRX_CTL_RTSFLOW_m |
364 RP2_TXRX_CTL_CTSFLOW_m,
365 ((cfl & PARENB) ? RP2_TXRX_CTL_PARENB_m : 0) |
366 ((cfl & PARODD) ? 0 : RP2_TXRX_CTL_nPARODD_m) |
367 ((cfl & CMSPAR) ? RP2_TXRX_CTL_CMSPAR_m : 0) |
368 ((cfl & CRTSCTS) ? (RP2_TXRX_CTL_RTSFLOW_m |
369 RP2_TXRX_CTL_CTSFLOW_m) : 0));
370
371 /* XON/XOFF software flow control */
372 writeb((ifl & IXON) ? RP2_TX_SWFLOW_ena : RP2_TX_SWFLOW_dis,
373 up->ucode + RP2_TX_SWFLOW);
374 writeb((ifl & IXOFF) ? RP2_RX_SWFLOW_ena : RP2_RX_SWFLOW_dis,
375 up->ucode + RP2_RX_SWFLOW);
376}
377
378static void rp2_uart_set_termios(struct uart_port *port,
379 struct ktermios *new,
380 struct ktermios *old)
381{
382 struct rp2_uart_port *up = port_to_up(port);
383 unsigned long flags;
384 unsigned int baud, baud_div;
385
386 baud = uart_get_baud_rate(port, new, old, 0, port->uartclk / 16);
387 baud_div = uart_get_divisor(port, baud);
388
389 if (tty_termios_baud_rate(new))
390 tty_termios_encode_baud_rate(new, baud, baud);
391
392 spin_lock_irqsave(&port->lock, flags);
393
394 /* ignore all characters if CREAD is not set */
395 port->ignore_status_mask = (new->c_cflag & CREAD) ? 0 : RP2_DUMMY_READ;
396
397 __rp2_uart_set_termios(up, new->c_cflag, new->c_iflag, baud_div);
398 uart_update_timeout(port, new->c_cflag, baud);
399
400 spin_unlock_irqrestore(&port->lock, flags);
401}
402
403static void rp2_rx_chars(struct rp2_uart_port *up)
404{
405 u16 bytes = readw(up->base + RP2_RX_FIFO_COUNT);
406 struct tty_port *port = &up->port.state->port;
407
408 for (; bytes != 0; bytes--) {
409 u32 byte = readw(up->base + RP2_DATA_BYTE) | RP2_DUMMY_READ;
410 char ch = byte & 0xff;
411
412 if (likely(!(byte & RP2_DATA_BYTE_EXCEPTION_MASK))) {
413 if (!uart_handle_sysrq_char(&up->port, ch))
414 uart_insert_char(&up->port, byte, 0, ch,
415 TTY_NORMAL);
416 } else {
417 char flag = TTY_NORMAL;
418
419 if (byte & RP2_DATA_BYTE_BREAK_m)
420 flag = TTY_BREAK;
421 else if (byte & RP2_DATA_BYTE_ERR_FRAMING_m)
422 flag = TTY_FRAME;
423 else if (byte & RP2_DATA_BYTE_ERR_PARITY_m)
424 flag = TTY_PARITY;
425 uart_insert_char(&up->port, byte,
426 RP2_DATA_BYTE_ERR_OVERRUN_m, ch, flag);
427 }
428 up->port.icount.rx++;
429 }
430
de7053c7 431 spin_unlock(&up->port.lock);
7d9f49af 432 tty_flip_buffer_push(port);
de7053c7 433 spin_lock(&up->port.lock);
7d9f49af
KC		 434}
435
436static void rp2_tx_chars(struct rp2_uart_port *up)
437{
438 u16 max_tx = FIFO_SIZE - readw(up->base + RP2_TX_FIFO_COUNT);
439 struct circ_buf *xmit = &up->port.state->xmit;
440
441 if (uart_tx_stopped(&up->port)) {
442 rp2_uart_stop_tx(&up->port);
443 return;
444 }
445
446 for (; max_tx != 0; max_tx--) {
447 if (up->port.x_char) {
448 writeb(up->port.x_char, up->base + RP2_DATA_BYTE);
449 up->port.x_char = 0;
450 up->port.icount.tx++;
451 continue;
452 }
453 if (uart_circ_empty(xmit)) {
454 rp2_uart_stop_tx(&up->port);
455 break;
456 }
457 writeb(xmit->buf[xmit->tail], up->base + RP2_DATA_BYTE);
458 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
459 up->port.icount.tx++;
460 }
461
462 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
463 uart_write_wakeup(&up->port);
464}
465
466static void rp2_ch_interrupt(struct rp2_uart_port *up)
467{
468 u32 status;
469
470 spin_lock(&up->port.lock);
471
472 /*
473 * The IRQ status bits are clear-on-write. Other status bits in
474 * this register aren't, so it's harmless to write to them.
475 */
476 status = readl(up->base + RP2_CHAN_STAT);
477 writel(status, up->base + RP2_CHAN_STAT);
478
479 if (status & RP2_CHAN_STAT_RXDATA_m)
480 rp2_rx_chars(up);
481 if (status & RP2_CHAN_STAT_TXEMPTY_m)
482 rp2_tx_chars(up);
483 if (status & RP2_CHAN_STAT_MS_CHANGED_MASK)
484 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
485
486 spin_unlock(&up->port.lock);
487}
488
489static int rp2_asic_interrupt(struct rp2_card *card, unsigned int asic_id)
490{
491 void __iomem *base = card->bar1 + RP2_ASIC_OFFSET(asic_id);
492 int ch, handled = 0;
493 unsigned long status = readl(base + RP2_CH_IRQ_STAT) &
494 ~readl(base + RP2_CH_IRQ_MASK);
495
496 for_each_set_bit(ch, &status, PORTS_PER_ASIC) {
497 rp2_ch_interrupt(&card->ports[ch]);
498 handled++;
499 }
500 return handled;
501}
502
503static irqreturn_t rp2_uart_interrupt(int irq, void *dev_id)
504{
505 struct rp2_card *card = dev_id;
506 int handled;
507
508 handled = rp2_asic_interrupt(card, 0);
509 if (card->n_ports >= PORTS_PER_ASIC)
510 handled += rp2_asic_interrupt(card, 1);
511
512 return handled ? IRQ_HANDLED : IRQ_NONE;
513}
514
515static inline void rp2_flush_fifos(struct rp2_uart_port *up)
516{
517 rp2_rmw_set(up, RP2_UART_CTL,
518 RP2_UART_CTL_FLUSH_RX_m | RP2_UART_CTL_FLUSH_TX_m);
519 readl(up->base + RP2_UART_CTL);
520 udelay(10);
521 rp2_rmw_clr(up, RP2_UART_CTL,
522 RP2_UART_CTL_FLUSH_RX_m | RP2_UART_CTL_FLUSH_TX_m);
523}
524
525static int rp2_uart_startup(struct uart_port *port)
526{
527 struct rp2_uart_port *up = port_to_up(port);
528
529 rp2_flush_fifos(up);
530 rp2_rmw(up, RP2_TXRX_CTL, RP2_TXRX_CTL_MSRIRQ_m, RP2_TXRX_CTL_RXIRQ_m);
531 rp2_rmw(up, RP2_TXRX_CTL, RP2_TXRX_CTL_RX_TRIG_m,
532 RP2_TXRX_CTL_RX_TRIG_1);
533 rp2_rmw(up, RP2_CHAN_STAT, 0, 0);
534 rp2_mask_ch_irq(up, up->idx, 1);
535
536 return 0;
537}
538
539static void rp2_uart_shutdown(struct uart_port *port)
540{
541 struct rp2_uart_port *up = port_to_up(port);
542 unsigned long flags;
543
544 rp2_uart_break_ctl(port, 0);
545
546 spin_lock_irqsave(&port->lock, flags);
547 rp2_mask_ch_irq(up, up->idx, 0);
548 rp2_rmw(up, RP2_CHAN_STAT, 0, 0);
549 spin_unlock_irqrestore(&port->lock, flags);
550}
551
552static const char *rp2_uart_type(struct uart_port *port)
553{
554 return (port->type == PORT_RP2) ? "RocketPort 2 UART" : NULL;
555}
556
557static void rp2_uart_release_port(struct uart_port *port)
558{
559 /* Nothing to release ... */
560}
561
562static int rp2_uart_request_port(struct uart_port *port)
563{
564 /* UARTs always present */
565 return 0;
566}
567
568static void rp2_uart_config_port(struct uart_port *port, int flags)
569{
570 if (flags & UART_CONFIG_TYPE)
571 port->type = PORT_RP2;
572}
573
574static int rp2_uart_verify_port(struct uart_port *port,
575 struct serial_struct *ser)
576{
577 if (ser->type != PORT_UNKNOWN && ser->type != PORT_RP2)
578 return -EINVAL;
579
580 return 0;
581}
582
583static const struct uart_ops rp2_uart_ops = {
584 .tx_empty = rp2_uart_tx_empty,
585 .set_mctrl = rp2_uart_set_mctrl,
586 .get_mctrl = rp2_uart_get_mctrl,
587 .stop_tx = rp2_uart_stop_tx,
588 .start_tx = rp2_uart_start_tx,
589 .stop_rx = rp2_uart_stop_rx,
590 .enable_ms = rp2_uart_enable_ms,
591 .break_ctl = rp2_uart_break_ctl,
592 .startup = rp2_uart_startup,
593 .shutdown = rp2_uart_shutdown,
594 .set_termios = rp2_uart_set_termios,
595 .type = rp2_uart_type,
596 .release_port = rp2_uart_release_port,
597 .request_port = rp2_uart_request_port,
598 .config_port = rp2_uart_config_port,
599 .verify_port = rp2_uart_verify_port,
600};
601
602static void rp2_reset_asic(struct rp2_card *card, unsigned int asic_id)
603{
604 void __iomem *base = card->bar1 + RP2_ASIC_OFFSET(asic_id);
605 u32 clk_cfg;
606
607 writew(1, base + RP2_GLOBAL_CMD);
608 readw(base + RP2_GLOBAL_CMD);
609 msleep(100);
610 writel(0, base + RP2_CLK_PRESCALER);
611
612 /* TDM clock configuration */
613 clk_cfg = readw(base + RP2_ASIC_CFG);
614 clk_cfg = (clk_cfg & ~BIT(8)) | BIT(9);
615 writew(clk_cfg, base + RP2_ASIC_CFG);
616
617 /* IRQ routing */
618 writel(ALL_PORTS_MASK, base + RP2_CH_IRQ_MASK);
619 writel(RP2_ASIC_IRQ_EN_m, base + RP2_ASIC_IRQ);
620}
621
622static void rp2_init_card(struct rp2_card *card)
623{
624 writel(4, card->bar0 + RP2_FPGA_CTL0);
625 writel(0, card->bar0 + RP2_FPGA_CTL1);
626
627 rp2_reset_asic(card, 0);
628 if (card->n_ports >= PORTS_PER_ASIC)
629 rp2_reset_asic(card, 1);
630
631 writel(RP2_IRQ_MASK_EN_m, card->bar0 + RP2_IRQ_MASK);
632}
633
634static void rp2_init_port(struct rp2_uart_port *up, const struct firmware *fw)
635{
636 int i;
637
638 writel(RP2_UART_CTL_RESET_CH_m, up->base + RP2_UART_CTL);
639 readl(up->base + RP2_UART_CTL);
640 udelay(1);
641
642 writel(0, up->base + RP2_TXRX_CTL);
643 writel(0, up->base + RP2_UART_CTL);
644 readl(up->base + RP2_UART_CTL);
645 udelay(1);
646
647 rp2_flush_fifos(up);
648
649 for (i = 0; i < min_t(int, fw->size, RP2_UCODE_BYTES); i++)
650 writeb(fw->data[i], up->ucode + i);
651
652 __rp2_uart_set_termios(up, CS8 | CREAD | CLOCAL, 0, DEFAULT_BAUD_DIV);
653 rp2_uart_set_mctrl(&up->port, 0);
654
655 writeb(RP2_RX_FIFO_ena, up->ucode + RP2_RX_FIFO);
656 rp2_rmw(up, RP2_UART_CTL, RP2_UART_CTL_MODE_m,
657 RP2_UART_CTL_XMIT_EN_m | RP2_UART_CTL_MODE_rs232);
658 rp2_rmw_set(up, RP2_TXRX_CTL,
659 RP2_TXRX_CTL_TX_EN_m | RP2_TXRX_CTL_RX_EN_m);
660}
661
662static void rp2_remove_ports(struct rp2_card *card)
663{
664 int i;
665
666 for (i = 0; i < card->initialized_ports; i++)
667 uart_remove_one_port(&rp2_uart_driver, &card->ports[i].port);
668 card->initialized_ports = 0;
669}
670
671static void rp2_fw_cb(const struct firmware *fw, void *context)
672{
673 struct rp2_card *card = context;
674 resource_size_t phys_base;
675 int i, rc = -ENOENT;
676
677 if (!fw) {
678 dev_err(&card->pdev->dev, "cannot find '%s' firmware image\n",
679 RP2_FW_NAME);
680 goto no_fw;
681 }
682
683 phys_base = pci_resource_start(card->pdev, 1);
684
685 for (i = 0; i < card->n_ports; i++) {
686 struct rp2_uart_port *rp = &card->ports[i];
687 struct uart_port *p;
688 int j = (unsigned)i % PORTS_PER_ASIC;
689
690 rp->asic_base = card->bar1;
691 rp->base = card->bar1 + RP2_PORT_BASE + j*RP2_PORT_SPACING;
692 rp->ucode = card->bar1 + RP2_UCODE_BASE + j*RP2_UCODE_SPACING;
693 rp->card = card;
694 rp->idx = j;
695
696 p = &rp->port;
697 p->line = card->minor_start + i;
698 p->dev = &card->pdev->dev;
699 p->type = PORT_RP2;
700 p->iotype = UPIO_MEM32;
701 p->uartclk = UART_CLOCK;
702 p->regshift = 2;
703 p->fifosize = FIFO_SIZE;
704 p->ops = &rp2_uart_ops;
705 p->irq = card->pdev->irq;
706 p->membase = rp->base;
707 p->mapbase = phys_base + RP2_PORT_BASE + j*RP2_PORT_SPACING;
708
709 if (i >= PORTS_PER_ASIC) {
710 rp->asic_base += RP2_ASIC_SPACING;
711 rp->base += RP2_ASIC_SPACING;
712 rp->ucode += RP2_ASIC_SPACING;
713 p->mapbase += RP2_ASIC_SPACING;
714 }
715
716 rp2_init_port(rp, fw);
717 rc = uart_add_one_port(&rp2_uart_driver, p);
718 if (rc) {
719 dev_err(&card->pdev->dev,
720 "error registering port %d: %d\n", i, rc);
721 rp2_remove_ports(card);
722 break;
723 }
724 card->initialized_ports++;
725 }
726
727 release_firmware(fw);
728no_fw:
729 /*
730 * rp2_fw_cb() is called from a workqueue long after rp2_probe()
731 * has already returned success. So if something failed here,
732 * we'll just leave the now-dormant device in place until somebody
733 * unbinds it.
734 */
735 if (rc)
736 dev_warn(&card->pdev->dev, "driver initialization failed\n");
737
738 complete(&card->fw_loaded);
739}
740
741static int rp2_probe(struct pci_dev *pdev,
742 const struct pci_device_id *id)
743{
744 struct rp2_card *card;
745 struct rp2_uart_port *ports;
746 void __iomem * const *bars;
747 int rc;
748
749 card = devm_kzalloc(&pdev->dev, sizeof(*card), GFP_KERNEL);
750 if (!card)
751 return -ENOMEM;
752 pci_set_drvdata(pdev, card);
753 spin_lock_init(&card->card_lock);
754 init_completion(&card->fw_loaded);
755
756 rc = pcim_enable_device(pdev);
757 if (rc)
758 return rc;
759
760 rc = pcim_iomap_regions_request_all(pdev, 0x03, DRV_NAME);
761 if (rc)
762 return rc;
763
764 bars = pcim_iomap_table(pdev);
765 card->bar0 = bars[0];
766 card->bar1 = bars[1];
767 card->pdev = pdev;
768
769 rp2_decode_cap(id, &card->n_ports, &card->smpte);
770 dev_info(&pdev->dev, "found new card with %d ports\n", card->n_ports);
771
772 card->minor_start = rp2_alloc_ports(card->n_ports);
773 if (card->minor_start < 0) {
774 dev_err(&pdev->dev,
775 "too many ports (try increasing CONFIG_SERIAL_RP2_NR_UARTS)\n");
776 return -EINVAL;
777 }
778
779 rp2_init_card(card);
780
781 ports = devm_kzalloc(&pdev->dev, sizeof(*ports) * card->n_ports,
782 GFP_KERNEL);
783 if (!ports)
784 return -ENOMEM;
785 card->ports = ports;
786
787 rc = devm_request_irq(&pdev->dev, pdev->irq, rp2_uart_interrupt,
788 IRQF_SHARED, DRV_NAME, card);
789 if (rc)
790 return rc;
791
792 /*
793 * Only catastrophic errors (e.g. ENOMEM) are reported here.
794 * If the FW image is missing, we'll find out in rp2_fw_cb()
795 * and print an error message.
796 */
797 rc = request_firmware_nowait(THIS_MODULE, 1, RP2_FW_NAME, &pdev->dev,
798 GFP_KERNEL, card, rp2_fw_cb);
799 if (rc)
800 return rc;
801 dev_dbg(&pdev->dev, "waiting for firmware blob...\n");
802
803 return 0;
804}
805
806static void rp2_remove(struct pci_dev *pdev)
807{
808 struct rp2_card *card = pci_get_drvdata(pdev);
809
810 wait_for_completion(&card->fw_loaded);
811 rp2_remove_ports(card);
812}
813
311df74a 814static const struct pci_device_id rp2_pci_tbl[] = {
7d9f49af
KC		 815
816 /* RocketPort INFINITY cards */
817
818 { RP_ID(0x0040), RP_CAP(8, 0) }, /* INF Octa, RJ45, selectable */
819 { RP_ID(0x0041), RP_CAP(32, 0) }, /* INF 32, ext interface */
820 { RP_ID(0x0042), RP_CAP(8, 0) }, /* INF Octa, ext interface */
821 { RP_ID(0x0043), RP_CAP(16, 0) }, /* INF 16, ext interface */
822 { RP_ID(0x0044), RP_CAP(4, 0) }, /* INF Quad, DB, selectable */
823 { RP_ID(0x0045), RP_CAP(8, 0) }, /* INF Octa, DB, selectable */
824 { RP_ID(0x0046), RP_CAP(4, 0) }, /* INF Quad, ext interface */
825 { RP_ID(0x0047), RP_CAP(4, 0) }, /* INF Quad, RJ45 */
826 { RP_ID(0x004a), RP_CAP(4, 0) }, /* INF Plus, Quad */
827 { RP_ID(0x004b), RP_CAP(8, 0) }, /* INF Plus, Octa */
828 { RP_ID(0x004c), RP_CAP(8, 0) }, /* INF III, Octa */
829 { RP_ID(0x004d), RP_CAP(4, 0) }, /* INF III, Quad */
830 { RP_ID(0x004e), RP_CAP(2, 0) }, /* INF Plus, 2, RS232 */
831 { RP_ID(0x004f), RP_CAP(2, 1) }, /* INF Plus, 2, SMPTE */
832 { RP_ID(0x0050), RP_CAP(4, 0) }, /* INF Plus, Quad, RJ45 */
833 { RP_ID(0x0051), RP_CAP(8, 0) }, /* INF Plus, Octa, RJ45 */
834 { RP_ID(0x0052), RP_CAP(8, 1) }, /* INF Octa, SMPTE */
835
836 /* RocketPort EXPRESS cards */
837
838 { RP_ID(0x0060), RP_CAP(8, 0) }, /* EXP Octa, RJ45, selectable */
839 { RP_ID(0x0061), RP_CAP(32, 0) }, /* EXP 32, ext interface */
840 { RP_ID(0x0062), RP_CAP(8, 0) }, /* EXP Octa, ext interface */
841 { RP_ID(0x0063), RP_CAP(16, 0) }, /* EXP 16, ext interface */
842 { RP_ID(0x0064), RP_CAP(4, 0) }, /* EXP Quad, DB, selectable */
843 { RP_ID(0x0065), RP_CAP(8, 0) }, /* EXP Octa, DB, selectable */
844 { RP_ID(0x0066), RP_CAP(4, 0) }, /* EXP Quad, ext interface */
845 { RP_ID(0x0067), RP_CAP(4, 0) }, /* EXP Quad, RJ45 */
846 { RP_ID(0x0068), RP_CAP(8, 0) }, /* EXP Octa, RJ11 */
847 { RP_ID(0x0072), RP_CAP(8, 1) }, /* EXP Octa, SMPTE */
848 { }
849};
850MODULE_DEVICE_TABLE(pci, rp2_pci_tbl);
851
852static struct pci_driver rp2_pci_driver = {
853 .name = DRV_NAME,
854 .id_table = rp2_pci_tbl,
855 .probe = rp2_probe,
856 .remove = rp2_remove,
857};
858
859static int __init rp2_uart_init(void)
860{
861 int rc;
862
863 rc = uart_register_driver(&rp2_uart_driver);
864 if (rc)
865 return rc;
866
867 rc = pci_register_driver(&rp2_pci_driver);
868 if (rc) {
869 uart_unregister_driver(&rp2_uart_driver);
870 return rc;
871 }
872
873 return 0;
874}
875
876static void __exit rp2_uart_exit(void)
877{
878 pci_unregister_driver(&rp2_pci_driver);
879 uart_unregister_driver(&rp2_uart_driver);
880}
881
882module_init(rp2_uart_init);
883module_exit(rp2_uart_exit);
884
885MODULE_DESCRIPTION("Comtrol RocketPort EXPRESS/INFINITY driver");
886MODULE_AUTHOR("Kevin Cernekee <cernekee@gmail.com>");
887MODULE_LICENSE("GPL v2");
888MODULE_FIRMWARE(RP2_FW_NAME);
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