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c4f52879 KR |
1 | // SPDX-License-Identifier: GPL-2.0 |
2 | // Copyright (c) 2017-2018, The Linux foundation. All rights reserved. | |
3 | ||
4 | #include <linux/clk.h> | |
5 | #include <linux/console.h> | |
6 | #include <linux/io.h> | |
7 | #include <linux/iopoll.h> | |
8 | #include <linux/module.h> | |
9 | #include <linux/of.h> | |
10 | #include <linux/of_device.h> | |
11 | #include <linux/platform_device.h> | |
12 | #include <linux/qcom-geni-se.h> | |
13 | #include <linux/serial.h> | |
14 | #include <linux/serial_core.h> | |
15 | #include <linux/slab.h> | |
16 | #include <linux/tty.h> | |
17 | #include <linux/tty_flip.h> | |
18 | ||
19 | /* UART specific GENI registers */ | |
20 | #define SE_UART_TX_TRANS_CFG 0x25c | |
21 | #define SE_UART_TX_WORD_LEN 0x268 | |
22 | #define SE_UART_TX_STOP_BIT_LEN 0x26c | |
23 | #define SE_UART_TX_TRANS_LEN 0x270 | |
24 | #define SE_UART_RX_TRANS_CFG 0x280 | |
25 | #define SE_UART_RX_WORD_LEN 0x28c | |
26 | #define SE_UART_RX_STALE_CNT 0x294 | |
27 | #define SE_UART_TX_PARITY_CFG 0x2a4 | |
28 | #define SE_UART_RX_PARITY_CFG 0x2a8 | |
29 | ||
30 | /* SE_UART_TRANS_CFG */ | |
31 | #define UART_TX_PAR_EN BIT(0) | |
32 | #define UART_CTS_MASK BIT(1) | |
33 | ||
34 | /* SE_UART_TX_WORD_LEN */ | |
35 | #define TX_WORD_LEN_MSK GENMASK(9, 0) | |
36 | ||
37 | /* SE_UART_TX_STOP_BIT_LEN */ | |
38 | #define TX_STOP_BIT_LEN_MSK GENMASK(23, 0) | |
39 | #define TX_STOP_BIT_LEN_1 0 | |
40 | #define TX_STOP_BIT_LEN_1_5 1 | |
41 | #define TX_STOP_BIT_LEN_2 2 | |
42 | ||
43 | /* SE_UART_TX_TRANS_LEN */ | |
44 | #define TX_TRANS_LEN_MSK GENMASK(23, 0) | |
45 | ||
46 | /* SE_UART_RX_TRANS_CFG */ | |
47 | #define UART_RX_INS_STATUS_BIT BIT(2) | |
48 | #define UART_RX_PAR_EN BIT(3) | |
49 | ||
50 | /* SE_UART_RX_WORD_LEN */ | |
51 | #define RX_WORD_LEN_MASK GENMASK(9, 0) | |
52 | ||
53 | /* SE_UART_RX_STALE_CNT */ | |
54 | #define RX_STALE_CNT GENMASK(23, 0) | |
55 | ||
56 | /* SE_UART_TX_PARITY_CFG/RX_PARITY_CFG */ | |
57 | #define PAR_CALC_EN BIT(0) | |
58 | #define PAR_MODE_MSK GENMASK(2, 1) | |
59 | #define PAR_MODE_SHFT 1 | |
60 | #define PAR_EVEN 0x00 | |
61 | #define PAR_ODD 0x01 | |
62 | #define PAR_SPACE 0x10 | |
63 | #define PAR_MARK 0x11 | |
64 | ||
65 | /* UART M_CMD OP codes */ | |
66 | #define UART_START_TX 0x1 | |
67 | #define UART_START_BREAK 0x4 | |
68 | #define UART_STOP_BREAK 0x5 | |
69 | /* UART S_CMD OP codes */ | |
70 | #define UART_START_READ 0x1 | |
71 | #define UART_PARAM 0x1 | |
72 | ||
73 | #define UART_OVERSAMPLING 32 | |
74 | #define STALE_TIMEOUT 16 | |
75 | #define DEFAULT_BITS_PER_CHAR 10 | |
76 | #define GENI_UART_CONS_PORTS 1 | |
77 | #define DEF_FIFO_DEPTH_WORDS 16 | |
78 | #define DEF_TX_WM 2 | |
79 | #define DEF_FIFO_WIDTH_BITS 32 | |
80 | #define UART_CONSOLE_RX_WM 2 | |
81 | ||
82 | #ifdef CONFIG_CONSOLE_POLL | |
83 | #define RX_BYTES_PW 1 | |
84 | #else | |
85 | #define RX_BYTES_PW 4 | |
86 | #endif | |
87 | ||
88 | struct qcom_geni_serial_port { | |
89 | struct uart_port uport; | |
90 | struct geni_se se; | |
91 | char name[20]; | |
92 | u32 tx_fifo_depth; | |
93 | u32 tx_fifo_width; | |
94 | u32 rx_fifo_depth; | |
95 | u32 tx_wm; | |
96 | u32 rx_wm; | |
97 | u32 rx_rfr; | |
98 | enum geni_se_xfer_mode xfer_mode; | |
99 | bool setup; | |
100 | int (*handle_rx)(struct uart_port *uport, u32 bytes, bool drop); | |
101 | unsigned int xmit_size; | |
102 | unsigned int baud; | |
103 | unsigned int tx_bytes_pw; | |
104 | unsigned int rx_bytes_pw; | |
105 | bool brk; | |
106 | }; | |
107 | ||
108 | static const struct uart_ops qcom_geni_serial_pops; | |
109 | static struct uart_driver qcom_geni_console_driver; | |
110 | static int handle_rx_console(struct uart_port *uport, u32 bytes, bool drop); | |
111 | static unsigned int qcom_geni_serial_tx_empty(struct uart_port *port); | |
112 | static void qcom_geni_serial_stop_rx(struct uart_port *uport); | |
113 | ||
114 | static const unsigned long root_freq[] = {7372800, 14745600, 19200000, 29491200, | |
115 | 32000000, 48000000, 64000000, 80000000, | |
116 | 96000000, 100000000}; | |
117 | ||
118 | #define to_dev_port(ptr, member) \ | |
119 | container_of(ptr, struct qcom_geni_serial_port, member) | |
120 | ||
121 | static struct qcom_geni_serial_port qcom_geni_console_port; | |
122 | ||
123 | static int qcom_geni_serial_request_port(struct uart_port *uport) | |
124 | { | |
125 | struct platform_device *pdev = to_platform_device(uport->dev); | |
126 | struct qcom_geni_serial_port *port = to_dev_port(uport, uport); | |
127 | struct resource *res; | |
128 | ||
129 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
130 | uport->membase = devm_ioremap_resource(&pdev->dev, res); | |
131 | if (IS_ERR(uport->membase)) | |
132 | return PTR_ERR(uport->membase); | |
133 | port->se.base = uport->membase; | |
134 | return 0; | |
135 | } | |
136 | ||
137 | static void qcom_geni_serial_config_port(struct uart_port *uport, int cfg_flags) | |
138 | { | |
139 | if (cfg_flags & UART_CONFIG_TYPE) { | |
140 | uport->type = PORT_MSM; | |
141 | qcom_geni_serial_request_port(uport); | |
142 | } | |
143 | } | |
144 | ||
145 | static unsigned int qcom_geni_cons_get_mctrl(struct uart_port *uport) | |
146 | { | |
147 | return TIOCM_DSR | TIOCM_CAR | TIOCM_CTS; | |
148 | } | |
149 | ||
150 | static void qcom_geni_cons_set_mctrl(struct uart_port *uport, | |
151 | unsigned int mctrl) | |
152 | { | |
153 | } | |
154 | ||
155 | static const char *qcom_geni_serial_get_type(struct uart_port *uport) | |
156 | { | |
157 | return "MSM"; | |
158 | } | |
159 | ||
160 | static struct qcom_geni_serial_port *get_port_from_line(int line) | |
161 | { | |
162 | if (line < 0 || line >= GENI_UART_CONS_PORTS) | |
163 | return ERR_PTR(-ENXIO); | |
164 | return &qcom_geni_console_port; | |
165 | } | |
166 | ||
167 | static bool qcom_geni_serial_poll_bit(struct uart_port *uport, | |
168 | int offset, int field, bool set) | |
169 | { | |
170 | u32 reg; | |
171 | struct qcom_geni_serial_port *port; | |
172 | unsigned int baud; | |
173 | unsigned int fifo_bits; | |
174 | unsigned long timeout_us = 20000; | |
175 | ||
176 | /* Ensure polling is not re-ordered before the prior writes/reads */ | |
177 | mb(); | |
178 | ||
179 | if (uport->private_data) { | |
180 | port = to_dev_port(uport, uport); | |
181 | baud = port->baud; | |
182 | if (!baud) | |
183 | baud = 115200; | |
184 | fifo_bits = port->tx_fifo_depth * port->tx_fifo_width; | |
185 | /* | |
186 | * Total polling iterations based on FIFO worth of bytes to be | |
187 | * sent at current baud. Add a little fluff to the wait. | |
188 | */ | |
189 | timeout_us = ((fifo_bits * USEC_PER_SEC) / baud) + 500; | |
190 | } | |
191 | ||
192 | return !readl_poll_timeout_atomic(uport->membase + offset, reg, | |
193 | (bool)(reg & field) == set, 10, timeout_us); | |
194 | } | |
195 | ||
196 | static void qcom_geni_serial_setup_tx(struct uart_port *uport, u32 xmit_size) | |
197 | { | |
198 | u32 m_cmd; | |
199 | ||
200 | writel_relaxed(xmit_size, uport->membase + SE_UART_TX_TRANS_LEN); | |
201 | m_cmd = UART_START_TX << M_OPCODE_SHFT; | |
202 | writel(m_cmd, uport->membase + SE_GENI_M_CMD0); | |
203 | } | |
204 | ||
205 | static void qcom_geni_serial_poll_tx_done(struct uart_port *uport) | |
206 | { | |
207 | int done; | |
208 | u32 irq_clear = M_CMD_DONE_EN; | |
209 | ||
210 | done = qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, | |
211 | M_CMD_DONE_EN, true); | |
212 | if (!done) { | |
213 | writel_relaxed(M_GENI_CMD_ABORT, uport->membase + | |
214 | SE_GENI_M_CMD_CTRL_REG); | |
215 | irq_clear |= M_CMD_ABORT_EN; | |
216 | qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, | |
217 | M_CMD_ABORT_EN, true); | |
218 | } | |
219 | writel_relaxed(irq_clear, uport->membase + SE_GENI_M_IRQ_CLEAR); | |
220 | } | |
221 | ||
222 | static void qcom_geni_serial_abort_rx(struct uart_port *uport) | |
223 | { | |
224 | u32 irq_clear = S_CMD_DONE_EN | S_CMD_ABORT_EN; | |
225 | ||
226 | writel(S_GENI_CMD_ABORT, uport->membase + SE_GENI_S_CMD_CTRL_REG); | |
227 | qcom_geni_serial_poll_bit(uport, SE_GENI_S_CMD_CTRL_REG, | |
228 | S_GENI_CMD_ABORT, false); | |
229 | writel_relaxed(irq_clear, uport->membase + SE_GENI_S_IRQ_CLEAR); | |
230 | writel_relaxed(FORCE_DEFAULT, uport->membase + GENI_FORCE_DEFAULT_REG); | |
231 | } | |
232 | ||
233 | #ifdef CONFIG_CONSOLE_POLL | |
234 | static int qcom_geni_serial_get_char(struct uart_port *uport) | |
235 | { | |
236 | u32 rx_fifo; | |
237 | u32 status; | |
238 | ||
239 | status = readl_relaxed(uport->membase + SE_GENI_M_IRQ_STATUS); | |
240 | writel_relaxed(status, uport->membase + SE_GENI_M_IRQ_CLEAR); | |
241 | ||
242 | status = readl_relaxed(uport->membase + SE_GENI_S_IRQ_STATUS); | |
243 | writel_relaxed(status, uport->membase + SE_GENI_S_IRQ_CLEAR); | |
244 | ||
245 | /* | |
246 | * Ensure the writes to clear interrupts is not re-ordered after | |
247 | * reading the data. | |
248 | */ | |
249 | mb(); | |
250 | ||
251 | status = readl_relaxed(uport->membase + SE_GENI_RX_FIFO_STATUS); | |
252 | if (!(status & RX_FIFO_WC_MSK)) | |
253 | return NO_POLL_CHAR; | |
254 | ||
255 | rx_fifo = readl(uport->membase + SE_GENI_RX_FIFOn); | |
256 | return rx_fifo & 0xff; | |
257 | } | |
258 | ||
259 | static void qcom_geni_serial_poll_put_char(struct uart_port *uport, | |
260 | unsigned char c) | |
261 | { | |
262 | struct qcom_geni_serial_port *port = to_dev_port(uport, uport); | |
263 | ||
264 | writel_relaxed(port->tx_wm, uport->membase + SE_GENI_TX_WATERMARK_REG); | |
265 | qcom_geni_serial_setup_tx(uport, 1); | |
266 | WARN_ON(!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, | |
267 | M_TX_FIFO_WATERMARK_EN, true)); | |
268 | writel_relaxed(c, uport->membase + SE_GENI_TX_FIFOn); | |
269 | writel_relaxed(M_TX_FIFO_WATERMARK_EN, uport->membase + | |
270 | SE_GENI_M_IRQ_CLEAR); | |
271 | qcom_geni_serial_poll_tx_done(uport); | |
272 | } | |
273 | #endif | |
274 | ||
275 | #ifdef CONFIG_SERIAL_QCOM_GENI_CONSOLE | |
276 | static void qcom_geni_serial_wr_char(struct uart_port *uport, int ch) | |
277 | { | |
278 | writel_relaxed(ch, uport->membase + SE_GENI_TX_FIFOn); | |
279 | } | |
280 | ||
281 | static void | |
282 | __qcom_geni_serial_console_write(struct uart_port *uport, const char *s, | |
283 | unsigned int count) | |
284 | { | |
285 | int i; | |
286 | u32 bytes_to_send = count; | |
287 | ||
288 | for (i = 0; i < count; i++) { | |
289 | if (s[i] == '\n') | |
290 | bytes_to_send++; | |
291 | } | |
292 | ||
293 | writel_relaxed(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG); | |
294 | qcom_geni_serial_setup_tx(uport, bytes_to_send); | |
295 | for (i = 0; i < count; ) { | |
296 | size_t chars_to_write = 0; | |
297 | size_t avail = DEF_FIFO_DEPTH_WORDS - DEF_TX_WM; | |
298 | ||
299 | /* | |
300 | * If the WM bit never set, then the Tx state machine is not | |
301 | * in a valid state, so break, cancel/abort any existing | |
302 | * command. Unfortunately the current data being written is | |
303 | * lost. | |
304 | */ | |
305 | if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, | |
306 | M_TX_FIFO_WATERMARK_EN, true)) | |
307 | break; | |
308 | chars_to_write = min_t(size_t, (size_t)(count - i), avail / 2); | |
309 | uart_console_write(uport, s + i, chars_to_write, | |
310 | qcom_geni_serial_wr_char); | |
311 | writel_relaxed(M_TX_FIFO_WATERMARK_EN, uport->membase + | |
312 | SE_GENI_M_IRQ_CLEAR); | |
313 | i += chars_to_write; | |
314 | } | |
315 | qcom_geni_serial_poll_tx_done(uport); | |
316 | } | |
317 | ||
318 | static void qcom_geni_serial_console_write(struct console *co, const char *s, | |
319 | unsigned int count) | |
320 | { | |
321 | struct uart_port *uport; | |
322 | struct qcom_geni_serial_port *port; | |
323 | bool locked = true; | |
324 | unsigned long flags; | |
325 | ||
326 | WARN_ON(co->index < 0 || co->index >= GENI_UART_CONS_PORTS); | |
327 | ||
328 | port = get_port_from_line(co->index); | |
329 | if (IS_ERR(port)) | |
330 | return; | |
331 | ||
332 | uport = &port->uport; | |
333 | if (oops_in_progress) | |
334 | locked = spin_trylock_irqsave(&uport->lock, flags); | |
335 | else | |
336 | spin_lock_irqsave(&uport->lock, flags); | |
337 | ||
338 | /* Cancel the current write to log the fault */ | |
339 | if (!locked) { | |
340 | geni_se_cancel_m_cmd(&port->se); | |
341 | if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, | |
342 | M_CMD_CANCEL_EN, true)) { | |
343 | geni_se_abort_m_cmd(&port->se); | |
344 | qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, | |
345 | M_CMD_ABORT_EN, true); | |
346 | writel_relaxed(M_CMD_ABORT_EN, uport->membase + | |
347 | SE_GENI_M_IRQ_CLEAR); | |
348 | } | |
349 | writel_relaxed(M_CMD_CANCEL_EN, uport->membase + | |
350 | SE_GENI_M_IRQ_CLEAR); | |
351 | } | |
352 | ||
353 | __qcom_geni_serial_console_write(uport, s, count); | |
354 | if (locked) | |
355 | spin_unlock_irqrestore(&uport->lock, flags); | |
356 | } | |
357 | ||
358 | static int handle_rx_console(struct uart_port *uport, u32 bytes, bool drop) | |
359 | { | |
360 | u32 i; | |
361 | unsigned char buf[sizeof(u32)]; | |
362 | struct tty_port *tport; | |
363 | struct qcom_geni_serial_port *port = to_dev_port(uport, uport); | |
364 | ||
365 | tport = &uport->state->port; | |
366 | for (i = 0; i < bytes; ) { | |
367 | int c; | |
368 | int chunk = min_t(int, bytes - i, port->rx_bytes_pw); | |
369 | ||
370 | ioread32_rep(uport->membase + SE_GENI_RX_FIFOn, buf, 1); | |
371 | i += chunk; | |
372 | if (drop) | |
373 | continue; | |
374 | ||
375 | for (c = 0; c < chunk; c++) { | |
376 | int sysrq; | |
377 | ||
378 | uport->icount.rx++; | |
379 | if (port->brk && buf[c] == 0) { | |
380 | port->brk = false; | |
381 | if (uart_handle_break(uport)) | |
382 | continue; | |
383 | } | |
384 | ||
385 | sysrq = uart_handle_sysrq_char(uport, buf[c]); | |
386 | if (!sysrq) | |
387 | tty_insert_flip_char(tport, buf[c], TTY_NORMAL); | |
388 | } | |
389 | } | |
390 | if (!drop) | |
391 | tty_flip_buffer_push(tport); | |
392 | return 0; | |
393 | } | |
394 | #else | |
395 | static int handle_rx_console(struct uart_port *uport, u32 bytes, bool drop) | |
396 | { | |
397 | return -EPERM; | |
398 | } | |
399 | ||
400 | #endif /* CONFIG_SERIAL_QCOM_GENI_CONSOLE */ | |
401 | ||
402 | static void qcom_geni_serial_start_tx(struct uart_port *uport) | |
403 | { | |
404 | u32 irq_en; | |
405 | struct qcom_geni_serial_port *port = to_dev_port(uport, uport); | |
406 | u32 status; | |
407 | ||
408 | if (port->xfer_mode == GENI_SE_FIFO) { | |
409 | status = readl_relaxed(uport->membase + SE_GENI_STATUS); | |
410 | if (status & M_GENI_CMD_ACTIVE) | |
411 | return; | |
412 | ||
413 | if (!qcom_geni_serial_tx_empty(uport)) | |
414 | return; | |
415 | ||
416 | /* | |
417 | * Ensure writing to IRQ_EN & watermark registers are not | |
418 | * re-ordered before checking the status of the Serial | |
419 | * Engine and TX FIFO | |
420 | */ | |
421 | mb(); | |
422 | ||
423 | irq_en = readl_relaxed(uport->membase + SE_GENI_M_IRQ_EN); | |
424 | irq_en |= M_TX_FIFO_WATERMARK_EN | M_CMD_DONE_EN; | |
425 | ||
426 | writel_relaxed(port->tx_wm, uport->membase + | |
427 | SE_GENI_TX_WATERMARK_REG); | |
428 | writel_relaxed(irq_en, uport->membase + SE_GENI_M_IRQ_EN); | |
429 | } | |
430 | } | |
431 | ||
432 | static void qcom_geni_serial_stop_tx(struct uart_port *uport) | |
433 | { | |
434 | u32 irq_en; | |
435 | u32 status; | |
436 | struct qcom_geni_serial_port *port = to_dev_port(uport, uport); | |
437 | ||
438 | irq_en = readl_relaxed(uport->membase + SE_GENI_M_IRQ_EN); | |
439 | irq_en &= ~M_CMD_DONE_EN; | |
440 | if (port->xfer_mode == GENI_SE_FIFO) { | |
441 | irq_en &= ~M_TX_FIFO_WATERMARK_EN; | |
442 | writel_relaxed(0, uport->membase + | |
443 | SE_GENI_TX_WATERMARK_REG); | |
444 | } | |
445 | port->xmit_size = 0; | |
446 | writel_relaxed(irq_en, uport->membase + SE_GENI_M_IRQ_EN); | |
447 | status = readl_relaxed(uport->membase + SE_GENI_STATUS); | |
448 | /* Possible stop tx is called multiple times. */ | |
449 | if (!(status & M_GENI_CMD_ACTIVE)) | |
450 | return; | |
451 | ||
452 | /* | |
453 | * Ensure cancel command write is not re-ordered before checking | |
454 | * the status of the Primary Sequencer. | |
455 | */ | |
456 | mb(); | |
457 | ||
458 | geni_se_cancel_m_cmd(&port->se); | |
459 | if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, | |
460 | M_CMD_CANCEL_EN, true)) { | |
461 | geni_se_abort_m_cmd(&port->se); | |
462 | qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, | |
463 | M_CMD_ABORT_EN, true); | |
464 | writel_relaxed(M_CMD_ABORT_EN, uport->membase + | |
465 | SE_GENI_M_IRQ_CLEAR); | |
466 | } | |
467 | writel_relaxed(M_CMD_CANCEL_EN, uport->membase + SE_GENI_M_IRQ_CLEAR); | |
468 | } | |
469 | ||
470 | static void qcom_geni_serial_start_rx(struct uart_port *uport) | |
471 | { | |
472 | u32 irq_en; | |
473 | u32 status; | |
474 | struct qcom_geni_serial_port *port = to_dev_port(uport, uport); | |
475 | ||
476 | status = readl_relaxed(uport->membase + SE_GENI_STATUS); | |
477 | if (status & S_GENI_CMD_ACTIVE) | |
478 | qcom_geni_serial_stop_rx(uport); | |
479 | ||
480 | /* | |
481 | * Ensure setup command write is not re-ordered before checking | |
482 | * the status of the Secondary Sequencer. | |
483 | */ | |
484 | mb(); | |
485 | ||
486 | geni_se_setup_s_cmd(&port->se, UART_START_READ, 0); | |
487 | ||
488 | if (port->xfer_mode == GENI_SE_FIFO) { | |
489 | irq_en = readl_relaxed(uport->membase + SE_GENI_S_IRQ_EN); | |
490 | irq_en |= S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN; | |
491 | writel_relaxed(irq_en, uport->membase + SE_GENI_S_IRQ_EN); | |
492 | ||
493 | irq_en = readl_relaxed(uport->membase + SE_GENI_M_IRQ_EN); | |
494 | irq_en |= M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN; | |
495 | writel_relaxed(irq_en, uport->membase + SE_GENI_M_IRQ_EN); | |
496 | } | |
497 | } | |
498 | ||
499 | static void qcom_geni_serial_stop_rx(struct uart_port *uport) | |
500 | { | |
501 | u32 irq_en; | |
502 | u32 status; | |
503 | struct qcom_geni_serial_port *port = to_dev_port(uport, uport); | |
504 | u32 irq_clear = S_CMD_DONE_EN; | |
505 | ||
506 | if (port->xfer_mode == GENI_SE_FIFO) { | |
507 | irq_en = readl_relaxed(uport->membase + SE_GENI_S_IRQ_EN); | |
508 | irq_en &= ~(S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN); | |
509 | writel_relaxed(irq_en, uport->membase + SE_GENI_S_IRQ_EN); | |
510 | ||
511 | irq_en = readl_relaxed(uport->membase + SE_GENI_M_IRQ_EN); | |
512 | irq_en &= ~(M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN); | |
513 | writel_relaxed(irq_en, uport->membase + SE_GENI_M_IRQ_EN); | |
514 | } | |
515 | ||
516 | status = readl_relaxed(uport->membase + SE_GENI_STATUS); | |
517 | /* Possible stop rx is called multiple times. */ | |
518 | if (!(status & S_GENI_CMD_ACTIVE)) | |
519 | return; | |
520 | ||
521 | /* | |
522 | * Ensure cancel command write is not re-ordered before checking | |
523 | * the status of the Secondary Sequencer. | |
524 | */ | |
525 | mb(); | |
526 | ||
527 | geni_se_cancel_s_cmd(&port->se); | |
528 | qcom_geni_serial_poll_bit(uport, SE_GENI_S_CMD_CTRL_REG, | |
529 | S_GENI_CMD_CANCEL, false); | |
530 | status = readl_relaxed(uport->membase + SE_GENI_STATUS); | |
531 | writel_relaxed(irq_clear, uport->membase + SE_GENI_S_IRQ_CLEAR); | |
532 | if (status & S_GENI_CMD_ACTIVE) | |
533 | qcom_geni_serial_abort_rx(uport); | |
534 | } | |
535 | ||
536 | static void qcom_geni_serial_handle_rx(struct uart_port *uport, bool drop) | |
537 | { | |
538 | u32 status; | |
539 | u32 word_cnt; | |
540 | u32 last_word_byte_cnt; | |
541 | u32 last_word_partial; | |
542 | u32 total_bytes; | |
543 | struct qcom_geni_serial_port *port = to_dev_port(uport, uport); | |
544 | ||
545 | status = readl_relaxed(uport->membase + SE_GENI_RX_FIFO_STATUS); | |
546 | word_cnt = status & RX_FIFO_WC_MSK; | |
547 | last_word_partial = status & RX_LAST; | |
548 | last_word_byte_cnt = (status & RX_LAST_BYTE_VALID_MSK) >> | |
549 | RX_LAST_BYTE_VALID_SHFT; | |
550 | ||
551 | if (!word_cnt) | |
552 | return; | |
553 | total_bytes = port->rx_bytes_pw * (word_cnt - 1); | |
554 | if (last_word_partial && last_word_byte_cnt) | |
555 | total_bytes += last_word_byte_cnt; | |
556 | else | |
557 | total_bytes += port->rx_bytes_pw; | |
558 | port->handle_rx(uport, total_bytes, drop); | |
559 | } | |
560 | ||
561 | static void qcom_geni_serial_handle_tx(struct uart_port *uport) | |
562 | { | |
563 | struct qcom_geni_serial_port *port = to_dev_port(uport, uport); | |
564 | struct circ_buf *xmit = &uport->state->xmit; | |
565 | size_t avail; | |
566 | size_t remaining; | |
567 | int i; | |
568 | u32 status; | |
569 | unsigned int chunk; | |
570 | int tail; | |
571 | ||
572 | chunk = uart_circ_chars_pending(xmit); | |
573 | status = readl_relaxed(uport->membase + SE_GENI_TX_FIFO_STATUS); | |
574 | /* Both FIFO and framework buffer are drained */ | |
575 | if (chunk == port->xmit_size && !status) { | |
576 | port->xmit_size = 0; | |
577 | uart_circ_clear(xmit); | |
578 | qcom_geni_serial_stop_tx(uport); | |
579 | goto out_write_wakeup; | |
580 | } | |
581 | chunk -= port->xmit_size; | |
582 | ||
583 | avail = (port->tx_fifo_depth - port->tx_wm) * port->tx_bytes_pw; | |
584 | tail = (xmit->tail + port->xmit_size) & (UART_XMIT_SIZE - 1); | |
585 | if (chunk > (UART_XMIT_SIZE - tail)) | |
586 | chunk = UART_XMIT_SIZE - tail; | |
587 | if (chunk > avail) | |
588 | chunk = avail; | |
589 | ||
590 | if (!chunk) | |
591 | goto out_write_wakeup; | |
592 | ||
593 | qcom_geni_serial_setup_tx(uport, chunk); | |
594 | ||
595 | remaining = chunk; | |
596 | for (i = 0; i < chunk; ) { | |
597 | unsigned int tx_bytes; | |
598 | unsigned int buf = 0; | |
599 | int c; | |
600 | ||
601 | tx_bytes = min_t(size_t, remaining, (size_t)port->tx_bytes_pw); | |
602 | for (c = 0; c < tx_bytes ; c++) | |
603 | buf |= (xmit->buf[tail + c] << (c * BITS_PER_BYTE)); | |
604 | ||
605 | writel_relaxed(buf, uport->membase + SE_GENI_TX_FIFOn); | |
606 | ||
607 | i += tx_bytes; | |
608 | tail = (tail + tx_bytes) & (UART_XMIT_SIZE - 1); | |
609 | uport->icount.tx += tx_bytes; | |
610 | remaining -= tx_bytes; | |
611 | } | |
612 | qcom_geni_serial_poll_tx_done(uport); | |
613 | port->xmit_size += chunk; | |
614 | out_write_wakeup: | |
615 | uart_write_wakeup(uport); | |
616 | } | |
617 | ||
618 | static irqreturn_t qcom_geni_serial_isr(int isr, void *dev) | |
619 | { | |
620 | unsigned int m_irq_status; | |
621 | unsigned int s_irq_status; | |
622 | struct uart_port *uport = dev; | |
623 | unsigned long flags; | |
624 | unsigned int m_irq_en; | |
625 | bool drop_rx = false; | |
626 | struct tty_port *tport = &uport->state->port; | |
627 | struct qcom_geni_serial_port *port = to_dev_port(uport, uport); | |
628 | ||
629 | if (uport->suspended) | |
630 | return IRQ_HANDLED; | |
631 | ||
632 | spin_lock_irqsave(&uport->lock, flags); | |
633 | m_irq_status = readl_relaxed(uport->membase + SE_GENI_M_IRQ_STATUS); | |
634 | s_irq_status = readl_relaxed(uport->membase + SE_GENI_S_IRQ_STATUS); | |
635 | m_irq_en = readl_relaxed(uport->membase + SE_GENI_M_IRQ_EN); | |
636 | writel_relaxed(m_irq_status, uport->membase + SE_GENI_M_IRQ_CLEAR); | |
637 | writel_relaxed(s_irq_status, uport->membase + SE_GENI_S_IRQ_CLEAR); | |
638 | ||
639 | if (WARN_ON(m_irq_status & M_ILLEGAL_CMD_EN)) | |
640 | goto out_unlock; | |
641 | ||
642 | if (s_irq_status & S_RX_FIFO_WR_ERR_EN) { | |
643 | uport->icount.overrun++; | |
644 | tty_insert_flip_char(tport, 0, TTY_OVERRUN); | |
645 | } | |
646 | ||
647 | if (m_irq_status & (M_TX_FIFO_WATERMARK_EN | M_CMD_DONE_EN) && | |
648 | m_irq_en & (M_TX_FIFO_WATERMARK_EN | M_CMD_DONE_EN)) | |
649 | qcom_geni_serial_handle_tx(uport); | |
650 | ||
651 | if (s_irq_status & S_GP_IRQ_0_EN || s_irq_status & S_GP_IRQ_1_EN) { | |
652 | if (s_irq_status & S_GP_IRQ_0_EN) | |
653 | uport->icount.parity++; | |
654 | drop_rx = true; | |
655 | } else if (s_irq_status & S_GP_IRQ_2_EN || | |
656 | s_irq_status & S_GP_IRQ_3_EN) { | |
657 | uport->icount.brk++; | |
658 | port->brk = true; | |
659 | } | |
660 | ||
661 | if (s_irq_status & S_RX_FIFO_WATERMARK_EN || | |
662 | s_irq_status & S_RX_FIFO_LAST_EN) | |
663 | qcom_geni_serial_handle_rx(uport, drop_rx); | |
664 | ||
665 | out_unlock: | |
666 | spin_unlock_irqrestore(&uport->lock, flags); | |
667 | return IRQ_HANDLED; | |
668 | } | |
669 | ||
670 | static int get_tx_fifo_size(struct qcom_geni_serial_port *port) | |
671 | { | |
672 | struct uart_port *uport; | |
673 | ||
674 | if (!port) | |
675 | return -ENODEV; | |
676 | ||
677 | uport = &port->uport; | |
678 | port->tx_fifo_depth = geni_se_get_tx_fifo_depth(&port->se); | |
679 | port->tx_fifo_width = geni_se_get_tx_fifo_width(&port->se); | |
680 | port->rx_fifo_depth = geni_se_get_rx_fifo_depth(&port->se); | |
681 | uport->fifosize = | |
682 | (port->tx_fifo_depth * port->tx_fifo_width) / BITS_PER_BYTE; | |
683 | return 0; | |
684 | } | |
685 | ||
686 | static void set_rfr_wm(struct qcom_geni_serial_port *port) | |
687 | { | |
688 | /* | |
689 | * Set RFR (Flow off) to FIFO_DEPTH - 2. | |
690 | * RX WM level at 10% RX_FIFO_DEPTH. | |
691 | * TX WM level at 10% TX_FIFO_DEPTH. | |
692 | */ | |
693 | port->rx_rfr = port->rx_fifo_depth - 2; | |
694 | port->rx_wm = UART_CONSOLE_RX_WM; | |
695 | port->tx_wm = DEF_TX_WM; | |
696 | } | |
697 | ||
698 | static void qcom_geni_serial_shutdown(struct uart_port *uport) | |
699 | { | |
700 | unsigned long flags; | |
701 | ||
702 | /* Stop the console before stopping the current tx */ | |
703 | console_stop(uport->cons); | |
704 | ||
705 | disable_irq(uport->irq); | |
706 | free_irq(uport->irq, uport); | |
707 | spin_lock_irqsave(&uport->lock, flags); | |
708 | qcom_geni_serial_stop_tx(uport); | |
709 | qcom_geni_serial_stop_rx(uport); | |
710 | spin_unlock_irqrestore(&uport->lock, flags); | |
711 | } | |
712 | ||
713 | static int qcom_geni_serial_port_setup(struct uart_port *uport) | |
714 | { | |
715 | struct qcom_geni_serial_port *port = to_dev_port(uport, uport); | |
716 | unsigned int rxstale = DEFAULT_BITS_PER_CHAR * STALE_TIMEOUT; | |
717 | ||
718 | set_rfr_wm(port); | |
719 | writel_relaxed(rxstale, uport->membase + SE_UART_RX_STALE_CNT); | |
720 | /* | |
721 | * Make an unconditional cancel on the main sequencer to reset | |
722 | * it else we could end up in data loss scenarios. | |
723 | */ | |
724 | port->xfer_mode = GENI_SE_FIFO; | |
725 | qcom_geni_serial_poll_tx_done(uport); | |
726 | geni_se_config_packing(&port->se, BITS_PER_BYTE, port->tx_bytes_pw, | |
727 | false, true, false); | |
728 | geni_se_config_packing(&port->se, BITS_PER_BYTE, port->rx_bytes_pw, | |
729 | false, false, true); | |
730 | geni_se_init(&port->se, port->rx_wm, port->rx_rfr); | |
731 | geni_se_select_mode(&port->se, port->xfer_mode); | |
732 | port->setup = true; | |
733 | return 0; | |
734 | } | |
735 | ||
736 | static int qcom_geni_serial_startup(struct uart_port *uport) | |
737 | { | |
738 | int ret; | |
739 | u32 proto; | |
740 | struct qcom_geni_serial_port *port = to_dev_port(uport, uport); | |
741 | ||
742 | scnprintf(port->name, sizeof(port->name), | |
743 | "qcom_serial_geni%d", uport->line); | |
744 | ||
745 | proto = geni_se_read_proto(&port->se); | |
746 | if (proto != GENI_SE_UART) { | |
747 | dev_err(uport->dev, "Invalid FW loaded, proto: %d\n", proto); | |
748 | return -ENXIO; | |
749 | } | |
750 | ||
751 | get_tx_fifo_size(port); | |
752 | if (!port->setup) { | |
753 | ret = qcom_geni_serial_port_setup(uport); | |
754 | if (ret) | |
755 | return ret; | |
756 | } | |
757 | ||
758 | ret = request_irq(uport->irq, qcom_geni_serial_isr, IRQF_TRIGGER_HIGH, | |
759 | port->name, uport); | |
760 | if (ret) | |
761 | dev_err(uport->dev, "Failed to get IRQ ret %d\n", ret); | |
762 | return ret; | |
763 | } | |
764 | ||
765 | static unsigned long get_clk_cfg(unsigned long clk_freq) | |
766 | { | |
767 | int i; | |
768 | ||
769 | for (i = 0; i < ARRAY_SIZE(root_freq); i++) { | |
770 | if (!(root_freq[i] % clk_freq)) | |
771 | return root_freq[i]; | |
772 | } | |
773 | return 0; | |
774 | } | |
775 | ||
776 | static unsigned long get_clk_div_rate(unsigned int baud, unsigned int *clk_div) | |
777 | { | |
778 | unsigned long ser_clk; | |
779 | unsigned long desired_clk; | |
780 | ||
781 | desired_clk = baud * UART_OVERSAMPLING; | |
782 | ser_clk = get_clk_cfg(desired_clk); | |
783 | if (!ser_clk) { | |
784 | pr_err("%s: Can't find matching DFS entry for baud %d\n", | |
785 | __func__, baud); | |
786 | return ser_clk; | |
787 | } | |
788 | ||
789 | *clk_div = ser_clk / desired_clk; | |
790 | return ser_clk; | |
791 | } | |
792 | ||
793 | static void qcom_geni_serial_set_termios(struct uart_port *uport, | |
794 | struct ktermios *termios, struct ktermios *old) | |
795 | { | |
796 | unsigned int baud; | |
797 | unsigned int bits_per_char; | |
798 | unsigned int tx_trans_cfg; | |
799 | unsigned int tx_parity_cfg; | |
800 | unsigned int rx_trans_cfg; | |
801 | unsigned int rx_parity_cfg; | |
802 | unsigned int stop_bit_len; | |
803 | unsigned int clk_div; | |
804 | unsigned long ser_clk_cfg; | |
805 | struct qcom_geni_serial_port *port = to_dev_port(uport, uport); | |
806 | unsigned long clk_rate; | |
807 | ||
808 | qcom_geni_serial_stop_rx(uport); | |
809 | /* baud rate */ | |
810 | baud = uart_get_baud_rate(uport, termios, old, 300, 4000000); | |
811 | port->baud = baud; | |
812 | clk_rate = get_clk_div_rate(baud, &clk_div); | |
813 | if (!clk_rate) | |
814 | goto out_restart_rx; | |
815 | ||
816 | uport->uartclk = clk_rate; | |
817 | clk_set_rate(port->se.clk, clk_rate); | |
818 | ser_clk_cfg = SER_CLK_EN; | |
819 | ser_clk_cfg |= clk_div << CLK_DIV_SHFT; | |
820 | ||
821 | /* parity */ | |
822 | tx_trans_cfg = readl_relaxed(uport->membase + SE_UART_TX_TRANS_CFG); | |
823 | tx_parity_cfg = readl_relaxed(uport->membase + SE_UART_TX_PARITY_CFG); | |
824 | rx_trans_cfg = readl_relaxed(uport->membase + SE_UART_RX_TRANS_CFG); | |
825 | rx_parity_cfg = readl_relaxed(uport->membase + SE_UART_RX_PARITY_CFG); | |
826 | if (termios->c_cflag & PARENB) { | |
827 | tx_trans_cfg |= UART_TX_PAR_EN; | |
828 | rx_trans_cfg |= UART_RX_PAR_EN; | |
829 | tx_parity_cfg |= PAR_CALC_EN; | |
830 | rx_parity_cfg |= PAR_CALC_EN; | |
831 | if (termios->c_cflag & PARODD) { | |
832 | tx_parity_cfg |= PAR_ODD; | |
833 | rx_parity_cfg |= PAR_ODD; | |
834 | } else if (termios->c_cflag & CMSPAR) { | |
835 | tx_parity_cfg |= PAR_SPACE; | |
836 | rx_parity_cfg |= PAR_SPACE; | |
837 | } else { | |
838 | tx_parity_cfg |= PAR_EVEN; | |
839 | rx_parity_cfg |= PAR_EVEN; | |
840 | } | |
841 | } else { | |
842 | tx_trans_cfg &= ~UART_TX_PAR_EN; | |
843 | rx_trans_cfg &= ~UART_RX_PAR_EN; | |
844 | tx_parity_cfg &= ~PAR_CALC_EN; | |
845 | rx_parity_cfg &= ~PAR_CALC_EN; | |
846 | } | |
847 | ||
848 | /* bits per char */ | |
849 | switch (termios->c_cflag & CSIZE) { | |
850 | case CS5: | |
851 | bits_per_char = 5; | |
852 | break; | |
853 | case CS6: | |
854 | bits_per_char = 6; | |
855 | break; | |
856 | case CS7: | |
857 | bits_per_char = 7; | |
858 | break; | |
859 | case CS8: | |
860 | default: | |
861 | bits_per_char = 8; | |
862 | break; | |
863 | } | |
864 | ||
865 | /* stop bits */ | |
866 | if (termios->c_cflag & CSTOPB) | |
867 | stop_bit_len = TX_STOP_BIT_LEN_2; | |
868 | else | |
869 | stop_bit_len = TX_STOP_BIT_LEN_1; | |
870 | ||
871 | /* flow control, clear the CTS_MASK bit if using flow control. */ | |
872 | if (termios->c_cflag & CRTSCTS) | |
873 | tx_trans_cfg &= ~UART_CTS_MASK; | |
874 | else | |
875 | tx_trans_cfg |= UART_CTS_MASK; | |
876 | ||
877 | if (baud) | |
878 | uart_update_timeout(uport, termios->c_cflag, baud); | |
879 | ||
880 | writel_relaxed(tx_trans_cfg, uport->membase + SE_UART_TX_TRANS_CFG); | |
881 | writel_relaxed(tx_parity_cfg, uport->membase + SE_UART_TX_PARITY_CFG); | |
882 | writel_relaxed(rx_trans_cfg, uport->membase + SE_UART_RX_TRANS_CFG); | |
883 | writel_relaxed(rx_parity_cfg, uport->membase + SE_UART_RX_PARITY_CFG); | |
884 | writel_relaxed(bits_per_char, uport->membase + SE_UART_TX_WORD_LEN); | |
885 | writel_relaxed(bits_per_char, uport->membase + SE_UART_RX_WORD_LEN); | |
886 | writel_relaxed(stop_bit_len, uport->membase + SE_UART_TX_STOP_BIT_LEN); | |
887 | writel_relaxed(ser_clk_cfg, uport->membase + GENI_SER_M_CLK_CFG); | |
888 | writel_relaxed(ser_clk_cfg, uport->membase + GENI_SER_S_CLK_CFG); | |
889 | out_restart_rx: | |
890 | qcom_geni_serial_start_rx(uport); | |
891 | } | |
892 | ||
893 | static unsigned int qcom_geni_serial_tx_empty(struct uart_port *uport) | |
894 | { | |
895 | return !readl_relaxed(uport->membase + SE_GENI_TX_FIFO_STATUS); | |
896 | } | |
897 | ||
898 | #ifdef CONFIG_SERIAL_QCOM_GENI_CONSOLE | |
899 | static int __init qcom_geni_console_setup(struct console *co, char *options) | |
900 | { | |
901 | struct uart_port *uport; | |
902 | struct qcom_geni_serial_port *port; | |
903 | int baud; | |
904 | int bits = 8; | |
905 | int parity = 'n'; | |
906 | int flow = 'n'; | |
907 | ||
908 | if (co->index >= GENI_UART_CONS_PORTS || co->index < 0) | |
909 | return -ENXIO; | |
910 | ||
911 | port = get_port_from_line(co->index); | |
912 | if (IS_ERR(port)) { | |
913 | pr_err("Invalid line %d(%d)\n", co->index, (int)PTR_ERR(port)); | |
914 | return PTR_ERR(port); | |
915 | } | |
916 | ||
917 | uport = &port->uport; | |
918 | ||
919 | if (unlikely(!uport->membase)) | |
920 | return -ENXIO; | |
921 | ||
922 | if (geni_se_resources_on(&port->se)) { | |
923 | dev_err(port->se.dev, "Error turning on resources\n"); | |
924 | return -ENXIO; | |
925 | } | |
926 | ||
927 | if (unlikely(geni_se_read_proto(&port->se) != GENI_SE_UART)) { | |
928 | geni_se_resources_off(&port->se); | |
929 | return -ENXIO; | |
930 | } | |
931 | ||
932 | if (!port->setup) { | |
933 | port->tx_bytes_pw = 1; | |
934 | port->rx_bytes_pw = RX_BYTES_PW; | |
935 | qcom_geni_serial_stop_rx(uport); | |
936 | qcom_geni_serial_port_setup(uport); | |
937 | } | |
938 | ||
939 | if (options) | |
940 | uart_parse_options(options, &baud, &parity, &bits, &flow); | |
941 | ||
942 | return uart_set_options(uport, co, baud, parity, bits, flow); | |
943 | } | |
944 | ||
945 | static int __init console_register(struct uart_driver *drv) | |
946 | { | |
947 | return uart_register_driver(drv); | |
948 | } | |
949 | ||
950 | static void console_unregister(struct uart_driver *drv) | |
951 | { | |
952 | uart_unregister_driver(drv); | |
953 | } | |
954 | ||
955 | static struct console cons_ops = { | |
956 | .name = "ttyMSM", | |
957 | .write = qcom_geni_serial_console_write, | |
958 | .device = uart_console_device, | |
959 | .setup = qcom_geni_console_setup, | |
960 | .flags = CON_PRINTBUFFER, | |
961 | .index = -1, | |
962 | .data = &qcom_geni_console_driver, | |
963 | }; | |
964 | ||
965 | static struct uart_driver qcom_geni_console_driver = { | |
966 | .owner = THIS_MODULE, | |
967 | .driver_name = "qcom_geni_console", | |
968 | .dev_name = "ttyMSM", | |
969 | .nr = GENI_UART_CONS_PORTS, | |
970 | .cons = &cons_ops, | |
971 | }; | |
972 | #else | |
973 | static int console_register(struct uart_driver *drv) | |
974 | { | |
975 | return 0; | |
976 | } | |
977 | ||
978 | static void console_unregister(struct uart_driver *drv) | |
979 | { | |
980 | } | |
981 | #endif /* CONFIG_SERIAL_QCOM_GENI_CONSOLE */ | |
982 | ||
983 | static void qcom_geni_serial_cons_pm(struct uart_port *uport, | |
984 | unsigned int new_state, unsigned int old_state) | |
985 | { | |
986 | struct qcom_geni_serial_port *port = to_dev_port(uport, uport); | |
987 | ||
988 | if (unlikely(!uart_console(uport))) | |
989 | return; | |
990 | ||
991 | if (new_state == UART_PM_STATE_ON && old_state == UART_PM_STATE_OFF) | |
992 | geni_se_resources_on(&port->se); | |
993 | else if (new_state == UART_PM_STATE_OFF && | |
994 | old_state == UART_PM_STATE_ON) | |
995 | geni_se_resources_off(&port->se); | |
996 | } | |
997 | ||
998 | static const struct uart_ops qcom_geni_console_pops = { | |
999 | .tx_empty = qcom_geni_serial_tx_empty, | |
1000 | .stop_tx = qcom_geni_serial_stop_tx, | |
1001 | .start_tx = qcom_geni_serial_start_tx, | |
1002 | .stop_rx = qcom_geni_serial_stop_rx, | |
1003 | .set_termios = qcom_geni_serial_set_termios, | |
1004 | .startup = qcom_geni_serial_startup, | |
1005 | .request_port = qcom_geni_serial_request_port, | |
1006 | .config_port = qcom_geni_serial_config_port, | |
1007 | .shutdown = qcom_geni_serial_shutdown, | |
1008 | .type = qcom_geni_serial_get_type, | |
1009 | .set_mctrl = qcom_geni_cons_set_mctrl, | |
1010 | .get_mctrl = qcom_geni_cons_get_mctrl, | |
1011 | #ifdef CONFIG_CONSOLE_POLL | |
1012 | .poll_get_char = qcom_geni_serial_get_char, | |
1013 | .poll_put_char = qcom_geni_serial_poll_put_char, | |
1014 | #endif | |
1015 | .pm = qcom_geni_serial_cons_pm, | |
1016 | }; | |
1017 | ||
1018 | static int qcom_geni_serial_probe(struct platform_device *pdev) | |
1019 | { | |
1020 | int ret = 0; | |
1021 | int line = -1; | |
1022 | struct qcom_geni_serial_port *port; | |
1023 | struct uart_port *uport; | |
1024 | struct resource *res; | |
1025 | ||
1026 | if (pdev->dev.of_node) | |
1027 | line = of_alias_get_id(pdev->dev.of_node, "serial"); | |
1028 | else | |
1029 | line = pdev->id; | |
1030 | ||
1031 | if (line < 0 || line >= GENI_UART_CONS_PORTS) | |
1032 | return -ENXIO; | |
1033 | port = get_port_from_line(line); | |
1034 | if (IS_ERR(port)) { | |
1035 | ret = PTR_ERR(port); | |
1036 | dev_err(&pdev->dev, "Invalid line %d(%d)\n", line, ret); | |
1037 | return ret; | |
1038 | } | |
1039 | ||
1040 | uport = &port->uport; | |
1041 | /* Don't allow 2 drivers to access the same port */ | |
1042 | if (uport->private_data) | |
1043 | return -ENODEV; | |
1044 | ||
1045 | uport->dev = &pdev->dev; | |
1046 | port->se.dev = &pdev->dev; | |
1047 | port->se.wrapper = dev_get_drvdata(pdev->dev.parent); | |
1048 | port->se.clk = devm_clk_get(&pdev->dev, "se"); | |
1049 | if (IS_ERR(port->se.clk)) { | |
1050 | ret = PTR_ERR(port->se.clk); | |
1051 | dev_err(&pdev->dev, "Err getting SE Core clk %d\n", ret); | |
1052 | return ret; | |
1053 | } | |
1054 | ||
1055 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
7693b331 WY |
1056 | if (!res) |
1057 | return -EINVAL; | |
c4f52879 KR |
1058 | uport->mapbase = res->start; |
1059 | ||
1060 | port->tx_fifo_depth = DEF_FIFO_DEPTH_WORDS; | |
1061 | port->rx_fifo_depth = DEF_FIFO_DEPTH_WORDS; | |
1062 | port->tx_fifo_width = DEF_FIFO_WIDTH_BITS; | |
1063 | ||
1064 | uport->irq = platform_get_irq(pdev, 0); | |
1065 | if (uport->irq < 0) { | |
1066 | dev_err(&pdev->dev, "Failed to get IRQ %d\n", uport->irq); | |
1067 | return uport->irq; | |
1068 | } | |
1069 | ||
1070 | uport->private_data = &qcom_geni_console_driver; | |
1071 | platform_set_drvdata(pdev, port); | |
1072 | port->handle_rx = handle_rx_console; | |
1073 | port->setup = false; | |
1074 | return uart_add_one_port(&qcom_geni_console_driver, uport); | |
1075 | } | |
1076 | ||
1077 | static int qcom_geni_serial_remove(struct platform_device *pdev) | |
1078 | { | |
1079 | struct qcom_geni_serial_port *port = platform_get_drvdata(pdev); | |
1080 | struct uart_driver *drv = port->uport.private_data; | |
1081 | ||
1082 | uart_remove_one_port(drv, &port->uport); | |
1083 | return 0; | |
1084 | } | |
1085 | ||
1086 | static int __maybe_unused qcom_geni_serial_sys_suspend_noirq(struct device *dev) | |
1087 | { | |
1088 | struct platform_device *pdev = to_platform_device(dev); | |
1089 | struct qcom_geni_serial_port *port = platform_get_drvdata(pdev); | |
1090 | struct uart_port *uport = &port->uport; | |
1091 | ||
1092 | uart_suspend_port(uport->private_data, uport); | |
1093 | return 0; | |
1094 | } | |
1095 | ||
1096 | static int __maybe_unused qcom_geni_serial_sys_resume_noirq(struct device *dev) | |
1097 | { | |
1098 | struct platform_device *pdev = to_platform_device(dev); | |
1099 | struct qcom_geni_serial_port *port = platform_get_drvdata(pdev); | |
1100 | struct uart_port *uport = &port->uport; | |
1101 | ||
1102 | if (console_suspend_enabled && uport->suspended) { | |
1103 | uart_resume_port(uport->private_data, uport); | |
1104 | disable_irq(uport->irq); | |
1105 | } | |
1106 | return 0; | |
1107 | } | |
1108 | ||
1109 | static const struct dev_pm_ops qcom_geni_serial_pm_ops = { | |
1110 | SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(qcom_geni_serial_sys_suspend_noirq, | |
1111 | qcom_geni_serial_sys_resume_noirq) | |
1112 | }; | |
1113 | ||
1114 | static const struct of_device_id qcom_geni_serial_match_table[] = { | |
1115 | { .compatible = "qcom,geni-debug-uart", }, | |
1116 | {} | |
1117 | }; | |
1118 | MODULE_DEVICE_TABLE(of, qcom_geni_serial_match_table); | |
1119 | ||
1120 | static struct platform_driver qcom_geni_serial_platform_driver = { | |
1121 | .remove = qcom_geni_serial_remove, | |
1122 | .probe = qcom_geni_serial_probe, | |
1123 | .driver = { | |
1124 | .name = "qcom_geni_serial", | |
1125 | .of_match_table = qcom_geni_serial_match_table, | |
1126 | .pm = &qcom_geni_serial_pm_ops, | |
1127 | }, | |
1128 | }; | |
1129 | ||
1130 | static int __init qcom_geni_serial_init(void) | |
1131 | { | |
1132 | int ret; | |
1133 | ||
1134 | qcom_geni_console_port.uport.iotype = UPIO_MEM; | |
1135 | qcom_geni_console_port.uport.ops = &qcom_geni_console_pops; | |
1136 | qcom_geni_console_port.uport.flags = UPF_BOOT_AUTOCONF; | |
1137 | qcom_geni_console_port.uport.line = 0; | |
1138 | ||
1139 | ret = console_register(&qcom_geni_console_driver); | |
1140 | if (ret) | |
1141 | return ret; | |
1142 | ||
1143 | ret = platform_driver_register(&qcom_geni_serial_platform_driver); | |
1144 | if (ret) | |
1145 | console_unregister(&qcom_geni_console_driver); | |
1146 | return ret; | |
1147 | } | |
1148 | module_init(qcom_geni_serial_init); | |
1149 | ||
1150 | static void __exit qcom_geni_serial_exit(void) | |
1151 | { | |
1152 | platform_driver_unregister(&qcom_geni_serial_platform_driver); | |
1153 | console_unregister(&qcom_geni_console_driver); | |
1154 | } | |
1155 | module_exit(qcom_geni_serial_exit); | |
1156 | ||
1157 | MODULE_DESCRIPTION("Serial driver for GENI based QUP cores"); | |
1158 | MODULE_LICENSE("GPL v2"); |