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c4f52879 KR |
1 | // SPDX-License-Identifier: GPL-2.0 |
2 | // Copyright (c) 2017-2018, The Linux foundation. All rights reserved. | |
3 | ||
60457d5e SPR |
4 | /* Disable MMIO tracing to prevent excessive logging of unwanted MMIO traces */ |
5 | #define __DISABLE_TRACE_MMIO__ | |
c4f52879 KR |
6 | |
7 | #include <linux/clk.h> | |
8 | #include <linux/console.h> | |
9 | #include <linux/io.h> | |
10 | #include <linux/iopoll.h> | |
3e4aaea7 | 11 | #include <linux/irq.h> |
c4f52879 KR |
12 | #include <linux/module.h> |
13 | #include <linux/of.h> | |
14 | #include <linux/of_device.h> | |
a5819b54 | 15 | #include <linux/pm_opp.h> |
c4f52879 | 16 | #include <linux/platform_device.h> |
f3974413 | 17 | #include <linux/pm_runtime.h> |
8b7103f3 | 18 | #include <linux/pm_wakeirq.h> |
c4f52879 KR |
19 | #include <linux/qcom-geni-se.h> |
20 | #include <linux/serial.h> | |
21 | #include <linux/serial_core.h> | |
22 | #include <linux/slab.h> | |
23 | #include <linux/tty.h> | |
24 | #include <linux/tty_flip.h> | |
408e532e | 25 | #include <dt-bindings/interconnect/qcom,icc.h> |
c4f52879 KR |
26 | |
27 | /* UART specific GENI registers */ | |
8a8a66a1 | 28 | #define SE_UART_LOOPBACK_CFG 0x22c |
9fa3c4b1 | 29 | #define SE_UART_IO_MACRO_CTRL 0x240 |
c4f52879 KR |
30 | #define SE_UART_TX_TRANS_CFG 0x25c |
31 | #define SE_UART_TX_WORD_LEN 0x268 | |
32 | #define SE_UART_TX_STOP_BIT_LEN 0x26c | |
33 | #define SE_UART_TX_TRANS_LEN 0x270 | |
34 | #define SE_UART_RX_TRANS_CFG 0x280 | |
35 | #define SE_UART_RX_WORD_LEN 0x28c | |
36 | #define SE_UART_RX_STALE_CNT 0x294 | |
37 | #define SE_UART_TX_PARITY_CFG 0x2a4 | |
38 | #define SE_UART_RX_PARITY_CFG 0x2a8 | |
8a8a66a1 | 39 | #define SE_UART_MANUAL_RFR 0x2ac |
c4f52879 KR |
40 | |
41 | /* SE_UART_TRANS_CFG */ | |
42 | #define UART_TX_PAR_EN BIT(0) | |
43 | #define UART_CTS_MASK BIT(1) | |
44 | ||
45 | /* SE_UART_TX_WORD_LEN */ | |
46 | #define TX_WORD_LEN_MSK GENMASK(9, 0) | |
47 | ||
48 | /* SE_UART_TX_STOP_BIT_LEN */ | |
49 | #define TX_STOP_BIT_LEN_MSK GENMASK(23, 0) | |
50 | #define TX_STOP_BIT_LEN_1 0 | |
51 | #define TX_STOP_BIT_LEN_1_5 1 | |
52 | #define TX_STOP_BIT_LEN_2 2 | |
53 | ||
54 | /* SE_UART_TX_TRANS_LEN */ | |
55 | #define TX_TRANS_LEN_MSK GENMASK(23, 0) | |
56 | ||
57 | /* SE_UART_RX_TRANS_CFG */ | |
58 | #define UART_RX_INS_STATUS_BIT BIT(2) | |
59 | #define UART_RX_PAR_EN BIT(3) | |
60 | ||
61 | /* SE_UART_RX_WORD_LEN */ | |
62 | #define RX_WORD_LEN_MASK GENMASK(9, 0) | |
63 | ||
64 | /* SE_UART_RX_STALE_CNT */ | |
65 | #define RX_STALE_CNT GENMASK(23, 0) | |
66 | ||
67 | /* SE_UART_TX_PARITY_CFG/RX_PARITY_CFG */ | |
68 | #define PAR_CALC_EN BIT(0) | |
69 | #define PAR_MODE_MSK GENMASK(2, 1) | |
70 | #define PAR_MODE_SHFT 1 | |
71 | #define PAR_EVEN 0x00 | |
72 | #define PAR_ODD 0x01 | |
73 | #define PAR_SPACE 0x10 | |
74 | #define PAR_MARK 0x11 | |
75 | ||
8a8a66a1 GM |
76 | /* SE_UART_MANUAL_RFR register fields */ |
77 | #define UART_MANUAL_RFR_EN BIT(31) | |
78 | #define UART_RFR_NOT_READY BIT(1) | |
79 | #define UART_RFR_READY BIT(0) | |
80 | ||
c4f52879 KR |
81 | /* UART M_CMD OP codes */ |
82 | #define UART_START_TX 0x1 | |
83 | #define UART_START_BREAK 0x4 | |
84 | #define UART_STOP_BREAK 0x5 | |
85 | /* UART S_CMD OP codes */ | |
86 | #define UART_START_READ 0x1 | |
87 | #define UART_PARAM 0x1 | |
88 | ||
89 | #define UART_OVERSAMPLING 32 | |
90 | #define STALE_TIMEOUT 16 | |
91 | #define DEFAULT_BITS_PER_CHAR 10 | |
92 | #define GENI_UART_CONS_PORTS 1 | |
8a8a66a1 | 93 | #define GENI_UART_PORTS 3 |
c4f52879 KR |
94 | #define DEF_FIFO_DEPTH_WORDS 16 |
95 | #define DEF_TX_WM 2 | |
96 | #define DEF_FIFO_WIDTH_BITS 32 | |
a85fb9ce | 97 | #define UART_RX_WM 2 |
69bd1a4f AA |
98 | |
99 | /* SE_UART_LOOPBACK_CFG */ | |
100 | #define RX_TX_SORTED BIT(0) | |
101 | #define CTS_RTS_SORTED BIT(1) | |
102 | #define RX_TX_CTS_RTS_SORTED (RX_TX_SORTED | CTS_RTS_SORTED) | |
c4f52879 | 103 | |
9fa3c4b1 RRY |
104 | /* UART pin swap value */ |
105 | #define DEFAULT_IO_MACRO_IO0_IO1_MASK GENMASK(3, 0) | |
106 | #define IO_MACRO_IO0_SEL 0x3 | |
107 | #define DEFAULT_IO_MACRO_IO2_IO3_MASK GENMASK(15, 4) | |
108 | #define IO_MACRO_IO2_IO3_SWAP 0x4640 | |
109 | ||
650c8bd3 DA |
110 | /* We always configure 4 bytes per FIFO word */ |
111 | #define BYTES_PER_FIFO_WORD 4 | |
112 | ||
e42d6c3e DA |
113 | struct qcom_geni_private_data { |
114 | /* NOTE: earlycon port will have NULL here */ | |
115 | struct uart_driver *drv; | |
116 | ||
117 | u32 poll_cached_bytes; | |
118 | unsigned int poll_cached_bytes_cnt; | |
650c8bd3 DA |
119 | |
120 | u32 write_cached_bytes; | |
121 | unsigned int write_cached_bytes_cnt; | |
e42d6c3e | 122 | }; |
c4f52879 KR |
123 | |
124 | struct qcom_geni_serial_port { | |
125 | struct uart_port uport; | |
126 | struct geni_se se; | |
f3974413 | 127 | const char *name; |
c4f52879 KR |
128 | u32 tx_fifo_depth; |
129 | u32 tx_fifo_width; | |
130 | u32 rx_fifo_depth; | |
c4f52879 KR |
131 | bool setup; |
132 | int (*handle_rx)(struct uart_port *uport, u32 bytes, bool drop); | |
c4f52879 | 133 | unsigned int baud; |
f9d690b6 | 134 | void *rx_fifo; |
8a8a66a1 | 135 | u32 loopback; |
c4f52879 | 136 | bool brk; |
a1fee899 RC |
137 | |
138 | unsigned int tx_remaining; | |
8b7103f3 | 139 | int wakeup_irq; |
9fa3c4b1 RRY |
140 | bool rx_tx_swap; |
141 | bool cts_rts_swap; | |
e42d6c3e DA |
142 | |
143 | struct qcom_geni_private_data private_data; | |
c4f52879 KR |
144 | }; |
145 | ||
f7371750 | 146 | static const struct uart_ops qcom_geni_console_pops; |
8a8a66a1 | 147 | static const struct uart_ops qcom_geni_uart_pops; |
c4f52879 | 148 | static struct uart_driver qcom_geni_console_driver; |
8a8a66a1 | 149 | static struct uart_driver qcom_geni_uart_driver; |
c4f52879 | 150 | static int handle_rx_console(struct uart_port *uport, u32 bytes, bool drop); |
8a8a66a1 | 151 | static int handle_rx_uart(struct uart_port *uport, u32 bytes, bool drop); |
c4f52879 KR |
152 | static unsigned int qcom_geni_serial_tx_empty(struct uart_port *port); |
153 | static void qcom_geni_serial_stop_rx(struct uart_port *uport); | |
679aac5e | 154 | static void qcom_geni_serial_handle_rx(struct uart_port *uport, bool drop); |
c4f52879 | 155 | |
c4f52879 KR |
156 | #define to_dev_port(ptr, member) \ |
157 | container_of(ptr, struct qcom_geni_serial_port, member) | |
158 | ||
8a8a66a1 GM |
159 | static struct qcom_geni_serial_port qcom_geni_uart_ports[GENI_UART_PORTS] = { |
160 | [0] = { | |
161 | .uport = { | |
162 | .iotype = UPIO_MEM, | |
163 | .ops = &qcom_geni_uart_pops, | |
164 | .flags = UPF_BOOT_AUTOCONF, | |
165 | .line = 0, | |
166 | }, | |
167 | }, | |
168 | [1] = { | |
169 | .uport = { | |
170 | .iotype = UPIO_MEM, | |
171 | .ops = &qcom_geni_uart_pops, | |
172 | .flags = UPF_BOOT_AUTOCONF, | |
173 | .line = 1, | |
174 | }, | |
175 | }, | |
176 | [2] = { | |
177 | .uport = { | |
178 | .iotype = UPIO_MEM, | |
179 | .ops = &qcom_geni_uart_pops, | |
180 | .flags = UPF_BOOT_AUTOCONF, | |
181 | .line = 2, | |
182 | }, | |
183 | }, | |
184 | }; | |
185 | ||
f7371750 KR |
186 | static struct qcom_geni_serial_port qcom_geni_console_port = { |
187 | .uport = { | |
188 | .iotype = UPIO_MEM, | |
189 | .ops = &qcom_geni_console_pops, | |
190 | .flags = UPF_BOOT_AUTOCONF, | |
191 | .line = 0, | |
192 | }, | |
193 | }; | |
c4f52879 KR |
194 | |
195 | static int qcom_geni_serial_request_port(struct uart_port *uport) | |
196 | { | |
197 | struct platform_device *pdev = to_platform_device(uport->dev); | |
198 | struct qcom_geni_serial_port *port = to_dev_port(uport, uport); | |
c4f52879 | 199 | |
44e60d52 | 200 | uport->membase = devm_platform_ioremap_resource(pdev, 0); |
c4f52879 KR |
201 | if (IS_ERR(uport->membase)) |
202 | return PTR_ERR(uport->membase); | |
203 | port->se.base = uport->membase; | |
204 | return 0; | |
205 | } | |
206 | ||
207 | static void qcom_geni_serial_config_port(struct uart_port *uport, int cfg_flags) | |
208 | { | |
209 | if (cfg_flags & UART_CONFIG_TYPE) { | |
210 | uport->type = PORT_MSM; | |
211 | qcom_geni_serial_request_port(uport); | |
212 | } | |
213 | } | |
214 | ||
8a8a66a1 | 215 | static unsigned int qcom_geni_serial_get_mctrl(struct uart_port *uport) |
c4f52879 | 216 | { |
8a8a66a1 GM |
217 | unsigned int mctrl = TIOCM_DSR | TIOCM_CAR; |
218 | u32 geni_ios; | |
219 | ||
e8a6ca80 | 220 | if (uart_console(uport)) { |
8a8a66a1 GM |
221 | mctrl |= TIOCM_CTS; |
222 | } else { | |
9e06d55f | 223 | geni_ios = readl(uport->membase + SE_GENI_IOS); |
8a8a66a1 GM |
224 | if (!(geni_ios & IO2_DATA_IN)) |
225 | mctrl |= TIOCM_CTS; | |
226 | } | |
227 | ||
228 | return mctrl; | |
c4f52879 KR |
229 | } |
230 | ||
8a8a66a1 | 231 | static void qcom_geni_serial_set_mctrl(struct uart_port *uport, |
c4f52879 KR |
232 | unsigned int mctrl) |
233 | { | |
8a8a66a1 | 234 | u32 uart_manual_rfr = 0; |
69bd1a4f | 235 | struct qcom_geni_serial_port *port = to_dev_port(uport, uport); |
8a8a66a1 | 236 | |
e8a6ca80 | 237 | if (uart_console(uport)) |
8a8a66a1 GM |
238 | return; |
239 | ||
69bd1a4f AA |
240 | if (mctrl & TIOCM_LOOP) |
241 | port->loopback = RX_TX_CTS_RTS_SORTED; | |
242 | ||
a4ced376 | 243 | if (!(mctrl & TIOCM_RTS) && !uport->suspended) |
8a8a66a1 | 244 | uart_manual_rfr = UART_MANUAL_RFR_EN | UART_RFR_NOT_READY; |
9e06d55f | 245 | writel(uart_manual_rfr, uport->membase + SE_UART_MANUAL_RFR); |
c4f52879 KR |
246 | } |
247 | ||
248 | static const char *qcom_geni_serial_get_type(struct uart_port *uport) | |
249 | { | |
250 | return "MSM"; | |
251 | } | |
252 | ||
8a8a66a1 | 253 | static struct qcom_geni_serial_port *get_port_from_line(int line, bool console) |
c4f52879 | 254 | { |
8a8a66a1 GM |
255 | struct qcom_geni_serial_port *port; |
256 | int nr_ports = console ? GENI_UART_CONS_PORTS : GENI_UART_PORTS; | |
257 | ||
258 | if (line < 0 || line >= nr_ports) | |
c4f52879 | 259 | return ERR_PTR(-ENXIO); |
8a8a66a1 GM |
260 | |
261 | port = console ? &qcom_geni_console_port : &qcom_geni_uart_ports[line]; | |
262 | return port; | |
c4f52879 KR |
263 | } |
264 | ||
265 | static bool qcom_geni_serial_poll_bit(struct uart_port *uport, | |
266 | int offset, int field, bool set) | |
267 | { | |
268 | u32 reg; | |
269 | struct qcom_geni_serial_port *port; | |
270 | unsigned int baud; | |
271 | unsigned int fifo_bits; | |
272 | unsigned long timeout_us = 20000; | |
e42d6c3e | 273 | struct qcom_geni_private_data *private_data = uport->private_data; |
c4f52879 | 274 | |
e42d6c3e | 275 | if (private_data->drv) { |
c4f52879 KR |
276 | port = to_dev_port(uport, uport); |
277 | baud = port->baud; | |
278 | if (!baud) | |
279 | baud = 115200; | |
280 | fifo_bits = port->tx_fifo_depth * port->tx_fifo_width; | |
281 | /* | |
282 | * Total polling iterations based on FIFO worth of bytes to be | |
283 | * sent at current baud. Add a little fluff to the wait. | |
284 | */ | |
285 | timeout_us = ((fifo_bits * USEC_PER_SEC) / baud) + 500; | |
286 | } | |
287 | ||
43f1831b KR |
288 | /* |
289 | * Use custom implementation instead of readl_poll_atomic since ktimer | |
290 | * is not ready at the time of early console. | |
291 | */ | |
292 | timeout_us = DIV_ROUND_UP(timeout_us, 10) * 10; | |
293 | while (timeout_us) { | |
9e06d55f | 294 | reg = readl(uport->membase + offset); |
43f1831b KR |
295 | if ((bool)(reg & field) == set) |
296 | return true; | |
297 | udelay(10); | |
298 | timeout_us -= 10; | |
299 | } | |
300 | return false; | |
c4f52879 KR |
301 | } |
302 | ||
303 | static void qcom_geni_serial_setup_tx(struct uart_port *uport, u32 xmit_size) | |
304 | { | |
305 | u32 m_cmd; | |
306 | ||
9e06d55f | 307 | writel(xmit_size, uport->membase + SE_UART_TX_TRANS_LEN); |
c4f52879 KR |
308 | m_cmd = UART_START_TX << M_OPCODE_SHFT; |
309 | writel(m_cmd, uport->membase + SE_GENI_M_CMD0); | |
310 | } | |
311 | ||
312 | static void qcom_geni_serial_poll_tx_done(struct uart_port *uport) | |
313 | { | |
314 | int done; | |
315 | u32 irq_clear = M_CMD_DONE_EN; | |
316 | ||
317 | done = qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, | |
318 | M_CMD_DONE_EN, true); | |
319 | if (!done) { | |
9e06d55f | 320 | writel(M_GENI_CMD_ABORT, uport->membase + |
c4f52879 KR |
321 | SE_GENI_M_CMD_CTRL_REG); |
322 | irq_clear |= M_CMD_ABORT_EN; | |
323 | qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, | |
324 | M_CMD_ABORT_EN, true); | |
325 | } | |
9e06d55f | 326 | writel(irq_clear, uport->membase + SE_GENI_M_IRQ_CLEAR); |
c4f52879 KR |
327 | } |
328 | ||
329 | static void qcom_geni_serial_abort_rx(struct uart_port *uport) | |
330 | { | |
331 | u32 irq_clear = S_CMD_DONE_EN | S_CMD_ABORT_EN; | |
332 | ||
333 | writel(S_GENI_CMD_ABORT, uport->membase + SE_GENI_S_CMD_CTRL_REG); | |
334 | qcom_geni_serial_poll_bit(uport, SE_GENI_S_CMD_CTRL_REG, | |
335 | S_GENI_CMD_ABORT, false); | |
9e06d55f RC |
336 | writel(irq_clear, uport->membase + SE_GENI_S_IRQ_CLEAR); |
337 | writel(FORCE_DEFAULT, uport->membase + GENI_FORCE_DEFAULT_REG); | |
c4f52879 KR |
338 | } |
339 | ||
340 | #ifdef CONFIG_CONSOLE_POLL | |
e42d6c3e | 341 | |
c4f52879 KR |
342 | static int qcom_geni_serial_get_char(struct uart_port *uport) |
343 | { | |
e42d6c3e | 344 | struct qcom_geni_private_data *private_data = uport->private_data; |
c4f52879 | 345 | u32 status; |
e42d6c3e DA |
346 | u32 word_cnt; |
347 | int ret; | |
348 | ||
349 | if (!private_data->poll_cached_bytes_cnt) { | |
350 | status = readl(uport->membase + SE_GENI_M_IRQ_STATUS); | |
351 | writel(status, uport->membase + SE_GENI_M_IRQ_CLEAR); | |
c4f52879 | 352 | |
e42d6c3e DA |
353 | status = readl(uport->membase + SE_GENI_S_IRQ_STATUS); |
354 | writel(status, uport->membase + SE_GENI_S_IRQ_CLEAR); | |
c4f52879 | 355 | |
e42d6c3e DA |
356 | status = readl(uport->membase + SE_GENI_RX_FIFO_STATUS); |
357 | word_cnt = status & RX_FIFO_WC_MSK; | |
358 | if (!word_cnt) | |
359 | return NO_POLL_CHAR; | |
c4f52879 | 360 | |
e42d6c3e | 361 | if (word_cnt == 1 && (status & RX_LAST)) |
d681a6e4 DA |
362 | /* |
363 | * NOTE: If RX_LAST_BYTE_VALID is 0 it needs to be | |
364 | * treated as if it was BYTES_PER_FIFO_WORD. | |
365 | */ | |
e42d6c3e DA |
366 | private_data->poll_cached_bytes_cnt = |
367 | (status & RX_LAST_BYTE_VALID_MSK) >> | |
368 | RX_LAST_BYTE_VALID_SHFT; | |
d681a6e4 DA |
369 | |
370 | if (private_data->poll_cached_bytes_cnt == 0) | |
371 | private_data->poll_cached_bytes_cnt = BYTES_PER_FIFO_WORD; | |
c4f52879 | 372 | |
e42d6c3e DA |
373 | private_data->poll_cached_bytes = |
374 | readl(uport->membase + SE_GENI_RX_FIFOn); | |
375 | } | |
376 | ||
377 | private_data->poll_cached_bytes_cnt--; | |
378 | ret = private_data->poll_cached_bytes & 0xff; | |
379 | private_data->poll_cached_bytes >>= 8; | |
380 | ||
381 | return ret; | |
c4f52879 KR |
382 | } |
383 | ||
384 | static void qcom_geni_serial_poll_put_char(struct uart_port *uport, | |
385 | unsigned char c) | |
386 | { | |
a85fb9ce | 387 | writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG); |
c4f52879 KR |
388 | qcom_geni_serial_setup_tx(uport, 1); |
389 | WARN_ON(!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, | |
390 | M_TX_FIFO_WATERMARK_EN, true)); | |
9e06d55f RC |
391 | writel(c, uport->membase + SE_GENI_TX_FIFOn); |
392 | writel(M_TX_FIFO_WATERMARK_EN, uport->membase + SE_GENI_M_IRQ_CLEAR); | |
c4f52879 KR |
393 | qcom_geni_serial_poll_tx_done(uport); |
394 | } | |
395 | #endif | |
396 | ||
397 | #ifdef CONFIG_SERIAL_QCOM_GENI_CONSOLE | |
3f8bab17 | 398 | static void qcom_geni_serial_wr_char(struct uart_port *uport, unsigned char ch) |
c4f52879 | 399 | { |
650c8bd3 DA |
400 | struct qcom_geni_private_data *private_data = uport->private_data; |
401 | ||
402 | private_data->write_cached_bytes = | |
403 | (private_data->write_cached_bytes >> 8) | (ch << 24); | |
404 | private_data->write_cached_bytes_cnt++; | |
405 | ||
406 | if (private_data->write_cached_bytes_cnt == BYTES_PER_FIFO_WORD) { | |
407 | writel(private_data->write_cached_bytes, | |
408 | uport->membase + SE_GENI_TX_FIFOn); | |
409 | private_data->write_cached_bytes_cnt = 0; | |
410 | } | |
c4f52879 KR |
411 | } |
412 | ||
413 | static void | |
414 | __qcom_geni_serial_console_write(struct uart_port *uport, const char *s, | |
415 | unsigned int count) | |
416 | { | |
650c8bd3 DA |
417 | struct qcom_geni_private_data *private_data = uport->private_data; |
418 | ||
c4f52879 KR |
419 | int i; |
420 | u32 bytes_to_send = count; | |
421 | ||
422 | for (i = 0; i < count; i++) { | |
f0262568 KR |
423 | /* |
424 | * uart_console_write() adds a carriage return for each newline. | |
425 | * Account for additional bytes to be written. | |
426 | */ | |
c4f52879 KR |
427 | if (s[i] == '\n') |
428 | bytes_to_send++; | |
429 | } | |
430 | ||
9e06d55f | 431 | writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG); |
c4f52879 KR |
432 | qcom_geni_serial_setup_tx(uport, bytes_to_send); |
433 | for (i = 0; i < count; ) { | |
434 | size_t chars_to_write = 0; | |
435 | size_t avail = DEF_FIFO_DEPTH_WORDS - DEF_TX_WM; | |
436 | ||
437 | /* | |
438 | * If the WM bit never set, then the Tx state machine is not | |
439 | * in a valid state, so break, cancel/abort any existing | |
440 | * command. Unfortunately the current data being written is | |
441 | * lost. | |
442 | */ | |
443 | if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, | |
444 | M_TX_FIFO_WATERMARK_EN, true)) | |
445 | break; | |
6a10635e | 446 | chars_to_write = min_t(size_t, count - i, avail / 2); |
c4f52879 KR |
447 | uart_console_write(uport, s + i, chars_to_write, |
448 | qcom_geni_serial_wr_char); | |
9e06d55f | 449 | writel(M_TX_FIFO_WATERMARK_EN, uport->membase + |
c4f52879 KR |
450 | SE_GENI_M_IRQ_CLEAR); |
451 | i += chars_to_write; | |
452 | } | |
650c8bd3 DA |
453 | |
454 | if (private_data->write_cached_bytes_cnt) { | |
455 | private_data->write_cached_bytes >>= BITS_PER_BYTE * | |
456 | (BYTES_PER_FIFO_WORD - private_data->write_cached_bytes_cnt); | |
457 | writel(private_data->write_cached_bytes, | |
458 | uport->membase + SE_GENI_TX_FIFOn); | |
459 | private_data->write_cached_bytes_cnt = 0; | |
460 | } | |
461 | ||
c4f52879 KR |
462 | qcom_geni_serial_poll_tx_done(uport); |
463 | } | |
464 | ||
465 | static void qcom_geni_serial_console_write(struct console *co, const char *s, | |
466 | unsigned int count) | |
467 | { | |
468 | struct uart_port *uport; | |
469 | struct qcom_geni_serial_port *port; | |
470 | bool locked = true; | |
471 | unsigned long flags; | |
a1fee899 | 472 | u32 geni_status; |
663abb1a | 473 | u32 irq_en; |
c4f52879 KR |
474 | |
475 | WARN_ON(co->index < 0 || co->index >= GENI_UART_CONS_PORTS); | |
476 | ||
8a8a66a1 | 477 | port = get_port_from_line(co->index, true); |
c4f52879 KR |
478 | if (IS_ERR(port)) |
479 | return; | |
480 | ||
481 | uport = &port->uport; | |
482 | if (oops_in_progress) | |
483 | locked = spin_trylock_irqsave(&uport->lock, flags); | |
484 | else | |
485 | spin_lock_irqsave(&uport->lock, flags); | |
486 | ||
9e06d55f | 487 | geni_status = readl(uport->membase + SE_GENI_STATUS); |
a1fee899 | 488 | |
c4f52879 KR |
489 | /* Cancel the current write to log the fault */ |
490 | if (!locked) { | |
491 | geni_se_cancel_m_cmd(&port->se); | |
492 | if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, | |
493 | M_CMD_CANCEL_EN, true)) { | |
494 | geni_se_abort_m_cmd(&port->se); | |
495 | qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, | |
496 | M_CMD_ABORT_EN, true); | |
9e06d55f | 497 | writel(M_CMD_ABORT_EN, uport->membase + |
c4f52879 KR |
498 | SE_GENI_M_IRQ_CLEAR); |
499 | } | |
9e06d55f | 500 | writel(M_CMD_CANCEL_EN, uport->membase + SE_GENI_M_IRQ_CLEAR); |
a1fee899 RC |
501 | } else if ((geni_status & M_GENI_CMD_ACTIVE) && !port->tx_remaining) { |
502 | /* | |
503 | * It seems we can't interrupt existing transfers if all data | |
504 | * has been sent, in which case we need to look for done first. | |
505 | */ | |
506 | qcom_geni_serial_poll_tx_done(uport); | |
663abb1a | 507 | |
d2b574c0 | 508 | if (!uart_circ_empty(&uport->state->xmit)) { |
9e06d55f RC |
509 | irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); |
510 | writel(irq_en | M_TX_FIFO_WATERMARK_EN, | |
663abb1a RC |
511 | uport->membase + SE_GENI_M_IRQ_EN); |
512 | } | |
c4f52879 KR |
513 | } |
514 | ||
515 | __qcom_geni_serial_console_write(uport, s, count); | |
a1fee899 RC |
516 | |
517 | if (port->tx_remaining) | |
518 | qcom_geni_serial_setup_tx(uport, port->tx_remaining); | |
519 | ||
c4f52879 KR |
520 | if (locked) |
521 | spin_unlock_irqrestore(&uport->lock, flags); | |
522 | } | |
523 | ||
524 | static int handle_rx_console(struct uart_port *uport, u32 bytes, bool drop) | |
525 | { | |
526 | u32 i; | |
527 | unsigned char buf[sizeof(u32)]; | |
528 | struct tty_port *tport; | |
529 | struct qcom_geni_serial_port *port = to_dev_port(uport, uport); | |
530 | ||
531 | tport = &uport->state->port; | |
532 | for (i = 0; i < bytes; ) { | |
533 | int c; | |
650c8bd3 | 534 | int chunk = min_t(int, bytes - i, BYTES_PER_FIFO_WORD); |
c4f52879 KR |
535 | |
536 | ioread32_rep(uport->membase + SE_GENI_RX_FIFOn, buf, 1); | |
537 | i += chunk; | |
538 | if (drop) | |
539 | continue; | |
540 | ||
541 | for (c = 0; c < chunk; c++) { | |
542 | int sysrq; | |
543 | ||
544 | uport->icount.rx++; | |
545 | if (port->brk && buf[c] == 0) { | |
546 | port->brk = false; | |
547 | if (uart_handle_break(uport)) | |
548 | continue; | |
549 | } | |
550 | ||
336447b3 | 551 | sysrq = uart_prepare_sysrq_char(uport, buf[c]); |
babeca85 | 552 | |
c4f52879 KR |
553 | if (!sysrq) |
554 | tty_insert_flip_char(tport, buf[c], TTY_NORMAL); | |
555 | } | |
556 | } | |
557 | if (!drop) | |
558 | tty_flip_buffer_push(tport); | |
559 | return 0; | |
560 | } | |
561 | #else | |
562 | static int handle_rx_console(struct uart_port *uport, u32 bytes, bool drop) | |
563 | { | |
564 | return -EPERM; | |
565 | } | |
566 | ||
567 | #endif /* CONFIG_SERIAL_QCOM_GENI_CONSOLE */ | |
568 | ||
8a8a66a1 GM |
569 | static int handle_rx_uart(struct uart_port *uport, u32 bytes, bool drop) |
570 | { | |
8a8a66a1 GM |
571 | struct tty_port *tport; |
572 | struct qcom_geni_serial_port *port = to_dev_port(uport, uport); | |
573 | u32 num_bytes_pw = port->tx_fifo_width / BITS_PER_BYTE; | |
574 | u32 words = ALIGN(bytes, num_bytes_pw) / num_bytes_pw; | |
575 | int ret; | |
576 | ||
577 | tport = &uport->state->port; | |
578 | ioread32_rep(uport->membase + SE_GENI_RX_FIFOn, port->rx_fifo, words); | |
579 | if (drop) | |
580 | return 0; | |
581 | ||
f9d690b6 | 582 | ret = tty_insert_flip_string(tport, port->rx_fifo, bytes); |
8a8a66a1 GM |
583 | if (ret != bytes) { |
584 | dev_err(uport->dev, "%s:Unable to push data ret %d_bytes %d\n", | |
585 | __func__, ret, bytes); | |
586 | WARN_ON_ONCE(1); | |
587 | } | |
588 | uport->icount.rx += ret; | |
589 | tty_flip_buffer_push(tport); | |
590 | return ret; | |
591 | } | |
592 | ||
c4f52879 KR |
593 | static void qcom_geni_serial_start_tx(struct uart_port *uport) |
594 | { | |
595 | u32 irq_en; | |
c4f52879 KR |
596 | u32 status; |
597 | ||
bdc05a8a RC |
598 | status = readl(uport->membase + SE_GENI_STATUS); |
599 | if (status & M_GENI_CMD_ACTIVE) | |
600 | return; | |
c4f52879 | 601 | |
bdc05a8a RC |
602 | if (!qcom_geni_serial_tx_empty(uport)) |
603 | return; | |
c4f52879 | 604 | |
bdc05a8a RC |
605 | irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); |
606 | irq_en |= M_TX_FIFO_WATERMARK_EN | M_CMD_DONE_EN; | |
c4f52879 | 607 | |
bdc05a8a RC |
608 | writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG); |
609 | writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN); | |
c4f52879 KR |
610 | } |
611 | ||
612 | static void qcom_geni_serial_stop_tx(struct uart_port *uport) | |
613 | { | |
614 | u32 irq_en; | |
615 | u32 status; | |
616 | struct qcom_geni_serial_port *port = to_dev_port(uport, uport); | |
617 | ||
9e06d55f | 618 | irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); |
bdc05a8a RC |
619 | irq_en &= ~(M_CMD_DONE_EN | M_TX_FIFO_WATERMARK_EN); |
620 | writel(0, uport->membase + SE_GENI_TX_WATERMARK_REG); | |
9e06d55f RC |
621 | writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN); |
622 | status = readl(uport->membase + SE_GENI_STATUS); | |
c4f52879 KR |
623 | /* Possible stop tx is called multiple times. */ |
624 | if (!(status & M_GENI_CMD_ACTIVE)) | |
625 | return; | |
626 | ||
c4f52879 KR |
627 | geni_se_cancel_m_cmd(&port->se); |
628 | if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, | |
629 | M_CMD_CANCEL_EN, true)) { | |
630 | geni_se_abort_m_cmd(&port->se); | |
631 | qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, | |
632 | M_CMD_ABORT_EN, true); | |
9e06d55f | 633 | writel(M_CMD_ABORT_EN, uport->membase + SE_GENI_M_IRQ_CLEAR); |
c4f52879 | 634 | } |
9e06d55f | 635 | writel(M_CMD_CANCEL_EN, uport->membase + SE_GENI_M_IRQ_CLEAR); |
c4f52879 KR |
636 | } |
637 | ||
638 | static void qcom_geni_serial_start_rx(struct uart_port *uport) | |
639 | { | |
640 | u32 irq_en; | |
641 | u32 status; | |
642 | struct qcom_geni_serial_port *port = to_dev_port(uport, uport); | |
643 | ||
9e06d55f | 644 | status = readl(uport->membase + SE_GENI_STATUS); |
c4f52879 KR |
645 | if (status & S_GENI_CMD_ACTIVE) |
646 | qcom_geni_serial_stop_rx(uport); | |
647 | ||
c4f52879 KR |
648 | geni_se_setup_s_cmd(&port->se, UART_START_READ, 0); |
649 | ||
bdc05a8a RC |
650 | irq_en = readl(uport->membase + SE_GENI_S_IRQ_EN); |
651 | irq_en |= S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN; | |
652 | writel(irq_en, uport->membase + SE_GENI_S_IRQ_EN); | |
c4f52879 | 653 | |
bdc05a8a RC |
654 | irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); |
655 | irq_en |= M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN; | |
656 | writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN); | |
c4f52879 KR |
657 | } |
658 | ||
659 | static void qcom_geni_serial_stop_rx(struct uart_port *uport) | |
660 | { | |
661 | u32 irq_en; | |
662 | u32 status; | |
663 | struct qcom_geni_serial_port *port = to_dev_port(uport, uport); | |
679aac5e | 664 | u32 s_irq_status; |
c4f52879 | 665 | |
bdc05a8a RC |
666 | irq_en = readl(uport->membase + SE_GENI_S_IRQ_EN); |
667 | irq_en &= ~(S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN); | |
668 | writel(irq_en, uport->membase + SE_GENI_S_IRQ_EN); | |
c4f52879 | 669 | |
bdc05a8a RC |
670 | irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); |
671 | irq_en &= ~(M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN); | |
672 | writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN); | |
c4f52879 | 673 | |
9e06d55f | 674 | status = readl(uport->membase + SE_GENI_STATUS); |
c4f52879 KR |
675 | /* Possible stop rx is called multiple times. */ |
676 | if (!(status & S_GENI_CMD_ACTIVE)) | |
677 | return; | |
678 | ||
c4f52879 | 679 | geni_se_cancel_s_cmd(&port->se); |
679aac5e | 680 | qcom_geni_serial_poll_bit(uport, SE_GENI_S_IRQ_STATUS, |
681 | S_CMD_CANCEL_EN, true); | |
682 | /* | |
683 | * If timeout occurs secondary engine remains active | |
684 | * and Abort sequence is executed. | |
685 | */ | |
686 | s_irq_status = readl(uport->membase + SE_GENI_S_IRQ_STATUS); | |
687 | /* Flush the Rx buffer */ | |
688 | if (s_irq_status & S_RX_FIFO_LAST_EN) | |
689 | qcom_geni_serial_handle_rx(uport, true); | |
690 | writel(s_irq_status, uport->membase + SE_GENI_S_IRQ_CLEAR); | |
691 | ||
9e06d55f | 692 | status = readl(uport->membase + SE_GENI_STATUS); |
c4f52879 KR |
693 | if (status & S_GENI_CMD_ACTIVE) |
694 | qcom_geni_serial_abort_rx(uport); | |
695 | } | |
696 | ||
697 | static void qcom_geni_serial_handle_rx(struct uart_port *uport, bool drop) | |
698 | { | |
699 | u32 status; | |
700 | u32 word_cnt; | |
701 | u32 last_word_byte_cnt; | |
702 | u32 last_word_partial; | |
703 | u32 total_bytes; | |
704 | struct qcom_geni_serial_port *port = to_dev_port(uport, uport); | |
705 | ||
9e06d55f | 706 | status = readl(uport->membase + SE_GENI_RX_FIFO_STATUS); |
c4f52879 KR |
707 | word_cnt = status & RX_FIFO_WC_MSK; |
708 | last_word_partial = status & RX_LAST; | |
709 | last_word_byte_cnt = (status & RX_LAST_BYTE_VALID_MSK) >> | |
710 | RX_LAST_BYTE_VALID_SHFT; | |
711 | ||
712 | if (!word_cnt) | |
713 | return; | |
650c8bd3 | 714 | total_bytes = BYTES_PER_FIFO_WORD * (word_cnt - 1); |
c4f52879 KR |
715 | if (last_word_partial && last_word_byte_cnt) |
716 | total_bytes += last_word_byte_cnt; | |
717 | else | |
650c8bd3 | 718 | total_bytes += BYTES_PER_FIFO_WORD; |
c4f52879 KR |
719 | port->handle_rx(uport, total_bytes, drop); |
720 | } | |
721 | ||
a1fee899 RC |
722 | static void qcom_geni_serial_handle_tx(struct uart_port *uport, bool done, |
723 | bool active) | |
c4f52879 KR |
724 | { |
725 | struct qcom_geni_serial_port *port = to_dev_port(uport, uport); | |
726 | struct circ_buf *xmit = &uport->state->xmit; | |
727 | size_t avail; | |
728 | size_t remaining; | |
a1fee899 | 729 | size_t pending; |
c4f52879 KR |
730 | int i; |
731 | u32 status; | |
64a42807 | 732 | u32 irq_en; |
c4f52879 KR |
733 | unsigned int chunk; |
734 | int tail; | |
735 | ||
9e06d55f | 736 | status = readl(uport->membase + SE_GENI_TX_FIFO_STATUS); |
a1fee899 RC |
737 | |
738 | /* Complete the current tx command before taking newly added data */ | |
739 | if (active) | |
740 | pending = port->tx_remaining; | |
741 | else | |
742 | pending = uart_circ_chars_pending(xmit); | |
743 | ||
744 | /* All data has been transmitted and acknowledged as received */ | |
745 | if (!pending && !status && done) { | |
c4f52879 KR |
746 | qcom_geni_serial_stop_tx(uport); |
747 | goto out_write_wakeup; | |
748 | } | |
c4f52879 | 749 | |
a1fee899 | 750 | avail = port->tx_fifo_depth - (status & TX_FIFO_WC); |
650c8bd3 | 751 | avail *= BYTES_PER_FIFO_WORD; |
8a8a66a1 | 752 | |
638a6f4e | 753 | tail = xmit->tail; |
3c66eb4b | 754 | chunk = min(avail, pending); |
c4f52879 KR |
755 | if (!chunk) |
756 | goto out_write_wakeup; | |
757 | ||
a1fee899 RC |
758 | if (!port->tx_remaining) { |
759 | qcom_geni_serial_setup_tx(uport, pending); | |
760 | port->tx_remaining = pending; | |
64a42807 | 761 | |
9e06d55f | 762 | irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); |
64a42807 | 763 | if (!(irq_en & M_TX_FIFO_WATERMARK_EN)) |
9e06d55f | 764 | writel(irq_en | M_TX_FIFO_WATERMARK_EN, |
64a42807 | 765 | uport->membase + SE_GENI_M_IRQ_EN); |
a1fee899 | 766 | } |
c4f52879 KR |
767 | |
768 | remaining = chunk; | |
769 | for (i = 0; i < chunk; ) { | |
770 | unsigned int tx_bytes; | |
69736b57 | 771 | u8 buf[sizeof(u32)]; |
c4f52879 KR |
772 | int c; |
773 | ||
3550f897 | 774 | memset(buf, 0, sizeof(buf)); |
650c8bd3 | 775 | tx_bytes = min_t(size_t, remaining, BYTES_PER_FIFO_WORD); |
3c66eb4b MK |
776 | |
777 | for (c = 0; c < tx_bytes ; c++) { | |
778 | buf[c] = xmit->buf[tail++]; | |
779 | tail &= UART_XMIT_SIZE - 1; | |
780 | } | |
c4f52879 | 781 | |
69736b57 | 782 | iowrite32_rep(uport->membase + SE_GENI_TX_FIFOn, buf, 1); |
c4f52879 KR |
783 | |
784 | i += tx_bytes; | |
c4f52879 KR |
785 | uport->icount.tx += tx_bytes; |
786 | remaining -= tx_bytes; | |
a1fee899 | 787 | port->tx_remaining -= tx_bytes; |
c4f52879 | 788 | } |
638a6f4e | 789 | |
3c66eb4b | 790 | xmit->tail = tail; |
64a42807 RC |
791 | |
792 | /* | |
793 | * The tx fifo watermark is level triggered and latched. Though we had | |
794 | * cleared it in qcom_geni_serial_isr it will have already reasserted | |
795 | * so we must clear it again here after our writes. | |
796 | */ | |
9e06d55f | 797 | writel(M_TX_FIFO_WATERMARK_EN, |
64a42807 RC |
798 | uport->membase + SE_GENI_M_IRQ_CLEAR); |
799 | ||
c4f52879 | 800 | out_write_wakeup: |
64a42807 | 801 | if (!port->tx_remaining) { |
9e06d55f | 802 | irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); |
64a42807 | 803 | if (irq_en & M_TX_FIFO_WATERMARK_EN) |
9e06d55f | 804 | writel(irq_en & ~M_TX_FIFO_WATERMARK_EN, |
64a42807 RC |
805 | uport->membase + SE_GENI_M_IRQ_EN); |
806 | } | |
807 | ||
638a6f4e EG |
808 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) |
809 | uart_write_wakeup(uport); | |
c4f52879 KR |
810 | } |
811 | ||
812 | static irqreturn_t qcom_geni_serial_isr(int isr, void *dev) | |
813 | { | |
385298ab RC |
814 | u32 m_irq_en; |
815 | u32 m_irq_status; | |
816 | u32 s_irq_status; | |
817 | u32 geni_status; | |
c4f52879 | 818 | struct uart_port *uport = dev; |
c4f52879 KR |
819 | bool drop_rx = false; |
820 | struct tty_port *tport = &uport->state->port; | |
821 | struct qcom_geni_serial_port *port = to_dev_port(uport, uport); | |
822 | ||
823 | if (uport->suspended) | |
ec91df8d | 824 | return IRQ_NONE; |
c4f52879 | 825 | |
75f4e830 JH |
826 | spin_lock(&uport->lock); |
827 | ||
9e06d55f RC |
828 | m_irq_status = readl(uport->membase + SE_GENI_M_IRQ_STATUS); |
829 | s_irq_status = readl(uport->membase + SE_GENI_S_IRQ_STATUS); | |
830 | geni_status = readl(uport->membase + SE_GENI_STATUS); | |
831 | m_irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); | |
832 | writel(m_irq_status, uport->membase + SE_GENI_M_IRQ_CLEAR); | |
833 | writel(s_irq_status, uport->membase + SE_GENI_S_IRQ_CLEAR); | |
c4f52879 KR |
834 | |
835 | if (WARN_ON(m_irq_status & M_ILLEGAL_CMD_EN)) | |
836 | goto out_unlock; | |
837 | ||
838 | if (s_irq_status & S_RX_FIFO_WR_ERR_EN) { | |
839 | uport->icount.overrun++; | |
840 | tty_insert_flip_char(tport, 0, TTY_OVERRUN); | |
841 | } | |
842 | ||
64a42807 | 843 | if (m_irq_status & m_irq_en & (M_TX_FIFO_WATERMARK_EN | M_CMD_DONE_EN)) |
a1fee899 RC |
844 | qcom_geni_serial_handle_tx(uport, m_irq_status & M_CMD_DONE_EN, |
845 | geni_status & M_GENI_CMD_ACTIVE); | |
c4f52879 KR |
846 | |
847 | if (s_irq_status & S_GP_IRQ_0_EN || s_irq_status & S_GP_IRQ_1_EN) { | |
848 | if (s_irq_status & S_GP_IRQ_0_EN) | |
849 | uport->icount.parity++; | |
850 | drop_rx = true; | |
851 | } else if (s_irq_status & S_GP_IRQ_2_EN || | |
852 | s_irq_status & S_GP_IRQ_3_EN) { | |
853 | uport->icount.brk++; | |
854 | port->brk = true; | |
855 | } | |
856 | ||
857 | if (s_irq_status & S_RX_FIFO_WATERMARK_EN || | |
858 | s_irq_status & S_RX_FIFO_LAST_EN) | |
859 | qcom_geni_serial_handle_rx(uport, drop_rx); | |
860 | ||
861 | out_unlock: | |
75f4e830 | 862 | uart_unlock_and_check_sysrq(uport); |
336447b3 | 863 | |
c4f52879 KR |
864 | return IRQ_HANDLED; |
865 | } | |
866 | ||
6a10635e | 867 | static void get_tx_fifo_size(struct qcom_geni_serial_port *port) |
c4f52879 KR |
868 | { |
869 | struct uart_port *uport; | |
870 | ||
c4f52879 KR |
871 | uport = &port->uport; |
872 | port->tx_fifo_depth = geni_se_get_tx_fifo_depth(&port->se); | |
873 | port->tx_fifo_width = geni_se_get_tx_fifo_width(&port->se); | |
874 | port->rx_fifo_depth = geni_se_get_rx_fifo_depth(&port->se); | |
875 | uport->fifosize = | |
876 | (port->tx_fifo_depth * port->tx_fifo_width) / BITS_PER_BYTE; | |
c4f52879 KR |
877 | } |
878 | ||
c4f52879 KR |
879 | |
880 | static void qcom_geni_serial_shutdown(struct uart_port *uport) | |
881 | { | |
3e4aaea7 | 882 | disable_irq(uport->irq); |
d8aca2f9 BG |
883 | qcom_geni_serial_stop_tx(uport); |
884 | qcom_geni_serial_stop_rx(uport); | |
c4f52879 KR |
885 | } |
886 | ||
887 | static int qcom_geni_serial_port_setup(struct uart_port *uport) | |
888 | { | |
889 | struct qcom_geni_serial_port *port = to_dev_port(uport, uport); | |
385298ab | 890 | u32 rxstale = DEFAULT_BITS_PER_CHAR * STALE_TIMEOUT; |
c362272b | 891 | u32 proto; |
9fa3c4b1 | 892 | u32 pin_swap; |
c362272b | 893 | |
c362272b DA |
894 | proto = geni_se_read_proto(&port->se); |
895 | if (proto != GENI_SE_UART) { | |
896 | dev_err(uport->dev, "Invalid FW loaded, proto: %d\n", proto); | |
897 | return -ENXIO; | |
898 | } | |
899 | ||
900 | qcom_geni_serial_stop_rx(uport); | |
901 | ||
902 | get_tx_fifo_size(port); | |
c4f52879 | 903 | |
9e06d55f | 904 | writel(rxstale, uport->membase + SE_UART_RX_STALE_CNT); |
9fa3c4b1 RRY |
905 | |
906 | pin_swap = readl(uport->membase + SE_UART_IO_MACRO_CTRL); | |
907 | if (port->rx_tx_swap) { | |
908 | pin_swap &= ~DEFAULT_IO_MACRO_IO2_IO3_MASK; | |
909 | pin_swap |= IO_MACRO_IO2_IO3_SWAP; | |
910 | } | |
911 | if (port->cts_rts_swap) { | |
912 | pin_swap &= ~DEFAULT_IO_MACRO_IO0_IO1_MASK; | |
913 | pin_swap |= IO_MACRO_IO0_SEL; | |
914 | } | |
915 | /* Configure this register if RX-TX, CTS-RTS pins are swapped */ | |
916 | if (port->rx_tx_swap || port->cts_rts_swap) | |
917 | writel(pin_swap, uport->membase + SE_UART_IO_MACRO_CTRL); | |
918 | ||
c4f52879 KR |
919 | /* |
920 | * Make an unconditional cancel on the main sequencer to reset | |
921 | * it else we could end up in data loss scenarios. | |
922 | */ | |
8a8a66a1 GM |
923 | if (uart_console(uport)) |
924 | qcom_geni_serial_poll_tx_done(uport); | |
650c8bd3 DA |
925 | geni_se_config_packing(&port->se, BITS_PER_BYTE, BYTES_PER_FIFO_WORD, |
926 | false, true, true); | |
a85fb9ce | 927 | geni_se_init(&port->se, UART_RX_WM, port->rx_fifo_depth - 2); |
bdc05a8a | 928 | geni_se_select_mode(&port->se, GENI_SE_FIFO); |
35781d83 | 929 | qcom_geni_serial_start_rx(uport); |
c4f52879 | 930 | port->setup = true; |
c362272b | 931 | |
c4f52879 KR |
932 | return 0; |
933 | } | |
934 | ||
935 | static int qcom_geni_serial_startup(struct uart_port *uport) | |
936 | { | |
937 | int ret; | |
c4f52879 KR |
938 | struct qcom_geni_serial_port *port = to_dev_port(uport, uport); |
939 | ||
c4f52879 KR |
940 | if (!port->setup) { |
941 | ret = qcom_geni_serial_port_setup(uport); | |
942 | if (ret) | |
943 | return ret; | |
944 | } | |
3e4aaea7 | 945 | enable_irq(uport->irq); |
c4f52879 | 946 | |
3e4aaea7 | 947 | return 0; |
c4f52879 KR |
948 | } |
949 | ||
c474c775 VKN |
950 | static unsigned long find_clk_rate_in_tol(struct clk *clk, unsigned int desired_clk, |
951 | unsigned int *clk_div, unsigned int percent_tol) | |
c4f52879 | 952 | { |
c474c775 | 953 | unsigned long freq; |
c2194bc9 | 954 | unsigned long div, maxdiv; |
c474c775 VKN |
955 | u64 mult; |
956 | unsigned long offset, abs_tol, achieved; | |
c2194bc9 | 957 | |
c474c775 | 958 | abs_tol = div_u64((u64)desired_clk * percent_tol, 100); |
c2194bc9 | 959 | maxdiv = CLK_DIV_MSK >> CLK_DIV_SHFT; |
c474c775 VKN |
960 | div = 1; |
961 | while (div <= maxdiv) { | |
962 | mult = (u64)div * desired_clk; | |
963 | if (mult != (unsigned long)mult) | |
c2194bc9 VKN |
964 | break; |
965 | ||
c474c775 VKN |
966 | offset = div * abs_tol; |
967 | freq = clk_round_rate(clk, mult - offset); | |
c2194bc9 | 968 | |
c474c775 VKN |
969 | /* Can only get lower if we're done */ |
970 | if (freq < mult - offset) | |
c2194bc9 VKN |
971 | break; |
972 | ||
c474c775 VKN |
973 | /* |
974 | * Re-calculate div in case rounding skipped rates but we | |
975 | * ended up at a good one, then check for a match. | |
976 | */ | |
977 | div = DIV_ROUND_CLOSEST(freq, desired_clk); | |
978 | achieved = DIV_ROUND_CLOSEST(freq, div); | |
979 | if (achieved <= desired_clk + abs_tol && | |
980 | achieved >= desired_clk - abs_tol) { | |
981 | *clk_div = div; | |
982 | return freq; | |
983 | } | |
c2194bc9 | 984 | |
c474c775 | 985 | div = DIV_ROUND_UP(freq, desired_clk); |
c4f52879 KR |
986 | } |
987 | ||
c474c775 VKN |
988 | return 0; |
989 | } | |
990 | ||
991 | static unsigned long get_clk_div_rate(struct clk *clk, unsigned int baud, | |
992 | unsigned int sampling_rate, unsigned int *clk_div) | |
993 | { | |
994 | unsigned long ser_clk; | |
995 | unsigned long desired_clk; | |
996 | ||
997 | desired_clk = baud * sampling_rate; | |
998 | if (!desired_clk) | |
999 | return 0; | |
1000 | ||
1001 | /* | |
1002 | * try to find a clock rate within 2% tolerance, then within 5% | |
1003 | */ | |
1004 | ser_clk = find_clk_rate_in_tol(clk, desired_clk, clk_div, 2); | |
1005 | if (!ser_clk) | |
1006 | ser_clk = find_clk_rate_in_tol(clk, desired_clk, clk_div, 5); | |
c2194bc9 | 1007 | |
c4f52879 KR |
1008 | return ser_clk; |
1009 | } | |
1010 | ||
1011 | static void qcom_geni_serial_set_termios(struct uart_port *uport, | |
bec5b814 IJ |
1012 | struct ktermios *termios, |
1013 | const struct ktermios *old) | |
c4f52879 KR |
1014 | { |
1015 | unsigned int baud; | |
385298ab RC |
1016 | u32 bits_per_char; |
1017 | u32 tx_trans_cfg; | |
1018 | u32 tx_parity_cfg; | |
1019 | u32 rx_trans_cfg; | |
1020 | u32 rx_parity_cfg; | |
1021 | u32 stop_bit_len; | |
c4f52879 | 1022 | unsigned int clk_div; |
385298ab | 1023 | u32 ser_clk_cfg; |
c4f52879 KR |
1024 | struct qcom_geni_serial_port *port = to_dev_port(uport, uport); |
1025 | unsigned long clk_rate; | |
ce734600 | 1026 | u32 ver, sampling_rate; |
7cf563b2 | 1027 | unsigned int avg_bw_core; |
c4f52879 KR |
1028 | |
1029 | qcom_geni_serial_stop_rx(uport); | |
1030 | /* baud rate */ | |
1031 | baud = uart_get_baud_rate(uport, termios, old, 300, 4000000); | |
1032 | port->baud = baud; | |
ce734600 VG |
1033 | |
1034 | sampling_rate = UART_OVERSAMPLING; | |
1035 | /* Sampling rate is halved for IP versions >= 2.5 */ | |
1036 | ver = geni_se_get_qup_hw_version(&port->se); | |
c9ca43d4 | 1037 | if (ver >= QUP_SE_VERSION_2_5) |
ce734600 VG |
1038 | sampling_rate /= 2; |
1039 | ||
c2194bc9 VKN |
1040 | clk_rate = get_clk_div_rate(port->se.clk, baud, |
1041 | sampling_rate, &clk_div); | |
c474c775 VKN |
1042 | if (!clk_rate) { |
1043 | dev_err(port->se.dev, | |
0fec5180 | 1044 | "Couldn't find suitable clock rate for %u\n", |
c474c775 | 1045 | baud * sampling_rate); |
c4f52879 | 1046 | goto out_restart_rx; |
c474c775 VKN |
1047 | } |
1048 | ||
0fec5180 | 1049 | dev_dbg(port->se.dev, "desired_rate-%u, clk_rate-%lu, clk_div-%u\n", |
c474c775 | 1050 | baud * sampling_rate, clk_rate, clk_div); |
c4f52879 KR |
1051 | |
1052 | uport->uartclk = clk_rate; | |
a5819b54 | 1053 | dev_pm_opp_set_rate(uport->dev, clk_rate); |
c4f52879 KR |
1054 | ser_clk_cfg = SER_CLK_EN; |
1055 | ser_clk_cfg |= clk_div << CLK_DIV_SHFT; | |
1056 | ||
7cf563b2 AA |
1057 | /* |
1058 | * Bump up BW vote on CPU and CORE path as driver supports FIFO mode | |
1059 | * only. | |
1060 | */ | |
1061 | avg_bw_core = (baud > 115200) ? Bps_to_icc(CORE_2X_50_MHZ) | |
1062 | : GENI_DEFAULT_BW; | |
1063 | port->se.icc_paths[GENI_TO_CORE].avg_bw = avg_bw_core; | |
1064 | port->se.icc_paths[CPU_TO_GENI].avg_bw = Bps_to_icc(baud); | |
1065 | geni_icc_set_bw(&port->se); | |
1066 | ||
c4f52879 | 1067 | /* parity */ |
9e06d55f RC |
1068 | tx_trans_cfg = readl(uport->membase + SE_UART_TX_TRANS_CFG); |
1069 | tx_parity_cfg = readl(uport->membase + SE_UART_TX_PARITY_CFG); | |
1070 | rx_trans_cfg = readl(uport->membase + SE_UART_RX_TRANS_CFG); | |
1071 | rx_parity_cfg = readl(uport->membase + SE_UART_RX_PARITY_CFG); | |
c4f52879 KR |
1072 | if (termios->c_cflag & PARENB) { |
1073 | tx_trans_cfg |= UART_TX_PAR_EN; | |
1074 | rx_trans_cfg |= UART_RX_PAR_EN; | |
1075 | tx_parity_cfg |= PAR_CALC_EN; | |
1076 | rx_parity_cfg |= PAR_CALC_EN; | |
1077 | if (termios->c_cflag & PARODD) { | |
1078 | tx_parity_cfg |= PAR_ODD; | |
1079 | rx_parity_cfg |= PAR_ODD; | |
1080 | } else if (termios->c_cflag & CMSPAR) { | |
1081 | tx_parity_cfg |= PAR_SPACE; | |
1082 | rx_parity_cfg |= PAR_SPACE; | |
1083 | } else { | |
1084 | tx_parity_cfg |= PAR_EVEN; | |
1085 | rx_parity_cfg |= PAR_EVEN; | |
1086 | } | |
1087 | } else { | |
1088 | tx_trans_cfg &= ~UART_TX_PAR_EN; | |
1089 | rx_trans_cfg &= ~UART_RX_PAR_EN; | |
1090 | tx_parity_cfg &= ~PAR_CALC_EN; | |
1091 | rx_parity_cfg &= ~PAR_CALC_EN; | |
1092 | } | |
1093 | ||
1094 | /* bits per char */ | |
3ec2ff37 | 1095 | bits_per_char = tty_get_char_size(termios->c_cflag); |
c4f52879 KR |
1096 | |
1097 | /* stop bits */ | |
1098 | if (termios->c_cflag & CSTOPB) | |
1099 | stop_bit_len = TX_STOP_BIT_LEN_2; | |
1100 | else | |
1101 | stop_bit_len = TX_STOP_BIT_LEN_1; | |
1102 | ||
1103 | /* flow control, clear the CTS_MASK bit if using flow control. */ | |
1104 | if (termios->c_cflag & CRTSCTS) | |
1105 | tx_trans_cfg &= ~UART_CTS_MASK; | |
1106 | else | |
1107 | tx_trans_cfg |= UART_CTS_MASK; | |
1108 | ||
1109 | if (baud) | |
1110 | uart_update_timeout(uport, termios->c_cflag, baud); | |
1111 | ||
8a8a66a1 | 1112 | if (!uart_console(uport)) |
9e06d55f | 1113 | writel(port->loopback, |
8a8a66a1 | 1114 | uport->membase + SE_UART_LOOPBACK_CFG); |
9e06d55f RC |
1115 | writel(tx_trans_cfg, uport->membase + SE_UART_TX_TRANS_CFG); |
1116 | writel(tx_parity_cfg, uport->membase + SE_UART_TX_PARITY_CFG); | |
1117 | writel(rx_trans_cfg, uport->membase + SE_UART_RX_TRANS_CFG); | |
1118 | writel(rx_parity_cfg, uport->membase + SE_UART_RX_PARITY_CFG); | |
1119 | writel(bits_per_char, uport->membase + SE_UART_TX_WORD_LEN); | |
1120 | writel(bits_per_char, uport->membase + SE_UART_RX_WORD_LEN); | |
1121 | writel(stop_bit_len, uport->membase + SE_UART_TX_STOP_BIT_LEN); | |
1122 | writel(ser_clk_cfg, uport->membase + GENI_SER_M_CLK_CFG); | |
1123 | writel(ser_clk_cfg, uport->membase + GENI_SER_S_CLK_CFG); | |
c4f52879 KR |
1124 | out_restart_rx: |
1125 | qcom_geni_serial_start_rx(uport); | |
1126 | } | |
1127 | ||
1128 | static unsigned int qcom_geni_serial_tx_empty(struct uart_port *uport) | |
1129 | { | |
7fb5b880 | 1130 | return !readl(uport->membase + SE_GENI_TX_FIFO_STATUS); |
c4f52879 KR |
1131 | } |
1132 | ||
1133 | #ifdef CONFIG_SERIAL_QCOM_GENI_CONSOLE | |
975efc66 | 1134 | static int qcom_geni_console_setup(struct console *co, char *options) |
c4f52879 KR |
1135 | { |
1136 | struct uart_port *uport; | |
1137 | struct qcom_geni_serial_port *port; | |
2ec812a0 | 1138 | int baud = 115200; |
c4f52879 KR |
1139 | int bits = 8; |
1140 | int parity = 'n'; | |
1141 | int flow = 'n'; | |
c362272b | 1142 | int ret; |
c4f52879 KR |
1143 | |
1144 | if (co->index >= GENI_UART_CONS_PORTS || co->index < 0) | |
1145 | return -ENXIO; | |
1146 | ||
8a8a66a1 | 1147 | port = get_port_from_line(co->index, true); |
c4f52879 | 1148 | if (IS_ERR(port)) { |
6a10635e | 1149 | pr_err("Invalid line %d\n", co->index); |
c4f52879 KR |
1150 | return PTR_ERR(port); |
1151 | } | |
1152 | ||
1153 | uport = &port->uport; | |
1154 | ||
1155 | if (unlikely(!uport->membase)) | |
1156 | return -ENXIO; | |
1157 | ||
c4f52879 | 1158 | if (!port->setup) { |
c362272b DA |
1159 | ret = qcom_geni_serial_port_setup(uport); |
1160 | if (ret) | |
1161 | return ret; | |
c4f52879 KR |
1162 | } |
1163 | ||
1164 | if (options) | |
1165 | uart_parse_options(options, &baud, &parity, &bits, &flow); | |
1166 | ||
1167 | return uart_set_options(uport, co, baud, parity, bits, flow); | |
1168 | } | |
1169 | ||
43f1831b KR |
1170 | static void qcom_geni_serial_earlycon_write(struct console *con, |
1171 | const char *s, unsigned int n) | |
1172 | { | |
1173 | struct earlycon_device *dev = con->data; | |
1174 | ||
1175 | __qcom_geni_serial_console_write(&dev->port, s, n); | |
1176 | } | |
1177 | ||
205b5bdd DA |
1178 | #ifdef CONFIG_CONSOLE_POLL |
1179 | static int qcom_geni_serial_earlycon_read(struct console *con, | |
1180 | char *s, unsigned int n) | |
1181 | { | |
1182 | struct earlycon_device *dev = con->data; | |
1183 | struct uart_port *uport = &dev->port; | |
1184 | int num_read = 0; | |
1185 | int ch; | |
1186 | ||
1187 | while (num_read < n) { | |
1188 | ch = qcom_geni_serial_get_char(uport); | |
1189 | if (ch == NO_POLL_CHAR) | |
1190 | break; | |
1191 | s[num_read++] = ch; | |
1192 | } | |
1193 | ||
1194 | return num_read; | |
1195 | } | |
1196 | ||
1197 | static void __init qcom_geni_serial_enable_early_read(struct geni_se *se, | |
1198 | struct console *con) | |
1199 | { | |
1200 | geni_se_setup_s_cmd(se, UART_START_READ, 0); | |
1201 | con->read = qcom_geni_serial_earlycon_read; | |
1202 | } | |
1203 | #else | |
1204 | static inline void qcom_geni_serial_enable_early_read(struct geni_se *se, | |
1205 | struct console *con) { } | |
1206 | #endif | |
1207 | ||
e42d6c3e DA |
1208 | static struct qcom_geni_private_data earlycon_private_data; |
1209 | ||
43f1831b KR |
1210 | static int __init qcom_geni_serial_earlycon_setup(struct earlycon_device *dev, |
1211 | const char *opt) | |
1212 | { | |
1213 | struct uart_port *uport = &dev->port; | |
1214 | u32 tx_trans_cfg; | |
1215 | u32 tx_parity_cfg = 0; /* Disable Tx Parity */ | |
1216 | u32 rx_trans_cfg = 0; | |
1217 | u32 rx_parity_cfg = 0; /* Disable Rx Parity */ | |
1218 | u32 stop_bit_len = 0; /* Default stop bit length - 1 bit */ | |
1219 | u32 bits_per_char; | |
1220 | struct geni_se se; | |
1221 | ||
1222 | if (!uport->membase) | |
1223 | return -EINVAL; | |
1224 | ||
e42d6c3e DA |
1225 | uport->private_data = &earlycon_private_data; |
1226 | ||
43f1831b KR |
1227 | memset(&se, 0, sizeof(se)); |
1228 | se.base = uport->membase; | |
1229 | if (geni_se_read_proto(&se) != GENI_SE_UART) | |
1230 | return -ENXIO; | |
1231 | /* | |
1232 | * Ignore Flow control. | |
1233 | * n = 8. | |
1234 | */ | |
1235 | tx_trans_cfg = UART_CTS_MASK; | |
1236 | bits_per_char = BITS_PER_BYTE; | |
1237 | ||
1238 | /* | |
1239 | * Make an unconditional cancel on the main sequencer to reset | |
1240 | * it else we could end up in data loss scenarios. | |
1241 | */ | |
1242 | qcom_geni_serial_poll_tx_done(uport); | |
1243 | qcom_geni_serial_abort_rx(uport); | |
650c8bd3 DA |
1244 | geni_se_config_packing(&se, BITS_PER_BYTE, BYTES_PER_FIFO_WORD, |
1245 | false, true, true); | |
43f1831b KR |
1246 | geni_se_init(&se, DEF_FIFO_DEPTH_WORDS / 2, DEF_FIFO_DEPTH_WORDS - 2); |
1247 | geni_se_select_mode(&se, GENI_SE_FIFO); | |
1248 | ||
9e06d55f RC |
1249 | writel(tx_trans_cfg, uport->membase + SE_UART_TX_TRANS_CFG); |
1250 | writel(tx_parity_cfg, uport->membase + SE_UART_TX_PARITY_CFG); | |
1251 | writel(rx_trans_cfg, uport->membase + SE_UART_RX_TRANS_CFG); | |
1252 | writel(rx_parity_cfg, uport->membase + SE_UART_RX_PARITY_CFG); | |
1253 | writel(bits_per_char, uport->membase + SE_UART_TX_WORD_LEN); | |
1254 | writel(bits_per_char, uport->membase + SE_UART_RX_WORD_LEN); | |
1255 | writel(stop_bit_len, uport->membase + SE_UART_TX_STOP_BIT_LEN); | |
43f1831b KR |
1256 | |
1257 | dev->con->write = qcom_geni_serial_earlycon_write; | |
1258 | dev->con->setup = NULL; | |
205b5bdd DA |
1259 | qcom_geni_serial_enable_early_read(&se, dev->con); |
1260 | ||
43f1831b KR |
1261 | return 0; |
1262 | } | |
1263 | OF_EARLYCON_DECLARE(qcom_geni, "qcom,geni-debug-uart", | |
1264 | qcom_geni_serial_earlycon_setup); | |
1265 | ||
c4f52879 KR |
1266 | static int __init console_register(struct uart_driver *drv) |
1267 | { | |
1268 | return uart_register_driver(drv); | |
1269 | } | |
1270 | ||
1271 | static void console_unregister(struct uart_driver *drv) | |
1272 | { | |
1273 | uart_unregister_driver(drv); | |
1274 | } | |
1275 | ||
1276 | static struct console cons_ops = { | |
1277 | .name = "ttyMSM", | |
1278 | .write = qcom_geni_serial_console_write, | |
1279 | .device = uart_console_device, | |
1280 | .setup = qcom_geni_console_setup, | |
1281 | .flags = CON_PRINTBUFFER, | |
1282 | .index = -1, | |
1283 | .data = &qcom_geni_console_driver, | |
1284 | }; | |
1285 | ||
1286 | static struct uart_driver qcom_geni_console_driver = { | |
1287 | .owner = THIS_MODULE, | |
1288 | .driver_name = "qcom_geni_console", | |
1289 | .dev_name = "ttyMSM", | |
1290 | .nr = GENI_UART_CONS_PORTS, | |
1291 | .cons = &cons_ops, | |
1292 | }; | |
1293 | #else | |
1294 | static int console_register(struct uart_driver *drv) | |
1295 | { | |
1296 | return 0; | |
1297 | } | |
1298 | ||
1299 | static void console_unregister(struct uart_driver *drv) | |
1300 | { | |
1301 | } | |
1302 | #endif /* CONFIG_SERIAL_QCOM_GENI_CONSOLE */ | |
1303 | ||
8a8a66a1 GM |
1304 | static struct uart_driver qcom_geni_uart_driver = { |
1305 | .owner = THIS_MODULE, | |
1306 | .driver_name = "qcom_geni_uart", | |
1307 | .dev_name = "ttyHS", | |
1308 | .nr = GENI_UART_PORTS, | |
1309 | }; | |
1310 | ||
1311 | static void qcom_geni_serial_pm(struct uart_port *uport, | |
c4f52879 KR |
1312 | unsigned int new_state, unsigned int old_state) |
1313 | { | |
1314 | struct qcom_geni_serial_port *port = to_dev_port(uport, uport); | |
1315 | ||
c362272b DA |
1316 | /* If we've never been called, treat it as off */ |
1317 | if (old_state == UART_PM_STATE_UNDEFINED) | |
1318 | old_state = UART_PM_STATE_OFF; | |
1319 | ||
7cf563b2 AA |
1320 | if (new_state == UART_PM_STATE_ON && old_state == UART_PM_STATE_OFF) { |
1321 | geni_icc_enable(&port->se); | |
c4f52879 | 1322 | geni_se_resources_on(&port->se); |
7cf563b2 AA |
1323 | } else if (new_state == UART_PM_STATE_OFF && |
1324 | old_state == UART_PM_STATE_ON) { | |
c4f52879 | 1325 | geni_se_resources_off(&port->se); |
7cf563b2 AA |
1326 | geni_icc_disable(&port->se); |
1327 | } | |
c4f52879 KR |
1328 | } |
1329 | ||
1330 | static const struct uart_ops qcom_geni_console_pops = { | |
1331 | .tx_empty = qcom_geni_serial_tx_empty, | |
1332 | .stop_tx = qcom_geni_serial_stop_tx, | |
1333 | .start_tx = qcom_geni_serial_start_tx, | |
1334 | .stop_rx = qcom_geni_serial_stop_rx, | |
654a8d6c | 1335 | .start_rx = qcom_geni_serial_start_rx, |
c4f52879 KR |
1336 | .set_termios = qcom_geni_serial_set_termios, |
1337 | .startup = qcom_geni_serial_startup, | |
1338 | .request_port = qcom_geni_serial_request_port, | |
1339 | .config_port = qcom_geni_serial_config_port, | |
1340 | .shutdown = qcom_geni_serial_shutdown, | |
1341 | .type = qcom_geni_serial_get_type, | |
8a8a66a1 GM |
1342 | .set_mctrl = qcom_geni_serial_set_mctrl, |
1343 | .get_mctrl = qcom_geni_serial_get_mctrl, | |
c4f52879 KR |
1344 | #ifdef CONFIG_CONSOLE_POLL |
1345 | .poll_get_char = qcom_geni_serial_get_char, | |
1346 | .poll_put_char = qcom_geni_serial_poll_put_char, | |
1347 | #endif | |
8a8a66a1 GM |
1348 | .pm = qcom_geni_serial_pm, |
1349 | }; | |
1350 | ||
1351 | static const struct uart_ops qcom_geni_uart_pops = { | |
1352 | .tx_empty = qcom_geni_serial_tx_empty, | |
1353 | .stop_tx = qcom_geni_serial_stop_tx, | |
1354 | .start_tx = qcom_geni_serial_start_tx, | |
1355 | .stop_rx = qcom_geni_serial_stop_rx, | |
1356 | .set_termios = qcom_geni_serial_set_termios, | |
1357 | .startup = qcom_geni_serial_startup, | |
1358 | .request_port = qcom_geni_serial_request_port, | |
1359 | .config_port = qcom_geni_serial_config_port, | |
1360 | .shutdown = qcom_geni_serial_shutdown, | |
1361 | .type = qcom_geni_serial_get_type, | |
1362 | .set_mctrl = qcom_geni_serial_set_mctrl, | |
1363 | .get_mctrl = qcom_geni_serial_get_mctrl, | |
1364 | .pm = qcom_geni_serial_pm, | |
c4f52879 KR |
1365 | }; |
1366 | ||
1367 | static int qcom_geni_serial_probe(struct platform_device *pdev) | |
1368 | { | |
1369 | int ret = 0; | |
71581242 | 1370 | int line; |
c4f52879 KR |
1371 | struct qcom_geni_serial_port *port; |
1372 | struct uart_port *uport; | |
1373 | struct resource *res; | |
066cd1c4 | 1374 | int irq; |
8a8a66a1 GM |
1375 | bool console = false; |
1376 | struct uart_driver *drv; | |
c4f52879 | 1377 | |
8a8a66a1 GM |
1378 | if (of_device_is_compatible(pdev->dev.of_node, "qcom,geni-debug-uart")) |
1379 | console = true; | |
c4f52879 | 1380 | |
2843cbb5 GU |
1381 | if (console) { |
1382 | drv = &qcom_geni_console_driver; | |
1383 | line = of_alias_get_id(pdev->dev.of_node, "serial"); | |
1384 | } else { | |
1385 | drv = &qcom_geni_uart_driver; | |
08b0adb1 DB |
1386 | line = of_alias_get_id(pdev->dev.of_node, "serial"); |
1387 | if (line == -ENODEV) /* compat with non-standard aliases */ | |
1388 | line = of_alias_get_id(pdev->dev.of_node, "hsuart"); | |
8a8a66a1 GM |
1389 | } |
1390 | ||
1391 | port = get_port_from_line(line, console); | |
c4f52879 | 1392 | if (IS_ERR(port)) { |
6a10635e KR |
1393 | dev_err(&pdev->dev, "Invalid line %d\n", line); |
1394 | return PTR_ERR(port); | |
c4f52879 KR |
1395 | } |
1396 | ||
1397 | uport = &port->uport; | |
1398 | /* Don't allow 2 drivers to access the same port */ | |
1399 | if (uport->private_data) | |
1400 | return -ENODEV; | |
1401 | ||
1402 | uport->dev = &pdev->dev; | |
1403 | port->se.dev = &pdev->dev; | |
1404 | port->se.wrapper = dev_get_drvdata(pdev->dev.parent); | |
1405 | port->se.clk = devm_clk_get(&pdev->dev, "se"); | |
1406 | if (IS_ERR(port->se.clk)) { | |
1407 | ret = PTR_ERR(port->se.clk); | |
1408 | dev_err(&pdev->dev, "Err getting SE Core clk %d\n", ret); | |
1409 | return ret; | |
1410 | } | |
1411 | ||
1412 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
7693b331 WY |
1413 | if (!res) |
1414 | return -EINVAL; | |
c4f52879 KR |
1415 | uport->mapbase = res->start; |
1416 | ||
1417 | port->tx_fifo_depth = DEF_FIFO_DEPTH_WORDS; | |
1418 | port->rx_fifo_depth = DEF_FIFO_DEPTH_WORDS; | |
1419 | port->tx_fifo_width = DEF_FIFO_WIDTH_BITS; | |
1420 | ||
f9d690b6 | 1421 | if (!console) { |
1422 | port->rx_fifo = devm_kcalloc(uport->dev, | |
1423 | port->rx_fifo_depth, sizeof(u32), GFP_KERNEL); | |
1424 | if (!port->rx_fifo) | |
1425 | return -ENOMEM; | |
1426 | } | |
1427 | ||
7cf563b2 AA |
1428 | ret = geni_icc_get(&port->se, NULL); |
1429 | if (ret) | |
1430 | return ret; | |
1431 | port->se.icc_paths[GENI_TO_CORE].avg_bw = GENI_DEFAULT_BW; | |
1432 | port->se.icc_paths[CPU_TO_GENI].avg_bw = GENI_DEFAULT_BW; | |
1433 | ||
1434 | /* Set BW for register access */ | |
1435 | ret = geni_icc_set_bw(&port->se); | |
1436 | if (ret) | |
1437 | return ret; | |
1438 | ||
f3974413 AA |
1439 | port->name = devm_kasprintf(uport->dev, GFP_KERNEL, |
1440 | "qcom_geni_serial_%s%d", | |
1441 | uart_console(uport) ? "console" : "uart", uport->line); | |
1442 | if (!port->name) | |
1443 | return -ENOMEM; | |
1444 | ||
066cd1c4 | 1445 | irq = platform_get_irq(pdev, 0); |
1df21786 | 1446 | if (irq < 0) |
066cd1c4 | 1447 | return irq; |
066cd1c4 | 1448 | uport->irq = irq; |
8f122698 | 1449 | uport->has_sysrq = IS_ENABLED(CONFIG_SERIAL_QCOM_GENI_CONSOLE); |
c4f52879 | 1450 | |
f3974413 AA |
1451 | if (!console) |
1452 | port->wakeup_irq = platform_get_irq_optional(pdev, 1); | |
1453 | ||
9fa3c4b1 RRY |
1454 | if (of_property_read_bool(pdev->dev.of_node, "rx-tx-swap")) |
1455 | port->rx_tx_swap = true; | |
1456 | ||
1457 | if (of_property_read_bool(pdev->dev.of_node, "cts-rts-swap")) | |
1458 | port->cts_rts_swap = true; | |
1459 | ||
300894a6 YL |
1460 | ret = devm_pm_opp_set_clkname(&pdev->dev, "se"); |
1461 | if (ret) | |
1462 | return ret; | |
a5819b54 | 1463 | /* OPP table is optional */ |
300894a6 | 1464 | ret = devm_pm_opp_of_add_table(&pdev->dev); |
c7ac46da | 1465 | if (ret && ret != -ENODEV) { |
a5819b54 | 1466 | dev_err(&pdev->dev, "invalid OPP table in device tree\n"); |
300894a6 | 1467 | return ret; |
a5819b54 RN |
1468 | } |
1469 | ||
e42d6c3e DA |
1470 | port->private_data.drv = drv; |
1471 | uport->private_data = &port->private_data; | |
f3974413 AA |
1472 | platform_set_drvdata(pdev, port); |
1473 | port->handle_rx = console ? handle_rx_console : handle_rx_uart; | |
f3974413 AA |
1474 | |
1475 | ret = uart_add_one_port(drv, uport); | |
1476 | if (ret) | |
300894a6 | 1477 | return ret; |
f3974413 | 1478 | |
3e4aaea7 AA |
1479 | irq_set_status_flags(uport->irq, IRQ_NOAUTOEN); |
1480 | ret = devm_request_irq(uport->dev, uport->irq, qcom_geni_serial_isr, | |
1481 | IRQF_TRIGGER_HIGH, port->name, uport); | |
1482 | if (ret) { | |
1483 | dev_err(uport->dev, "Failed to get IRQ ret %d\n", ret); | |
f3974413 | 1484 | uart_remove_one_port(drv, uport); |
300894a6 | 1485 | return ret; |
3e4aaea7 AA |
1486 | } |
1487 | ||
f3974413 AA |
1488 | /* |
1489 | * Set pm_runtime status as ACTIVE so that wakeup_irq gets | |
1490 | * enabled/disabled from dev_pm_arm_wake_irq during system | |
1491 | * suspend/resume respectively. | |
1492 | */ | |
1493 | pm_runtime_set_active(&pdev->dev); | |
1494 | ||
1495 | if (port->wakeup_irq > 0) { | |
1496 | device_init_wakeup(&pdev->dev, true); | |
1497 | ret = dev_pm_set_dedicated_wake_irq(&pdev->dev, | |
1498 | port->wakeup_irq); | |
1499 | if (ret) { | |
1500 | device_init_wakeup(&pdev->dev, false); | |
1501 | uart_remove_one_port(drv, uport); | |
300894a6 | 1502 | return ret; |
8b7103f3 AA |
1503 | } |
1504 | } | |
f3974413 AA |
1505 | |
1506 | return 0; | |
c4f52879 KR |
1507 | } |
1508 | ||
1509 | static int qcom_geni_serial_remove(struct platform_device *pdev) | |
1510 | { | |
1511 | struct qcom_geni_serial_port *port = platform_get_drvdata(pdev); | |
e42d6c3e | 1512 | struct uart_driver *drv = port->private_data.drv; |
c4f52879 | 1513 | |
f3974413 AA |
1514 | dev_pm_clear_wake_irq(&pdev->dev); |
1515 | device_init_wakeup(&pdev->dev, false); | |
c4f52879 | 1516 | uart_remove_one_port(drv, &port->uport); |
f3974413 | 1517 | |
c4f52879 KR |
1518 | return 0; |
1519 | } | |
1520 | ||
b1f84dd3 | 1521 | static int __maybe_unused qcom_geni_serial_sys_suspend(struct device *dev) |
c4f52879 | 1522 | { |
a406c4b8 | 1523 | struct qcom_geni_serial_port *port = dev_get_drvdata(dev); |
c4f52879 | 1524 | struct uart_port *uport = &port->uport; |
e42d6c3e | 1525 | struct qcom_geni_private_data *private_data = uport->private_data; |
c4f52879 | 1526 | |
4a3107f6 RN |
1527 | /* |
1528 | * This is done so we can hit the lowest possible state in suspend | |
1529 | * even with no_console_suspend | |
1530 | */ | |
1531 | if (uart_console(uport)) { | |
408e532e | 1532 | geni_icc_set_tag(&port->se, QCOM_ICC_TAG_ACTIVE_ONLY); |
4a3107f6 RN |
1533 | geni_icc_set_bw(&port->se); |
1534 | } | |
e42d6c3e | 1535 | return uart_suspend_port(private_data->drv, uport); |
c4f52879 KR |
1536 | } |
1537 | ||
b1f84dd3 | 1538 | static int __maybe_unused qcom_geni_serial_sys_resume(struct device *dev) |
c4f52879 | 1539 | { |
4a3107f6 | 1540 | int ret; |
a406c4b8 | 1541 | struct qcom_geni_serial_port *port = dev_get_drvdata(dev); |
c4f52879 | 1542 | struct uart_port *uport = &port->uport; |
e42d6c3e | 1543 | struct qcom_geni_private_data *private_data = uport->private_data; |
c4f52879 | 1544 | |
4a3107f6 RN |
1545 | ret = uart_resume_port(private_data->drv, uport); |
1546 | if (uart_console(uport)) { | |
408e532e | 1547 | geni_icc_set_tag(&port->se, QCOM_ICC_TAG_ALWAYS); |
4a3107f6 RN |
1548 | geni_icc_set_bw(&port->se); |
1549 | } | |
1550 | return ret; | |
c4f52879 KR |
1551 | } |
1552 | ||
35781d83 AR |
1553 | static int qcom_geni_serial_sys_hib_resume(struct device *dev) |
1554 | { | |
1555 | int ret = 0; | |
1556 | struct uart_port *uport; | |
1557 | struct qcom_geni_private_data *private_data; | |
1558 | struct qcom_geni_serial_port *port = dev_get_drvdata(dev); | |
1559 | ||
1560 | uport = &port->uport; | |
1561 | private_data = uport->private_data; | |
1562 | ||
1563 | if (uart_console(uport)) { | |
1564 | geni_icc_set_tag(&port->se, 0x7); | |
1565 | geni_icc_set_bw(&port->se); | |
1566 | ret = uart_resume_port(private_data->drv, uport); | |
1567 | /* | |
1568 | * For hibernation usecase clients for | |
1569 | * console UART won't call port setup during restore, | |
1570 | * hence call port setup for console uart. | |
1571 | */ | |
1572 | qcom_geni_serial_port_setup(uport); | |
1573 | } else { | |
1574 | /* | |
1575 | * Peripheral register settings are lost during hibernation. | |
1576 | * Update setup flag such that port setup happens again | |
1577 | * during next session. Clients of HS-UART will close and | |
1578 | * open the port during hibernation. | |
1579 | */ | |
1580 | port->setup = false; | |
1581 | } | |
1582 | return ret; | |
1583 | } | |
1584 | ||
c4f52879 | 1585 | static const struct dev_pm_ops qcom_geni_serial_pm_ops = { |
b1f84dd3 MKS |
1586 | SET_SYSTEM_SLEEP_PM_OPS(qcom_geni_serial_sys_suspend, |
1587 | qcom_geni_serial_sys_resume) | |
35781d83 AR |
1588 | .restore = qcom_geni_serial_sys_hib_resume, |
1589 | .thaw = qcom_geni_serial_sys_hib_resume, | |
c4f52879 KR |
1590 | }; |
1591 | ||
1592 | static const struct of_device_id qcom_geni_serial_match_table[] = { | |
1593 | { .compatible = "qcom,geni-debug-uart", }, | |
8a8a66a1 | 1594 | { .compatible = "qcom,geni-uart", }, |
c4f52879 KR |
1595 | {} |
1596 | }; | |
1597 | MODULE_DEVICE_TABLE(of, qcom_geni_serial_match_table); | |
1598 | ||
1599 | static struct platform_driver qcom_geni_serial_platform_driver = { | |
1600 | .remove = qcom_geni_serial_remove, | |
1601 | .probe = qcom_geni_serial_probe, | |
1602 | .driver = { | |
1603 | .name = "qcom_geni_serial", | |
1604 | .of_match_table = qcom_geni_serial_match_table, | |
1605 | .pm = &qcom_geni_serial_pm_ops, | |
1606 | }, | |
1607 | }; | |
1608 | ||
1609 | static int __init qcom_geni_serial_init(void) | |
1610 | { | |
1611 | int ret; | |
1612 | ||
c4f52879 KR |
1613 | ret = console_register(&qcom_geni_console_driver); |
1614 | if (ret) | |
1615 | return ret; | |
1616 | ||
8a8a66a1 GM |
1617 | ret = uart_register_driver(&qcom_geni_uart_driver); |
1618 | if (ret) { | |
1619 | console_unregister(&qcom_geni_console_driver); | |
1620 | return ret; | |
1621 | } | |
1622 | ||
c4f52879 | 1623 | ret = platform_driver_register(&qcom_geni_serial_platform_driver); |
8a8a66a1 | 1624 | if (ret) { |
c4f52879 | 1625 | console_unregister(&qcom_geni_console_driver); |
8a8a66a1 GM |
1626 | uart_unregister_driver(&qcom_geni_uart_driver); |
1627 | } | |
c4f52879 KR |
1628 | return ret; |
1629 | } | |
1630 | module_init(qcom_geni_serial_init); | |
1631 | ||
1632 | static void __exit qcom_geni_serial_exit(void) | |
1633 | { | |
1634 | platform_driver_unregister(&qcom_geni_serial_platform_driver); | |
1635 | console_unregister(&qcom_geni_console_driver); | |
8a8a66a1 | 1636 | uart_unregister_driver(&qcom_geni_uart_driver); |
c4f52879 KR |
1637 | } |
1638 | module_exit(qcom_geni_serial_exit); | |
1639 | ||
1640 | MODULE_DESCRIPTION("Serial driver for GENI based QUP cores"); | |
1641 | MODULE_LICENSE("GPL v2"); |