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tty: serial: qcom_geni_serial: Use min3 to find minimum of 3 values
[linux-2.6-block.git] / drivers / tty / serial / qcom_geni_serial.c
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c4f52879
KR		 1// SPDX-License-Identifier: GPL-2.0
2// Copyright (c) 2017-2018, The Linux foundation. All rights reserved.
3
4#include <linux/clk.h>
5#include <linux/console.h>
6#include <linux/io.h>
7#include <linux/iopoll.h>
8#include <linux/module.h>
9#include <linux/of.h>
10#include <linux/of_device.h>
11#include <linux/platform_device.h>
12#include <linux/qcom-geni-se.h>
13#include <linux/serial.h>
14#include <linux/serial_core.h>
15#include <linux/slab.h>
16#include <linux/tty.h>
17#include <linux/tty_flip.h>
18
19/* UART specific GENI registers */
20#define SE_UART_TX_TRANS_CFG 0x25c
21#define SE_UART_TX_WORD_LEN 0x268
22#define SE_UART_TX_STOP_BIT_LEN 0x26c
23#define SE_UART_TX_TRANS_LEN 0x270
24#define SE_UART_RX_TRANS_CFG 0x280
25#define SE_UART_RX_WORD_LEN 0x28c
26#define SE_UART_RX_STALE_CNT 0x294
27#define SE_UART_TX_PARITY_CFG 0x2a4
28#define SE_UART_RX_PARITY_CFG 0x2a8
29
30/* SE_UART_TRANS_CFG */
31#define UART_TX_PAR_EN BIT(0)
32#define UART_CTS_MASK BIT(1)
33
34/* SE_UART_TX_WORD_LEN */
35#define TX_WORD_LEN_MSK GENMASK(9, 0)
36
37/* SE_UART_TX_STOP_BIT_LEN */
38#define TX_STOP_BIT_LEN_MSK GENMASK(23, 0)
39#define TX_STOP_BIT_LEN_1 0
40#define TX_STOP_BIT_LEN_1_5 1
41#define TX_STOP_BIT_LEN_2 2
42
43/* SE_UART_TX_TRANS_LEN */
44#define TX_TRANS_LEN_MSK GENMASK(23, 0)
45
46/* SE_UART_RX_TRANS_CFG */
47#define UART_RX_INS_STATUS_BIT BIT(2)
48#define UART_RX_PAR_EN BIT(3)
49
50/* SE_UART_RX_WORD_LEN */
51#define RX_WORD_LEN_MASK GENMASK(9, 0)
52
53/* SE_UART_RX_STALE_CNT */
54#define RX_STALE_CNT GENMASK(23, 0)
55
56/* SE_UART_TX_PARITY_CFG/RX_PARITY_CFG */
57#define PAR_CALC_EN BIT(0)
58#define PAR_MODE_MSK GENMASK(2, 1)
59#define PAR_MODE_SHFT 1
60#define PAR_EVEN 0x00
61#define PAR_ODD 0x01
62#define PAR_SPACE 0x10
63#define PAR_MARK 0x11
64
65/* UART M_CMD OP codes */
66#define UART_START_TX 0x1
67#define UART_START_BREAK 0x4
68#define UART_STOP_BREAK 0x5
69/* UART S_CMD OP codes */
70#define UART_START_READ 0x1
71#define UART_PARAM 0x1
72
73#define UART_OVERSAMPLING 32
74#define STALE_TIMEOUT 16
75#define DEFAULT_BITS_PER_CHAR 10
76#define GENI_UART_CONS_PORTS 1
77#define DEF_FIFO_DEPTH_WORDS 16
78#define DEF_TX_WM 2
79#define DEF_FIFO_WIDTH_BITS 32
80#define UART_CONSOLE_RX_WM 2
81
82#ifdef CONFIG_CONSOLE_POLL
83#define RX_BYTES_PW 1
84#else
85#define RX_BYTES_PW 4
86#endif
87
88struct qcom_geni_serial_port {
89 struct uart_port uport;
90 struct geni_se se;
91 char name[20];
92 u32 tx_fifo_depth;
93 u32 tx_fifo_width;
94 u32 rx_fifo_depth;
95 u32 tx_wm;
96 u32 rx_wm;
97 u32 rx_rfr;
98 enum geni_se_xfer_mode xfer_mode;
99 bool setup;
100 int (*handle_rx)(struct uart_port *uport, u32 bytes, bool drop);
101 unsigned int xmit_size;
102 unsigned int baud;
103 unsigned int tx_bytes_pw;
104 unsigned int rx_bytes_pw;
105 bool brk;
106};
107
108static const struct uart_ops qcom_geni_serial_pops;
109static struct uart_driver qcom_geni_console_driver;
110static int handle_rx_console(struct uart_port *uport, u32 bytes, bool drop);
111static unsigned int qcom_geni_serial_tx_empty(struct uart_port *port);
112static void qcom_geni_serial_stop_rx(struct uart_port *uport);
113
114static const unsigned long root_freq[] = {7372800, 14745600, 19200000, 29491200,
115 32000000, 48000000, 64000000, 80000000,
116 96000000, 100000000};
117
118#define to_dev_port(ptr, member) \
119 container_of(ptr, struct qcom_geni_serial_port, member)
120
121static struct qcom_geni_serial_port qcom_geni_console_port;
122
123static int qcom_geni_serial_request_port(struct uart_port *uport)
124{
125 struct platform_device *pdev = to_platform_device(uport->dev);
126 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
127 struct resource *res;
128
129 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
130 uport->membase = devm_ioremap_resource(&pdev->dev, res);
131 if (IS_ERR(uport->membase))
132 return PTR_ERR(uport->membase);
133 port->se.base = uport->membase;
134 return 0;
135}
136
137static void qcom_geni_serial_config_port(struct uart_port *uport, int cfg_flags)
138{
139 if (cfg_flags & UART_CONFIG_TYPE) {
140 uport->type = PORT_MSM;
141 qcom_geni_serial_request_port(uport);
142 }
143}
144
145static unsigned int qcom_geni_cons_get_mctrl(struct uart_port *uport)
146{
147 return TIOCM_DSR | TIOCM_CAR | TIOCM_CTS;
148}
149
150static void qcom_geni_cons_set_mctrl(struct uart_port *uport,
151 unsigned int mctrl)
152{
153}
154
155static const char *qcom_geni_serial_get_type(struct uart_port *uport)
156{
157 return "MSM";
158}
159
160static struct qcom_geni_serial_port *get_port_from_line(int line)
161{
162 if (line < 0 || line >= GENI_UART_CONS_PORTS)
163 return ERR_PTR(-ENXIO);
164 return &qcom_geni_console_port;
165}
166
167static bool qcom_geni_serial_poll_bit(struct uart_port *uport,
168 int offset, int field, bool set)
169{
170 u32 reg;
171 struct qcom_geni_serial_port *port;
172 unsigned int baud;
173 unsigned int fifo_bits;
174 unsigned long timeout_us = 20000;
175
176 /* Ensure polling is not re-ordered before the prior writes/reads */
177 mb();
178
179 if (uport->private_data) {
180 port = to_dev_port(uport, uport);
181 baud = port->baud;
182 if (!baud)
183 baud = 115200;
184 fifo_bits = port->tx_fifo_depth * port->tx_fifo_width;
185 /*
186 * Total polling iterations based on FIFO worth of bytes to be
187 * sent at current baud. Add a little fluff to the wait.
188 */
189 timeout_us = ((fifo_bits * USEC_PER_SEC) / baud) + 500;
190 }
191
192 return !readl_poll_timeout_atomic(uport->membase + offset, reg,
193 (bool)(reg & field) == set, 10, timeout_us);
194}
195
196static void qcom_geni_serial_setup_tx(struct uart_port *uport, u32 xmit_size)
197{
198 u32 m_cmd;
199
200 writel_relaxed(xmit_size, uport->membase + SE_UART_TX_TRANS_LEN);
201 m_cmd = UART_START_TX << M_OPCODE_SHFT;
202 writel(m_cmd, uport->membase + SE_GENI_M_CMD0);
203}
204
205static void qcom_geni_serial_poll_tx_done(struct uart_port *uport)
206{
207 int done;
208 u32 irq_clear = M_CMD_DONE_EN;
209
210 done = qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
211 M_CMD_DONE_EN, true);
212 if (!done) {
213 writel_relaxed(M_GENI_CMD_ABORT, uport->membase +
214 SE_GENI_M_CMD_CTRL_REG);
215 irq_clear |= M_CMD_ABORT_EN;
216 qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
217 M_CMD_ABORT_EN, true);
218 }
219 writel_relaxed(irq_clear, uport->membase + SE_GENI_M_IRQ_CLEAR);
220}
221
222static void qcom_geni_serial_abort_rx(struct uart_port *uport)
223{
224 u32 irq_clear = S_CMD_DONE_EN | S_CMD_ABORT_EN;
225
226 writel(S_GENI_CMD_ABORT, uport->membase + SE_GENI_S_CMD_CTRL_REG);
227 qcom_geni_serial_poll_bit(uport, SE_GENI_S_CMD_CTRL_REG,
228 S_GENI_CMD_ABORT, false);
229 writel_relaxed(irq_clear, uport->membase + SE_GENI_S_IRQ_CLEAR);
230 writel_relaxed(FORCE_DEFAULT, uport->membase + GENI_FORCE_DEFAULT_REG);
231}
232
233#ifdef CONFIG_CONSOLE_POLL
234static int qcom_geni_serial_get_char(struct uart_port *uport)
235{
236 u32 rx_fifo;
237 u32 status;
238
239 status = readl_relaxed(uport->membase + SE_GENI_M_IRQ_STATUS);
240 writel_relaxed(status, uport->membase + SE_GENI_M_IRQ_CLEAR);
241
242 status = readl_relaxed(uport->membase + SE_GENI_S_IRQ_STATUS);
243 writel_relaxed(status, uport->membase + SE_GENI_S_IRQ_CLEAR);
244
245 /*
246 * Ensure the writes to clear interrupts is not re-ordered after
247 * reading the data.
248 */
249 mb();
250
251 status = readl_relaxed(uport->membase + SE_GENI_RX_FIFO_STATUS);
252 if (!(status & RX_FIFO_WC_MSK))
253 return NO_POLL_CHAR;
254
255 rx_fifo = readl(uport->membase + SE_GENI_RX_FIFOn);
256 return rx_fifo & 0xff;
257}
258
259static void qcom_geni_serial_poll_put_char(struct uart_port *uport,
260 unsigned char c)
261{
262 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
263
264 writel_relaxed(port->tx_wm, uport->membase + SE_GENI_TX_WATERMARK_REG);
265 qcom_geni_serial_setup_tx(uport, 1);
266 WARN_ON(!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
267 M_TX_FIFO_WATERMARK_EN, true));
268 writel_relaxed(c, uport->membase + SE_GENI_TX_FIFOn);
269 writel_relaxed(M_TX_FIFO_WATERMARK_EN, uport->membase +
270 SE_GENI_M_IRQ_CLEAR);
271 qcom_geni_serial_poll_tx_done(uport);
272}
273#endif
274
275#ifdef CONFIG_SERIAL_QCOM_GENI_CONSOLE
276static void qcom_geni_serial_wr_char(struct uart_port *uport, int ch)
277{
278 writel_relaxed(ch, uport->membase + SE_GENI_TX_FIFOn);
279}
280
281static void
282__qcom_geni_serial_console_write(struct uart_port *uport, const char *s,
283 unsigned int count)
284{
285 int i;
286 u32 bytes_to_send = count;
287
288 for (i = 0; i < count; i++) {
f0262568
KR		 289 /*
290 * uart_console_write() adds a carriage return for each newline.
291 * Account for additional bytes to be written.
292 */
c4f52879
KR		 293 if (s[i] == '\n')
294 bytes_to_send++;
295 }
296
297 writel_relaxed(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG);
298 qcom_geni_serial_setup_tx(uport, bytes_to_send);
299 for (i = 0; i < count; ) {
300 size_t chars_to_write = 0;
301 size_t avail = DEF_FIFO_DEPTH_WORDS - DEF_TX_WM;
302
303 /*
304 * If the WM bit never set, then the Tx state machine is not
305 * in a valid state, so break, cancel/abort any existing
306 * command. Unfortunately the current data being written is
307 * lost.
308 */
309 if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
310 M_TX_FIFO_WATERMARK_EN, true))
311 break;
6a10635e 312 chars_to_write = min_t(size_t, count - i, avail / 2);
c4f52879
KR		 313 uart_console_write(uport, s + i, chars_to_write,
314 qcom_geni_serial_wr_char);
315 writel_relaxed(M_TX_FIFO_WATERMARK_EN, uport->membase +
316 SE_GENI_M_IRQ_CLEAR);
317 i += chars_to_write;
318 }
319 qcom_geni_serial_poll_tx_done(uport);
320}
321
322static void qcom_geni_serial_console_write(struct console *co, const char *s,
323 unsigned int count)
324{
325 struct uart_port *uport;
326 struct qcom_geni_serial_port *port;
327 bool locked = true;
328 unsigned long flags;
329
330 WARN_ON(co->index < 0 || co->index >= GENI_UART_CONS_PORTS);
331
332 port = get_port_from_line(co->index);
333 if (IS_ERR(port))
334 return;
335
336 uport = &port->uport;
337 if (oops_in_progress)
338 locked = spin_trylock_irqsave(&uport->lock, flags);
339 else
340 spin_lock_irqsave(&uport->lock, flags);
341
342 /* Cancel the current write to log the fault */
343 if (!locked) {
344 geni_se_cancel_m_cmd(&port->se);
345 if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
346 M_CMD_CANCEL_EN, true)) {
347 geni_se_abort_m_cmd(&port->se);
348 qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
349 M_CMD_ABORT_EN, true);
350 writel_relaxed(M_CMD_ABORT_EN, uport->membase +
351 SE_GENI_M_IRQ_CLEAR);
352 }
353 writel_relaxed(M_CMD_CANCEL_EN, uport->membase +
354 SE_GENI_M_IRQ_CLEAR);
355 }
356
357 __qcom_geni_serial_console_write(uport, s, count);
358 if (locked)
359 spin_unlock_irqrestore(&uport->lock, flags);
360}
361
362static int handle_rx_console(struct uart_port *uport, u32 bytes, bool drop)
363{
364 u32 i;
365 unsigned char buf[sizeof(u32)];
366 struct tty_port *tport;
367 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
368
369 tport = &uport->state->port;
370 for (i = 0; i < bytes; ) {
371 int c;
372 int chunk = min_t(int, bytes - i, port->rx_bytes_pw);
373
374 ioread32_rep(uport->membase + SE_GENI_RX_FIFOn, buf, 1);
375 i += chunk;
376 if (drop)
377 continue;
378
379 for (c = 0; c < chunk; c++) {
380 int sysrq;
381
382 uport->icount.rx++;
383 if (port->brk && buf[c] == 0) {
384 port->brk = false;
385 if (uart_handle_break(uport))
386 continue;
387 }
388
389 sysrq = uart_handle_sysrq_char(uport, buf[c]);
390 if (!sysrq)
391 tty_insert_flip_char(tport, buf[c], TTY_NORMAL);
392 }
393 }
394 if (!drop)
395 tty_flip_buffer_push(tport);
396 return 0;
397}
398#else
399static int handle_rx_console(struct uart_port *uport, u32 bytes, bool drop)
400{
401 return -EPERM;
402}
403
404#endif /* CONFIG_SERIAL_QCOM_GENI_CONSOLE */
405
406static void qcom_geni_serial_start_tx(struct uart_port *uport)
407{
408 u32 irq_en;
409 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
410 u32 status;
411
412 if (port->xfer_mode == GENI_SE_FIFO) {
413 status = readl_relaxed(uport->membase + SE_GENI_STATUS);
414 if (status & M_GENI_CMD_ACTIVE)
415 return;
416
417 if (!qcom_geni_serial_tx_empty(uport))
418 return;
419
420 /*
421 * Ensure writing to IRQ_EN & watermark registers are not
422 * re-ordered before checking the status of the Serial
423 * Engine and TX FIFO
424 */
425 mb();
426
427 irq_en = readl_relaxed(uport->membase + SE_GENI_M_IRQ_EN);
428 irq_en |= M_TX_FIFO_WATERMARK_EN | M_CMD_DONE_EN;
429
430 writel_relaxed(port->tx_wm, uport->membase +
431 SE_GENI_TX_WATERMARK_REG);
432 writel_relaxed(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
433 }
434}
435
436static void qcom_geni_serial_stop_tx(struct uart_port *uport)
437{
438 u32 irq_en;
439 u32 status;
440 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
441
442 irq_en = readl_relaxed(uport->membase + SE_GENI_M_IRQ_EN);
443 irq_en &= ~M_CMD_DONE_EN;
444 if (port->xfer_mode == GENI_SE_FIFO) {
445 irq_en &= ~M_TX_FIFO_WATERMARK_EN;
446 writel_relaxed(0, uport->membase +
447 SE_GENI_TX_WATERMARK_REG);
448 }
449 port->xmit_size = 0;
450 writel_relaxed(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
451 status = readl_relaxed(uport->membase + SE_GENI_STATUS);
452 /* Possible stop tx is called multiple times. */
453 if (!(status & M_GENI_CMD_ACTIVE))
454 return;
455
456 /*
457 * Ensure cancel command write is not re-ordered before checking
458 * the status of the Primary Sequencer.
459 */
460 mb();
461
462 geni_se_cancel_m_cmd(&port->se);
463 if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
464 M_CMD_CANCEL_EN, true)) {
465 geni_se_abort_m_cmd(&port->se);
466 qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
467 M_CMD_ABORT_EN, true);
468 writel_relaxed(M_CMD_ABORT_EN, uport->membase +
469 SE_GENI_M_IRQ_CLEAR);
470 }
471 writel_relaxed(M_CMD_CANCEL_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
472}
473
474static void qcom_geni_serial_start_rx(struct uart_port *uport)
475{
476 u32 irq_en;
477 u32 status;
478 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
479
480 status = readl_relaxed(uport->membase + SE_GENI_STATUS);
481 if (status & S_GENI_CMD_ACTIVE)
482 qcom_geni_serial_stop_rx(uport);
483
484 /*
485 * Ensure setup command write is not re-ordered before checking
486 * the status of the Secondary Sequencer.
487 */
488 mb();
489
490 geni_se_setup_s_cmd(&port->se, UART_START_READ, 0);
491
492 if (port->xfer_mode == GENI_SE_FIFO) {
493 irq_en = readl_relaxed(uport->membase + SE_GENI_S_IRQ_EN);
494 irq_en |= S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN;
495 writel_relaxed(irq_en, uport->membase + SE_GENI_S_IRQ_EN);
496
497 irq_en = readl_relaxed(uport->membase + SE_GENI_M_IRQ_EN);
498 irq_en |= M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN;
499 writel_relaxed(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
500 }
501}
502
503static void qcom_geni_serial_stop_rx(struct uart_port *uport)
504{
505 u32 irq_en;
506 u32 status;
507 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
508 u32 irq_clear = S_CMD_DONE_EN;
509
510 if (port->xfer_mode == GENI_SE_FIFO) {
511 irq_en = readl_relaxed(uport->membase + SE_GENI_S_IRQ_EN);
512 irq_en &= ~(S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN);
513 writel_relaxed(irq_en, uport->membase + SE_GENI_S_IRQ_EN);
514
515 irq_en = readl_relaxed(uport->membase + SE_GENI_M_IRQ_EN);
516 irq_en &= ~(M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN);
517 writel_relaxed(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
518 }
519
520 status = readl_relaxed(uport->membase + SE_GENI_STATUS);
521 /* Possible stop rx is called multiple times. */
522 if (!(status & S_GENI_CMD_ACTIVE))
523 return;
524
525 /*
526 * Ensure cancel command write is not re-ordered before checking
527 * the status of the Secondary Sequencer.
528 */
529 mb();
530
531 geni_se_cancel_s_cmd(&port->se);
532 qcom_geni_serial_poll_bit(uport, SE_GENI_S_CMD_CTRL_REG,
533 S_GENI_CMD_CANCEL, false);
534 status = readl_relaxed(uport->membase + SE_GENI_STATUS);
535 writel_relaxed(irq_clear, uport->membase + SE_GENI_S_IRQ_CLEAR);
536 if (status & S_GENI_CMD_ACTIVE)
537 qcom_geni_serial_abort_rx(uport);
538}
539
540static void qcom_geni_serial_handle_rx(struct uart_port *uport, bool drop)
541{
542 u32 status;
543 u32 word_cnt;
544 u32 last_word_byte_cnt;
545 u32 last_word_partial;
546 u32 total_bytes;
547 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
548
549 status = readl_relaxed(uport->membase + SE_GENI_RX_FIFO_STATUS);
550 word_cnt = status & RX_FIFO_WC_MSK;
551 last_word_partial = status & RX_LAST;
552 last_word_byte_cnt = (status & RX_LAST_BYTE_VALID_MSK) >>
553 RX_LAST_BYTE_VALID_SHFT;
554
555 if (!word_cnt)
556 return;
557 total_bytes = port->rx_bytes_pw * (word_cnt - 1);
558 if (last_word_partial && last_word_byte_cnt)
559 total_bytes += last_word_byte_cnt;
560 else
561 total_bytes += port->rx_bytes_pw;
562 port->handle_rx(uport, total_bytes, drop);
563}
564
565static void qcom_geni_serial_handle_tx(struct uart_port *uport)
566{
567 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
568 struct circ_buf *xmit = &uport->state->xmit;
569 size_t avail;
570 size_t remaining;
571 int i;
572 u32 status;
573 unsigned int chunk;
574 int tail;
575
576 chunk = uart_circ_chars_pending(xmit);
577 status = readl_relaxed(uport->membase + SE_GENI_TX_FIFO_STATUS);
578 /* Both FIFO and framework buffer are drained */
579 if (chunk == port->xmit_size && !status) {
580 port->xmit_size = 0;
581 uart_circ_clear(xmit);
582 qcom_geni_serial_stop_tx(uport);
583 goto out_write_wakeup;
584 }
585 chunk -= port->xmit_size;
586
587 avail = (port->tx_fifo_depth - port->tx_wm) * port->tx_bytes_pw;
588 tail = (xmit->tail + port->xmit_size) & (UART_XMIT_SIZE - 1);
8e70c47c 589 chunk = min3((size_t)chunk, (size_t)(UART_XMIT_SIZE - tail), avail);
c4f52879
KR		 590 if (!chunk)
591 goto out_write_wakeup;
592
593 qcom_geni_serial_setup_tx(uport, chunk);
594
595 remaining = chunk;
596 for (i = 0; i < chunk; ) {
597 unsigned int tx_bytes;
598 unsigned int buf = 0;
599 int c;
600
6a10635e 601 tx_bytes = min_t(size_t, remaining, port->tx_bytes_pw);
c4f52879
KR		 602 for (c = 0; c < tx_bytes ; c++)
603 buf |= (xmit->buf[tail + c] << (c * BITS_PER_BYTE));
604
605 writel_relaxed(buf, uport->membase + SE_GENI_TX_FIFOn);
606
607 i += tx_bytes;
608 tail = (tail + tx_bytes) & (UART_XMIT_SIZE - 1);
609 uport->icount.tx += tx_bytes;
610 remaining -= tx_bytes;
611 }
612 qcom_geni_serial_poll_tx_done(uport);
613 port->xmit_size += chunk;
614out_write_wakeup:
615 uart_write_wakeup(uport);
616}
617
618static irqreturn_t qcom_geni_serial_isr(int isr, void *dev)
619{
620 unsigned int m_irq_status;
621 unsigned int s_irq_status;
622 struct uart_port *uport = dev;
623 unsigned long flags;
624 unsigned int m_irq_en;
625 bool drop_rx = false;
626 struct tty_port *tport = &uport->state->port;
627 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
628
629 if (uport->suspended)
630 return IRQ_HANDLED;
631
632 spin_lock_irqsave(&uport->lock, flags);
633 m_irq_status = readl_relaxed(uport->membase + SE_GENI_M_IRQ_STATUS);
634 s_irq_status = readl_relaxed(uport->membase + SE_GENI_S_IRQ_STATUS);
635 m_irq_en = readl_relaxed(uport->membase + SE_GENI_M_IRQ_EN);
636 writel_relaxed(m_irq_status, uport->membase + SE_GENI_M_IRQ_CLEAR);
637 writel_relaxed(s_irq_status, uport->membase + SE_GENI_S_IRQ_CLEAR);
638
639 if (WARN_ON(m_irq_status & M_ILLEGAL_CMD_EN))
640 goto out_unlock;
641
642 if (s_irq_status & S_RX_FIFO_WR_ERR_EN) {
643 uport->icount.overrun++;
644 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
645 }
646
647 if (m_irq_status & (M_TX_FIFO_WATERMARK_EN | M_CMD_DONE_EN) &&
648 m_irq_en & (M_TX_FIFO_WATERMARK_EN | M_CMD_DONE_EN))
649 qcom_geni_serial_handle_tx(uport);
650
651 if (s_irq_status & S_GP_IRQ_0_EN || s_irq_status & S_GP_IRQ_1_EN) {
652 if (s_irq_status & S_GP_IRQ_0_EN)
653 uport->icount.parity++;
654 drop_rx = true;
655 } else if (s_irq_status & S_GP_IRQ_2_EN ||
656 s_irq_status & S_GP_IRQ_3_EN) {
657 uport->icount.brk++;
658 port->brk = true;
659 }
660
661 if (s_irq_status & S_RX_FIFO_WATERMARK_EN ||
662 s_irq_status & S_RX_FIFO_LAST_EN)
663 qcom_geni_serial_handle_rx(uport, drop_rx);
664
665out_unlock:
666 spin_unlock_irqrestore(&uport->lock, flags);
667 return IRQ_HANDLED;
668}
669
6a10635e 670static void get_tx_fifo_size(struct qcom_geni_serial_port *port)
c4f52879
KR		 671{
672 struct uart_port *uport;
673
c4f52879
KR		 674 uport = &port->uport;
675 port->tx_fifo_depth = geni_se_get_tx_fifo_depth(&port->se);
676 port->tx_fifo_width = geni_se_get_tx_fifo_width(&port->se);
677 port->rx_fifo_depth = geni_se_get_rx_fifo_depth(&port->se);
678 uport->fifosize =
679 (port->tx_fifo_depth * port->tx_fifo_width) / BITS_PER_BYTE;
c4f52879
KR		 680}
681
682static void set_rfr_wm(struct qcom_geni_serial_port *port)
683{
684 /*
685 * Set RFR (Flow off) to FIFO_DEPTH - 2.
686 * RX WM level at 10% RX_FIFO_DEPTH.
687 * TX WM level at 10% TX_FIFO_DEPTH.
688 */
689 port->rx_rfr = port->rx_fifo_depth - 2;
690 port->rx_wm = UART_CONSOLE_RX_WM;
691 port->tx_wm = DEF_TX_WM;
692}
693
694static void qcom_geni_serial_shutdown(struct uart_port *uport)
695{
696 unsigned long flags;
697
698 /* Stop the console before stopping the current tx */
699 console_stop(uport->cons);
700
c4f52879
KR		 701 free_irq(uport->irq, uport);
702 spin_lock_irqsave(&uport->lock, flags);
703 qcom_geni_serial_stop_tx(uport);
704 qcom_geni_serial_stop_rx(uport);
705 spin_unlock_irqrestore(&uport->lock, flags);
706}
707
708static int qcom_geni_serial_port_setup(struct uart_port *uport)
709{
710 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
711 unsigned int rxstale = DEFAULT_BITS_PER_CHAR * STALE_TIMEOUT;
712
713 set_rfr_wm(port);
714 writel_relaxed(rxstale, uport->membase + SE_UART_RX_STALE_CNT);
715 /*
716 * Make an unconditional cancel on the main sequencer to reset
717 * it else we could end up in data loss scenarios.
718 */
719 port->xfer_mode = GENI_SE_FIFO;
720 qcom_geni_serial_poll_tx_done(uport);
721 geni_se_config_packing(&port->se, BITS_PER_BYTE, port->tx_bytes_pw,
722 false, true, false);
723 geni_se_config_packing(&port->se, BITS_PER_BYTE, port->rx_bytes_pw,
724 false, false, true);
725 geni_se_init(&port->se, port->rx_wm, port->rx_rfr);
726 geni_se_select_mode(&port->se, port->xfer_mode);
727 port->setup = true;
728 return 0;
729}
730
731static int qcom_geni_serial_startup(struct uart_port *uport)
732{
733 int ret;
734 u32 proto;
735 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
736
737 scnprintf(port->name, sizeof(port->name),
738 "qcom_serial_geni%d", uport->line);
739
740 proto = geni_se_read_proto(&port->se);
741 if (proto != GENI_SE_UART) {
742 dev_err(uport->dev, "Invalid FW loaded, proto: %d\n", proto);
743 return -ENXIO;
744 }
745
746 get_tx_fifo_size(port);
747 if (!port->setup) {
748 ret = qcom_geni_serial_port_setup(uport);
749 if (ret)
750 return ret;
751 }
752
753 ret = request_irq(uport->irq, qcom_geni_serial_isr, IRQF_TRIGGER_HIGH,
754 port->name, uport);
755 if (ret)
756 dev_err(uport->dev, "Failed to get IRQ ret %d\n", ret);
757 return ret;
758}
759
760static unsigned long get_clk_cfg(unsigned long clk_freq)
761{
762 int i;
763
764 for (i = 0; i < ARRAY_SIZE(root_freq); i++) {
765 if (!(root_freq[i] % clk_freq))
766 return root_freq[i];
767 }
768 return 0;
769}
770
771static unsigned long get_clk_div_rate(unsigned int baud, unsigned int *clk_div)
772{
773 unsigned long ser_clk;
774 unsigned long desired_clk;
775
776 desired_clk = baud * UART_OVERSAMPLING;
777 ser_clk = get_clk_cfg(desired_clk);
778 if (!ser_clk) {
779 pr_err("%s: Can't find matching DFS entry for baud %d\n",
780 __func__, baud);
781 return ser_clk;
782 }
783
784 *clk_div = ser_clk / desired_clk;
785 return ser_clk;
786}
787
788static void qcom_geni_serial_set_termios(struct uart_port *uport,
789 struct ktermios *termios, struct ktermios *old)
790{
791 unsigned int baud;
792 unsigned int bits_per_char;
793 unsigned int tx_trans_cfg;
794 unsigned int tx_parity_cfg;
795 unsigned int rx_trans_cfg;
796 unsigned int rx_parity_cfg;
797 unsigned int stop_bit_len;
798 unsigned int clk_div;
799 unsigned long ser_clk_cfg;
800 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
801 unsigned long clk_rate;
802
803 qcom_geni_serial_stop_rx(uport);
804 /* baud rate */
805 baud = uart_get_baud_rate(uport, termios, old, 300, 4000000);
806 port->baud = baud;
807 clk_rate = get_clk_div_rate(baud, &clk_div);
808 if (!clk_rate)
809 goto out_restart_rx;
810
811 uport->uartclk = clk_rate;
812 clk_set_rate(port->se.clk, clk_rate);
813 ser_clk_cfg = SER_CLK_EN;
814 ser_clk_cfg |= clk_div << CLK_DIV_SHFT;
815
816 /* parity */
817 tx_trans_cfg = readl_relaxed(uport->membase + SE_UART_TX_TRANS_CFG);
818 tx_parity_cfg = readl_relaxed(uport->membase + SE_UART_TX_PARITY_CFG);
819 rx_trans_cfg = readl_relaxed(uport->membase + SE_UART_RX_TRANS_CFG);
820 rx_parity_cfg = readl_relaxed(uport->membase + SE_UART_RX_PARITY_CFG);
821 if (termios->c_cflag & PARENB) {
822 tx_trans_cfg |= UART_TX_PAR_EN;
823 rx_trans_cfg |= UART_RX_PAR_EN;
824 tx_parity_cfg |= PAR_CALC_EN;
825 rx_parity_cfg |= PAR_CALC_EN;
826 if (termios->c_cflag & PARODD) {
827 tx_parity_cfg |= PAR_ODD;
828 rx_parity_cfg |= PAR_ODD;
829 } else if (termios->c_cflag & CMSPAR) {
830 tx_parity_cfg |= PAR_SPACE;
831 rx_parity_cfg |= PAR_SPACE;
832 } else {
833 tx_parity_cfg |= PAR_EVEN;
834 rx_parity_cfg |= PAR_EVEN;
835 }
836 } else {
837 tx_trans_cfg &= ~UART_TX_PAR_EN;
838 rx_trans_cfg &= ~UART_RX_PAR_EN;
839 tx_parity_cfg &= ~PAR_CALC_EN;
840 rx_parity_cfg &= ~PAR_CALC_EN;
841 }
842
843 /* bits per char */
844 switch (termios->c_cflag & CSIZE) {
845 case CS5:
846 bits_per_char = 5;
847 break;
848 case CS6:
849 bits_per_char = 6;
850 break;
851 case CS7:
852 bits_per_char = 7;
853 break;
854 case CS8:
855 default:
856 bits_per_char = 8;
857 break;
858 }
859
860 /* stop bits */
861 if (termios->c_cflag & CSTOPB)
862 stop_bit_len = TX_STOP_BIT_LEN_2;
863 else
864 stop_bit_len = TX_STOP_BIT_LEN_1;
865
866 /* flow control, clear the CTS_MASK bit if using flow control. */
867 if (termios->c_cflag & CRTSCTS)
868 tx_trans_cfg &= ~UART_CTS_MASK;
869 else
870 tx_trans_cfg |= UART_CTS_MASK;
871
872 if (baud)
873 uart_update_timeout(uport, termios->c_cflag, baud);
874
875 writel_relaxed(tx_trans_cfg, uport->membase + SE_UART_TX_TRANS_CFG);
876 writel_relaxed(tx_parity_cfg, uport->membase + SE_UART_TX_PARITY_CFG);
877 writel_relaxed(rx_trans_cfg, uport->membase + SE_UART_RX_TRANS_CFG);
878 writel_relaxed(rx_parity_cfg, uport->membase + SE_UART_RX_PARITY_CFG);
879 writel_relaxed(bits_per_char, uport->membase + SE_UART_TX_WORD_LEN);
880 writel_relaxed(bits_per_char, uport->membase + SE_UART_RX_WORD_LEN);
881 writel_relaxed(stop_bit_len, uport->membase + SE_UART_TX_STOP_BIT_LEN);
882 writel_relaxed(ser_clk_cfg, uport->membase + GENI_SER_M_CLK_CFG);
883 writel_relaxed(ser_clk_cfg, uport->membase + GENI_SER_S_CLK_CFG);
884out_restart_rx:
885 qcom_geni_serial_start_rx(uport);
886}
887
888static unsigned int qcom_geni_serial_tx_empty(struct uart_port *uport)
889{
890 return !readl_relaxed(uport->membase + SE_GENI_TX_FIFO_STATUS);
891}
892
893#ifdef CONFIG_SERIAL_QCOM_GENI_CONSOLE
894static int __init qcom_geni_console_setup(struct console *co, char *options)
895{
896 struct uart_port *uport;
897 struct qcom_geni_serial_port *port;
898 int baud;
899 int bits = 8;
900 int parity = 'n';
901 int flow = 'n';
902
903 if (co->index >= GENI_UART_CONS_PORTS || co->index < 0)
904 return -ENXIO;
905
906 port = get_port_from_line(co->index);
907 if (IS_ERR(port)) {
6a10635e 908 pr_err("Invalid line %d\n", co->index);
c4f52879
KR		 909 return PTR_ERR(port);
910 }
911
912 uport = &port->uport;
913
914 if (unlikely(!uport->membase))
915 return -ENXIO;
916
917 if (geni_se_resources_on(&port->se)) {
918 dev_err(port->se.dev, "Error turning on resources\n");
919 return -ENXIO;
920 }
921
922 if (unlikely(geni_se_read_proto(&port->se) != GENI_SE_UART)) {
923 geni_se_resources_off(&port->se);
924 return -ENXIO;
925 }
926
927 if (!port->setup) {
928 port->tx_bytes_pw = 1;
929 port->rx_bytes_pw = RX_BYTES_PW;
930 qcom_geni_serial_stop_rx(uport);
931 qcom_geni_serial_port_setup(uport);
932 }
933
934 if (options)
935 uart_parse_options(options, &baud, &parity, &bits, &flow);
936
937 return uart_set_options(uport, co, baud, parity, bits, flow);
938}
939
940static int __init console_register(struct uart_driver *drv)
941{
942 return uart_register_driver(drv);
943}
944
945static void console_unregister(struct uart_driver *drv)
946{
947 uart_unregister_driver(drv);
948}
949
950static struct console cons_ops = {
951 .name = "ttyMSM",
952 .write = qcom_geni_serial_console_write,
953 .device = uart_console_device,
954 .setup = qcom_geni_console_setup,
955 .flags = CON_PRINTBUFFER,
956 .index = -1,
957 .data = &qcom_geni_console_driver,
958};
959
960static struct uart_driver qcom_geni_console_driver = {
961 .owner = THIS_MODULE,
962 .driver_name = "qcom_geni_console",
963 .dev_name = "ttyMSM",
964 .nr = GENI_UART_CONS_PORTS,
965 .cons = &cons_ops,
966};
967#else
968static int console_register(struct uart_driver *drv)
969{
970 return 0;
971}
972
973static void console_unregister(struct uart_driver *drv)
974{
975}
976#endif /* CONFIG_SERIAL_QCOM_GENI_CONSOLE */
977
978static void qcom_geni_serial_cons_pm(struct uart_port *uport,
979 unsigned int new_state, unsigned int old_state)
980{
981 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
982
983 if (unlikely(!uart_console(uport)))
984 return;
985
986 if (new_state == UART_PM_STATE_ON && old_state == UART_PM_STATE_OFF)
987 geni_se_resources_on(&port->se);
988 else if (new_state == UART_PM_STATE_OFF &&
989 old_state == UART_PM_STATE_ON)
990 geni_se_resources_off(&port->se);
991}
992
993static const struct uart_ops qcom_geni_console_pops = {
994 .tx_empty = qcom_geni_serial_tx_empty,
995 .stop_tx = qcom_geni_serial_stop_tx,
996 .start_tx = qcom_geni_serial_start_tx,
997 .stop_rx = qcom_geni_serial_stop_rx,
998 .set_termios = qcom_geni_serial_set_termios,
999 .startup = qcom_geni_serial_startup,
1000 .request_port = qcom_geni_serial_request_port,
1001 .config_port = qcom_geni_serial_config_port,
1002 .shutdown = qcom_geni_serial_shutdown,
1003 .type = qcom_geni_serial_get_type,
1004 .set_mctrl = qcom_geni_cons_set_mctrl,
1005 .get_mctrl = qcom_geni_cons_get_mctrl,
1006#ifdef CONFIG_CONSOLE_POLL
1007 .poll_get_char = qcom_geni_serial_get_char,
1008 .poll_put_char = qcom_geni_serial_poll_put_char,
1009#endif
1010 .pm = qcom_geni_serial_cons_pm,
1011};
1012
1013static int qcom_geni_serial_probe(struct platform_device *pdev)
1014{
1015 int ret = 0;
1016 int line = -1;
1017 struct qcom_geni_serial_port *port;
1018 struct uart_port *uport;
1019 struct resource *res;
066cd1c4 1020 int irq;
c4f52879
KR		 1021
1022 if (pdev->dev.of_node)
1023 line = of_alias_get_id(pdev->dev.of_node, "serial");
c4f52879
KR		 1024
1025 if (line < 0 || line >= GENI_UART_CONS_PORTS)
1026 return -ENXIO;
1027 port = get_port_from_line(line);
1028 if (IS_ERR(port)) {
6a10635e
KR		 1029 dev_err(&pdev->dev, "Invalid line %d\n", line);
1030 return PTR_ERR(port);
c4f52879
KR		 1031 }
1032
1033 uport = &port->uport;
1034 /* Don't allow 2 drivers to access the same port */
1035 if (uport->private_data)
1036 return -ENODEV;
1037
1038 uport->dev = &pdev->dev;
1039 port->se.dev = &pdev->dev;
1040 port->se.wrapper = dev_get_drvdata(pdev->dev.parent);
1041 port->se.clk = devm_clk_get(&pdev->dev, "se");
1042 if (IS_ERR(port->se.clk)) {
1043 ret = PTR_ERR(port->se.clk);
1044 dev_err(&pdev->dev, "Err getting SE Core clk %d\n", ret);
1045 return ret;
1046 }
1047
1048 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
7693b331
WY		 1049 if (!res)
1050 return -EINVAL;
c4f52879
KR		 1051 uport->mapbase = res->start;
1052
1053 port->tx_fifo_depth = DEF_FIFO_DEPTH_WORDS;
1054 port->rx_fifo_depth = DEF_FIFO_DEPTH_WORDS;
1055 port->tx_fifo_width = DEF_FIFO_WIDTH_BITS;
1056
066cd1c4
KR		 1057 irq = platform_get_irq(pdev, 0);
1058 if (irq < 0) {
1059 dev_err(&pdev->dev, "Failed to get IRQ %d\n", irq);
1060 return irq;
c4f52879 1061 }
066cd1c4 1062 uport->irq = irq;
c4f52879
KR		 1063
1064 uport->private_data = &qcom_geni_console_driver;
1065 platform_set_drvdata(pdev, port);
1066 port->handle_rx = handle_rx_console;
c4f52879
KR		 1067 return uart_add_one_port(&qcom_geni_console_driver, uport);
1068}
1069
1070static int qcom_geni_serial_remove(struct platform_device *pdev)
1071{
1072 struct qcom_geni_serial_port *port = platform_get_drvdata(pdev);
1073 struct uart_driver *drv = port->uport.private_data;
1074
1075 uart_remove_one_port(drv, &port->uport);
1076 return 0;
1077}
1078
1079static int __maybe_unused qcom_geni_serial_sys_suspend_noirq(struct device *dev)
1080{
a406c4b8 1081 struct qcom_geni_serial_port *port = dev_get_drvdata(dev);
c4f52879
KR		 1082 struct uart_port *uport = &port->uport;
1083
1084 uart_suspend_port(uport->private_data, uport);
1085 return 0;
1086}
1087
1088static int __maybe_unused qcom_geni_serial_sys_resume_noirq(struct device *dev)
1089{
a406c4b8 1090 struct qcom_geni_serial_port *port = dev_get_drvdata(dev);
c4f52879
KR		 1091 struct uart_port *uport = &port->uport;
1092
1093 if (console_suspend_enabled && uport->suspended) {
1094 uart_resume_port(uport->private_data, uport);
f0262568
KR		 1095 /*
1096 * uart_suspend_port() invokes port shutdown which in turn
1097 * frees the irq. uart_resume_port invokes port startup which
1098 * performs request_irq. The request_irq auto-enables the IRQ.
1099 * In addition, resume_noirq implicitly enables the IRQ and
1100 * leads to an unbalanced IRQ enable warning. Disable the IRQ
1101 * before returning so that the warning is suppressed.
1102 */
c4f52879
KR		 1103 disable_irq(uport->irq);
1104 }
1105 return 0;
1106}
1107
1108static const struct dev_pm_ops qcom_geni_serial_pm_ops = {
1109 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(qcom_geni_serial_sys_suspend_noirq,
1110 qcom_geni_serial_sys_resume_noirq)
1111};
1112
1113static const struct of_device_id qcom_geni_serial_match_table[] = {
1114 { .compatible = "qcom,geni-debug-uart", },
1115 {}
1116};
1117MODULE_DEVICE_TABLE(of, qcom_geni_serial_match_table);
1118
1119static struct platform_driver qcom_geni_serial_platform_driver = {
1120 .remove = qcom_geni_serial_remove,
1121 .probe = qcom_geni_serial_probe,
1122 .driver = {
1123 .name = "qcom_geni_serial",
1124 .of_match_table = qcom_geni_serial_match_table,
1125 .pm = &qcom_geni_serial_pm_ops,
1126 },
1127};
1128
1129static int __init qcom_geni_serial_init(void)
1130{
1131 int ret;
1132
1133 qcom_geni_console_port.uport.iotype = UPIO_MEM;
1134 qcom_geni_console_port.uport.ops = &qcom_geni_console_pops;
1135 qcom_geni_console_port.uport.flags = UPF_BOOT_AUTOCONF;
1136 qcom_geni_console_port.uport.line = 0;
1137
1138 ret = console_register(&qcom_geni_console_driver);
1139 if (ret)
1140 return ret;
1141
1142 ret = platform_driver_register(&qcom_geni_serial_platform_driver);
1143 if (ret)
1144 console_unregister(&qcom_geni_console_driver);
1145 return ret;
1146}
1147module_init(qcom_geni_serial_init);
1148
1149static void __exit qcom_geni_serial_exit(void)
1150{
1151 platform_driver_unregister(&qcom_geni_serial_platform_driver);
1152 console_unregister(&qcom_geni_console_driver);
1153}
1154module_exit(qcom_geni_serial_exit);
1155
1156MODULE_DESCRIPTION("Serial driver for GENI based QUP cores");
1157MODULE_LICENSE("GPL v2");
Linux 6.x block layer and io_uring tree(s)