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c4f52879 KR |
1 | // SPDX-License-Identifier: GPL-2.0 |
2 | // Copyright (c) 2017-2018, The Linux foundation. All rights reserved. | |
3 | ||
60457d5e SPR |
4 | /* Disable MMIO tracing to prevent excessive logging of unwanted MMIO traces */ |
5 | #define __DISABLE_TRACE_MMIO__ | |
c4f52879 KR |
6 | |
7 | #include <linux/clk.h> | |
8 | #include <linux/console.h> | |
9 | #include <linux/io.h> | |
10 | #include <linux/iopoll.h> | |
3e4aaea7 | 11 | #include <linux/irq.h> |
c4f52879 KR |
12 | #include <linux/module.h> |
13 | #include <linux/of.h> | |
a5819b54 | 14 | #include <linux/pm_opp.h> |
c4f52879 | 15 | #include <linux/platform_device.h> |
f3974413 | 16 | #include <linux/pm_runtime.h> |
8b7103f3 | 17 | #include <linux/pm_wakeirq.h> |
491581f4 | 18 | #include <linux/soc/qcom/geni-se.h> |
c4f52879 KR |
19 | #include <linux/serial.h> |
20 | #include <linux/serial_core.h> | |
21 | #include <linux/slab.h> | |
22 | #include <linux/tty.h> | |
23 | #include <linux/tty_flip.h> | |
408e532e | 24 | #include <dt-bindings/interconnect/qcom,icc.h> |
c4f52879 KR |
25 | |
26 | /* UART specific GENI registers */ | |
8a8a66a1 | 27 | #define SE_UART_LOOPBACK_CFG 0x22c |
9fa3c4b1 | 28 | #define SE_UART_IO_MACRO_CTRL 0x240 |
c4f52879 KR |
29 | #define SE_UART_TX_TRANS_CFG 0x25c |
30 | #define SE_UART_TX_WORD_LEN 0x268 | |
31 | #define SE_UART_TX_STOP_BIT_LEN 0x26c | |
32 | #define SE_UART_TX_TRANS_LEN 0x270 | |
33 | #define SE_UART_RX_TRANS_CFG 0x280 | |
34 | #define SE_UART_RX_WORD_LEN 0x28c | |
35 | #define SE_UART_RX_STALE_CNT 0x294 | |
36 | #define SE_UART_TX_PARITY_CFG 0x2a4 | |
37 | #define SE_UART_RX_PARITY_CFG 0x2a8 | |
8a8a66a1 | 38 | #define SE_UART_MANUAL_RFR 0x2ac |
c4f52879 KR |
39 | |
40 | /* SE_UART_TRANS_CFG */ | |
6cde11db BG |
41 | #define UART_TX_PAR_EN BIT(0) |
42 | #define UART_CTS_MASK BIT(1) | |
c4f52879 | 43 | |
c4f52879 | 44 | /* SE_UART_TX_STOP_BIT_LEN */ |
6cde11db BG |
45 | #define TX_STOP_BIT_LEN_1 0 |
46 | #define TX_STOP_BIT_LEN_2 2 | |
c4f52879 | 47 | |
c4f52879 | 48 | /* SE_UART_RX_TRANS_CFG */ |
6cde11db | 49 | #define UART_RX_PAR_EN BIT(3) |
c4f52879 KR |
50 | |
51 | /* SE_UART_RX_WORD_LEN */ | |
6cde11db | 52 | #define RX_WORD_LEN_MASK GENMASK(9, 0) |
c4f52879 KR |
53 | |
54 | /* SE_UART_RX_STALE_CNT */ | |
6cde11db | 55 | #define RX_STALE_CNT GENMASK(23, 0) |
c4f52879 KR |
56 | |
57 | /* SE_UART_TX_PARITY_CFG/RX_PARITY_CFG */ | |
6cde11db BG |
58 | #define PAR_CALC_EN BIT(0) |
59 | #define PAR_EVEN 0x00 | |
60 | #define PAR_ODD 0x01 | |
61 | #define PAR_SPACE 0x10 | |
c4f52879 | 62 | |
8a8a66a1 | 63 | /* SE_UART_MANUAL_RFR register fields */ |
6cde11db BG |
64 | #define UART_MANUAL_RFR_EN BIT(31) |
65 | #define UART_RFR_NOT_READY BIT(1) | |
66 | #define UART_RFR_READY BIT(0) | |
8a8a66a1 | 67 | |
c4f52879 | 68 | /* UART M_CMD OP codes */ |
6cde11db | 69 | #define UART_START_TX 0x1 |
c4f52879 | 70 | /* UART S_CMD OP codes */ |
6cde11db | 71 | #define UART_START_READ 0x1 |
2aaa43c7 BG |
72 | #define UART_PARAM 0x1 |
73 | #define UART_PARAM_RFR_OPEN BIT(7) | |
6cde11db BG |
74 | |
75 | #define UART_OVERSAMPLING 32 | |
76 | #define STALE_TIMEOUT 16 | |
77 | #define DEFAULT_BITS_PER_CHAR 10 | |
78 | #define GENI_UART_CONS_PORTS 1 | |
79 | #define GENI_UART_PORTS 3 | |
80 | #define DEF_FIFO_DEPTH_WORDS 16 | |
81 | #define DEF_TX_WM 2 | |
82 | #define DEF_FIFO_WIDTH_BITS 32 | |
83 | #define UART_RX_WM 2 | |
69bd1a4f AA |
84 | |
85 | /* SE_UART_LOOPBACK_CFG */ | |
6cde11db BG |
86 | #define RX_TX_SORTED BIT(0) |
87 | #define CTS_RTS_SORTED BIT(1) | |
88 | #define RX_TX_CTS_RTS_SORTED (RX_TX_SORTED | CTS_RTS_SORTED) | |
c4f52879 | 89 | |
9fa3c4b1 | 90 | /* UART pin swap value */ |
6cde11db | 91 | #define DEFAULT_IO_MACRO_IO0_IO1_MASK GENMASK(3, 0) |
9fa3c4b1 | 92 | #define IO_MACRO_IO0_SEL 0x3 |
6cde11db | 93 | #define DEFAULT_IO_MACRO_IO2_IO3_MASK GENMASK(15, 4) |
9fa3c4b1 RRY |
94 | #define IO_MACRO_IO2_IO3_SWAP 0x4640 |
95 | ||
650c8bd3 | 96 | /* We always configure 4 bytes per FIFO word */ |
bd795584 | 97 | #define BYTES_PER_FIFO_WORD 4U |
650c8bd3 | 98 | |
2aaa43c7 BG |
99 | #define DMA_RX_BUF_SIZE 2048 |
100 | ||
40ec6d41 BG |
101 | struct qcom_geni_device_data { |
102 | bool console; | |
2aaa43c7 | 103 | enum geni_se_xfer_mode mode; |
40ec6d41 BG |
104 | }; |
105 | ||
e42d6c3e DA |
106 | struct qcom_geni_private_data { |
107 | /* NOTE: earlycon port will have NULL here */ | |
108 | struct uart_driver *drv; | |
109 | ||
110 | u32 poll_cached_bytes; | |
111 | unsigned int poll_cached_bytes_cnt; | |
650c8bd3 DA |
112 | |
113 | u32 write_cached_bytes; | |
114 | unsigned int write_cached_bytes_cnt; | |
e42d6c3e | 115 | }; |
c4f52879 KR |
116 | |
117 | struct qcom_geni_serial_port { | |
118 | struct uart_port uport; | |
119 | struct geni_se se; | |
f3974413 | 120 | const char *name; |
c4f52879 KR |
121 | u32 tx_fifo_depth; |
122 | u32 tx_fifo_width; | |
123 | u32 rx_fifo_depth; | |
2aaa43c7 BG |
124 | dma_addr_t tx_dma_addr; |
125 | dma_addr_t rx_dma_addr; | |
c4f52879 | 126 | bool setup; |
c4f52879 | 127 | unsigned int baud; |
8ece7b75 | 128 | unsigned long clk_rate; |
2aaa43c7 | 129 | void *rx_buf; |
8a8a66a1 | 130 | u32 loopback; |
c4f52879 | 131 | bool brk; |
a1fee899 RC |
132 | |
133 | unsigned int tx_remaining; | |
8b7103f3 | 134 | int wakeup_irq; |
9fa3c4b1 RRY |
135 | bool rx_tx_swap; |
136 | bool cts_rts_swap; | |
e42d6c3e DA |
137 | |
138 | struct qcom_geni_private_data private_data; | |
40ec6d41 | 139 | const struct qcom_geni_device_data *dev_data; |
c4f52879 KR |
140 | }; |
141 | ||
f7371750 | 142 | static const struct uart_ops qcom_geni_console_pops; |
8a8a66a1 | 143 | static const struct uart_ops qcom_geni_uart_pops; |
c4f52879 | 144 | static struct uart_driver qcom_geni_console_driver; |
8a8a66a1 | 145 | static struct uart_driver qcom_geni_uart_driver; |
c4f52879 | 146 | |
00ce7c6e BG |
147 | static inline struct qcom_geni_serial_port *to_dev_port(struct uart_port *uport) |
148 | { | |
149 | return container_of(uport, struct qcom_geni_serial_port, uport); | |
150 | } | |
c4f52879 | 151 | |
8a8a66a1 GM |
152 | static struct qcom_geni_serial_port qcom_geni_uart_ports[GENI_UART_PORTS] = { |
153 | [0] = { | |
154 | .uport = { | |
3931b8fd BG |
155 | .iotype = UPIO_MEM, |
156 | .ops = &qcom_geni_uart_pops, | |
157 | .flags = UPF_BOOT_AUTOCONF, | |
158 | .line = 0, | |
8a8a66a1 GM |
159 | }, |
160 | }, | |
161 | [1] = { | |
162 | .uport = { | |
3931b8fd BG |
163 | .iotype = UPIO_MEM, |
164 | .ops = &qcom_geni_uart_pops, | |
165 | .flags = UPF_BOOT_AUTOCONF, | |
166 | .line = 1, | |
8a8a66a1 GM |
167 | }, |
168 | }, | |
169 | [2] = { | |
170 | .uport = { | |
3931b8fd BG |
171 | .iotype = UPIO_MEM, |
172 | .ops = &qcom_geni_uart_pops, | |
173 | .flags = UPF_BOOT_AUTOCONF, | |
174 | .line = 2, | |
8a8a66a1 GM |
175 | }, |
176 | }, | |
177 | }; | |
178 | ||
f7371750 KR |
179 | static struct qcom_geni_serial_port qcom_geni_console_port = { |
180 | .uport = { | |
181 | .iotype = UPIO_MEM, | |
182 | .ops = &qcom_geni_console_pops, | |
183 | .flags = UPF_BOOT_AUTOCONF, | |
184 | .line = 0, | |
185 | }, | |
186 | }; | |
c4f52879 KR |
187 | |
188 | static int qcom_geni_serial_request_port(struct uart_port *uport) | |
189 | { | |
190 | struct platform_device *pdev = to_platform_device(uport->dev); | |
00ce7c6e | 191 | struct qcom_geni_serial_port *port = to_dev_port(uport); |
c4f52879 | 192 | |
44e60d52 | 193 | uport->membase = devm_platform_ioremap_resource(pdev, 0); |
c4f52879 KR |
194 | if (IS_ERR(uport->membase)) |
195 | return PTR_ERR(uport->membase); | |
196 | port->se.base = uport->membase; | |
197 | return 0; | |
198 | } | |
199 | ||
200 | static void qcom_geni_serial_config_port(struct uart_port *uport, int cfg_flags) | |
201 | { | |
202 | if (cfg_flags & UART_CONFIG_TYPE) { | |
203 | uport->type = PORT_MSM; | |
204 | qcom_geni_serial_request_port(uport); | |
205 | } | |
206 | } | |
207 | ||
8a8a66a1 | 208 | static unsigned int qcom_geni_serial_get_mctrl(struct uart_port *uport) |
c4f52879 | 209 | { |
8a8a66a1 GM |
210 | unsigned int mctrl = TIOCM_DSR | TIOCM_CAR; |
211 | u32 geni_ios; | |
212 | ||
e8a6ca80 | 213 | if (uart_console(uport)) { |
8a8a66a1 GM |
214 | mctrl |= TIOCM_CTS; |
215 | } else { | |
9e06d55f | 216 | geni_ios = readl(uport->membase + SE_GENI_IOS); |
8a8a66a1 GM |
217 | if (!(geni_ios & IO2_DATA_IN)) |
218 | mctrl |= TIOCM_CTS; | |
219 | } | |
220 | ||
221 | return mctrl; | |
c4f52879 KR |
222 | } |
223 | ||
8a8a66a1 | 224 | static void qcom_geni_serial_set_mctrl(struct uart_port *uport, |
c4f52879 KR |
225 | unsigned int mctrl) |
226 | { | |
8a8a66a1 | 227 | u32 uart_manual_rfr = 0; |
00ce7c6e | 228 | struct qcom_geni_serial_port *port = to_dev_port(uport); |
8a8a66a1 | 229 | |
e8a6ca80 | 230 | if (uart_console(uport)) |
8a8a66a1 GM |
231 | return; |
232 | ||
69bd1a4f AA |
233 | if (mctrl & TIOCM_LOOP) |
234 | port->loopback = RX_TX_CTS_RTS_SORTED; | |
235 | ||
a4ced376 | 236 | if (!(mctrl & TIOCM_RTS) && !uport->suspended) |
8a8a66a1 | 237 | uart_manual_rfr = UART_MANUAL_RFR_EN | UART_RFR_NOT_READY; |
9e06d55f | 238 | writel(uart_manual_rfr, uport->membase + SE_UART_MANUAL_RFR); |
c4f52879 KR |
239 | } |
240 | ||
241 | static const char *qcom_geni_serial_get_type(struct uart_port *uport) | |
242 | { | |
243 | return "MSM"; | |
244 | } | |
245 | ||
8a8a66a1 | 246 | static struct qcom_geni_serial_port *get_port_from_line(int line, bool console) |
c4f52879 | 247 | { |
8a8a66a1 GM |
248 | struct qcom_geni_serial_port *port; |
249 | int nr_ports = console ? GENI_UART_CONS_PORTS : GENI_UART_PORTS; | |
250 | ||
251 | if (line < 0 || line >= nr_ports) | |
c4f52879 | 252 | return ERR_PTR(-ENXIO); |
8a8a66a1 GM |
253 | |
254 | port = console ? &qcom_geni_console_port : &qcom_geni_uart_ports[line]; | |
255 | return port; | |
c4f52879 KR |
256 | } |
257 | ||
2aaa43c7 BG |
258 | static bool qcom_geni_serial_main_active(struct uart_port *uport) |
259 | { | |
260 | return readl(uport->membase + SE_GENI_STATUS) & M_GENI_CMD_ACTIVE; | |
261 | } | |
262 | ||
263 | static bool qcom_geni_serial_secondary_active(struct uart_port *uport) | |
264 | { | |
265 | return readl(uport->membase + SE_GENI_STATUS) & S_GENI_CMD_ACTIVE; | |
266 | } | |
267 | ||
c4f52879 KR |
268 | static bool qcom_geni_serial_poll_bit(struct uart_port *uport, |
269 | int offset, int field, bool set) | |
270 | { | |
271 | u32 reg; | |
272 | struct qcom_geni_serial_port *port; | |
273 | unsigned int baud; | |
274 | unsigned int fifo_bits; | |
275 | unsigned long timeout_us = 20000; | |
e42d6c3e | 276 | struct qcom_geni_private_data *private_data = uport->private_data; |
c4f52879 | 277 | |
e42d6c3e | 278 | if (private_data->drv) { |
00ce7c6e | 279 | port = to_dev_port(uport); |
c4f52879 KR |
280 | baud = port->baud; |
281 | if (!baud) | |
282 | baud = 115200; | |
283 | fifo_bits = port->tx_fifo_depth * port->tx_fifo_width; | |
284 | /* | |
285 | * Total polling iterations based on FIFO worth of bytes to be | |
286 | * sent at current baud. Add a little fluff to the wait. | |
287 | */ | |
288 | timeout_us = ((fifo_bits * USEC_PER_SEC) / baud) + 500; | |
289 | } | |
290 | ||
43f1831b KR |
291 | /* |
292 | * Use custom implementation instead of readl_poll_atomic since ktimer | |
293 | * is not ready at the time of early console. | |
294 | */ | |
295 | timeout_us = DIV_ROUND_UP(timeout_us, 10) * 10; | |
296 | while (timeout_us) { | |
9e06d55f | 297 | reg = readl(uport->membase + offset); |
43f1831b KR |
298 | if ((bool)(reg & field) == set) |
299 | return true; | |
300 | udelay(10); | |
301 | timeout_us -= 10; | |
302 | } | |
303 | return false; | |
c4f52879 KR |
304 | } |
305 | ||
306 | static void qcom_geni_serial_setup_tx(struct uart_port *uport, u32 xmit_size) | |
307 | { | |
308 | u32 m_cmd; | |
309 | ||
9e06d55f | 310 | writel(xmit_size, uport->membase + SE_UART_TX_TRANS_LEN); |
c4f52879 KR |
311 | m_cmd = UART_START_TX << M_OPCODE_SHFT; |
312 | writel(m_cmd, uport->membase + SE_GENI_M_CMD0); | |
313 | } | |
314 | ||
315 | static void qcom_geni_serial_poll_tx_done(struct uart_port *uport) | |
316 | { | |
317 | int done; | |
318 | u32 irq_clear = M_CMD_DONE_EN; | |
319 | ||
320 | done = qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, | |
321 | M_CMD_DONE_EN, true); | |
322 | if (!done) { | |
9e06d55f | 323 | writel(M_GENI_CMD_ABORT, uport->membase + |
c4f52879 KR |
324 | SE_GENI_M_CMD_CTRL_REG); |
325 | irq_clear |= M_CMD_ABORT_EN; | |
326 | qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, | |
327 | M_CMD_ABORT_EN, true); | |
328 | } | |
9e06d55f | 329 | writel(irq_clear, uport->membase + SE_GENI_M_IRQ_CLEAR); |
c4f52879 KR |
330 | } |
331 | ||
332 | static void qcom_geni_serial_abort_rx(struct uart_port *uport) | |
333 | { | |
334 | u32 irq_clear = S_CMD_DONE_EN | S_CMD_ABORT_EN; | |
335 | ||
336 | writel(S_GENI_CMD_ABORT, uport->membase + SE_GENI_S_CMD_CTRL_REG); | |
337 | qcom_geni_serial_poll_bit(uport, SE_GENI_S_CMD_CTRL_REG, | |
338 | S_GENI_CMD_ABORT, false); | |
9e06d55f RC |
339 | writel(irq_clear, uport->membase + SE_GENI_S_IRQ_CLEAR); |
340 | writel(FORCE_DEFAULT, uport->membase + GENI_FORCE_DEFAULT_REG); | |
c4f52879 KR |
341 | } |
342 | ||
343 | #ifdef CONFIG_CONSOLE_POLL | |
344 | static int qcom_geni_serial_get_char(struct uart_port *uport) | |
345 | { | |
e42d6c3e | 346 | struct qcom_geni_private_data *private_data = uport->private_data; |
c4f52879 | 347 | u32 status; |
e42d6c3e DA |
348 | u32 word_cnt; |
349 | int ret; | |
350 | ||
351 | if (!private_data->poll_cached_bytes_cnt) { | |
352 | status = readl(uport->membase + SE_GENI_M_IRQ_STATUS); | |
353 | writel(status, uport->membase + SE_GENI_M_IRQ_CLEAR); | |
c4f52879 | 354 | |
e42d6c3e DA |
355 | status = readl(uport->membase + SE_GENI_S_IRQ_STATUS); |
356 | writel(status, uport->membase + SE_GENI_S_IRQ_CLEAR); | |
c4f52879 | 357 | |
e42d6c3e DA |
358 | status = readl(uport->membase + SE_GENI_RX_FIFO_STATUS); |
359 | word_cnt = status & RX_FIFO_WC_MSK; | |
360 | if (!word_cnt) | |
361 | return NO_POLL_CHAR; | |
c4f52879 | 362 | |
e42d6c3e | 363 | if (word_cnt == 1 && (status & RX_LAST)) |
d681a6e4 DA |
364 | /* |
365 | * NOTE: If RX_LAST_BYTE_VALID is 0 it needs to be | |
366 | * treated as if it was BYTES_PER_FIFO_WORD. | |
367 | */ | |
e42d6c3e DA |
368 | private_data->poll_cached_bytes_cnt = |
369 | (status & RX_LAST_BYTE_VALID_MSK) >> | |
370 | RX_LAST_BYTE_VALID_SHFT; | |
d681a6e4 DA |
371 | |
372 | if (private_data->poll_cached_bytes_cnt == 0) | |
373 | private_data->poll_cached_bytes_cnt = BYTES_PER_FIFO_WORD; | |
c4f52879 | 374 | |
e42d6c3e DA |
375 | private_data->poll_cached_bytes = |
376 | readl(uport->membase + SE_GENI_RX_FIFOn); | |
377 | } | |
378 | ||
379 | private_data->poll_cached_bytes_cnt--; | |
380 | ret = private_data->poll_cached_bytes & 0xff; | |
381 | private_data->poll_cached_bytes >>= 8; | |
382 | ||
383 | return ret; | |
c4f52879 KR |
384 | } |
385 | ||
386 | static void qcom_geni_serial_poll_put_char(struct uart_port *uport, | |
387 | unsigned char c) | |
388 | { | |
a85fb9ce | 389 | writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG); |
c4f52879 KR |
390 | qcom_geni_serial_setup_tx(uport, 1); |
391 | WARN_ON(!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, | |
392 | M_TX_FIFO_WATERMARK_EN, true)); | |
9e06d55f RC |
393 | writel(c, uport->membase + SE_GENI_TX_FIFOn); |
394 | writel(M_TX_FIFO_WATERMARK_EN, uport->membase + SE_GENI_M_IRQ_CLEAR); | |
c4f52879 KR |
395 | qcom_geni_serial_poll_tx_done(uport); |
396 | } | |
397 | #endif | |
398 | ||
399 | #ifdef CONFIG_SERIAL_QCOM_GENI_CONSOLE | |
3f8bab17 | 400 | static void qcom_geni_serial_wr_char(struct uart_port *uport, unsigned char ch) |
c4f52879 | 401 | { |
650c8bd3 DA |
402 | struct qcom_geni_private_data *private_data = uport->private_data; |
403 | ||
404 | private_data->write_cached_bytes = | |
405 | (private_data->write_cached_bytes >> 8) | (ch << 24); | |
406 | private_data->write_cached_bytes_cnt++; | |
407 | ||
408 | if (private_data->write_cached_bytes_cnt == BYTES_PER_FIFO_WORD) { | |
409 | writel(private_data->write_cached_bytes, | |
410 | uport->membase + SE_GENI_TX_FIFOn); | |
411 | private_data->write_cached_bytes_cnt = 0; | |
412 | } | |
c4f52879 KR |
413 | } |
414 | ||
415 | static void | |
416 | __qcom_geni_serial_console_write(struct uart_port *uport, const char *s, | |
417 | unsigned int count) | |
418 | { | |
650c8bd3 DA |
419 | struct qcom_geni_private_data *private_data = uport->private_data; |
420 | ||
c4f52879 KR |
421 | int i; |
422 | u32 bytes_to_send = count; | |
423 | ||
424 | for (i = 0; i < count; i++) { | |
f0262568 KR |
425 | /* |
426 | * uart_console_write() adds a carriage return for each newline. | |
427 | * Account for additional bytes to be written. | |
428 | */ | |
c4f52879 KR |
429 | if (s[i] == '\n') |
430 | bytes_to_send++; | |
431 | } | |
432 | ||
9e06d55f | 433 | writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG); |
c4f52879 KR |
434 | qcom_geni_serial_setup_tx(uport, bytes_to_send); |
435 | for (i = 0; i < count; ) { | |
436 | size_t chars_to_write = 0; | |
437 | size_t avail = DEF_FIFO_DEPTH_WORDS - DEF_TX_WM; | |
438 | ||
439 | /* | |
440 | * If the WM bit never set, then the Tx state machine is not | |
441 | * in a valid state, so break, cancel/abort any existing | |
442 | * command. Unfortunately the current data being written is | |
443 | * lost. | |
444 | */ | |
445 | if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, | |
446 | M_TX_FIFO_WATERMARK_EN, true)) | |
447 | break; | |
6a10635e | 448 | chars_to_write = min_t(size_t, count - i, avail / 2); |
c4f52879 KR |
449 | uart_console_write(uport, s + i, chars_to_write, |
450 | qcom_geni_serial_wr_char); | |
9e06d55f | 451 | writel(M_TX_FIFO_WATERMARK_EN, uport->membase + |
c4f52879 KR |
452 | SE_GENI_M_IRQ_CLEAR); |
453 | i += chars_to_write; | |
454 | } | |
650c8bd3 DA |
455 | |
456 | if (private_data->write_cached_bytes_cnt) { | |
457 | private_data->write_cached_bytes >>= BITS_PER_BYTE * | |
458 | (BYTES_PER_FIFO_WORD - private_data->write_cached_bytes_cnt); | |
459 | writel(private_data->write_cached_bytes, | |
460 | uport->membase + SE_GENI_TX_FIFOn); | |
461 | private_data->write_cached_bytes_cnt = 0; | |
462 | } | |
463 | ||
c4f52879 KR |
464 | qcom_geni_serial_poll_tx_done(uport); |
465 | } | |
466 | ||
467 | static void qcom_geni_serial_console_write(struct console *co, const char *s, | |
468 | unsigned int count) | |
469 | { | |
470 | struct uart_port *uport; | |
471 | struct qcom_geni_serial_port *port; | |
472 | bool locked = true; | |
473 | unsigned long flags; | |
a1fee899 | 474 | u32 geni_status; |
663abb1a | 475 | u32 irq_en; |
c4f52879 KR |
476 | |
477 | WARN_ON(co->index < 0 || co->index >= GENI_UART_CONS_PORTS); | |
478 | ||
8a8a66a1 | 479 | port = get_port_from_line(co->index, true); |
c4f52879 KR |
480 | if (IS_ERR(port)) |
481 | return; | |
482 | ||
483 | uport = &port->uport; | |
484 | if (oops_in_progress) | |
485 | locked = spin_trylock_irqsave(&uport->lock, flags); | |
486 | else | |
487 | spin_lock_irqsave(&uport->lock, flags); | |
488 | ||
9e06d55f | 489 | geni_status = readl(uport->membase + SE_GENI_STATUS); |
a1fee899 | 490 | |
c4f52879 KR |
491 | /* Cancel the current write to log the fault */ |
492 | if (!locked) { | |
493 | geni_se_cancel_m_cmd(&port->se); | |
494 | if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, | |
495 | M_CMD_CANCEL_EN, true)) { | |
496 | geni_se_abort_m_cmd(&port->se); | |
497 | qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, | |
498 | M_CMD_ABORT_EN, true); | |
9e06d55f | 499 | writel(M_CMD_ABORT_EN, uport->membase + |
c4f52879 KR |
500 | SE_GENI_M_IRQ_CLEAR); |
501 | } | |
9e06d55f | 502 | writel(M_CMD_CANCEL_EN, uport->membase + SE_GENI_M_IRQ_CLEAR); |
a1fee899 RC |
503 | } else if ((geni_status & M_GENI_CMD_ACTIVE) && !port->tx_remaining) { |
504 | /* | |
505 | * It seems we can't interrupt existing transfers if all data | |
506 | * has been sent, in which case we need to look for done first. | |
507 | */ | |
508 | qcom_geni_serial_poll_tx_done(uport); | |
663abb1a | 509 | |
d2b574c0 | 510 | if (!uart_circ_empty(&uport->state->xmit)) { |
9e06d55f RC |
511 | irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); |
512 | writel(irq_en | M_TX_FIFO_WATERMARK_EN, | |
663abb1a RC |
513 | uport->membase + SE_GENI_M_IRQ_EN); |
514 | } | |
c4f52879 KR |
515 | } |
516 | ||
517 | __qcom_geni_serial_console_write(uport, s, count); | |
a1fee899 RC |
518 | |
519 | if (port->tx_remaining) | |
520 | qcom_geni_serial_setup_tx(uport, port->tx_remaining); | |
521 | ||
c4f52879 KR |
522 | if (locked) |
523 | spin_unlock_irqrestore(&uport->lock, flags); | |
524 | } | |
525 | ||
0626afe5 | 526 | static void handle_rx_console(struct uart_port *uport, u32 bytes, bool drop) |
c4f52879 KR |
527 | { |
528 | u32 i; | |
529 | unsigned char buf[sizeof(u32)]; | |
530 | struct tty_port *tport; | |
00ce7c6e | 531 | struct qcom_geni_serial_port *port = to_dev_port(uport); |
c4f52879 KR |
532 | |
533 | tport = &uport->state->port; | |
534 | for (i = 0; i < bytes; ) { | |
535 | int c; | |
650c8bd3 | 536 | int chunk = min_t(int, bytes - i, BYTES_PER_FIFO_WORD); |
c4f52879 KR |
537 | |
538 | ioread32_rep(uport->membase + SE_GENI_RX_FIFOn, buf, 1); | |
539 | i += chunk; | |
540 | if (drop) | |
541 | continue; | |
542 | ||
543 | for (c = 0; c < chunk; c++) { | |
544 | int sysrq; | |
545 | ||
546 | uport->icount.rx++; | |
547 | if (port->brk && buf[c] == 0) { | |
548 | port->brk = false; | |
549 | if (uart_handle_break(uport)) | |
550 | continue; | |
551 | } | |
552 | ||
336447b3 | 553 | sysrq = uart_prepare_sysrq_char(uport, buf[c]); |
babeca85 | 554 | |
c4f52879 KR |
555 | if (!sysrq) |
556 | tty_insert_flip_char(tport, buf[c], TTY_NORMAL); | |
557 | } | |
558 | } | |
559 | if (!drop) | |
560 | tty_flip_buffer_push(tport); | |
c4f52879 KR |
561 | } |
562 | #else | |
0626afe5 | 563 | static void handle_rx_console(struct uart_port *uport, u32 bytes, bool drop) |
c4f52879 | 564 | { |
0626afe5 | 565 | |
c4f52879 | 566 | } |
c4f52879 KR |
567 | #endif /* CONFIG_SERIAL_QCOM_GENI_CONSOLE */ |
568 | ||
0626afe5 | 569 | static void handle_rx_uart(struct uart_port *uport, u32 bytes, bool drop) |
8a8a66a1 | 570 | { |
00ce7c6e | 571 | struct qcom_geni_serial_port *port = to_dev_port(uport); |
2aaa43c7 | 572 | struct tty_port *tport = &uport->state->port; |
8a8a66a1 GM |
573 | int ret; |
574 | ||
2aaa43c7 | 575 | ret = tty_insert_flip_string(tport, port->rx_buf, bytes); |
8a8a66a1 GM |
576 | if (ret != bytes) { |
577 | dev_err(uport->dev, "%s:Unable to push data ret %d_bytes %d\n", | |
578 | __func__, ret, bytes); | |
579 | WARN_ON_ONCE(1); | |
580 | } | |
581 | uport->icount.rx += ret; | |
582 | tty_flip_buffer_push(tport); | |
8a8a66a1 GM |
583 | } |
584 | ||
d0fabb0d BG |
585 | static unsigned int qcom_geni_serial_tx_empty(struct uart_port *uport) |
586 | { | |
587 | return !readl(uport->membase + SE_GENI_TX_FIFO_STATUS); | |
588 | } | |
589 | ||
2aaa43c7 | 590 | static void qcom_geni_serial_stop_tx_dma(struct uart_port *uport) |
c4f52879 | 591 | { |
2aaa43c7 BG |
592 | struct qcom_geni_serial_port *port = to_dev_port(uport); |
593 | bool done; | |
594 | u32 m_irq_en; | |
595 | ||
596 | if (!qcom_geni_serial_main_active(uport)) | |
597 | return; | |
598 | ||
95fcfc08 | 599 | if (port->tx_dma_addr) { |
2aaa43c7 BG |
600 | geni_se_tx_dma_unprep(&port->se, port->tx_dma_addr, |
601 | port->tx_remaining); | |
602 | port->tx_dma_addr = 0; | |
603 | port->tx_remaining = 0; | |
604 | } | |
605 | ||
606 | m_irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); | |
607 | writel(m_irq_en, uport->membase + SE_GENI_M_IRQ_EN); | |
608 | geni_se_cancel_m_cmd(&port->se); | |
609 | ||
610 | done = qcom_geni_serial_poll_bit(uport, SE_GENI_S_IRQ_STATUS, | |
611 | S_CMD_CANCEL_EN, true); | |
612 | if (!done) { | |
613 | geni_se_abort_m_cmd(&port->se); | |
614 | done = qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, | |
615 | M_CMD_ABORT_EN, true); | |
616 | if (!done) | |
617 | dev_err_ratelimited(uport->dev, "M_CMD_ABORT_EN not set"); | |
618 | writel(M_CMD_ABORT_EN, uport->membase + SE_GENI_M_IRQ_CLEAR); | |
619 | } | |
620 | ||
621 | writel(M_CMD_CANCEL_EN, uport->membase + SE_GENI_M_IRQ_CLEAR); | |
622 | } | |
623 | ||
624 | static void qcom_geni_serial_start_tx_dma(struct uart_port *uport) | |
625 | { | |
626 | struct qcom_geni_serial_port *port = to_dev_port(uport); | |
627 | struct circ_buf *xmit = &uport->state->xmit; | |
628 | unsigned int xmit_size; | |
629 | int ret; | |
630 | ||
631 | if (port->tx_dma_addr) | |
632 | return; | |
633 | ||
97820780 JH |
634 | if (uart_circ_empty(xmit)) |
635 | return; | |
636 | ||
2aaa43c7 BG |
637 | xmit_size = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE); |
638 | ||
639 | qcom_geni_serial_setup_tx(uport, xmit_size); | |
640 | ||
641 | ret = geni_se_tx_dma_prep(&port->se, &xmit->buf[xmit->tail], | |
642 | xmit_size, &port->tx_dma_addr); | |
643 | if (ret) { | |
644 | dev_err(uport->dev, "unable to start TX SE DMA: %d\n", ret); | |
645 | qcom_geni_serial_stop_tx_dma(uport); | |
bdc05a8a | 646 | return; |
2aaa43c7 BG |
647 | } |
648 | ||
649 | port->tx_remaining = xmit_size; | |
650 | } | |
651 | ||
652 | static void qcom_geni_serial_start_tx_fifo(struct uart_port *uport) | |
653 | { | |
654 | u32 irq_en; | |
c4f52879 | 655 | |
2aaa43c7 BG |
656 | if (qcom_geni_serial_main_active(uport) || |
657 | !qcom_geni_serial_tx_empty(uport)) | |
bdc05a8a | 658 | return; |
c4f52879 | 659 | |
bdc05a8a RC |
660 | irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); |
661 | irq_en |= M_TX_FIFO_WATERMARK_EN | M_CMD_DONE_EN; | |
c4f52879 | 662 | |
bdc05a8a RC |
663 | writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG); |
664 | writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN); | |
c4f52879 KR |
665 | } |
666 | ||
2aaa43c7 | 667 | static void qcom_geni_serial_stop_tx_fifo(struct uart_port *uport) |
c4f52879 KR |
668 | { |
669 | u32 irq_en; | |
00ce7c6e | 670 | struct qcom_geni_serial_port *port = to_dev_port(uport); |
c4f52879 | 671 | |
9e06d55f | 672 | irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); |
bdc05a8a RC |
673 | irq_en &= ~(M_CMD_DONE_EN | M_TX_FIFO_WATERMARK_EN); |
674 | writel(0, uport->membase + SE_GENI_TX_WATERMARK_REG); | |
9e06d55f | 675 | writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN); |
c4f52879 | 676 | /* Possible stop tx is called multiple times. */ |
2aaa43c7 | 677 | if (!qcom_geni_serial_main_active(uport)) |
c4f52879 KR |
678 | return; |
679 | ||
c4f52879 KR |
680 | geni_se_cancel_m_cmd(&port->se); |
681 | if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, | |
682 | M_CMD_CANCEL_EN, true)) { | |
683 | geni_se_abort_m_cmd(&port->se); | |
684 | qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS, | |
685 | M_CMD_ABORT_EN, true); | |
9e06d55f | 686 | writel(M_CMD_ABORT_EN, uport->membase + SE_GENI_M_IRQ_CLEAR); |
c4f52879 | 687 | } |
9e06d55f | 688 | writel(M_CMD_CANCEL_EN, uport->membase + SE_GENI_M_IRQ_CLEAR); |
c4f52879 KR |
689 | } |
690 | ||
2aaa43c7 | 691 | static void qcom_geni_serial_handle_rx_fifo(struct uart_port *uport, bool drop) |
c4f52879 | 692 | { |
c4f52879 | 693 | u32 status; |
d0fabb0d BG |
694 | u32 word_cnt; |
695 | u32 last_word_byte_cnt; | |
696 | u32 last_word_partial; | |
697 | u32 total_bytes; | |
c4f52879 | 698 | |
d0fabb0d BG |
699 | status = readl(uport->membase + SE_GENI_RX_FIFO_STATUS); |
700 | word_cnt = status & RX_FIFO_WC_MSK; | |
701 | last_word_partial = status & RX_LAST; | |
702 | last_word_byte_cnt = (status & RX_LAST_BYTE_VALID_MSK) >> | |
703 | RX_LAST_BYTE_VALID_SHFT; | |
c4f52879 | 704 | |
d0fabb0d BG |
705 | if (!word_cnt) |
706 | return; | |
707 | total_bytes = BYTES_PER_FIFO_WORD * (word_cnt - 1); | |
708 | if (last_word_partial && last_word_byte_cnt) | |
709 | total_bytes += last_word_byte_cnt; | |
710 | else | |
711 | total_bytes += BYTES_PER_FIFO_WORD; | |
2aaa43c7 | 712 | handle_rx_console(uport, total_bytes, drop); |
c4f52879 KR |
713 | } |
714 | ||
2aaa43c7 | 715 | static void qcom_geni_serial_stop_rx_fifo(struct uart_port *uport) |
c4f52879 KR |
716 | { |
717 | u32 irq_en; | |
00ce7c6e | 718 | struct qcom_geni_serial_port *port = to_dev_port(uport); |
679aac5e | 719 | u32 s_irq_status; |
c4f52879 | 720 | |
bdc05a8a RC |
721 | irq_en = readl(uport->membase + SE_GENI_S_IRQ_EN); |
722 | irq_en &= ~(S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN); | |
723 | writel(irq_en, uport->membase + SE_GENI_S_IRQ_EN); | |
c4f52879 | 724 | |
bdc05a8a RC |
725 | irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); |
726 | irq_en &= ~(M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN); | |
727 | writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN); | |
c4f52879 | 728 | |
2aaa43c7 | 729 | if (!qcom_geni_serial_secondary_active(uport)) |
c4f52879 KR |
730 | return; |
731 | ||
c4f52879 | 732 | geni_se_cancel_s_cmd(&port->se); |
679aac5e | 733 | qcom_geni_serial_poll_bit(uport, SE_GENI_S_IRQ_STATUS, |
734 | S_CMD_CANCEL_EN, true); | |
735 | /* | |
736 | * If timeout occurs secondary engine remains active | |
737 | * and Abort sequence is executed. | |
738 | */ | |
739 | s_irq_status = readl(uport->membase + SE_GENI_S_IRQ_STATUS); | |
740 | /* Flush the Rx buffer */ | |
741 | if (s_irq_status & S_RX_FIFO_LAST_EN) | |
2aaa43c7 | 742 | qcom_geni_serial_handle_rx_fifo(uport, true); |
679aac5e | 743 | writel(s_irq_status, uport->membase + SE_GENI_S_IRQ_CLEAR); |
744 | ||
2aaa43c7 | 745 | if (qcom_geni_serial_secondary_active(uport)) |
c4f52879 KR |
746 | qcom_geni_serial_abort_rx(uport); |
747 | } | |
748 | ||
2aaa43c7 | 749 | static void qcom_geni_serial_start_rx_fifo(struct uart_port *uport) |
c4f52879 | 750 | { |
d0fabb0d | 751 | u32 irq_en; |
00ce7c6e | 752 | struct qcom_geni_serial_port *port = to_dev_port(uport); |
c4f52879 | 753 | |
2aaa43c7 BG |
754 | if (qcom_geni_serial_secondary_active(uport)) |
755 | qcom_geni_serial_stop_rx_fifo(uport); | |
c4f52879 | 756 | |
d0fabb0d BG |
757 | geni_se_setup_s_cmd(&port->se, UART_START_READ, 0); |
758 | ||
759 | irq_en = readl(uport->membase + SE_GENI_S_IRQ_EN); | |
760 | irq_en |= S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN; | |
761 | writel(irq_en, uport->membase + SE_GENI_S_IRQ_EN); | |
762 | ||
763 | irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); | |
764 | irq_en |= M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN; | |
765 | writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN); | |
c4f52879 KR |
766 | } |
767 | ||
2aaa43c7 BG |
768 | static void qcom_geni_serial_stop_rx_dma(struct uart_port *uport) |
769 | { | |
770 | struct qcom_geni_serial_port *port = to_dev_port(uport); | |
771 | ||
772 | if (!qcom_geni_serial_secondary_active(uport)) | |
773 | return; | |
774 | ||
775 | geni_se_cancel_s_cmd(&port->se); | |
776 | qcom_geni_serial_poll_bit(uport, SE_GENI_S_IRQ_STATUS, | |
777 | S_CMD_CANCEL_EN, true); | |
778 | ||
779 | if (qcom_geni_serial_secondary_active(uport)) | |
780 | qcom_geni_serial_abort_rx(uport); | |
781 | ||
782 | if (port->rx_dma_addr) { | |
783 | geni_se_rx_dma_unprep(&port->se, port->rx_dma_addr, | |
784 | DMA_RX_BUF_SIZE); | |
785 | port->rx_dma_addr = 0; | |
786 | } | |
787 | } | |
788 | ||
789 | static void qcom_geni_serial_start_rx_dma(struct uart_port *uport) | |
790 | { | |
791 | struct qcom_geni_serial_port *port = to_dev_port(uport); | |
792 | int ret; | |
793 | ||
794 | if (qcom_geni_serial_secondary_active(uport)) | |
795 | qcom_geni_serial_stop_rx_dma(uport); | |
796 | ||
797 | geni_se_setup_s_cmd(&port->se, UART_START_READ, UART_PARAM_RFR_OPEN); | |
798 | ||
799 | ret = geni_se_rx_dma_prep(&port->se, port->rx_buf, | |
800 | DMA_RX_BUF_SIZE, | |
801 | &port->rx_dma_addr); | |
802 | if (ret) { | |
803 | dev_err(uport->dev, "unable to start RX SE DMA: %d\n", ret); | |
804 | qcom_geni_serial_stop_rx_dma(uport); | |
805 | } | |
806 | } | |
807 | ||
808 | static void qcom_geni_serial_handle_rx_dma(struct uart_port *uport, bool drop) | |
809 | { | |
810 | struct qcom_geni_serial_port *port = to_dev_port(uport); | |
811 | u32 rx_in; | |
812 | int ret; | |
813 | ||
814 | if (!qcom_geni_serial_secondary_active(uport)) | |
815 | return; | |
816 | ||
817 | if (!port->rx_dma_addr) | |
818 | return; | |
819 | ||
820 | geni_se_rx_dma_unprep(&port->se, port->rx_dma_addr, DMA_RX_BUF_SIZE); | |
821 | port->rx_dma_addr = 0; | |
822 | ||
823 | rx_in = readl(uport->membase + SE_DMA_RX_LEN_IN); | |
824 | if (!rx_in) { | |
825 | dev_warn(uport->dev, "serial engine reports 0 RX bytes in!\n"); | |
826 | return; | |
827 | } | |
828 | ||
829 | if (!drop) | |
830 | handle_rx_uart(uport, rx_in, drop); | |
831 | ||
832 | ret = geni_se_rx_dma_prep(&port->se, port->rx_buf, | |
833 | DMA_RX_BUF_SIZE, | |
834 | &port->rx_dma_addr); | |
835 | if (ret) { | |
836 | dev_err(uport->dev, "unable to start RX SE DMA: %d\n", ret); | |
837 | qcom_geni_serial_stop_rx_dma(uport); | |
838 | } | |
839 | } | |
840 | ||
841 | static void qcom_geni_serial_start_rx(struct uart_port *uport) | |
842 | { | |
843 | uport->ops->start_rx(uport); | |
844 | } | |
845 | ||
846 | static void qcom_geni_serial_stop_rx(struct uart_port *uport) | |
847 | { | |
848 | uport->ops->stop_rx(uport); | |
849 | } | |
850 | ||
851 | static void qcom_geni_serial_stop_tx(struct uart_port *uport) | |
852 | { | |
853 | uport->ops->stop_tx(uport); | |
854 | } | |
855 | ||
bd795584 | 856 | static void qcom_geni_serial_send_chunk_fifo(struct uart_port *uport, |
5c7e105c | 857 | unsigned int remaining) |
d420fb49 BG |
858 | { |
859 | struct qcom_geni_serial_port *port = to_dev_port(uport); | |
860 | struct circ_buf *xmit = &uport->state->xmit; | |
5c7e105c | 861 | unsigned int tx_bytes; |
bd795584 | 862 | u8 buf[BYTES_PER_FIFO_WORD]; |
d420fb49 | 863 | |
bd795584 | 864 | while (remaining) { |
d420fb49 | 865 | memset(buf, 0, sizeof(buf)); |
bd795584 | 866 | tx_bytes = min(remaining, BYTES_PER_FIFO_WORD); |
d420fb49 | 867 | |
5c7e105c JSS |
868 | memcpy(buf, &xmit->buf[xmit->tail], tx_bytes); |
869 | uart_xmit_advance(uport, tx_bytes); | |
d420fb49 BG |
870 | |
871 | iowrite32_rep(uport->membase + SE_GENI_TX_FIFOn, buf, 1); | |
872 | ||
d420fb49 BG |
873 | remaining -= tx_bytes; |
874 | port->tx_remaining -= tx_bytes; | |
875 | } | |
d420fb49 BG |
876 | } |
877 | ||
2aaa43c7 BG |
878 | static void qcom_geni_serial_handle_tx_fifo(struct uart_port *uport, |
879 | bool done, bool active) | |
c4f52879 | 880 | { |
00ce7c6e | 881 | struct qcom_geni_serial_port *port = to_dev_port(uport); |
c4f52879 KR |
882 | struct circ_buf *xmit = &uport->state->xmit; |
883 | size_t avail; | |
a1fee899 | 884 | size_t pending; |
c4f52879 | 885 | u32 status; |
64a42807 | 886 | u32 irq_en; |
c4f52879 | 887 | unsigned int chunk; |
c4f52879 | 888 | |
9e06d55f | 889 | status = readl(uport->membase + SE_GENI_TX_FIFO_STATUS); |
a1fee899 RC |
890 | |
891 | /* Complete the current tx command before taking newly added data */ | |
892 | if (active) | |
893 | pending = port->tx_remaining; | |
894 | else | |
895 | pending = uart_circ_chars_pending(xmit); | |
896 | ||
897 | /* All data has been transmitted and acknowledged as received */ | |
898 | if (!pending && !status && done) { | |
2aaa43c7 | 899 | qcom_geni_serial_stop_tx_fifo(uport); |
c4f52879 KR |
900 | goto out_write_wakeup; |
901 | } | |
c4f52879 | 902 | |
a1fee899 | 903 | avail = port->tx_fifo_depth - (status & TX_FIFO_WC); |
650c8bd3 | 904 | avail *= BYTES_PER_FIFO_WORD; |
8a8a66a1 | 905 | |
3c66eb4b | 906 | chunk = min(avail, pending); |
c4f52879 KR |
907 | if (!chunk) |
908 | goto out_write_wakeup; | |
909 | ||
a1fee899 RC |
910 | if (!port->tx_remaining) { |
911 | qcom_geni_serial_setup_tx(uport, pending); | |
912 | port->tx_remaining = pending; | |
64a42807 | 913 | |
9e06d55f | 914 | irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); |
64a42807 | 915 | if (!(irq_en & M_TX_FIFO_WATERMARK_EN)) |
9e06d55f | 916 | writel(irq_en | M_TX_FIFO_WATERMARK_EN, |
64a42807 | 917 | uport->membase + SE_GENI_M_IRQ_EN); |
a1fee899 | 918 | } |
c4f52879 | 919 | |
bd795584 | 920 | qcom_geni_serial_send_chunk_fifo(uport, chunk); |
64a42807 RC |
921 | |
922 | /* | |
923 | * The tx fifo watermark is level triggered and latched. Though we had | |
924 | * cleared it in qcom_geni_serial_isr it will have already reasserted | |
925 | * so we must clear it again here after our writes. | |
926 | */ | |
9e06d55f | 927 | writel(M_TX_FIFO_WATERMARK_EN, |
64a42807 RC |
928 | uport->membase + SE_GENI_M_IRQ_CLEAR); |
929 | ||
c4f52879 | 930 | out_write_wakeup: |
64a42807 | 931 | if (!port->tx_remaining) { |
9e06d55f | 932 | irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); |
64a42807 | 933 | if (irq_en & M_TX_FIFO_WATERMARK_EN) |
9e06d55f | 934 | writel(irq_en & ~M_TX_FIFO_WATERMARK_EN, |
64a42807 RC |
935 | uport->membase + SE_GENI_M_IRQ_EN); |
936 | } | |
937 | ||
638a6f4e EG |
938 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) |
939 | uart_write_wakeup(uport); | |
c4f52879 KR |
940 | } |
941 | ||
2aaa43c7 BG |
942 | static void qcom_geni_serial_handle_tx_dma(struct uart_port *uport) |
943 | { | |
944 | struct qcom_geni_serial_port *port = to_dev_port(uport); | |
945 | struct circ_buf *xmit = &uport->state->xmit; | |
946 | ||
947 | uart_xmit_advance(uport, port->tx_remaining); | |
948 | geni_se_tx_dma_unprep(&port->se, port->tx_dma_addr, port->tx_remaining); | |
949 | port->tx_dma_addr = 0; | |
950 | port->tx_remaining = 0; | |
951 | ||
952 | if (!uart_circ_empty(xmit)) | |
953 | qcom_geni_serial_start_tx_dma(uport); | |
954 | ||
955 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
956 | uart_write_wakeup(uport); | |
957 | } | |
958 | ||
c4f52879 KR |
959 | static irqreturn_t qcom_geni_serial_isr(int isr, void *dev) |
960 | { | |
385298ab RC |
961 | u32 m_irq_en; |
962 | u32 m_irq_status; | |
963 | u32 s_irq_status; | |
964 | u32 geni_status; | |
2aaa43c7 BG |
965 | u32 dma; |
966 | u32 dma_tx_status; | |
967 | u32 dma_rx_status; | |
c4f52879 | 968 | struct uart_port *uport = dev; |
c4f52879 KR |
969 | bool drop_rx = false; |
970 | struct tty_port *tport = &uport->state->port; | |
00ce7c6e | 971 | struct qcom_geni_serial_port *port = to_dev_port(uport); |
c4f52879 KR |
972 | |
973 | if (uport->suspended) | |
ec91df8d | 974 | return IRQ_NONE; |
c4f52879 | 975 | |
75f4e830 JH |
976 | spin_lock(&uport->lock); |
977 | ||
9e06d55f RC |
978 | m_irq_status = readl(uport->membase + SE_GENI_M_IRQ_STATUS); |
979 | s_irq_status = readl(uport->membase + SE_GENI_S_IRQ_STATUS); | |
2aaa43c7 BG |
980 | dma_tx_status = readl(uport->membase + SE_DMA_TX_IRQ_STAT); |
981 | dma_rx_status = readl(uport->membase + SE_DMA_RX_IRQ_STAT); | |
9e06d55f | 982 | geni_status = readl(uport->membase + SE_GENI_STATUS); |
2aaa43c7 | 983 | dma = readl(uport->membase + SE_GENI_DMA_MODE_EN); |
9e06d55f RC |
984 | m_irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN); |
985 | writel(m_irq_status, uport->membase + SE_GENI_M_IRQ_CLEAR); | |
986 | writel(s_irq_status, uport->membase + SE_GENI_S_IRQ_CLEAR); | |
2aaa43c7 BG |
987 | writel(dma_tx_status, uport->membase + SE_DMA_TX_IRQ_CLR); |
988 | writel(dma_rx_status, uport->membase + SE_DMA_RX_IRQ_CLR); | |
c4f52879 KR |
989 | |
990 | if (WARN_ON(m_irq_status & M_ILLEGAL_CMD_EN)) | |
991 | goto out_unlock; | |
992 | ||
993 | if (s_irq_status & S_RX_FIFO_WR_ERR_EN) { | |
994 | uport->icount.overrun++; | |
995 | tty_insert_flip_char(tport, 0, TTY_OVERRUN); | |
996 | } | |
997 | ||
fe6a00e8 | 998 | if (s_irq_status & (S_GP_IRQ_0_EN | S_GP_IRQ_1_EN)) { |
c4f52879 KR |
999 | if (s_irq_status & S_GP_IRQ_0_EN) |
1000 | uport->icount.parity++; | |
1001 | drop_rx = true; | |
fe6a00e8 | 1002 | } else if (s_irq_status & (S_GP_IRQ_2_EN | S_GP_IRQ_3_EN)) { |
c4f52879 KR |
1003 | uport->icount.brk++; |
1004 | port->brk = true; | |
1005 | } | |
1006 | ||
2aaa43c7 BG |
1007 | if (dma) { |
1008 | if (dma_tx_status & TX_DMA_DONE) | |
1009 | qcom_geni_serial_handle_tx_dma(uport); | |
1010 | ||
1011 | if (dma_rx_status) { | |
1012 | if (dma_rx_status & RX_RESET_DONE) | |
1013 | goto out_unlock; | |
1014 | ||
1015 | if (dma_rx_status & RX_DMA_PARITY_ERR) { | |
1016 | uport->icount.parity++; | |
1017 | drop_rx = true; | |
1018 | } | |
1019 | ||
1020 | if (dma_rx_status & RX_DMA_BREAK) | |
1021 | uport->icount.brk++; | |
1022 | ||
1023 | if (dma_rx_status & (RX_DMA_DONE | RX_EOT)) | |
1024 | qcom_geni_serial_handle_rx_dma(uport, drop_rx); | |
1025 | } | |
1026 | } else { | |
1027 | if (m_irq_status & m_irq_en & | |
1028 | (M_TX_FIFO_WATERMARK_EN | M_CMD_DONE_EN)) | |
1029 | qcom_geni_serial_handle_tx_fifo(uport, | |
1030 | m_irq_status & M_CMD_DONE_EN, | |
1031 | geni_status & M_GENI_CMD_ACTIVE); | |
1032 | ||
1033 | if (s_irq_status & (S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN)) | |
1034 | qcom_geni_serial_handle_rx_fifo(uport, drop_rx); | |
1035 | } | |
c4f52879 KR |
1036 | |
1037 | out_unlock: | |
75f4e830 | 1038 | uart_unlock_and_check_sysrq(uport); |
336447b3 | 1039 | |
c4f52879 KR |
1040 | return IRQ_HANDLED; |
1041 | } | |
1042 | ||
b8caf69a | 1043 | static int setup_fifos(struct qcom_geni_serial_port *port) |
c4f52879 KR |
1044 | { |
1045 | struct uart_port *uport; | |
b8caf69a | 1046 | u32 old_rx_fifo_depth = port->rx_fifo_depth; |
c4f52879 | 1047 | |
c4f52879 KR |
1048 | uport = &port->uport; |
1049 | port->tx_fifo_depth = geni_se_get_tx_fifo_depth(&port->se); | |
1050 | port->tx_fifo_width = geni_se_get_tx_fifo_width(&port->se); | |
1051 | port->rx_fifo_depth = geni_se_get_rx_fifo_depth(&port->se); | |
1052 | uport->fifosize = | |
1053 | (port->tx_fifo_depth * port->tx_fifo_width) / BITS_PER_BYTE; | |
b8caf69a | 1054 | |
a3cf6b94 | 1055 | if (port->rx_buf && (old_rx_fifo_depth != port->rx_fifo_depth) && port->rx_fifo_depth) { |
9e6aa7c2 JC |
1056 | /* |
1057 | * Use krealloc rather than krealloc_array because rx_buf is | |
1058 | * accessed as 1 byte entries as well as 4 byte entries so it's | |
1059 | * not necessarily an array. | |
1060 | */ | |
a3cf6b94 IJ |
1061 | port->rx_buf = devm_krealloc(uport->dev, port->rx_buf, |
1062 | port->rx_fifo_depth * sizeof(u32), | |
1063 | GFP_KERNEL); | |
1064 | if (!port->rx_buf) | |
b8caf69a KK |
1065 | return -ENOMEM; |
1066 | } | |
1067 | ||
1068 | return 0; | |
c4f52879 KR |
1069 | } |
1070 | ||
c4f52879 KR |
1071 | |
1072 | static void qcom_geni_serial_shutdown(struct uart_port *uport) | |
1073 | { | |
3e4aaea7 | 1074 | disable_irq(uport->irq); |
9aff74cc JH |
1075 | |
1076 | if (uart_console(uport)) | |
1077 | return; | |
1078 | ||
d8aca2f9 BG |
1079 | qcom_geni_serial_stop_tx(uport); |
1080 | qcom_geni_serial_stop_rx(uport); | |
c4f52879 KR |
1081 | } |
1082 | ||
1083 | static int qcom_geni_serial_port_setup(struct uart_port *uport) | |
1084 | { | |
00ce7c6e | 1085 | struct qcom_geni_serial_port *port = to_dev_port(uport); |
385298ab | 1086 | u32 rxstale = DEFAULT_BITS_PER_CHAR * STALE_TIMEOUT; |
c362272b | 1087 | u32 proto; |
9fa3c4b1 | 1088 | u32 pin_swap; |
b8caf69a | 1089 | int ret; |
c362272b | 1090 | |
c362272b DA |
1091 | proto = geni_se_read_proto(&port->se); |
1092 | if (proto != GENI_SE_UART) { | |
1093 | dev_err(uport->dev, "Invalid FW loaded, proto: %d\n", proto); | |
1094 | return -ENXIO; | |
1095 | } | |
1096 | ||
1097 | qcom_geni_serial_stop_rx(uport); | |
1098 | ||
b8caf69a KK |
1099 | ret = setup_fifos(port); |
1100 | if (ret) | |
1101 | return ret; | |
c4f52879 | 1102 | |
9e06d55f | 1103 | writel(rxstale, uport->membase + SE_UART_RX_STALE_CNT); |
9fa3c4b1 RRY |
1104 | |
1105 | pin_swap = readl(uport->membase + SE_UART_IO_MACRO_CTRL); | |
1106 | if (port->rx_tx_swap) { | |
1107 | pin_swap &= ~DEFAULT_IO_MACRO_IO2_IO3_MASK; | |
1108 | pin_swap |= IO_MACRO_IO2_IO3_SWAP; | |
1109 | } | |
1110 | if (port->cts_rts_swap) { | |
1111 | pin_swap &= ~DEFAULT_IO_MACRO_IO0_IO1_MASK; | |
1112 | pin_swap |= IO_MACRO_IO0_SEL; | |
1113 | } | |
1114 | /* Configure this register if RX-TX, CTS-RTS pins are swapped */ | |
1115 | if (port->rx_tx_swap || port->cts_rts_swap) | |
1116 | writel(pin_swap, uport->membase + SE_UART_IO_MACRO_CTRL); | |
1117 | ||
c4f52879 KR |
1118 | /* |
1119 | * Make an unconditional cancel on the main sequencer to reset | |
1120 | * it else we could end up in data loss scenarios. | |
1121 | */ | |
8a8a66a1 GM |
1122 | if (uart_console(uport)) |
1123 | qcom_geni_serial_poll_tx_done(uport); | |
650c8bd3 DA |
1124 | geni_se_config_packing(&port->se, BITS_PER_BYTE, BYTES_PER_FIFO_WORD, |
1125 | false, true, true); | |
a85fb9ce | 1126 | geni_se_init(&port->se, UART_RX_WM, port->rx_fifo_depth - 2); |
2aaa43c7 | 1127 | geni_se_select_mode(&port->se, port->dev_data->mode); |
35781d83 | 1128 | qcom_geni_serial_start_rx(uport); |
c4f52879 | 1129 | port->setup = true; |
c362272b | 1130 | |
c4f52879 KR |
1131 | return 0; |
1132 | } | |
1133 | ||
1134 | static int qcom_geni_serial_startup(struct uart_port *uport) | |
1135 | { | |
1136 | int ret; | |
00ce7c6e | 1137 | struct qcom_geni_serial_port *port = to_dev_port(uport); |
c4f52879 | 1138 | |
c4f52879 KR |
1139 | if (!port->setup) { |
1140 | ret = qcom_geni_serial_port_setup(uport); | |
1141 | if (ret) | |
1142 | return ret; | |
1143 | } | |
3e4aaea7 | 1144 | enable_irq(uport->irq); |
c4f52879 | 1145 | |
3e4aaea7 | 1146 | return 0; |
c4f52879 KR |
1147 | } |
1148 | ||
c474c775 VKN |
1149 | static unsigned long find_clk_rate_in_tol(struct clk *clk, unsigned int desired_clk, |
1150 | unsigned int *clk_div, unsigned int percent_tol) | |
c4f52879 | 1151 | { |
c474c775 | 1152 | unsigned long freq; |
c2194bc9 | 1153 | unsigned long div, maxdiv; |
c474c775 VKN |
1154 | u64 mult; |
1155 | unsigned long offset, abs_tol, achieved; | |
c2194bc9 | 1156 | |
c474c775 | 1157 | abs_tol = div_u64((u64)desired_clk * percent_tol, 100); |
c2194bc9 | 1158 | maxdiv = CLK_DIV_MSK >> CLK_DIV_SHFT; |
c474c775 VKN |
1159 | div = 1; |
1160 | while (div <= maxdiv) { | |
1161 | mult = (u64)div * desired_clk; | |
1162 | if (mult != (unsigned long)mult) | |
c2194bc9 VKN |
1163 | break; |
1164 | ||
c474c775 VKN |
1165 | offset = div * abs_tol; |
1166 | freq = clk_round_rate(clk, mult - offset); | |
c2194bc9 | 1167 | |
c474c775 VKN |
1168 | /* Can only get lower if we're done */ |
1169 | if (freq < mult - offset) | |
c2194bc9 VKN |
1170 | break; |
1171 | ||
c474c775 VKN |
1172 | /* |
1173 | * Re-calculate div in case rounding skipped rates but we | |
1174 | * ended up at a good one, then check for a match. | |
1175 | */ | |
1176 | div = DIV_ROUND_CLOSEST(freq, desired_clk); | |
1177 | achieved = DIV_ROUND_CLOSEST(freq, div); | |
1178 | if (achieved <= desired_clk + abs_tol && | |
1179 | achieved >= desired_clk - abs_tol) { | |
1180 | *clk_div = div; | |
1181 | return freq; | |
1182 | } | |
c2194bc9 | 1183 | |
c474c775 | 1184 | div = DIV_ROUND_UP(freq, desired_clk); |
c4f52879 KR |
1185 | } |
1186 | ||
c474c775 VKN |
1187 | return 0; |
1188 | } | |
1189 | ||
1190 | static unsigned long get_clk_div_rate(struct clk *clk, unsigned int baud, | |
1191 | unsigned int sampling_rate, unsigned int *clk_div) | |
1192 | { | |
1193 | unsigned long ser_clk; | |
1194 | unsigned long desired_clk; | |
1195 | ||
1196 | desired_clk = baud * sampling_rate; | |
1197 | if (!desired_clk) | |
1198 | return 0; | |
1199 | ||
1200 | /* | |
1201 | * try to find a clock rate within 2% tolerance, then within 5% | |
1202 | */ | |
1203 | ser_clk = find_clk_rate_in_tol(clk, desired_clk, clk_div, 2); | |
1204 | if (!ser_clk) | |
1205 | ser_clk = find_clk_rate_in_tol(clk, desired_clk, clk_div, 5); | |
c2194bc9 | 1206 | |
c4f52879 KR |
1207 | return ser_clk; |
1208 | } | |
1209 | ||
1210 | static void qcom_geni_serial_set_termios(struct uart_port *uport, | |
bec5b814 IJ |
1211 | struct ktermios *termios, |
1212 | const struct ktermios *old) | |
c4f52879 KR |
1213 | { |
1214 | unsigned int baud; | |
385298ab RC |
1215 | u32 bits_per_char; |
1216 | u32 tx_trans_cfg; | |
1217 | u32 tx_parity_cfg; | |
1218 | u32 rx_trans_cfg; | |
1219 | u32 rx_parity_cfg; | |
1220 | u32 stop_bit_len; | |
c4f52879 | 1221 | unsigned int clk_div; |
385298ab | 1222 | u32 ser_clk_cfg; |
00ce7c6e | 1223 | struct qcom_geni_serial_port *port = to_dev_port(uport); |
c4f52879 | 1224 | unsigned long clk_rate; |
ce734600 | 1225 | u32 ver, sampling_rate; |
7cf563b2 | 1226 | unsigned int avg_bw_core; |
c4f52879 KR |
1227 | |
1228 | qcom_geni_serial_stop_rx(uport); | |
1229 | /* baud rate */ | |
1230 | baud = uart_get_baud_rate(uport, termios, old, 300, 4000000); | |
1231 | port->baud = baud; | |
ce734600 VG |
1232 | |
1233 | sampling_rate = UART_OVERSAMPLING; | |
1234 | /* Sampling rate is halved for IP versions >= 2.5 */ | |
1235 | ver = geni_se_get_qup_hw_version(&port->se); | |
c9ca43d4 | 1236 | if (ver >= QUP_SE_VERSION_2_5) |
ce734600 VG |
1237 | sampling_rate /= 2; |
1238 | ||
c2194bc9 VKN |
1239 | clk_rate = get_clk_div_rate(port->se.clk, baud, |
1240 | sampling_rate, &clk_div); | |
c474c775 VKN |
1241 | if (!clk_rate) { |
1242 | dev_err(port->se.dev, | |
0fec5180 | 1243 | "Couldn't find suitable clock rate for %u\n", |
c474c775 | 1244 | baud * sampling_rate); |
c4f52879 | 1245 | goto out_restart_rx; |
c474c775 VKN |
1246 | } |
1247 | ||
18536cc8 | 1248 | dev_dbg(port->se.dev, "desired_rate = %u, clk_rate = %lu, clk_div = %u\n", |
c474c775 | 1249 | baud * sampling_rate, clk_rate, clk_div); |
c4f52879 KR |
1250 | |
1251 | uport->uartclk = clk_rate; | |
8ece7b75 | 1252 | port->clk_rate = clk_rate; |
a5819b54 | 1253 | dev_pm_opp_set_rate(uport->dev, clk_rate); |
c4f52879 KR |
1254 | ser_clk_cfg = SER_CLK_EN; |
1255 | ser_clk_cfg |= clk_div << CLK_DIV_SHFT; | |
1256 | ||
7cf563b2 AA |
1257 | /* |
1258 | * Bump up BW vote on CPU and CORE path as driver supports FIFO mode | |
1259 | * only. | |
1260 | */ | |
1261 | avg_bw_core = (baud > 115200) ? Bps_to_icc(CORE_2X_50_MHZ) | |
1262 | : GENI_DEFAULT_BW; | |
1263 | port->se.icc_paths[GENI_TO_CORE].avg_bw = avg_bw_core; | |
1264 | port->se.icc_paths[CPU_TO_GENI].avg_bw = Bps_to_icc(baud); | |
1265 | geni_icc_set_bw(&port->se); | |
1266 | ||
c4f52879 | 1267 | /* parity */ |
9e06d55f RC |
1268 | tx_trans_cfg = readl(uport->membase + SE_UART_TX_TRANS_CFG); |
1269 | tx_parity_cfg = readl(uport->membase + SE_UART_TX_PARITY_CFG); | |
1270 | rx_trans_cfg = readl(uport->membase + SE_UART_RX_TRANS_CFG); | |
1271 | rx_parity_cfg = readl(uport->membase + SE_UART_RX_PARITY_CFG); | |
c4f52879 KR |
1272 | if (termios->c_cflag & PARENB) { |
1273 | tx_trans_cfg |= UART_TX_PAR_EN; | |
1274 | rx_trans_cfg |= UART_RX_PAR_EN; | |
1275 | tx_parity_cfg |= PAR_CALC_EN; | |
1276 | rx_parity_cfg |= PAR_CALC_EN; | |
1277 | if (termios->c_cflag & PARODD) { | |
1278 | tx_parity_cfg |= PAR_ODD; | |
1279 | rx_parity_cfg |= PAR_ODD; | |
1280 | } else if (termios->c_cflag & CMSPAR) { | |
1281 | tx_parity_cfg |= PAR_SPACE; | |
1282 | rx_parity_cfg |= PAR_SPACE; | |
1283 | } else { | |
1284 | tx_parity_cfg |= PAR_EVEN; | |
1285 | rx_parity_cfg |= PAR_EVEN; | |
1286 | } | |
1287 | } else { | |
1288 | tx_trans_cfg &= ~UART_TX_PAR_EN; | |
1289 | rx_trans_cfg &= ~UART_RX_PAR_EN; | |
1290 | tx_parity_cfg &= ~PAR_CALC_EN; | |
1291 | rx_parity_cfg &= ~PAR_CALC_EN; | |
1292 | } | |
1293 | ||
1294 | /* bits per char */ | |
3ec2ff37 | 1295 | bits_per_char = tty_get_char_size(termios->c_cflag); |
c4f52879 KR |
1296 | |
1297 | /* stop bits */ | |
1298 | if (termios->c_cflag & CSTOPB) | |
1299 | stop_bit_len = TX_STOP_BIT_LEN_2; | |
1300 | else | |
1301 | stop_bit_len = TX_STOP_BIT_LEN_1; | |
1302 | ||
1303 | /* flow control, clear the CTS_MASK bit if using flow control. */ | |
1304 | if (termios->c_cflag & CRTSCTS) | |
1305 | tx_trans_cfg &= ~UART_CTS_MASK; | |
1306 | else | |
1307 | tx_trans_cfg |= UART_CTS_MASK; | |
1308 | ||
1309 | if (baud) | |
1310 | uart_update_timeout(uport, termios->c_cflag, baud); | |
1311 | ||
8a8a66a1 | 1312 | if (!uart_console(uport)) |
9e06d55f | 1313 | writel(port->loopback, |
8a8a66a1 | 1314 | uport->membase + SE_UART_LOOPBACK_CFG); |
9e06d55f RC |
1315 | writel(tx_trans_cfg, uport->membase + SE_UART_TX_TRANS_CFG); |
1316 | writel(tx_parity_cfg, uport->membase + SE_UART_TX_PARITY_CFG); | |
1317 | writel(rx_trans_cfg, uport->membase + SE_UART_RX_TRANS_CFG); | |
1318 | writel(rx_parity_cfg, uport->membase + SE_UART_RX_PARITY_CFG); | |
1319 | writel(bits_per_char, uport->membase + SE_UART_TX_WORD_LEN); | |
1320 | writel(bits_per_char, uport->membase + SE_UART_RX_WORD_LEN); | |
1321 | writel(stop_bit_len, uport->membase + SE_UART_TX_STOP_BIT_LEN); | |
1322 | writel(ser_clk_cfg, uport->membase + GENI_SER_M_CLK_CFG); | |
1323 | writel(ser_clk_cfg, uport->membase + GENI_SER_S_CLK_CFG); | |
c4f52879 KR |
1324 | out_restart_rx: |
1325 | qcom_geni_serial_start_rx(uport); | |
1326 | } | |
1327 | ||
c4f52879 | 1328 | #ifdef CONFIG_SERIAL_QCOM_GENI_CONSOLE |
975efc66 | 1329 | static int qcom_geni_console_setup(struct console *co, char *options) |
c4f52879 KR |
1330 | { |
1331 | struct uart_port *uport; | |
1332 | struct qcom_geni_serial_port *port; | |
2ec812a0 | 1333 | int baud = 115200; |
c4f52879 KR |
1334 | int bits = 8; |
1335 | int parity = 'n'; | |
1336 | int flow = 'n'; | |
c362272b | 1337 | int ret; |
c4f52879 KR |
1338 | |
1339 | if (co->index >= GENI_UART_CONS_PORTS || co->index < 0) | |
1340 | return -ENXIO; | |
1341 | ||
8a8a66a1 | 1342 | port = get_port_from_line(co->index, true); |
c4f52879 | 1343 | if (IS_ERR(port)) { |
6a10635e | 1344 | pr_err("Invalid line %d\n", co->index); |
c4f52879 KR |
1345 | return PTR_ERR(port); |
1346 | } | |
1347 | ||
1348 | uport = &port->uport; | |
1349 | ||
1350 | if (unlikely(!uport->membase)) | |
1351 | return -ENXIO; | |
1352 | ||
c4f52879 | 1353 | if (!port->setup) { |
c362272b DA |
1354 | ret = qcom_geni_serial_port_setup(uport); |
1355 | if (ret) | |
1356 | return ret; | |
c4f52879 KR |
1357 | } |
1358 | ||
1359 | if (options) | |
1360 | uart_parse_options(options, &baud, &parity, &bits, &flow); | |
1361 | ||
1362 | return uart_set_options(uport, co, baud, parity, bits, flow); | |
1363 | } | |
1364 | ||
43f1831b KR |
1365 | static void qcom_geni_serial_earlycon_write(struct console *con, |
1366 | const char *s, unsigned int n) | |
1367 | { | |
1368 | struct earlycon_device *dev = con->data; | |
1369 | ||
1370 | __qcom_geni_serial_console_write(&dev->port, s, n); | |
1371 | } | |
1372 | ||
205b5bdd DA |
1373 | #ifdef CONFIG_CONSOLE_POLL |
1374 | static int qcom_geni_serial_earlycon_read(struct console *con, | |
1375 | char *s, unsigned int n) | |
1376 | { | |
1377 | struct earlycon_device *dev = con->data; | |
1378 | struct uart_port *uport = &dev->port; | |
1379 | int num_read = 0; | |
1380 | int ch; | |
1381 | ||
1382 | while (num_read < n) { | |
1383 | ch = qcom_geni_serial_get_char(uport); | |
1384 | if (ch == NO_POLL_CHAR) | |
1385 | break; | |
1386 | s[num_read++] = ch; | |
1387 | } | |
1388 | ||
1389 | return num_read; | |
1390 | } | |
1391 | ||
1392 | static void __init qcom_geni_serial_enable_early_read(struct geni_se *se, | |
1393 | struct console *con) | |
1394 | { | |
1395 | geni_se_setup_s_cmd(se, UART_START_READ, 0); | |
1396 | con->read = qcom_geni_serial_earlycon_read; | |
1397 | } | |
1398 | #else | |
1399 | static inline void qcom_geni_serial_enable_early_read(struct geni_se *se, | |
1400 | struct console *con) { } | |
1401 | #endif | |
1402 | ||
e42d6c3e DA |
1403 | static struct qcom_geni_private_data earlycon_private_data; |
1404 | ||
43f1831b KR |
1405 | static int __init qcom_geni_serial_earlycon_setup(struct earlycon_device *dev, |
1406 | const char *opt) | |
1407 | { | |
1408 | struct uart_port *uport = &dev->port; | |
1409 | u32 tx_trans_cfg; | |
1410 | u32 tx_parity_cfg = 0; /* Disable Tx Parity */ | |
1411 | u32 rx_trans_cfg = 0; | |
1412 | u32 rx_parity_cfg = 0; /* Disable Rx Parity */ | |
1413 | u32 stop_bit_len = 0; /* Default stop bit length - 1 bit */ | |
1414 | u32 bits_per_char; | |
1415 | struct geni_se se; | |
1416 | ||
1417 | if (!uport->membase) | |
1418 | return -EINVAL; | |
1419 | ||
e42d6c3e DA |
1420 | uport->private_data = &earlycon_private_data; |
1421 | ||
43f1831b KR |
1422 | memset(&se, 0, sizeof(se)); |
1423 | se.base = uport->membase; | |
1424 | if (geni_se_read_proto(&se) != GENI_SE_UART) | |
1425 | return -ENXIO; | |
1426 | /* | |
1427 | * Ignore Flow control. | |
1428 | * n = 8. | |
1429 | */ | |
1430 | tx_trans_cfg = UART_CTS_MASK; | |
1431 | bits_per_char = BITS_PER_BYTE; | |
1432 | ||
1433 | /* | |
1434 | * Make an unconditional cancel on the main sequencer to reset | |
1435 | * it else we could end up in data loss scenarios. | |
1436 | */ | |
1437 | qcom_geni_serial_poll_tx_done(uport); | |
1438 | qcom_geni_serial_abort_rx(uport); | |
650c8bd3 DA |
1439 | geni_se_config_packing(&se, BITS_PER_BYTE, BYTES_PER_FIFO_WORD, |
1440 | false, true, true); | |
43f1831b KR |
1441 | geni_se_init(&se, DEF_FIFO_DEPTH_WORDS / 2, DEF_FIFO_DEPTH_WORDS - 2); |
1442 | geni_se_select_mode(&se, GENI_SE_FIFO); | |
1443 | ||
9e06d55f RC |
1444 | writel(tx_trans_cfg, uport->membase + SE_UART_TX_TRANS_CFG); |
1445 | writel(tx_parity_cfg, uport->membase + SE_UART_TX_PARITY_CFG); | |
1446 | writel(rx_trans_cfg, uport->membase + SE_UART_RX_TRANS_CFG); | |
1447 | writel(rx_parity_cfg, uport->membase + SE_UART_RX_PARITY_CFG); | |
1448 | writel(bits_per_char, uport->membase + SE_UART_TX_WORD_LEN); | |
1449 | writel(bits_per_char, uport->membase + SE_UART_RX_WORD_LEN); | |
1450 | writel(stop_bit_len, uport->membase + SE_UART_TX_STOP_BIT_LEN); | |
43f1831b KR |
1451 | |
1452 | dev->con->write = qcom_geni_serial_earlycon_write; | |
1453 | dev->con->setup = NULL; | |
205b5bdd DA |
1454 | qcom_geni_serial_enable_early_read(&se, dev->con); |
1455 | ||
43f1831b KR |
1456 | return 0; |
1457 | } | |
1458 | OF_EARLYCON_DECLARE(qcom_geni, "qcom,geni-debug-uart", | |
1459 | qcom_geni_serial_earlycon_setup); | |
1460 | ||
c4f52879 KR |
1461 | static int __init console_register(struct uart_driver *drv) |
1462 | { | |
1463 | return uart_register_driver(drv); | |
1464 | } | |
1465 | ||
1466 | static void console_unregister(struct uart_driver *drv) | |
1467 | { | |
1468 | uart_unregister_driver(drv); | |
1469 | } | |
1470 | ||
1471 | static struct console cons_ops = { | |
1472 | .name = "ttyMSM", | |
1473 | .write = qcom_geni_serial_console_write, | |
1474 | .device = uart_console_device, | |
1475 | .setup = qcom_geni_console_setup, | |
1476 | .flags = CON_PRINTBUFFER, | |
1477 | .index = -1, | |
1478 | .data = &qcom_geni_console_driver, | |
1479 | }; | |
1480 | ||
1481 | static struct uart_driver qcom_geni_console_driver = { | |
1482 | .owner = THIS_MODULE, | |
1483 | .driver_name = "qcom_geni_console", | |
1484 | .dev_name = "ttyMSM", | |
1485 | .nr = GENI_UART_CONS_PORTS, | |
1486 | .cons = &cons_ops, | |
1487 | }; | |
1488 | #else | |
1489 | static int console_register(struct uart_driver *drv) | |
1490 | { | |
1491 | return 0; | |
1492 | } | |
1493 | ||
1494 | static void console_unregister(struct uart_driver *drv) | |
1495 | { | |
1496 | } | |
1497 | #endif /* CONFIG_SERIAL_QCOM_GENI_CONSOLE */ | |
1498 | ||
8a8a66a1 GM |
1499 | static struct uart_driver qcom_geni_uart_driver = { |
1500 | .owner = THIS_MODULE, | |
1501 | .driver_name = "qcom_geni_uart", | |
1502 | .dev_name = "ttyHS", | |
1503 | .nr = GENI_UART_PORTS, | |
1504 | }; | |
1505 | ||
1506 | static void qcom_geni_serial_pm(struct uart_port *uport, | |
c4f52879 KR |
1507 | unsigned int new_state, unsigned int old_state) |
1508 | { | |
00ce7c6e | 1509 | struct qcom_geni_serial_port *port = to_dev_port(uport); |
c4f52879 | 1510 | |
c362272b DA |
1511 | /* If we've never been called, treat it as off */ |
1512 | if (old_state == UART_PM_STATE_UNDEFINED) | |
1513 | old_state = UART_PM_STATE_OFF; | |
1514 | ||
7cf563b2 AA |
1515 | if (new_state == UART_PM_STATE_ON && old_state == UART_PM_STATE_OFF) { |
1516 | geni_icc_enable(&port->se); | |
8ece7b75 JH |
1517 | if (port->clk_rate) |
1518 | dev_pm_opp_set_rate(uport->dev, port->clk_rate); | |
c4f52879 | 1519 | geni_se_resources_on(&port->se); |
7cf563b2 AA |
1520 | } else if (new_state == UART_PM_STATE_OFF && |
1521 | old_state == UART_PM_STATE_ON) { | |
c4f52879 | 1522 | geni_se_resources_off(&port->se); |
8ece7b75 | 1523 | dev_pm_opp_set_rate(uport->dev, 0); |
7cf563b2 AA |
1524 | geni_icc_disable(&port->se); |
1525 | } | |
c4f52879 KR |
1526 | } |
1527 | ||
1528 | static const struct uart_ops qcom_geni_console_pops = { | |
1529 | .tx_empty = qcom_geni_serial_tx_empty, | |
2aaa43c7 BG |
1530 | .stop_tx = qcom_geni_serial_stop_tx_fifo, |
1531 | .start_tx = qcom_geni_serial_start_tx_fifo, | |
1532 | .stop_rx = qcom_geni_serial_stop_rx_fifo, | |
1533 | .start_rx = qcom_geni_serial_start_rx_fifo, | |
c4f52879 KR |
1534 | .set_termios = qcom_geni_serial_set_termios, |
1535 | .startup = qcom_geni_serial_startup, | |
1536 | .request_port = qcom_geni_serial_request_port, | |
1537 | .config_port = qcom_geni_serial_config_port, | |
1538 | .shutdown = qcom_geni_serial_shutdown, | |
1539 | .type = qcom_geni_serial_get_type, | |
8a8a66a1 GM |
1540 | .set_mctrl = qcom_geni_serial_set_mctrl, |
1541 | .get_mctrl = qcom_geni_serial_get_mctrl, | |
c4f52879 KR |
1542 | #ifdef CONFIG_CONSOLE_POLL |
1543 | .poll_get_char = qcom_geni_serial_get_char, | |
1544 | .poll_put_char = qcom_geni_serial_poll_put_char, | |
d8851a96 | 1545 | .poll_init = qcom_geni_serial_port_setup, |
c4f52879 | 1546 | #endif |
8a8a66a1 GM |
1547 | .pm = qcom_geni_serial_pm, |
1548 | }; | |
1549 | ||
1550 | static const struct uart_ops qcom_geni_uart_pops = { | |
1551 | .tx_empty = qcom_geni_serial_tx_empty, | |
2aaa43c7 BG |
1552 | .stop_tx = qcom_geni_serial_stop_tx_dma, |
1553 | .start_tx = qcom_geni_serial_start_tx_dma, | |
1554 | .start_rx = qcom_geni_serial_start_rx_dma, | |
1555 | .stop_rx = qcom_geni_serial_stop_rx_dma, | |
8a8a66a1 GM |
1556 | .set_termios = qcom_geni_serial_set_termios, |
1557 | .startup = qcom_geni_serial_startup, | |
1558 | .request_port = qcom_geni_serial_request_port, | |
1559 | .config_port = qcom_geni_serial_config_port, | |
1560 | .shutdown = qcom_geni_serial_shutdown, | |
1561 | .type = qcom_geni_serial_get_type, | |
1562 | .set_mctrl = qcom_geni_serial_set_mctrl, | |
1563 | .get_mctrl = qcom_geni_serial_get_mctrl, | |
1564 | .pm = qcom_geni_serial_pm, | |
c4f52879 KR |
1565 | }; |
1566 | ||
1567 | static int qcom_geni_serial_probe(struct platform_device *pdev) | |
1568 | { | |
1569 | int ret = 0; | |
71581242 | 1570 | int line; |
c4f52879 KR |
1571 | struct qcom_geni_serial_port *port; |
1572 | struct uart_port *uport; | |
1573 | struct resource *res; | |
066cd1c4 | 1574 | int irq; |
8a8a66a1 | 1575 | struct uart_driver *drv; |
40ec6d41 | 1576 | const struct qcom_geni_device_data *data; |
c4f52879 | 1577 | |
40ec6d41 BG |
1578 | data = of_device_get_match_data(&pdev->dev); |
1579 | if (!data) | |
1580 | return -EINVAL; | |
c4f52879 | 1581 | |
40ec6d41 | 1582 | if (data->console) { |
2843cbb5 GU |
1583 | drv = &qcom_geni_console_driver; |
1584 | line = of_alias_get_id(pdev->dev.of_node, "serial"); | |
1585 | } else { | |
1586 | drv = &qcom_geni_uart_driver; | |
08b0adb1 DB |
1587 | line = of_alias_get_id(pdev->dev.of_node, "serial"); |
1588 | if (line == -ENODEV) /* compat with non-standard aliases */ | |
1589 | line = of_alias_get_id(pdev->dev.of_node, "hsuart"); | |
8a8a66a1 GM |
1590 | } |
1591 | ||
40ec6d41 | 1592 | port = get_port_from_line(line, data->console); |
c4f52879 | 1593 | if (IS_ERR(port)) { |
6a10635e KR |
1594 | dev_err(&pdev->dev, "Invalid line %d\n", line); |
1595 | return PTR_ERR(port); | |
c4f52879 KR |
1596 | } |
1597 | ||
1598 | uport = &port->uport; | |
1599 | /* Don't allow 2 drivers to access the same port */ | |
1600 | if (uport->private_data) | |
1601 | return -ENODEV; | |
1602 | ||
1603 | uport->dev = &pdev->dev; | |
40ec6d41 | 1604 | port->dev_data = data; |
c4f52879 KR |
1605 | port->se.dev = &pdev->dev; |
1606 | port->se.wrapper = dev_get_drvdata(pdev->dev.parent); | |
1607 | port->se.clk = devm_clk_get(&pdev->dev, "se"); | |
1608 | if (IS_ERR(port->se.clk)) { | |
1609 | ret = PTR_ERR(port->se.clk); | |
1610 | dev_err(&pdev->dev, "Err getting SE Core clk %d\n", ret); | |
1611 | return ret; | |
1612 | } | |
1613 | ||
1614 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
7693b331 WY |
1615 | if (!res) |
1616 | return -EINVAL; | |
c4f52879 KR |
1617 | uport->mapbase = res->start; |
1618 | ||
1619 | port->tx_fifo_depth = DEF_FIFO_DEPTH_WORDS; | |
1620 | port->rx_fifo_depth = DEF_FIFO_DEPTH_WORDS; | |
1621 | port->tx_fifo_width = DEF_FIFO_WIDTH_BITS; | |
1622 | ||
40ec6d41 | 1623 | if (!data->console) { |
2aaa43c7 BG |
1624 | port->rx_buf = devm_kzalloc(uport->dev, |
1625 | DMA_RX_BUF_SIZE, GFP_KERNEL); | |
1626 | if (!port->rx_buf) | |
f9d690b6 | 1627 | return -ENOMEM; |
1628 | } | |
1629 | ||
7cf563b2 AA |
1630 | ret = geni_icc_get(&port->se, NULL); |
1631 | if (ret) | |
1632 | return ret; | |
1633 | port->se.icc_paths[GENI_TO_CORE].avg_bw = GENI_DEFAULT_BW; | |
1634 | port->se.icc_paths[CPU_TO_GENI].avg_bw = GENI_DEFAULT_BW; | |
1635 | ||
1636 | /* Set BW for register access */ | |
1637 | ret = geni_icc_set_bw(&port->se); | |
1638 | if (ret) | |
1639 | return ret; | |
1640 | ||
f3974413 AA |
1641 | port->name = devm_kasprintf(uport->dev, GFP_KERNEL, |
1642 | "qcom_geni_serial_%s%d", | |
1643 | uart_console(uport) ? "console" : "uart", uport->line); | |
1644 | if (!port->name) | |
1645 | return -ENOMEM; | |
1646 | ||
066cd1c4 | 1647 | irq = platform_get_irq(pdev, 0); |
1df21786 | 1648 | if (irq < 0) |
066cd1c4 | 1649 | return irq; |
066cd1c4 | 1650 | uport->irq = irq; |
8f122698 | 1651 | uport->has_sysrq = IS_ENABLED(CONFIG_SERIAL_QCOM_GENI_CONSOLE); |
c4f52879 | 1652 | |
40ec6d41 | 1653 | if (!data->console) |
f3974413 AA |
1654 | port->wakeup_irq = platform_get_irq_optional(pdev, 1); |
1655 | ||
9fa3c4b1 RRY |
1656 | if (of_property_read_bool(pdev->dev.of_node, "rx-tx-swap")) |
1657 | port->rx_tx_swap = true; | |
1658 | ||
1659 | if (of_property_read_bool(pdev->dev.of_node, "cts-rts-swap")) | |
1660 | port->cts_rts_swap = true; | |
1661 | ||
300894a6 YL |
1662 | ret = devm_pm_opp_set_clkname(&pdev->dev, "se"); |
1663 | if (ret) | |
1664 | return ret; | |
a5819b54 | 1665 | /* OPP table is optional */ |
300894a6 | 1666 | ret = devm_pm_opp_of_add_table(&pdev->dev); |
c7ac46da | 1667 | if (ret && ret != -ENODEV) { |
a5819b54 | 1668 | dev_err(&pdev->dev, "invalid OPP table in device tree\n"); |
300894a6 | 1669 | return ret; |
a5819b54 RN |
1670 | } |
1671 | ||
e42d6c3e DA |
1672 | port->private_data.drv = drv; |
1673 | uport->private_data = &port->private_data; | |
f3974413 | 1674 | platform_set_drvdata(pdev, port); |
f3974413 | 1675 | |
3e4aaea7 AA |
1676 | irq_set_status_flags(uport->irq, IRQ_NOAUTOEN); |
1677 | ret = devm_request_irq(uport->dev, uport->irq, qcom_geni_serial_isr, | |
1678 | IRQF_TRIGGER_HIGH, port->name, uport); | |
1679 | if (ret) { | |
1680 | dev_err(uport->dev, "Failed to get IRQ ret %d\n", ret); | |
300894a6 | 1681 | return ret; |
3e4aaea7 AA |
1682 | } |
1683 | ||
5f949f14 KK |
1684 | ret = uart_add_one_port(drv, uport); |
1685 | if (ret) | |
1686 | return ret; | |
1687 | ||
f3974413 AA |
1688 | if (port->wakeup_irq > 0) { |
1689 | device_init_wakeup(&pdev->dev, true); | |
1690 | ret = dev_pm_set_dedicated_wake_irq(&pdev->dev, | |
1691 | port->wakeup_irq); | |
1692 | if (ret) { | |
1693 | device_init_wakeup(&pdev->dev, false); | |
1694 | uart_remove_one_port(drv, uport); | |
300894a6 | 1695 | return ret; |
8b7103f3 AA |
1696 | } |
1697 | } | |
f3974413 AA |
1698 | |
1699 | return 0; | |
c4f52879 KR |
1700 | } |
1701 | ||
1702 | static int qcom_geni_serial_remove(struct platform_device *pdev) | |
1703 | { | |
1704 | struct qcom_geni_serial_port *port = platform_get_drvdata(pdev); | |
e42d6c3e | 1705 | struct uart_driver *drv = port->private_data.drv; |
c4f52879 | 1706 | |
f3974413 AA |
1707 | dev_pm_clear_wake_irq(&pdev->dev); |
1708 | device_init_wakeup(&pdev->dev, false); | |
c4f52879 | 1709 | uart_remove_one_port(drv, &port->uport); |
f3974413 | 1710 | |
c4f52879 KR |
1711 | return 0; |
1712 | } | |
1713 | ||
5342ab0a | 1714 | static int qcom_geni_serial_sys_suspend(struct device *dev) |
c4f52879 | 1715 | { |
a406c4b8 | 1716 | struct qcom_geni_serial_port *port = dev_get_drvdata(dev); |
c4f52879 | 1717 | struct uart_port *uport = &port->uport; |
e42d6c3e | 1718 | struct qcom_geni_private_data *private_data = uport->private_data; |
c4f52879 | 1719 | |
4a3107f6 RN |
1720 | /* |
1721 | * This is done so we can hit the lowest possible state in suspend | |
1722 | * even with no_console_suspend | |
1723 | */ | |
1724 | if (uart_console(uport)) { | |
408e532e | 1725 | geni_icc_set_tag(&port->se, QCOM_ICC_TAG_ACTIVE_ONLY); |
4a3107f6 RN |
1726 | geni_icc_set_bw(&port->se); |
1727 | } | |
e42d6c3e | 1728 | return uart_suspend_port(private_data->drv, uport); |
c4f52879 KR |
1729 | } |
1730 | ||
5342ab0a | 1731 | static int qcom_geni_serial_sys_resume(struct device *dev) |
c4f52879 | 1732 | { |
4a3107f6 | 1733 | int ret; |
a406c4b8 | 1734 | struct qcom_geni_serial_port *port = dev_get_drvdata(dev); |
c4f52879 | 1735 | struct uart_port *uport = &port->uport; |
e42d6c3e | 1736 | struct qcom_geni_private_data *private_data = uport->private_data; |
c4f52879 | 1737 | |
4a3107f6 RN |
1738 | ret = uart_resume_port(private_data->drv, uport); |
1739 | if (uart_console(uport)) { | |
408e532e | 1740 | geni_icc_set_tag(&port->se, QCOM_ICC_TAG_ALWAYS); |
4a3107f6 RN |
1741 | geni_icc_set_bw(&port->se); |
1742 | } | |
1743 | return ret; | |
c4f52879 KR |
1744 | } |
1745 | ||
35781d83 AR |
1746 | static int qcom_geni_serial_sys_hib_resume(struct device *dev) |
1747 | { | |
1748 | int ret = 0; | |
1749 | struct uart_port *uport; | |
1750 | struct qcom_geni_private_data *private_data; | |
1751 | struct qcom_geni_serial_port *port = dev_get_drvdata(dev); | |
1752 | ||
1753 | uport = &port->uport; | |
1754 | private_data = uport->private_data; | |
1755 | ||
1756 | if (uart_console(uport)) { | |
51273792 | 1757 | geni_icc_set_tag(&port->se, QCOM_ICC_TAG_ALWAYS); |
35781d83 AR |
1758 | geni_icc_set_bw(&port->se); |
1759 | ret = uart_resume_port(private_data->drv, uport); | |
1760 | /* | |
1761 | * For hibernation usecase clients for | |
1762 | * console UART won't call port setup during restore, | |
1763 | * hence call port setup for console uart. | |
1764 | */ | |
1765 | qcom_geni_serial_port_setup(uport); | |
1766 | } else { | |
1767 | /* | |
1768 | * Peripheral register settings are lost during hibernation. | |
1769 | * Update setup flag such that port setup happens again | |
1770 | * during next session. Clients of HS-UART will close and | |
1771 | * open the port during hibernation. | |
1772 | */ | |
1773 | port->setup = false; | |
1774 | } | |
1775 | return ret; | |
1776 | } | |
1777 | ||
40ec6d41 BG |
1778 | static const struct qcom_geni_device_data qcom_geni_console_data = { |
1779 | .console = true, | |
2aaa43c7 | 1780 | .mode = GENI_SE_FIFO, |
40ec6d41 BG |
1781 | }; |
1782 | ||
1783 | static const struct qcom_geni_device_data qcom_geni_uart_data = { | |
1784 | .console = false, | |
2aaa43c7 | 1785 | .mode = GENI_SE_DMA, |
40ec6d41 BG |
1786 | }; |
1787 | ||
c4f52879 | 1788 | static const struct dev_pm_ops qcom_geni_serial_pm_ops = { |
5342ab0a AB |
1789 | .suspend = pm_sleep_ptr(qcom_geni_serial_sys_suspend), |
1790 | .resume = pm_sleep_ptr(qcom_geni_serial_sys_resume), | |
1791 | .freeze = pm_sleep_ptr(qcom_geni_serial_sys_suspend), | |
1792 | .poweroff = pm_sleep_ptr(qcom_geni_serial_sys_suspend), | |
1793 | .restore = pm_sleep_ptr(qcom_geni_serial_sys_hib_resume), | |
1794 | .thaw = pm_sleep_ptr(qcom_geni_serial_sys_hib_resume), | |
c4f52879 KR |
1795 | }; |
1796 | ||
1797 | static const struct of_device_id qcom_geni_serial_match_table[] = { | |
40ec6d41 BG |
1798 | { |
1799 | .compatible = "qcom,geni-debug-uart", | |
1800 | .data = &qcom_geni_console_data, | |
1801 | }, | |
1802 | { | |
1803 | .compatible = "qcom,geni-uart", | |
1804 | .data = &qcom_geni_uart_data, | |
1805 | }, | |
c4f52879 KR |
1806 | {} |
1807 | }; | |
1808 | MODULE_DEVICE_TABLE(of, qcom_geni_serial_match_table); | |
1809 | ||
1810 | static struct platform_driver qcom_geni_serial_platform_driver = { | |
1811 | .remove = qcom_geni_serial_remove, | |
1812 | .probe = qcom_geni_serial_probe, | |
1813 | .driver = { | |
1814 | .name = "qcom_geni_serial", | |
1815 | .of_match_table = qcom_geni_serial_match_table, | |
1816 | .pm = &qcom_geni_serial_pm_ops, | |
1817 | }, | |
1818 | }; | |
1819 | ||
1820 | static int __init qcom_geni_serial_init(void) | |
1821 | { | |
1822 | int ret; | |
1823 | ||
c4f52879 KR |
1824 | ret = console_register(&qcom_geni_console_driver); |
1825 | if (ret) | |
1826 | return ret; | |
1827 | ||
8a8a66a1 GM |
1828 | ret = uart_register_driver(&qcom_geni_uart_driver); |
1829 | if (ret) { | |
1830 | console_unregister(&qcom_geni_console_driver); | |
1831 | return ret; | |
1832 | } | |
1833 | ||
c4f52879 | 1834 | ret = platform_driver_register(&qcom_geni_serial_platform_driver); |
8a8a66a1 | 1835 | if (ret) { |
c4f52879 | 1836 | console_unregister(&qcom_geni_console_driver); |
8a8a66a1 GM |
1837 | uart_unregister_driver(&qcom_geni_uart_driver); |
1838 | } | |
c4f52879 KR |
1839 | return ret; |
1840 | } | |
1841 | module_init(qcom_geni_serial_init); | |
1842 | ||
1843 | static void __exit qcom_geni_serial_exit(void) | |
1844 | { | |
1845 | platform_driver_unregister(&qcom_geni_serial_platform_driver); | |
1846 | console_unregister(&qcom_geni_console_driver); | |
8a8a66a1 | 1847 | uart_unregister_driver(&qcom_geni_uart_driver); |
c4f52879 KR |
1848 | } |
1849 | module_exit(qcom_geni_serial_exit); | |
1850 | ||
1851 | MODULE_DESCRIPTION("Serial driver for GENI based QUP cores"); | |
1852 | MODULE_LICENSE("GPL v2"); |