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Merge tag 'upstream-4.18-rc1' of git://git.infradead.org/linux-ubifs
[linux-2.6-block.git] / drivers / tty / serial / qcom_geni_serial.c
CommitLineData
c4f52879
KR		 1// SPDX-License-Identifier: GPL-2.0
2// Copyright (c) 2017-2018, The Linux foundation. All rights reserved.
3
4#include <linux/clk.h>
5#include <linux/console.h>
6#include <linux/io.h>
7#include <linux/iopoll.h>
8#include <linux/module.h>
9#include <linux/of.h>
10#include <linux/of_device.h>
11#include <linux/platform_device.h>
12#include <linux/qcom-geni-se.h>
13#include <linux/serial.h>
14#include <linux/serial_core.h>
15#include <linux/slab.h>
16#include <linux/tty.h>
17#include <linux/tty_flip.h>
18
19/* UART specific GENI registers */
20#define SE_UART_TX_TRANS_CFG 0x25c
21#define SE_UART_TX_WORD_LEN 0x268
22#define SE_UART_TX_STOP_BIT_LEN 0x26c
23#define SE_UART_TX_TRANS_LEN 0x270
24#define SE_UART_RX_TRANS_CFG 0x280
25#define SE_UART_RX_WORD_LEN 0x28c
26#define SE_UART_RX_STALE_CNT 0x294
27#define SE_UART_TX_PARITY_CFG 0x2a4
28#define SE_UART_RX_PARITY_CFG 0x2a8
29
30/* SE_UART_TRANS_CFG */
31#define UART_TX_PAR_EN BIT(0)
32#define UART_CTS_MASK BIT(1)
33
34/* SE_UART_TX_WORD_LEN */
35#define TX_WORD_LEN_MSK GENMASK(9, 0)
36
37/* SE_UART_TX_STOP_BIT_LEN */
38#define TX_STOP_BIT_LEN_MSK GENMASK(23, 0)
39#define TX_STOP_BIT_LEN_1 0
40#define TX_STOP_BIT_LEN_1_5 1
41#define TX_STOP_BIT_LEN_2 2
42
43/* SE_UART_TX_TRANS_LEN */
44#define TX_TRANS_LEN_MSK GENMASK(23, 0)
45
46/* SE_UART_RX_TRANS_CFG */
47#define UART_RX_INS_STATUS_BIT BIT(2)
48#define UART_RX_PAR_EN BIT(3)
49
50/* SE_UART_RX_WORD_LEN */
51#define RX_WORD_LEN_MASK GENMASK(9, 0)
52
53/* SE_UART_RX_STALE_CNT */
54#define RX_STALE_CNT GENMASK(23, 0)
55
56/* SE_UART_TX_PARITY_CFG/RX_PARITY_CFG */
57#define PAR_CALC_EN BIT(0)
58#define PAR_MODE_MSK GENMASK(2, 1)
59#define PAR_MODE_SHFT 1
60#define PAR_EVEN 0x00
61#define PAR_ODD 0x01
62#define PAR_SPACE 0x10
63#define PAR_MARK 0x11
64
65/* UART M_CMD OP codes */
66#define UART_START_TX 0x1
67#define UART_START_BREAK 0x4
68#define UART_STOP_BREAK 0x5
69/* UART S_CMD OP codes */
70#define UART_START_READ 0x1
71#define UART_PARAM 0x1
72
73#define UART_OVERSAMPLING 32
74#define STALE_TIMEOUT 16
75#define DEFAULT_BITS_PER_CHAR 10
76#define GENI_UART_CONS_PORTS 1
77#define DEF_FIFO_DEPTH_WORDS 16
78#define DEF_TX_WM 2
79#define DEF_FIFO_WIDTH_BITS 32
80#define UART_CONSOLE_RX_WM 2
81
82#ifdef CONFIG_CONSOLE_POLL
83#define RX_BYTES_PW 1
84#else
85#define RX_BYTES_PW 4
86#endif
87
88struct qcom_geni_serial_port {
89 struct uart_port uport;
90 struct geni_se se;
91 char name[20];
92 u32 tx_fifo_depth;
93 u32 tx_fifo_width;
94 u32 rx_fifo_depth;
95 u32 tx_wm;
96 u32 rx_wm;
97 u32 rx_rfr;
98 enum geni_se_xfer_mode xfer_mode;
99 bool setup;
100 int (*handle_rx)(struct uart_port *uport, u32 bytes, bool drop);
c4f52879
KR		 101 unsigned int baud;
102 unsigned int tx_bytes_pw;
103 unsigned int rx_bytes_pw;
104 bool brk;
105};
106
f7371750 107static const struct uart_ops qcom_geni_console_pops;
c4f52879
KR		 108static struct uart_driver qcom_geni_console_driver;
109static int handle_rx_console(struct uart_port *uport, u32 bytes, bool drop);
110static unsigned int qcom_geni_serial_tx_empty(struct uart_port *port);
111static void qcom_geni_serial_stop_rx(struct uart_port *uport);
112
113static const unsigned long root_freq[] = {7372800, 14745600, 19200000, 29491200,
114 32000000, 48000000, 64000000, 80000000,
115 96000000, 100000000};
116
117#define to_dev_port(ptr, member) \
118 container_of(ptr, struct qcom_geni_serial_port, member)
119
f7371750
KR		 120static struct qcom_geni_serial_port qcom_geni_console_port = {
121 .uport = {
122 .iotype = UPIO_MEM,
123 .ops = &qcom_geni_console_pops,
124 .flags = UPF_BOOT_AUTOCONF,
125 .line = 0,
126 },
127};
c4f52879
KR		 128
129static int qcom_geni_serial_request_port(struct uart_port *uport)
130{
131 struct platform_device *pdev = to_platform_device(uport->dev);
132 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
133 struct resource *res;
134
135 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
136 uport->membase = devm_ioremap_resource(&pdev->dev, res);
137 if (IS_ERR(uport->membase))
138 return PTR_ERR(uport->membase);
139 port->se.base = uport->membase;
140 return 0;
141}
142
143static void qcom_geni_serial_config_port(struct uart_port *uport, int cfg_flags)
144{
145 if (cfg_flags & UART_CONFIG_TYPE) {
146 uport->type = PORT_MSM;
147 qcom_geni_serial_request_port(uport);
148 }
149}
150
151static unsigned int qcom_geni_cons_get_mctrl(struct uart_port *uport)
152{
153 return TIOCM_DSR | TIOCM_CAR | TIOCM_CTS;
154}
155
156static void qcom_geni_cons_set_mctrl(struct uart_port *uport,
157 unsigned int mctrl)
158{
159}
160
161static const char *qcom_geni_serial_get_type(struct uart_port *uport)
162{
163 return "MSM";
164}
165
166static struct qcom_geni_serial_port *get_port_from_line(int line)
167{
168 if (line < 0 || line >= GENI_UART_CONS_PORTS)
169 return ERR_PTR(-ENXIO);
170 return &qcom_geni_console_port;
171}
172
173static bool qcom_geni_serial_poll_bit(struct uart_port *uport,
174 int offset, int field, bool set)
175{
176 u32 reg;
177 struct qcom_geni_serial_port *port;
178 unsigned int baud;
179 unsigned int fifo_bits;
180 unsigned long timeout_us = 20000;
181
182 /* Ensure polling is not re-ordered before the prior writes/reads */
183 mb();
184
185 if (uport->private_data) {
186 port = to_dev_port(uport, uport);
187 baud = port->baud;
188 if (!baud)
189 baud = 115200;
190 fifo_bits = port->tx_fifo_depth * port->tx_fifo_width;
191 /*
192 * Total polling iterations based on FIFO worth of bytes to be
193 * sent at current baud. Add a little fluff to the wait.
194 */
195 timeout_us = ((fifo_bits * USEC_PER_SEC) / baud) + 500;
196 }
197
43f1831b
KR		 198 /*
199 * Use custom implementation instead of readl_poll_atomic since ktimer
200 * is not ready at the time of early console.
201 */
202 timeout_us = DIV_ROUND_UP(timeout_us, 10) * 10;
203 while (timeout_us) {
204 reg = readl_relaxed(uport->membase + offset);
205 if ((bool)(reg & field) == set)
206 return true;
207 udelay(10);
208 timeout_us -= 10;
209 }
210 return false;
c4f52879
KR		 211}
212
213static void qcom_geni_serial_setup_tx(struct uart_port *uport, u32 xmit_size)
214{
215 u32 m_cmd;
216
217 writel_relaxed(xmit_size, uport->membase + SE_UART_TX_TRANS_LEN);
218 m_cmd = UART_START_TX << M_OPCODE_SHFT;
219 writel(m_cmd, uport->membase + SE_GENI_M_CMD0);
220}
221
222static void qcom_geni_serial_poll_tx_done(struct uart_port *uport)
223{
224 int done;
225 u32 irq_clear = M_CMD_DONE_EN;
226
227 done = qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
228 M_CMD_DONE_EN, true);
229 if (!done) {
230 writel_relaxed(M_GENI_CMD_ABORT, uport->membase +
231 SE_GENI_M_CMD_CTRL_REG);
232 irq_clear |= M_CMD_ABORT_EN;
233 qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
234 M_CMD_ABORT_EN, true);
235 }
236 writel_relaxed(irq_clear, uport->membase + SE_GENI_M_IRQ_CLEAR);
237}
238
239static void qcom_geni_serial_abort_rx(struct uart_port *uport)
240{
241 u32 irq_clear = S_CMD_DONE_EN | S_CMD_ABORT_EN;
242
243 writel(S_GENI_CMD_ABORT, uport->membase + SE_GENI_S_CMD_CTRL_REG);
244 qcom_geni_serial_poll_bit(uport, SE_GENI_S_CMD_CTRL_REG,
245 S_GENI_CMD_ABORT, false);
246 writel_relaxed(irq_clear, uport->membase + SE_GENI_S_IRQ_CLEAR);
247 writel_relaxed(FORCE_DEFAULT, uport->membase + GENI_FORCE_DEFAULT_REG);
248}
249
250#ifdef CONFIG_CONSOLE_POLL
251static int qcom_geni_serial_get_char(struct uart_port *uport)
252{
253 u32 rx_fifo;
254 u32 status;
255
256 status = readl_relaxed(uport->membase + SE_GENI_M_IRQ_STATUS);
257 writel_relaxed(status, uport->membase + SE_GENI_M_IRQ_CLEAR);
258
259 status = readl_relaxed(uport->membase + SE_GENI_S_IRQ_STATUS);
260 writel_relaxed(status, uport->membase + SE_GENI_S_IRQ_CLEAR);
261
262 /*
263 * Ensure the writes to clear interrupts is not re-ordered after
264 * reading the data.
265 */
266 mb();
267
268 status = readl_relaxed(uport->membase + SE_GENI_RX_FIFO_STATUS);
269 if (!(status & RX_FIFO_WC_MSK))
270 return NO_POLL_CHAR;
271
272 rx_fifo = readl(uport->membase + SE_GENI_RX_FIFOn);
273 return rx_fifo & 0xff;
274}
275
276static void qcom_geni_serial_poll_put_char(struct uart_port *uport,
277 unsigned char c)
278{
279 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
280
281 writel_relaxed(port->tx_wm, uport->membase + SE_GENI_TX_WATERMARK_REG);
282 qcom_geni_serial_setup_tx(uport, 1);
283 WARN_ON(!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
284 M_TX_FIFO_WATERMARK_EN, true));
285 writel_relaxed(c, uport->membase + SE_GENI_TX_FIFOn);
286 writel_relaxed(M_TX_FIFO_WATERMARK_EN, uport->membase +
287 SE_GENI_M_IRQ_CLEAR);
288 qcom_geni_serial_poll_tx_done(uport);
289}
290#endif
291
292#ifdef CONFIG_SERIAL_QCOM_GENI_CONSOLE
293static void qcom_geni_serial_wr_char(struct uart_port *uport, int ch)
294{
295 writel_relaxed(ch, uport->membase + SE_GENI_TX_FIFOn);
296}
297
298static void
299__qcom_geni_serial_console_write(struct uart_port *uport, const char *s,
300 unsigned int count)
301{
302 int i;
303 u32 bytes_to_send = count;
304
305 for (i = 0; i < count; i++) {
f0262568
KR		 306 /*
307 * uart_console_write() adds a carriage return for each newline.
308 * Account for additional bytes to be written.
309 */
c4f52879
KR		 310 if (s[i] == '\n')
311 bytes_to_send++;
312 }
313
314 writel_relaxed(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG);
315 qcom_geni_serial_setup_tx(uport, bytes_to_send);
316 for (i = 0; i < count; ) {
317 size_t chars_to_write = 0;
318 size_t avail = DEF_FIFO_DEPTH_WORDS - DEF_TX_WM;
319
320 /*
321 * If the WM bit never set, then the Tx state machine is not
322 * in a valid state, so break, cancel/abort any existing
323 * command. Unfortunately the current data being written is
324 * lost.
325 */
326 if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
327 M_TX_FIFO_WATERMARK_EN, true))
328 break;
6a10635e 329 chars_to_write = min_t(size_t, count - i, avail / 2);
c4f52879
KR		 330 uart_console_write(uport, s + i, chars_to_write,
331 qcom_geni_serial_wr_char);
332 writel_relaxed(M_TX_FIFO_WATERMARK_EN, uport->membase +
333 SE_GENI_M_IRQ_CLEAR);
334 i += chars_to_write;
335 }
336 qcom_geni_serial_poll_tx_done(uport);
337}
338
339static void qcom_geni_serial_console_write(struct console *co, const char *s,
340 unsigned int count)
341{
342 struct uart_port *uport;
343 struct qcom_geni_serial_port *port;
344 bool locked = true;
345 unsigned long flags;
346
347 WARN_ON(co->index < 0 || co->index >= GENI_UART_CONS_PORTS);
348
349 port = get_port_from_line(co->index);
350 if (IS_ERR(port))
351 return;
352
353 uport = &port->uport;
354 if (oops_in_progress)
355 locked = spin_trylock_irqsave(&uport->lock, flags);
356 else
357 spin_lock_irqsave(&uport->lock, flags);
358
359 /* Cancel the current write to log the fault */
360 if (!locked) {
361 geni_se_cancel_m_cmd(&port->se);
362 if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
363 M_CMD_CANCEL_EN, true)) {
364 geni_se_abort_m_cmd(&port->se);
365 qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
366 M_CMD_ABORT_EN, true);
367 writel_relaxed(M_CMD_ABORT_EN, uport->membase +
368 SE_GENI_M_IRQ_CLEAR);
369 }
370 writel_relaxed(M_CMD_CANCEL_EN, uport->membase +
371 SE_GENI_M_IRQ_CLEAR);
372 }
373
374 __qcom_geni_serial_console_write(uport, s, count);
375 if (locked)
376 spin_unlock_irqrestore(&uport->lock, flags);
377}
378
379static int handle_rx_console(struct uart_port *uport, u32 bytes, bool drop)
380{
381 u32 i;
382 unsigned char buf[sizeof(u32)];
383 struct tty_port *tport;
384 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
385
386 tport = &uport->state->port;
387 for (i = 0; i < bytes; ) {
388 int c;
389 int chunk = min_t(int, bytes - i, port->rx_bytes_pw);
390
391 ioread32_rep(uport->membase + SE_GENI_RX_FIFOn, buf, 1);
392 i += chunk;
393 if (drop)
394 continue;
395
396 for (c = 0; c < chunk; c++) {
397 int sysrq;
398
399 uport->icount.rx++;
400 if (port->brk && buf[c] == 0) {
401 port->brk = false;
402 if (uart_handle_break(uport))
403 continue;
404 }
405
406 sysrq = uart_handle_sysrq_char(uport, buf[c]);
407 if (!sysrq)
408 tty_insert_flip_char(tport, buf[c], TTY_NORMAL);
409 }
410 }
411 if (!drop)
412 tty_flip_buffer_push(tport);
413 return 0;
414}
415#else
416static int handle_rx_console(struct uart_port *uport, u32 bytes, bool drop)
417{
418 return -EPERM;
419}
420
421#endif /* CONFIG_SERIAL_QCOM_GENI_CONSOLE */
422
423static void qcom_geni_serial_start_tx(struct uart_port *uport)
424{
425 u32 irq_en;
426 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
427 u32 status;
428
429 if (port->xfer_mode == GENI_SE_FIFO) {
7fb5b880
KR		 430 /*
431 * readl ensures reading & writing of IRQ_EN register
432 * is not re-ordered before checking the status of the
433 * Serial Engine.
434 */
435 status = readl(uport->membase + SE_GENI_STATUS);
c4f52879
KR		 436 if (status & M_GENI_CMD_ACTIVE)
437 return;
438
439 if (!qcom_geni_serial_tx_empty(uport))
440 return;
441
c4f52879
KR		 442 irq_en = readl_relaxed(uport->membase + SE_GENI_M_IRQ_EN);
443 irq_en |= M_TX_FIFO_WATERMARK_EN | M_CMD_DONE_EN;
444
445 writel_relaxed(port->tx_wm, uport->membase +
446 SE_GENI_TX_WATERMARK_REG);
447 writel_relaxed(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
448 }
449}
450
451static void qcom_geni_serial_stop_tx(struct uart_port *uport)
452{
453 u32 irq_en;
454 u32 status;
455 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
456
457 irq_en = readl_relaxed(uport->membase + SE_GENI_M_IRQ_EN);
458 irq_en &= ~M_CMD_DONE_EN;
459 if (port->xfer_mode == GENI_SE_FIFO) {
460 irq_en &= ~M_TX_FIFO_WATERMARK_EN;
461 writel_relaxed(0, uport->membase +
462 SE_GENI_TX_WATERMARK_REG);
463 }
c4f52879
KR		 464 writel_relaxed(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
465 status = readl_relaxed(uport->membase + SE_GENI_STATUS);
466 /* Possible stop tx is called multiple times. */
467 if (!(status & M_GENI_CMD_ACTIVE))
468 return;
469
470 /*
471 * Ensure cancel command write is not re-ordered before checking
472 * the status of the Primary Sequencer.
473 */
474 mb();
475
476 geni_se_cancel_m_cmd(&port->se);
477 if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
478 M_CMD_CANCEL_EN, true)) {
479 geni_se_abort_m_cmd(&port->se);
480 qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
481 M_CMD_ABORT_EN, true);
482 writel_relaxed(M_CMD_ABORT_EN, uport->membase +
483 SE_GENI_M_IRQ_CLEAR);
484 }
485 writel_relaxed(M_CMD_CANCEL_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
486}
487
488static void qcom_geni_serial_start_rx(struct uart_port *uport)
489{
490 u32 irq_en;
491 u32 status;
492 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
493
494 status = readl_relaxed(uport->membase + SE_GENI_STATUS);
495 if (status & S_GENI_CMD_ACTIVE)
496 qcom_geni_serial_stop_rx(uport);
497
498 /*
499 * Ensure setup command write is not re-ordered before checking
500 * the status of the Secondary Sequencer.
501 */
502 mb();
503
504 geni_se_setup_s_cmd(&port->se, UART_START_READ, 0);
505
506 if (port->xfer_mode == GENI_SE_FIFO) {
507 irq_en = readl_relaxed(uport->membase + SE_GENI_S_IRQ_EN);
508 irq_en |= S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN;
509 writel_relaxed(irq_en, uport->membase + SE_GENI_S_IRQ_EN);
510
511 irq_en = readl_relaxed(uport->membase + SE_GENI_M_IRQ_EN);
512 irq_en |= M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN;
513 writel_relaxed(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
514 }
515}
516
517static void qcom_geni_serial_stop_rx(struct uart_port *uport)
518{
519 u32 irq_en;
520 u32 status;
521 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
522 u32 irq_clear = S_CMD_DONE_EN;
523
524 if (port->xfer_mode == GENI_SE_FIFO) {
525 irq_en = readl_relaxed(uport->membase + SE_GENI_S_IRQ_EN);
526 irq_en &= ~(S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN);
527 writel_relaxed(irq_en, uport->membase + SE_GENI_S_IRQ_EN);
528
529 irq_en = readl_relaxed(uport->membase + SE_GENI_M_IRQ_EN);
530 irq_en &= ~(M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN);
531 writel_relaxed(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
532 }
533
534 status = readl_relaxed(uport->membase + SE_GENI_STATUS);
535 /* Possible stop rx is called multiple times. */
536 if (!(status & S_GENI_CMD_ACTIVE))
537 return;
538
539 /*
540 * Ensure cancel command write is not re-ordered before checking
541 * the status of the Secondary Sequencer.
542 */
543 mb();
544
545 geni_se_cancel_s_cmd(&port->se);
546 qcom_geni_serial_poll_bit(uport, SE_GENI_S_CMD_CTRL_REG,
547 S_GENI_CMD_CANCEL, false);
548 status = readl_relaxed(uport->membase + SE_GENI_STATUS);
549 writel_relaxed(irq_clear, uport->membase + SE_GENI_S_IRQ_CLEAR);
550 if (status & S_GENI_CMD_ACTIVE)
551 qcom_geni_serial_abort_rx(uport);
552}
553
554static void qcom_geni_serial_handle_rx(struct uart_port *uport, bool drop)
555{
556 u32 status;
557 u32 word_cnt;
558 u32 last_word_byte_cnt;
559 u32 last_word_partial;
560 u32 total_bytes;
561 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
562
563 status = readl_relaxed(uport->membase + SE_GENI_RX_FIFO_STATUS);
564 word_cnt = status & RX_FIFO_WC_MSK;
565 last_word_partial = status & RX_LAST;
566 last_word_byte_cnt = (status & RX_LAST_BYTE_VALID_MSK) >>
567 RX_LAST_BYTE_VALID_SHFT;
568
569 if (!word_cnt)
570 return;
571 total_bytes = port->rx_bytes_pw * (word_cnt - 1);
572 if (last_word_partial && last_word_byte_cnt)
573 total_bytes += last_word_byte_cnt;
574 else
575 total_bytes += port->rx_bytes_pw;
576 port->handle_rx(uport, total_bytes, drop);
577}
578
579static void qcom_geni_serial_handle_tx(struct uart_port *uport)
580{
581 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
582 struct circ_buf *xmit = &uport->state->xmit;
583 size_t avail;
584 size_t remaining;
585 int i;
586 u32 status;
587 unsigned int chunk;
588 int tail;
589
590 chunk = uart_circ_chars_pending(xmit);
591 status = readl_relaxed(uport->membase + SE_GENI_TX_FIFO_STATUS);
592 /* Both FIFO and framework buffer are drained */
638a6f4e 593 if (!chunk && !status) {
c4f52879
KR		 594 qcom_geni_serial_stop_tx(uport);
595 goto out_write_wakeup;
596 }
c4f52879
KR		 597
598 avail = (port->tx_fifo_depth - port->tx_wm) * port->tx_bytes_pw;
638a6f4e 599 tail = xmit->tail;
8e70c47c 600 chunk = min3((size_t)chunk, (size_t)(UART_XMIT_SIZE - tail), avail);
c4f52879
KR		 601 if (!chunk)
602 goto out_write_wakeup;
603
604 qcom_geni_serial_setup_tx(uport, chunk);
605
606 remaining = chunk;
607 for (i = 0; i < chunk; ) {
608 unsigned int tx_bytes;
69736b57 609 u8 buf[sizeof(u32)];
c4f52879
KR		 610 int c;
611
69736b57 612 memset(buf, 0, ARRAY_SIZE(buf));
6a10635e 613 tx_bytes = min_t(size_t, remaining, port->tx_bytes_pw);
c4f52879 614 for (c = 0; c < tx_bytes ; c++)
69736b57 615 buf[c] = xmit->buf[tail + c];
c4f52879 616
69736b57 617 iowrite32_rep(uport->membase + SE_GENI_TX_FIFOn, buf, 1);
c4f52879
KR		 618
619 i += tx_bytes;
638a6f4e 620 tail += tx_bytes;
c4f52879
KR		 621 uport->icount.tx += tx_bytes;
622 remaining -= tx_bytes;
623 }
638a6f4e
EG		 624
625 xmit->tail = tail & (UART_XMIT_SIZE - 1);
c4f52879 626 qcom_geni_serial_poll_tx_done(uport);
c4f52879 627out_write_wakeup:
638a6f4e
EG		 628 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
629 uart_write_wakeup(uport);
c4f52879
KR		 630}
631
632static irqreturn_t qcom_geni_serial_isr(int isr, void *dev)
633{
634 unsigned int m_irq_status;
635 unsigned int s_irq_status;
636 struct uart_port *uport = dev;
637 unsigned long flags;
638 unsigned int m_irq_en;
639 bool drop_rx = false;
640 struct tty_port *tport = &uport->state->port;
641 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
642
643 if (uport->suspended)
ec91df8d 644 return IRQ_NONE;
c4f52879
KR		 645
646 spin_lock_irqsave(&uport->lock, flags);
647 m_irq_status = readl_relaxed(uport->membase + SE_GENI_M_IRQ_STATUS);
648 s_irq_status = readl_relaxed(uport->membase + SE_GENI_S_IRQ_STATUS);
649 m_irq_en = readl_relaxed(uport->membase + SE_GENI_M_IRQ_EN);
650 writel_relaxed(m_irq_status, uport->membase + SE_GENI_M_IRQ_CLEAR);
651 writel_relaxed(s_irq_status, uport->membase + SE_GENI_S_IRQ_CLEAR);
652
653 if (WARN_ON(m_irq_status & M_ILLEGAL_CMD_EN))
654 goto out_unlock;
655
656 if (s_irq_status & S_RX_FIFO_WR_ERR_EN) {
657 uport->icount.overrun++;
658 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
659 }
660
661 if (m_irq_status & (M_TX_FIFO_WATERMARK_EN | M_CMD_DONE_EN) &&
662 m_irq_en & (M_TX_FIFO_WATERMARK_EN | M_CMD_DONE_EN))
663 qcom_geni_serial_handle_tx(uport);
664
665 if (s_irq_status & S_GP_IRQ_0_EN || s_irq_status & S_GP_IRQ_1_EN) {
666 if (s_irq_status & S_GP_IRQ_0_EN)
667 uport->icount.parity++;
668 drop_rx = true;
669 } else if (s_irq_status & S_GP_IRQ_2_EN ||
670 s_irq_status & S_GP_IRQ_3_EN) {
671 uport->icount.brk++;
672 port->brk = true;
673 }
674
675 if (s_irq_status & S_RX_FIFO_WATERMARK_EN ||
676 s_irq_status & S_RX_FIFO_LAST_EN)
677 qcom_geni_serial_handle_rx(uport, drop_rx);
678
679out_unlock:
680 spin_unlock_irqrestore(&uport->lock, flags);
681 return IRQ_HANDLED;
682}
683
6a10635e 684static void get_tx_fifo_size(struct qcom_geni_serial_port *port)
c4f52879
KR		 685{
686 struct uart_port *uport;
687
c4f52879
KR		 688 uport = &port->uport;
689 port->tx_fifo_depth = geni_se_get_tx_fifo_depth(&port->se);
690 port->tx_fifo_width = geni_se_get_tx_fifo_width(&port->se);
691 port->rx_fifo_depth = geni_se_get_rx_fifo_depth(&port->se);
692 uport->fifosize =
693 (port->tx_fifo_depth * port->tx_fifo_width) / BITS_PER_BYTE;
c4f52879
KR		 694}
695
696static void set_rfr_wm(struct qcom_geni_serial_port *port)
697{
698 /*
699 * Set RFR (Flow off) to FIFO_DEPTH - 2.
700 * RX WM level at 10% RX_FIFO_DEPTH.
701 * TX WM level at 10% TX_FIFO_DEPTH.
702 */
703 port->rx_rfr = port->rx_fifo_depth - 2;
704 port->rx_wm = UART_CONSOLE_RX_WM;
705 port->tx_wm = DEF_TX_WM;
706}
707
708static void qcom_geni_serial_shutdown(struct uart_port *uport)
709{
710 unsigned long flags;
711
712 /* Stop the console before stopping the current tx */
713 console_stop(uport->cons);
714
c4f52879
KR		 715 free_irq(uport->irq, uport);
716 spin_lock_irqsave(&uport->lock, flags);
717 qcom_geni_serial_stop_tx(uport);
718 qcom_geni_serial_stop_rx(uport);
719 spin_unlock_irqrestore(&uport->lock, flags);
720}
721
722static int qcom_geni_serial_port_setup(struct uart_port *uport)
723{
724 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
725 unsigned int rxstale = DEFAULT_BITS_PER_CHAR * STALE_TIMEOUT;
726
727 set_rfr_wm(port);
728 writel_relaxed(rxstale, uport->membase + SE_UART_RX_STALE_CNT);
729 /*
730 * Make an unconditional cancel on the main sequencer to reset
731 * it else we could end up in data loss scenarios.
732 */
733 port->xfer_mode = GENI_SE_FIFO;
734 qcom_geni_serial_poll_tx_done(uport);
735 geni_se_config_packing(&port->se, BITS_PER_BYTE, port->tx_bytes_pw,
736 false, true, false);
737 geni_se_config_packing(&port->se, BITS_PER_BYTE, port->rx_bytes_pw,
738 false, false, true);
739 geni_se_init(&port->se, port->rx_wm, port->rx_rfr);
740 geni_se_select_mode(&port->se, port->xfer_mode);
741 port->setup = true;
742 return 0;
743}
744
745static int qcom_geni_serial_startup(struct uart_port *uport)
746{
747 int ret;
748 u32 proto;
749 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
750
751 scnprintf(port->name, sizeof(port->name),
752 "qcom_serial_geni%d", uport->line);
753
754 proto = geni_se_read_proto(&port->se);
755 if (proto != GENI_SE_UART) {
756 dev_err(uport->dev, "Invalid FW loaded, proto: %d\n", proto);
757 return -ENXIO;
758 }
759
760 get_tx_fifo_size(port);
761 if (!port->setup) {
762 ret = qcom_geni_serial_port_setup(uport);
763 if (ret)
764 return ret;
765 }
766
767 ret = request_irq(uport->irq, qcom_geni_serial_isr, IRQF_TRIGGER_HIGH,
768 port->name, uport);
769 if (ret)
770 dev_err(uport->dev, "Failed to get IRQ ret %d\n", ret);
771 return ret;
772}
773
774static unsigned long get_clk_cfg(unsigned long clk_freq)
775{
776 int i;
777
778 for (i = 0; i < ARRAY_SIZE(root_freq); i++) {
779 if (!(root_freq[i] % clk_freq))
780 return root_freq[i];
781 }
782 return 0;
783}
784
785static unsigned long get_clk_div_rate(unsigned int baud, unsigned int *clk_div)
786{
787 unsigned long ser_clk;
788 unsigned long desired_clk;
789
790 desired_clk = baud * UART_OVERSAMPLING;
791 ser_clk = get_clk_cfg(desired_clk);
792 if (!ser_clk) {
793 pr_err("%s: Can't find matching DFS entry for baud %d\n",
794 __func__, baud);
795 return ser_clk;
796 }
797
798 *clk_div = ser_clk / desired_clk;
799 return ser_clk;
800}
801
802static void qcom_geni_serial_set_termios(struct uart_port *uport,
803 struct ktermios *termios, struct ktermios *old)
804{
805 unsigned int baud;
806 unsigned int bits_per_char;
807 unsigned int tx_trans_cfg;
808 unsigned int tx_parity_cfg;
809 unsigned int rx_trans_cfg;
810 unsigned int rx_parity_cfg;
811 unsigned int stop_bit_len;
812 unsigned int clk_div;
813 unsigned long ser_clk_cfg;
814 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
815 unsigned long clk_rate;
816
817 qcom_geni_serial_stop_rx(uport);
818 /* baud rate */
819 baud = uart_get_baud_rate(uport, termios, old, 300, 4000000);
820 port->baud = baud;
821 clk_rate = get_clk_div_rate(baud, &clk_div);
822 if (!clk_rate)
823 goto out_restart_rx;
824
825 uport->uartclk = clk_rate;
826 clk_set_rate(port->se.clk, clk_rate);
827 ser_clk_cfg = SER_CLK_EN;
828 ser_clk_cfg |= clk_div << CLK_DIV_SHFT;
829
830 /* parity */
831 tx_trans_cfg = readl_relaxed(uport->membase + SE_UART_TX_TRANS_CFG);
832 tx_parity_cfg = readl_relaxed(uport->membase + SE_UART_TX_PARITY_CFG);
833 rx_trans_cfg = readl_relaxed(uport->membase + SE_UART_RX_TRANS_CFG);
834 rx_parity_cfg = readl_relaxed(uport->membase + SE_UART_RX_PARITY_CFG);
835 if (termios->c_cflag & PARENB) {
836 tx_trans_cfg |= UART_TX_PAR_EN;
837 rx_trans_cfg |= UART_RX_PAR_EN;
838 tx_parity_cfg |= PAR_CALC_EN;
839 rx_parity_cfg |= PAR_CALC_EN;
840 if (termios->c_cflag & PARODD) {
841 tx_parity_cfg |= PAR_ODD;
842 rx_parity_cfg |= PAR_ODD;
843 } else if (termios->c_cflag & CMSPAR) {
844 tx_parity_cfg |= PAR_SPACE;
845 rx_parity_cfg |= PAR_SPACE;
846 } else {
847 tx_parity_cfg |= PAR_EVEN;
848 rx_parity_cfg |= PAR_EVEN;
849 }
850 } else {
851 tx_trans_cfg &= ~UART_TX_PAR_EN;
852 rx_trans_cfg &= ~UART_RX_PAR_EN;
853 tx_parity_cfg &= ~PAR_CALC_EN;
854 rx_parity_cfg &= ~PAR_CALC_EN;
855 }
856
857 /* bits per char */
858 switch (termios->c_cflag & CSIZE) {
859 case CS5:
860 bits_per_char = 5;
861 break;
862 case CS6:
863 bits_per_char = 6;
864 break;
865 case CS7:
866 bits_per_char = 7;
867 break;
868 case CS8:
869 default:
870 bits_per_char = 8;
871 break;
872 }
873
874 /* stop bits */
875 if (termios->c_cflag & CSTOPB)
876 stop_bit_len = TX_STOP_BIT_LEN_2;
877 else
878 stop_bit_len = TX_STOP_BIT_LEN_1;
879
880 /* flow control, clear the CTS_MASK bit if using flow control. */
881 if (termios->c_cflag & CRTSCTS)
882 tx_trans_cfg &= ~UART_CTS_MASK;
883 else
884 tx_trans_cfg |= UART_CTS_MASK;
885
886 if (baud)
887 uart_update_timeout(uport, termios->c_cflag, baud);
888
889 writel_relaxed(tx_trans_cfg, uport->membase + SE_UART_TX_TRANS_CFG);
890 writel_relaxed(tx_parity_cfg, uport->membase + SE_UART_TX_PARITY_CFG);
891 writel_relaxed(rx_trans_cfg, uport->membase + SE_UART_RX_TRANS_CFG);
892 writel_relaxed(rx_parity_cfg, uport->membase + SE_UART_RX_PARITY_CFG);
893 writel_relaxed(bits_per_char, uport->membase + SE_UART_TX_WORD_LEN);
894 writel_relaxed(bits_per_char, uport->membase + SE_UART_RX_WORD_LEN);
895 writel_relaxed(stop_bit_len, uport->membase + SE_UART_TX_STOP_BIT_LEN);
896 writel_relaxed(ser_clk_cfg, uport->membase + GENI_SER_M_CLK_CFG);
897 writel_relaxed(ser_clk_cfg, uport->membase + GENI_SER_S_CLK_CFG);
898out_restart_rx:
899 qcom_geni_serial_start_rx(uport);
900}
901
902static unsigned int qcom_geni_serial_tx_empty(struct uart_port *uport)
903{
7fb5b880 904 return !readl(uport->membase + SE_GENI_TX_FIFO_STATUS);
c4f52879
KR		 905}
906
907#ifdef CONFIG_SERIAL_QCOM_GENI_CONSOLE
908static int __init qcom_geni_console_setup(struct console *co, char *options)
909{
910 struct uart_port *uport;
911 struct qcom_geni_serial_port *port;
912 int baud;
913 int bits = 8;
914 int parity = 'n';
915 int flow = 'n';
916
917 if (co->index >= GENI_UART_CONS_PORTS || co->index < 0)
918 return -ENXIO;
919
920 port = get_port_from_line(co->index);
921 if (IS_ERR(port)) {
6a10635e 922 pr_err("Invalid line %d\n", co->index);
c4f52879
KR		 923 return PTR_ERR(port);
924 }
925
926 uport = &port->uport;
927
928 if (unlikely(!uport->membase))
929 return -ENXIO;
930
931 if (geni_se_resources_on(&port->se)) {
932 dev_err(port->se.dev, "Error turning on resources\n");
933 return -ENXIO;
934 }
935
936 if (unlikely(geni_se_read_proto(&port->se) != GENI_SE_UART)) {
937 geni_se_resources_off(&port->se);
938 return -ENXIO;
939 }
940
941 if (!port->setup) {
942 port->tx_bytes_pw = 1;
943 port->rx_bytes_pw = RX_BYTES_PW;
944 qcom_geni_serial_stop_rx(uport);
945 qcom_geni_serial_port_setup(uport);
946 }
947
948 if (options)
949 uart_parse_options(options, &baud, &parity, &bits, &flow);
950
951 return uart_set_options(uport, co, baud, parity, bits, flow);
952}
953
43f1831b
KR		 954static void qcom_geni_serial_earlycon_write(struct console *con,
955 const char *s, unsigned int n)
956{
957 struct earlycon_device *dev = con->data;
958
959 __qcom_geni_serial_console_write(&dev->port, s, n);
960}
961
962static int __init qcom_geni_serial_earlycon_setup(struct earlycon_device *dev,
963 const char *opt)
964{
965 struct uart_port *uport = &dev->port;
966 u32 tx_trans_cfg;
967 u32 tx_parity_cfg = 0; /* Disable Tx Parity */
968 u32 rx_trans_cfg = 0;
969 u32 rx_parity_cfg = 0; /* Disable Rx Parity */
970 u32 stop_bit_len = 0; /* Default stop bit length - 1 bit */
971 u32 bits_per_char;
972 struct geni_se se;
973
974 if (!uport->membase)
975 return -EINVAL;
976
977 memset(&se, 0, sizeof(se));
978 se.base = uport->membase;
979 if (geni_se_read_proto(&se) != GENI_SE_UART)
980 return -ENXIO;
981 /*
982 * Ignore Flow control.
983 * n = 8.
984 */
985 tx_trans_cfg = UART_CTS_MASK;
986 bits_per_char = BITS_PER_BYTE;
987
988 /*
989 * Make an unconditional cancel on the main sequencer to reset
990 * it else we could end up in data loss scenarios.
991 */
992 qcom_geni_serial_poll_tx_done(uport);
993 qcom_geni_serial_abort_rx(uport);
994 geni_se_config_packing(&se, BITS_PER_BYTE, 1, false, true, false);
995 geni_se_init(&se, DEF_FIFO_DEPTH_WORDS / 2, DEF_FIFO_DEPTH_WORDS - 2);
996 geni_se_select_mode(&se, GENI_SE_FIFO);
997
998 writel_relaxed(tx_trans_cfg, uport->membase + SE_UART_TX_TRANS_CFG);
999 writel_relaxed(tx_parity_cfg, uport->membase + SE_UART_TX_PARITY_CFG);
1000 writel_relaxed(rx_trans_cfg, uport->membase + SE_UART_RX_TRANS_CFG);
1001 writel_relaxed(rx_parity_cfg, uport->membase + SE_UART_RX_PARITY_CFG);
1002 writel_relaxed(bits_per_char, uport->membase + SE_UART_TX_WORD_LEN);
1003 writel_relaxed(bits_per_char, uport->membase + SE_UART_RX_WORD_LEN);
1004 writel_relaxed(stop_bit_len, uport->membase + SE_UART_TX_STOP_BIT_LEN);
1005
1006 dev->con->write = qcom_geni_serial_earlycon_write;
1007 dev->con->setup = NULL;
1008 return 0;
1009}
1010OF_EARLYCON_DECLARE(qcom_geni, "qcom,geni-debug-uart",
1011 qcom_geni_serial_earlycon_setup);
1012
c4f52879
KR		 1013static int __init console_register(struct uart_driver *drv)
1014{
1015 return uart_register_driver(drv);
1016}
1017
1018static void console_unregister(struct uart_driver *drv)
1019{
1020 uart_unregister_driver(drv);
1021}
1022
1023static struct console cons_ops = {
1024 .name = "ttyMSM",
1025 .write = qcom_geni_serial_console_write,
1026 .device = uart_console_device,
1027 .setup = qcom_geni_console_setup,
1028 .flags = CON_PRINTBUFFER,
1029 .index = -1,
1030 .data = &qcom_geni_console_driver,
1031};
1032
1033static struct uart_driver qcom_geni_console_driver = {
1034 .owner = THIS_MODULE,
1035 .driver_name = "qcom_geni_console",
1036 .dev_name = "ttyMSM",
1037 .nr = GENI_UART_CONS_PORTS,
1038 .cons = &cons_ops,
1039};
1040#else
1041static int console_register(struct uart_driver *drv)
1042{
1043 return 0;
1044}
1045
1046static void console_unregister(struct uart_driver *drv)
1047{
1048}
1049#endif /* CONFIG_SERIAL_QCOM_GENI_CONSOLE */
1050
1051static void qcom_geni_serial_cons_pm(struct uart_port *uport,
1052 unsigned int new_state, unsigned int old_state)
1053{
1054 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
1055
1056 if (unlikely(!uart_console(uport)))
1057 return;
1058
1059 if (new_state == UART_PM_STATE_ON && old_state == UART_PM_STATE_OFF)
1060 geni_se_resources_on(&port->se);
1061 else if (new_state == UART_PM_STATE_OFF &&
1062 old_state == UART_PM_STATE_ON)
1063 geni_se_resources_off(&port->se);
1064}
1065
1066static const struct uart_ops qcom_geni_console_pops = {
1067 .tx_empty = qcom_geni_serial_tx_empty,
1068 .stop_tx = qcom_geni_serial_stop_tx,
1069 .start_tx = qcom_geni_serial_start_tx,
1070 .stop_rx = qcom_geni_serial_stop_rx,
1071 .set_termios = qcom_geni_serial_set_termios,
1072 .startup = qcom_geni_serial_startup,
1073 .request_port = qcom_geni_serial_request_port,
1074 .config_port = qcom_geni_serial_config_port,
1075 .shutdown = qcom_geni_serial_shutdown,
1076 .type = qcom_geni_serial_get_type,
1077 .set_mctrl = qcom_geni_cons_set_mctrl,
1078 .get_mctrl = qcom_geni_cons_get_mctrl,
1079#ifdef CONFIG_CONSOLE_POLL
1080 .poll_get_char = qcom_geni_serial_get_char,
1081 .poll_put_char = qcom_geni_serial_poll_put_char,
1082#endif
1083 .pm = qcom_geni_serial_cons_pm,
1084};
1085
1086static int qcom_geni_serial_probe(struct platform_device *pdev)
1087{
1088 int ret = 0;
1089 int line = -1;
1090 struct qcom_geni_serial_port *port;
1091 struct uart_port *uport;
1092 struct resource *res;
066cd1c4 1093 int irq;
c4f52879
KR		 1094
1095 if (pdev->dev.of_node)
1096 line = of_alias_get_id(pdev->dev.of_node, "serial");
c4f52879
KR		 1097
1098 if (line < 0 || line >= GENI_UART_CONS_PORTS)
1099 return -ENXIO;
1100 port = get_port_from_line(line);
1101 if (IS_ERR(port)) {
6a10635e
KR		 1102 dev_err(&pdev->dev, "Invalid line %d\n", line);
1103 return PTR_ERR(port);
c4f52879
KR		 1104 }
1105
1106 uport = &port->uport;
1107 /* Don't allow 2 drivers to access the same port */
1108 if (uport->private_data)
1109 return -ENODEV;
1110
1111 uport->dev = &pdev->dev;
1112 port->se.dev = &pdev->dev;
1113 port->se.wrapper = dev_get_drvdata(pdev->dev.parent);
1114 port->se.clk = devm_clk_get(&pdev->dev, "se");
1115 if (IS_ERR(port->se.clk)) {
1116 ret = PTR_ERR(port->se.clk);
1117 dev_err(&pdev->dev, "Err getting SE Core clk %d\n", ret);
1118 return ret;
1119 }
1120
1121 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
7693b331
WY		 1122 if (!res)
1123 return -EINVAL;
c4f52879
KR		 1124 uport->mapbase = res->start;
1125
1126 port->tx_fifo_depth = DEF_FIFO_DEPTH_WORDS;
1127 port->rx_fifo_depth = DEF_FIFO_DEPTH_WORDS;
1128 port->tx_fifo_width = DEF_FIFO_WIDTH_BITS;
1129
066cd1c4
KR		 1130 irq = platform_get_irq(pdev, 0);
1131 if (irq < 0) {
1132 dev_err(&pdev->dev, "Failed to get IRQ %d\n", irq);
1133 return irq;
c4f52879 1134 }
066cd1c4 1135 uport->irq = irq;
c4f52879
KR		 1136
1137 uport->private_data = &qcom_geni_console_driver;
1138 platform_set_drvdata(pdev, port);
1139 port->handle_rx = handle_rx_console;
c4f52879
KR		 1140 return uart_add_one_port(&qcom_geni_console_driver, uport);
1141}
1142
1143static int qcom_geni_serial_remove(struct platform_device *pdev)
1144{
1145 struct qcom_geni_serial_port *port = platform_get_drvdata(pdev);
1146 struct uart_driver *drv = port->uport.private_data;
1147
1148 uart_remove_one_port(drv, &port->uport);
1149 return 0;
1150}
1151
1152static int __maybe_unused qcom_geni_serial_sys_suspend_noirq(struct device *dev)
1153{
a406c4b8 1154 struct qcom_geni_serial_port *port = dev_get_drvdata(dev);
c4f52879
KR		 1155 struct uart_port *uport = &port->uport;
1156
1157 uart_suspend_port(uport->private_data, uport);
1158 return 0;
1159}
1160
1161static int __maybe_unused qcom_geni_serial_sys_resume_noirq(struct device *dev)
1162{
a406c4b8 1163 struct qcom_geni_serial_port *port = dev_get_drvdata(dev);
c4f52879
KR		 1164 struct uart_port *uport = &port->uport;
1165
1166 if (console_suspend_enabled && uport->suspended) {
1167 uart_resume_port(uport->private_data, uport);
f0262568
KR		 1168 /*
1169 * uart_suspend_port() invokes port shutdown which in turn
1170 * frees the irq. uart_resume_port invokes port startup which
1171 * performs request_irq. The request_irq auto-enables the IRQ.
1172 * In addition, resume_noirq implicitly enables the IRQ and
1173 * leads to an unbalanced IRQ enable warning. Disable the IRQ
1174 * before returning so that the warning is suppressed.
1175 */
c4f52879
KR		 1176 disable_irq(uport->irq);
1177 }
1178 return 0;
1179}
1180
1181static const struct dev_pm_ops qcom_geni_serial_pm_ops = {
1182 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(qcom_geni_serial_sys_suspend_noirq,
1183 qcom_geni_serial_sys_resume_noirq)
1184};
1185
1186static const struct of_device_id qcom_geni_serial_match_table[] = {
1187 { .compatible = "qcom,geni-debug-uart", },
1188 {}
1189};
1190MODULE_DEVICE_TABLE(of, qcom_geni_serial_match_table);
1191
1192static struct platform_driver qcom_geni_serial_platform_driver = {
1193 .remove = qcom_geni_serial_remove,
1194 .probe = qcom_geni_serial_probe,
1195 .driver = {
1196 .name = "qcom_geni_serial",
1197 .of_match_table = qcom_geni_serial_match_table,
1198 .pm = &qcom_geni_serial_pm_ops,
1199 },
1200};
1201
1202static int __init qcom_geni_serial_init(void)
1203{
1204 int ret;
1205
c4f52879
KR		 1206 ret = console_register(&qcom_geni_console_driver);
1207 if (ret)
1208 return ret;
1209
1210 ret = platform_driver_register(&qcom_geni_serial_platform_driver);
1211 if (ret)
1212 console_unregister(&qcom_geni_console_driver);
1213 return ret;
1214}
1215module_init(qcom_geni_serial_init);
1216
1217static void __exit qcom_geni_serial_exit(void)
1218{
1219 platform_driver_unregister(&qcom_geni_serial_platform_driver);
1220 console_unregister(&qcom_geni_console_driver);
1221}
1222module_exit(qcom_geni_serial_exit);
1223
1224MODULE_DESCRIPTION("Serial driver for GENI based QUP cores");
1225MODULE_LICENSE("GPL v2");
Linux 6.x block layer and io_uring tree(s)