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e3b3d0f5 | 1 | // SPDX-License-Identifier: GPL-2.0+ |
1da177e4 | 2 | /* |
1da177e4 LT |
3 | * Based on drivers/serial/8250.c by Russell King. |
4 | * | |
5 | * Author: Nicolas Pitre | |
6 | * Created: Feb 20, 2003 | |
7 | * Copyright: (C) 2003 Monta Vista Software, Inc. | |
8 | * | |
1da177e4 LT |
9 | * Note 1: This driver is made separate from the already too overloaded |
10 | * 8250.c because it needs some kirks of its own and that'll make it | |
11 | * easier to add DMA support. | |
12 | * | |
13 | * Note 2: I'm too sick of device allocation policies for serial ports. | |
14 | * If someone else wants to request an "official" allocation of major/minor | |
15 | * for this driver please be my guest. And don't forget that new hardware | |
16 | * to come from Intel might have more than 3 or 4 of those UARTs. Let's | |
17 | * hope for a better port registration and dynamic device allocation scheme | |
18 | * with the serial core maintainer satisfaction to appear soon. | |
19 | */ | |
20 | ||
1da177e4 | 21 | |
1da177e4 LT |
22 | #include <linux/ioport.h> |
23 | #include <linux/init.h> | |
24 | #include <linux/console.h> | |
25 | #include <linux/sysrq.h> | |
34619de1 | 26 | #include <linux/serial.h> |
1da177e4 LT |
27 | #include <linux/serial_reg.h> |
28 | #include <linux/circ_buf.h> | |
29 | #include <linux/delay.h> | |
30 | #include <linux/interrupt.h> | |
699c20f3 | 31 | #include <linux/of.h> |
d052d1be | 32 | #include <linux/platform_device.h> |
1da177e4 LT |
33 | #include <linux/tty.h> |
34 | #include <linux/tty_flip.h> | |
35 | #include <linux/serial_core.h> | |
b049bd9d | 36 | #include <linux/clk.h> |
290a5589 | 37 | #include <linux/io.h> |
5a0e3ad6 | 38 | #include <linux/slab.h> |
1da177e4 | 39 | |
699c20f3 HZ |
40 | #define PXA_NAME_LEN 8 |
41 | ||
1da177e4 LT |
42 | struct uart_pxa_port { |
43 | struct uart_port port; | |
44 | unsigned char ier; | |
45 | unsigned char lcr; | |
46 | unsigned char mcr; | |
47 | unsigned int lsr_break_flag; | |
b049bd9d | 48 | struct clk *clk; |
699c20f3 | 49 | char name[PXA_NAME_LEN]; |
1da177e4 LT |
50 | }; |
51 | ||
52 | static inline unsigned int serial_in(struct uart_pxa_port *up, int offset) | |
53 | { | |
54 | offset <<= 2; | |
55 | return readl(up->port.membase + offset); | |
56 | } | |
57 | ||
58 | static inline void serial_out(struct uart_pxa_port *up, int offset, int value) | |
59 | { | |
60 | offset <<= 2; | |
61 | writel(value, up->port.membase + offset); | |
62 | } | |
63 | ||
64 | static void serial_pxa_enable_ms(struct uart_port *port) | |
65 | { | |
66 | struct uart_pxa_port *up = (struct uart_pxa_port *)port; | |
67 | ||
68 | up->ier |= UART_IER_MSI; | |
69 | serial_out(up, UART_IER, up->ier); | |
70 | } | |
71 | ||
b129a8cc | 72 | static void serial_pxa_stop_tx(struct uart_port *port) |
1da177e4 LT |
73 | { |
74 | struct uart_pxa_port *up = (struct uart_pxa_port *)port; | |
75 | ||
76 | if (up->ier & UART_IER_THRI) { | |
77 | up->ier &= ~UART_IER_THRI; | |
78 | serial_out(up, UART_IER, up->ier); | |
79 | } | |
80 | } | |
81 | ||
82 | static void serial_pxa_stop_rx(struct uart_port *port) | |
83 | { | |
84 | struct uart_pxa_port *up = (struct uart_pxa_port *)port; | |
85 | ||
86 | up->ier &= ~UART_IER_RLSI; | |
87 | up->port.read_status_mask &= ~UART_LSR_DR; | |
88 | serial_out(up, UART_IER, up->ier); | |
89 | } | |
90 | ||
7d12e780 | 91 | static inline void receive_chars(struct uart_pxa_port *up, int *status) |
1da177e4 | 92 | { |
fd2b55f8 | 93 | u8 ch, flag; |
1da177e4 LT |
94 | int max_count = 256; |
95 | ||
96 | do { | |
e44aabd6 MF |
97 | /* work around Errata #20 according to |
98 | * Intel(R) PXA27x Processor Family | |
99 | * Specification Update (May 2005) | |
100 | * | |
101 | * Step 2 | |
102 | * Disable the Reciever Time Out Interrupt via IER[RTOEI] | |
103 | */ | |
104 | up->ier &= ~UART_IER_RTOIE; | |
105 | serial_out(up, UART_IER, up->ier); | |
106 | ||
1da177e4 LT |
107 | ch = serial_in(up, UART_RX); |
108 | flag = TTY_NORMAL; | |
109 | up->port.icount.rx++; | |
110 | ||
111 | if (unlikely(*status & (UART_LSR_BI | UART_LSR_PE | | |
112 | UART_LSR_FE | UART_LSR_OE))) { | |
113 | /* | |
114 | * For statistics only | |
115 | */ | |
116 | if (*status & UART_LSR_BI) { | |
117 | *status &= ~(UART_LSR_FE | UART_LSR_PE); | |
118 | up->port.icount.brk++; | |
119 | /* | |
120 | * We do the SysRQ and SAK checking | |
121 | * here because otherwise the break | |
122 | * may get masked by ignore_status_mask | |
123 | * or read_status_mask. | |
124 | */ | |
125 | if (uart_handle_break(&up->port)) | |
126 | goto ignore_char; | |
127 | } else if (*status & UART_LSR_PE) | |
128 | up->port.icount.parity++; | |
129 | else if (*status & UART_LSR_FE) | |
130 | up->port.icount.frame++; | |
131 | if (*status & UART_LSR_OE) | |
132 | up->port.icount.overrun++; | |
133 | ||
134 | /* | |
135 | * Mask off conditions which should be ignored. | |
136 | */ | |
137 | *status &= up->port.read_status_mask; | |
138 | ||
139 | #ifdef CONFIG_SERIAL_PXA_CONSOLE | |
140 | if (up->port.line == up->port.cons->index) { | |
141 | /* Recover the break flag from console xmit */ | |
142 | *status |= up->lsr_break_flag; | |
143 | up->lsr_break_flag = 0; | |
144 | } | |
145 | #endif | |
146 | if (*status & UART_LSR_BI) { | |
147 | flag = TTY_BREAK; | |
148 | } else if (*status & UART_LSR_PE) | |
149 | flag = TTY_PARITY; | |
150 | else if (*status & UART_LSR_FE) | |
151 | flag = TTY_FRAME; | |
152 | } | |
05ab3014 | 153 | |
51f7ed07 | 154 | if (uart_prepare_sysrq_char(&up->port, ch)) |
1da177e4 | 155 | goto ignore_char; |
05ab3014 RK |
156 | |
157 | uart_insert_char(&up->port, *status, UART_LSR_OE, ch, flag); | |
158 | ||
1da177e4 LT |
159 | ignore_char: |
160 | *status = serial_in(up, UART_LSR); | |
161 | } while ((*status & UART_LSR_DR) && (max_count-- > 0)); | |
2e124b4a | 162 | tty_flip_buffer_push(&up->port.state->port); |
e44aabd6 MF |
163 | |
164 | /* work around Errata #20 according to | |
165 | * Intel(R) PXA27x Processor Family | |
166 | * Specification Update (May 2005) | |
167 | * | |
168 | * Step 6: | |
169 | * No more data in FIFO: Re-enable RTO interrupt via IER[RTOIE] | |
170 | */ | |
171 | up->ier |= UART_IER_RTOIE; | |
172 | serial_out(up, UART_IER, up->ier); | |
1da177e4 LT |
173 | } |
174 | ||
175 | static void transmit_chars(struct uart_pxa_port *up) | |
176 | { | |
d11cc8c3 | 177 | u8 ch; |
1da177e4 | 178 | |
d11cc8c3 JSS |
179 | uart_port_tx_limited(&up->port, ch, up->port.fifosize / 2, |
180 | true, | |
181 | serial_out(up, UART_TX, ch), | |
182 | ({})); | |
1da177e4 LT |
183 | } |
184 | ||
b129a8cc | 185 | static void serial_pxa_start_tx(struct uart_port *port) |
1da177e4 LT |
186 | { |
187 | struct uart_pxa_port *up = (struct uart_pxa_port *)port; | |
188 | ||
189 | if (!(up->ier & UART_IER_THRI)) { | |
190 | up->ier |= UART_IER_THRI; | |
191 | serial_out(up, UART_IER, up->ier); | |
192 | } | |
193 | } | |
194 | ||
50d1e7d1 | 195 | /* should hold up->port.lock */ |
1da177e4 LT |
196 | static inline void check_modem_status(struct uart_pxa_port *up) |
197 | { | |
198 | int status; | |
199 | ||
200 | status = serial_in(up, UART_MSR); | |
201 | ||
202 | if ((status & UART_MSR_ANY_DELTA) == 0) | |
203 | return; | |
204 | ||
205 | if (status & UART_MSR_TERI) | |
206 | up->port.icount.rng++; | |
207 | if (status & UART_MSR_DDSR) | |
208 | up->port.icount.dsr++; | |
209 | if (status & UART_MSR_DDCD) | |
210 | uart_handle_dcd_change(&up->port, status & UART_MSR_DCD); | |
211 | if (status & UART_MSR_DCTS) | |
212 | uart_handle_cts_change(&up->port, status & UART_MSR_CTS); | |
213 | ||
bdc04e31 | 214 | wake_up_interruptible(&up->port.state->port.delta_msr_wait); |
1da177e4 LT |
215 | } |
216 | ||
217 | /* | |
218 | * This handles the interrupt from one port. | |
219 | */ | |
7d12e780 | 220 | static inline irqreturn_t serial_pxa_irq(int irq, void *dev_id) |
1da177e4 | 221 | { |
c7bec5ab | 222 | struct uart_pxa_port *up = dev_id; |
1da177e4 LT |
223 | unsigned int iir, lsr; |
224 | ||
225 | iir = serial_in(up, UART_IIR); | |
226 | if (iir & UART_IIR_NO_INT) | |
227 | return IRQ_NONE; | |
ae3c3962 | 228 | uart_port_lock(&up->port); |
1da177e4 LT |
229 | lsr = serial_in(up, UART_LSR); |
230 | if (lsr & UART_LSR_DR) | |
7d12e780 | 231 | receive_chars(up, &lsr); |
1da177e4 LT |
232 | check_modem_status(up); |
233 | if (lsr & UART_LSR_THRE) | |
234 | transmit_chars(up); | |
51f7ed07 | 235 | uart_unlock_and_check_sysrq(&up->port); |
1da177e4 LT |
236 | return IRQ_HANDLED; |
237 | } | |
238 | ||
239 | static unsigned int serial_pxa_tx_empty(struct uart_port *port) | |
240 | { | |
241 | struct uart_pxa_port *up = (struct uart_pxa_port *)port; | |
242 | unsigned long flags; | |
243 | unsigned int ret; | |
244 | ||
ae3c3962 | 245 | uart_port_lock_irqsave(&up->port, &flags); |
1da177e4 | 246 | ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0; |
ae3c3962 | 247 | uart_port_unlock_irqrestore(&up->port, flags); |
1da177e4 LT |
248 | |
249 | return ret; | |
250 | } | |
251 | ||
252 | static unsigned int serial_pxa_get_mctrl(struct uart_port *port) | |
253 | { | |
254 | struct uart_pxa_port *up = (struct uart_pxa_port *)port; | |
1da177e4 LT |
255 | unsigned char status; |
256 | unsigned int ret; | |
257 | ||
1da177e4 | 258 | status = serial_in(up, UART_MSR); |
1da177e4 LT |
259 | |
260 | ret = 0; | |
261 | if (status & UART_MSR_DCD) | |
262 | ret |= TIOCM_CAR; | |
263 | if (status & UART_MSR_RI) | |
264 | ret |= TIOCM_RNG; | |
265 | if (status & UART_MSR_DSR) | |
266 | ret |= TIOCM_DSR; | |
267 | if (status & UART_MSR_CTS) | |
268 | ret |= TIOCM_CTS; | |
269 | return ret; | |
270 | } | |
271 | ||
272 | static void serial_pxa_set_mctrl(struct uart_port *port, unsigned int mctrl) | |
273 | { | |
274 | struct uart_pxa_port *up = (struct uart_pxa_port *)port; | |
275 | unsigned char mcr = 0; | |
276 | ||
277 | if (mctrl & TIOCM_RTS) | |
278 | mcr |= UART_MCR_RTS; | |
279 | if (mctrl & TIOCM_DTR) | |
280 | mcr |= UART_MCR_DTR; | |
281 | if (mctrl & TIOCM_OUT1) | |
282 | mcr |= UART_MCR_OUT1; | |
283 | if (mctrl & TIOCM_OUT2) | |
284 | mcr |= UART_MCR_OUT2; | |
285 | if (mctrl & TIOCM_LOOP) | |
286 | mcr |= UART_MCR_LOOP; | |
287 | ||
288 | mcr |= up->mcr; | |
289 | ||
290 | serial_out(up, UART_MCR, mcr); | |
291 | } | |
292 | ||
293 | static void serial_pxa_break_ctl(struct uart_port *port, int break_state) | |
294 | { | |
295 | struct uart_pxa_port *up = (struct uart_pxa_port *)port; | |
296 | unsigned long flags; | |
297 | ||
ae3c3962 | 298 | uart_port_lock_irqsave(&up->port, &flags); |
1da177e4 LT |
299 | if (break_state == -1) |
300 | up->lcr |= UART_LCR_SBC; | |
301 | else | |
302 | up->lcr &= ~UART_LCR_SBC; | |
303 | serial_out(up, UART_LCR, up->lcr); | |
ae3c3962 | 304 | uart_port_unlock_irqrestore(&up->port, flags); |
1da177e4 LT |
305 | } |
306 | ||
1da177e4 LT |
307 | static int serial_pxa_startup(struct uart_port *port) |
308 | { | |
309 | struct uart_pxa_port *up = (struct uart_pxa_port *)port; | |
310 | unsigned long flags; | |
311 | int retval; | |
312 | ||
d9e29649 MR |
313 | if (port->line == 3) /* HWUART */ |
314 | up->mcr |= UART_MCR_AFE; | |
315 | else | |
f02aa3f9 | 316 | up->mcr = 0; |
1da177e4 | 317 | |
b049bd9d RK |
318 | up->port.uartclk = clk_get_rate(up->clk); |
319 | ||
1da177e4 LT |
320 | /* |
321 | * Allocate the IRQ | |
322 | */ | |
323 | retval = request_irq(up->port.irq, serial_pxa_irq, 0, up->name, up); | |
324 | if (retval) | |
325 | return retval; | |
326 | ||
327 | /* | |
328 | * Clear the FIFO buffers and disable them. | |
329 | * (they will be reenabled in set_termios()) | |
330 | */ | |
331 | serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO); | |
332 | serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | | |
333 | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); | |
334 | serial_out(up, UART_FCR, 0); | |
335 | ||
336 | /* | |
337 | * Clear the interrupt registers. | |
338 | */ | |
339 | (void) serial_in(up, UART_LSR); | |
340 | (void) serial_in(up, UART_RX); | |
341 | (void) serial_in(up, UART_IIR); | |
342 | (void) serial_in(up, UART_MSR); | |
343 | ||
344 | /* | |
345 | * Now, initialize the UART | |
346 | */ | |
347 | serial_out(up, UART_LCR, UART_LCR_WLEN8); | |
348 | ||
ae3c3962 | 349 | uart_port_lock_irqsave(&up->port, &flags); |
1da177e4 LT |
350 | up->port.mctrl |= TIOCM_OUT2; |
351 | serial_pxa_set_mctrl(&up->port, up->port.mctrl); | |
ae3c3962 | 352 | uart_port_unlock_irqrestore(&up->port, flags); |
1da177e4 LT |
353 | |
354 | /* | |
355 | * Finally, enable interrupts. Note: Modem status interrupts | |
80f7228b | 356 | * are set via set_termios(), which will be occurring imminently |
1da177e4 LT |
357 | * anyway, so we don't enable them here. |
358 | */ | |
359 | up->ier = UART_IER_RLSI | UART_IER_RDI | UART_IER_RTOIE | UART_IER_UUE; | |
360 | serial_out(up, UART_IER, up->ier); | |
361 | ||
362 | /* | |
363 | * And clear the interrupt registers again for luck. | |
364 | */ | |
365 | (void) serial_in(up, UART_LSR); | |
366 | (void) serial_in(up, UART_RX); | |
367 | (void) serial_in(up, UART_IIR); | |
368 | (void) serial_in(up, UART_MSR); | |
369 | ||
370 | return 0; | |
371 | } | |
372 | ||
373 | static void serial_pxa_shutdown(struct uart_port *port) | |
374 | { | |
375 | struct uart_pxa_port *up = (struct uart_pxa_port *)port; | |
376 | unsigned long flags; | |
377 | ||
378 | free_irq(up->port.irq, up); | |
379 | ||
380 | /* | |
381 | * Disable interrupts from this port | |
382 | */ | |
383 | up->ier = 0; | |
384 | serial_out(up, UART_IER, 0); | |
385 | ||
ae3c3962 | 386 | uart_port_lock_irqsave(&up->port, &flags); |
1da177e4 LT |
387 | up->port.mctrl &= ~TIOCM_OUT2; |
388 | serial_pxa_set_mctrl(&up->port, up->port.mctrl); | |
ae3c3962 | 389 | uart_port_unlock_irqrestore(&up->port, flags); |
1da177e4 LT |
390 | |
391 | /* | |
392 | * Disable break condition and FIFOs | |
393 | */ | |
394 | serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC); | |
395 | serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | | |
396 | UART_FCR_CLEAR_RCVR | | |
397 | UART_FCR_CLEAR_XMIT); | |
398 | serial_out(up, UART_FCR, 0); | |
399 | } | |
400 | ||
401 | static void | |
606d099c | 402 | serial_pxa_set_termios(struct uart_port *port, struct ktermios *termios, |
bec5b814 | 403 | const struct ktermios *old) |
1da177e4 LT |
404 | { |
405 | struct uart_pxa_port *up = (struct uart_pxa_port *)port; | |
406 | unsigned char cval, fcr = 0; | |
407 | unsigned long flags; | |
408 | unsigned int baud, quot; | |
c934878c | 409 | unsigned int dll; |
1da177e4 | 410 | |
988c5bbe | 411 | cval = UART_LCR_WLEN(tty_get_char_size(termios->c_cflag)); |
1da177e4 LT |
412 | |
413 | if (termios->c_cflag & CSTOPB) | |
0a8b80c5 | 414 | cval |= UART_LCR_STOP; |
1da177e4 LT |
415 | if (termios->c_cflag & PARENB) |
416 | cval |= UART_LCR_PARITY; | |
417 | if (!(termios->c_cflag & PARODD)) | |
418 | cval |= UART_LCR_EPAR; | |
419 | ||
420 | /* | |
421 | * Ask the core to calculate the divisor for us. | |
422 | */ | |
423 | baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16); | |
424 | quot = uart_get_divisor(port, baud); | |
425 | ||
426 | if ((up->port.uartclk / quot) < (2400 * 16)) | |
427 | fcr = UART_FCR_ENABLE_FIFO | UART_FCR_PXAR1; | |
d9e29649 | 428 | else if ((up->port.uartclk / quot) < (230400 * 16)) |
1da177e4 | 429 | fcr = UART_FCR_ENABLE_FIFO | UART_FCR_PXAR8; |
d9e29649 MR |
430 | else |
431 | fcr = UART_FCR_ENABLE_FIFO | UART_FCR_PXAR32; | |
1da177e4 LT |
432 | |
433 | /* | |
434 | * Ok, we're now changing the port state. Do it with | |
435 | * interrupts disabled. | |
436 | */ | |
ae3c3962 | 437 | uart_port_lock_irqsave(&up->port, &flags); |
1da177e4 LT |
438 | |
439 | /* | |
440 | * Ensure the port will be enabled. | |
441 | * This is required especially for serial console. | |
442 | */ | |
290a5589 | 443 | up->ier |= UART_IER_UUE; |
1da177e4 LT |
444 | |
445 | /* | |
446 | * Update the per-port timeout. | |
447 | */ | |
e6158b4a | 448 | uart_update_timeout(port, termios->c_cflag, baud); |
1da177e4 LT |
449 | |
450 | up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR; | |
451 | if (termios->c_iflag & INPCK) | |
452 | up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE; | |
ef8b9ddc | 453 | if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) |
1da177e4 LT |
454 | up->port.read_status_mask |= UART_LSR_BI; |
455 | ||
456 | /* | |
457 | * Characters to ignore | |
458 | */ | |
459 | up->port.ignore_status_mask = 0; | |
460 | if (termios->c_iflag & IGNPAR) | |
461 | up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE; | |
462 | if (termios->c_iflag & IGNBRK) { | |
463 | up->port.ignore_status_mask |= UART_LSR_BI; | |
464 | /* | |
465 | * If we're ignoring parity and break indicators, | |
466 | * ignore overruns too (for real raw support). | |
467 | */ | |
468 | if (termios->c_iflag & IGNPAR) | |
469 | up->port.ignore_status_mask |= UART_LSR_OE; | |
470 | } | |
471 | ||
472 | /* | |
473 | * ignore all characters if CREAD is not set | |
474 | */ | |
475 | if ((termios->c_cflag & CREAD) == 0) | |
476 | up->port.ignore_status_mask |= UART_LSR_DR; | |
477 | ||
478 | /* | |
479 | * CTS flow control flag and modem status interrupts | |
480 | */ | |
481 | up->ier &= ~UART_IER_MSI; | |
482 | if (UART_ENABLE_MS(&up->port, termios->c_cflag)) | |
483 | up->ier |= UART_IER_MSI; | |
484 | ||
485 | serial_out(up, UART_IER, up->ier); | |
486 | ||
2276f03b RJ |
487 | if (termios->c_cflag & CRTSCTS) |
488 | up->mcr |= UART_MCR_AFE; | |
489 | else | |
490 | up->mcr &= ~UART_MCR_AFE; | |
491 | ||
c934878c | 492 | serial_out(up, UART_LCR, cval | UART_LCR_DLAB); /* set DLAB */ |
1da177e4 | 493 | serial_out(up, UART_DLL, quot & 0xff); /* LS of divisor */ |
c934878c UKK |
494 | |
495 | /* | |
496 | * work around Errata #75 according to Intel(R) PXA27x Processor Family | |
497 | * Specification Update (Nov 2005) | |
498 | */ | |
499 | dll = serial_in(up, UART_DLL); | |
500 | WARN_ON(dll != (quot & 0xff)); | |
501 | ||
1da177e4 | 502 | serial_out(up, UART_DLM, quot >> 8); /* MS of divisor */ |
c934878c | 503 | serial_out(up, UART_LCR, cval); /* reset DLAB */ |
1da177e4 LT |
504 | up->lcr = cval; /* Save LCR */ |
505 | serial_pxa_set_mctrl(&up->port, up->port.mctrl); | |
506 | serial_out(up, UART_FCR, fcr); | |
ae3c3962 | 507 | uart_port_unlock_irqrestore(&up->port, flags); |
1da177e4 LT |
508 | } |
509 | ||
510 | static void | |
511 | serial_pxa_pm(struct uart_port *port, unsigned int state, | |
512 | unsigned int oldstate) | |
513 | { | |
514 | struct uart_pxa_port *up = (struct uart_pxa_port *)port; | |
b049bd9d | 515 | |
1da177e4 | 516 | if (!state) |
fb8ebec0 | 517 | clk_prepare_enable(up->clk); |
b049bd9d | 518 | else |
fb8ebec0 | 519 | clk_disable_unprepare(up->clk); |
1da177e4 LT |
520 | } |
521 | ||
522 | static void serial_pxa_release_port(struct uart_port *port) | |
523 | { | |
524 | } | |
525 | ||
526 | static int serial_pxa_request_port(struct uart_port *port) | |
527 | { | |
528 | return 0; | |
529 | } | |
530 | ||
531 | static void serial_pxa_config_port(struct uart_port *port, int flags) | |
532 | { | |
533 | struct uart_pxa_port *up = (struct uart_pxa_port *)port; | |
534 | up->port.type = PORT_PXA; | |
535 | } | |
536 | ||
537 | static int | |
538 | serial_pxa_verify_port(struct uart_port *port, struct serial_struct *ser) | |
539 | { | |
540 | /* we don't want the core code to modify any port params */ | |
541 | return -EINVAL; | |
542 | } | |
543 | ||
544 | static const char * | |
545 | serial_pxa_type(struct uart_port *port) | |
546 | { | |
547 | struct uart_pxa_port *up = (struct uart_pxa_port *)port; | |
548 | return up->name; | |
549 | } | |
550 | ||
e259a3ae | 551 | static struct uart_pxa_port *serial_pxa_ports[4]; |
2d93486c | 552 | static struct uart_driver serial_pxa_reg; |
1da177e4 | 553 | |
fa7f1518 PZ |
554 | #ifdef CONFIG_SERIAL_PXA_CONSOLE |
555 | ||
1da177e4 LT |
556 | /* |
557 | * Wait for transmitter & holding register to empty | |
558 | */ | |
be9ae5d9 | 559 | static void wait_for_xmitr(struct uart_pxa_port *up) |
1da177e4 LT |
560 | { |
561 | unsigned int status, tmout = 10000; | |
562 | ||
563 | /* Wait up to 10ms for the character(s) to be sent. */ | |
564 | do { | |
565 | status = serial_in(up, UART_LSR); | |
566 | ||
567 | if (status & UART_LSR_BI) | |
568 | up->lsr_break_flag = UART_LSR_BI; | |
569 | ||
570 | if (--tmout == 0) | |
571 | break; | |
572 | udelay(1); | |
34619de1 | 573 | } while (!uart_lsr_tx_empty(status)); |
1da177e4 LT |
574 | |
575 | /* Wait up to 1s for flow control if necessary */ | |
576 | if (up->port.flags & UPF_CONS_FLOW) { | |
577 | tmout = 1000000; | |
578 | while (--tmout && | |
579 | ((serial_in(up, UART_MSR) & UART_MSR_CTS) == 0)) | |
580 | udelay(1); | |
581 | } | |
582 | } | |
583 | ||
3f8bab17 | 584 | static void serial_pxa_console_putchar(struct uart_port *port, unsigned char ch) |
d358788f RK |
585 | { |
586 | struct uart_pxa_port *up = (struct uart_pxa_port *)port; | |
587 | ||
588 | wait_for_xmitr(up); | |
589 | serial_out(up, UART_TX, ch); | |
590 | } | |
591 | ||
1da177e4 LT |
592 | /* |
593 | * Print a string to the serial port trying not to disturb | |
594 | * any possible real use of the port... | |
595 | * | |
596 | * The console_lock must be held when we get here. | |
597 | */ | |
598 | static void | |
599 | serial_pxa_console_write(struct console *co, const char *s, unsigned int count) | |
600 | { | |
e259a3ae | 601 | struct uart_pxa_port *up = serial_pxa_ports[co->index]; |
1da177e4 | 602 | unsigned int ier; |
cfe275c2 CX |
603 | unsigned long flags; |
604 | int locked = 1; | |
1da177e4 | 605 | |
9429ccbf | 606 | clk_enable(up->clk); |
51f7ed07 SAS |
607 | if (oops_in_progress) |
608 | locked = uart_port_trylock_irqsave(&up->port, &flags); | |
cfe275c2 | 609 | else |
51f7ed07 | 610 | uart_port_lock_irqsave(&up->port, &flags); |
cfe275c2 | 611 | |
1da177e4 | 612 | /* |
f02aa3f9 | 613 | * First save the IER then disable the interrupts |
1da177e4 LT |
614 | */ |
615 | ier = serial_in(up, UART_IER); | |
616 | serial_out(up, UART_IER, UART_IER_UUE); | |
617 | ||
d358788f | 618 | uart_console_write(&up->port, s, count, serial_pxa_console_putchar); |
1da177e4 LT |
619 | |
620 | /* | |
621 | * Finally, wait for transmitter to become empty | |
622 | * and restore the IER | |
623 | */ | |
624 | wait_for_xmitr(up); | |
625 | serial_out(up, UART_IER, ier); | |
b049bd9d | 626 | |
cfe275c2 | 627 | if (locked) |
51f7ed07 | 628 | uart_port_unlock_irqrestore(&up->port, flags); |
9429ccbf | 629 | clk_disable(up->clk); |
1da177e4 LT |
630 | } |
631 | ||
e1a9c179 DL |
632 | #ifdef CONFIG_CONSOLE_POLL |
633 | /* | |
634 | * Console polling routines for writing and reading from the uart while | |
635 | * in an interrupt or debug context. | |
636 | */ | |
637 | ||
638 | static int serial_pxa_get_poll_char(struct uart_port *port) | |
639 | { | |
640 | struct uart_pxa_port *up = (struct uart_pxa_port *)port; | |
641 | unsigned char lsr = serial_in(up, UART_LSR); | |
642 | ||
643 | while (!(lsr & UART_LSR_DR)) | |
644 | lsr = serial_in(up, UART_LSR); | |
645 | ||
646 | return serial_in(up, UART_RX); | |
647 | } | |
648 | ||
649 | ||
650 | static void serial_pxa_put_poll_char(struct uart_port *port, | |
651 | unsigned char c) | |
652 | { | |
653 | unsigned int ier; | |
654 | struct uart_pxa_port *up = (struct uart_pxa_port *)port; | |
655 | ||
656 | /* | |
657 | * First save the IER then disable the interrupts | |
658 | */ | |
659 | ier = serial_in(up, UART_IER); | |
660 | serial_out(up, UART_IER, UART_IER_UUE); | |
661 | ||
662 | wait_for_xmitr(up); | |
663 | /* | |
664 | * Send the character out. | |
e1a9c179 DL |
665 | */ |
666 | serial_out(up, UART_TX, c); | |
e1a9c179 DL |
667 | |
668 | /* | |
669 | * Finally, wait for transmitter to become empty | |
670 | * and restore the IER | |
671 | */ | |
672 | wait_for_xmitr(up); | |
673 | serial_out(up, UART_IER, ier); | |
674 | } | |
675 | ||
676 | #endif /* CONFIG_CONSOLE_POLL */ | |
677 | ||
1da177e4 LT |
678 | static int __init |
679 | serial_pxa_console_setup(struct console *co, char *options) | |
680 | { | |
681 | struct uart_pxa_port *up; | |
682 | int baud = 9600; | |
683 | int bits = 8; | |
684 | int parity = 'n'; | |
685 | int flow = 'n'; | |
686 | ||
687 | if (co->index == -1 || co->index >= serial_pxa_reg.nr) | |
688 | co->index = 0; | |
e259a3ae RK |
689 | up = serial_pxa_ports[co->index]; |
690 | if (!up) | |
691 | return -ENODEV; | |
1da177e4 LT |
692 | |
693 | if (options) | |
694 | uart_parse_options(options, &baud, &parity, &bits, &flow); | |
695 | ||
696 | return uart_set_options(&up->port, co, baud, parity, bits, flow); | |
697 | } | |
698 | ||
699 | static struct console serial_pxa_console = { | |
700 | .name = "ttyS", | |
701 | .write = serial_pxa_console_write, | |
702 | .device = uart_console_device, | |
703 | .setup = serial_pxa_console_setup, | |
704 | .flags = CON_PRINTBUFFER, | |
705 | .index = -1, | |
706 | .data = &serial_pxa_reg, | |
707 | }; | |
708 | ||
1da177e4 LT |
709 | #define PXA_CONSOLE &serial_pxa_console |
710 | #else | |
711 | #define PXA_CONSOLE NULL | |
712 | #endif | |
713 | ||
2331e068 | 714 | static const struct uart_ops serial_pxa_pops = { |
1da177e4 LT |
715 | .tx_empty = serial_pxa_tx_empty, |
716 | .set_mctrl = serial_pxa_set_mctrl, | |
717 | .get_mctrl = serial_pxa_get_mctrl, | |
718 | .stop_tx = serial_pxa_stop_tx, | |
719 | .start_tx = serial_pxa_start_tx, | |
720 | .stop_rx = serial_pxa_stop_rx, | |
721 | .enable_ms = serial_pxa_enable_ms, | |
722 | .break_ctl = serial_pxa_break_ctl, | |
723 | .startup = serial_pxa_startup, | |
724 | .shutdown = serial_pxa_shutdown, | |
725 | .set_termios = serial_pxa_set_termios, | |
726 | .pm = serial_pxa_pm, | |
727 | .type = serial_pxa_type, | |
728 | .release_port = serial_pxa_release_port, | |
729 | .request_port = serial_pxa_request_port, | |
730 | .config_port = serial_pxa_config_port, | |
731 | .verify_port = serial_pxa_verify_port, | |
2ee881b7 | 732 | #if defined(CONFIG_CONSOLE_POLL) && defined(CONFIG_SERIAL_PXA_CONSOLE) |
e1a9c179 DL |
733 | .poll_get_char = serial_pxa_get_poll_char, |
734 | .poll_put_char = serial_pxa_put_poll_char, | |
735 | #endif | |
1da177e4 LT |
736 | }; |
737 | ||
1da177e4 LT |
738 | static struct uart_driver serial_pxa_reg = { |
739 | .owner = THIS_MODULE, | |
740 | .driver_name = "PXA serial", | |
1da177e4 LT |
741 | .dev_name = "ttyS", |
742 | .major = TTY_MAJOR, | |
743 | .minor = 64, | |
e259a3ae | 744 | .nr = 4, |
1da177e4 LT |
745 | .cons = PXA_CONSOLE, |
746 | }; | |
747 | ||
bf56c751 MR |
748 | #ifdef CONFIG_PM |
749 | static int serial_pxa_suspend(struct device *dev) | |
1da177e4 | 750 | { |
bf56c751 | 751 | struct uart_pxa_port *sport = dev_get_drvdata(dev); |
1da177e4 | 752 | |
9480e307 | 753 | if (sport) |
1da177e4 LT |
754 | uart_suspend_port(&serial_pxa_reg, &sport->port); |
755 | ||
756 | return 0; | |
757 | } | |
758 | ||
bf56c751 | 759 | static int serial_pxa_resume(struct device *dev) |
1da177e4 | 760 | { |
bf56c751 | 761 | struct uart_pxa_port *sport = dev_get_drvdata(dev); |
1da177e4 | 762 | |
9480e307 | 763 | if (sport) |
1da177e4 LT |
764 | uart_resume_port(&serial_pxa_reg, &sport->port); |
765 | ||
766 | return 0; | |
767 | } | |
768 | ||
47145210 | 769 | static const struct dev_pm_ops serial_pxa_pm_ops = { |
bf56c751 MR |
770 | .suspend = serial_pxa_suspend, |
771 | .resume = serial_pxa_resume, | |
772 | }; | |
773 | #endif | |
774 | ||
ed0bb232 | 775 | static const struct of_device_id serial_pxa_dt_ids[] = { |
699c20f3 HZ |
776 | { .compatible = "mrvl,pxa-uart", }, |
777 | { .compatible = "mrvl,mmp-uart", }, | |
778 | {} | |
779 | }; | |
699c20f3 HZ |
780 | |
781 | static int serial_pxa_probe_dt(struct platform_device *pdev, | |
782 | struct uart_pxa_port *sport) | |
783 | { | |
784 | struct device_node *np = pdev->dev.of_node; | |
785 | int ret; | |
786 | ||
787 | if (!np) | |
788 | return 1; | |
789 | ||
790 | ret = of_alias_get_id(np, "serial"); | |
791 | if (ret < 0) { | |
792 | dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret); | |
793 | return ret; | |
794 | } | |
795 | sport->port.line = ret; | |
796 | return 0; | |
797 | } | |
798 | ||
3ae5eaec | 799 | static int serial_pxa_probe(struct platform_device *dev) |
1da177e4 | 800 | { |
e259a3ae | 801 | struct uart_pxa_port *sport; |
6050efac | 802 | struct resource *mmres; |
e259a3ae | 803 | int ret; |
6050efac | 804 | int irq; |
e259a3ae RK |
805 | |
806 | mmres = platform_get_resource(dev, IORESOURCE_MEM, 0); | |
6050efac | 807 | if (!mmres) |
e259a3ae RK |
808 | return -ENODEV; |
809 | ||
6050efac LP |
810 | irq = platform_get_irq(dev, 0); |
811 | if (irq < 0) | |
812 | return irq; | |
813 | ||
e259a3ae RK |
814 | sport = kzalloc(sizeof(struct uart_pxa_port), GFP_KERNEL); |
815 | if (!sport) | |
816 | return -ENOMEM; | |
817 | ||
e0d8b13a | 818 | sport->clk = clk_get(&dev->dev, NULL); |
b049bd9d RK |
819 | if (IS_ERR(sport->clk)) { |
820 | ret = PTR_ERR(sport->clk); | |
821 | goto err_free; | |
822 | } | |
823 | ||
9429ccbf YZ |
824 | ret = clk_prepare(sport->clk); |
825 | if (ret) { | |
826 | clk_put(sport->clk); | |
827 | goto err_free; | |
828 | } | |
829 | ||
e259a3ae RK |
830 | sport->port.type = PORT_PXA; |
831 | sport->port.iotype = UPIO_MEM; | |
832 | sport->port.mapbase = mmres->start; | |
6050efac | 833 | sport->port.irq = irq; |
e259a3ae RK |
834 | sport->port.fifosize = 64; |
835 | sport->port.ops = &serial_pxa_pops; | |
e259a3ae RK |
836 | sport->port.dev = &dev->dev; |
837 | sport->port.flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF; | |
b049bd9d | 838 | sport->port.uartclk = clk_get_rate(sport->clk); |
31b3bee4 | 839 | sport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_PXA_CONSOLE); |
e259a3ae | 840 | |
699c20f3 HZ |
841 | ret = serial_pxa_probe_dt(dev, sport); |
842 | if (ret > 0) | |
843 | sport->port.line = dev->id; | |
844 | else if (ret < 0) | |
845 | goto err_clk; | |
afc7851f GU |
846 | if (sport->port.line >= ARRAY_SIZE(serial_pxa_ports)) { |
847 | dev_err(&dev->dev, "serial%d out of range\n", sport->port.line); | |
95a0e656 CJ |
848 | ret = -EINVAL; |
849 | goto err_clk; | |
afc7851f | 850 | } |
699c20f3 | 851 | snprintf(sport->name, PXA_NAME_LEN - 1, "UART%d", sport->port.line + 1); |
e259a3ae | 852 | |
28f65c11 | 853 | sport->port.membase = ioremap(mmres->start, resource_size(mmres)); |
e259a3ae RK |
854 | if (!sport->port.membase) { |
855 | ret = -ENOMEM; | |
b049bd9d | 856 | goto err_clk; |
e259a3ae RK |
857 | } |
858 | ||
699c20f3 | 859 | serial_pxa_ports[sport->port.line] = sport; |
e259a3ae RK |
860 | |
861 | uart_add_one_port(&serial_pxa_reg, &sport->port); | |
862 | platform_set_drvdata(dev, sport); | |
863 | ||
1da177e4 | 864 | return 0; |
e259a3ae | 865 | |
b049bd9d | 866 | err_clk: |
9429ccbf | 867 | clk_unprepare(sport->clk); |
b049bd9d | 868 | clk_put(sport->clk); |
e259a3ae RK |
869 | err_free: |
870 | kfree(sport); | |
871 | return ret; | |
1da177e4 LT |
872 | } |
873 | ||
3ae5eaec | 874 | static struct platform_driver serial_pxa_driver = { |
1da177e4 | 875 | .probe = serial_pxa_probe, |
1da177e4 | 876 | |
3ae5eaec RK |
877 | .driver = { |
878 | .name = "pxa2xx-uart", | |
bf56c751 MR |
879 | #ifdef CONFIG_PM |
880 | .pm = &serial_pxa_pm_ops, | |
881 | #endif | |
ca16c5a3 | 882 | .suppress_bind_attrs = true, |
699c20f3 | 883 | .of_match_table = serial_pxa_dt_ids, |
3ae5eaec | 884 | }, |
1da177e4 LT |
885 | }; |
886 | ||
ab28f51c SY |
887 | |
888 | /* 8250 driver for PXA serial ports should be used */ | |
9de4153d | 889 | static int __init serial_pxa_init(void) |
1da177e4 LT |
890 | { |
891 | int ret; | |
892 | ||
893 | ret = uart_register_driver(&serial_pxa_reg); | |
894 | if (ret != 0) | |
895 | return ret; | |
896 | ||
3ae5eaec | 897 | ret = platform_driver_register(&serial_pxa_driver); |
1da177e4 LT |
898 | if (ret != 0) |
899 | uart_unregister_driver(&serial_pxa_reg); | |
900 | ||
901 | return ret; | |
902 | } | |
ca16c5a3 | 903 | device_initcall(serial_pxa_init); |