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Linux 3.3-rc6
[linux-2.6-block.git] / drivers / tty / serial / pxa.c
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1da177e4 1/*
1da177e4
LT		 2 * Based on drivers/serial/8250.c by Russell King.
3 *
4 * Author: Nicolas Pitre
5 * Created: Feb 20, 2003
6 * Copyright: (C) 2003 Monta Vista Software, Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * Note 1: This driver is made separate from the already too overloaded
14 * 8250.c because it needs some kirks of its own and that'll make it
15 * easier to add DMA support.
16 *
17 * Note 2: I'm too sick of device allocation policies for serial ports.
18 * If someone else wants to request an "official" allocation of major/minor
19 * for this driver please be my guest. And don't forget that new hardware
20 * to come from Intel might have more than 3 or 4 of those UARTs. Let's
21 * hope for a better port registration and dynamic device allocation scheme
22 * with the serial core maintainer satisfaction to appear soon.
23 */
24
1da177e4
LT		 25
26#if defined(CONFIG_SERIAL_PXA_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
27#define SUPPORT_SYSRQ
28#endif
29
30#include <linux/module.h>
31#include <linux/ioport.h>
32#include <linux/init.h>
33#include <linux/console.h>
34#include <linux/sysrq.h>
35#include <linux/serial_reg.h>
36#include <linux/circ_buf.h>
37#include <linux/delay.h>
38#include <linux/interrupt.h>
d052d1be 39#include <linux/platform_device.h>
1da177e4
LT		 40#include <linux/tty.h>
41#include <linux/tty_flip.h>
42#include <linux/serial_core.h>
b049bd9d 43#include <linux/clk.h>
290a5589 44#include <linux/io.h>
5a0e3ad6 45#include <linux/slab.h>
1da177e4
LT		 46
47struct uart_pxa_port {
48 struct uart_port port;
49 unsigned char ier;
50 unsigned char lcr;
51 unsigned char mcr;
52 unsigned int lsr_break_flag;
b049bd9d 53 struct clk *clk;
1da177e4
LT		 54 char *name;
55};
56
57static inline unsigned int serial_in(struct uart_pxa_port *up, int offset)
58{
59 offset <<= 2;
60 return readl(up->port.membase + offset);
61}
62
63static inline void serial_out(struct uart_pxa_port *up, int offset, int value)
64{
65 offset <<= 2;
66 writel(value, up->port.membase + offset);
67}
68
69static void serial_pxa_enable_ms(struct uart_port *port)
70{
71 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
72
73 up->ier |= UART_IER_MSI;
74 serial_out(up, UART_IER, up->ier);
75}
76
b129a8cc 77static void serial_pxa_stop_tx(struct uart_port *port)
1da177e4
LT		 78{
79 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
80
81 if (up->ier & UART_IER_THRI) {
82 up->ier &= ~UART_IER_THRI;
83 serial_out(up, UART_IER, up->ier);
84 }
85}
86
87static void serial_pxa_stop_rx(struct uart_port *port)
88{
89 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
90
91 up->ier &= ~UART_IER_RLSI;
92 up->port.read_status_mask &= ~UART_LSR_DR;
93 serial_out(up, UART_IER, up->ier);
94}
95
7d12e780 96static inline void receive_chars(struct uart_pxa_port *up, int *status)
1da177e4 97{
ebd2c8f6 98 struct tty_struct *tty = up->port.state->port.tty;
1da177e4
LT		 99 unsigned int ch, flag;
100 int max_count = 256;
101
102 do {
e44aabd6
MF		 103 /* work around Errata #20 according to
104 * Intel(R) PXA27x Processor Family
105 * Specification Update (May 2005)
106 *
107 * Step 2
108 * Disable the Reciever Time Out Interrupt via IER[RTOEI]
109 */
110 up->ier &= ~UART_IER_RTOIE;
111 serial_out(up, UART_IER, up->ier);
112
1da177e4
LT		 113 ch = serial_in(up, UART_RX);
114 flag = TTY_NORMAL;
115 up->port.icount.rx++;
116
117 if (unlikely(*status & (UART_LSR_BI | UART_LSR_PE |
118 UART_LSR_FE | UART_LSR_OE))) {
119 /*
120 * For statistics only
121 */
122 if (*status & UART_LSR_BI) {
123 *status &= ~(UART_LSR_FE | UART_LSR_PE);
124 up->port.icount.brk++;
125 /*
126 * We do the SysRQ and SAK checking
127 * here because otherwise the break
128 * may get masked by ignore_status_mask
129 * or read_status_mask.
130 */
131 if (uart_handle_break(&up->port))
132 goto ignore_char;
133 } else if (*status & UART_LSR_PE)
134 up->port.icount.parity++;
135 else if (*status & UART_LSR_FE)
136 up->port.icount.frame++;
137 if (*status & UART_LSR_OE)
138 up->port.icount.overrun++;
139
140 /*
141 * Mask off conditions which should be ignored.
142 */
143 *status &= up->port.read_status_mask;
144
145#ifdef CONFIG_SERIAL_PXA_CONSOLE
146 if (up->port.line == up->port.cons->index) {
147 /* Recover the break flag from console xmit */
148 *status |= up->lsr_break_flag;
149 up->lsr_break_flag = 0;
150 }
151#endif
152 if (*status & UART_LSR_BI) {
153 flag = TTY_BREAK;
154 } else if (*status & UART_LSR_PE)
155 flag = TTY_PARITY;
156 else if (*status & UART_LSR_FE)
157 flag = TTY_FRAME;
158 }
05ab3014 159
7d12e780 160 if (uart_handle_sysrq_char(&up->port, ch))
1da177e4 161 goto ignore_char;
05ab3014
RK		 162
163 uart_insert_char(&up->port, *status, UART_LSR_OE, ch, flag);
164
1da177e4
LT		 165 ignore_char:
166 *status = serial_in(up, UART_LSR);
167 } while ((*status & UART_LSR_DR) && (max_count-- > 0));
168 tty_flip_buffer_push(tty);
e44aabd6
MF		 169
170 /* work around Errata #20 according to
171 * Intel(R) PXA27x Processor Family
172 * Specification Update (May 2005)
173 *
174 * Step 6:
175 * No more data in FIFO: Re-enable RTO interrupt via IER[RTOIE]
176 */
177 up->ier |= UART_IER_RTOIE;
178 serial_out(up, UART_IER, up->ier);
1da177e4
LT		 179}
180
181static void transmit_chars(struct uart_pxa_port *up)
182{
ebd2c8f6 183 struct circ_buf *xmit = &up->port.state->xmit;
1da177e4
LT		 184 int count;
185
186 if (up->port.x_char) {
187 serial_out(up, UART_TX, up->port.x_char);
188 up->port.icount.tx++;
189 up->port.x_char = 0;
190 return;
191 }
192 if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
b129a8cc 193 serial_pxa_stop_tx(&up->port);
1da177e4
LT		 194 return;
195 }
196
197 count = up->port.fifosize / 2;
198 do {
199 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
200 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
201 up->port.icount.tx++;
202 if (uart_circ_empty(xmit))
203 break;
204 } while (--count > 0);
205
206 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
207 uart_write_wakeup(&up->port);
208
209
210 if (uart_circ_empty(xmit))
b129a8cc 211 serial_pxa_stop_tx(&up->port);
1da177e4
LT		 212}
213
b129a8cc 214static void serial_pxa_start_tx(struct uart_port *port)
1da177e4
LT		 215{
216 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
217
218 if (!(up->ier & UART_IER_THRI)) {
219 up->ier |= UART_IER_THRI;
220 serial_out(up, UART_IER, up->ier);
221 }
222}
223
224static inline void check_modem_status(struct uart_pxa_port *up)
225{
226 int status;
227
228 status = serial_in(up, UART_MSR);
229
230 if ((status & UART_MSR_ANY_DELTA) == 0)
231 return;
232
233 if (status & UART_MSR_TERI)
234 up->port.icount.rng++;
235 if (status & UART_MSR_DDSR)
236 up->port.icount.dsr++;
237 if (status & UART_MSR_DDCD)
238 uart_handle_dcd_change(&up->port, status & UART_MSR_DCD);
239 if (status & UART_MSR_DCTS)
240 uart_handle_cts_change(&up->port, status & UART_MSR_CTS);
241
bdc04e31 242 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
1da177e4
LT		 243}
244
245/*
246 * This handles the interrupt from one port.
247 */
7d12e780 248static inline irqreturn_t serial_pxa_irq(int irq, void *dev_id)
1da177e4 249{
c7bec5ab 250 struct uart_pxa_port *up = dev_id;
1da177e4
LT		 251 unsigned int iir, lsr;
252
253 iir = serial_in(up, UART_IIR);
254 if (iir & UART_IIR_NO_INT)
255 return IRQ_NONE;
256 lsr = serial_in(up, UART_LSR);
257 if (lsr & UART_LSR_DR)
7d12e780 258 receive_chars(up, &lsr);
1da177e4
LT		 259 check_modem_status(up);
260 if (lsr & UART_LSR_THRE)
261 transmit_chars(up);
262 return IRQ_HANDLED;
263}
264
265static unsigned int serial_pxa_tx_empty(struct uart_port *port)
266{
267 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
268 unsigned long flags;
269 unsigned int ret;
270
271 spin_lock_irqsave(&up->port.lock, flags);
272 ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
273 spin_unlock_irqrestore(&up->port.lock, flags);
274
275 return ret;
276}
277
278static unsigned int serial_pxa_get_mctrl(struct uart_port *port)
279{
280 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
1da177e4
LT		 281 unsigned char status;
282 unsigned int ret;
283
1da177e4 284 status = serial_in(up, UART_MSR);
1da177e4
LT		 285
286 ret = 0;
287 if (status & UART_MSR_DCD)
288 ret |= TIOCM_CAR;
289 if (status & UART_MSR_RI)
290 ret |= TIOCM_RNG;
291 if (status & UART_MSR_DSR)
292 ret |= TIOCM_DSR;
293 if (status & UART_MSR_CTS)
294 ret |= TIOCM_CTS;
295 return ret;
296}
297
298static void serial_pxa_set_mctrl(struct uart_port *port, unsigned int mctrl)
299{
300 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
301 unsigned char mcr = 0;
302
303 if (mctrl & TIOCM_RTS)
304 mcr |= UART_MCR_RTS;
305 if (mctrl & TIOCM_DTR)
306 mcr |= UART_MCR_DTR;
307 if (mctrl & TIOCM_OUT1)
308 mcr |= UART_MCR_OUT1;
309 if (mctrl & TIOCM_OUT2)
310 mcr |= UART_MCR_OUT2;
311 if (mctrl & TIOCM_LOOP)
312 mcr |= UART_MCR_LOOP;
313
314 mcr |= up->mcr;
315
316 serial_out(up, UART_MCR, mcr);
317}
318
319static void serial_pxa_break_ctl(struct uart_port *port, int break_state)
320{
321 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
322 unsigned long flags;
323
324 spin_lock_irqsave(&up->port.lock, flags);
325 if (break_state == -1)
326 up->lcr |= UART_LCR_SBC;
327 else
328 up->lcr &= ~UART_LCR_SBC;
329 serial_out(up, UART_LCR, up->lcr);
330 spin_unlock_irqrestore(&up->port.lock, flags);
331}
332
333#if 0
334static void serial_pxa_dma_init(struct pxa_uart *up)
335{
336 up->rxdma =
337 pxa_request_dma(up->name, DMA_PRIO_LOW, pxa_receive_dma, up);
338 if (up->rxdma < 0)
339 goto out;
340 up->txdma =
341 pxa_request_dma(up->name, DMA_PRIO_LOW, pxa_transmit_dma, up);
342 if (up->txdma < 0)
343 goto err_txdma;
344 up->dmadesc = kmalloc(4 * sizeof(pxa_dma_desc), GFP_KERNEL);
345 if (!up->dmadesc)
346 goto err_alloc;
347
348 /* ... */
349err_alloc:
350 pxa_free_dma(up->txdma);
351err_rxdma:
352 pxa_free_dma(up->rxdma);
353out:
354 return;
355}
356#endif
357
358static int serial_pxa_startup(struct uart_port *port)
359{
360 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
361 unsigned long flags;
362 int retval;
363
d9e29649
MR		 364 if (port->line == 3) /* HWUART */
365 up->mcr |= UART_MCR_AFE;
366 else
f02aa3f9 367 up->mcr = 0;
1da177e4 368
b049bd9d
RK		 369 up->port.uartclk = clk_get_rate(up->clk);
370
1da177e4
LT		 371 /*
372 * Allocate the IRQ
373 */
374 retval = request_irq(up->port.irq, serial_pxa_irq, 0, up->name, up);
375 if (retval)
376 return retval;
377
378 /*
379 * Clear the FIFO buffers and disable them.
380 * (they will be reenabled in set_termios())
381 */
382 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
383 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
384 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
385 serial_out(up, UART_FCR, 0);
386
387 /*
388 * Clear the interrupt registers.
389 */
390 (void) serial_in(up, UART_LSR);
391 (void) serial_in(up, UART_RX);
392 (void) serial_in(up, UART_IIR);
393 (void) serial_in(up, UART_MSR);
394
395 /*
396 * Now, initialize the UART
397 */
398 serial_out(up, UART_LCR, UART_LCR_WLEN8);
399
400 spin_lock_irqsave(&up->port.lock, flags);
401 up->port.mctrl |= TIOCM_OUT2;
402 serial_pxa_set_mctrl(&up->port, up->port.mctrl);
403 spin_unlock_irqrestore(&up->port.lock, flags);
404
405 /*
406 * Finally, enable interrupts. Note: Modem status interrupts
80f7228b 407 * are set via set_termios(), which will be occurring imminently
1da177e4
LT		 408 * anyway, so we don't enable them here.
409 */
410 up->ier = UART_IER_RLSI | UART_IER_RDI | UART_IER_RTOIE | UART_IER_UUE;
411 serial_out(up, UART_IER, up->ier);
412
413 /*
414 * And clear the interrupt registers again for luck.
415 */
416 (void) serial_in(up, UART_LSR);
417 (void) serial_in(up, UART_RX);
418 (void) serial_in(up, UART_IIR);
419 (void) serial_in(up, UART_MSR);
420
421 return 0;
422}
423
424static void serial_pxa_shutdown(struct uart_port *port)
425{
426 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
427 unsigned long flags;
428
429 free_irq(up->port.irq, up);
430
431 /*
432 * Disable interrupts from this port
433 */
434 up->ier = 0;
435 serial_out(up, UART_IER, 0);
436
437 spin_lock_irqsave(&up->port.lock, flags);
438 up->port.mctrl &= ~TIOCM_OUT2;
439 serial_pxa_set_mctrl(&up->port, up->port.mctrl);
440 spin_unlock_irqrestore(&up->port.lock, flags);
441
442 /*
443 * Disable break condition and FIFOs
444 */
445 serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC);
446 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
447 UART_FCR_CLEAR_RCVR |
448 UART_FCR_CLEAR_XMIT);
449 serial_out(up, UART_FCR, 0);
450}
451
452static void
606d099c
AC		 453serial_pxa_set_termios(struct uart_port *port, struct ktermios *termios,
454 struct ktermios *old)
1da177e4
LT		 455{
456 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
457 unsigned char cval, fcr = 0;
458 unsigned long flags;
459 unsigned int baud, quot;
c934878c 460 unsigned int dll;
1da177e4
LT		 461
462 switch (termios->c_cflag & CSIZE) {
463 case CS5:
0a8b80c5 464 cval = UART_LCR_WLEN5;
1da177e4
LT		 465 break;
466 case CS6:
0a8b80c5 467 cval = UART_LCR_WLEN6;
1da177e4
LT		 468 break;
469 case CS7:
0a8b80c5 470 cval = UART_LCR_WLEN7;
1da177e4
LT		 471 break;
472 default:
473 case CS8:
0a8b80c5 474 cval = UART_LCR_WLEN8;
1da177e4
LT		 475 break;
476 }
477
478 if (termios->c_cflag & CSTOPB)
0a8b80c5 479 cval |= UART_LCR_STOP;
1da177e4
LT		 480 if (termios->c_cflag & PARENB)
481 cval |= UART_LCR_PARITY;
482 if (!(termios->c_cflag & PARODD))
483 cval |= UART_LCR_EPAR;
484
485 /*
486 * Ask the core to calculate the divisor for us.
487 */
488 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
489 quot = uart_get_divisor(port, baud);
490
491 if ((up->port.uartclk / quot) < (2400 * 16))
492 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_PXAR1;
d9e29649 493 else if ((up->port.uartclk / quot) < (230400 * 16))
1da177e4 494 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_PXAR8;
d9e29649
MR		 495 else
496 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_PXAR32;
1da177e4
LT		 497
498 /*
499 * Ok, we're now changing the port state. Do it with
500 * interrupts disabled.
501 */
502 spin_lock_irqsave(&up->port.lock, flags);
503
504 /*
505 * Ensure the port will be enabled.
506 * This is required especially for serial console.
507 */
290a5589 508 up->ier |= UART_IER_UUE;
1da177e4
LT		 509
510 /*
511 * Update the per-port timeout.
512 */
e6158b4a 513 uart_update_timeout(port, termios->c_cflag, baud);
1da177e4
LT		 514
515 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
516 if (termios->c_iflag & INPCK)
517 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
518 if (termios->c_iflag & (BRKINT | PARMRK))
519 up->port.read_status_mask |= UART_LSR_BI;
520
521 /*
522 * Characters to ignore
523 */
524 up->port.ignore_status_mask = 0;
525 if (termios->c_iflag & IGNPAR)
526 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
527 if (termios->c_iflag & IGNBRK) {
528 up->port.ignore_status_mask |= UART_LSR_BI;
529 /*
530 * If we're ignoring parity and break indicators,
531 * ignore overruns too (for real raw support).
532 */
533 if (termios->c_iflag & IGNPAR)
534 up->port.ignore_status_mask |= UART_LSR_OE;
535 }
536
537 /*
538 * ignore all characters if CREAD is not set
539 */
540 if ((termios->c_cflag & CREAD) == 0)
541 up->port.ignore_status_mask |= UART_LSR_DR;
542
543 /*
544 * CTS flow control flag and modem status interrupts
545 */
546 up->ier &= ~UART_IER_MSI;
547 if (UART_ENABLE_MS(&up->port, termios->c_cflag))
548 up->ier |= UART_IER_MSI;
549
550 serial_out(up, UART_IER, up->ier);
551
2276f03b
RJ		 552 if (termios->c_cflag & CRTSCTS)
553 up->mcr |= UART_MCR_AFE;
554 else
555 up->mcr &= ~UART_MCR_AFE;
556
c934878c 557 serial_out(up, UART_LCR, cval | UART_LCR_DLAB); /* set DLAB */
1da177e4 558 serial_out(up, UART_DLL, quot & 0xff); /* LS of divisor */
c934878c
UKK		 559
560 /*
561 * work around Errata #75 according to Intel(R) PXA27x Processor Family
562 * Specification Update (Nov 2005)
563 */
564 dll = serial_in(up, UART_DLL);
565 WARN_ON(dll != (quot & 0xff));
566
1da177e4 567 serial_out(up, UART_DLM, quot >> 8); /* MS of divisor */
c934878c 568 serial_out(up, UART_LCR, cval); /* reset DLAB */
1da177e4
LT		 569 up->lcr = cval; /* Save LCR */
570 serial_pxa_set_mctrl(&up->port, up->port.mctrl);
571 serial_out(up, UART_FCR, fcr);
572 spin_unlock_irqrestore(&up->port.lock, flags);
573}
574
575static void
576serial_pxa_pm(struct uart_port *port, unsigned int state,
577 unsigned int oldstate)
578{
579 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
b049bd9d 580
1da177e4 581 if (!state)
b049bd9d
RK		 582 clk_enable(up->clk);
583 else
584 clk_disable(up->clk);
1da177e4
LT		 585}
586
587static void serial_pxa_release_port(struct uart_port *port)
588{
589}
590
591static int serial_pxa_request_port(struct uart_port *port)
592{
593 return 0;
594}
595
596static void serial_pxa_config_port(struct uart_port *port, int flags)
597{
598 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
599 up->port.type = PORT_PXA;
600}
601
602static int
603serial_pxa_verify_port(struct uart_port *port, struct serial_struct *ser)
604{
605 /* we don't want the core code to modify any port params */
606 return -EINVAL;
607}
608
609static const char *
610serial_pxa_type(struct uart_port *port)
611{
612 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
613 return up->name;
614}
615
e259a3ae 616static struct uart_pxa_port *serial_pxa_ports[4];
2d93486c 617static struct uart_driver serial_pxa_reg;
1da177e4 618
fa7f1518
PZ		 619#ifdef CONFIG_SERIAL_PXA_CONSOLE
620
1da177e4
LT		 621#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
622
623/*
624 * Wait for transmitter & holding register to empty
625 */
626static inline void wait_for_xmitr(struct uart_pxa_port *up)
627{
628 unsigned int status, tmout = 10000;
629
630 /* Wait up to 10ms for the character(s) to be sent. */
631 do {
632 status = serial_in(up, UART_LSR);
633
634 if (status & UART_LSR_BI)
635 up->lsr_break_flag = UART_LSR_BI;
636
637 if (--tmout == 0)
638 break;
639 udelay(1);
640 } while ((status & BOTH_EMPTY) != BOTH_EMPTY);
641
642 /* Wait up to 1s for flow control if necessary */
643 if (up->port.flags & UPF_CONS_FLOW) {
644 tmout = 1000000;
645 while (--tmout &&
646 ((serial_in(up, UART_MSR) & UART_MSR_CTS) == 0))
647 udelay(1);
648 }
649}
650
d358788f
RK		 651static void serial_pxa_console_putchar(struct uart_port *port, int ch)
652{
653 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
654
655 wait_for_xmitr(up);
656 serial_out(up, UART_TX, ch);
657}
658
1da177e4
LT		 659/*
660 * Print a string to the serial port trying not to disturb
661 * any possible real use of the port...
662 *
663 * The console_lock must be held when we get here.
664 */
665static void
666serial_pxa_console_write(struct console *co, const char *s, unsigned int count)
667{
e259a3ae 668 struct uart_pxa_port *up = serial_pxa_ports[co->index];
1da177e4 669 unsigned int ier;
1da177e4 670
b049bd9d
RK		 671 clk_enable(up->clk);
672
1da177e4 673 /*
f02aa3f9 674 * First save the IER then disable the interrupts
1da177e4
LT		 675 */
676 ier = serial_in(up, UART_IER);
677 serial_out(up, UART_IER, UART_IER_UUE);
678
d358788f 679 uart_console_write(&up->port, s, count, serial_pxa_console_putchar);
1da177e4
LT		 680
681 /*
682 * Finally, wait for transmitter to become empty
683 * and restore the IER
684 */
685 wait_for_xmitr(up);
686 serial_out(up, UART_IER, ier);
b049bd9d
RK		 687
688 clk_disable(up->clk);
1da177e4
LT		 689}
690
691static int __init
692serial_pxa_console_setup(struct console *co, char *options)
693{
694 struct uart_pxa_port *up;
695 int baud = 9600;
696 int bits = 8;
697 int parity = 'n';
698 int flow = 'n';
699
700 if (co->index == -1 || co->index >= serial_pxa_reg.nr)
701 co->index = 0;
e259a3ae
RK		 702 up = serial_pxa_ports[co->index];
703 if (!up)
704 return -ENODEV;
1da177e4
LT		 705
706 if (options)
707 uart_parse_options(options, &baud, &parity, &bits, &flow);
708
709 return uart_set_options(&up->port, co, baud, parity, bits, flow);
710}
711
712static struct console serial_pxa_console = {
713 .name = "ttyS",
714 .write = serial_pxa_console_write,
715 .device = uart_console_device,
716 .setup = serial_pxa_console_setup,
717 .flags = CON_PRINTBUFFER,
718 .index = -1,
719 .data = &serial_pxa_reg,
720};
721
1da177e4
LT		 722#define PXA_CONSOLE &serial_pxa_console
723#else
724#define PXA_CONSOLE NULL
725#endif
726
727struct uart_ops serial_pxa_pops = {
728 .tx_empty = serial_pxa_tx_empty,
729 .set_mctrl = serial_pxa_set_mctrl,
730 .get_mctrl = serial_pxa_get_mctrl,
731 .stop_tx = serial_pxa_stop_tx,
732 .start_tx = serial_pxa_start_tx,
733 .stop_rx = serial_pxa_stop_rx,
734 .enable_ms = serial_pxa_enable_ms,
735 .break_ctl = serial_pxa_break_ctl,
736 .startup = serial_pxa_startup,
737 .shutdown = serial_pxa_shutdown,
738 .set_termios = serial_pxa_set_termios,
739 .pm = serial_pxa_pm,
740 .type = serial_pxa_type,
741 .release_port = serial_pxa_release_port,
742 .request_port = serial_pxa_request_port,
743 .config_port = serial_pxa_config_port,
744 .verify_port = serial_pxa_verify_port,
745};
746
1da177e4
LT		 747static struct uart_driver serial_pxa_reg = {
748 .owner = THIS_MODULE,
749 .driver_name = "PXA serial",
1da177e4
LT		 750 .dev_name = "ttyS",
751 .major = TTY_MAJOR,
752 .minor = 64,
e259a3ae 753 .nr = 4,
1da177e4
LT		 754 .cons = PXA_CONSOLE,
755};
756
bf56c751
MR		 757#ifdef CONFIG_PM
758static int serial_pxa_suspend(struct device *dev)
1da177e4 759{
bf56c751 760 struct uart_pxa_port *sport = dev_get_drvdata(dev);
1da177e4 761
9480e307 762 if (sport)
1da177e4
LT		 763 uart_suspend_port(&serial_pxa_reg, &sport->port);
764
765 return 0;
766}
767
bf56c751 768static int serial_pxa_resume(struct device *dev)
1da177e4 769{
bf56c751 770 struct uart_pxa_port *sport = dev_get_drvdata(dev);
1da177e4 771
9480e307 772 if (sport)
1da177e4
LT		 773 uart_resume_port(&serial_pxa_reg, &sport->port);
774
775 return 0;
776}
777
47145210 778static const struct dev_pm_ops serial_pxa_pm_ops = {
bf56c751
MR		 779 .suspend = serial_pxa_suspend,
780 .resume = serial_pxa_resume,
781};
782#endif
783
3ae5eaec 784static int serial_pxa_probe(struct platform_device *dev)
1da177e4 785{
e259a3ae
RK		 786 struct uart_pxa_port *sport;
787 struct resource *mmres, *irqres;
788 int ret;
789
790 mmres = platform_get_resource(dev, IORESOURCE_MEM, 0);
791 irqres = platform_get_resource(dev, IORESOURCE_IRQ, 0);
792 if (!mmres || !irqres)
793 return -ENODEV;
794
795 sport = kzalloc(sizeof(struct uart_pxa_port), GFP_KERNEL);
796 if (!sport)
797 return -ENOMEM;
798
e0d8b13a 799 sport->clk = clk_get(&dev->dev, NULL);
b049bd9d
RK		 800 if (IS_ERR(sport->clk)) {
801 ret = PTR_ERR(sport->clk);
802 goto err_free;
803 }
804
e259a3ae
RK		 805 sport->port.type = PORT_PXA;
806 sport->port.iotype = UPIO_MEM;
807 sport->port.mapbase = mmres->start;
808 sport->port.irq = irqres->start;
809 sport->port.fifosize = 64;
810 sport->port.ops = &serial_pxa_pops;
811 sport->port.line = dev->id;
812 sport->port.dev = &dev->dev;
813 sport->port.flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF;
b049bd9d 814 sport->port.uartclk = clk_get_rate(sport->clk);
e259a3ae 815
290a5589
EM		 816 switch (dev->id) {
817 case 0: sport->name = "FFUART"; break;
818 case 1: sport->name = "BTUART"; break;
819 case 2: sport->name = "STUART"; break;
820 case 3: sport->name = "HWUART"; break;
821 default:
e259a3ae 822 sport->name = "???";
290a5589
EM		 823 break;
824 }
e259a3ae 825
28f65c11 826 sport->port.membase = ioremap(mmres->start, resource_size(mmres));
e259a3ae
RK		 827 if (!sport->port.membase) {
828 ret = -ENOMEM;
b049bd9d 829 goto err_clk;
e259a3ae
RK		 830 }
831
832 serial_pxa_ports[dev->id] = sport;
833
834 uart_add_one_port(&serial_pxa_reg, &sport->port);
835 platform_set_drvdata(dev, sport);
836
1da177e4 837 return 0;
e259a3ae 838
b049bd9d
RK		 839 err_clk:
840 clk_put(sport->clk);
e259a3ae
RK		 841 err_free:
842 kfree(sport);
843 return ret;
1da177e4
LT		 844}
845
3ae5eaec 846static int serial_pxa_remove(struct platform_device *dev)
1da177e4 847{
3ae5eaec 848 struct uart_pxa_port *sport = platform_get_drvdata(dev);
1da177e4 849
3ae5eaec 850 platform_set_drvdata(dev, NULL);
1da177e4 851
e259a3ae 852 uart_remove_one_port(&serial_pxa_reg, &sport->port);
b049bd9d 853 clk_put(sport->clk);
e259a3ae 854 kfree(sport);
1da177e4
LT		 855
856 return 0;
857}
858
3ae5eaec 859static struct platform_driver serial_pxa_driver = {
1da177e4
LT		 860 .probe = serial_pxa_probe,
861 .remove = serial_pxa_remove,
862
3ae5eaec
RK		 863 .driver = {
864 .name = "pxa2xx-uart",
e169c139 865 .owner = THIS_MODULE,
bf56c751
MR		 866#ifdef CONFIG_PM
867 .pm = &serial_pxa_pm_ops,
868#endif
3ae5eaec 869 },
1da177e4
LT		 870};
871
872int __init serial_pxa_init(void)
873{
874 int ret;
875
876 ret = uart_register_driver(&serial_pxa_reg);
877 if (ret != 0)
878 return ret;
879
3ae5eaec 880 ret = platform_driver_register(&serial_pxa_driver);
1da177e4
LT		 881 if (ret != 0)
882 uart_unregister_driver(&serial_pxa_reg);
883
884 return ret;
885}
886
887void __exit serial_pxa_exit(void)
888{
3ae5eaec 889 platform_driver_unregister(&serial_pxa_driver);
1da177e4
LT		 890 uart_unregister_driver(&serial_pxa_reg);
891}
892
893module_init(serial_pxa_init);
894module_exit(serial_pxa_exit);
895
896MODULE_LICENSE("GPL");
e169c139 897MODULE_ALIAS("platform:pxa2xx-uart");
Linux 6.x block layer and io_uring tree(s)