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Merge tag 'kbuild-v4.18-2' of git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy...
[linux-2.6-block.git] / drivers / tty / serial / pxa.c
CommitLineData
e3b3d0f5 1// SPDX-License-Identifier: GPL-2.0+
1da177e4 2/*
1da177e4
LT		 3 * Based on drivers/serial/8250.c by Russell King.
4 *
5 * Author: Nicolas Pitre
6 * Created: Feb 20, 2003
7 * Copyright: (C) 2003 Monta Vista Software, Inc.
8 *
1da177e4
LT		 9 * Note 1: This driver is made separate from the already too overloaded
10 * 8250.c because it needs some kirks of its own and that'll make it
11 * easier to add DMA support.
12 *
13 * Note 2: I'm too sick of device allocation policies for serial ports.
14 * If someone else wants to request an "official" allocation of major/minor
15 * for this driver please be my guest. And don't forget that new hardware
16 * to come from Intel might have more than 3 or 4 of those UARTs. Let's
17 * hope for a better port registration and dynamic device allocation scheme
18 * with the serial core maintainer satisfaction to appear soon.
19 */
20
1da177e4
LT		 21
22#if defined(CONFIG_SERIAL_PXA_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
23#define SUPPORT_SYSRQ
24#endif
25
1da177e4
LT		 26#include <linux/ioport.h>
27#include <linux/init.h>
28#include <linux/console.h>
29#include <linux/sysrq.h>
30#include <linux/serial_reg.h>
31#include <linux/circ_buf.h>
32#include <linux/delay.h>
33#include <linux/interrupt.h>
699c20f3 34#include <linux/of.h>
d052d1be 35#include <linux/platform_device.h>
1da177e4
LT		 36#include <linux/tty.h>
37#include <linux/tty_flip.h>
38#include <linux/serial_core.h>
b049bd9d 39#include <linux/clk.h>
290a5589 40#include <linux/io.h>
5a0e3ad6 41#include <linux/slab.h>
1da177e4 42
699c20f3
HZ		 43#define PXA_NAME_LEN 8
44
1da177e4
LT		 45struct uart_pxa_port {
46 struct uart_port port;
47 unsigned char ier;
48 unsigned char lcr;
49 unsigned char mcr;
50 unsigned int lsr_break_flag;
b049bd9d 51 struct clk *clk;
699c20f3 52 char name[PXA_NAME_LEN];
1da177e4
LT		 53};
54
55static inline unsigned int serial_in(struct uart_pxa_port *up, int offset)
56{
57 offset <<= 2;
58 return readl(up->port.membase + offset);
59}
60
61static inline void serial_out(struct uart_pxa_port *up, int offset, int value)
62{
63 offset <<= 2;
64 writel(value, up->port.membase + offset);
65}
66
67static void serial_pxa_enable_ms(struct uart_port *port)
68{
69 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
70
71 up->ier |= UART_IER_MSI;
72 serial_out(up, UART_IER, up->ier);
73}
74
b129a8cc 75static void serial_pxa_stop_tx(struct uart_port *port)
1da177e4
LT		 76{
77 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
78
79 if (up->ier & UART_IER_THRI) {
80 up->ier &= ~UART_IER_THRI;
81 serial_out(up, UART_IER, up->ier);
82 }
83}
84
85static void serial_pxa_stop_rx(struct uart_port *port)
86{
87 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
88
89 up->ier &= ~UART_IER_RLSI;
90 up->port.read_status_mask &= ~UART_LSR_DR;
91 serial_out(up, UART_IER, up->ier);
92}
93
7d12e780 94static inline void receive_chars(struct uart_pxa_port *up, int *status)
1da177e4 95{
1da177e4
LT		 96 unsigned int ch, flag;
97 int max_count = 256;
98
99 do {
e44aabd6
MF		 100 /* work around Errata #20 according to
101 * Intel(R) PXA27x Processor Family
102 * Specification Update (May 2005)
103 *
104 * Step 2
105 * Disable the Reciever Time Out Interrupt via IER[RTOEI]
106 */
107 up->ier &= ~UART_IER_RTOIE;
108 serial_out(up, UART_IER, up->ier);
109
1da177e4
LT		 110 ch = serial_in(up, UART_RX);
111 flag = TTY_NORMAL;
112 up->port.icount.rx++;
113
114 if (unlikely(*status & (UART_LSR_BI | UART_LSR_PE |
115 UART_LSR_FE | UART_LSR_OE))) {
116 /*
117 * For statistics only
118 */
119 if (*status & UART_LSR_BI) {
120 *status &= ~(UART_LSR_FE | UART_LSR_PE);
121 up->port.icount.brk++;
122 /*
123 * We do the SysRQ and SAK checking
124 * here because otherwise the break
125 * may get masked by ignore_status_mask
126 * or read_status_mask.
127 */
128 if (uart_handle_break(&up->port))
129 goto ignore_char;
130 } else if (*status & UART_LSR_PE)
131 up->port.icount.parity++;
132 else if (*status & UART_LSR_FE)
133 up->port.icount.frame++;
134 if (*status & UART_LSR_OE)
135 up->port.icount.overrun++;
136
137 /*
138 * Mask off conditions which should be ignored.
139 */
140 *status &= up->port.read_status_mask;
141
142#ifdef CONFIG_SERIAL_PXA_CONSOLE
143 if (up->port.line == up->port.cons->index) {
144 /* Recover the break flag from console xmit */
145 *status |= up->lsr_break_flag;
146 up->lsr_break_flag = 0;
147 }
148#endif
149 if (*status & UART_LSR_BI) {
150 flag = TTY_BREAK;
151 } else if (*status & UART_LSR_PE)
152 flag = TTY_PARITY;
153 else if (*status & UART_LSR_FE)
154 flag = TTY_FRAME;
155 }
05ab3014 156
7d12e780 157 if (uart_handle_sysrq_char(&up->port, ch))
1da177e4 158 goto ignore_char;
05ab3014
RK		 159
160 uart_insert_char(&up->port, *status, UART_LSR_OE, ch, flag);
161
1da177e4
LT		 162 ignore_char:
163 *status = serial_in(up, UART_LSR);
164 } while ((*status & UART_LSR_DR) && (max_count-- > 0));
2e124b4a 165 tty_flip_buffer_push(&up->port.state->port);
e44aabd6
MF		 166
167 /* work around Errata #20 according to
168 * Intel(R) PXA27x Processor Family
169 * Specification Update (May 2005)
170 *
171 * Step 6:
172 * No more data in FIFO: Re-enable RTO interrupt via IER[RTOIE]
173 */
174 up->ier |= UART_IER_RTOIE;
175 serial_out(up, UART_IER, up->ier);
1da177e4
LT		 176}
177
178static void transmit_chars(struct uart_pxa_port *up)
179{
ebd2c8f6 180 struct circ_buf *xmit = &up->port.state->xmit;
1da177e4
LT		 181 int count;
182
183 if (up->port.x_char) {
184 serial_out(up, UART_TX, up->port.x_char);
185 up->port.icount.tx++;
186 up->port.x_char = 0;
187 return;
188 }
189 if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
b129a8cc 190 serial_pxa_stop_tx(&up->port);
1da177e4
LT		 191 return;
192 }
193
194 count = up->port.fifosize / 2;
195 do {
196 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
197 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
198 up->port.icount.tx++;
199 if (uart_circ_empty(xmit))
200 break;
201 } while (--count > 0);
202
203 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
204 uart_write_wakeup(&up->port);
205
206
207 if (uart_circ_empty(xmit))
b129a8cc 208 serial_pxa_stop_tx(&up->port);
1da177e4
LT		 209}
210
b129a8cc 211static void serial_pxa_start_tx(struct uart_port *port)
1da177e4
LT		 212{
213 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
214
215 if (!(up->ier & UART_IER_THRI)) {
216 up->ier |= UART_IER_THRI;
217 serial_out(up, UART_IER, up->ier);
218 }
219}
220
50d1e7d1 221/* should hold up->port.lock */
1da177e4
LT		 222static inline void check_modem_status(struct uart_pxa_port *up)
223{
224 int status;
225
226 status = serial_in(up, UART_MSR);
227
228 if ((status & UART_MSR_ANY_DELTA) == 0)
229 return;
230
231 if (status & UART_MSR_TERI)
232 up->port.icount.rng++;
233 if (status & UART_MSR_DDSR)
234 up->port.icount.dsr++;
235 if (status & UART_MSR_DDCD)
236 uart_handle_dcd_change(&up->port, status & UART_MSR_DCD);
237 if (status & UART_MSR_DCTS)
238 uart_handle_cts_change(&up->port, status & UART_MSR_CTS);
239
bdc04e31 240 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
1da177e4
LT		 241}
242
243/*
244 * This handles the interrupt from one port.
245 */
7d12e780 246static inline irqreturn_t serial_pxa_irq(int irq, void *dev_id)
1da177e4 247{
c7bec5ab 248 struct uart_pxa_port *up = dev_id;
1da177e4
LT		 249 unsigned int iir, lsr;
250
251 iir = serial_in(up, UART_IIR);
252 if (iir & UART_IIR_NO_INT)
253 return IRQ_NONE;
50d1e7d1 254 spin_lock(&up->port.lock);
1da177e4
LT		 255 lsr = serial_in(up, UART_LSR);
256 if (lsr & UART_LSR_DR)
7d12e780 257 receive_chars(up, &lsr);
1da177e4
LT		 258 check_modem_status(up);
259 if (lsr & UART_LSR_THRE)
260 transmit_chars(up);
50d1e7d1 261 spin_unlock(&up->port.lock);
1da177e4
LT		 262 return IRQ_HANDLED;
263}
264
265static unsigned int serial_pxa_tx_empty(struct uart_port *port)
266{
267 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
268 unsigned long flags;
269 unsigned int ret;
270
271 spin_lock_irqsave(&up->port.lock, flags);
272 ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
273 spin_unlock_irqrestore(&up->port.lock, flags);
274
275 return ret;
276}
277
278static unsigned int serial_pxa_get_mctrl(struct uart_port *port)
279{
280 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
1da177e4
LT		 281 unsigned char status;
282 unsigned int ret;
283
1da177e4 284 status = serial_in(up, UART_MSR);
1da177e4
LT		 285
286 ret = 0;
287 if (status & UART_MSR_DCD)
288 ret |= TIOCM_CAR;
289 if (status & UART_MSR_RI)
290 ret |= TIOCM_RNG;
291 if (status & UART_MSR_DSR)
292 ret |= TIOCM_DSR;
293 if (status & UART_MSR_CTS)
294 ret |= TIOCM_CTS;
295 return ret;
296}
297
298static void serial_pxa_set_mctrl(struct uart_port *port, unsigned int mctrl)
299{
300 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
301 unsigned char mcr = 0;
302
303 if (mctrl & TIOCM_RTS)
304 mcr |= UART_MCR_RTS;
305 if (mctrl & TIOCM_DTR)
306 mcr |= UART_MCR_DTR;
307 if (mctrl & TIOCM_OUT1)
308 mcr |= UART_MCR_OUT1;
309 if (mctrl & TIOCM_OUT2)
310 mcr |= UART_MCR_OUT2;
311 if (mctrl & TIOCM_LOOP)
312 mcr |= UART_MCR_LOOP;
313
314 mcr |= up->mcr;
315
316 serial_out(up, UART_MCR, mcr);
317}
318
319static void serial_pxa_break_ctl(struct uart_port *port, int break_state)
320{
321 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
322 unsigned long flags;
323
324 spin_lock_irqsave(&up->port.lock, flags);
325 if (break_state == -1)
326 up->lcr |= UART_LCR_SBC;
327 else
328 up->lcr &= ~UART_LCR_SBC;
329 serial_out(up, UART_LCR, up->lcr);
330 spin_unlock_irqrestore(&up->port.lock, flags);
331}
332
1da177e4
LT		 333static int serial_pxa_startup(struct uart_port *port)
334{
335 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
336 unsigned long flags;
337 int retval;
338
d9e29649
MR		 339 if (port->line == 3) /* HWUART */
340 up->mcr |= UART_MCR_AFE;
341 else
f02aa3f9 342 up->mcr = 0;
1da177e4 343
b049bd9d
RK		 344 up->port.uartclk = clk_get_rate(up->clk);
345
1da177e4
LT		 346 /*
347 * Allocate the IRQ
348 */
349 retval = request_irq(up->port.irq, serial_pxa_irq, 0, up->name, up);
350 if (retval)
351 return retval;
352
353 /*
354 * Clear the FIFO buffers and disable them.
355 * (they will be reenabled in set_termios())
356 */
357 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
358 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
359 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
360 serial_out(up, UART_FCR, 0);
361
362 /*
363 * Clear the interrupt registers.
364 */
365 (void) serial_in(up, UART_LSR);
366 (void) serial_in(up, UART_RX);
367 (void) serial_in(up, UART_IIR);
368 (void) serial_in(up, UART_MSR);
369
370 /*
371 * Now, initialize the UART
372 */
373 serial_out(up, UART_LCR, UART_LCR_WLEN8);
374
375 spin_lock_irqsave(&up->port.lock, flags);
376 up->port.mctrl |= TIOCM_OUT2;
377 serial_pxa_set_mctrl(&up->port, up->port.mctrl);
378 spin_unlock_irqrestore(&up->port.lock, flags);
379
380 /*
381 * Finally, enable interrupts. Note: Modem status interrupts
80f7228b 382 * are set via set_termios(), which will be occurring imminently
1da177e4
LT		 383 * anyway, so we don't enable them here.
384 */
385 up->ier = UART_IER_RLSI | UART_IER_RDI | UART_IER_RTOIE | UART_IER_UUE;
386 serial_out(up, UART_IER, up->ier);
387
388 /*
389 * And clear the interrupt registers again for luck.
390 */
391 (void) serial_in(up, UART_LSR);
392 (void) serial_in(up, UART_RX);
393 (void) serial_in(up, UART_IIR);
394 (void) serial_in(up, UART_MSR);
395
396 return 0;
397}
398
399static void serial_pxa_shutdown(struct uart_port *port)
400{
401 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
402 unsigned long flags;
403
404 free_irq(up->port.irq, up);
405
406 /*
407 * Disable interrupts from this port
408 */
409 up->ier = 0;
410 serial_out(up, UART_IER, 0);
411
412 spin_lock_irqsave(&up->port.lock, flags);
413 up->port.mctrl &= ~TIOCM_OUT2;
414 serial_pxa_set_mctrl(&up->port, up->port.mctrl);
415 spin_unlock_irqrestore(&up->port.lock, flags);
416
417 /*
418 * Disable break condition and FIFOs
419 */
420 serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC);
421 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
422 UART_FCR_CLEAR_RCVR |
423 UART_FCR_CLEAR_XMIT);
424 serial_out(up, UART_FCR, 0);
425}
426
427static void
606d099c
AC		 428serial_pxa_set_termios(struct uart_port *port, struct ktermios *termios,
429 struct ktermios *old)
1da177e4
LT		 430{
431 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
432 unsigned char cval, fcr = 0;
433 unsigned long flags;
434 unsigned int baud, quot;
c934878c 435 unsigned int dll;
1da177e4
LT		 436
437 switch (termios->c_cflag & CSIZE) {
438 case CS5:
0a8b80c5 439 cval = UART_LCR_WLEN5;
1da177e4
LT		 440 break;
441 case CS6:
0a8b80c5 442 cval = UART_LCR_WLEN6;
1da177e4
LT		 443 break;
444 case CS7:
0a8b80c5 445 cval = UART_LCR_WLEN7;
1da177e4
LT		 446 break;
447 default:
448 case CS8:
0a8b80c5 449 cval = UART_LCR_WLEN8;
1da177e4
LT		 450 break;
451 }
452
453 if (termios->c_cflag & CSTOPB)
0a8b80c5 454 cval |= UART_LCR_STOP;
1da177e4
LT		 455 if (termios->c_cflag & PARENB)
456 cval |= UART_LCR_PARITY;
457 if (!(termios->c_cflag & PARODD))
458 cval |= UART_LCR_EPAR;
459
460 /*
461 * Ask the core to calculate the divisor for us.
462 */
463 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
464 quot = uart_get_divisor(port, baud);
465
466 if ((up->port.uartclk / quot) < (2400 * 16))
467 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_PXAR1;
d9e29649 468 else if ((up->port.uartclk / quot) < (230400 * 16))
1da177e4 469 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_PXAR8;
d9e29649
MR		 470 else
471 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_PXAR32;
1da177e4
LT		 472
473 /*
474 * Ok, we're now changing the port state. Do it with
475 * interrupts disabled.
476 */
477 spin_lock_irqsave(&up->port.lock, flags);
478
479 /*
480 * Ensure the port will be enabled.
481 * This is required especially for serial console.
482 */
290a5589 483 up->ier |= UART_IER_UUE;
1da177e4
LT		 484
485 /*
486 * Update the per-port timeout.
487 */
e6158b4a 488 uart_update_timeout(port, termios->c_cflag, baud);
1da177e4
LT		 489
490 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
491 if (termios->c_iflag & INPCK)
492 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
ef8b9ddc 493 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
1da177e4
LT		 494 up->port.read_status_mask |= UART_LSR_BI;
495
496 /*
497 * Characters to ignore
498 */
499 up->port.ignore_status_mask = 0;
500 if (termios->c_iflag & IGNPAR)
501 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
502 if (termios->c_iflag & IGNBRK) {
503 up->port.ignore_status_mask |= UART_LSR_BI;
504 /*
505 * If we're ignoring parity and break indicators,
506 * ignore overruns too (for real raw support).
507 */
508 if (termios->c_iflag & IGNPAR)
509 up->port.ignore_status_mask |= UART_LSR_OE;
510 }
511
512 /*
513 * ignore all characters if CREAD is not set
514 */
515 if ((termios->c_cflag & CREAD) == 0)
516 up->port.ignore_status_mask |= UART_LSR_DR;
517
518 /*
519 * CTS flow control flag and modem status interrupts
520 */
521 up->ier &= ~UART_IER_MSI;
522 if (UART_ENABLE_MS(&up->port, termios->c_cflag))
523 up->ier |= UART_IER_MSI;
524
525 serial_out(up, UART_IER, up->ier);
526
2276f03b
RJ		 527 if (termios->c_cflag & CRTSCTS)
528 up->mcr |= UART_MCR_AFE;
529 else
530 up->mcr &= ~UART_MCR_AFE;
531
c934878c 532 serial_out(up, UART_LCR, cval | UART_LCR_DLAB); /* set DLAB */
1da177e4 533 serial_out(up, UART_DLL, quot & 0xff); /* LS of divisor */
c934878c
UKK		 534
535 /*
536 * work around Errata #75 according to Intel(R) PXA27x Processor Family
537 * Specification Update (Nov 2005)
538 */
539 dll = serial_in(up, UART_DLL);
540 WARN_ON(dll != (quot & 0xff));
541
1da177e4 542 serial_out(up, UART_DLM, quot >> 8); /* MS of divisor */
c934878c 543 serial_out(up, UART_LCR, cval); /* reset DLAB */
1da177e4
LT		 544 up->lcr = cval; /* Save LCR */
545 serial_pxa_set_mctrl(&up->port, up->port.mctrl);
546 serial_out(up, UART_FCR, fcr);
547 spin_unlock_irqrestore(&up->port.lock, flags);
548}
549
550static void
551serial_pxa_pm(struct uart_port *port, unsigned int state,
552 unsigned int oldstate)
553{
554 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
b049bd9d 555
1da177e4 556 if (!state)
fb8ebec0 557 clk_prepare_enable(up->clk);
b049bd9d 558 else
fb8ebec0 559 clk_disable_unprepare(up->clk);
1da177e4
LT		 560}
561
562static void serial_pxa_release_port(struct uart_port *port)
563{
564}
565
566static int serial_pxa_request_port(struct uart_port *port)
567{
568 return 0;
569}
570
571static void serial_pxa_config_port(struct uart_port *port, int flags)
572{
573 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
574 up->port.type = PORT_PXA;
575}
576
577static int
578serial_pxa_verify_port(struct uart_port *port, struct serial_struct *ser)
579{
580 /* we don't want the core code to modify any port params */
581 return -EINVAL;
582}
583
584static const char *
585serial_pxa_type(struct uart_port *port)
586{
587 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
588 return up->name;
589}
590
e259a3ae 591static struct uart_pxa_port *serial_pxa_ports[4];
2d93486c 592static struct uart_driver serial_pxa_reg;
1da177e4 593
fa7f1518
PZ		 594#ifdef CONFIG_SERIAL_PXA_CONSOLE
595
1da177e4
LT		 596#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
597
598/*
599 * Wait for transmitter & holding register to empty
600 */
be9ae5d9 601static void wait_for_xmitr(struct uart_pxa_port *up)
1da177e4
LT		 602{
603 unsigned int status, tmout = 10000;
604
605 /* Wait up to 10ms for the character(s) to be sent. */
606 do {
607 status = serial_in(up, UART_LSR);
608
609 if (status & UART_LSR_BI)
610 up->lsr_break_flag = UART_LSR_BI;
611
612 if (--tmout == 0)
613 break;
614 udelay(1);
615 } while ((status & BOTH_EMPTY) != BOTH_EMPTY);
616
617 /* Wait up to 1s for flow control if necessary */
618 if (up->port.flags & UPF_CONS_FLOW) {
619 tmout = 1000000;
620 while (--tmout &&
621 ((serial_in(up, UART_MSR) & UART_MSR_CTS) == 0))
622 udelay(1);
623 }
624}
625
d358788f
RK		 626static void serial_pxa_console_putchar(struct uart_port *port, int ch)
627{
628 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
629
630 wait_for_xmitr(up);
631 serial_out(up, UART_TX, ch);
632}
633
1da177e4
LT		 634/*
635 * Print a string to the serial port trying not to disturb
636 * any possible real use of the port...
637 *
638 * The console_lock must be held when we get here.
639 */
640static void
641serial_pxa_console_write(struct console *co, const char *s, unsigned int count)
642{
e259a3ae 643 struct uart_pxa_port *up = serial_pxa_ports[co->index];
1da177e4 644 unsigned int ier;
cfe275c2
CX		 645 unsigned long flags;
646 int locked = 1;
1da177e4 647
9429ccbf 648 clk_enable(up->clk);
cfe275c2
CX		 649 local_irq_save(flags);
650 if (up->port.sysrq)
651 locked = 0;
652 else if (oops_in_progress)
653 locked = spin_trylock(&up->port.lock);
654 else
655 spin_lock(&up->port.lock);
656
1da177e4 657 /*
f02aa3f9 658 * First save the IER then disable the interrupts
1da177e4
LT		 659 */
660 ier = serial_in(up, UART_IER);
661 serial_out(up, UART_IER, UART_IER_UUE);
662
d358788f 663 uart_console_write(&up->port, s, count, serial_pxa_console_putchar);
1da177e4
LT		 664
665 /*
666 * Finally, wait for transmitter to become empty
667 * and restore the IER
668 */
669 wait_for_xmitr(up);
670 serial_out(up, UART_IER, ier);
b049bd9d 671
cfe275c2
CX		 672 if (locked)
673 spin_unlock(&up->port.lock);
674 local_irq_restore(flags);
9429ccbf 675 clk_disable(up->clk);
cfe275c2 676
1da177e4
LT		 677}
678
e1a9c179
DL		 679#ifdef CONFIG_CONSOLE_POLL
680/*
681 * Console polling routines for writing and reading from the uart while
682 * in an interrupt or debug context.
683 */
684
685static int serial_pxa_get_poll_char(struct uart_port *port)
686{
687 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
688 unsigned char lsr = serial_in(up, UART_LSR);
689
690 while (!(lsr & UART_LSR_DR))
691 lsr = serial_in(up, UART_LSR);
692
693 return serial_in(up, UART_RX);
694}
695
696
697static void serial_pxa_put_poll_char(struct uart_port *port,
698 unsigned char c)
699{
700 unsigned int ier;
701 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
702
703 /*
704 * First save the IER then disable the interrupts
705 */
706 ier = serial_in(up, UART_IER);
707 serial_out(up, UART_IER, UART_IER_UUE);
708
709 wait_for_xmitr(up);
710 /*
711 * Send the character out.
e1a9c179
DL		 712 */
713 serial_out(up, UART_TX, c);
e1a9c179
DL		 714
715 /*
716 * Finally, wait for transmitter to become empty
717 * and restore the IER
718 */
719 wait_for_xmitr(up);
720 serial_out(up, UART_IER, ier);
721}
722
723#endif /* CONFIG_CONSOLE_POLL */
724
1da177e4
LT		 725static int __init
726serial_pxa_console_setup(struct console *co, char *options)
727{
728 struct uart_pxa_port *up;
729 int baud = 9600;
730 int bits = 8;
731 int parity = 'n';
732 int flow = 'n';
733
734 if (co->index == -1 || co->index >= serial_pxa_reg.nr)
735 co->index = 0;
e259a3ae
RK		 736 up = serial_pxa_ports[co->index];
737 if (!up)
738 return -ENODEV;
1da177e4
LT		 739
740 if (options)
741 uart_parse_options(options, &baud, &parity, &bits, &flow);
742
743 return uart_set_options(&up->port, co, baud, parity, bits, flow);
744}
745
746static struct console serial_pxa_console = {
747 .name = "ttyS",
748 .write = serial_pxa_console_write,
749 .device = uart_console_device,
750 .setup = serial_pxa_console_setup,
751 .flags = CON_PRINTBUFFER,
752 .index = -1,
753 .data = &serial_pxa_reg,
754};
755
1da177e4
LT		 756#define PXA_CONSOLE &serial_pxa_console
757#else
758#define PXA_CONSOLE NULL
759#endif
760
2331e068 761static const struct uart_ops serial_pxa_pops = {
1da177e4
LT		 762 .tx_empty = serial_pxa_tx_empty,
763 .set_mctrl = serial_pxa_set_mctrl,
764 .get_mctrl = serial_pxa_get_mctrl,
765 .stop_tx = serial_pxa_stop_tx,
766 .start_tx = serial_pxa_start_tx,
767 .stop_rx = serial_pxa_stop_rx,
768 .enable_ms = serial_pxa_enable_ms,
769 .break_ctl = serial_pxa_break_ctl,
770 .startup = serial_pxa_startup,
771 .shutdown = serial_pxa_shutdown,
772 .set_termios = serial_pxa_set_termios,
773 .pm = serial_pxa_pm,
774 .type = serial_pxa_type,
775 .release_port = serial_pxa_release_port,
776 .request_port = serial_pxa_request_port,
777 .config_port = serial_pxa_config_port,
778 .verify_port = serial_pxa_verify_port,
2ee881b7 779#if defined(CONFIG_CONSOLE_POLL) && defined(CONFIG_SERIAL_PXA_CONSOLE)
e1a9c179
DL		 780 .poll_get_char = serial_pxa_get_poll_char,
781 .poll_put_char = serial_pxa_put_poll_char,
782#endif
1da177e4
LT		 783};
784
1da177e4
LT		 785static struct uart_driver serial_pxa_reg = {
786 .owner = THIS_MODULE,
787 .driver_name = "PXA serial",
1da177e4
LT		 788 .dev_name = "ttyS",
789 .major = TTY_MAJOR,
790 .minor = 64,
e259a3ae 791 .nr = 4,
1da177e4
LT		 792 .cons = PXA_CONSOLE,
793};
794
bf56c751
MR		 795#ifdef CONFIG_PM
796static int serial_pxa_suspend(struct device *dev)
1da177e4 797{
bf56c751 798 struct uart_pxa_port *sport = dev_get_drvdata(dev);
1da177e4 799
9480e307 800 if (sport)
1da177e4
LT		 801 uart_suspend_port(&serial_pxa_reg, &sport->port);
802
803 return 0;
804}
805
bf56c751 806static int serial_pxa_resume(struct device *dev)
1da177e4 807{
bf56c751 808 struct uart_pxa_port *sport = dev_get_drvdata(dev);
1da177e4 809
9480e307 810 if (sport)
1da177e4
LT		 811 uart_resume_port(&serial_pxa_reg, &sport->port);
812
813 return 0;
814}
815
47145210 816static const struct dev_pm_ops serial_pxa_pm_ops = {
bf56c751
MR		 817 .suspend = serial_pxa_suspend,
818 .resume = serial_pxa_resume,
819};
820#endif
821
ed0bb232 822static const struct of_device_id serial_pxa_dt_ids[] = {
699c20f3
HZ		 823 { .compatible = "mrvl,pxa-uart", },
824 { .compatible = "mrvl,mmp-uart", },
825 {}
826};
699c20f3
HZ		 827
828static int serial_pxa_probe_dt(struct platform_device *pdev,
829 struct uart_pxa_port *sport)
830{
831 struct device_node *np = pdev->dev.of_node;
832 int ret;
833
834 if (!np)
835 return 1;
836
837 ret = of_alias_get_id(np, "serial");
838 if (ret < 0) {
839 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
840 return ret;
841 }
842 sport->port.line = ret;
843 return 0;
844}
845
3ae5eaec 846static int serial_pxa_probe(struct platform_device *dev)
1da177e4 847{
e259a3ae
RK		 848 struct uart_pxa_port *sport;
849 struct resource *mmres, *irqres;
850 int ret;
851
852 mmres = platform_get_resource(dev, IORESOURCE_MEM, 0);
853 irqres = platform_get_resource(dev, IORESOURCE_IRQ, 0);
854 if (!mmres || !irqres)
855 return -ENODEV;
856
857 sport = kzalloc(sizeof(struct uart_pxa_port), GFP_KERNEL);
858 if (!sport)
859 return -ENOMEM;
860
e0d8b13a 861 sport->clk = clk_get(&dev->dev, NULL);
b049bd9d
RK		 862 if (IS_ERR(sport->clk)) {
863 ret = PTR_ERR(sport->clk);
864 goto err_free;
865 }
866
9429ccbf
YZ		 867 ret = clk_prepare(sport->clk);
868 if (ret) {
869 clk_put(sport->clk);
870 goto err_free;
871 }
872
e259a3ae
RK		 873 sport->port.type = PORT_PXA;
874 sport->port.iotype = UPIO_MEM;
875 sport->port.mapbase = mmres->start;
876 sport->port.irq = irqres->start;
877 sport->port.fifosize = 64;
878 sport->port.ops = &serial_pxa_pops;
e259a3ae
RK		 879 sport->port.dev = &dev->dev;
880 sport->port.flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF;
b049bd9d 881 sport->port.uartclk = clk_get_rate(sport->clk);
e259a3ae 882
699c20f3
HZ		 883 ret = serial_pxa_probe_dt(dev, sport);
884 if (ret > 0)
885 sport->port.line = dev->id;
886 else if (ret < 0)
887 goto err_clk;
afc7851f
GU		 888 if (sport->port.line >= ARRAY_SIZE(serial_pxa_ports)) {
889 dev_err(&dev->dev, "serial%d out of range\n", sport->port.line);
890 return -EINVAL;
891 }
699c20f3 892 snprintf(sport->name, PXA_NAME_LEN - 1, "UART%d", sport->port.line + 1);
e259a3ae 893
28f65c11 894 sport->port.membase = ioremap(mmres->start, resource_size(mmres));
e259a3ae
RK		 895 if (!sport->port.membase) {
896 ret = -ENOMEM;
b049bd9d 897 goto err_clk;
e259a3ae
RK		 898 }
899
699c20f3 900 serial_pxa_ports[sport->port.line] = sport;
e259a3ae
RK		 901
902 uart_add_one_port(&serial_pxa_reg, &sport->port);
903 platform_set_drvdata(dev, sport);
904
1da177e4 905 return 0;
e259a3ae 906
b049bd9d 907 err_clk:
9429ccbf 908 clk_unprepare(sport->clk);
b049bd9d 909 clk_put(sport->clk);
e259a3ae
RK		 910 err_free:
911 kfree(sport);
912 return ret;
1da177e4
LT		 913}
914
3ae5eaec 915static struct platform_driver serial_pxa_driver = {
1da177e4 916 .probe = serial_pxa_probe,
1da177e4 917
3ae5eaec
RK		 918 .driver = {
919 .name = "pxa2xx-uart",
bf56c751
MR		 920#ifdef CONFIG_PM
921 .pm = &serial_pxa_pm_ops,
922#endif
ca16c5a3 923 .suppress_bind_attrs = true,
699c20f3 924 .of_match_table = serial_pxa_dt_ids,
3ae5eaec 925 },
1da177e4
LT		 926};
927
ab28f51c
SY		 928
929/* 8250 driver for PXA serial ports should be used */
9de4153d 930static int __init serial_pxa_init(void)
1da177e4
LT		 931{
932 int ret;
933
934 ret = uart_register_driver(&serial_pxa_reg);
935 if (ret != 0)
936 return ret;
937
3ae5eaec 938 ret = platform_driver_register(&serial_pxa_driver);
1da177e4
LT		 939 if (ret != 0)
940 uart_unregister_driver(&serial_pxa_reg);
941
942 return ret;
943}
ca16c5a3 944device_initcall(serial_pxa_init);
Linux 6.x block layer and io_uring tree(s)