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tty: add SPDX identifiers to all remaining files in drivers/tty/
[linux-2.6-block.git] / drivers / tty / serial / pic32_uart.c
CommitLineData
e3b3d0f5 1// SPDX-License-Identifier: GPL-2.0+
157b9394
AP		 2/*
3 * PIC32 Integrated Serial Driver.
4 *
5 * Copyright (C) 2015 Microchip Technology, Inc.
6 *
7 * Authors:
8 * Sorin-Andrei Pistirica <andrei.pistirica@microchip.com>
9 *
10 * Licensed under GPLv2 or later.
11 */
12
13#include <linux/kernel.h>
14#include <linux/platform_device.h>
15#include <linux/of.h>
16#include <linux/of_device.h>
17#include <linux/of_irq.h>
18#include <linux/of_gpio.h>
19#include <linux/init.h>
20#include <linux/module.h>
21#include <linux/slab.h>
22#include <linux/console.h>
23#include <linux/clk.h>
24#include <linux/tty.h>
25#include <linux/tty_flip.h>
26#include <linux/serial_core.h>
27#include <linux/delay.h>
28
29#include <asm/mach-pic32/pic32.h>
30#include "pic32_uart.h"
31
32/* UART name and device definitions */
33#define PIC32_DEV_NAME "pic32-uart"
34#define PIC32_MAX_UARTS 6
35#define PIC32_SDEV_NAME "ttyPIC"
36
37/* pic32_sport pointer for console use */
38static struct pic32_sport *pic32_sports[PIC32_MAX_UARTS];
39
40static inline void pic32_wait_deplete_txbuf(struct pic32_sport *sport)
41{
42 /* wait for tx empty, otherwise chars will be lost or corrupted */
43 while (!(pic32_uart_readl(sport, PIC32_UART_STA) & PIC32_UART_STA_TRMT))
44 udelay(1);
45}
46
47static inline int pic32_enable_clock(struct pic32_sport *sport)
48{
49 int ret = clk_prepare_enable(sport->clk);
50
51 if (ret)
52 return ret;
53
54 sport->ref_clk++;
55 return 0;
56}
57
58static inline void pic32_disable_clock(struct pic32_sport *sport)
59{
60 sport->ref_clk--;
61 clk_disable_unprepare(sport->clk);
62}
63
64/* serial core request to check if uart tx buffer is empty */
65static unsigned int pic32_uart_tx_empty(struct uart_port *port)
66{
67 struct pic32_sport *sport = to_pic32_sport(port);
68 u32 val = pic32_uart_readl(sport, PIC32_UART_STA);
69
70 return (val & PIC32_UART_STA_TRMT) ? 1 : 0;
71}
72
73/* serial core request to set UART outputs */
74static void pic32_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
75{
76 struct pic32_sport *sport = to_pic32_sport(port);
77
78 /* set loopback mode */
79 if (mctrl & TIOCM_LOOP)
80 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_MODE),
81 PIC32_UART_MODE_LPBK);
82 else
83 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
84 PIC32_UART_MODE_LPBK);
85}
86
87/* get the state of CTS input pin for this port */
88static unsigned int get_cts_state(struct pic32_sport *sport)
89{
90 /* read and invert UxCTS */
91 if (gpio_is_valid(sport->cts_gpio))
92 return !gpio_get_value(sport->cts_gpio);
93
94 return 1;
95}
96
97/* serial core request to return the state of misc UART input pins */
98static unsigned int pic32_uart_get_mctrl(struct uart_port *port)
99{
100 struct pic32_sport *sport = to_pic32_sport(port);
101 unsigned int mctrl = 0;
102
103 if (!sport->hw_flow_ctrl)
104 mctrl |= TIOCM_CTS;
105 else if (get_cts_state(sport))
106 mctrl |= TIOCM_CTS;
107
108 /* DSR and CD are not supported in PIC32, so return 1
109 * RI is not supported in PIC32, so return 0
110 */
111 mctrl |= TIOCM_CD;
112 mctrl |= TIOCM_DSR;
113
114 return mctrl;
115}
116
117/* stop tx and start tx are not called in pairs, therefore a flag indicates
118 * the status of irq to control the irq-depth.
119 */
120static inline void pic32_uart_irqtxen(struct pic32_sport *sport, u8 en)
121{
122 if (en && !tx_irq_enabled(sport)) {
123 enable_irq(sport->irq_tx);
124 tx_irq_enabled(sport) = 1;
125 } else if (!en && tx_irq_enabled(sport)) {
126 /* use disable_irq_nosync() and not disable_irq() to avoid self
127 * imposed deadlock by not waiting for irq handler to end,
128 * since this callback is called from interrupt context.
129 */
130 disable_irq_nosync(sport->irq_tx);
131 tx_irq_enabled(sport) = 0;
132 }
133}
134
135/* serial core request to disable tx ASAP (used for flow control) */
136static void pic32_uart_stop_tx(struct uart_port *port)
137{
138 struct pic32_sport *sport = to_pic32_sport(port);
139
140 if (!(pic32_uart_readl(sport, PIC32_UART_MODE) & PIC32_UART_MODE_ON))
141 return;
142
143 if (!(pic32_uart_readl(sport, PIC32_UART_STA) & PIC32_UART_STA_UTXEN))
144 return;
145
146 /* wait for tx empty */
147 pic32_wait_deplete_txbuf(sport);
148
149 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA),
150 PIC32_UART_STA_UTXEN);
151 pic32_uart_irqtxen(sport, 0);
152}
153
154/* serial core request to (re)enable tx */
155static void pic32_uart_start_tx(struct uart_port *port)
156{
157 struct pic32_sport *sport = to_pic32_sport(port);
158
159 pic32_uart_irqtxen(sport, 1);
160 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_STA),
161 PIC32_UART_STA_UTXEN);
162}
163
164/* serial core request to stop rx, called before port shutdown */
165static void pic32_uart_stop_rx(struct uart_port *port)
166{
167 struct pic32_sport *sport = to_pic32_sport(port);
168
169 /* disable rx interrupts */
170 disable_irq(sport->irq_rx);
171
172 /* receiver Enable bit OFF */
173 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA),
174 PIC32_UART_STA_URXEN);
175}
176
177/* serial core request to start/stop emitting break char */
178static void pic32_uart_break_ctl(struct uart_port *port, int ctl)
179{
180 struct pic32_sport *sport = to_pic32_sport(port);
181 unsigned long flags;
182
183 spin_lock_irqsave(&port->lock, flags);
184
185 if (ctl)
186 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_STA),
187 PIC32_UART_STA_UTXBRK);
188 else
189 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA),
190 PIC32_UART_STA_UTXBRK);
191
192 spin_unlock_irqrestore(&port->lock, flags);
193}
194
195/* get port type in string format */
196static const char *pic32_uart_type(struct uart_port *port)
197{
198 return (port->type == PORT_PIC32) ? PIC32_DEV_NAME : NULL;
199}
200
201/* read all chars in rx fifo and send them to core */
202static void pic32_uart_do_rx(struct uart_port *port)
203{
204 struct pic32_sport *sport = to_pic32_sport(port);
205 struct tty_port *tty;
206 unsigned int max_count;
207
208 /* limit number of char read in interrupt, should not be
209 * higher than fifo size anyway since we're much faster than
210 * serial port
211 */
212 max_count = PIC32_UART_RX_FIFO_DEPTH;
213
214 spin_lock(&port->lock);
215
216 tty = &port->state->port;
217
218 do {
219 u32 sta_reg, c;
220 char flag;
221
222 /* get overrun/fifo empty information from status register */
223 sta_reg = pic32_uart_readl(sport, PIC32_UART_STA);
224 if (unlikely(sta_reg & PIC32_UART_STA_OERR)) {
225
226 /* fifo reset is required to clear interrupt */
227 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA),
228 PIC32_UART_STA_OERR);
229
230 port->icount.overrun++;
231 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
232 }
233
234 /* Can at least one more character can be read? */
235 if (!(sta_reg & PIC32_UART_STA_URXDA))
236 break;
237
238 /* read the character and increment the rx counter */
239 c = pic32_uart_readl(sport, PIC32_UART_RX);
240
241 port->icount.rx++;
242 flag = TTY_NORMAL;
243 c &= 0xff;
244
245 if (unlikely((sta_reg & PIC32_UART_STA_PERR) ||
246 (sta_reg & PIC32_UART_STA_FERR))) {
247
248 /* do stats first */
249 if (sta_reg & PIC32_UART_STA_PERR)
250 port->icount.parity++;
251 if (sta_reg & PIC32_UART_STA_FERR)
252 port->icount.frame++;
253
254 /* update flag wrt read_status_mask */
255 sta_reg &= port->read_status_mask;
256
257 if (sta_reg & PIC32_UART_STA_FERR)
258 flag = TTY_FRAME;
259 if (sta_reg & PIC32_UART_STA_PERR)
260 flag = TTY_PARITY;
261 }
262
263 if (uart_handle_sysrq_char(port, c))
264 continue;
265
266 if ((sta_reg & port->ignore_status_mask) == 0)
267 tty_insert_flip_char(tty, c, flag);
268
269 } while (--max_count);
270
271 spin_unlock(&port->lock);
272
273 tty_flip_buffer_push(tty);
274}
275
276/* fill tx fifo with chars to send, stop when fifo is about to be full
277 * or when all chars have been sent.
278 */
279static void pic32_uart_do_tx(struct uart_port *port)
280{
281 struct pic32_sport *sport = to_pic32_sport(port);
282 struct circ_buf *xmit = &port->state->xmit;
283 unsigned int max_count = PIC32_UART_TX_FIFO_DEPTH;
284
285 if (port->x_char) {
286 pic32_uart_writel(sport, PIC32_UART_TX, port->x_char);
287 port->icount.tx++;
288 port->x_char = 0;
289 return;
290 }
291
292 if (uart_tx_stopped(port)) {
293 pic32_uart_stop_tx(port);
294 return;
295 }
296
297 if (uart_circ_empty(xmit))
298 goto txq_empty;
299
300 /* keep stuffing chars into uart tx buffer
301 * 1) until uart fifo is full
302 * or
303 * 2) until the circ buffer is empty
304 * (all chars have been sent)
305 * or
306 * 3) until the max count is reached
307 * (prevents lingering here for too long in certain cases)
308 */
309 while (!(PIC32_UART_STA_UTXBF &
310 pic32_uart_readl(sport, PIC32_UART_STA))) {
311 unsigned int c = xmit->buf[xmit->tail];
312
313 pic32_uart_writel(sport, PIC32_UART_TX, c);
314
315 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
316 port->icount.tx++;
317 if (uart_circ_empty(xmit))
318 break;
319 if (--max_count == 0)
320 break;
321 }
322
323 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
324 uart_write_wakeup(port);
325
326 if (uart_circ_empty(xmit))
327 goto txq_empty;
328
329 return;
330
331txq_empty:
332 pic32_uart_irqtxen(sport, 0);
333}
334
335/* RX interrupt handler */
336static irqreturn_t pic32_uart_rx_interrupt(int irq, void *dev_id)
337{
338 struct uart_port *port = dev_id;
339
340 pic32_uart_do_rx(port);
341
342 return IRQ_HANDLED;
343}
344
345/* TX interrupt handler */
346static irqreturn_t pic32_uart_tx_interrupt(int irq, void *dev_id)
347{
348 struct uart_port *port = dev_id;
349 unsigned long flags;
350
351 spin_lock_irqsave(&port->lock, flags);
352 pic32_uart_do_tx(port);
353 spin_unlock_irqrestore(&port->lock, flags);
354
355 return IRQ_HANDLED;
356}
357
358/* FAULT interrupt handler */
359static irqreturn_t pic32_uart_fault_interrupt(int irq, void *dev_id)
360{
361 /* do nothing: pic32_uart_do_rx() handles faults. */
362 return IRQ_HANDLED;
363}
364
365/* enable rx & tx operation on uart */
366static void pic32_uart_en_and_unmask(struct uart_port *port)
367{
368 struct pic32_sport *sport = to_pic32_sport(port);
369
370 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_STA),
371 PIC32_UART_STA_UTXEN | PIC32_UART_STA_URXEN);
372 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_MODE),
373 PIC32_UART_MODE_ON);
374}
375
376/* disable rx & tx operation on uart */
377static void pic32_uart_dsbl_and_mask(struct uart_port *port)
378{
379 struct pic32_sport *sport = to_pic32_sport(port);
380
381 /* wait for tx empty, otherwise chars will be lost or corrupted */
382 pic32_wait_deplete_txbuf(sport);
383
384 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA),
385 PIC32_UART_STA_UTXEN | PIC32_UART_STA_URXEN);
386 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
387 PIC32_UART_MODE_ON);
388}
389
390/* serial core request to initialize uart and start rx operation */
391static int pic32_uart_startup(struct uart_port *port)
392{
393 struct pic32_sport *sport = to_pic32_sport(port);
394 u32 dflt_baud = (port->uartclk / PIC32_UART_DFLT_BRATE / 16) - 1;
395 unsigned long flags;
396 int ret;
397
398 local_irq_save(flags);
399
400 ret = pic32_enable_clock(sport);
401 if (ret) {
402 local_irq_restore(flags);
403 goto out_done;
404 }
405
406 /* clear status and mode registers */
407 pic32_uart_writel(sport, PIC32_UART_MODE, 0);
408 pic32_uart_writel(sport, PIC32_UART_STA, 0);
409
410 /* disable uart and mask all interrupts */
411 pic32_uart_dsbl_and_mask(port);
412
413 /* set default baud */
414 pic32_uart_writel(sport, PIC32_UART_BRG, dflt_baud);
415
416 local_irq_restore(flags);
417
418 /* Each UART of a PIC32 has three interrupts therefore,
419 * we setup driver to register the 3 irqs for the device.
420 *
421 * For each irq request_irq() is called with interrupt disabled.
422 * And the irq is enabled as soon as we are ready to handle them.
423 */
424 tx_irq_enabled(sport) = 0;
425
426 sport->irq_fault_name = kasprintf(GFP_KERNEL, "%s%d-fault",
427 pic32_uart_type(port),
428 sport->idx);
429 if (!sport->irq_fault_name) {
430 dev_err(port->dev, "%s: kasprintf err!", __func__);
431 ret = -ENOMEM;
432 goto out_done;
433 }
434 irq_set_status_flags(sport->irq_fault, IRQ_NOAUTOEN);
435 ret = request_irq(sport->irq_fault, pic32_uart_fault_interrupt,
436 sport->irqflags_fault, sport->irq_fault_name, port);
437 if (ret) {
438 dev_err(port->dev, "%s: request irq(%d) err! ret:%d name:%s\n",
439 __func__, sport->irq_fault, ret,
440 pic32_uart_type(port));
441 goto out_f;
442 }
443
444 sport->irq_rx_name = kasprintf(GFP_KERNEL, "%s%d-rx",
445 pic32_uart_type(port),
446 sport->idx);
447 if (!sport->irq_rx_name) {
448 dev_err(port->dev, "%s: kasprintf err!", __func__);
157b9394
AP		 449 ret = -ENOMEM;
450 goto out_f;
451 }
452 irq_set_status_flags(sport->irq_rx, IRQ_NOAUTOEN);
453 ret = request_irq(sport->irq_rx, pic32_uart_rx_interrupt,
454 sport->irqflags_rx, sport->irq_rx_name, port);
455 if (ret) {
456 dev_err(port->dev, "%s: request irq(%d) err! ret:%d name:%s\n",
457 __func__, sport->irq_rx, ret,
458 pic32_uart_type(port));
459 goto out_r;
460 }
461
462 sport->irq_tx_name = kasprintf(GFP_KERNEL, "%s%d-tx",
463 pic32_uart_type(port),
464 sport->idx);
465 if (!sport->irq_tx_name) {
466 dev_err(port->dev, "%s: kasprintf err!", __func__);
467 ret = -ENOMEM;
468 goto out_r;
469 }
470 irq_set_status_flags(sport->irq_tx, IRQ_NOAUTOEN);
471 ret = request_irq(sport->irq_tx, pic32_uart_tx_interrupt,
472 sport->irqflags_tx, sport->irq_tx_name, port);
473 if (ret) {
474 dev_err(port->dev, "%s: request irq(%d) err! ret:%d name:%s\n",
475 __func__, sport->irq_tx, ret,
476 pic32_uart_type(port));
477 goto out_t;
478 }
479
480 local_irq_save(flags);
481
482 /* set rx interrupt on first receive */
483 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA),
484 PIC32_UART_STA_URXISEL1 | PIC32_UART_STA_URXISEL0);
485
486 /* set interrupt on empty */
487 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA),
488 PIC32_UART_STA_UTXISEL1);
489
490 /* enable all interrupts and eanable uart */
491 pic32_uart_en_and_unmask(port);
492
493 enable_irq(sport->irq_rx);
494
495 return 0;
496
497out_t:
498 kfree(sport->irq_tx_name);
2aaa9573 499 free_irq(sport->irq_tx, port);
157b9394
AP		 500out_r:
501 kfree(sport->irq_rx_name);
2aaa9573 502 free_irq(sport->irq_rx, port);
157b9394
AP		 503out_f:
504 kfree(sport->irq_fault_name);
2aaa9573 505 free_irq(sport->irq_fault, port);
157b9394
AP		 506out_done:
507 return ret;
508}
509
510/* serial core request to flush & disable uart */
511static void pic32_uart_shutdown(struct uart_port *port)
512{
513 struct pic32_sport *sport = to_pic32_sport(port);
514 unsigned long flags;
515
516 /* disable uart */
517 spin_lock_irqsave(&port->lock, flags);
518 pic32_uart_dsbl_and_mask(port);
519 spin_unlock_irqrestore(&port->lock, flags);
520 pic32_disable_clock(sport);
521
522 /* free all 3 interrupts for this UART */
523 free_irq(sport->irq_fault, port);
524 free_irq(sport->irq_tx, port);
525 free_irq(sport->irq_rx, port);
526}
527
528/* serial core request to change current uart setting */
529static void pic32_uart_set_termios(struct uart_port *port,
530 struct ktermios *new,
531 struct ktermios *old)
532{
533 struct pic32_sport *sport = to_pic32_sport(port);
534 unsigned int baud;
535 unsigned int quot;
536 unsigned long flags;
537
538 spin_lock_irqsave(&port->lock, flags);
539
540 /* disable uart and mask all interrupts while changing speed */
541 pic32_uart_dsbl_and_mask(port);
542
543 /* stop bit options */
544 if (new->c_cflag & CSTOPB)
545 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_MODE),
546 PIC32_UART_MODE_STSEL);
547 else
548 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
549 PIC32_UART_MODE_STSEL);
550
551 /* parity options */
552 if (new->c_cflag & PARENB) {
553 if (new->c_cflag & PARODD) {
554 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_MODE),
555 PIC32_UART_MODE_PDSEL1);
556 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
557 PIC32_UART_MODE_PDSEL0);
558 } else {
559 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_MODE),
560 PIC32_UART_MODE_PDSEL0);
561 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
562 PIC32_UART_MODE_PDSEL1);
563 }
564 } else {
565 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
566 PIC32_UART_MODE_PDSEL1 |
567 PIC32_UART_MODE_PDSEL0);
568 }
569 /* if hw flow ctrl, then the pins must be specified in device tree */
570 if ((new->c_cflag & CRTSCTS) && sport->hw_flow_ctrl) {
571 /* enable hardware flow control */
572 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_MODE),
573 PIC32_UART_MODE_UEN1);
574 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
575 PIC32_UART_MODE_UEN0);
576 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
577 PIC32_UART_MODE_RTSMD);
578 } else {
579 /* disable hardware flow control */
580 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
581 PIC32_UART_MODE_UEN1);
582 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
583 PIC32_UART_MODE_UEN0);
584 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE),
585 PIC32_UART_MODE_RTSMD);
586 }
587
588 /* Always 8-bit */
589 new->c_cflag |= CS8;
590
591 /* Mark/Space parity is not supported */
592 new->c_cflag &= ~CMSPAR;
593
594 /* update baud */
595 baud = uart_get_baud_rate(port, new, old, 0, port->uartclk / 16);
596 quot = uart_get_divisor(port, baud) - 1;
597 pic32_uart_writel(sport, PIC32_UART_BRG, quot);
598 uart_update_timeout(port, new->c_cflag, baud);
599
600 if (tty_termios_baud_rate(new))
601 tty_termios_encode_baud_rate(new, baud, baud);
602
603 /* enable uart */
604 pic32_uart_en_and_unmask(port);
605
606 spin_unlock_irqrestore(&port->lock, flags);
607}
608
609/* serial core request to claim uart iomem */
610static int pic32_uart_request_port(struct uart_port *port)
611{
612 struct platform_device *pdev = to_platform_device(port->dev);
613 struct resource *res_mem;
614
615 res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
616 if (unlikely(!res_mem))
617 return -EINVAL;
618
619 if (!request_mem_region(port->mapbase, resource_size(res_mem),
620 "pic32_uart_mem"))
621 return -EBUSY;
622
623 port->membase = devm_ioremap_nocache(port->dev, port->mapbase,
624 resource_size(res_mem));
625 if (!port->membase) {
626 dev_err(port->dev, "Unable to map registers\n");
627 release_mem_region(port->mapbase, resource_size(res_mem));
628 return -ENOMEM;
629 }
630
631 return 0;
632}
633
634/* serial core request to release uart iomem */
635static void pic32_uart_release_port(struct uart_port *port)
636{
637 struct platform_device *pdev = to_platform_device(port->dev);
638 struct resource *res_mem;
639 unsigned int res_size;
640
641 res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
642 if (unlikely(!res_mem))
643 return;
644 res_size = resource_size(res_mem);
645
646 release_mem_region(port->mapbase, res_size);
647}
648
649/* serial core request to do any port required auto-configuration */
650static void pic32_uart_config_port(struct uart_port *port, int flags)
651{
652 if (flags & UART_CONFIG_TYPE) {
653 if (pic32_uart_request_port(port))
654 return;
655 port->type = PORT_PIC32;
656 }
657}
658
659/* serial core request to check that port information in serinfo are suitable */
660static int pic32_uart_verify_port(struct uart_port *port,
661 struct serial_struct *serinfo)
662{
663 if (port->type != PORT_PIC32)
664 return -EINVAL;
665 if (port->irq != serinfo->irq)
666 return -EINVAL;
667 if (port->iotype != serinfo->io_type)
668 return -EINVAL;
669 if (port->mapbase != (unsigned long)serinfo->iomem_base)
670 return -EINVAL;
671
672 return 0;
673}
674
675/* serial core callbacks */
676static const struct uart_ops pic32_uart_ops = {
677 .tx_empty = pic32_uart_tx_empty,
678 .get_mctrl = pic32_uart_get_mctrl,
679 .set_mctrl = pic32_uart_set_mctrl,
680 .start_tx = pic32_uart_start_tx,
681 .stop_tx = pic32_uart_stop_tx,
682 .stop_rx = pic32_uart_stop_rx,
683 .break_ctl = pic32_uart_break_ctl,
684 .startup = pic32_uart_startup,
685 .shutdown = pic32_uart_shutdown,
686 .set_termios = pic32_uart_set_termios,
687 .type = pic32_uart_type,
688 .release_port = pic32_uart_release_port,
689 .request_port = pic32_uart_request_port,
690 .config_port = pic32_uart_config_port,
691 .verify_port = pic32_uart_verify_port,
692};
693
694#ifdef CONFIG_SERIAL_PIC32_CONSOLE
695/* output given char */
696static void pic32_console_putchar(struct uart_port *port, int ch)
697{
698 struct pic32_sport *sport = to_pic32_sport(port);
699
700 if (!(pic32_uart_readl(sport, PIC32_UART_MODE) & PIC32_UART_MODE_ON))
701 return;
702
703 if (!(pic32_uart_readl(sport, PIC32_UART_STA) & PIC32_UART_STA_UTXEN))
704 return;
705
706 /* wait for tx empty */
707 pic32_wait_deplete_txbuf(sport);
708
709 pic32_uart_writel(sport, PIC32_UART_TX, ch & 0xff);
710}
711
712/* console core request to output given string */
713static void pic32_console_write(struct console *co, const char *s,
714 unsigned int count)
715{
716 struct pic32_sport *sport = pic32_sports[co->index];
717 struct uart_port *port = pic32_get_port(sport);
718
719 /* call uart helper to deal with \r\n */
720 uart_console_write(port, s, count, pic32_console_putchar);
721}
722
723/* console core request to setup given console, find matching uart
724 * port and setup it.
725 */
726static int pic32_console_setup(struct console *co, char *options)
727{
728 struct pic32_sport *sport;
729 struct uart_port *port = NULL;
730 int baud = 115200;
731 int bits = 8;
732 int parity = 'n';
733 int flow = 'n';
734 int ret = 0;
735
736 if (unlikely(co->index < 0 || co->index >= PIC32_MAX_UARTS))
737 return -ENODEV;
738
739 sport = pic32_sports[co->index];
740 if (!sport)
741 return -ENODEV;
742 port = pic32_get_port(sport);
743
744 ret = pic32_enable_clock(sport);
745 if (ret)
746 return ret;
747
748 if (options)
749 uart_parse_options(options, &baud, &parity, &bits, &flow);
750
751 return uart_set_options(port, co, baud, parity, bits, flow);
752}
753
754static struct uart_driver pic32_uart_driver;
755static struct console pic32_console = {
756 .name = PIC32_SDEV_NAME,
757 .write = pic32_console_write,
758 .device = uart_console_device,
759 .setup = pic32_console_setup,
760 .flags = CON_PRINTBUFFER,
761 .index = -1,
762 .data = &pic32_uart_driver,
763};
764#define PIC32_SCONSOLE (&pic32_console)
765
766static int __init pic32_console_init(void)
767{
768 register_console(&pic32_console);
769 return 0;
770}
771console_initcall(pic32_console_init);
772
773static inline bool is_pic32_console_port(struct uart_port *port)
774{
775 return port->cons && port->cons->index == port->line;
776}
777
778/*
779 * Late console initialization.
780 */
781static int __init pic32_late_console_init(void)
782{
783 if (!(pic32_console.flags & CON_ENABLED))
784 register_console(&pic32_console);
785
786 return 0;
787}
788
789core_initcall(pic32_late_console_init);
790
791#else
792#define PIC32_SCONSOLE NULL
793#endif
794
795static struct uart_driver pic32_uart_driver = {
796 .owner = THIS_MODULE,
797 .driver_name = PIC32_DEV_NAME,
798 .dev_name = PIC32_SDEV_NAME,
799 .nr = PIC32_MAX_UARTS,
800 .cons = PIC32_SCONSOLE,
801};
802
803static int pic32_uart_probe(struct platform_device *pdev)
804{
805 struct device_node *np = pdev->dev.of_node;
806 struct pic32_sport *sport;
807 int uart_idx = 0;
808 struct resource *res_mem;
809 struct uart_port *port;
810 int ret;
811
812 uart_idx = of_alias_get_id(np, "serial");
813 if (uart_idx < 0 || uart_idx >= PIC32_MAX_UARTS)
814 return -EINVAL;
815
816 res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
817 if (!res_mem)
818 return -EINVAL;
819
820 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
821 if (!sport)
822 return -ENOMEM;
823
824 sport->idx = uart_idx;
825 sport->irq_fault = irq_of_parse_and_map(np, 0);
826 sport->irqflags_fault = IRQF_NO_THREAD;
827 sport->irq_rx = irq_of_parse_and_map(np, 1);
828 sport->irqflags_rx = IRQF_NO_THREAD;
829 sport->irq_tx = irq_of_parse_and_map(np, 2);
830 sport->irqflags_tx = IRQF_NO_THREAD;
831 sport->clk = devm_clk_get(&pdev->dev, NULL);
832 sport->cts_gpio = -EINVAL;
833 sport->dev = &pdev->dev;
834
835 /* Hardware flow control: gpios
836 * !Note: Basically, CTS is needed for reading the status.
837 */
838 sport->hw_flow_ctrl = false;
839 sport->cts_gpio = of_get_named_gpio(np, "cts-gpios", 0);
840 if (gpio_is_valid(sport->cts_gpio)) {
841 sport->hw_flow_ctrl = true;
842
843 ret = devm_gpio_request(sport->dev,
844 sport->cts_gpio, "CTS");
845 if (ret) {
846 dev_err(&pdev->dev,
847 "error requesting CTS GPIO\n");
848 goto err;
849 }
850
851 ret = gpio_direction_input(sport->cts_gpio);
852 if (ret) {
853 dev_err(&pdev->dev, "error setting CTS GPIO\n");
854 goto err;
855 }
856 }
857
858 pic32_sports[uart_idx] = sport;
859 port = &sport->port;
860 memset(port, 0, sizeof(*port));
861 port->iotype = UPIO_MEM;
862 port->mapbase = res_mem->start;
863 port->ops = &pic32_uart_ops;
864 port->flags = UPF_BOOT_AUTOCONF;
865 port->dev = &pdev->dev;
866 port->fifosize = PIC32_UART_TX_FIFO_DEPTH;
867 port->uartclk = clk_get_rate(sport->clk);
868 port->line = uart_idx;
869
870 ret = uart_add_one_port(&pic32_uart_driver, port);
871 if (ret) {
872 port->membase = NULL;
873 dev_err(port->dev, "%s: uart add port error!\n", __func__);
874 goto err;
875 }
876
877#ifdef CONFIG_SERIAL_PIC32_CONSOLE
878 if (is_pic32_console_port(port) &&
879 (pic32_console.flags & CON_ENABLED)) {
880 /* The peripheral clock has been enabled by console_setup,
881 * so disable it till the port is used.
882 */
883 pic32_disable_clock(sport);
884 }
885#endif
886
887 platform_set_drvdata(pdev, port);
888
889 dev_info(&pdev->dev, "%s: uart(%d) driver initialized.\n",
890 __func__, uart_idx);
891
892 return 0;
893err:
894 /* automatic unroll of sport and gpios */
895 return ret;
896}
897
898static int pic32_uart_remove(struct platform_device *pdev)
899{
900 struct uart_port *port = platform_get_drvdata(pdev);
901 struct pic32_sport *sport = to_pic32_sport(port);
902
903 uart_remove_one_port(&pic32_uart_driver, port);
904 pic32_disable_clock(sport);
905 platform_set_drvdata(pdev, NULL);
906 pic32_sports[sport->idx] = NULL;
907
908 /* automatic unroll of sport and gpios */
909 return 0;
910}
911
912static const struct of_device_id pic32_serial_dt_ids[] = {
913 { .compatible = "microchip,pic32mzda-uart" },
914 { /* sentinel */ }
915};
916MODULE_DEVICE_TABLE(of, pic32_serial_dt_ids);
917
918static struct platform_driver pic32_uart_platform_driver = {
919 .probe = pic32_uart_probe,
920 .remove = pic32_uart_remove,
921 .driver = {
922 .name = PIC32_DEV_NAME,
923 .of_match_table = of_match_ptr(pic32_serial_dt_ids),
924 },
925};
926
927static int __init pic32_uart_init(void)
928{
929 int ret;
930
931 ret = uart_register_driver(&pic32_uart_driver);
932 if (ret) {
933 pr_err("failed to register %s:%d\n",
934 pic32_uart_driver.driver_name, ret);
935 return ret;
936 }
937
938 ret = platform_driver_register(&pic32_uart_platform_driver);
939 if (ret) {
940 pr_err("fail to register pic32 uart\n");
941 uart_unregister_driver(&pic32_uart_driver);
942 }
943
944 return ret;
945}
946arch_initcall(pic32_uart_init);
947
948static void __exit pic32_uart_exit(void)
949{
950#ifdef CONFIG_SERIAL_PIC32_CONSOLE
951 unregister_console(&pic32_console);
952#endif
953 platform_driver_unregister(&pic32_uart_platform_driver);
954 uart_unregister_driver(&pic32_uart_driver);
955}
956module_exit(pic32_uart_exit);
957
958MODULE_AUTHOR("Sorin-Andrei Pistirica <andrei.pistirica@microchip.com>");
959MODULE_DESCRIPTION("Microchip PIC32 integrated serial port driver");
960MODULE_LICENSE("GPL v2");
Linux 6.x block layer and io_uring tree(s)