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157b9394 AP |
1 | /* |
2 | * PIC32 Integrated Serial Driver. | |
3 | * | |
4 | * Copyright (C) 2015 Microchip Technology, Inc. | |
5 | * | |
6 | * Authors: | |
7 | * Sorin-Andrei Pistirica <andrei.pistirica@microchip.com> | |
8 | * | |
9 | * Licensed under GPLv2 or later. | |
10 | */ | |
11 | ||
12 | #include <linux/kernel.h> | |
13 | #include <linux/platform_device.h> | |
14 | #include <linux/of.h> | |
15 | #include <linux/of_device.h> | |
16 | #include <linux/of_irq.h> | |
17 | #include <linux/of_gpio.h> | |
18 | #include <linux/init.h> | |
19 | #include <linux/module.h> | |
20 | #include <linux/slab.h> | |
21 | #include <linux/console.h> | |
22 | #include <linux/clk.h> | |
23 | #include <linux/tty.h> | |
24 | #include <linux/tty_flip.h> | |
25 | #include <linux/serial_core.h> | |
26 | #include <linux/delay.h> | |
27 | ||
28 | #include <asm/mach-pic32/pic32.h> | |
29 | #include "pic32_uart.h" | |
30 | ||
31 | /* UART name and device definitions */ | |
32 | #define PIC32_DEV_NAME "pic32-uart" | |
33 | #define PIC32_MAX_UARTS 6 | |
34 | #define PIC32_SDEV_NAME "ttyPIC" | |
35 | ||
36 | /* pic32_sport pointer for console use */ | |
37 | static struct pic32_sport *pic32_sports[PIC32_MAX_UARTS]; | |
38 | ||
39 | static inline void pic32_wait_deplete_txbuf(struct pic32_sport *sport) | |
40 | { | |
41 | /* wait for tx empty, otherwise chars will be lost or corrupted */ | |
42 | while (!(pic32_uart_readl(sport, PIC32_UART_STA) & PIC32_UART_STA_TRMT)) | |
43 | udelay(1); | |
44 | } | |
45 | ||
46 | static inline int pic32_enable_clock(struct pic32_sport *sport) | |
47 | { | |
48 | int ret = clk_prepare_enable(sport->clk); | |
49 | ||
50 | if (ret) | |
51 | return ret; | |
52 | ||
53 | sport->ref_clk++; | |
54 | return 0; | |
55 | } | |
56 | ||
57 | static inline void pic32_disable_clock(struct pic32_sport *sport) | |
58 | { | |
59 | sport->ref_clk--; | |
60 | clk_disable_unprepare(sport->clk); | |
61 | } | |
62 | ||
63 | /* serial core request to check if uart tx buffer is empty */ | |
64 | static unsigned int pic32_uart_tx_empty(struct uart_port *port) | |
65 | { | |
66 | struct pic32_sport *sport = to_pic32_sport(port); | |
67 | u32 val = pic32_uart_readl(sport, PIC32_UART_STA); | |
68 | ||
69 | return (val & PIC32_UART_STA_TRMT) ? 1 : 0; | |
70 | } | |
71 | ||
72 | /* serial core request to set UART outputs */ | |
73 | static void pic32_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) | |
74 | { | |
75 | struct pic32_sport *sport = to_pic32_sport(port); | |
76 | ||
77 | /* set loopback mode */ | |
78 | if (mctrl & TIOCM_LOOP) | |
79 | pic32_uart_writel(sport, PIC32_SET(PIC32_UART_MODE), | |
80 | PIC32_UART_MODE_LPBK); | |
81 | else | |
82 | pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE), | |
83 | PIC32_UART_MODE_LPBK); | |
84 | } | |
85 | ||
86 | /* get the state of CTS input pin for this port */ | |
87 | static unsigned int get_cts_state(struct pic32_sport *sport) | |
88 | { | |
89 | /* read and invert UxCTS */ | |
90 | if (gpio_is_valid(sport->cts_gpio)) | |
91 | return !gpio_get_value(sport->cts_gpio); | |
92 | ||
93 | return 1; | |
94 | } | |
95 | ||
96 | /* serial core request to return the state of misc UART input pins */ | |
97 | static unsigned int pic32_uart_get_mctrl(struct uart_port *port) | |
98 | { | |
99 | struct pic32_sport *sport = to_pic32_sport(port); | |
100 | unsigned int mctrl = 0; | |
101 | ||
102 | if (!sport->hw_flow_ctrl) | |
103 | mctrl |= TIOCM_CTS; | |
104 | else if (get_cts_state(sport)) | |
105 | mctrl |= TIOCM_CTS; | |
106 | ||
107 | /* DSR and CD are not supported in PIC32, so return 1 | |
108 | * RI is not supported in PIC32, so return 0 | |
109 | */ | |
110 | mctrl |= TIOCM_CD; | |
111 | mctrl |= TIOCM_DSR; | |
112 | ||
113 | return mctrl; | |
114 | } | |
115 | ||
116 | /* stop tx and start tx are not called in pairs, therefore a flag indicates | |
117 | * the status of irq to control the irq-depth. | |
118 | */ | |
119 | static inline void pic32_uart_irqtxen(struct pic32_sport *sport, u8 en) | |
120 | { | |
121 | if (en && !tx_irq_enabled(sport)) { | |
122 | enable_irq(sport->irq_tx); | |
123 | tx_irq_enabled(sport) = 1; | |
124 | } else if (!en && tx_irq_enabled(sport)) { | |
125 | /* use disable_irq_nosync() and not disable_irq() to avoid self | |
126 | * imposed deadlock by not waiting for irq handler to end, | |
127 | * since this callback is called from interrupt context. | |
128 | */ | |
129 | disable_irq_nosync(sport->irq_tx); | |
130 | tx_irq_enabled(sport) = 0; | |
131 | } | |
132 | } | |
133 | ||
134 | /* serial core request to disable tx ASAP (used for flow control) */ | |
135 | static void pic32_uart_stop_tx(struct uart_port *port) | |
136 | { | |
137 | struct pic32_sport *sport = to_pic32_sport(port); | |
138 | ||
139 | if (!(pic32_uart_readl(sport, PIC32_UART_MODE) & PIC32_UART_MODE_ON)) | |
140 | return; | |
141 | ||
142 | if (!(pic32_uart_readl(sport, PIC32_UART_STA) & PIC32_UART_STA_UTXEN)) | |
143 | return; | |
144 | ||
145 | /* wait for tx empty */ | |
146 | pic32_wait_deplete_txbuf(sport); | |
147 | ||
148 | pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA), | |
149 | PIC32_UART_STA_UTXEN); | |
150 | pic32_uart_irqtxen(sport, 0); | |
151 | } | |
152 | ||
153 | /* serial core request to (re)enable tx */ | |
154 | static void pic32_uart_start_tx(struct uart_port *port) | |
155 | { | |
156 | struct pic32_sport *sport = to_pic32_sport(port); | |
157 | ||
158 | pic32_uart_irqtxen(sport, 1); | |
159 | pic32_uart_writel(sport, PIC32_SET(PIC32_UART_STA), | |
160 | PIC32_UART_STA_UTXEN); | |
161 | } | |
162 | ||
163 | /* serial core request to stop rx, called before port shutdown */ | |
164 | static void pic32_uart_stop_rx(struct uart_port *port) | |
165 | { | |
166 | struct pic32_sport *sport = to_pic32_sport(port); | |
167 | ||
168 | /* disable rx interrupts */ | |
169 | disable_irq(sport->irq_rx); | |
170 | ||
171 | /* receiver Enable bit OFF */ | |
172 | pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA), | |
173 | PIC32_UART_STA_URXEN); | |
174 | } | |
175 | ||
176 | /* serial core request to start/stop emitting break char */ | |
177 | static void pic32_uart_break_ctl(struct uart_port *port, int ctl) | |
178 | { | |
179 | struct pic32_sport *sport = to_pic32_sport(port); | |
180 | unsigned long flags; | |
181 | ||
182 | spin_lock_irqsave(&port->lock, flags); | |
183 | ||
184 | if (ctl) | |
185 | pic32_uart_writel(sport, PIC32_SET(PIC32_UART_STA), | |
186 | PIC32_UART_STA_UTXBRK); | |
187 | else | |
188 | pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA), | |
189 | PIC32_UART_STA_UTXBRK); | |
190 | ||
191 | spin_unlock_irqrestore(&port->lock, flags); | |
192 | } | |
193 | ||
194 | /* get port type in string format */ | |
195 | static const char *pic32_uart_type(struct uart_port *port) | |
196 | { | |
197 | return (port->type == PORT_PIC32) ? PIC32_DEV_NAME : NULL; | |
198 | } | |
199 | ||
200 | /* read all chars in rx fifo and send them to core */ | |
201 | static void pic32_uart_do_rx(struct uart_port *port) | |
202 | { | |
203 | struct pic32_sport *sport = to_pic32_sport(port); | |
204 | struct tty_port *tty; | |
205 | unsigned int max_count; | |
206 | ||
207 | /* limit number of char read in interrupt, should not be | |
208 | * higher than fifo size anyway since we're much faster than | |
209 | * serial port | |
210 | */ | |
211 | max_count = PIC32_UART_RX_FIFO_DEPTH; | |
212 | ||
213 | spin_lock(&port->lock); | |
214 | ||
215 | tty = &port->state->port; | |
216 | ||
217 | do { | |
218 | u32 sta_reg, c; | |
219 | char flag; | |
220 | ||
221 | /* get overrun/fifo empty information from status register */ | |
222 | sta_reg = pic32_uart_readl(sport, PIC32_UART_STA); | |
223 | if (unlikely(sta_reg & PIC32_UART_STA_OERR)) { | |
224 | ||
225 | /* fifo reset is required to clear interrupt */ | |
226 | pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA), | |
227 | PIC32_UART_STA_OERR); | |
228 | ||
229 | port->icount.overrun++; | |
230 | tty_insert_flip_char(tty, 0, TTY_OVERRUN); | |
231 | } | |
232 | ||
233 | /* Can at least one more character can be read? */ | |
234 | if (!(sta_reg & PIC32_UART_STA_URXDA)) | |
235 | break; | |
236 | ||
237 | /* read the character and increment the rx counter */ | |
238 | c = pic32_uart_readl(sport, PIC32_UART_RX); | |
239 | ||
240 | port->icount.rx++; | |
241 | flag = TTY_NORMAL; | |
242 | c &= 0xff; | |
243 | ||
244 | if (unlikely((sta_reg & PIC32_UART_STA_PERR) || | |
245 | (sta_reg & PIC32_UART_STA_FERR))) { | |
246 | ||
247 | /* do stats first */ | |
248 | if (sta_reg & PIC32_UART_STA_PERR) | |
249 | port->icount.parity++; | |
250 | if (sta_reg & PIC32_UART_STA_FERR) | |
251 | port->icount.frame++; | |
252 | ||
253 | /* update flag wrt read_status_mask */ | |
254 | sta_reg &= port->read_status_mask; | |
255 | ||
256 | if (sta_reg & PIC32_UART_STA_FERR) | |
257 | flag = TTY_FRAME; | |
258 | if (sta_reg & PIC32_UART_STA_PERR) | |
259 | flag = TTY_PARITY; | |
260 | } | |
261 | ||
262 | if (uart_handle_sysrq_char(port, c)) | |
263 | continue; | |
264 | ||
265 | if ((sta_reg & port->ignore_status_mask) == 0) | |
266 | tty_insert_flip_char(tty, c, flag); | |
267 | ||
268 | } while (--max_count); | |
269 | ||
270 | spin_unlock(&port->lock); | |
271 | ||
272 | tty_flip_buffer_push(tty); | |
273 | } | |
274 | ||
275 | /* fill tx fifo with chars to send, stop when fifo is about to be full | |
276 | * or when all chars have been sent. | |
277 | */ | |
278 | static void pic32_uart_do_tx(struct uart_port *port) | |
279 | { | |
280 | struct pic32_sport *sport = to_pic32_sport(port); | |
281 | struct circ_buf *xmit = &port->state->xmit; | |
282 | unsigned int max_count = PIC32_UART_TX_FIFO_DEPTH; | |
283 | ||
284 | if (port->x_char) { | |
285 | pic32_uart_writel(sport, PIC32_UART_TX, port->x_char); | |
286 | port->icount.tx++; | |
287 | port->x_char = 0; | |
288 | return; | |
289 | } | |
290 | ||
291 | if (uart_tx_stopped(port)) { | |
292 | pic32_uart_stop_tx(port); | |
293 | return; | |
294 | } | |
295 | ||
296 | if (uart_circ_empty(xmit)) | |
297 | goto txq_empty; | |
298 | ||
299 | /* keep stuffing chars into uart tx buffer | |
300 | * 1) until uart fifo is full | |
301 | * or | |
302 | * 2) until the circ buffer is empty | |
303 | * (all chars have been sent) | |
304 | * or | |
305 | * 3) until the max count is reached | |
306 | * (prevents lingering here for too long in certain cases) | |
307 | */ | |
308 | while (!(PIC32_UART_STA_UTXBF & | |
309 | pic32_uart_readl(sport, PIC32_UART_STA))) { | |
310 | unsigned int c = xmit->buf[xmit->tail]; | |
311 | ||
312 | pic32_uart_writel(sport, PIC32_UART_TX, c); | |
313 | ||
314 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); | |
315 | port->icount.tx++; | |
316 | if (uart_circ_empty(xmit)) | |
317 | break; | |
318 | if (--max_count == 0) | |
319 | break; | |
320 | } | |
321 | ||
322 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
323 | uart_write_wakeup(port); | |
324 | ||
325 | if (uart_circ_empty(xmit)) | |
326 | goto txq_empty; | |
327 | ||
328 | return; | |
329 | ||
330 | txq_empty: | |
331 | pic32_uart_irqtxen(sport, 0); | |
332 | } | |
333 | ||
334 | /* RX interrupt handler */ | |
335 | static irqreturn_t pic32_uart_rx_interrupt(int irq, void *dev_id) | |
336 | { | |
337 | struct uart_port *port = dev_id; | |
338 | ||
339 | pic32_uart_do_rx(port); | |
340 | ||
341 | return IRQ_HANDLED; | |
342 | } | |
343 | ||
344 | /* TX interrupt handler */ | |
345 | static irqreturn_t pic32_uart_tx_interrupt(int irq, void *dev_id) | |
346 | { | |
347 | struct uart_port *port = dev_id; | |
348 | unsigned long flags; | |
349 | ||
350 | spin_lock_irqsave(&port->lock, flags); | |
351 | pic32_uart_do_tx(port); | |
352 | spin_unlock_irqrestore(&port->lock, flags); | |
353 | ||
354 | return IRQ_HANDLED; | |
355 | } | |
356 | ||
357 | /* FAULT interrupt handler */ | |
358 | static irqreturn_t pic32_uart_fault_interrupt(int irq, void *dev_id) | |
359 | { | |
360 | /* do nothing: pic32_uart_do_rx() handles faults. */ | |
361 | return IRQ_HANDLED; | |
362 | } | |
363 | ||
364 | /* enable rx & tx operation on uart */ | |
365 | static void pic32_uart_en_and_unmask(struct uart_port *port) | |
366 | { | |
367 | struct pic32_sport *sport = to_pic32_sport(port); | |
368 | ||
369 | pic32_uart_writel(sport, PIC32_SET(PIC32_UART_STA), | |
370 | PIC32_UART_STA_UTXEN | PIC32_UART_STA_URXEN); | |
371 | pic32_uart_writel(sport, PIC32_SET(PIC32_UART_MODE), | |
372 | PIC32_UART_MODE_ON); | |
373 | } | |
374 | ||
375 | /* disable rx & tx operation on uart */ | |
376 | static void pic32_uart_dsbl_and_mask(struct uart_port *port) | |
377 | { | |
378 | struct pic32_sport *sport = to_pic32_sport(port); | |
379 | ||
380 | /* wait for tx empty, otherwise chars will be lost or corrupted */ | |
381 | pic32_wait_deplete_txbuf(sport); | |
382 | ||
383 | pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA), | |
384 | PIC32_UART_STA_UTXEN | PIC32_UART_STA_URXEN); | |
385 | pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE), | |
386 | PIC32_UART_MODE_ON); | |
387 | } | |
388 | ||
389 | /* serial core request to initialize uart and start rx operation */ | |
390 | static int pic32_uart_startup(struct uart_port *port) | |
391 | { | |
392 | struct pic32_sport *sport = to_pic32_sport(port); | |
393 | u32 dflt_baud = (port->uartclk / PIC32_UART_DFLT_BRATE / 16) - 1; | |
394 | unsigned long flags; | |
395 | int ret; | |
396 | ||
397 | local_irq_save(flags); | |
398 | ||
399 | ret = pic32_enable_clock(sport); | |
400 | if (ret) { | |
401 | local_irq_restore(flags); | |
402 | goto out_done; | |
403 | } | |
404 | ||
405 | /* clear status and mode registers */ | |
406 | pic32_uart_writel(sport, PIC32_UART_MODE, 0); | |
407 | pic32_uart_writel(sport, PIC32_UART_STA, 0); | |
408 | ||
409 | /* disable uart and mask all interrupts */ | |
410 | pic32_uart_dsbl_and_mask(port); | |
411 | ||
412 | /* set default baud */ | |
413 | pic32_uart_writel(sport, PIC32_UART_BRG, dflt_baud); | |
414 | ||
415 | local_irq_restore(flags); | |
416 | ||
417 | /* Each UART of a PIC32 has three interrupts therefore, | |
418 | * we setup driver to register the 3 irqs for the device. | |
419 | * | |
420 | * For each irq request_irq() is called with interrupt disabled. | |
421 | * And the irq is enabled as soon as we are ready to handle them. | |
422 | */ | |
423 | tx_irq_enabled(sport) = 0; | |
424 | ||
425 | sport->irq_fault_name = kasprintf(GFP_KERNEL, "%s%d-fault", | |
426 | pic32_uart_type(port), | |
427 | sport->idx); | |
428 | if (!sport->irq_fault_name) { | |
429 | dev_err(port->dev, "%s: kasprintf err!", __func__); | |
430 | ret = -ENOMEM; | |
431 | goto out_done; | |
432 | } | |
433 | irq_set_status_flags(sport->irq_fault, IRQ_NOAUTOEN); | |
434 | ret = request_irq(sport->irq_fault, pic32_uart_fault_interrupt, | |
435 | sport->irqflags_fault, sport->irq_fault_name, port); | |
436 | if (ret) { | |
437 | dev_err(port->dev, "%s: request irq(%d) err! ret:%d name:%s\n", | |
438 | __func__, sport->irq_fault, ret, | |
439 | pic32_uart_type(port)); | |
440 | goto out_f; | |
441 | } | |
442 | ||
443 | sport->irq_rx_name = kasprintf(GFP_KERNEL, "%s%d-rx", | |
444 | pic32_uart_type(port), | |
445 | sport->idx); | |
446 | if (!sport->irq_rx_name) { | |
447 | dev_err(port->dev, "%s: kasprintf err!", __func__); | |
157b9394 AP |
448 | ret = -ENOMEM; |
449 | goto out_f; | |
450 | } | |
451 | irq_set_status_flags(sport->irq_rx, IRQ_NOAUTOEN); | |
452 | ret = request_irq(sport->irq_rx, pic32_uart_rx_interrupt, | |
453 | sport->irqflags_rx, sport->irq_rx_name, port); | |
454 | if (ret) { | |
455 | dev_err(port->dev, "%s: request irq(%d) err! ret:%d name:%s\n", | |
456 | __func__, sport->irq_rx, ret, | |
457 | pic32_uart_type(port)); | |
458 | goto out_r; | |
459 | } | |
460 | ||
461 | sport->irq_tx_name = kasprintf(GFP_KERNEL, "%s%d-tx", | |
462 | pic32_uart_type(port), | |
463 | sport->idx); | |
464 | if (!sport->irq_tx_name) { | |
465 | dev_err(port->dev, "%s: kasprintf err!", __func__); | |
466 | ret = -ENOMEM; | |
467 | goto out_r; | |
468 | } | |
469 | irq_set_status_flags(sport->irq_tx, IRQ_NOAUTOEN); | |
470 | ret = request_irq(sport->irq_tx, pic32_uart_tx_interrupt, | |
471 | sport->irqflags_tx, sport->irq_tx_name, port); | |
472 | if (ret) { | |
473 | dev_err(port->dev, "%s: request irq(%d) err! ret:%d name:%s\n", | |
474 | __func__, sport->irq_tx, ret, | |
475 | pic32_uart_type(port)); | |
476 | goto out_t; | |
477 | } | |
478 | ||
479 | local_irq_save(flags); | |
480 | ||
481 | /* set rx interrupt on first receive */ | |
482 | pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA), | |
483 | PIC32_UART_STA_URXISEL1 | PIC32_UART_STA_URXISEL0); | |
484 | ||
485 | /* set interrupt on empty */ | |
486 | pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA), | |
487 | PIC32_UART_STA_UTXISEL1); | |
488 | ||
489 | /* enable all interrupts and eanable uart */ | |
490 | pic32_uart_en_and_unmask(port); | |
491 | ||
492 | enable_irq(sport->irq_rx); | |
493 | ||
494 | return 0; | |
495 | ||
496 | out_t: | |
497 | kfree(sport->irq_tx_name); | |
498 | free_irq(sport->irq_tx, sport); | |
499 | out_r: | |
500 | kfree(sport->irq_rx_name); | |
501 | free_irq(sport->irq_rx, sport); | |
502 | out_f: | |
503 | kfree(sport->irq_fault_name); | |
504 | free_irq(sport->irq_fault, sport); | |
505 | out_done: | |
506 | return ret; | |
507 | } | |
508 | ||
509 | /* serial core request to flush & disable uart */ | |
510 | static void pic32_uart_shutdown(struct uart_port *port) | |
511 | { | |
512 | struct pic32_sport *sport = to_pic32_sport(port); | |
513 | unsigned long flags; | |
514 | ||
515 | /* disable uart */ | |
516 | spin_lock_irqsave(&port->lock, flags); | |
517 | pic32_uart_dsbl_and_mask(port); | |
518 | spin_unlock_irqrestore(&port->lock, flags); | |
519 | pic32_disable_clock(sport); | |
520 | ||
521 | /* free all 3 interrupts for this UART */ | |
522 | free_irq(sport->irq_fault, port); | |
523 | free_irq(sport->irq_tx, port); | |
524 | free_irq(sport->irq_rx, port); | |
525 | } | |
526 | ||
527 | /* serial core request to change current uart setting */ | |
528 | static void pic32_uart_set_termios(struct uart_port *port, | |
529 | struct ktermios *new, | |
530 | struct ktermios *old) | |
531 | { | |
532 | struct pic32_sport *sport = to_pic32_sport(port); | |
533 | unsigned int baud; | |
534 | unsigned int quot; | |
535 | unsigned long flags; | |
536 | ||
537 | spin_lock_irqsave(&port->lock, flags); | |
538 | ||
539 | /* disable uart and mask all interrupts while changing speed */ | |
540 | pic32_uart_dsbl_and_mask(port); | |
541 | ||
542 | /* stop bit options */ | |
543 | if (new->c_cflag & CSTOPB) | |
544 | pic32_uart_writel(sport, PIC32_SET(PIC32_UART_MODE), | |
545 | PIC32_UART_MODE_STSEL); | |
546 | else | |
547 | pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE), | |
548 | PIC32_UART_MODE_STSEL); | |
549 | ||
550 | /* parity options */ | |
551 | if (new->c_cflag & PARENB) { | |
552 | if (new->c_cflag & PARODD) { | |
553 | pic32_uart_writel(sport, PIC32_SET(PIC32_UART_MODE), | |
554 | PIC32_UART_MODE_PDSEL1); | |
555 | pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE), | |
556 | PIC32_UART_MODE_PDSEL0); | |
557 | } else { | |
558 | pic32_uart_writel(sport, PIC32_SET(PIC32_UART_MODE), | |
559 | PIC32_UART_MODE_PDSEL0); | |
560 | pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE), | |
561 | PIC32_UART_MODE_PDSEL1); | |
562 | } | |
563 | } else { | |
564 | pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE), | |
565 | PIC32_UART_MODE_PDSEL1 | | |
566 | PIC32_UART_MODE_PDSEL0); | |
567 | } | |
568 | /* if hw flow ctrl, then the pins must be specified in device tree */ | |
569 | if ((new->c_cflag & CRTSCTS) && sport->hw_flow_ctrl) { | |
570 | /* enable hardware flow control */ | |
571 | pic32_uart_writel(sport, PIC32_SET(PIC32_UART_MODE), | |
572 | PIC32_UART_MODE_UEN1); | |
573 | pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE), | |
574 | PIC32_UART_MODE_UEN0); | |
575 | pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE), | |
576 | PIC32_UART_MODE_RTSMD); | |
577 | } else { | |
578 | /* disable hardware flow control */ | |
579 | pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE), | |
580 | PIC32_UART_MODE_UEN1); | |
581 | pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE), | |
582 | PIC32_UART_MODE_UEN0); | |
583 | pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE), | |
584 | PIC32_UART_MODE_RTSMD); | |
585 | } | |
586 | ||
587 | /* Always 8-bit */ | |
588 | new->c_cflag |= CS8; | |
589 | ||
590 | /* Mark/Space parity is not supported */ | |
591 | new->c_cflag &= ~CMSPAR; | |
592 | ||
593 | /* update baud */ | |
594 | baud = uart_get_baud_rate(port, new, old, 0, port->uartclk / 16); | |
595 | quot = uart_get_divisor(port, baud) - 1; | |
596 | pic32_uart_writel(sport, PIC32_UART_BRG, quot); | |
597 | uart_update_timeout(port, new->c_cflag, baud); | |
598 | ||
599 | if (tty_termios_baud_rate(new)) | |
600 | tty_termios_encode_baud_rate(new, baud, baud); | |
601 | ||
602 | /* enable uart */ | |
603 | pic32_uart_en_and_unmask(port); | |
604 | ||
605 | spin_unlock_irqrestore(&port->lock, flags); | |
606 | } | |
607 | ||
608 | /* serial core request to claim uart iomem */ | |
609 | static int pic32_uart_request_port(struct uart_port *port) | |
610 | { | |
611 | struct platform_device *pdev = to_platform_device(port->dev); | |
612 | struct resource *res_mem; | |
613 | ||
614 | res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
615 | if (unlikely(!res_mem)) | |
616 | return -EINVAL; | |
617 | ||
618 | if (!request_mem_region(port->mapbase, resource_size(res_mem), | |
619 | "pic32_uart_mem")) | |
620 | return -EBUSY; | |
621 | ||
622 | port->membase = devm_ioremap_nocache(port->dev, port->mapbase, | |
623 | resource_size(res_mem)); | |
624 | if (!port->membase) { | |
625 | dev_err(port->dev, "Unable to map registers\n"); | |
626 | release_mem_region(port->mapbase, resource_size(res_mem)); | |
627 | return -ENOMEM; | |
628 | } | |
629 | ||
630 | return 0; | |
631 | } | |
632 | ||
633 | /* serial core request to release uart iomem */ | |
634 | static void pic32_uart_release_port(struct uart_port *port) | |
635 | { | |
636 | struct platform_device *pdev = to_platform_device(port->dev); | |
637 | struct resource *res_mem; | |
638 | unsigned int res_size; | |
639 | ||
640 | res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
641 | if (unlikely(!res_mem)) | |
642 | return; | |
643 | res_size = resource_size(res_mem); | |
644 | ||
645 | release_mem_region(port->mapbase, res_size); | |
646 | } | |
647 | ||
648 | /* serial core request to do any port required auto-configuration */ | |
649 | static void pic32_uart_config_port(struct uart_port *port, int flags) | |
650 | { | |
651 | if (flags & UART_CONFIG_TYPE) { | |
652 | if (pic32_uart_request_port(port)) | |
653 | return; | |
654 | port->type = PORT_PIC32; | |
655 | } | |
656 | } | |
657 | ||
658 | /* serial core request to check that port information in serinfo are suitable */ | |
659 | static int pic32_uart_verify_port(struct uart_port *port, | |
660 | struct serial_struct *serinfo) | |
661 | { | |
662 | if (port->type != PORT_PIC32) | |
663 | return -EINVAL; | |
664 | if (port->irq != serinfo->irq) | |
665 | return -EINVAL; | |
666 | if (port->iotype != serinfo->io_type) | |
667 | return -EINVAL; | |
668 | if (port->mapbase != (unsigned long)serinfo->iomem_base) | |
669 | return -EINVAL; | |
670 | ||
671 | return 0; | |
672 | } | |
673 | ||
674 | /* serial core callbacks */ | |
675 | static const struct uart_ops pic32_uart_ops = { | |
676 | .tx_empty = pic32_uart_tx_empty, | |
677 | .get_mctrl = pic32_uart_get_mctrl, | |
678 | .set_mctrl = pic32_uart_set_mctrl, | |
679 | .start_tx = pic32_uart_start_tx, | |
680 | .stop_tx = pic32_uart_stop_tx, | |
681 | .stop_rx = pic32_uart_stop_rx, | |
682 | .break_ctl = pic32_uart_break_ctl, | |
683 | .startup = pic32_uart_startup, | |
684 | .shutdown = pic32_uart_shutdown, | |
685 | .set_termios = pic32_uart_set_termios, | |
686 | .type = pic32_uart_type, | |
687 | .release_port = pic32_uart_release_port, | |
688 | .request_port = pic32_uart_request_port, | |
689 | .config_port = pic32_uart_config_port, | |
690 | .verify_port = pic32_uart_verify_port, | |
691 | }; | |
692 | ||
693 | #ifdef CONFIG_SERIAL_PIC32_CONSOLE | |
694 | /* output given char */ | |
695 | static void pic32_console_putchar(struct uart_port *port, int ch) | |
696 | { | |
697 | struct pic32_sport *sport = to_pic32_sport(port); | |
698 | ||
699 | if (!(pic32_uart_readl(sport, PIC32_UART_MODE) & PIC32_UART_MODE_ON)) | |
700 | return; | |
701 | ||
702 | if (!(pic32_uart_readl(sport, PIC32_UART_STA) & PIC32_UART_STA_UTXEN)) | |
703 | return; | |
704 | ||
705 | /* wait for tx empty */ | |
706 | pic32_wait_deplete_txbuf(sport); | |
707 | ||
708 | pic32_uart_writel(sport, PIC32_UART_TX, ch & 0xff); | |
709 | } | |
710 | ||
711 | /* console core request to output given string */ | |
712 | static void pic32_console_write(struct console *co, const char *s, | |
713 | unsigned int count) | |
714 | { | |
715 | struct pic32_sport *sport = pic32_sports[co->index]; | |
716 | struct uart_port *port = pic32_get_port(sport); | |
717 | ||
718 | /* call uart helper to deal with \r\n */ | |
719 | uart_console_write(port, s, count, pic32_console_putchar); | |
720 | } | |
721 | ||
722 | /* console core request to setup given console, find matching uart | |
723 | * port and setup it. | |
724 | */ | |
725 | static int pic32_console_setup(struct console *co, char *options) | |
726 | { | |
727 | struct pic32_sport *sport; | |
728 | struct uart_port *port = NULL; | |
729 | int baud = 115200; | |
730 | int bits = 8; | |
731 | int parity = 'n'; | |
732 | int flow = 'n'; | |
733 | int ret = 0; | |
734 | ||
735 | if (unlikely(co->index < 0 || co->index >= PIC32_MAX_UARTS)) | |
736 | return -ENODEV; | |
737 | ||
738 | sport = pic32_sports[co->index]; | |
739 | if (!sport) | |
740 | return -ENODEV; | |
741 | port = pic32_get_port(sport); | |
742 | ||
743 | ret = pic32_enable_clock(sport); | |
744 | if (ret) | |
745 | return ret; | |
746 | ||
747 | if (options) | |
748 | uart_parse_options(options, &baud, &parity, &bits, &flow); | |
749 | ||
750 | return uart_set_options(port, co, baud, parity, bits, flow); | |
751 | } | |
752 | ||
753 | static struct uart_driver pic32_uart_driver; | |
754 | static struct console pic32_console = { | |
755 | .name = PIC32_SDEV_NAME, | |
756 | .write = pic32_console_write, | |
757 | .device = uart_console_device, | |
758 | .setup = pic32_console_setup, | |
759 | .flags = CON_PRINTBUFFER, | |
760 | .index = -1, | |
761 | .data = &pic32_uart_driver, | |
762 | }; | |
763 | #define PIC32_SCONSOLE (&pic32_console) | |
764 | ||
765 | static int __init pic32_console_init(void) | |
766 | { | |
767 | register_console(&pic32_console); | |
768 | return 0; | |
769 | } | |
770 | console_initcall(pic32_console_init); | |
771 | ||
772 | static inline bool is_pic32_console_port(struct uart_port *port) | |
773 | { | |
774 | return port->cons && port->cons->index == port->line; | |
775 | } | |
776 | ||
777 | /* | |
778 | * Late console initialization. | |
779 | */ | |
780 | static int __init pic32_late_console_init(void) | |
781 | { | |
782 | if (!(pic32_console.flags & CON_ENABLED)) | |
783 | register_console(&pic32_console); | |
784 | ||
785 | return 0; | |
786 | } | |
787 | ||
788 | core_initcall(pic32_late_console_init); | |
789 | ||
790 | #else | |
791 | #define PIC32_SCONSOLE NULL | |
792 | #endif | |
793 | ||
794 | static struct uart_driver pic32_uart_driver = { | |
795 | .owner = THIS_MODULE, | |
796 | .driver_name = PIC32_DEV_NAME, | |
797 | .dev_name = PIC32_SDEV_NAME, | |
798 | .nr = PIC32_MAX_UARTS, | |
799 | .cons = PIC32_SCONSOLE, | |
800 | }; | |
801 | ||
802 | static int pic32_uart_probe(struct platform_device *pdev) | |
803 | { | |
804 | struct device_node *np = pdev->dev.of_node; | |
805 | struct pic32_sport *sport; | |
806 | int uart_idx = 0; | |
807 | struct resource *res_mem; | |
808 | struct uart_port *port; | |
809 | int ret; | |
810 | ||
811 | uart_idx = of_alias_get_id(np, "serial"); | |
812 | if (uart_idx < 0 || uart_idx >= PIC32_MAX_UARTS) | |
813 | return -EINVAL; | |
814 | ||
815 | res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
816 | if (!res_mem) | |
817 | return -EINVAL; | |
818 | ||
819 | sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL); | |
820 | if (!sport) | |
821 | return -ENOMEM; | |
822 | ||
823 | sport->idx = uart_idx; | |
824 | sport->irq_fault = irq_of_parse_and_map(np, 0); | |
825 | sport->irqflags_fault = IRQF_NO_THREAD; | |
826 | sport->irq_rx = irq_of_parse_and_map(np, 1); | |
827 | sport->irqflags_rx = IRQF_NO_THREAD; | |
828 | sport->irq_tx = irq_of_parse_and_map(np, 2); | |
829 | sport->irqflags_tx = IRQF_NO_THREAD; | |
830 | sport->clk = devm_clk_get(&pdev->dev, NULL); | |
831 | sport->cts_gpio = -EINVAL; | |
832 | sport->dev = &pdev->dev; | |
833 | ||
834 | /* Hardware flow control: gpios | |
835 | * !Note: Basically, CTS is needed for reading the status. | |
836 | */ | |
837 | sport->hw_flow_ctrl = false; | |
838 | sport->cts_gpio = of_get_named_gpio(np, "cts-gpios", 0); | |
839 | if (gpio_is_valid(sport->cts_gpio)) { | |
840 | sport->hw_flow_ctrl = true; | |
841 | ||
842 | ret = devm_gpio_request(sport->dev, | |
843 | sport->cts_gpio, "CTS"); | |
844 | if (ret) { | |
845 | dev_err(&pdev->dev, | |
846 | "error requesting CTS GPIO\n"); | |
847 | goto err; | |
848 | } | |
849 | ||
850 | ret = gpio_direction_input(sport->cts_gpio); | |
851 | if (ret) { | |
852 | dev_err(&pdev->dev, "error setting CTS GPIO\n"); | |
853 | goto err; | |
854 | } | |
855 | } | |
856 | ||
857 | pic32_sports[uart_idx] = sport; | |
858 | port = &sport->port; | |
859 | memset(port, 0, sizeof(*port)); | |
860 | port->iotype = UPIO_MEM; | |
861 | port->mapbase = res_mem->start; | |
862 | port->ops = &pic32_uart_ops; | |
863 | port->flags = UPF_BOOT_AUTOCONF; | |
864 | port->dev = &pdev->dev; | |
865 | port->fifosize = PIC32_UART_TX_FIFO_DEPTH; | |
866 | port->uartclk = clk_get_rate(sport->clk); | |
867 | port->line = uart_idx; | |
868 | ||
869 | ret = uart_add_one_port(&pic32_uart_driver, port); | |
870 | if (ret) { | |
871 | port->membase = NULL; | |
872 | dev_err(port->dev, "%s: uart add port error!\n", __func__); | |
873 | goto err; | |
874 | } | |
875 | ||
876 | #ifdef CONFIG_SERIAL_PIC32_CONSOLE | |
877 | if (is_pic32_console_port(port) && | |
878 | (pic32_console.flags & CON_ENABLED)) { | |
879 | /* The peripheral clock has been enabled by console_setup, | |
880 | * so disable it till the port is used. | |
881 | */ | |
882 | pic32_disable_clock(sport); | |
883 | } | |
884 | #endif | |
885 | ||
886 | platform_set_drvdata(pdev, port); | |
887 | ||
888 | dev_info(&pdev->dev, "%s: uart(%d) driver initialized.\n", | |
889 | __func__, uart_idx); | |
890 | ||
891 | return 0; | |
892 | err: | |
893 | /* automatic unroll of sport and gpios */ | |
894 | return ret; | |
895 | } | |
896 | ||
897 | static int pic32_uart_remove(struct platform_device *pdev) | |
898 | { | |
899 | struct uart_port *port = platform_get_drvdata(pdev); | |
900 | struct pic32_sport *sport = to_pic32_sport(port); | |
901 | ||
902 | uart_remove_one_port(&pic32_uart_driver, port); | |
903 | pic32_disable_clock(sport); | |
904 | platform_set_drvdata(pdev, NULL); | |
905 | pic32_sports[sport->idx] = NULL; | |
906 | ||
907 | /* automatic unroll of sport and gpios */ | |
908 | return 0; | |
909 | } | |
910 | ||
911 | static const struct of_device_id pic32_serial_dt_ids[] = { | |
912 | { .compatible = "microchip,pic32mzda-uart" }, | |
913 | { /* sentinel */ } | |
914 | }; | |
915 | MODULE_DEVICE_TABLE(of, pic32_serial_dt_ids); | |
916 | ||
917 | static struct platform_driver pic32_uart_platform_driver = { | |
918 | .probe = pic32_uart_probe, | |
919 | .remove = pic32_uart_remove, | |
920 | .driver = { | |
921 | .name = PIC32_DEV_NAME, | |
922 | .of_match_table = of_match_ptr(pic32_serial_dt_ids), | |
923 | }, | |
924 | }; | |
925 | ||
926 | static int __init pic32_uart_init(void) | |
927 | { | |
928 | int ret; | |
929 | ||
930 | ret = uart_register_driver(&pic32_uart_driver); | |
931 | if (ret) { | |
932 | pr_err("failed to register %s:%d\n", | |
933 | pic32_uart_driver.driver_name, ret); | |
934 | return ret; | |
935 | } | |
936 | ||
937 | ret = platform_driver_register(&pic32_uart_platform_driver); | |
938 | if (ret) { | |
939 | pr_err("fail to register pic32 uart\n"); | |
940 | uart_unregister_driver(&pic32_uart_driver); | |
941 | } | |
942 | ||
943 | return ret; | |
944 | } | |
945 | arch_initcall(pic32_uart_init); | |
946 | ||
947 | static void __exit pic32_uart_exit(void) | |
948 | { | |
949 | #ifdef CONFIG_SERIAL_PIC32_CONSOLE | |
950 | unregister_console(&pic32_console); | |
951 | #endif | |
952 | platform_driver_unregister(&pic32_uart_platform_driver); | |
953 | uart_unregister_driver(&pic32_uart_driver); | |
954 | } | |
955 | module_exit(pic32_uart_exit); | |
956 | ||
957 | MODULE_AUTHOR("Sorin-Andrei Pistirica <andrei.pistirica@microchip.com>"); | |
958 | MODULE_DESCRIPTION("Microchip PIC32 integrated serial port driver"); | |
959 | MODULE_LICENSE("GPL v2"); |