Commit | Line | Data |
---|---|---|
3c6a4832 TM |
1 | /* |
2 | *Copyright (C) 2010 OKI SEMICONDUCTOR CO., LTD. | |
3 | * | |
4 | *This program is free software; you can redistribute it and/or modify | |
5 | *it under the terms of the GNU General Public License as published by | |
6 | *the Free Software Foundation; version 2 of the License. | |
7 | * | |
8 | *This program is distributed in the hope that it will be useful, | |
9 | *but WITHOUT ANY WARRANTY; without even the implied warranty of | |
10 | *MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
11 | *GNU General Public License for more details. | |
12 | * | |
13 | *You should have received a copy of the GNU General Public License | |
14 | *along with this program; if not, write to the Free Software | |
15 | *Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. | |
16 | */ | |
17 | #include <linux/serial_reg.h> | |
18 | #include <linux/pci.h> | |
19 | #include <linux/module.h> | |
20 | #include <linux/pci.h> | |
21 | #include <linux/serial_core.h> | |
22 | #include <linux/interrupt.h> | |
23 | #include <linux/io.h> | |
24 | ||
25 | #include <linux/dmaengine.h> | |
26 | #include <linux/pch_dma.h> | |
27 | ||
28 | enum { | |
29 | PCH_UART_HANDLED_RX_INT_SHIFT, | |
30 | PCH_UART_HANDLED_TX_INT_SHIFT, | |
31 | PCH_UART_HANDLED_RX_ERR_INT_SHIFT, | |
32 | PCH_UART_HANDLED_RX_TRG_INT_SHIFT, | |
33 | PCH_UART_HANDLED_MS_INT_SHIFT, | |
34 | }; | |
35 | ||
36 | enum { | |
37 | PCH_UART_8LINE, | |
38 | PCH_UART_2LINE, | |
39 | }; | |
40 | ||
41 | #define PCH_UART_DRIVER_DEVICE "ttyPCH" | |
42 | ||
4564e1ef TM |
43 | /* Set the max number of UART port |
44 | * Intel EG20T PCH: 4 port | |
45 | * OKI SEMICONDUCTOR ML7213 IOH: 3 port | |
46 | */ | |
47 | #define PCH_UART_NR 4 | |
3c6a4832 TM |
48 | |
49 | #define PCH_UART_HANDLED_RX_INT (1<<((PCH_UART_HANDLED_RX_INT_SHIFT)<<1)) | |
50 | #define PCH_UART_HANDLED_TX_INT (1<<((PCH_UART_HANDLED_TX_INT_SHIFT)<<1)) | |
51 | #define PCH_UART_HANDLED_RX_ERR_INT (1<<((\ | |
52 | PCH_UART_HANDLED_RX_ERR_INT_SHIFT)<<1)) | |
53 | #define PCH_UART_HANDLED_RX_TRG_INT (1<<((\ | |
54 | PCH_UART_HANDLED_RX_TRG_INT_SHIFT)<<1)) | |
55 | #define PCH_UART_HANDLED_MS_INT (1<<((PCH_UART_HANDLED_MS_INT_SHIFT)<<1)) | |
56 | ||
57 | #define PCH_UART_RBR 0x00 | |
58 | #define PCH_UART_THR 0x00 | |
59 | ||
60 | #define PCH_UART_IER_MASK (PCH_UART_IER_ERBFI|PCH_UART_IER_ETBEI|\ | |
61 | PCH_UART_IER_ELSI|PCH_UART_IER_EDSSI) | |
62 | #define PCH_UART_IER_ERBFI 0x00000001 | |
63 | #define PCH_UART_IER_ETBEI 0x00000002 | |
64 | #define PCH_UART_IER_ELSI 0x00000004 | |
65 | #define PCH_UART_IER_EDSSI 0x00000008 | |
66 | ||
67 | #define PCH_UART_IIR_IP 0x00000001 | |
68 | #define PCH_UART_IIR_IID 0x00000006 | |
69 | #define PCH_UART_IIR_MSI 0x00000000 | |
70 | #define PCH_UART_IIR_TRI 0x00000002 | |
71 | #define PCH_UART_IIR_RRI 0x00000004 | |
72 | #define PCH_UART_IIR_REI 0x00000006 | |
73 | #define PCH_UART_IIR_TOI 0x00000008 | |
74 | #define PCH_UART_IIR_FIFO256 0x00000020 | |
75 | #define PCH_UART_IIR_FIFO64 PCH_UART_IIR_FIFO256 | |
76 | #define PCH_UART_IIR_FE 0x000000C0 | |
77 | ||
78 | #define PCH_UART_FCR_FIFOE 0x00000001 | |
79 | #define PCH_UART_FCR_RFR 0x00000002 | |
80 | #define PCH_UART_FCR_TFR 0x00000004 | |
81 | #define PCH_UART_FCR_DMS 0x00000008 | |
82 | #define PCH_UART_FCR_FIFO256 0x00000020 | |
83 | #define PCH_UART_FCR_RFTL 0x000000C0 | |
84 | ||
85 | #define PCH_UART_FCR_RFTL1 0x00000000 | |
86 | #define PCH_UART_FCR_RFTL64 0x00000040 | |
87 | #define PCH_UART_FCR_RFTL128 0x00000080 | |
88 | #define PCH_UART_FCR_RFTL224 0x000000C0 | |
89 | #define PCH_UART_FCR_RFTL16 PCH_UART_FCR_RFTL64 | |
90 | #define PCH_UART_FCR_RFTL32 PCH_UART_FCR_RFTL128 | |
91 | #define PCH_UART_FCR_RFTL56 PCH_UART_FCR_RFTL224 | |
92 | #define PCH_UART_FCR_RFTL4 PCH_UART_FCR_RFTL64 | |
93 | #define PCH_UART_FCR_RFTL8 PCH_UART_FCR_RFTL128 | |
94 | #define PCH_UART_FCR_RFTL14 PCH_UART_FCR_RFTL224 | |
95 | #define PCH_UART_FCR_RFTL_SHIFT 6 | |
96 | ||
97 | #define PCH_UART_LCR_WLS 0x00000003 | |
98 | #define PCH_UART_LCR_STB 0x00000004 | |
99 | #define PCH_UART_LCR_PEN 0x00000008 | |
100 | #define PCH_UART_LCR_EPS 0x00000010 | |
101 | #define PCH_UART_LCR_SP 0x00000020 | |
102 | #define PCH_UART_LCR_SB 0x00000040 | |
103 | #define PCH_UART_LCR_DLAB 0x00000080 | |
104 | #define PCH_UART_LCR_NP 0x00000000 | |
105 | #define PCH_UART_LCR_OP PCH_UART_LCR_PEN | |
106 | #define PCH_UART_LCR_EP (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS) | |
107 | #define PCH_UART_LCR_1P (PCH_UART_LCR_PEN | PCH_UART_LCR_SP) | |
108 | #define PCH_UART_LCR_0P (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS |\ | |
109 | PCH_UART_LCR_SP) | |
110 | ||
111 | #define PCH_UART_LCR_5BIT 0x00000000 | |
112 | #define PCH_UART_LCR_6BIT 0x00000001 | |
113 | #define PCH_UART_LCR_7BIT 0x00000002 | |
114 | #define PCH_UART_LCR_8BIT 0x00000003 | |
115 | ||
116 | #define PCH_UART_MCR_DTR 0x00000001 | |
117 | #define PCH_UART_MCR_RTS 0x00000002 | |
118 | #define PCH_UART_MCR_OUT 0x0000000C | |
119 | #define PCH_UART_MCR_LOOP 0x00000010 | |
120 | #define PCH_UART_MCR_AFE 0x00000020 | |
121 | ||
122 | #define PCH_UART_LSR_DR 0x00000001 | |
123 | #define PCH_UART_LSR_ERR (1<<7) | |
124 | ||
125 | #define PCH_UART_MSR_DCTS 0x00000001 | |
126 | #define PCH_UART_MSR_DDSR 0x00000002 | |
127 | #define PCH_UART_MSR_TERI 0x00000004 | |
128 | #define PCH_UART_MSR_DDCD 0x00000008 | |
129 | #define PCH_UART_MSR_CTS 0x00000010 | |
130 | #define PCH_UART_MSR_DSR 0x00000020 | |
131 | #define PCH_UART_MSR_RI 0x00000040 | |
132 | #define PCH_UART_MSR_DCD 0x00000080 | |
133 | #define PCH_UART_MSR_DELTA (PCH_UART_MSR_DCTS | PCH_UART_MSR_DDSR |\ | |
134 | PCH_UART_MSR_TERI | PCH_UART_MSR_DDCD) | |
135 | ||
136 | #define PCH_UART_DLL 0x00 | |
137 | #define PCH_UART_DLM 0x01 | |
138 | ||
139 | #define DIV_ROUND(a, b) (((a) + ((b)/2)) / (b)) | |
140 | ||
141 | #define PCH_UART_IID_RLS (PCH_UART_IIR_REI) | |
142 | #define PCH_UART_IID_RDR (PCH_UART_IIR_RRI) | |
143 | #define PCH_UART_IID_RDR_TO (PCH_UART_IIR_RRI | PCH_UART_IIR_TOI) | |
144 | #define PCH_UART_IID_THRE (PCH_UART_IIR_TRI) | |
145 | #define PCH_UART_IID_MS (PCH_UART_IIR_MSI) | |
146 | ||
147 | #define PCH_UART_HAL_PARITY_NONE (PCH_UART_LCR_NP) | |
148 | #define PCH_UART_HAL_PARITY_ODD (PCH_UART_LCR_OP) | |
149 | #define PCH_UART_HAL_PARITY_EVEN (PCH_UART_LCR_EP) | |
150 | #define PCH_UART_HAL_PARITY_FIX1 (PCH_UART_LCR_1P) | |
151 | #define PCH_UART_HAL_PARITY_FIX0 (PCH_UART_LCR_0P) | |
152 | #define PCH_UART_HAL_5BIT (PCH_UART_LCR_5BIT) | |
153 | #define PCH_UART_HAL_6BIT (PCH_UART_LCR_6BIT) | |
154 | #define PCH_UART_HAL_7BIT (PCH_UART_LCR_7BIT) | |
155 | #define PCH_UART_HAL_8BIT (PCH_UART_LCR_8BIT) | |
156 | #define PCH_UART_HAL_STB1 0 | |
157 | #define PCH_UART_HAL_STB2 (PCH_UART_LCR_STB) | |
158 | ||
159 | #define PCH_UART_HAL_CLR_TX_FIFO (PCH_UART_FCR_TFR) | |
160 | #define PCH_UART_HAL_CLR_RX_FIFO (PCH_UART_FCR_RFR) | |
161 | #define PCH_UART_HAL_CLR_ALL_FIFO (PCH_UART_HAL_CLR_TX_FIFO | \ | |
162 | PCH_UART_HAL_CLR_RX_FIFO) | |
163 | ||
164 | #define PCH_UART_HAL_DMA_MODE0 0 | |
165 | #define PCH_UART_HAL_FIFO_DIS 0 | |
166 | #define PCH_UART_HAL_FIFO16 (PCH_UART_FCR_FIFOE) | |
167 | #define PCH_UART_HAL_FIFO256 (PCH_UART_FCR_FIFOE | \ | |
168 | PCH_UART_FCR_FIFO256) | |
169 | #define PCH_UART_HAL_FIFO64 (PCH_UART_HAL_FIFO256) | |
170 | #define PCH_UART_HAL_TRIGGER1 (PCH_UART_FCR_RFTL1) | |
171 | #define PCH_UART_HAL_TRIGGER64 (PCH_UART_FCR_RFTL64) | |
172 | #define PCH_UART_HAL_TRIGGER128 (PCH_UART_FCR_RFTL128) | |
173 | #define PCH_UART_HAL_TRIGGER224 (PCH_UART_FCR_RFTL224) | |
174 | #define PCH_UART_HAL_TRIGGER16 (PCH_UART_FCR_RFTL16) | |
175 | #define PCH_UART_HAL_TRIGGER32 (PCH_UART_FCR_RFTL32) | |
176 | #define PCH_UART_HAL_TRIGGER56 (PCH_UART_FCR_RFTL56) | |
177 | #define PCH_UART_HAL_TRIGGER4 (PCH_UART_FCR_RFTL4) | |
178 | #define PCH_UART_HAL_TRIGGER8 (PCH_UART_FCR_RFTL8) | |
179 | #define PCH_UART_HAL_TRIGGER14 (PCH_UART_FCR_RFTL14) | |
180 | #define PCH_UART_HAL_TRIGGER_L (PCH_UART_FCR_RFTL64) | |
181 | #define PCH_UART_HAL_TRIGGER_M (PCH_UART_FCR_RFTL128) | |
182 | #define PCH_UART_HAL_TRIGGER_H (PCH_UART_FCR_RFTL224) | |
183 | ||
184 | #define PCH_UART_HAL_RX_INT (PCH_UART_IER_ERBFI) | |
185 | #define PCH_UART_HAL_TX_INT (PCH_UART_IER_ETBEI) | |
186 | #define PCH_UART_HAL_RX_ERR_INT (PCH_UART_IER_ELSI) | |
187 | #define PCH_UART_HAL_MS_INT (PCH_UART_IER_EDSSI) | |
188 | #define PCH_UART_HAL_ALL_INT (PCH_UART_IER_MASK) | |
189 | ||
190 | #define PCH_UART_HAL_DTR (PCH_UART_MCR_DTR) | |
191 | #define PCH_UART_HAL_RTS (PCH_UART_MCR_RTS) | |
192 | #define PCH_UART_HAL_OUT (PCH_UART_MCR_OUT) | |
193 | #define PCH_UART_HAL_LOOP (PCH_UART_MCR_LOOP) | |
194 | #define PCH_UART_HAL_AFE (PCH_UART_MCR_AFE) | |
195 | ||
4564e1ef TM |
196 | #define PCI_VENDOR_ID_ROHM 0x10DB |
197 | ||
3c6a4832 TM |
198 | struct pch_uart_buffer { |
199 | unsigned char *buf; | |
200 | int size; | |
201 | }; | |
202 | ||
203 | struct eg20t_port { | |
204 | struct uart_port port; | |
205 | int port_type; | |
206 | void __iomem *membase; | |
207 | resource_size_t mapbase; | |
208 | unsigned int iobase; | |
209 | struct pci_dev *pdev; | |
210 | int fifo_size; | |
211 | int base_baud; | |
212 | int start_tx; | |
213 | int start_rx; | |
214 | int tx_empty; | |
215 | int int_dis_flag; | |
216 | int trigger; | |
217 | int trigger_level; | |
218 | struct pch_uart_buffer rxbuf; | |
219 | unsigned int dmsr; | |
220 | unsigned int fcr; | |
221 | unsigned int use_dma; | |
222 | unsigned int use_dma_flag; | |
223 | struct dma_async_tx_descriptor *desc_tx; | |
224 | struct dma_async_tx_descriptor *desc_rx; | |
225 | struct pch_dma_slave param_tx; | |
226 | struct pch_dma_slave param_rx; | |
227 | struct dma_chan *chan_tx; | |
228 | struct dma_chan *chan_rx; | |
da3564ee TM |
229 | struct scatterlist *sg_tx_p; |
230 | int nent; | |
3c6a4832 TM |
231 | struct scatterlist sg_rx; |
232 | int tx_dma_use; | |
233 | void *rx_buf_virt; | |
234 | dma_addr_t rx_buf_dma; | |
235 | }; | |
236 | ||
237 | static unsigned int default_baud = 9600; | |
238 | static const int trigger_level_256[4] = { 1, 64, 128, 224 }; | |
239 | static const int trigger_level_64[4] = { 1, 16, 32, 56 }; | |
240 | static const int trigger_level_16[4] = { 1, 4, 8, 14 }; | |
241 | static const int trigger_level_1[4] = { 1, 1, 1, 1 }; | |
242 | ||
243 | static void pch_uart_hal_request(struct pci_dev *pdev, int fifosize, | |
244 | int base_baud) | |
245 | { | |
246 | struct eg20t_port *priv = pci_get_drvdata(pdev); | |
247 | ||
248 | priv->trigger_level = 1; | |
249 | priv->fcr = 0; | |
250 | } | |
251 | ||
252 | static unsigned int get_msr(struct eg20t_port *priv, void __iomem *base) | |
253 | { | |
254 | unsigned int msr = ioread8(base + UART_MSR); | |
255 | priv->dmsr |= msr & PCH_UART_MSR_DELTA; | |
256 | ||
257 | return msr; | |
258 | } | |
259 | ||
260 | static void pch_uart_hal_enable_interrupt(struct eg20t_port *priv, | |
261 | unsigned int flag) | |
262 | { | |
263 | u8 ier = ioread8(priv->membase + UART_IER); | |
264 | ier |= flag & PCH_UART_IER_MASK; | |
265 | iowrite8(ier, priv->membase + UART_IER); | |
266 | } | |
267 | ||
268 | static void pch_uart_hal_disable_interrupt(struct eg20t_port *priv, | |
269 | unsigned int flag) | |
270 | { | |
271 | u8 ier = ioread8(priv->membase + UART_IER); | |
272 | ier &= ~(flag & PCH_UART_IER_MASK); | |
273 | iowrite8(ier, priv->membase + UART_IER); | |
274 | } | |
275 | ||
276 | static int pch_uart_hal_set_line(struct eg20t_port *priv, int baud, | |
277 | unsigned int parity, unsigned int bits, | |
278 | unsigned int stb) | |
279 | { | |
280 | unsigned int dll, dlm, lcr; | |
281 | int div; | |
282 | ||
283 | div = DIV_ROUND(priv->base_baud / 16, baud); | |
284 | if (div < 0 || USHRT_MAX <= div) { | |
23877fdc | 285 | dev_err(priv->port.dev, "Invalid Baud(div=0x%x)\n", div); |
3c6a4832 TM |
286 | return -EINVAL; |
287 | } | |
288 | ||
289 | dll = (unsigned int)div & 0x00FFU; | |
290 | dlm = ((unsigned int)div >> 8) & 0x00FFU; | |
291 | ||
292 | if (parity & ~(PCH_UART_LCR_PEN | PCH_UART_LCR_EPS | PCH_UART_LCR_SP)) { | |
23877fdc | 293 | dev_err(priv->port.dev, "Invalid parity(0x%x)\n", parity); |
3c6a4832 TM |
294 | return -EINVAL; |
295 | } | |
296 | ||
297 | if (bits & ~PCH_UART_LCR_WLS) { | |
23877fdc | 298 | dev_err(priv->port.dev, "Invalid bits(0x%x)\n", bits); |
3c6a4832 TM |
299 | return -EINVAL; |
300 | } | |
301 | ||
302 | if (stb & ~PCH_UART_LCR_STB) { | |
23877fdc | 303 | dev_err(priv->port.dev, "Invalid STB(0x%x)\n", stb); |
3c6a4832 TM |
304 | return -EINVAL; |
305 | } | |
306 | ||
307 | lcr = parity; | |
308 | lcr |= bits; | |
309 | lcr |= stb; | |
310 | ||
23877fdc | 311 | dev_dbg(priv->port.dev, "%s:baud = %d, div = %04x, lcr = %02x (%lu)\n", |
3c6a4832 TM |
312 | __func__, baud, div, lcr, jiffies); |
313 | iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR); | |
314 | iowrite8(dll, priv->membase + PCH_UART_DLL); | |
315 | iowrite8(dlm, priv->membase + PCH_UART_DLM); | |
316 | iowrite8(lcr, priv->membase + UART_LCR); | |
317 | ||
318 | return 0; | |
319 | } | |
320 | ||
321 | static int pch_uart_hal_fifo_reset(struct eg20t_port *priv, | |
322 | unsigned int flag) | |
323 | { | |
324 | if (flag & ~(PCH_UART_FCR_TFR | PCH_UART_FCR_RFR)) { | |
23877fdc TM |
325 | dev_err(priv->port.dev, "%s:Invalid flag(0x%x)\n", |
326 | __func__, flag); | |
3c6a4832 TM |
327 | return -EINVAL; |
328 | } | |
329 | ||
330 | iowrite8(PCH_UART_FCR_FIFOE | priv->fcr, priv->membase + UART_FCR); | |
331 | iowrite8(PCH_UART_FCR_FIFOE | priv->fcr | flag, | |
332 | priv->membase + UART_FCR); | |
333 | iowrite8(priv->fcr, priv->membase + UART_FCR); | |
334 | ||
335 | return 0; | |
336 | } | |
337 | ||
338 | static int pch_uart_hal_set_fifo(struct eg20t_port *priv, | |
339 | unsigned int dmamode, | |
340 | unsigned int fifo_size, unsigned int trigger) | |
341 | { | |
342 | u8 fcr; | |
343 | ||
344 | if (dmamode & ~PCH_UART_FCR_DMS) { | |
23877fdc TM |
345 | dev_err(priv->port.dev, "%s:Invalid DMA Mode(0x%x)\n", |
346 | __func__, dmamode); | |
3c6a4832 TM |
347 | return -EINVAL; |
348 | } | |
349 | ||
350 | if (fifo_size & ~(PCH_UART_FCR_FIFOE | PCH_UART_FCR_FIFO256)) { | |
23877fdc TM |
351 | dev_err(priv->port.dev, "%s:Invalid FIFO SIZE(0x%x)\n", |
352 | __func__, fifo_size); | |
3c6a4832 TM |
353 | return -EINVAL; |
354 | } | |
355 | ||
356 | if (trigger & ~PCH_UART_FCR_RFTL) { | |
23877fdc TM |
357 | dev_err(priv->port.dev, "%s:Invalid TRIGGER(0x%x)\n", |
358 | __func__, trigger); | |
3c6a4832 TM |
359 | return -EINVAL; |
360 | } | |
361 | ||
362 | switch (priv->fifo_size) { | |
363 | case 256: | |
364 | priv->trigger_level = | |
365 | trigger_level_256[trigger >> PCH_UART_FCR_RFTL_SHIFT]; | |
366 | break; | |
367 | case 64: | |
368 | priv->trigger_level = | |
369 | trigger_level_64[trigger >> PCH_UART_FCR_RFTL_SHIFT]; | |
370 | break; | |
371 | case 16: | |
372 | priv->trigger_level = | |
373 | trigger_level_16[trigger >> PCH_UART_FCR_RFTL_SHIFT]; | |
374 | break; | |
375 | default: | |
376 | priv->trigger_level = | |
377 | trigger_level_1[trigger >> PCH_UART_FCR_RFTL_SHIFT]; | |
378 | break; | |
379 | } | |
380 | fcr = | |
381 | dmamode | fifo_size | trigger | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR; | |
382 | iowrite8(PCH_UART_FCR_FIFOE, priv->membase + UART_FCR); | |
383 | iowrite8(PCH_UART_FCR_FIFOE | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR, | |
384 | priv->membase + UART_FCR); | |
385 | iowrite8(fcr, priv->membase + UART_FCR); | |
386 | priv->fcr = fcr; | |
387 | ||
388 | return 0; | |
389 | } | |
390 | ||
391 | static u8 pch_uart_hal_get_modem(struct eg20t_port *priv) | |
392 | { | |
393 | priv->dmsr = 0; | |
394 | return get_msr(priv, priv->membase); | |
395 | } | |
396 | ||
1822076c | 397 | static void pch_uart_hal_write(struct eg20t_port *priv, |
3c6a4832 TM |
398 | const unsigned char *buf, int tx_size) |
399 | { | |
400 | int i; | |
401 | unsigned int thr; | |
402 | ||
403 | for (i = 0; i < tx_size;) { | |
404 | thr = buf[i++]; | |
405 | iowrite8(thr, priv->membase + PCH_UART_THR); | |
406 | } | |
3c6a4832 TM |
407 | } |
408 | ||
409 | static int pch_uart_hal_read(struct eg20t_port *priv, unsigned char *buf, | |
410 | int rx_size) | |
411 | { | |
412 | int i; | |
413 | u8 rbr, lsr; | |
414 | ||
415 | lsr = ioread8(priv->membase + UART_LSR); | |
416 | for (i = 0, lsr = ioread8(priv->membase + UART_LSR); | |
417 | i < rx_size && lsr & UART_LSR_DR; | |
418 | lsr = ioread8(priv->membase + UART_LSR)) { | |
419 | rbr = ioread8(priv->membase + PCH_UART_RBR); | |
420 | buf[i++] = rbr; | |
421 | } | |
422 | return i; | |
423 | } | |
424 | ||
425 | static unsigned int pch_uart_hal_get_iid(struct eg20t_port *priv) | |
426 | { | |
427 | unsigned int iir; | |
428 | int ret; | |
429 | ||
430 | iir = ioread8(priv->membase + UART_IIR); | |
431 | ret = (iir & (PCH_UART_IIR_IID | PCH_UART_IIR_TOI | PCH_UART_IIR_IP)); | |
432 | return ret; | |
433 | } | |
434 | ||
435 | static u8 pch_uart_hal_get_line_status(struct eg20t_port *priv) | |
436 | { | |
437 | return ioread8(priv->membase + UART_LSR); | |
438 | } | |
439 | ||
440 | static void pch_uart_hal_set_break(struct eg20t_port *priv, int on) | |
441 | { | |
442 | unsigned int lcr; | |
443 | ||
444 | lcr = ioread8(priv->membase + UART_LCR); | |
445 | if (on) | |
446 | lcr |= PCH_UART_LCR_SB; | |
447 | else | |
448 | lcr &= ~PCH_UART_LCR_SB; | |
449 | ||
450 | iowrite8(lcr, priv->membase + UART_LCR); | |
451 | } | |
452 | ||
453 | static int push_rx(struct eg20t_port *priv, const unsigned char *buf, | |
454 | int size) | |
455 | { | |
456 | struct uart_port *port; | |
457 | struct tty_struct *tty; | |
458 | ||
459 | port = &priv->port; | |
460 | tty = tty_port_tty_get(&port->state->port); | |
461 | if (!tty) { | |
23877fdc | 462 | dev_dbg(priv->port.dev, "%s:tty is busy now", __func__); |
3c6a4832 TM |
463 | return -EBUSY; |
464 | } | |
465 | ||
466 | tty_insert_flip_string(tty, buf, size); | |
467 | tty_flip_buffer_push(tty); | |
468 | tty_kref_put(tty); | |
469 | ||
470 | return 0; | |
471 | } | |
472 | ||
473 | static int pop_tx_x(struct eg20t_port *priv, unsigned char *buf) | |
474 | { | |
475 | int ret; | |
476 | struct uart_port *port = &priv->port; | |
477 | ||
478 | if (port->x_char) { | |
23877fdc TM |
479 | dev_dbg(priv->port.dev, "%s:X character send %02x (%lu)\n", |
480 | __func__, port->x_char, jiffies); | |
3c6a4832 TM |
481 | buf[0] = port->x_char; |
482 | port->x_char = 0; | |
483 | ret = 1; | |
484 | } else { | |
485 | ret = 0; | |
486 | } | |
487 | ||
488 | return ret; | |
489 | } | |
490 | ||
491 | static int dma_push_rx(struct eg20t_port *priv, int size) | |
492 | { | |
493 | struct tty_struct *tty; | |
494 | int room; | |
495 | struct uart_port *port = &priv->port; | |
496 | ||
497 | port = &priv->port; | |
498 | tty = tty_port_tty_get(&port->state->port); | |
499 | if (!tty) { | |
23877fdc | 500 | dev_dbg(priv->port.dev, "%s:tty is busy now", __func__); |
3c6a4832 TM |
501 | return 0; |
502 | } | |
503 | ||
504 | room = tty_buffer_request_room(tty, size); | |
505 | ||
506 | if (room < size) | |
507 | dev_warn(port->dev, "Rx overrun: dropping %u bytes\n", | |
508 | size - room); | |
509 | if (!room) | |
510 | return room; | |
511 | ||
512 | tty_insert_flip_string(tty, sg_virt(&priv->sg_rx), size); | |
513 | ||
514 | port->icount.rx += room; | |
515 | tty_kref_put(tty); | |
516 | ||
517 | return room; | |
518 | } | |
519 | ||
520 | static void pch_free_dma(struct uart_port *port) | |
521 | { | |
522 | struct eg20t_port *priv; | |
523 | priv = container_of(port, struct eg20t_port, port); | |
524 | ||
525 | if (priv->chan_tx) { | |
526 | dma_release_channel(priv->chan_tx); | |
527 | priv->chan_tx = NULL; | |
528 | } | |
529 | if (priv->chan_rx) { | |
530 | dma_release_channel(priv->chan_rx); | |
531 | priv->chan_rx = NULL; | |
532 | } | |
533 | if (sg_dma_address(&priv->sg_rx)) | |
534 | dma_free_coherent(port->dev, port->fifosize, | |
535 | sg_virt(&priv->sg_rx), | |
536 | sg_dma_address(&priv->sg_rx)); | |
537 | ||
538 | return; | |
539 | } | |
540 | ||
541 | static bool filter(struct dma_chan *chan, void *slave) | |
542 | { | |
543 | struct pch_dma_slave *param = slave; | |
544 | ||
545 | if ((chan->chan_id == param->chan_id) && (param->dma_dev == | |
546 | chan->device->dev)) { | |
547 | chan->private = param; | |
548 | return true; | |
549 | } else { | |
550 | return false; | |
551 | } | |
552 | } | |
553 | ||
554 | static void pch_request_dma(struct uart_port *port) | |
555 | { | |
556 | dma_cap_mask_t mask; | |
557 | struct dma_chan *chan; | |
558 | struct pci_dev *dma_dev; | |
559 | struct pch_dma_slave *param; | |
560 | struct eg20t_port *priv = | |
561 | container_of(port, struct eg20t_port, port); | |
562 | dma_cap_zero(mask); | |
563 | dma_cap_set(DMA_SLAVE, mask); | |
564 | ||
565 | dma_dev = pci_get_bus_and_slot(2, PCI_DEVFN(0xa, 0)); /* Get DMA's dev | |
566 | information */ | |
567 | /* Set Tx DMA */ | |
568 | param = &priv->param_tx; | |
569 | param->dma_dev = &dma_dev->dev; | |
570 | param->chan_id = priv->port.line; | |
571 | param->tx_reg = port->mapbase + UART_TX; | |
572 | chan = dma_request_channel(mask, filter, param); | |
573 | if (!chan) { | |
23877fdc TM |
574 | dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Tx)\n", |
575 | __func__); | |
3c6a4832 TM |
576 | return; |
577 | } | |
578 | priv->chan_tx = chan; | |
579 | ||
580 | /* Set Rx DMA */ | |
581 | param = &priv->param_rx; | |
582 | param->dma_dev = &dma_dev->dev; | |
583 | param->chan_id = priv->port.line + 1; /* Rx = Tx + 1 */ | |
584 | param->rx_reg = port->mapbase + UART_RX; | |
585 | chan = dma_request_channel(mask, filter, param); | |
586 | if (!chan) { | |
23877fdc TM |
587 | dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Rx)\n", |
588 | __func__); | |
3c6a4832 TM |
589 | dma_release_channel(priv->chan_tx); |
590 | return; | |
591 | } | |
592 | ||
593 | /* Get Consistent memory for DMA */ | |
594 | priv->rx_buf_virt = dma_alloc_coherent(port->dev, port->fifosize, | |
595 | &priv->rx_buf_dma, GFP_KERNEL); | |
596 | priv->chan_rx = chan; | |
597 | } | |
598 | ||
599 | static void pch_dma_rx_complete(void *arg) | |
600 | { | |
601 | struct eg20t_port *priv = arg; | |
602 | struct uart_port *port = &priv->port; | |
603 | struct tty_struct *tty = tty_port_tty_get(&port->state->port); | |
da3564ee | 604 | int count; |
3c6a4832 TM |
605 | |
606 | if (!tty) { | |
23877fdc | 607 | dev_dbg(priv->port.dev, "%s:tty is busy now", __func__); |
3c6a4832 TM |
608 | return; |
609 | } | |
610 | ||
da3564ee TM |
611 | dma_sync_sg_for_cpu(port->dev, &priv->sg_rx, 1, DMA_FROM_DEVICE); |
612 | count = dma_push_rx(priv, priv->trigger_level); | |
613 | if (count) | |
3c6a4832 | 614 | tty_flip_buffer_push(tty); |
3c6a4832 | 615 | tty_kref_put(tty); |
da3564ee TM |
616 | async_tx_ack(priv->desc_rx); |
617 | pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT); | |
3c6a4832 TM |
618 | } |
619 | ||
620 | static void pch_dma_tx_complete(void *arg) | |
621 | { | |
622 | struct eg20t_port *priv = arg; | |
623 | struct uart_port *port = &priv->port; | |
624 | struct circ_buf *xmit = &port->state->xmit; | |
da3564ee TM |
625 | struct scatterlist *sg = priv->sg_tx_p; |
626 | int i; | |
3c6a4832 | 627 | |
da3564ee TM |
628 | for (i = 0; i < priv->nent; i++, sg++) { |
629 | xmit->tail += sg_dma_len(sg); | |
630 | port->icount.tx += sg_dma_len(sg); | |
631 | } | |
3c6a4832 | 632 | xmit->tail &= UART_XMIT_SIZE - 1; |
3c6a4832 | 633 | async_tx_ack(priv->desc_tx); |
da3564ee | 634 | dma_unmap_sg(port->dev, sg, priv->nent, DMA_TO_DEVICE); |
3c6a4832 | 635 | priv->tx_dma_use = 0; |
da3564ee TM |
636 | priv->nent = 0; |
637 | kfree(priv->sg_tx_p); | |
638 | if (uart_circ_chars_pending(xmit)) | |
639 | pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT); | |
3c6a4832 TM |
640 | } |
641 | ||
1822076c | 642 | static int pop_tx(struct eg20t_port *priv, int size) |
3c6a4832 TM |
643 | { |
644 | int count = 0; | |
645 | struct uart_port *port = &priv->port; | |
646 | struct circ_buf *xmit = &port->state->xmit; | |
647 | ||
648 | if (uart_tx_stopped(port) || uart_circ_empty(xmit) || count >= size) | |
649 | goto pop_tx_end; | |
650 | ||
651 | do { | |
652 | int cnt_to_end = | |
653 | CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE); | |
654 | int sz = min(size - count, cnt_to_end); | |
1822076c | 655 | pch_uart_hal_write(priv, &xmit->buf[xmit->tail], sz); |
3c6a4832 TM |
656 | xmit->tail = (xmit->tail + sz) & (UART_XMIT_SIZE - 1); |
657 | count += sz; | |
658 | } while (!uart_circ_empty(xmit) && count < size); | |
659 | ||
660 | pop_tx_end: | |
23877fdc | 661 | dev_dbg(priv->port.dev, "%d characters. Remained %d characters.(%lu)\n", |
3c6a4832 TM |
662 | count, size - count, jiffies); |
663 | ||
664 | return count; | |
665 | } | |
666 | ||
667 | static int handle_rx_to(struct eg20t_port *priv) | |
668 | { | |
669 | struct pch_uart_buffer *buf; | |
670 | int rx_size; | |
671 | int ret; | |
672 | if (!priv->start_rx) { | |
673 | pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT); | |
674 | return 0; | |
675 | } | |
676 | buf = &priv->rxbuf; | |
677 | do { | |
678 | rx_size = pch_uart_hal_read(priv, buf->buf, buf->size); | |
679 | ret = push_rx(priv, buf->buf, rx_size); | |
680 | if (ret) | |
681 | return 0; | |
682 | } while (rx_size == buf->size); | |
683 | ||
684 | return PCH_UART_HANDLED_RX_INT; | |
685 | } | |
686 | ||
687 | static int handle_rx(struct eg20t_port *priv) | |
688 | { | |
689 | return handle_rx_to(priv); | |
690 | } | |
691 | ||
692 | static int dma_handle_rx(struct eg20t_port *priv) | |
693 | { | |
694 | struct uart_port *port = &priv->port; | |
695 | struct dma_async_tx_descriptor *desc; | |
696 | struct scatterlist *sg; | |
697 | ||
698 | priv = container_of(port, struct eg20t_port, port); | |
699 | sg = &priv->sg_rx; | |
700 | ||
701 | sg_init_table(&priv->sg_rx, 1); /* Initialize SG table */ | |
702 | ||
da3564ee | 703 | sg_dma_len(sg) = priv->trigger_level; |
3c6a4832 TM |
704 | |
705 | sg_set_page(&priv->sg_rx, virt_to_page(priv->rx_buf_virt), | |
1c518997 TM |
706 | sg_dma_len(sg), (unsigned long)priv->rx_buf_virt & |
707 | ~PAGE_MASK); | |
3c6a4832 TM |
708 | |
709 | sg_dma_address(sg) = priv->rx_buf_dma; | |
710 | ||
711 | desc = priv->chan_rx->device->device_prep_slave_sg(priv->chan_rx, | |
712 | sg, 1, DMA_FROM_DEVICE, | |
da3564ee TM |
713 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
714 | ||
3c6a4832 TM |
715 | if (!desc) |
716 | return 0; | |
717 | ||
718 | priv->desc_rx = desc; | |
719 | desc->callback = pch_dma_rx_complete; | |
720 | desc->callback_param = priv; | |
721 | desc->tx_submit(desc); | |
722 | dma_async_issue_pending(priv->chan_rx); | |
723 | ||
724 | return PCH_UART_HANDLED_RX_INT; | |
725 | } | |
726 | ||
727 | static unsigned int handle_tx(struct eg20t_port *priv) | |
728 | { | |
729 | struct uart_port *port = &priv->port; | |
730 | struct circ_buf *xmit = &port->state->xmit; | |
3c6a4832 TM |
731 | int fifo_size; |
732 | int tx_size; | |
733 | int size; | |
734 | int tx_empty; | |
735 | ||
736 | if (!priv->start_tx) { | |
23877fdc TM |
737 | dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n", |
738 | __func__, jiffies); | |
3c6a4832 TM |
739 | pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT); |
740 | priv->tx_empty = 1; | |
741 | return 0; | |
742 | } | |
743 | ||
744 | fifo_size = max(priv->fifo_size, 1); | |
745 | tx_empty = 1; | |
746 | if (pop_tx_x(priv, xmit->buf)) { | |
747 | pch_uart_hal_write(priv, xmit->buf, 1); | |
748 | port->icount.tx++; | |
749 | tx_empty = 0; | |
750 | fifo_size--; | |
751 | } | |
752 | size = min(xmit->head - xmit->tail, fifo_size); | |
da3564ee TM |
753 | if (size < 0) |
754 | size = fifo_size; | |
755 | ||
1822076c | 756 | tx_size = pop_tx(priv, size); |
3c6a4832 | 757 | if (tx_size > 0) { |
1822076c | 758 | port->icount.tx += tx_size; |
3c6a4832 TM |
759 | tx_empty = 0; |
760 | } | |
761 | ||
762 | priv->tx_empty = tx_empty; | |
763 | ||
da3564ee | 764 | if (tx_empty) { |
3c6a4832 | 765 | pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT); |
da3564ee TM |
766 | uart_write_wakeup(port); |
767 | } | |
3c6a4832 TM |
768 | |
769 | return PCH_UART_HANDLED_TX_INT; | |
770 | } | |
771 | ||
772 | static unsigned int dma_handle_tx(struct eg20t_port *priv) | |
773 | { | |
774 | struct uart_port *port = &priv->port; | |
775 | struct circ_buf *xmit = &port->state->xmit; | |
da3564ee | 776 | struct scatterlist *sg; |
3c6a4832 TM |
777 | int nent; |
778 | int fifo_size; | |
779 | int tx_empty; | |
780 | struct dma_async_tx_descriptor *desc; | |
da3564ee TM |
781 | int num; |
782 | int i; | |
783 | int bytes; | |
784 | int size; | |
785 | int rem; | |
3c6a4832 TM |
786 | |
787 | if (!priv->start_tx) { | |
23877fdc TM |
788 | dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n", |
789 | __func__, jiffies); | |
3c6a4832 TM |
790 | pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT); |
791 | priv->tx_empty = 1; | |
792 | return 0; | |
793 | } | |
794 | ||
795 | fifo_size = max(priv->fifo_size, 1); | |
796 | tx_empty = 1; | |
797 | if (pop_tx_x(priv, xmit->buf)) { | |
798 | pch_uart_hal_write(priv, xmit->buf, 1); | |
799 | port->icount.tx++; | |
800 | tx_empty = 0; | |
801 | fifo_size--; | |
802 | } | |
803 | ||
da3564ee TM |
804 | bytes = min((int)CIRC_CNT(xmit->head, xmit->tail, |
805 | UART_XMIT_SIZE), CIRC_CNT_TO_END(xmit->head, | |
806 | xmit->tail, UART_XMIT_SIZE)); | |
807 | if (!bytes) { | |
23877fdc | 808 | dev_dbg(priv->port.dev, "%s 0 bytes return\n", __func__); |
da3564ee TM |
809 | pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT); |
810 | uart_write_wakeup(port); | |
811 | return 0; | |
812 | } | |
813 | ||
814 | if (bytes > fifo_size) { | |
815 | num = bytes / fifo_size + 1; | |
816 | size = fifo_size; | |
817 | rem = bytes % fifo_size; | |
818 | } else { | |
819 | num = 1; | |
820 | size = bytes; | |
821 | rem = bytes; | |
822 | } | |
3c6a4832 | 823 | |
23877fdc TM |
824 | dev_dbg(priv->port.dev, "%s num=%d size=%d rem=%d\n", |
825 | __func__, num, size, rem); | |
826 | ||
3c6a4832 TM |
827 | priv->tx_dma_use = 1; |
828 | ||
da3564ee | 829 | priv->sg_tx_p = kzalloc(sizeof(struct scatterlist)*num, GFP_ATOMIC); |
3c6a4832 | 830 | |
da3564ee TM |
831 | sg_init_table(priv->sg_tx_p, num); /* Initialize SG table */ |
832 | sg = priv->sg_tx_p; | |
3c6a4832 | 833 | |
da3564ee TM |
834 | for (i = 0; i < num; i++, sg++) { |
835 | if (i == (num - 1)) | |
836 | sg_set_page(sg, virt_to_page(xmit->buf), | |
837 | rem, fifo_size * i); | |
838 | else | |
839 | sg_set_page(sg, virt_to_page(xmit->buf), | |
840 | size, fifo_size * i); | |
841 | } | |
842 | ||
843 | sg = priv->sg_tx_p; | |
844 | nent = dma_map_sg(port->dev, sg, num, DMA_TO_DEVICE); | |
3c6a4832 | 845 | if (!nent) { |
23877fdc | 846 | dev_err(priv->port.dev, "%s:dma_map_sg Failed\n", __func__); |
3c6a4832 TM |
847 | return 0; |
848 | } | |
da3564ee TM |
849 | priv->nent = nent; |
850 | ||
851 | for (i = 0; i < nent; i++, sg++) { | |
852 | sg->offset = (xmit->tail & (UART_XMIT_SIZE - 1)) + | |
853 | fifo_size * i; | |
854 | sg_dma_address(sg) = (sg_dma_address(sg) & | |
855 | ~(UART_XMIT_SIZE - 1)) + sg->offset; | |
856 | if (i == (nent - 1)) | |
857 | sg_dma_len(sg) = rem; | |
858 | else | |
859 | sg_dma_len(sg) = size; | |
860 | } | |
3c6a4832 TM |
861 | |
862 | desc = priv->chan_tx->device->device_prep_slave_sg(priv->chan_tx, | |
da3564ee TM |
863 | priv->sg_tx_p, nent, DMA_TO_DEVICE, |
864 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
3c6a4832 | 865 | if (!desc) { |
23877fdc TM |
866 | dev_err(priv->port.dev, "%s:device_prep_slave_sg Failed\n", |
867 | __func__); | |
3c6a4832 TM |
868 | return 0; |
869 | } | |
da3564ee | 870 | dma_sync_sg_for_device(port->dev, priv->sg_tx_p, nent, DMA_TO_DEVICE); |
3c6a4832 TM |
871 | priv->desc_tx = desc; |
872 | desc->callback = pch_dma_tx_complete; | |
873 | desc->callback_param = priv; | |
874 | ||
875 | desc->tx_submit(desc); | |
876 | ||
877 | dma_async_issue_pending(priv->chan_tx); | |
878 | ||
879 | return PCH_UART_HANDLED_TX_INT; | |
880 | } | |
881 | ||
882 | static void pch_uart_err_ir(struct eg20t_port *priv, unsigned int lsr) | |
883 | { | |
884 | u8 fcr = ioread8(priv->membase + UART_FCR); | |
885 | ||
886 | /* Reset FIFO */ | |
887 | fcr |= UART_FCR_CLEAR_RCVR; | |
888 | iowrite8(fcr, priv->membase + UART_FCR); | |
889 | ||
890 | if (lsr & PCH_UART_LSR_ERR) | |
891 | dev_err(&priv->pdev->dev, "Error data in FIFO\n"); | |
892 | ||
893 | if (lsr & UART_LSR_FE) | |
894 | dev_err(&priv->pdev->dev, "Framing Error\n"); | |
895 | ||
896 | if (lsr & UART_LSR_PE) | |
897 | dev_err(&priv->pdev->dev, "Parity Error\n"); | |
898 | ||
899 | if (lsr & UART_LSR_OE) | |
900 | dev_err(&priv->pdev->dev, "Overrun Error\n"); | |
901 | } | |
902 | ||
903 | static irqreturn_t pch_uart_interrupt(int irq, void *dev_id) | |
904 | { | |
905 | struct eg20t_port *priv = dev_id; | |
906 | unsigned int handled; | |
907 | u8 lsr; | |
908 | int ret = 0; | |
909 | unsigned int iid; | |
910 | unsigned long flags; | |
911 | ||
912 | spin_lock_irqsave(&priv->port.lock, flags); | |
913 | handled = 0; | |
914 | while ((iid = pch_uart_hal_get_iid(priv)) > 1) { | |
915 | switch (iid) { | |
916 | case PCH_UART_IID_RLS: /* Receiver Line Status */ | |
917 | lsr = pch_uart_hal_get_line_status(priv); | |
918 | if (lsr & (PCH_UART_LSR_ERR | UART_LSR_FE | | |
919 | UART_LSR_PE | UART_LSR_OE)) { | |
920 | pch_uart_err_ir(priv, lsr); | |
921 | ret = PCH_UART_HANDLED_RX_ERR_INT; | |
922 | } | |
923 | break; | |
924 | case PCH_UART_IID_RDR: /* Received Data Ready */ | |
da3564ee TM |
925 | if (priv->use_dma) { |
926 | pch_uart_hal_disable_interrupt(priv, | |
927 | PCH_UART_HAL_RX_INT); | |
3c6a4832 | 928 | ret = dma_handle_rx(priv); |
da3564ee TM |
929 | if (!ret) |
930 | pch_uart_hal_enable_interrupt(priv, | |
931 | PCH_UART_HAL_RX_INT); | |
932 | } else { | |
3c6a4832 | 933 | ret = handle_rx(priv); |
da3564ee | 934 | } |
3c6a4832 TM |
935 | break; |
936 | case PCH_UART_IID_RDR_TO: /* Received Data Ready | |
937 | (FIFO Timeout) */ | |
938 | ret = handle_rx_to(priv); | |
939 | break; | |
940 | case PCH_UART_IID_THRE: /* Transmitter Holding Register | |
941 | Empty */ | |
942 | if (priv->use_dma) | |
943 | ret = dma_handle_tx(priv); | |
944 | else | |
945 | ret = handle_tx(priv); | |
946 | break; | |
947 | case PCH_UART_IID_MS: /* Modem Status */ | |
948 | ret = PCH_UART_HANDLED_MS_INT; | |
949 | break; | |
950 | default: /* Never junp to this label */ | |
23877fdc TM |
951 | dev_err(priv->port.dev, "%s:iid=%d (%lu)\n", __func__, |
952 | iid, jiffies); | |
3c6a4832 TM |
953 | ret = -1; |
954 | break; | |
955 | } | |
956 | handled |= (unsigned int)ret; | |
957 | } | |
958 | if (handled == 0 && iid <= 1) { | |
959 | if (priv->int_dis_flag) | |
960 | priv->int_dis_flag = 0; | |
961 | } | |
962 | ||
963 | spin_unlock_irqrestore(&priv->port.lock, flags); | |
964 | return IRQ_RETVAL(handled); | |
965 | } | |
966 | ||
967 | /* This function tests whether the transmitter fifo and shifter for the port | |
968 | described by 'port' is empty. */ | |
969 | static unsigned int pch_uart_tx_empty(struct uart_port *port) | |
970 | { | |
971 | struct eg20t_port *priv; | |
972 | int ret; | |
973 | priv = container_of(port, struct eg20t_port, port); | |
974 | if (priv->tx_empty) | |
975 | ret = TIOCSER_TEMT; | |
976 | else | |
977 | ret = 0; | |
978 | ||
979 | return ret; | |
980 | } | |
981 | ||
982 | /* Returns the current state of modem control inputs. */ | |
983 | static unsigned int pch_uart_get_mctrl(struct uart_port *port) | |
984 | { | |
985 | struct eg20t_port *priv; | |
986 | u8 modem; | |
987 | unsigned int ret = 0; | |
988 | ||
989 | priv = container_of(port, struct eg20t_port, port); | |
990 | modem = pch_uart_hal_get_modem(priv); | |
991 | ||
992 | if (modem & UART_MSR_DCD) | |
993 | ret |= TIOCM_CAR; | |
994 | ||
995 | if (modem & UART_MSR_RI) | |
996 | ret |= TIOCM_RNG; | |
997 | ||
998 | if (modem & UART_MSR_DSR) | |
999 | ret |= TIOCM_DSR; | |
1000 | ||
1001 | if (modem & UART_MSR_CTS) | |
1002 | ret |= TIOCM_CTS; | |
1003 | ||
1004 | return ret; | |
1005 | } | |
1006 | ||
1007 | static void pch_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) | |
1008 | { | |
1009 | u32 mcr = 0; | |
1010 | unsigned int dat; | |
1011 | struct eg20t_port *priv = container_of(port, struct eg20t_port, port); | |
1012 | ||
1013 | if (mctrl & TIOCM_DTR) | |
1014 | mcr |= UART_MCR_DTR; | |
1015 | if (mctrl & TIOCM_RTS) | |
1016 | mcr |= UART_MCR_RTS; | |
1017 | if (mctrl & TIOCM_LOOP) | |
1018 | mcr |= UART_MCR_LOOP; | |
1019 | ||
1020 | if (mctrl) { | |
1021 | dat = pch_uart_get_mctrl(port); | |
1022 | dat |= mcr; | |
1023 | iowrite8(dat, priv->membase + UART_MCR); | |
1024 | } | |
1025 | } | |
1026 | ||
1027 | static void pch_uart_stop_tx(struct uart_port *port) | |
1028 | { | |
1029 | struct eg20t_port *priv; | |
1030 | priv = container_of(port, struct eg20t_port, port); | |
1031 | priv->start_tx = 0; | |
1032 | priv->tx_dma_use = 0; | |
1033 | } | |
1034 | ||
1035 | static void pch_uart_start_tx(struct uart_port *port) | |
1036 | { | |
1037 | struct eg20t_port *priv; | |
1038 | ||
1039 | priv = container_of(port, struct eg20t_port, port); | |
1040 | ||
23877fdc TM |
1041 | if (priv->use_dma) { |
1042 | if (priv->tx_dma_use) { | |
1043 | dev_dbg(priv->port.dev, "%s : Tx DMA is NOT empty.\n", | |
1044 | __func__); | |
3c6a4832 | 1045 | return; |
23877fdc TM |
1046 | } |
1047 | } | |
3c6a4832 TM |
1048 | |
1049 | priv->start_tx = 1; | |
1050 | pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT); | |
1051 | } | |
1052 | ||
1053 | static void pch_uart_stop_rx(struct uart_port *port) | |
1054 | { | |
1055 | struct eg20t_port *priv; | |
1056 | priv = container_of(port, struct eg20t_port, port); | |
1057 | priv->start_rx = 0; | |
1058 | pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT); | |
1059 | priv->int_dis_flag = 1; | |
1060 | } | |
1061 | ||
1062 | /* Enable the modem status interrupts. */ | |
1063 | static void pch_uart_enable_ms(struct uart_port *port) | |
1064 | { | |
1065 | struct eg20t_port *priv; | |
1066 | priv = container_of(port, struct eg20t_port, port); | |
1067 | pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_MS_INT); | |
1068 | } | |
1069 | ||
1070 | /* Control the transmission of a break signal. */ | |
1071 | static void pch_uart_break_ctl(struct uart_port *port, int ctl) | |
1072 | { | |
1073 | struct eg20t_port *priv; | |
1074 | unsigned long flags; | |
1075 | ||
1076 | priv = container_of(port, struct eg20t_port, port); | |
1077 | spin_lock_irqsave(&port->lock, flags); | |
1078 | pch_uart_hal_set_break(priv, ctl); | |
1079 | spin_unlock_irqrestore(&port->lock, flags); | |
1080 | } | |
1081 | ||
1082 | /* Grab any interrupt resources and initialise any low level driver state. */ | |
1083 | static int pch_uart_startup(struct uart_port *port) | |
1084 | { | |
1085 | struct eg20t_port *priv; | |
1086 | int ret; | |
1087 | int fifo_size; | |
1088 | int trigger_level; | |
1089 | ||
1090 | priv = container_of(port, struct eg20t_port, port); | |
1091 | priv->tx_empty = 1; | |
aac6c0b0 TM |
1092 | |
1093 | if (port->uartclk) | |
1094 | priv->base_baud = port->uartclk; | |
1095 | else | |
1096 | port->uartclk = priv->base_baud; | |
1097 | ||
3c6a4832 TM |
1098 | pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT); |
1099 | ret = pch_uart_hal_set_line(priv, default_baud, | |
1100 | PCH_UART_HAL_PARITY_NONE, PCH_UART_HAL_8BIT, | |
1101 | PCH_UART_HAL_STB1); | |
1102 | if (ret) | |
1103 | return ret; | |
1104 | ||
1105 | switch (priv->fifo_size) { | |
1106 | case 256: | |
1107 | fifo_size = PCH_UART_HAL_FIFO256; | |
1108 | break; | |
1109 | case 64: | |
1110 | fifo_size = PCH_UART_HAL_FIFO64; | |
1111 | break; | |
1112 | case 16: | |
1113 | fifo_size = PCH_UART_HAL_FIFO16; | |
1114 | case 1: | |
1115 | default: | |
1116 | fifo_size = PCH_UART_HAL_FIFO_DIS; | |
1117 | break; | |
1118 | } | |
1119 | ||
1120 | switch (priv->trigger) { | |
1121 | case PCH_UART_HAL_TRIGGER1: | |
1122 | trigger_level = 1; | |
1123 | break; | |
1124 | case PCH_UART_HAL_TRIGGER_L: | |
1125 | trigger_level = priv->fifo_size / 4; | |
1126 | break; | |
1127 | case PCH_UART_HAL_TRIGGER_M: | |
1128 | trigger_level = priv->fifo_size / 2; | |
1129 | break; | |
1130 | case PCH_UART_HAL_TRIGGER_H: | |
1131 | default: | |
1132 | trigger_level = priv->fifo_size - (priv->fifo_size / 8); | |
1133 | break; | |
1134 | } | |
1135 | ||
1136 | priv->trigger_level = trigger_level; | |
1137 | ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0, | |
1138 | fifo_size, priv->trigger); | |
1139 | if (ret < 0) | |
1140 | return ret; | |
1141 | ||
1142 | ret = request_irq(priv->port.irq, pch_uart_interrupt, IRQF_SHARED, | |
1143 | KBUILD_MODNAME, priv); | |
1144 | if (ret < 0) | |
1145 | return ret; | |
1146 | ||
1147 | if (priv->use_dma) | |
1148 | pch_request_dma(port); | |
1149 | ||
1150 | priv->start_rx = 1; | |
1151 | pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT); | |
1152 | uart_update_timeout(port, CS8, default_baud); | |
1153 | ||
1154 | return 0; | |
1155 | } | |
1156 | ||
1157 | static void pch_uart_shutdown(struct uart_port *port) | |
1158 | { | |
1159 | struct eg20t_port *priv; | |
1160 | int ret; | |
1161 | ||
1162 | priv = container_of(port, struct eg20t_port, port); | |
1163 | pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT); | |
1164 | pch_uart_hal_fifo_reset(priv, PCH_UART_HAL_CLR_ALL_FIFO); | |
1165 | ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0, | |
1166 | PCH_UART_HAL_FIFO_DIS, PCH_UART_HAL_TRIGGER1); | |
1167 | if (ret) | |
23877fdc TM |
1168 | dev_err(priv->port.dev, |
1169 | "pch_uart_hal_set_fifo Failed(ret=%d)\n", ret); | |
3c6a4832 TM |
1170 | |
1171 | if (priv->use_dma_flag) | |
1172 | pch_free_dma(port); | |
1173 | ||
1174 | free_irq(priv->port.irq, priv); | |
1175 | } | |
1176 | ||
1177 | /* Change the port parameters, including word length, parity, stop | |
1178 | *bits. Update read_status_mask and ignore_status_mask to indicate | |
1179 | *the types of events we are interested in receiving. */ | |
1180 | static void pch_uart_set_termios(struct uart_port *port, | |
1181 | struct ktermios *termios, struct ktermios *old) | |
1182 | { | |
1183 | int baud; | |
1184 | int rtn; | |
1185 | unsigned int parity, bits, stb; | |
1186 | struct eg20t_port *priv; | |
1187 | unsigned long flags; | |
1188 | ||
1189 | priv = container_of(port, struct eg20t_port, port); | |
1190 | switch (termios->c_cflag & CSIZE) { | |
1191 | case CS5: | |
1192 | bits = PCH_UART_HAL_5BIT; | |
1193 | break; | |
1194 | case CS6: | |
1195 | bits = PCH_UART_HAL_6BIT; | |
1196 | break; | |
1197 | case CS7: | |
1198 | bits = PCH_UART_HAL_7BIT; | |
1199 | break; | |
1200 | default: /* CS8 */ | |
1201 | bits = PCH_UART_HAL_8BIT; | |
1202 | break; | |
1203 | } | |
1204 | if (termios->c_cflag & CSTOPB) | |
1205 | stb = PCH_UART_HAL_STB2; | |
1206 | else | |
1207 | stb = PCH_UART_HAL_STB1; | |
1208 | ||
1209 | if (termios->c_cflag & PARENB) { | |
1210 | if (!(termios->c_cflag & PARODD)) | |
1211 | parity = PCH_UART_HAL_PARITY_ODD; | |
1212 | else | |
1213 | parity = PCH_UART_HAL_PARITY_EVEN; | |
1214 | ||
1215 | } else { | |
1216 | parity = PCH_UART_HAL_PARITY_NONE; | |
1217 | } | |
1218 | termios->c_cflag &= ~CMSPAR; /* Mark/Space parity is not supported */ | |
1219 | ||
1220 | baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16); | |
1221 | ||
1222 | spin_lock_irqsave(&port->lock, flags); | |
1223 | ||
1224 | uart_update_timeout(port, termios->c_cflag, baud); | |
1225 | rtn = pch_uart_hal_set_line(priv, baud, parity, bits, stb); | |
1226 | if (rtn) | |
1227 | goto out; | |
1228 | ||
1229 | /* Don't rewrite B0 */ | |
1230 | if (tty_termios_baud_rate(termios)) | |
1231 | tty_termios_encode_baud_rate(termios, baud, baud); | |
1232 | ||
1233 | out: | |
1234 | spin_unlock_irqrestore(&port->lock, flags); | |
1235 | } | |
1236 | ||
1237 | static const char *pch_uart_type(struct uart_port *port) | |
1238 | { | |
1239 | return KBUILD_MODNAME; | |
1240 | } | |
1241 | ||
1242 | static void pch_uart_release_port(struct uart_port *port) | |
1243 | { | |
1244 | struct eg20t_port *priv; | |
1245 | ||
1246 | priv = container_of(port, struct eg20t_port, port); | |
1247 | pci_iounmap(priv->pdev, priv->membase); | |
1248 | pci_release_regions(priv->pdev); | |
1249 | } | |
1250 | ||
1251 | static int pch_uart_request_port(struct uart_port *port) | |
1252 | { | |
1253 | struct eg20t_port *priv; | |
1254 | int ret; | |
1255 | void __iomem *membase; | |
1256 | ||
1257 | priv = container_of(port, struct eg20t_port, port); | |
1258 | ret = pci_request_regions(priv->pdev, KBUILD_MODNAME); | |
1259 | if (ret < 0) | |
1260 | return -EBUSY; | |
1261 | ||
1262 | membase = pci_iomap(priv->pdev, 1, 0); | |
1263 | if (!membase) { | |
1264 | pci_release_regions(priv->pdev); | |
1265 | return -EBUSY; | |
1266 | } | |
1267 | priv->membase = port->membase = membase; | |
1268 | ||
1269 | return 0; | |
1270 | } | |
1271 | ||
1272 | static void pch_uart_config_port(struct uart_port *port, int type) | |
1273 | { | |
1274 | struct eg20t_port *priv; | |
1275 | ||
1276 | priv = container_of(port, struct eg20t_port, port); | |
1277 | if (type & UART_CONFIG_TYPE) { | |
1278 | port->type = priv->port_type; | |
1279 | pch_uart_request_port(port); | |
1280 | } | |
1281 | } | |
1282 | ||
1283 | static int pch_uart_verify_port(struct uart_port *port, | |
1284 | struct serial_struct *serinfo) | |
1285 | { | |
1286 | struct eg20t_port *priv; | |
1287 | ||
1288 | priv = container_of(port, struct eg20t_port, port); | |
1289 | if (serinfo->flags & UPF_LOW_LATENCY) { | |
23877fdc TM |
1290 | dev_info(priv->port.dev, |
1291 | "PCH UART : Use PIO Mode (without DMA)\n"); | |
3c6a4832 TM |
1292 | priv->use_dma = 0; |
1293 | serinfo->flags &= ~UPF_LOW_LATENCY; | |
1294 | } else { | |
1295 | #ifndef CONFIG_PCH_DMA | |
23877fdc TM |
1296 | dev_err(priv->port.dev, "%s : PCH DMA is not Loaded.\n", |
1297 | __func__); | |
3c6a4832 TM |
1298 | return -EOPNOTSUPP; |
1299 | #endif | |
1300 | priv->use_dma = 1; | |
1301 | priv->use_dma_flag = 1; | |
23877fdc | 1302 | dev_info(priv->port.dev, "PCH UART : Use DMA Mode\n"); |
3c6a4832 TM |
1303 | } |
1304 | ||
1305 | return 0; | |
1306 | } | |
1307 | ||
1308 | static struct uart_ops pch_uart_ops = { | |
1309 | .tx_empty = pch_uart_tx_empty, | |
1310 | .set_mctrl = pch_uart_set_mctrl, | |
1311 | .get_mctrl = pch_uart_get_mctrl, | |
1312 | .stop_tx = pch_uart_stop_tx, | |
1313 | .start_tx = pch_uart_start_tx, | |
1314 | .stop_rx = pch_uart_stop_rx, | |
1315 | .enable_ms = pch_uart_enable_ms, | |
1316 | .break_ctl = pch_uart_break_ctl, | |
1317 | .startup = pch_uart_startup, | |
1318 | .shutdown = pch_uart_shutdown, | |
1319 | .set_termios = pch_uart_set_termios, | |
1320 | /* .pm = pch_uart_pm, Not supported yet */ | |
1321 | /* .set_wake = pch_uart_set_wake, Not supported yet */ | |
1322 | .type = pch_uart_type, | |
1323 | .release_port = pch_uart_release_port, | |
1324 | .request_port = pch_uart_request_port, | |
1325 | .config_port = pch_uart_config_port, | |
1326 | .verify_port = pch_uart_verify_port | |
1327 | }; | |
1328 | ||
1329 | static struct uart_driver pch_uart_driver = { | |
1330 | .owner = THIS_MODULE, | |
1331 | .driver_name = KBUILD_MODNAME, | |
1332 | .dev_name = PCH_UART_DRIVER_DEVICE, | |
1333 | .major = 0, | |
1334 | .minor = 0, | |
1335 | .nr = PCH_UART_NR, | |
1336 | }; | |
1337 | ||
1338 | static struct eg20t_port *pch_uart_init_port(struct pci_dev *pdev, | |
4564e1ef | 1339 | const struct pci_device_id *id) |
3c6a4832 TM |
1340 | { |
1341 | struct eg20t_port *priv; | |
1342 | int ret; | |
1343 | unsigned int iobase; | |
1344 | unsigned int mapbase; | |
1c518997 | 1345 | unsigned char *rxbuf; |
3c6a4832 TM |
1346 | int fifosize, base_baud; |
1347 | static int num; | |
4564e1ef | 1348 | int port_type = id->driver_data; |
3c6a4832 TM |
1349 | |
1350 | priv = kzalloc(sizeof(struct eg20t_port), GFP_KERNEL); | |
1351 | if (priv == NULL) | |
1352 | goto init_port_alloc_err; | |
1353 | ||
1c518997 | 1354 | rxbuf = (unsigned char *)__get_free_page(GFP_KERNEL); |
3c6a4832 TM |
1355 | if (!rxbuf) |
1356 | goto init_port_free_txbuf; | |
1357 | ||
1358 | switch (port_type) { | |
1359 | case PORT_UNKNOWN: | |
4564e1ef | 1360 | fifosize = 256; /* EG20T/ML7213: UART0 */ |
3c6a4832 TM |
1361 | base_baud = 1843200; /* 1.8432MHz */ |
1362 | break; | |
1363 | case PORT_8250: | |
4564e1ef | 1364 | fifosize = 64; /* EG20T:UART1~3 ML7213: UART1~2*/ |
3c6a4832 TM |
1365 | base_baud = 1843200; /* 1.8432MHz */ |
1366 | break; | |
1367 | default: | |
1368 | dev_err(&pdev->dev, "Invalid Port Type(=%d)\n", port_type); | |
1369 | goto init_port_hal_free; | |
1370 | } | |
1371 | ||
1372 | iobase = pci_resource_start(pdev, 0); | |
1373 | mapbase = pci_resource_start(pdev, 1); | |
1374 | priv->mapbase = mapbase; | |
1375 | priv->iobase = iobase; | |
1376 | priv->pdev = pdev; | |
1377 | priv->tx_empty = 1; | |
1c518997 | 1378 | priv->rxbuf.buf = rxbuf; |
3c6a4832 TM |
1379 | priv->rxbuf.size = PAGE_SIZE; |
1380 | ||
1381 | priv->fifo_size = fifosize; | |
1382 | priv->base_baud = base_baud; | |
1383 | priv->port_type = PORT_MAX_8250 + port_type + 1; | |
1384 | priv->port.dev = &pdev->dev; | |
1385 | priv->port.iobase = iobase; | |
1386 | priv->port.membase = NULL; | |
1387 | priv->port.mapbase = mapbase; | |
1388 | priv->port.irq = pdev->irq; | |
1389 | priv->port.iotype = UPIO_PORT; | |
1390 | priv->port.ops = &pch_uart_ops; | |
1391 | priv->port.flags = UPF_BOOT_AUTOCONF; | |
1392 | priv->port.fifosize = fifosize; | |
1393 | priv->port.line = num++; | |
1394 | priv->trigger = PCH_UART_HAL_TRIGGER_M; | |
1395 | ||
7e461329 TM |
1396 | spin_lock_init(&priv->port.lock); |
1397 | ||
3c6a4832 TM |
1398 | pci_set_drvdata(pdev, priv); |
1399 | pch_uart_hal_request(pdev, fifosize, base_baud); | |
4564e1ef | 1400 | |
3c6a4832 TM |
1401 | ret = uart_add_one_port(&pch_uart_driver, &priv->port); |
1402 | if (ret < 0) | |
1403 | goto init_port_hal_free; | |
1404 | ||
1405 | return priv; | |
1406 | ||
1407 | init_port_hal_free: | |
1c518997 | 1408 | free_page((unsigned long)rxbuf); |
3c6a4832 TM |
1409 | init_port_free_txbuf: |
1410 | kfree(priv); | |
1411 | init_port_alloc_err: | |
1412 | ||
1413 | return NULL; | |
1414 | } | |
1415 | ||
1416 | static void pch_uart_exit_port(struct eg20t_port *priv) | |
1417 | { | |
1418 | uart_remove_one_port(&pch_uart_driver, &priv->port); | |
1419 | pci_set_drvdata(priv->pdev, NULL); | |
1c518997 | 1420 | free_page((unsigned long)priv->rxbuf.buf); |
3c6a4832 TM |
1421 | } |
1422 | ||
1423 | static void pch_uart_pci_remove(struct pci_dev *pdev) | |
1424 | { | |
1425 | struct eg20t_port *priv; | |
1426 | ||
1427 | priv = (struct eg20t_port *)pci_get_drvdata(pdev); | |
1428 | pch_uart_exit_port(priv); | |
1429 | pci_disable_device(pdev); | |
1430 | kfree(priv); | |
1431 | return; | |
1432 | } | |
1433 | #ifdef CONFIG_PM | |
1434 | static int pch_uart_pci_suspend(struct pci_dev *pdev, pm_message_t state) | |
1435 | { | |
1436 | struct eg20t_port *priv = pci_get_drvdata(pdev); | |
1437 | ||
1438 | uart_suspend_port(&pch_uart_driver, &priv->port); | |
1439 | ||
1440 | pci_save_state(pdev); | |
1441 | pci_set_power_state(pdev, pci_choose_state(pdev, state)); | |
1442 | return 0; | |
1443 | } | |
1444 | ||
1445 | static int pch_uart_pci_resume(struct pci_dev *pdev) | |
1446 | { | |
1447 | struct eg20t_port *priv = pci_get_drvdata(pdev); | |
1448 | int ret; | |
1449 | ||
1450 | pci_set_power_state(pdev, PCI_D0); | |
1451 | pci_restore_state(pdev); | |
1452 | ||
1453 | ret = pci_enable_device(pdev); | |
1454 | if (ret) { | |
1455 | dev_err(&pdev->dev, | |
1456 | "%s-pci_enable_device failed(ret=%d) ", __func__, ret); | |
1457 | return ret; | |
1458 | } | |
1459 | ||
1460 | uart_resume_port(&pch_uart_driver, &priv->port); | |
1461 | ||
1462 | return 0; | |
1463 | } | |
1464 | #else | |
1465 | #define pch_uart_pci_suspend NULL | |
1466 | #define pch_uart_pci_resume NULL | |
1467 | #endif | |
1468 | ||
1469 | static DEFINE_PCI_DEVICE_TABLE(pch_uart_pci_id) = { | |
1470 | {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8811), | |
1471 | .driver_data = PCH_UART_8LINE}, | |
1472 | {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8812), | |
1473 | .driver_data = PCH_UART_2LINE}, | |
1474 | {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8813), | |
1475 | .driver_data = PCH_UART_2LINE}, | |
1476 | {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8814), | |
1477 | .driver_data = PCH_UART_2LINE}, | |
4564e1ef TM |
1478 | {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8027), |
1479 | .driver_data = PCH_UART_8LINE}, | |
1480 | {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8028), | |
1481 | .driver_data = PCH_UART_2LINE}, | |
1482 | {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8029), | |
1483 | .driver_data = PCH_UART_2LINE}, | |
3c6a4832 TM |
1484 | {0,}, |
1485 | }; | |
1486 | ||
1487 | static int __devinit pch_uart_pci_probe(struct pci_dev *pdev, | |
1488 | const struct pci_device_id *id) | |
1489 | { | |
1490 | int ret; | |
1491 | struct eg20t_port *priv; | |
1492 | ||
1493 | ret = pci_enable_device(pdev); | |
1494 | if (ret < 0) | |
1495 | goto probe_error; | |
1496 | ||
4564e1ef | 1497 | priv = pch_uart_init_port(pdev, id); |
3c6a4832 TM |
1498 | if (!priv) { |
1499 | ret = -EBUSY; | |
1500 | goto probe_disable_device; | |
1501 | } | |
1502 | pci_set_drvdata(pdev, priv); | |
1503 | ||
1504 | return ret; | |
1505 | ||
1506 | probe_disable_device: | |
1507 | pci_disable_device(pdev); | |
1508 | probe_error: | |
1509 | return ret; | |
1510 | } | |
1511 | ||
1512 | static struct pci_driver pch_uart_pci_driver = { | |
1513 | .name = "pch_uart", | |
1514 | .id_table = pch_uart_pci_id, | |
1515 | .probe = pch_uart_pci_probe, | |
1516 | .remove = __devexit_p(pch_uart_pci_remove), | |
1517 | .suspend = pch_uart_pci_suspend, | |
1518 | .resume = pch_uart_pci_resume, | |
1519 | }; | |
1520 | ||
1521 | static int __init pch_uart_module_init(void) | |
1522 | { | |
1523 | int ret; | |
1524 | ||
1525 | /* register as UART driver */ | |
1526 | ret = uart_register_driver(&pch_uart_driver); | |
1527 | if (ret < 0) | |
1528 | return ret; | |
1529 | ||
1530 | /* register as PCI driver */ | |
1531 | ret = pci_register_driver(&pch_uart_pci_driver); | |
1532 | if (ret < 0) | |
1533 | uart_unregister_driver(&pch_uart_driver); | |
1534 | ||
1535 | return ret; | |
1536 | } | |
1537 | module_init(pch_uart_module_init); | |
1538 | ||
1539 | static void __exit pch_uart_module_exit(void) | |
1540 | { | |
1541 | pci_unregister_driver(&pch_uart_pci_driver); | |
1542 | uart_unregister_driver(&pch_uart_driver); | |
1543 | } | |
1544 | module_exit(pch_uart_module_exit); | |
1545 | ||
1546 | MODULE_LICENSE("GPL v2"); | |
1547 | MODULE_DESCRIPTION("Intel EG20T PCH UART PCI Driver"); | |
1548 | module_param(default_baud, uint, S_IRUGO); |