Commit | Line | Data |
---|---|---|
3c6a4832 | 1 | /* |
eca9dfa8 | 2 | *Copyright (C) 2011 LAPIS Semiconductor Co., Ltd. |
3c6a4832 TM |
3 | * |
4 | *This program is free software; you can redistribute it and/or modify | |
5 | *it under the terms of the GNU General Public License as published by | |
6 | *the Free Software Foundation; version 2 of the License. | |
7 | * | |
8 | *This program is distributed in the hope that it will be useful, | |
9 | *but WITHOUT ANY WARRANTY; without even the implied warranty of | |
10 | *MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
11 | *GNU General Public License for more details. | |
12 | * | |
13 | *You should have received a copy of the GNU General Public License | |
14 | *along with this program; if not, write to the Free Software | |
15 | *Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. | |
16 | */ | |
0e2adc06 | 17 | #include <linux/kernel.h> |
3c6a4832 | 18 | #include <linux/serial_reg.h> |
023bc8e7 | 19 | #include <linux/slab.h> |
3c6a4832 TM |
20 | #include <linux/module.h> |
21 | #include <linux/pci.h> | |
22 | #include <linux/serial_core.h> | |
ee160a38 JS |
23 | #include <linux/tty.h> |
24 | #include <linux/tty_flip.h> | |
3c6a4832 TM |
25 | #include <linux/interrupt.h> |
26 | #include <linux/io.h> | |
6ae705b2 | 27 | #include <linux/dmi.h> |
e30f867d AS |
28 | #include <linux/console.h> |
29 | #include <linux/nmi.h> | |
30 | #include <linux/delay.h> | |
3c6a4832 | 31 | |
d011411d | 32 | #include <linux/debugfs.h> |
3c6a4832 TM |
33 | #include <linux/dmaengine.h> |
34 | #include <linux/pch_dma.h> | |
35 | ||
36 | enum { | |
37 | PCH_UART_HANDLED_RX_INT_SHIFT, | |
38 | PCH_UART_HANDLED_TX_INT_SHIFT, | |
39 | PCH_UART_HANDLED_RX_ERR_INT_SHIFT, | |
40 | PCH_UART_HANDLED_RX_TRG_INT_SHIFT, | |
41 | PCH_UART_HANDLED_MS_INT_SHIFT, | |
42 | }; | |
43 | ||
44 | enum { | |
45 | PCH_UART_8LINE, | |
46 | PCH_UART_2LINE, | |
47 | }; | |
48 | ||
49 | #define PCH_UART_DRIVER_DEVICE "ttyPCH" | |
50 | ||
4564e1ef TM |
51 | /* Set the max number of UART port |
52 | * Intel EG20T PCH: 4 port | |
eca9dfa8 TM |
53 | * LAPIS Semiconductor ML7213 IOH: 3 port |
54 | * LAPIS Semiconductor ML7223 IOH: 2 port | |
4564e1ef TM |
55 | */ |
56 | #define PCH_UART_NR 4 | |
3c6a4832 TM |
57 | |
58 | #define PCH_UART_HANDLED_RX_INT (1<<((PCH_UART_HANDLED_RX_INT_SHIFT)<<1)) | |
59 | #define PCH_UART_HANDLED_TX_INT (1<<((PCH_UART_HANDLED_TX_INT_SHIFT)<<1)) | |
60 | #define PCH_UART_HANDLED_RX_ERR_INT (1<<((\ | |
61 | PCH_UART_HANDLED_RX_ERR_INT_SHIFT)<<1)) | |
62 | #define PCH_UART_HANDLED_RX_TRG_INT (1<<((\ | |
63 | PCH_UART_HANDLED_RX_TRG_INT_SHIFT)<<1)) | |
64 | #define PCH_UART_HANDLED_MS_INT (1<<((PCH_UART_HANDLED_MS_INT_SHIFT)<<1)) | |
65 | ||
66 | #define PCH_UART_RBR 0x00 | |
67 | #define PCH_UART_THR 0x00 | |
68 | ||
69 | #define PCH_UART_IER_MASK (PCH_UART_IER_ERBFI|PCH_UART_IER_ETBEI|\ | |
70 | PCH_UART_IER_ELSI|PCH_UART_IER_EDSSI) | |
71 | #define PCH_UART_IER_ERBFI 0x00000001 | |
72 | #define PCH_UART_IER_ETBEI 0x00000002 | |
73 | #define PCH_UART_IER_ELSI 0x00000004 | |
74 | #define PCH_UART_IER_EDSSI 0x00000008 | |
75 | ||
76 | #define PCH_UART_IIR_IP 0x00000001 | |
77 | #define PCH_UART_IIR_IID 0x00000006 | |
78 | #define PCH_UART_IIR_MSI 0x00000000 | |
79 | #define PCH_UART_IIR_TRI 0x00000002 | |
80 | #define PCH_UART_IIR_RRI 0x00000004 | |
81 | #define PCH_UART_IIR_REI 0x00000006 | |
82 | #define PCH_UART_IIR_TOI 0x00000008 | |
83 | #define PCH_UART_IIR_FIFO256 0x00000020 | |
84 | #define PCH_UART_IIR_FIFO64 PCH_UART_IIR_FIFO256 | |
85 | #define PCH_UART_IIR_FE 0x000000C0 | |
86 | ||
87 | #define PCH_UART_FCR_FIFOE 0x00000001 | |
88 | #define PCH_UART_FCR_RFR 0x00000002 | |
89 | #define PCH_UART_FCR_TFR 0x00000004 | |
90 | #define PCH_UART_FCR_DMS 0x00000008 | |
91 | #define PCH_UART_FCR_FIFO256 0x00000020 | |
92 | #define PCH_UART_FCR_RFTL 0x000000C0 | |
93 | ||
94 | #define PCH_UART_FCR_RFTL1 0x00000000 | |
95 | #define PCH_UART_FCR_RFTL64 0x00000040 | |
96 | #define PCH_UART_FCR_RFTL128 0x00000080 | |
97 | #define PCH_UART_FCR_RFTL224 0x000000C0 | |
98 | #define PCH_UART_FCR_RFTL16 PCH_UART_FCR_RFTL64 | |
99 | #define PCH_UART_FCR_RFTL32 PCH_UART_FCR_RFTL128 | |
100 | #define PCH_UART_FCR_RFTL56 PCH_UART_FCR_RFTL224 | |
101 | #define PCH_UART_FCR_RFTL4 PCH_UART_FCR_RFTL64 | |
102 | #define PCH_UART_FCR_RFTL8 PCH_UART_FCR_RFTL128 | |
103 | #define PCH_UART_FCR_RFTL14 PCH_UART_FCR_RFTL224 | |
104 | #define PCH_UART_FCR_RFTL_SHIFT 6 | |
105 | ||
106 | #define PCH_UART_LCR_WLS 0x00000003 | |
107 | #define PCH_UART_LCR_STB 0x00000004 | |
108 | #define PCH_UART_LCR_PEN 0x00000008 | |
109 | #define PCH_UART_LCR_EPS 0x00000010 | |
110 | #define PCH_UART_LCR_SP 0x00000020 | |
111 | #define PCH_UART_LCR_SB 0x00000040 | |
112 | #define PCH_UART_LCR_DLAB 0x00000080 | |
113 | #define PCH_UART_LCR_NP 0x00000000 | |
114 | #define PCH_UART_LCR_OP PCH_UART_LCR_PEN | |
115 | #define PCH_UART_LCR_EP (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS) | |
116 | #define PCH_UART_LCR_1P (PCH_UART_LCR_PEN | PCH_UART_LCR_SP) | |
117 | #define PCH_UART_LCR_0P (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS |\ | |
118 | PCH_UART_LCR_SP) | |
119 | ||
120 | #define PCH_UART_LCR_5BIT 0x00000000 | |
121 | #define PCH_UART_LCR_6BIT 0x00000001 | |
122 | #define PCH_UART_LCR_7BIT 0x00000002 | |
123 | #define PCH_UART_LCR_8BIT 0x00000003 | |
124 | ||
125 | #define PCH_UART_MCR_DTR 0x00000001 | |
126 | #define PCH_UART_MCR_RTS 0x00000002 | |
127 | #define PCH_UART_MCR_OUT 0x0000000C | |
128 | #define PCH_UART_MCR_LOOP 0x00000010 | |
129 | #define PCH_UART_MCR_AFE 0x00000020 | |
130 | ||
131 | #define PCH_UART_LSR_DR 0x00000001 | |
132 | #define PCH_UART_LSR_ERR (1<<7) | |
133 | ||
134 | #define PCH_UART_MSR_DCTS 0x00000001 | |
135 | #define PCH_UART_MSR_DDSR 0x00000002 | |
136 | #define PCH_UART_MSR_TERI 0x00000004 | |
137 | #define PCH_UART_MSR_DDCD 0x00000008 | |
138 | #define PCH_UART_MSR_CTS 0x00000010 | |
139 | #define PCH_UART_MSR_DSR 0x00000020 | |
140 | #define PCH_UART_MSR_RI 0x00000040 | |
141 | #define PCH_UART_MSR_DCD 0x00000080 | |
142 | #define PCH_UART_MSR_DELTA (PCH_UART_MSR_DCTS | PCH_UART_MSR_DDSR |\ | |
143 | PCH_UART_MSR_TERI | PCH_UART_MSR_DDCD) | |
144 | ||
145 | #define PCH_UART_DLL 0x00 | |
146 | #define PCH_UART_DLM 0x01 | |
147 | ||
d011411d FT |
148 | #define PCH_UART_BRCSR 0x0E |
149 | ||
3c6a4832 TM |
150 | #define PCH_UART_IID_RLS (PCH_UART_IIR_REI) |
151 | #define PCH_UART_IID_RDR (PCH_UART_IIR_RRI) | |
152 | #define PCH_UART_IID_RDR_TO (PCH_UART_IIR_RRI | PCH_UART_IIR_TOI) | |
153 | #define PCH_UART_IID_THRE (PCH_UART_IIR_TRI) | |
154 | #define PCH_UART_IID_MS (PCH_UART_IIR_MSI) | |
155 | ||
156 | #define PCH_UART_HAL_PARITY_NONE (PCH_UART_LCR_NP) | |
157 | #define PCH_UART_HAL_PARITY_ODD (PCH_UART_LCR_OP) | |
158 | #define PCH_UART_HAL_PARITY_EVEN (PCH_UART_LCR_EP) | |
159 | #define PCH_UART_HAL_PARITY_FIX1 (PCH_UART_LCR_1P) | |
160 | #define PCH_UART_HAL_PARITY_FIX0 (PCH_UART_LCR_0P) | |
161 | #define PCH_UART_HAL_5BIT (PCH_UART_LCR_5BIT) | |
162 | #define PCH_UART_HAL_6BIT (PCH_UART_LCR_6BIT) | |
163 | #define PCH_UART_HAL_7BIT (PCH_UART_LCR_7BIT) | |
164 | #define PCH_UART_HAL_8BIT (PCH_UART_LCR_8BIT) | |
165 | #define PCH_UART_HAL_STB1 0 | |
166 | #define PCH_UART_HAL_STB2 (PCH_UART_LCR_STB) | |
167 | ||
168 | #define PCH_UART_HAL_CLR_TX_FIFO (PCH_UART_FCR_TFR) | |
169 | #define PCH_UART_HAL_CLR_RX_FIFO (PCH_UART_FCR_RFR) | |
170 | #define PCH_UART_HAL_CLR_ALL_FIFO (PCH_UART_HAL_CLR_TX_FIFO | \ | |
171 | PCH_UART_HAL_CLR_RX_FIFO) | |
172 | ||
173 | #define PCH_UART_HAL_DMA_MODE0 0 | |
174 | #define PCH_UART_HAL_FIFO_DIS 0 | |
175 | #define PCH_UART_HAL_FIFO16 (PCH_UART_FCR_FIFOE) | |
176 | #define PCH_UART_HAL_FIFO256 (PCH_UART_FCR_FIFOE | \ | |
177 | PCH_UART_FCR_FIFO256) | |
178 | #define PCH_UART_HAL_FIFO64 (PCH_UART_HAL_FIFO256) | |
179 | #define PCH_UART_HAL_TRIGGER1 (PCH_UART_FCR_RFTL1) | |
180 | #define PCH_UART_HAL_TRIGGER64 (PCH_UART_FCR_RFTL64) | |
181 | #define PCH_UART_HAL_TRIGGER128 (PCH_UART_FCR_RFTL128) | |
182 | #define PCH_UART_HAL_TRIGGER224 (PCH_UART_FCR_RFTL224) | |
183 | #define PCH_UART_HAL_TRIGGER16 (PCH_UART_FCR_RFTL16) | |
184 | #define PCH_UART_HAL_TRIGGER32 (PCH_UART_FCR_RFTL32) | |
185 | #define PCH_UART_HAL_TRIGGER56 (PCH_UART_FCR_RFTL56) | |
186 | #define PCH_UART_HAL_TRIGGER4 (PCH_UART_FCR_RFTL4) | |
187 | #define PCH_UART_HAL_TRIGGER8 (PCH_UART_FCR_RFTL8) | |
188 | #define PCH_UART_HAL_TRIGGER14 (PCH_UART_FCR_RFTL14) | |
189 | #define PCH_UART_HAL_TRIGGER_L (PCH_UART_FCR_RFTL64) | |
190 | #define PCH_UART_HAL_TRIGGER_M (PCH_UART_FCR_RFTL128) | |
191 | #define PCH_UART_HAL_TRIGGER_H (PCH_UART_FCR_RFTL224) | |
192 | ||
193 | #define PCH_UART_HAL_RX_INT (PCH_UART_IER_ERBFI) | |
194 | #define PCH_UART_HAL_TX_INT (PCH_UART_IER_ETBEI) | |
195 | #define PCH_UART_HAL_RX_ERR_INT (PCH_UART_IER_ELSI) | |
196 | #define PCH_UART_HAL_MS_INT (PCH_UART_IER_EDSSI) | |
197 | #define PCH_UART_HAL_ALL_INT (PCH_UART_IER_MASK) | |
198 | ||
199 | #define PCH_UART_HAL_DTR (PCH_UART_MCR_DTR) | |
200 | #define PCH_UART_HAL_RTS (PCH_UART_MCR_RTS) | |
201 | #define PCH_UART_HAL_OUT (PCH_UART_MCR_OUT) | |
202 | #define PCH_UART_HAL_LOOP (PCH_UART_MCR_LOOP) | |
203 | #define PCH_UART_HAL_AFE (PCH_UART_MCR_AFE) | |
204 | ||
4564e1ef TM |
205 | #define PCI_VENDOR_ID_ROHM 0x10DB |
206 | ||
e30f867d AS |
207 | #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE) |
208 | ||
077175f0 DH |
209 | #define DEFAULT_UARTCLK 1843200 /* 1.8432 MHz */ |
210 | #define CMITC_UARTCLK 192000000 /* 192.0000 MHz */ | |
211 | #define FRI2_64_UARTCLK 64000000 /* 64.0000 MHz */ | |
212 | #define FRI2_48_UARTCLK 48000000 /* 48.0000 MHz */ | |
11bbd5b6 | 213 | #define NTC1_UARTCLK 64000000 /* 64.0000 MHz */ |
e30f867d | 214 | |
3c6a4832 TM |
215 | struct pch_uart_buffer { |
216 | unsigned char *buf; | |
217 | int size; | |
218 | }; | |
219 | ||
220 | struct eg20t_port { | |
221 | struct uart_port port; | |
222 | int port_type; | |
223 | void __iomem *membase; | |
224 | resource_size_t mapbase; | |
225 | unsigned int iobase; | |
226 | struct pci_dev *pdev; | |
227 | int fifo_size; | |
a8a3ec9d | 228 | int uartclk; |
3c6a4832 TM |
229 | int start_tx; |
230 | int start_rx; | |
231 | int tx_empty; | |
232 | int int_dis_flag; | |
233 | int trigger; | |
234 | int trigger_level; | |
235 | struct pch_uart_buffer rxbuf; | |
236 | unsigned int dmsr; | |
237 | unsigned int fcr; | |
9af7155b | 238 | unsigned int mcr; |
3c6a4832 TM |
239 | unsigned int use_dma; |
240 | unsigned int use_dma_flag; | |
241 | struct dma_async_tx_descriptor *desc_tx; | |
242 | struct dma_async_tx_descriptor *desc_rx; | |
243 | struct pch_dma_slave param_tx; | |
244 | struct pch_dma_slave param_rx; | |
245 | struct dma_chan *chan_tx; | |
246 | struct dma_chan *chan_rx; | |
da3564ee TM |
247 | struct scatterlist *sg_tx_p; |
248 | int nent; | |
3c6a4832 TM |
249 | struct scatterlist sg_rx; |
250 | int tx_dma_use; | |
251 | void *rx_buf_virt; | |
252 | dma_addr_t rx_buf_dma; | |
d011411d FT |
253 | |
254 | struct dentry *debugfs; | |
3c6a4832 TM |
255 | }; |
256 | ||
fec38d17 TM |
257 | /** |
258 | * struct pch_uart_driver_data - private data structure for UART-DMA | |
259 | * @port_type: The number of DMA channel | |
260 | * @line_no: UART port line number (0, 1, 2...) | |
261 | */ | |
262 | struct pch_uart_driver_data { | |
263 | int port_type; | |
264 | int line_no; | |
265 | }; | |
266 | ||
267 | enum pch_uart_num_t { | |
268 | pch_et20t_uart0 = 0, | |
269 | pch_et20t_uart1, | |
270 | pch_et20t_uart2, | |
271 | pch_et20t_uart3, | |
272 | pch_ml7213_uart0, | |
273 | pch_ml7213_uart1, | |
274 | pch_ml7213_uart2, | |
177c2cbf TM |
275 | pch_ml7223_uart0, |
276 | pch_ml7223_uart1, | |
8249f743 TM |
277 | pch_ml7831_uart0, |
278 | pch_ml7831_uart1, | |
fec38d17 TM |
279 | }; |
280 | ||
281 | static struct pch_uart_driver_data drv_dat[] = { | |
282 | [pch_et20t_uart0] = {PCH_UART_8LINE, 0}, | |
283 | [pch_et20t_uart1] = {PCH_UART_2LINE, 1}, | |
284 | [pch_et20t_uart2] = {PCH_UART_2LINE, 2}, | |
285 | [pch_et20t_uart3] = {PCH_UART_2LINE, 3}, | |
286 | [pch_ml7213_uart0] = {PCH_UART_8LINE, 0}, | |
287 | [pch_ml7213_uart1] = {PCH_UART_2LINE, 1}, | |
288 | [pch_ml7213_uart2] = {PCH_UART_2LINE, 2}, | |
177c2cbf TM |
289 | [pch_ml7223_uart0] = {PCH_UART_8LINE, 0}, |
290 | [pch_ml7223_uart1] = {PCH_UART_2LINE, 1}, | |
8249f743 TM |
291 | [pch_ml7831_uart0] = {PCH_UART_8LINE, 0}, |
292 | [pch_ml7831_uart1] = {PCH_UART_2LINE, 1}, | |
fec38d17 TM |
293 | }; |
294 | ||
e30f867d AS |
295 | #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE |
296 | static struct eg20t_port *pch_uart_ports[PCH_UART_NR]; | |
297 | #endif | |
3c6a4832 | 298 | static unsigned int default_baud = 9600; |
2a44feb2 | 299 | static unsigned int user_uartclk = 0; |
3c6a4832 TM |
300 | static const int trigger_level_256[4] = { 1, 64, 128, 224 }; |
301 | static const int trigger_level_64[4] = { 1, 16, 32, 56 }; | |
302 | static const int trigger_level_16[4] = { 1, 4, 8, 14 }; | |
303 | static const int trigger_level_1[4] = { 1, 1, 1, 1 }; | |
304 | ||
d011411d FT |
305 | #ifdef CONFIG_DEBUG_FS |
306 | ||
307 | #define PCH_REGS_BUFSIZE 1024 | |
234e3405 | 308 | |
d011411d FT |
309 | |
310 | static ssize_t port_show_regs(struct file *file, char __user *user_buf, | |
311 | size_t count, loff_t *ppos) | |
312 | { | |
313 | struct eg20t_port *priv = file->private_data; | |
314 | char *buf; | |
315 | u32 len = 0; | |
316 | ssize_t ret; | |
317 | unsigned char lcr; | |
318 | ||
319 | buf = kzalloc(PCH_REGS_BUFSIZE, GFP_KERNEL); | |
320 | if (!buf) | |
321 | return 0; | |
322 | ||
323 | len += snprintf(buf + len, PCH_REGS_BUFSIZE - len, | |
324 | "PCH EG20T port[%d] regs:\n", priv->port.line); | |
325 | ||
326 | len += snprintf(buf + len, PCH_REGS_BUFSIZE - len, | |
327 | "=================================\n"); | |
328 | len += snprintf(buf + len, PCH_REGS_BUFSIZE - len, | |
329 | "IER: \t0x%02x\n", ioread8(priv->membase + UART_IER)); | |
330 | len += snprintf(buf + len, PCH_REGS_BUFSIZE - len, | |
331 | "IIR: \t0x%02x\n", ioread8(priv->membase + UART_IIR)); | |
332 | len += snprintf(buf + len, PCH_REGS_BUFSIZE - len, | |
333 | "LCR: \t0x%02x\n", ioread8(priv->membase + UART_LCR)); | |
334 | len += snprintf(buf + len, PCH_REGS_BUFSIZE - len, | |
335 | "MCR: \t0x%02x\n", ioread8(priv->membase + UART_MCR)); | |
336 | len += snprintf(buf + len, PCH_REGS_BUFSIZE - len, | |
337 | "LSR: \t0x%02x\n", ioread8(priv->membase + UART_LSR)); | |
338 | len += snprintf(buf + len, PCH_REGS_BUFSIZE - len, | |
339 | "MSR: \t0x%02x\n", ioread8(priv->membase + UART_MSR)); | |
340 | len += snprintf(buf + len, PCH_REGS_BUFSIZE - len, | |
341 | "BRCSR: \t0x%02x\n", | |
342 | ioread8(priv->membase + PCH_UART_BRCSR)); | |
343 | ||
344 | lcr = ioread8(priv->membase + UART_LCR); | |
345 | iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR); | |
346 | len += snprintf(buf + len, PCH_REGS_BUFSIZE - len, | |
347 | "DLL: \t0x%02x\n", ioread8(priv->membase + UART_DLL)); | |
348 | len += snprintf(buf + len, PCH_REGS_BUFSIZE - len, | |
349 | "DLM: \t0x%02x\n", ioread8(priv->membase + UART_DLM)); | |
350 | iowrite8(lcr, priv->membase + UART_LCR); | |
351 | ||
352 | if (len > PCH_REGS_BUFSIZE) | |
353 | len = PCH_REGS_BUFSIZE; | |
354 | ||
355 | ret = simple_read_from_buffer(user_buf, count, ppos, buf, len); | |
356 | kfree(buf); | |
357 | return ret; | |
358 | } | |
359 | ||
360 | static const struct file_operations port_regs_ops = { | |
361 | .owner = THIS_MODULE, | |
234e3405 | 362 | .open = simple_open, |
d011411d FT |
363 | .read = port_show_regs, |
364 | .llseek = default_llseek, | |
365 | }; | |
366 | #endif /* CONFIG_DEBUG_FS */ | |
367 | ||
077175f0 DH |
368 | /* Return UART clock, checking for board specific clocks. */ |
369 | static int pch_uart_get_uartclk(void) | |
370 | { | |
371 | const char *cmp; | |
372 | ||
2a44feb2 DH |
373 | if (user_uartclk) |
374 | return user_uartclk; | |
375 | ||
077175f0 DH |
376 | cmp = dmi_get_system_info(DMI_BOARD_NAME); |
377 | if (cmp && strstr(cmp, "CM-iTC")) | |
378 | return CMITC_UARTCLK; | |
379 | ||
380 | cmp = dmi_get_system_info(DMI_BIOS_VERSION); | |
381 | if (cmp && strnstr(cmp, "FRI2", 4)) | |
382 | return FRI2_64_UARTCLK; | |
383 | ||
384 | cmp = dmi_get_system_info(DMI_PRODUCT_NAME); | |
385 | if (cmp && strstr(cmp, "Fish River Island II")) | |
386 | return FRI2_48_UARTCLK; | |
387 | ||
11bbd5b6 MB |
388 | /* Kontron COMe-mTT10 (nanoETXexpress-TT) */ |
389 | cmp = dmi_get_system_info(DMI_BOARD_NAME); | |
390 | if (cmp && (strstr(cmp, "COMe-mTT") || | |
391 | strstr(cmp, "nanoETXexpress-TT"))) | |
392 | return NTC1_UARTCLK; | |
393 | ||
077175f0 DH |
394 | return DEFAULT_UARTCLK; |
395 | } | |
396 | ||
3c6a4832 TM |
397 | static void pch_uart_hal_enable_interrupt(struct eg20t_port *priv, |
398 | unsigned int flag) | |
399 | { | |
400 | u8 ier = ioread8(priv->membase + UART_IER); | |
401 | ier |= flag & PCH_UART_IER_MASK; | |
402 | iowrite8(ier, priv->membase + UART_IER); | |
403 | } | |
404 | ||
405 | static void pch_uart_hal_disable_interrupt(struct eg20t_port *priv, | |
406 | unsigned int flag) | |
407 | { | |
408 | u8 ier = ioread8(priv->membase + UART_IER); | |
409 | ier &= ~(flag & PCH_UART_IER_MASK); | |
410 | iowrite8(ier, priv->membase + UART_IER); | |
411 | } | |
412 | ||
413 | static int pch_uart_hal_set_line(struct eg20t_port *priv, int baud, | |
414 | unsigned int parity, unsigned int bits, | |
415 | unsigned int stb) | |
416 | { | |
417 | unsigned int dll, dlm, lcr; | |
418 | int div; | |
419 | ||
a8a3ec9d | 420 | div = DIV_ROUND_CLOSEST(priv->uartclk / 16, baud); |
3c6a4832 | 421 | if (div < 0 || USHRT_MAX <= div) { |
23877fdc | 422 | dev_err(priv->port.dev, "Invalid Baud(div=0x%x)\n", div); |
3c6a4832 TM |
423 | return -EINVAL; |
424 | } | |
425 | ||
426 | dll = (unsigned int)div & 0x00FFU; | |
427 | dlm = ((unsigned int)div >> 8) & 0x00FFU; | |
428 | ||
429 | if (parity & ~(PCH_UART_LCR_PEN | PCH_UART_LCR_EPS | PCH_UART_LCR_SP)) { | |
23877fdc | 430 | dev_err(priv->port.dev, "Invalid parity(0x%x)\n", parity); |
3c6a4832 TM |
431 | return -EINVAL; |
432 | } | |
433 | ||
434 | if (bits & ~PCH_UART_LCR_WLS) { | |
23877fdc | 435 | dev_err(priv->port.dev, "Invalid bits(0x%x)\n", bits); |
3c6a4832 TM |
436 | return -EINVAL; |
437 | } | |
438 | ||
439 | if (stb & ~PCH_UART_LCR_STB) { | |
23877fdc | 440 | dev_err(priv->port.dev, "Invalid STB(0x%x)\n", stb); |
3c6a4832 TM |
441 | return -EINVAL; |
442 | } | |
443 | ||
444 | lcr = parity; | |
445 | lcr |= bits; | |
446 | lcr |= stb; | |
447 | ||
23877fdc | 448 | dev_dbg(priv->port.dev, "%s:baud = %d, div = %04x, lcr = %02x (%lu)\n", |
3c6a4832 TM |
449 | __func__, baud, div, lcr, jiffies); |
450 | iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR); | |
451 | iowrite8(dll, priv->membase + PCH_UART_DLL); | |
452 | iowrite8(dlm, priv->membase + PCH_UART_DLM); | |
453 | iowrite8(lcr, priv->membase + UART_LCR); | |
454 | ||
455 | return 0; | |
456 | } | |
457 | ||
458 | static int pch_uart_hal_fifo_reset(struct eg20t_port *priv, | |
459 | unsigned int flag) | |
460 | { | |
461 | if (flag & ~(PCH_UART_FCR_TFR | PCH_UART_FCR_RFR)) { | |
23877fdc TM |
462 | dev_err(priv->port.dev, "%s:Invalid flag(0x%x)\n", |
463 | __func__, flag); | |
3c6a4832 TM |
464 | return -EINVAL; |
465 | } | |
466 | ||
467 | iowrite8(PCH_UART_FCR_FIFOE | priv->fcr, priv->membase + UART_FCR); | |
468 | iowrite8(PCH_UART_FCR_FIFOE | priv->fcr | flag, | |
469 | priv->membase + UART_FCR); | |
470 | iowrite8(priv->fcr, priv->membase + UART_FCR); | |
471 | ||
472 | return 0; | |
473 | } | |
474 | ||
475 | static int pch_uart_hal_set_fifo(struct eg20t_port *priv, | |
476 | unsigned int dmamode, | |
477 | unsigned int fifo_size, unsigned int trigger) | |
478 | { | |
479 | u8 fcr; | |
480 | ||
481 | if (dmamode & ~PCH_UART_FCR_DMS) { | |
23877fdc TM |
482 | dev_err(priv->port.dev, "%s:Invalid DMA Mode(0x%x)\n", |
483 | __func__, dmamode); | |
3c6a4832 TM |
484 | return -EINVAL; |
485 | } | |
486 | ||
487 | if (fifo_size & ~(PCH_UART_FCR_FIFOE | PCH_UART_FCR_FIFO256)) { | |
23877fdc TM |
488 | dev_err(priv->port.dev, "%s:Invalid FIFO SIZE(0x%x)\n", |
489 | __func__, fifo_size); | |
3c6a4832 TM |
490 | return -EINVAL; |
491 | } | |
492 | ||
493 | if (trigger & ~PCH_UART_FCR_RFTL) { | |
23877fdc TM |
494 | dev_err(priv->port.dev, "%s:Invalid TRIGGER(0x%x)\n", |
495 | __func__, trigger); | |
3c6a4832 TM |
496 | return -EINVAL; |
497 | } | |
498 | ||
499 | switch (priv->fifo_size) { | |
500 | case 256: | |
501 | priv->trigger_level = | |
502 | trigger_level_256[trigger >> PCH_UART_FCR_RFTL_SHIFT]; | |
503 | break; | |
504 | case 64: | |
505 | priv->trigger_level = | |
506 | trigger_level_64[trigger >> PCH_UART_FCR_RFTL_SHIFT]; | |
507 | break; | |
508 | case 16: | |
509 | priv->trigger_level = | |
510 | trigger_level_16[trigger >> PCH_UART_FCR_RFTL_SHIFT]; | |
511 | break; | |
512 | default: | |
513 | priv->trigger_level = | |
514 | trigger_level_1[trigger >> PCH_UART_FCR_RFTL_SHIFT]; | |
515 | break; | |
516 | } | |
517 | fcr = | |
518 | dmamode | fifo_size | trigger | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR; | |
519 | iowrite8(PCH_UART_FCR_FIFOE, priv->membase + UART_FCR); | |
520 | iowrite8(PCH_UART_FCR_FIFOE | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR, | |
521 | priv->membase + UART_FCR); | |
522 | iowrite8(fcr, priv->membase + UART_FCR); | |
523 | priv->fcr = fcr; | |
524 | ||
525 | return 0; | |
526 | } | |
527 | ||
528 | static u8 pch_uart_hal_get_modem(struct eg20t_port *priv) | |
529 | { | |
30c6c6b5 FT |
530 | unsigned int msr = ioread8(priv->membase + UART_MSR); |
531 | priv->dmsr = msr & PCH_UART_MSR_DELTA; | |
532 | return (u8)msr; | |
3c6a4832 TM |
533 | } |
534 | ||
1822076c | 535 | static void pch_uart_hal_write(struct eg20t_port *priv, |
3c6a4832 TM |
536 | const unsigned char *buf, int tx_size) |
537 | { | |
538 | int i; | |
539 | unsigned int thr; | |
540 | ||
541 | for (i = 0; i < tx_size;) { | |
542 | thr = buf[i++]; | |
543 | iowrite8(thr, priv->membase + PCH_UART_THR); | |
544 | } | |
3c6a4832 TM |
545 | } |
546 | ||
547 | static int pch_uart_hal_read(struct eg20t_port *priv, unsigned char *buf, | |
548 | int rx_size) | |
549 | { | |
550 | int i; | |
551 | u8 rbr, lsr; | |
552 | ||
553 | lsr = ioread8(priv->membase + UART_LSR); | |
554 | for (i = 0, lsr = ioread8(priv->membase + UART_LSR); | |
555 | i < rx_size && lsr & UART_LSR_DR; | |
556 | lsr = ioread8(priv->membase + UART_LSR)) { | |
557 | rbr = ioread8(priv->membase + PCH_UART_RBR); | |
558 | buf[i++] = rbr; | |
559 | } | |
560 | return i; | |
561 | } | |
562 | ||
563 | static unsigned int pch_uart_hal_get_iid(struct eg20t_port *priv) | |
564 | { | |
565 | unsigned int iir; | |
566 | int ret; | |
567 | ||
568 | iir = ioread8(priv->membase + UART_IIR); | |
569 | ret = (iir & (PCH_UART_IIR_IID | PCH_UART_IIR_TOI | PCH_UART_IIR_IP)); | |
570 | return ret; | |
571 | } | |
572 | ||
573 | static u8 pch_uart_hal_get_line_status(struct eg20t_port *priv) | |
574 | { | |
575 | return ioread8(priv->membase + UART_LSR); | |
576 | } | |
577 | ||
578 | static void pch_uart_hal_set_break(struct eg20t_port *priv, int on) | |
579 | { | |
580 | unsigned int lcr; | |
581 | ||
582 | lcr = ioread8(priv->membase + UART_LCR); | |
583 | if (on) | |
584 | lcr |= PCH_UART_LCR_SB; | |
585 | else | |
586 | lcr &= ~PCH_UART_LCR_SB; | |
587 | ||
588 | iowrite8(lcr, priv->membase + UART_LCR); | |
589 | } | |
590 | ||
591 | static int push_rx(struct eg20t_port *priv, const unsigned char *buf, | |
592 | int size) | |
593 | { | |
594 | struct uart_port *port; | |
595 | struct tty_struct *tty; | |
596 | ||
597 | port = &priv->port; | |
598 | tty = tty_port_tty_get(&port->state->port); | |
599 | if (!tty) { | |
23877fdc | 600 | dev_dbg(priv->port.dev, "%s:tty is busy now", __func__); |
3c6a4832 TM |
601 | return -EBUSY; |
602 | } | |
603 | ||
604 | tty_insert_flip_string(tty, buf, size); | |
605 | tty_flip_buffer_push(tty); | |
606 | tty_kref_put(tty); | |
607 | ||
608 | return 0; | |
609 | } | |
610 | ||
611 | static int pop_tx_x(struct eg20t_port *priv, unsigned char *buf) | |
612 | { | |
30c6c6b5 | 613 | int ret = 0; |
3c6a4832 TM |
614 | struct uart_port *port = &priv->port; |
615 | ||
616 | if (port->x_char) { | |
23877fdc TM |
617 | dev_dbg(priv->port.dev, "%s:X character send %02x (%lu)\n", |
618 | __func__, port->x_char, jiffies); | |
3c6a4832 TM |
619 | buf[0] = port->x_char; |
620 | port->x_char = 0; | |
621 | ret = 1; | |
3c6a4832 TM |
622 | } |
623 | ||
624 | return ret; | |
625 | } | |
626 | ||
627 | static int dma_push_rx(struct eg20t_port *priv, int size) | |
628 | { | |
629 | struct tty_struct *tty; | |
630 | int room; | |
631 | struct uart_port *port = &priv->port; | |
632 | ||
633 | port = &priv->port; | |
634 | tty = tty_port_tty_get(&port->state->port); | |
635 | if (!tty) { | |
23877fdc | 636 | dev_dbg(priv->port.dev, "%s:tty is busy now", __func__); |
3c6a4832 TM |
637 | return 0; |
638 | } | |
639 | ||
640 | room = tty_buffer_request_room(tty, size); | |
641 | ||
642 | if (room < size) | |
643 | dev_warn(port->dev, "Rx overrun: dropping %u bytes\n", | |
644 | size - room); | |
645 | if (!room) | |
646 | return room; | |
647 | ||
648 | tty_insert_flip_string(tty, sg_virt(&priv->sg_rx), size); | |
649 | ||
650 | port->icount.rx += room; | |
651 | tty_kref_put(tty); | |
652 | ||
653 | return room; | |
654 | } | |
655 | ||
656 | static void pch_free_dma(struct uart_port *port) | |
657 | { | |
658 | struct eg20t_port *priv; | |
659 | priv = container_of(port, struct eg20t_port, port); | |
660 | ||
661 | if (priv->chan_tx) { | |
662 | dma_release_channel(priv->chan_tx); | |
663 | priv->chan_tx = NULL; | |
664 | } | |
665 | if (priv->chan_rx) { | |
666 | dma_release_channel(priv->chan_rx); | |
667 | priv->chan_rx = NULL; | |
668 | } | |
669 | if (sg_dma_address(&priv->sg_rx)) | |
670 | dma_free_coherent(port->dev, port->fifosize, | |
671 | sg_virt(&priv->sg_rx), | |
672 | sg_dma_address(&priv->sg_rx)); | |
673 | ||
674 | return; | |
675 | } | |
676 | ||
677 | static bool filter(struct dma_chan *chan, void *slave) | |
678 | { | |
679 | struct pch_dma_slave *param = slave; | |
680 | ||
681 | if ((chan->chan_id == param->chan_id) && (param->dma_dev == | |
682 | chan->device->dev)) { | |
683 | chan->private = param; | |
684 | return true; | |
685 | } else { | |
686 | return false; | |
687 | } | |
688 | } | |
689 | ||
690 | static void pch_request_dma(struct uart_port *port) | |
691 | { | |
692 | dma_cap_mask_t mask; | |
693 | struct dma_chan *chan; | |
694 | struct pci_dev *dma_dev; | |
695 | struct pch_dma_slave *param; | |
696 | struct eg20t_port *priv = | |
697 | container_of(port, struct eg20t_port, port); | |
698 | dma_cap_zero(mask); | |
699 | dma_cap_set(DMA_SLAVE, mask); | |
700 | ||
6c4b47d2 TM |
701 | dma_dev = pci_get_bus_and_slot(priv->pdev->bus->number, |
702 | PCI_DEVFN(0xa, 0)); /* Get DMA's dev | |
3c6a4832 TM |
703 | information */ |
704 | /* Set Tx DMA */ | |
705 | param = &priv->param_tx; | |
706 | param->dma_dev = &dma_dev->dev; | |
fec38d17 TM |
707 | param->chan_id = priv->port.line * 2; /* Tx = 0, 2, 4, ... */ |
708 | ||
3c6a4832 TM |
709 | param->tx_reg = port->mapbase + UART_TX; |
710 | chan = dma_request_channel(mask, filter, param); | |
711 | if (!chan) { | |
23877fdc TM |
712 | dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Tx)\n", |
713 | __func__); | |
3c6a4832 TM |
714 | return; |
715 | } | |
716 | priv->chan_tx = chan; | |
717 | ||
718 | /* Set Rx DMA */ | |
719 | param = &priv->param_rx; | |
720 | param->dma_dev = &dma_dev->dev; | |
fec38d17 TM |
721 | param->chan_id = priv->port.line * 2 + 1; /* Rx = Tx + 1 */ |
722 | ||
3c6a4832 TM |
723 | param->rx_reg = port->mapbase + UART_RX; |
724 | chan = dma_request_channel(mask, filter, param); | |
725 | if (!chan) { | |
23877fdc TM |
726 | dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Rx)\n", |
727 | __func__); | |
3c6a4832 | 728 | dma_release_channel(priv->chan_tx); |
90f04c29 | 729 | priv->chan_tx = NULL; |
3c6a4832 TM |
730 | return; |
731 | } | |
732 | ||
733 | /* Get Consistent memory for DMA */ | |
734 | priv->rx_buf_virt = dma_alloc_coherent(port->dev, port->fifosize, | |
735 | &priv->rx_buf_dma, GFP_KERNEL); | |
736 | priv->chan_rx = chan; | |
737 | } | |
738 | ||
739 | static void pch_dma_rx_complete(void *arg) | |
740 | { | |
741 | struct eg20t_port *priv = arg; | |
742 | struct uart_port *port = &priv->port; | |
743 | struct tty_struct *tty = tty_port_tty_get(&port->state->port); | |
da3564ee | 744 | int count; |
3c6a4832 TM |
745 | |
746 | if (!tty) { | |
23877fdc | 747 | dev_dbg(priv->port.dev, "%s:tty is busy now", __func__); |
3c6a4832 TM |
748 | return; |
749 | } | |
750 | ||
da3564ee TM |
751 | dma_sync_sg_for_cpu(port->dev, &priv->sg_rx, 1, DMA_FROM_DEVICE); |
752 | count = dma_push_rx(priv, priv->trigger_level); | |
753 | if (count) | |
3c6a4832 | 754 | tty_flip_buffer_push(tty); |
3c6a4832 | 755 | tty_kref_put(tty); |
da3564ee TM |
756 | async_tx_ack(priv->desc_rx); |
757 | pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT); | |
3c6a4832 TM |
758 | } |
759 | ||
760 | static void pch_dma_tx_complete(void *arg) | |
761 | { | |
762 | struct eg20t_port *priv = arg; | |
763 | struct uart_port *port = &priv->port; | |
764 | struct circ_buf *xmit = &port->state->xmit; | |
da3564ee TM |
765 | struct scatterlist *sg = priv->sg_tx_p; |
766 | int i; | |
3c6a4832 | 767 | |
da3564ee TM |
768 | for (i = 0; i < priv->nent; i++, sg++) { |
769 | xmit->tail += sg_dma_len(sg); | |
770 | port->icount.tx += sg_dma_len(sg); | |
771 | } | |
3c6a4832 | 772 | xmit->tail &= UART_XMIT_SIZE - 1; |
3c6a4832 | 773 | async_tx_ack(priv->desc_tx); |
da3564ee | 774 | dma_unmap_sg(port->dev, sg, priv->nent, DMA_TO_DEVICE); |
3c6a4832 | 775 | priv->tx_dma_use = 0; |
da3564ee TM |
776 | priv->nent = 0; |
777 | kfree(priv->sg_tx_p); | |
60d1031e | 778 | pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT); |
3c6a4832 TM |
779 | } |
780 | ||
1822076c | 781 | static int pop_tx(struct eg20t_port *priv, int size) |
3c6a4832 TM |
782 | { |
783 | int count = 0; | |
784 | struct uart_port *port = &priv->port; | |
785 | struct circ_buf *xmit = &port->state->xmit; | |
786 | ||
787 | if (uart_tx_stopped(port) || uart_circ_empty(xmit) || count >= size) | |
788 | goto pop_tx_end; | |
789 | ||
790 | do { | |
791 | int cnt_to_end = | |
792 | CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE); | |
793 | int sz = min(size - count, cnt_to_end); | |
1822076c | 794 | pch_uart_hal_write(priv, &xmit->buf[xmit->tail], sz); |
3c6a4832 TM |
795 | xmit->tail = (xmit->tail + sz) & (UART_XMIT_SIZE - 1); |
796 | count += sz; | |
797 | } while (!uart_circ_empty(xmit) && count < size); | |
798 | ||
799 | pop_tx_end: | |
23877fdc | 800 | dev_dbg(priv->port.dev, "%d characters. Remained %d characters.(%lu)\n", |
3c6a4832 TM |
801 | count, size - count, jiffies); |
802 | ||
803 | return count; | |
804 | } | |
805 | ||
806 | static int handle_rx_to(struct eg20t_port *priv) | |
807 | { | |
808 | struct pch_uart_buffer *buf; | |
809 | int rx_size; | |
810 | int ret; | |
811 | if (!priv->start_rx) { | |
812 | pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT); | |
813 | return 0; | |
814 | } | |
815 | buf = &priv->rxbuf; | |
816 | do { | |
817 | rx_size = pch_uart_hal_read(priv, buf->buf, buf->size); | |
818 | ret = push_rx(priv, buf->buf, rx_size); | |
819 | if (ret) | |
820 | return 0; | |
821 | } while (rx_size == buf->size); | |
822 | ||
823 | return PCH_UART_HANDLED_RX_INT; | |
824 | } | |
825 | ||
826 | static int handle_rx(struct eg20t_port *priv) | |
827 | { | |
828 | return handle_rx_to(priv); | |
829 | } | |
830 | ||
831 | static int dma_handle_rx(struct eg20t_port *priv) | |
832 | { | |
833 | struct uart_port *port = &priv->port; | |
834 | struct dma_async_tx_descriptor *desc; | |
835 | struct scatterlist *sg; | |
836 | ||
837 | priv = container_of(port, struct eg20t_port, port); | |
838 | sg = &priv->sg_rx; | |
839 | ||
840 | sg_init_table(&priv->sg_rx, 1); /* Initialize SG table */ | |
841 | ||
da3564ee | 842 | sg_dma_len(sg) = priv->trigger_level; |
3c6a4832 TM |
843 | |
844 | sg_set_page(&priv->sg_rx, virt_to_page(priv->rx_buf_virt), | |
1c518997 TM |
845 | sg_dma_len(sg), (unsigned long)priv->rx_buf_virt & |
846 | ~PAGE_MASK); | |
3c6a4832 TM |
847 | |
848 | sg_dma_address(sg) = priv->rx_buf_dma; | |
849 | ||
16052827 | 850 | desc = dmaengine_prep_slave_sg(priv->chan_rx, |
a485df4b | 851 | sg, 1, DMA_DEV_TO_MEM, |
da3564ee TM |
852 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
853 | ||
3c6a4832 TM |
854 | if (!desc) |
855 | return 0; | |
856 | ||
857 | priv->desc_rx = desc; | |
858 | desc->callback = pch_dma_rx_complete; | |
859 | desc->callback_param = priv; | |
860 | desc->tx_submit(desc); | |
861 | dma_async_issue_pending(priv->chan_rx); | |
862 | ||
863 | return PCH_UART_HANDLED_RX_INT; | |
864 | } | |
865 | ||
866 | static unsigned int handle_tx(struct eg20t_port *priv) | |
867 | { | |
868 | struct uart_port *port = &priv->port; | |
869 | struct circ_buf *xmit = &port->state->xmit; | |
3c6a4832 TM |
870 | int fifo_size; |
871 | int tx_size; | |
872 | int size; | |
873 | int tx_empty; | |
874 | ||
875 | if (!priv->start_tx) { | |
23877fdc TM |
876 | dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n", |
877 | __func__, jiffies); | |
3c6a4832 TM |
878 | pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT); |
879 | priv->tx_empty = 1; | |
880 | return 0; | |
881 | } | |
882 | ||
883 | fifo_size = max(priv->fifo_size, 1); | |
884 | tx_empty = 1; | |
885 | if (pop_tx_x(priv, xmit->buf)) { | |
886 | pch_uart_hal_write(priv, xmit->buf, 1); | |
887 | port->icount.tx++; | |
888 | tx_empty = 0; | |
889 | fifo_size--; | |
890 | } | |
891 | size = min(xmit->head - xmit->tail, fifo_size); | |
da3564ee TM |
892 | if (size < 0) |
893 | size = fifo_size; | |
894 | ||
1822076c | 895 | tx_size = pop_tx(priv, size); |
3c6a4832 | 896 | if (tx_size > 0) { |
1822076c | 897 | port->icount.tx += tx_size; |
3c6a4832 TM |
898 | tx_empty = 0; |
899 | } | |
900 | ||
901 | priv->tx_empty = tx_empty; | |
902 | ||
da3564ee | 903 | if (tx_empty) { |
3c6a4832 | 904 | pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT); |
da3564ee TM |
905 | uart_write_wakeup(port); |
906 | } | |
3c6a4832 TM |
907 | |
908 | return PCH_UART_HANDLED_TX_INT; | |
909 | } | |
910 | ||
911 | static unsigned int dma_handle_tx(struct eg20t_port *priv) | |
912 | { | |
913 | struct uart_port *port = &priv->port; | |
914 | struct circ_buf *xmit = &port->state->xmit; | |
da3564ee | 915 | struct scatterlist *sg; |
3c6a4832 TM |
916 | int nent; |
917 | int fifo_size; | |
918 | int tx_empty; | |
919 | struct dma_async_tx_descriptor *desc; | |
da3564ee TM |
920 | int num; |
921 | int i; | |
922 | int bytes; | |
923 | int size; | |
924 | int rem; | |
3c6a4832 TM |
925 | |
926 | if (!priv->start_tx) { | |
23877fdc TM |
927 | dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n", |
928 | __func__, jiffies); | |
3c6a4832 TM |
929 | pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT); |
930 | priv->tx_empty = 1; | |
931 | return 0; | |
932 | } | |
933 | ||
60d1031e TM |
934 | if (priv->tx_dma_use) { |
935 | dev_dbg(priv->port.dev, "%s:Tx is not completed. (%lu)\n", | |
936 | __func__, jiffies); | |
937 | pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT); | |
938 | priv->tx_empty = 1; | |
939 | return 0; | |
940 | } | |
941 | ||
3c6a4832 TM |
942 | fifo_size = max(priv->fifo_size, 1); |
943 | tx_empty = 1; | |
944 | if (pop_tx_x(priv, xmit->buf)) { | |
945 | pch_uart_hal_write(priv, xmit->buf, 1); | |
946 | port->icount.tx++; | |
947 | tx_empty = 0; | |
948 | fifo_size--; | |
949 | } | |
950 | ||
da3564ee TM |
951 | bytes = min((int)CIRC_CNT(xmit->head, xmit->tail, |
952 | UART_XMIT_SIZE), CIRC_CNT_TO_END(xmit->head, | |
953 | xmit->tail, UART_XMIT_SIZE)); | |
954 | if (!bytes) { | |
23877fdc | 955 | dev_dbg(priv->port.dev, "%s 0 bytes return\n", __func__); |
da3564ee TM |
956 | pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT); |
957 | uart_write_wakeup(port); | |
958 | return 0; | |
959 | } | |
960 | ||
961 | if (bytes > fifo_size) { | |
962 | num = bytes / fifo_size + 1; | |
963 | size = fifo_size; | |
964 | rem = bytes % fifo_size; | |
965 | } else { | |
966 | num = 1; | |
967 | size = bytes; | |
968 | rem = bytes; | |
969 | } | |
3c6a4832 | 970 | |
23877fdc TM |
971 | dev_dbg(priv->port.dev, "%s num=%d size=%d rem=%d\n", |
972 | __func__, num, size, rem); | |
973 | ||
3c6a4832 TM |
974 | priv->tx_dma_use = 1; |
975 | ||
da3564ee | 976 | priv->sg_tx_p = kzalloc(sizeof(struct scatterlist)*num, GFP_ATOMIC); |
3c6a4832 | 977 | |
da3564ee TM |
978 | sg_init_table(priv->sg_tx_p, num); /* Initialize SG table */ |
979 | sg = priv->sg_tx_p; | |
3c6a4832 | 980 | |
da3564ee TM |
981 | for (i = 0; i < num; i++, sg++) { |
982 | if (i == (num - 1)) | |
983 | sg_set_page(sg, virt_to_page(xmit->buf), | |
984 | rem, fifo_size * i); | |
985 | else | |
986 | sg_set_page(sg, virt_to_page(xmit->buf), | |
987 | size, fifo_size * i); | |
988 | } | |
989 | ||
990 | sg = priv->sg_tx_p; | |
991 | nent = dma_map_sg(port->dev, sg, num, DMA_TO_DEVICE); | |
3c6a4832 | 992 | if (!nent) { |
23877fdc | 993 | dev_err(priv->port.dev, "%s:dma_map_sg Failed\n", __func__); |
3c6a4832 TM |
994 | return 0; |
995 | } | |
da3564ee TM |
996 | priv->nent = nent; |
997 | ||
998 | for (i = 0; i < nent; i++, sg++) { | |
999 | sg->offset = (xmit->tail & (UART_XMIT_SIZE - 1)) + | |
1000 | fifo_size * i; | |
1001 | sg_dma_address(sg) = (sg_dma_address(sg) & | |
1002 | ~(UART_XMIT_SIZE - 1)) + sg->offset; | |
1003 | if (i == (nent - 1)) | |
1004 | sg_dma_len(sg) = rem; | |
1005 | else | |
1006 | sg_dma_len(sg) = size; | |
1007 | } | |
3c6a4832 | 1008 | |
16052827 | 1009 | desc = dmaengine_prep_slave_sg(priv->chan_tx, |
a485df4b | 1010 | priv->sg_tx_p, nent, DMA_MEM_TO_DEV, |
da3564ee | 1011 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); |
3c6a4832 | 1012 | if (!desc) { |
23877fdc TM |
1013 | dev_err(priv->port.dev, "%s:device_prep_slave_sg Failed\n", |
1014 | __func__); | |
3c6a4832 TM |
1015 | return 0; |
1016 | } | |
da3564ee | 1017 | dma_sync_sg_for_device(port->dev, priv->sg_tx_p, nent, DMA_TO_DEVICE); |
3c6a4832 TM |
1018 | priv->desc_tx = desc; |
1019 | desc->callback = pch_dma_tx_complete; | |
1020 | desc->callback_param = priv; | |
1021 | ||
1022 | desc->tx_submit(desc); | |
1023 | ||
1024 | dma_async_issue_pending(priv->chan_tx); | |
1025 | ||
1026 | return PCH_UART_HANDLED_TX_INT; | |
1027 | } | |
1028 | ||
1029 | static void pch_uart_err_ir(struct eg20t_port *priv, unsigned int lsr) | |
1030 | { | |
1031 | u8 fcr = ioread8(priv->membase + UART_FCR); | |
1032 | ||
1033 | /* Reset FIFO */ | |
1034 | fcr |= UART_FCR_CLEAR_RCVR; | |
1035 | iowrite8(fcr, priv->membase + UART_FCR); | |
1036 | ||
1037 | if (lsr & PCH_UART_LSR_ERR) | |
1038 | dev_err(&priv->pdev->dev, "Error data in FIFO\n"); | |
1039 | ||
1040 | if (lsr & UART_LSR_FE) | |
1041 | dev_err(&priv->pdev->dev, "Framing Error\n"); | |
1042 | ||
1043 | if (lsr & UART_LSR_PE) | |
1044 | dev_err(&priv->pdev->dev, "Parity Error\n"); | |
1045 | ||
1046 | if (lsr & UART_LSR_OE) | |
1047 | dev_err(&priv->pdev->dev, "Overrun Error\n"); | |
1048 | } | |
1049 | ||
1050 | static irqreturn_t pch_uart_interrupt(int irq, void *dev_id) | |
1051 | { | |
1052 | struct eg20t_port *priv = dev_id; | |
1053 | unsigned int handled; | |
1054 | u8 lsr; | |
1055 | int ret = 0; | |
1056 | unsigned int iid; | |
1057 | unsigned long flags; | |
1058 | ||
1059 | spin_lock_irqsave(&priv->port.lock, flags); | |
1060 | handled = 0; | |
1061 | while ((iid = pch_uart_hal_get_iid(priv)) > 1) { | |
1062 | switch (iid) { | |
1063 | case PCH_UART_IID_RLS: /* Receiver Line Status */ | |
1064 | lsr = pch_uart_hal_get_line_status(priv); | |
1065 | if (lsr & (PCH_UART_LSR_ERR | UART_LSR_FE | | |
1066 | UART_LSR_PE | UART_LSR_OE)) { | |
1067 | pch_uart_err_ir(priv, lsr); | |
1068 | ret = PCH_UART_HANDLED_RX_ERR_INT; | |
1069 | } | |
1070 | break; | |
1071 | case PCH_UART_IID_RDR: /* Received Data Ready */ | |
da3564ee TM |
1072 | if (priv->use_dma) { |
1073 | pch_uart_hal_disable_interrupt(priv, | |
1074 | PCH_UART_HAL_RX_INT); | |
3c6a4832 | 1075 | ret = dma_handle_rx(priv); |
da3564ee TM |
1076 | if (!ret) |
1077 | pch_uart_hal_enable_interrupt(priv, | |
1078 | PCH_UART_HAL_RX_INT); | |
1079 | } else { | |
3c6a4832 | 1080 | ret = handle_rx(priv); |
da3564ee | 1081 | } |
3c6a4832 TM |
1082 | break; |
1083 | case PCH_UART_IID_RDR_TO: /* Received Data Ready | |
1084 | (FIFO Timeout) */ | |
1085 | ret = handle_rx_to(priv); | |
1086 | break; | |
1087 | case PCH_UART_IID_THRE: /* Transmitter Holding Register | |
1088 | Empty */ | |
1089 | if (priv->use_dma) | |
1090 | ret = dma_handle_tx(priv); | |
1091 | else | |
1092 | ret = handle_tx(priv); | |
1093 | break; | |
1094 | case PCH_UART_IID_MS: /* Modem Status */ | |
1095 | ret = PCH_UART_HANDLED_MS_INT; | |
1096 | break; | |
1097 | default: /* Never junp to this label */ | |
23877fdc TM |
1098 | dev_err(priv->port.dev, "%s:iid=%d (%lu)\n", __func__, |
1099 | iid, jiffies); | |
3c6a4832 TM |
1100 | ret = -1; |
1101 | break; | |
1102 | } | |
1103 | handled |= (unsigned int)ret; | |
1104 | } | |
1105 | if (handled == 0 && iid <= 1) { | |
1106 | if (priv->int_dis_flag) | |
1107 | priv->int_dis_flag = 0; | |
1108 | } | |
1109 | ||
1110 | spin_unlock_irqrestore(&priv->port.lock, flags); | |
1111 | return IRQ_RETVAL(handled); | |
1112 | } | |
1113 | ||
1114 | /* This function tests whether the transmitter fifo and shifter for the port | |
1115 | described by 'port' is empty. */ | |
1116 | static unsigned int pch_uart_tx_empty(struct uart_port *port) | |
1117 | { | |
1118 | struct eg20t_port *priv; | |
30c6c6b5 | 1119 | |
3c6a4832 TM |
1120 | priv = container_of(port, struct eg20t_port, port); |
1121 | if (priv->tx_empty) | |
30c6c6b5 | 1122 | return TIOCSER_TEMT; |
3c6a4832 | 1123 | else |
30c6c6b5 | 1124 | return 0; |
3c6a4832 TM |
1125 | } |
1126 | ||
1127 | /* Returns the current state of modem control inputs. */ | |
1128 | static unsigned int pch_uart_get_mctrl(struct uart_port *port) | |
1129 | { | |
1130 | struct eg20t_port *priv; | |
1131 | u8 modem; | |
1132 | unsigned int ret = 0; | |
1133 | ||
1134 | priv = container_of(port, struct eg20t_port, port); | |
1135 | modem = pch_uart_hal_get_modem(priv); | |
1136 | ||
1137 | if (modem & UART_MSR_DCD) | |
1138 | ret |= TIOCM_CAR; | |
1139 | ||
1140 | if (modem & UART_MSR_RI) | |
1141 | ret |= TIOCM_RNG; | |
1142 | ||
1143 | if (modem & UART_MSR_DSR) | |
1144 | ret |= TIOCM_DSR; | |
1145 | ||
1146 | if (modem & UART_MSR_CTS) | |
1147 | ret |= TIOCM_CTS; | |
1148 | ||
1149 | return ret; | |
1150 | } | |
1151 | ||
1152 | static void pch_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) | |
1153 | { | |
1154 | u32 mcr = 0; | |
3c6a4832 TM |
1155 | struct eg20t_port *priv = container_of(port, struct eg20t_port, port); |
1156 | ||
1157 | if (mctrl & TIOCM_DTR) | |
1158 | mcr |= UART_MCR_DTR; | |
1159 | if (mctrl & TIOCM_RTS) | |
1160 | mcr |= UART_MCR_RTS; | |
1161 | if (mctrl & TIOCM_LOOP) | |
1162 | mcr |= UART_MCR_LOOP; | |
1163 | ||
9af7155b TM |
1164 | if (priv->mcr & UART_MCR_AFE) |
1165 | mcr |= UART_MCR_AFE; | |
1166 | ||
1167 | if (mctrl) | |
1168 | iowrite8(mcr, priv->membase + UART_MCR); | |
3c6a4832 TM |
1169 | } |
1170 | ||
1171 | static void pch_uart_stop_tx(struct uart_port *port) | |
1172 | { | |
1173 | struct eg20t_port *priv; | |
1174 | priv = container_of(port, struct eg20t_port, port); | |
1175 | priv->start_tx = 0; | |
1176 | priv->tx_dma_use = 0; | |
1177 | } | |
1178 | ||
1179 | static void pch_uart_start_tx(struct uart_port *port) | |
1180 | { | |
1181 | struct eg20t_port *priv; | |
1182 | ||
1183 | priv = container_of(port, struct eg20t_port, port); | |
1184 | ||
23877fdc TM |
1185 | if (priv->use_dma) { |
1186 | if (priv->tx_dma_use) { | |
1187 | dev_dbg(priv->port.dev, "%s : Tx DMA is NOT empty.\n", | |
1188 | __func__); | |
3c6a4832 | 1189 | return; |
23877fdc TM |
1190 | } |
1191 | } | |
3c6a4832 TM |
1192 | |
1193 | priv->start_tx = 1; | |
1194 | pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT); | |
1195 | } | |
1196 | ||
1197 | static void pch_uart_stop_rx(struct uart_port *port) | |
1198 | { | |
1199 | struct eg20t_port *priv; | |
1200 | priv = container_of(port, struct eg20t_port, port); | |
1201 | priv->start_rx = 0; | |
1202 | pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT); | |
1203 | priv->int_dis_flag = 1; | |
1204 | } | |
1205 | ||
1206 | /* Enable the modem status interrupts. */ | |
1207 | static void pch_uart_enable_ms(struct uart_port *port) | |
1208 | { | |
1209 | struct eg20t_port *priv; | |
1210 | priv = container_of(port, struct eg20t_port, port); | |
1211 | pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_MS_INT); | |
1212 | } | |
1213 | ||
1214 | /* Control the transmission of a break signal. */ | |
1215 | static void pch_uart_break_ctl(struct uart_port *port, int ctl) | |
1216 | { | |
1217 | struct eg20t_port *priv; | |
1218 | unsigned long flags; | |
1219 | ||
1220 | priv = container_of(port, struct eg20t_port, port); | |
1221 | spin_lock_irqsave(&port->lock, flags); | |
1222 | pch_uart_hal_set_break(priv, ctl); | |
1223 | spin_unlock_irqrestore(&port->lock, flags); | |
1224 | } | |
1225 | ||
1226 | /* Grab any interrupt resources and initialise any low level driver state. */ | |
1227 | static int pch_uart_startup(struct uart_port *port) | |
1228 | { | |
1229 | struct eg20t_port *priv; | |
1230 | int ret; | |
1231 | int fifo_size; | |
1232 | int trigger_level; | |
1233 | ||
1234 | priv = container_of(port, struct eg20t_port, port); | |
1235 | priv->tx_empty = 1; | |
aac6c0b0 TM |
1236 | |
1237 | if (port->uartclk) | |
a8a3ec9d | 1238 | priv->uartclk = port->uartclk; |
aac6c0b0 | 1239 | else |
a8a3ec9d | 1240 | port->uartclk = priv->uartclk; |
aac6c0b0 | 1241 | |
3c6a4832 TM |
1242 | pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT); |
1243 | ret = pch_uart_hal_set_line(priv, default_baud, | |
1244 | PCH_UART_HAL_PARITY_NONE, PCH_UART_HAL_8BIT, | |
1245 | PCH_UART_HAL_STB1); | |
1246 | if (ret) | |
1247 | return ret; | |
1248 | ||
1249 | switch (priv->fifo_size) { | |
1250 | case 256: | |
1251 | fifo_size = PCH_UART_HAL_FIFO256; | |
1252 | break; | |
1253 | case 64: | |
1254 | fifo_size = PCH_UART_HAL_FIFO64; | |
1255 | break; | |
1256 | case 16: | |
1257 | fifo_size = PCH_UART_HAL_FIFO16; | |
1258 | case 1: | |
1259 | default: | |
1260 | fifo_size = PCH_UART_HAL_FIFO_DIS; | |
1261 | break; | |
1262 | } | |
1263 | ||
1264 | switch (priv->trigger) { | |
1265 | case PCH_UART_HAL_TRIGGER1: | |
1266 | trigger_level = 1; | |
1267 | break; | |
1268 | case PCH_UART_HAL_TRIGGER_L: | |
1269 | trigger_level = priv->fifo_size / 4; | |
1270 | break; | |
1271 | case PCH_UART_HAL_TRIGGER_M: | |
1272 | trigger_level = priv->fifo_size / 2; | |
1273 | break; | |
1274 | case PCH_UART_HAL_TRIGGER_H: | |
1275 | default: | |
1276 | trigger_level = priv->fifo_size - (priv->fifo_size / 8); | |
1277 | break; | |
1278 | } | |
1279 | ||
1280 | priv->trigger_level = trigger_level; | |
1281 | ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0, | |
1282 | fifo_size, priv->trigger); | |
1283 | if (ret < 0) | |
1284 | return ret; | |
1285 | ||
1286 | ret = request_irq(priv->port.irq, pch_uart_interrupt, IRQF_SHARED, | |
1287 | KBUILD_MODNAME, priv); | |
1288 | if (ret < 0) | |
1289 | return ret; | |
1290 | ||
1291 | if (priv->use_dma) | |
1292 | pch_request_dma(port); | |
1293 | ||
1294 | priv->start_rx = 1; | |
1295 | pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT); | |
1296 | uart_update_timeout(port, CS8, default_baud); | |
1297 | ||
1298 | return 0; | |
1299 | } | |
1300 | ||
1301 | static void pch_uart_shutdown(struct uart_port *port) | |
1302 | { | |
1303 | struct eg20t_port *priv; | |
1304 | int ret; | |
1305 | ||
1306 | priv = container_of(port, struct eg20t_port, port); | |
1307 | pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT); | |
1308 | pch_uart_hal_fifo_reset(priv, PCH_UART_HAL_CLR_ALL_FIFO); | |
1309 | ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0, | |
1310 | PCH_UART_HAL_FIFO_DIS, PCH_UART_HAL_TRIGGER1); | |
1311 | if (ret) | |
23877fdc TM |
1312 | dev_err(priv->port.dev, |
1313 | "pch_uart_hal_set_fifo Failed(ret=%d)\n", ret); | |
3c6a4832 | 1314 | |
90f04c29 | 1315 | pch_free_dma(port); |
3c6a4832 TM |
1316 | |
1317 | free_irq(priv->port.irq, priv); | |
1318 | } | |
1319 | ||
1320 | /* Change the port parameters, including word length, parity, stop | |
1321 | *bits. Update read_status_mask and ignore_status_mask to indicate | |
1322 | *the types of events we are interested in receiving. */ | |
1323 | static void pch_uart_set_termios(struct uart_port *port, | |
1324 | struct ktermios *termios, struct ktermios *old) | |
1325 | { | |
1326 | int baud; | |
1327 | int rtn; | |
1328 | unsigned int parity, bits, stb; | |
1329 | struct eg20t_port *priv; | |
1330 | unsigned long flags; | |
1331 | ||
1332 | priv = container_of(port, struct eg20t_port, port); | |
1333 | switch (termios->c_cflag & CSIZE) { | |
1334 | case CS5: | |
1335 | bits = PCH_UART_HAL_5BIT; | |
1336 | break; | |
1337 | case CS6: | |
1338 | bits = PCH_UART_HAL_6BIT; | |
1339 | break; | |
1340 | case CS7: | |
1341 | bits = PCH_UART_HAL_7BIT; | |
1342 | break; | |
1343 | default: /* CS8 */ | |
1344 | bits = PCH_UART_HAL_8BIT; | |
1345 | break; | |
1346 | } | |
1347 | if (termios->c_cflag & CSTOPB) | |
1348 | stb = PCH_UART_HAL_STB2; | |
1349 | else | |
1350 | stb = PCH_UART_HAL_STB1; | |
1351 | ||
1352 | if (termios->c_cflag & PARENB) { | |
1353 | if (!(termios->c_cflag & PARODD)) | |
1354 | parity = PCH_UART_HAL_PARITY_ODD; | |
1355 | else | |
1356 | parity = PCH_UART_HAL_PARITY_EVEN; | |
1357 | ||
30c6c6b5 | 1358 | } else |
3c6a4832 | 1359 | parity = PCH_UART_HAL_PARITY_NONE; |
9af7155b TM |
1360 | |
1361 | /* Only UART0 has auto hardware flow function */ | |
1362 | if ((termios->c_cflag & CRTSCTS) && (priv->fifo_size == 256)) | |
1363 | priv->mcr |= UART_MCR_AFE; | |
1364 | else | |
1365 | priv->mcr &= ~UART_MCR_AFE; | |
1366 | ||
3c6a4832 TM |
1367 | termios->c_cflag &= ~CMSPAR; /* Mark/Space parity is not supported */ |
1368 | ||
1369 | baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16); | |
1370 | ||
1371 | spin_lock_irqsave(&port->lock, flags); | |
1372 | ||
1373 | uart_update_timeout(port, termios->c_cflag, baud); | |
1374 | rtn = pch_uart_hal_set_line(priv, baud, parity, bits, stb); | |
1375 | if (rtn) | |
1376 | goto out; | |
1377 | ||
a1d7cfe2 | 1378 | pch_uart_set_mctrl(&priv->port, priv->port.mctrl); |
3c6a4832 TM |
1379 | /* Don't rewrite B0 */ |
1380 | if (tty_termios_baud_rate(termios)) | |
1381 | tty_termios_encode_baud_rate(termios, baud, baud); | |
1382 | ||
1383 | out: | |
1384 | spin_unlock_irqrestore(&port->lock, flags); | |
1385 | } | |
1386 | ||
1387 | static const char *pch_uart_type(struct uart_port *port) | |
1388 | { | |
1389 | return KBUILD_MODNAME; | |
1390 | } | |
1391 | ||
1392 | static void pch_uart_release_port(struct uart_port *port) | |
1393 | { | |
1394 | struct eg20t_port *priv; | |
1395 | ||
1396 | priv = container_of(port, struct eg20t_port, port); | |
1397 | pci_iounmap(priv->pdev, priv->membase); | |
1398 | pci_release_regions(priv->pdev); | |
1399 | } | |
1400 | ||
1401 | static int pch_uart_request_port(struct uart_port *port) | |
1402 | { | |
1403 | struct eg20t_port *priv; | |
1404 | int ret; | |
1405 | void __iomem *membase; | |
1406 | ||
1407 | priv = container_of(port, struct eg20t_port, port); | |
1408 | ret = pci_request_regions(priv->pdev, KBUILD_MODNAME); | |
1409 | if (ret < 0) | |
1410 | return -EBUSY; | |
1411 | ||
1412 | membase = pci_iomap(priv->pdev, 1, 0); | |
1413 | if (!membase) { | |
1414 | pci_release_regions(priv->pdev); | |
1415 | return -EBUSY; | |
1416 | } | |
1417 | priv->membase = port->membase = membase; | |
1418 | ||
1419 | return 0; | |
1420 | } | |
1421 | ||
1422 | static void pch_uart_config_port(struct uart_port *port, int type) | |
1423 | { | |
1424 | struct eg20t_port *priv; | |
1425 | ||
1426 | priv = container_of(port, struct eg20t_port, port); | |
1427 | if (type & UART_CONFIG_TYPE) { | |
1428 | port->type = priv->port_type; | |
1429 | pch_uart_request_port(port); | |
1430 | } | |
1431 | } | |
1432 | ||
1433 | static int pch_uart_verify_port(struct uart_port *port, | |
1434 | struct serial_struct *serinfo) | |
1435 | { | |
1436 | struct eg20t_port *priv; | |
1437 | ||
1438 | priv = container_of(port, struct eg20t_port, port); | |
1439 | if (serinfo->flags & UPF_LOW_LATENCY) { | |
23877fdc TM |
1440 | dev_info(priv->port.dev, |
1441 | "PCH UART : Use PIO Mode (without DMA)\n"); | |
3c6a4832 TM |
1442 | priv->use_dma = 0; |
1443 | serinfo->flags &= ~UPF_LOW_LATENCY; | |
1444 | } else { | |
1445 | #ifndef CONFIG_PCH_DMA | |
23877fdc TM |
1446 | dev_err(priv->port.dev, "%s : PCH DMA is not Loaded.\n", |
1447 | __func__); | |
3c6a4832 TM |
1448 | return -EOPNOTSUPP; |
1449 | #endif | |
1450 | priv->use_dma = 1; | |
1451 | priv->use_dma_flag = 1; | |
23877fdc | 1452 | dev_info(priv->port.dev, "PCH UART : Use DMA Mode\n"); |
3c6a4832 TM |
1453 | } |
1454 | ||
1455 | return 0; | |
1456 | } | |
1457 | ||
1458 | static struct uart_ops pch_uart_ops = { | |
1459 | .tx_empty = pch_uart_tx_empty, | |
1460 | .set_mctrl = pch_uart_set_mctrl, | |
1461 | .get_mctrl = pch_uart_get_mctrl, | |
1462 | .stop_tx = pch_uart_stop_tx, | |
1463 | .start_tx = pch_uart_start_tx, | |
1464 | .stop_rx = pch_uart_stop_rx, | |
1465 | .enable_ms = pch_uart_enable_ms, | |
1466 | .break_ctl = pch_uart_break_ctl, | |
1467 | .startup = pch_uart_startup, | |
1468 | .shutdown = pch_uart_shutdown, | |
1469 | .set_termios = pch_uart_set_termios, | |
1470 | /* .pm = pch_uart_pm, Not supported yet */ | |
1471 | /* .set_wake = pch_uart_set_wake, Not supported yet */ | |
1472 | .type = pch_uart_type, | |
1473 | .release_port = pch_uart_release_port, | |
1474 | .request_port = pch_uart_request_port, | |
1475 | .config_port = pch_uart_config_port, | |
1476 | .verify_port = pch_uart_verify_port | |
1477 | }; | |
1478 | ||
e30f867d AS |
1479 | #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE |
1480 | ||
1481 | /* | |
1482 | * Wait for transmitter & holding register to empty | |
1483 | */ | |
1484 | static void wait_for_xmitr(struct eg20t_port *up, int bits) | |
1485 | { | |
1486 | unsigned int status, tmout = 10000; | |
1487 | ||
1488 | /* Wait up to 10ms for the character(s) to be sent. */ | |
1489 | for (;;) { | |
1490 | status = ioread8(up->membase + UART_LSR); | |
1491 | ||
1492 | if ((status & bits) == bits) | |
1493 | break; | |
1494 | if (--tmout == 0) | |
1495 | break; | |
1496 | udelay(1); | |
1497 | } | |
1498 | ||
1499 | /* Wait up to 1s for flow control if necessary */ | |
1500 | if (up->port.flags & UPF_CONS_FLOW) { | |
1501 | unsigned int tmout; | |
1502 | for (tmout = 1000000; tmout; tmout--) { | |
1503 | unsigned int msr = ioread8(up->membase + UART_MSR); | |
1504 | if (msr & UART_MSR_CTS) | |
1505 | break; | |
1506 | udelay(1); | |
1507 | touch_nmi_watchdog(); | |
1508 | } | |
1509 | } | |
1510 | } | |
1511 | ||
1512 | static void pch_console_putchar(struct uart_port *port, int ch) | |
1513 | { | |
1514 | struct eg20t_port *priv = | |
1515 | container_of(port, struct eg20t_port, port); | |
1516 | ||
1517 | wait_for_xmitr(priv, UART_LSR_THRE); | |
1518 | iowrite8(ch, priv->membase + PCH_UART_THR); | |
1519 | } | |
1520 | ||
1521 | /* | |
1522 | * Print a string to the serial port trying not to disturb | |
1523 | * any possible real use of the port... | |
1524 | * | |
1525 | * The console_lock must be held when we get here. | |
1526 | */ | |
1527 | static void | |
1528 | pch_console_write(struct console *co, const char *s, unsigned int count) | |
1529 | { | |
1530 | struct eg20t_port *priv; | |
e30f867d AS |
1531 | unsigned long flags; |
1532 | u8 ier; | |
1533 | int locked = 1; | |
1534 | ||
1535 | priv = pch_uart_ports[co->index]; | |
1536 | ||
1537 | touch_nmi_watchdog(); | |
1538 | ||
1539 | local_irq_save(flags); | |
1540 | if (priv->port.sysrq) { | |
1541 | /* serial8250_handle_port() already took the lock */ | |
1542 | locked = 0; | |
1543 | } else if (oops_in_progress) { | |
1544 | locked = spin_trylock(&priv->port.lock); | |
1545 | } else | |
1546 | spin_lock(&priv->port.lock); | |
1547 | ||
1548 | /* | |
1549 | * First save the IER then disable the interrupts | |
1550 | */ | |
1551 | ier = ioread8(priv->membase + UART_IER); | |
1552 | ||
1553 | pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT); | |
1554 | ||
1555 | uart_console_write(&priv->port, s, count, pch_console_putchar); | |
1556 | ||
1557 | /* | |
1558 | * Finally, wait for transmitter to become empty | |
1559 | * and restore the IER | |
1560 | */ | |
1561 | wait_for_xmitr(priv, BOTH_EMPTY); | |
1562 | iowrite8(ier, priv->membase + UART_IER); | |
1563 | ||
1564 | if (locked) | |
1565 | spin_unlock(&priv->port.lock); | |
1566 | local_irq_restore(flags); | |
1567 | } | |
1568 | ||
1569 | static int __init pch_console_setup(struct console *co, char *options) | |
1570 | { | |
1571 | struct uart_port *port; | |
7ce9251d | 1572 | int baud = default_baud; |
e30f867d AS |
1573 | int bits = 8; |
1574 | int parity = 'n'; | |
1575 | int flow = 'n'; | |
1576 | ||
1577 | /* | |
1578 | * Check whether an invalid uart number has been specified, and | |
1579 | * if so, search for the first available port that does have | |
1580 | * console support. | |
1581 | */ | |
1582 | if (co->index >= PCH_UART_NR) | |
1583 | co->index = 0; | |
1584 | port = &pch_uart_ports[co->index]->port; | |
1585 | ||
1586 | if (!port || (!port->iobase && !port->membase)) | |
1587 | return -ENODEV; | |
1588 | ||
077175f0 | 1589 | port->uartclk = pch_uart_get_uartclk(); |
e30f867d AS |
1590 | |
1591 | if (options) | |
1592 | uart_parse_options(options, &baud, &parity, &bits, &flow); | |
1593 | ||
1594 | return uart_set_options(port, co, baud, parity, bits, flow); | |
1595 | } | |
1596 | ||
1597 | static struct uart_driver pch_uart_driver; | |
1598 | ||
1599 | static struct console pch_console = { | |
1600 | .name = PCH_UART_DRIVER_DEVICE, | |
1601 | .write = pch_console_write, | |
1602 | .device = uart_console_device, | |
1603 | .setup = pch_console_setup, | |
1604 | .flags = CON_PRINTBUFFER | CON_ANYTIME, | |
1605 | .index = -1, | |
1606 | .data = &pch_uart_driver, | |
1607 | }; | |
1608 | ||
1609 | #define PCH_CONSOLE (&pch_console) | |
1610 | #else | |
1611 | #define PCH_CONSOLE NULL | |
1612 | #endif | |
1613 | ||
3c6a4832 TM |
1614 | static struct uart_driver pch_uart_driver = { |
1615 | .owner = THIS_MODULE, | |
1616 | .driver_name = KBUILD_MODNAME, | |
1617 | .dev_name = PCH_UART_DRIVER_DEVICE, | |
1618 | .major = 0, | |
1619 | .minor = 0, | |
1620 | .nr = PCH_UART_NR, | |
e30f867d | 1621 | .cons = PCH_CONSOLE, |
3c6a4832 TM |
1622 | }; |
1623 | ||
1624 | static struct eg20t_port *pch_uart_init_port(struct pci_dev *pdev, | |
4564e1ef | 1625 | const struct pci_device_id *id) |
3c6a4832 TM |
1626 | { |
1627 | struct eg20t_port *priv; | |
1628 | int ret; | |
1629 | unsigned int iobase; | |
1630 | unsigned int mapbase; | |
1c518997 | 1631 | unsigned char *rxbuf; |
077175f0 | 1632 | int fifosize; |
fec38d17 TM |
1633 | int port_type; |
1634 | struct pch_uart_driver_data *board; | |
d011411d | 1635 | char name[32]; /* for debugfs file name */ |
fec38d17 TM |
1636 | |
1637 | board = &drv_dat[id->driver_data]; | |
1638 | port_type = board->port_type; | |
3c6a4832 TM |
1639 | |
1640 | priv = kzalloc(sizeof(struct eg20t_port), GFP_KERNEL); | |
1641 | if (priv == NULL) | |
1642 | goto init_port_alloc_err; | |
1643 | ||
1c518997 | 1644 | rxbuf = (unsigned char *)__get_free_page(GFP_KERNEL); |
3c6a4832 TM |
1645 | if (!rxbuf) |
1646 | goto init_port_free_txbuf; | |
1647 | ||
1648 | switch (port_type) { | |
1649 | case PORT_UNKNOWN: | |
4564e1ef | 1650 | fifosize = 256; /* EG20T/ML7213: UART0 */ |
3c6a4832 TM |
1651 | break; |
1652 | case PORT_8250: | |
4564e1ef | 1653 | fifosize = 64; /* EG20T:UART1~3 ML7213: UART1~2*/ |
3c6a4832 TM |
1654 | break; |
1655 | default: | |
1656 | dev_err(&pdev->dev, "Invalid Port Type(=%d)\n", port_type); | |
1657 | goto init_port_hal_free; | |
1658 | } | |
1659 | ||
e463595f | 1660 | pci_enable_msi(pdev); |
867c902e | 1661 | pci_set_master(pdev); |
e463595f | 1662 | |
3c6a4832 TM |
1663 | iobase = pci_resource_start(pdev, 0); |
1664 | mapbase = pci_resource_start(pdev, 1); | |
1665 | priv->mapbase = mapbase; | |
1666 | priv->iobase = iobase; | |
1667 | priv->pdev = pdev; | |
1668 | priv->tx_empty = 1; | |
1c518997 | 1669 | priv->rxbuf.buf = rxbuf; |
3c6a4832 TM |
1670 | priv->rxbuf.size = PAGE_SIZE; |
1671 | ||
1672 | priv->fifo_size = fifosize; | |
077175f0 | 1673 | priv->uartclk = pch_uart_get_uartclk(); |
3c6a4832 TM |
1674 | priv->port_type = PORT_MAX_8250 + port_type + 1; |
1675 | priv->port.dev = &pdev->dev; | |
1676 | priv->port.iobase = iobase; | |
1677 | priv->port.membase = NULL; | |
1678 | priv->port.mapbase = mapbase; | |
1679 | priv->port.irq = pdev->irq; | |
1680 | priv->port.iotype = UPIO_PORT; | |
1681 | priv->port.ops = &pch_uart_ops; | |
1682 | priv->port.flags = UPF_BOOT_AUTOCONF; | |
1683 | priv->port.fifosize = fifosize; | |
fec38d17 | 1684 | priv->port.line = board->line_no; |
3c6a4832 TM |
1685 | priv->trigger = PCH_UART_HAL_TRIGGER_M; |
1686 | ||
7e461329 TM |
1687 | spin_lock_init(&priv->port.lock); |
1688 | ||
3c6a4832 | 1689 | pci_set_drvdata(pdev, priv); |
6f56d0f4 FT |
1690 | priv->trigger_level = 1; |
1691 | priv->fcr = 0; | |
4564e1ef | 1692 | |
e30f867d AS |
1693 | #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE |
1694 | pch_uart_ports[board->line_no] = priv; | |
1695 | #endif | |
3c6a4832 TM |
1696 | ret = uart_add_one_port(&pch_uart_driver, &priv->port); |
1697 | if (ret < 0) | |
1698 | goto init_port_hal_free; | |
1699 | ||
d011411d FT |
1700 | #ifdef CONFIG_DEBUG_FS |
1701 | snprintf(name, sizeof(name), "uart%d_regs", board->line_no); | |
1702 | priv->debugfs = debugfs_create_file(name, S_IFREG | S_IRUGO, | |
1703 | NULL, priv, &port_regs_ops); | |
1704 | #endif | |
1705 | ||
3c6a4832 TM |
1706 | return priv; |
1707 | ||
1708 | init_port_hal_free: | |
e30f867d AS |
1709 | #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE |
1710 | pch_uart_ports[board->line_no] = NULL; | |
1711 | #endif | |
1c518997 | 1712 | free_page((unsigned long)rxbuf); |
3c6a4832 TM |
1713 | init_port_free_txbuf: |
1714 | kfree(priv); | |
1715 | init_port_alloc_err: | |
1716 | ||
1717 | return NULL; | |
1718 | } | |
1719 | ||
1720 | static void pch_uart_exit_port(struct eg20t_port *priv) | |
1721 | { | |
d011411d FT |
1722 | |
1723 | #ifdef CONFIG_DEBUG_FS | |
1724 | if (priv->debugfs) | |
1725 | debugfs_remove(priv->debugfs); | |
1726 | #endif | |
3c6a4832 TM |
1727 | uart_remove_one_port(&pch_uart_driver, &priv->port); |
1728 | pci_set_drvdata(priv->pdev, NULL); | |
1c518997 | 1729 | free_page((unsigned long)priv->rxbuf.buf); |
3c6a4832 TM |
1730 | } |
1731 | ||
1732 | static void pch_uart_pci_remove(struct pci_dev *pdev) | |
1733 | { | |
6f56d0f4 | 1734 | struct eg20t_port *priv = pci_get_drvdata(pdev); |
e463595f AS |
1735 | |
1736 | pci_disable_msi(pdev); | |
e30f867d AS |
1737 | |
1738 | #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE | |
1739 | pch_uart_ports[priv->port.line] = NULL; | |
1740 | #endif | |
3c6a4832 TM |
1741 | pch_uart_exit_port(priv); |
1742 | pci_disable_device(pdev); | |
1743 | kfree(priv); | |
1744 | return; | |
1745 | } | |
1746 | #ifdef CONFIG_PM | |
1747 | static int pch_uart_pci_suspend(struct pci_dev *pdev, pm_message_t state) | |
1748 | { | |
1749 | struct eg20t_port *priv = pci_get_drvdata(pdev); | |
1750 | ||
1751 | uart_suspend_port(&pch_uart_driver, &priv->port); | |
1752 | ||
1753 | pci_save_state(pdev); | |
1754 | pci_set_power_state(pdev, pci_choose_state(pdev, state)); | |
1755 | return 0; | |
1756 | } | |
1757 | ||
1758 | static int pch_uart_pci_resume(struct pci_dev *pdev) | |
1759 | { | |
1760 | struct eg20t_port *priv = pci_get_drvdata(pdev); | |
1761 | int ret; | |
1762 | ||
1763 | pci_set_power_state(pdev, PCI_D0); | |
1764 | pci_restore_state(pdev); | |
1765 | ||
1766 | ret = pci_enable_device(pdev); | |
1767 | if (ret) { | |
1768 | dev_err(&pdev->dev, | |
1769 | "%s-pci_enable_device failed(ret=%d) ", __func__, ret); | |
1770 | return ret; | |
1771 | } | |
1772 | ||
1773 | uart_resume_port(&pch_uart_driver, &priv->port); | |
1774 | ||
1775 | return 0; | |
1776 | } | |
1777 | #else | |
1778 | #define pch_uart_pci_suspend NULL | |
1779 | #define pch_uart_pci_resume NULL | |
1780 | #endif | |
1781 | ||
1782 | static DEFINE_PCI_DEVICE_TABLE(pch_uart_pci_id) = { | |
1783 | {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8811), | |
fec38d17 | 1784 | .driver_data = pch_et20t_uart0}, |
3c6a4832 | 1785 | {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8812), |
fec38d17 | 1786 | .driver_data = pch_et20t_uart1}, |
3c6a4832 | 1787 | {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8813), |
fec38d17 | 1788 | .driver_data = pch_et20t_uart2}, |
3c6a4832 | 1789 | {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8814), |
fec38d17 | 1790 | .driver_data = pch_et20t_uart3}, |
4564e1ef | 1791 | {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8027), |
fec38d17 | 1792 | .driver_data = pch_ml7213_uart0}, |
4564e1ef | 1793 | {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8028), |
fec38d17 | 1794 | .driver_data = pch_ml7213_uart1}, |
4564e1ef | 1795 | {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8029), |
fec38d17 | 1796 | .driver_data = pch_ml7213_uart2}, |
177c2cbf TM |
1797 | {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800C), |
1798 | .driver_data = pch_ml7223_uart0}, | |
1799 | {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800D), | |
1800 | .driver_data = pch_ml7223_uart1}, | |
8249f743 TM |
1801 | {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8811), |
1802 | .driver_data = pch_ml7831_uart0}, | |
1803 | {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8812), | |
1804 | .driver_data = pch_ml7831_uart1}, | |
3c6a4832 TM |
1805 | {0,}, |
1806 | }; | |
1807 | ||
1808 | static int __devinit pch_uart_pci_probe(struct pci_dev *pdev, | |
1809 | const struct pci_device_id *id) | |
1810 | { | |
1811 | int ret; | |
1812 | struct eg20t_port *priv; | |
1813 | ||
1814 | ret = pci_enable_device(pdev); | |
1815 | if (ret < 0) | |
1816 | goto probe_error; | |
1817 | ||
4564e1ef | 1818 | priv = pch_uart_init_port(pdev, id); |
3c6a4832 TM |
1819 | if (!priv) { |
1820 | ret = -EBUSY; | |
1821 | goto probe_disable_device; | |
1822 | } | |
1823 | pci_set_drvdata(pdev, priv); | |
1824 | ||
1825 | return ret; | |
1826 | ||
1827 | probe_disable_device: | |
e463595f | 1828 | pci_disable_msi(pdev); |
3c6a4832 TM |
1829 | pci_disable_device(pdev); |
1830 | probe_error: | |
1831 | return ret; | |
1832 | } | |
1833 | ||
1834 | static struct pci_driver pch_uart_pci_driver = { | |
1835 | .name = "pch_uart", | |
1836 | .id_table = pch_uart_pci_id, | |
1837 | .probe = pch_uart_pci_probe, | |
1838 | .remove = __devexit_p(pch_uart_pci_remove), | |
1839 | .suspend = pch_uart_pci_suspend, | |
1840 | .resume = pch_uart_pci_resume, | |
1841 | }; | |
1842 | ||
1843 | static int __init pch_uart_module_init(void) | |
1844 | { | |
1845 | int ret; | |
1846 | ||
1847 | /* register as UART driver */ | |
1848 | ret = uart_register_driver(&pch_uart_driver); | |
1849 | if (ret < 0) | |
1850 | return ret; | |
1851 | ||
1852 | /* register as PCI driver */ | |
1853 | ret = pci_register_driver(&pch_uart_pci_driver); | |
1854 | if (ret < 0) | |
1855 | uart_unregister_driver(&pch_uart_driver); | |
1856 | ||
1857 | return ret; | |
1858 | } | |
1859 | module_init(pch_uart_module_init); | |
1860 | ||
1861 | static void __exit pch_uart_module_exit(void) | |
1862 | { | |
1863 | pci_unregister_driver(&pch_uart_pci_driver); | |
1864 | uart_unregister_driver(&pch_uart_driver); | |
1865 | } | |
1866 | module_exit(pch_uart_module_exit); | |
1867 | ||
1868 | MODULE_LICENSE("GPL v2"); | |
1869 | MODULE_DESCRIPTION("Intel EG20T PCH UART PCI Driver"); | |
1870 | module_param(default_baud, uint, S_IRUGO); | |
a46f5533 DH |
1871 | MODULE_PARM_DESC(default_baud, |
1872 | "Default BAUD for initial driver state and console (default 9600)"); | |
2a44feb2 | 1873 | module_param(user_uartclk, uint, S_IRUGO); |
a46f5533 DH |
1874 | MODULE_PARM_DESC(user_uartclk, |
1875 | "Override UART default or board specific UART clock"); |