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b612633b G |
1 | /* |
2 | * Driver for OMAP-UART controller. | |
3 | * Based on drivers/serial/8250.c | |
4 | * | |
5 | * Copyright (C) 2010 Texas Instruments. | |
6 | * | |
7 | * Authors: | |
8 | * Govindraj R <govindraj.raja@ti.com> | |
9 | * Thara Gopinath <thara@ti.com> | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2 of the License, or | |
14 | * (at your option) any later version. | |
15 | * | |
25985edc | 16 | * Note: This driver is made separate from 8250 driver as we cannot |
b612633b G |
17 | * over load 8250 driver with omap platform specific configuration for |
18 | * features like DMA, it makes easier to implement features like DMA and | |
19 | * hardware flow control and software flow control configuration with | |
20 | * this driver as required for the omap-platform. | |
21 | */ | |
22 | ||
364a6ece TW |
23 | #if defined(CONFIG_SERIAL_OMAP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) |
24 | #define SUPPORT_SYSRQ | |
25 | #endif | |
26 | ||
b612633b G |
27 | #include <linux/module.h> |
28 | #include <linux/init.h> | |
29 | #include <linux/console.h> | |
30 | #include <linux/serial_reg.h> | |
31 | #include <linux/delay.h> | |
32 | #include <linux/slab.h> | |
33 | #include <linux/tty.h> | |
34 | #include <linux/tty_flip.h> | |
35 | #include <linux/io.h> | |
36 | #include <linux/dma-mapping.h> | |
37 | #include <linux/clk.h> | |
38 | #include <linux/serial_core.h> | |
39 | #include <linux/irq.h> | |
fcdca757 | 40 | #include <linux/pm_runtime.h> |
b612633b G |
41 | |
42 | #include <plat/dma.h> | |
43 | #include <plat/dmtimer.h> | |
44 | #include <plat/omap-serial.h> | |
45 | ||
fcdca757 G |
46 | #define OMAP_UART_AUTOSUSPEND_DELAY -1 |
47 | ||
b612633b G |
48 | static struct uart_omap_port *ui[OMAP_MAX_HSUART_PORTS]; |
49 | ||
50 | /* Forward declaration of functions */ | |
51 | static void uart_tx_dma_callback(int lch, u16 ch_status, void *data); | |
52 | static void serial_omap_rx_timeout(unsigned long uart_no); | |
53 | static int serial_omap_start_rxdma(struct uart_omap_port *up); | |
54 | ||
55 | static inline unsigned int serial_in(struct uart_omap_port *up, int offset) | |
56 | { | |
57 | offset <<= up->port.regshift; | |
58 | return readw(up->port.membase + offset); | |
59 | } | |
60 | ||
61 | static inline void serial_out(struct uart_omap_port *up, int offset, int value) | |
62 | { | |
63 | offset <<= up->port.regshift; | |
64 | writew(value, up->port.membase + offset); | |
65 | } | |
66 | ||
67 | static inline void serial_omap_clear_fifos(struct uart_omap_port *up) | |
68 | { | |
69 | serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO); | |
70 | serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | | |
71 | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); | |
72 | serial_out(up, UART_FCR, 0); | |
73 | } | |
74 | ||
75 | /* | |
76 | * serial_omap_get_divisor - calculate divisor value | |
77 | * @port: uart port info | |
78 | * @baud: baudrate for which divisor needs to be calculated. | |
79 | * | |
80 | * We have written our own function to get the divisor so as to support | |
81 | * 13x mode. 3Mbps Baudrate as an different divisor. | |
82 | * Reference OMAP TRM Chapter 17: | |
83 | * Table 17-1. UART Mode Baud Rates, Divisor Values, and Error Rates | |
84 | * referring to oversampling - divisor value | |
85 | * baudrate 460,800 to 3,686,400 all have divisor 13 | |
86 | * except 3,000,000 which has divisor value 16 | |
87 | */ | |
88 | static unsigned int | |
89 | serial_omap_get_divisor(struct uart_port *port, unsigned int baud) | |
90 | { | |
91 | unsigned int divisor; | |
92 | ||
93 | if (baud > OMAP_MODE13X_SPEED && baud != 3000000) | |
94 | divisor = 13; | |
95 | else | |
96 | divisor = 16; | |
97 | return port->uartclk/(baud * divisor); | |
98 | } | |
99 | ||
100 | static void serial_omap_stop_rxdma(struct uart_omap_port *up) | |
101 | { | |
102 | if (up->uart_dma.rx_dma_used) { | |
103 | del_timer(&up->uart_dma.rx_timer); | |
104 | omap_stop_dma(up->uart_dma.rx_dma_channel); | |
105 | omap_free_dma(up->uart_dma.rx_dma_channel); | |
106 | up->uart_dma.rx_dma_channel = OMAP_UART_DMA_CH_FREE; | |
107 | up->uart_dma.rx_dma_used = false; | |
fcdca757 G |
108 | pm_runtime_mark_last_busy(&up->pdev->dev); |
109 | pm_runtime_put_autosuspend(&up->pdev->dev); | |
b612633b G |
110 | } |
111 | } | |
112 | ||
113 | static void serial_omap_enable_ms(struct uart_port *port) | |
114 | { | |
115 | struct uart_omap_port *up = (struct uart_omap_port *)port; | |
116 | ||
117 | dev_dbg(up->port.dev, "serial_omap_enable_ms+%d\n", up->pdev->id); | |
fcdca757 G |
118 | |
119 | pm_runtime_get_sync(&up->pdev->dev); | |
b612633b G |
120 | up->ier |= UART_IER_MSI; |
121 | serial_out(up, UART_IER, up->ier); | |
fcdca757 | 122 | pm_runtime_put(&up->pdev->dev); |
b612633b G |
123 | } |
124 | ||
125 | static void serial_omap_stop_tx(struct uart_port *port) | |
126 | { | |
127 | struct uart_omap_port *up = (struct uart_omap_port *)port; | |
128 | ||
129 | if (up->use_dma && | |
130 | up->uart_dma.tx_dma_channel != OMAP_UART_DMA_CH_FREE) { | |
131 | /* | |
132 | * Check if dma is still active. If yes do nothing, | |
133 | * return. Else stop dma | |
134 | */ | |
135 | if (omap_get_dma_active_status(up->uart_dma.tx_dma_channel)) | |
136 | return; | |
137 | omap_stop_dma(up->uart_dma.tx_dma_channel); | |
138 | omap_free_dma(up->uart_dma.tx_dma_channel); | |
139 | up->uart_dma.tx_dma_channel = OMAP_UART_DMA_CH_FREE; | |
fcdca757 G |
140 | pm_runtime_mark_last_busy(&up->pdev->dev); |
141 | pm_runtime_put_autosuspend(&up->pdev->dev); | |
b612633b G |
142 | } |
143 | ||
fcdca757 | 144 | pm_runtime_get_sync(&up->pdev->dev); |
b612633b G |
145 | if (up->ier & UART_IER_THRI) { |
146 | up->ier &= ~UART_IER_THRI; | |
147 | serial_out(up, UART_IER, up->ier); | |
148 | } | |
fcdca757 G |
149 | |
150 | pm_runtime_mark_last_busy(&up->pdev->dev); | |
151 | pm_runtime_put_autosuspend(&up->pdev->dev); | |
b612633b G |
152 | } |
153 | ||
154 | static void serial_omap_stop_rx(struct uart_port *port) | |
155 | { | |
156 | struct uart_omap_port *up = (struct uart_omap_port *)port; | |
157 | ||
fcdca757 | 158 | pm_runtime_get_sync(&up->pdev->dev); |
b612633b G |
159 | if (up->use_dma) |
160 | serial_omap_stop_rxdma(up); | |
161 | up->ier &= ~UART_IER_RLSI; | |
162 | up->port.read_status_mask &= ~UART_LSR_DR; | |
163 | serial_out(up, UART_IER, up->ier); | |
fcdca757 G |
164 | pm_runtime_mark_last_busy(&up->pdev->dev); |
165 | pm_runtime_put_autosuspend(&up->pdev->dev); | |
b612633b G |
166 | } |
167 | ||
168 | static inline void receive_chars(struct uart_omap_port *up, int *status) | |
169 | { | |
170 | struct tty_struct *tty = up->port.state->port.tty; | |
171 | unsigned int flag; | |
172 | unsigned char ch, lsr = *status; | |
173 | int max_count = 256; | |
174 | ||
175 | do { | |
176 | if (likely(lsr & UART_LSR_DR)) | |
177 | ch = serial_in(up, UART_RX); | |
178 | flag = TTY_NORMAL; | |
179 | up->port.icount.rx++; | |
180 | ||
181 | if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) { | |
182 | /* | |
183 | * For statistics only | |
184 | */ | |
185 | if (lsr & UART_LSR_BI) { | |
186 | lsr &= ~(UART_LSR_FE | UART_LSR_PE); | |
187 | up->port.icount.brk++; | |
188 | /* | |
189 | * We do the SysRQ and SAK checking | |
190 | * here because otherwise the break | |
191 | * may get masked by ignore_status_mask | |
192 | * or read_status_mask. | |
193 | */ | |
194 | if (uart_handle_break(&up->port)) | |
195 | goto ignore_char; | |
196 | } else if (lsr & UART_LSR_PE) { | |
197 | up->port.icount.parity++; | |
198 | } else if (lsr & UART_LSR_FE) { | |
199 | up->port.icount.frame++; | |
200 | } | |
201 | ||
202 | if (lsr & UART_LSR_OE) | |
203 | up->port.icount.overrun++; | |
204 | ||
205 | /* | |
206 | * Mask off conditions which should be ignored. | |
207 | */ | |
208 | lsr &= up->port.read_status_mask; | |
209 | ||
210 | #ifdef CONFIG_SERIAL_OMAP_CONSOLE | |
211 | if (up->port.line == up->port.cons->index) { | |
212 | /* Recover the break flag from console xmit */ | |
213 | lsr |= up->lsr_break_flag; | |
b612633b G |
214 | } |
215 | #endif | |
216 | if (lsr & UART_LSR_BI) | |
217 | flag = TTY_BREAK; | |
218 | else if (lsr & UART_LSR_PE) | |
219 | flag = TTY_PARITY; | |
220 | else if (lsr & UART_LSR_FE) | |
221 | flag = TTY_FRAME; | |
222 | } | |
223 | ||
224 | if (uart_handle_sysrq_char(&up->port, ch)) | |
225 | goto ignore_char; | |
226 | uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag); | |
227 | ignore_char: | |
228 | lsr = serial_in(up, UART_LSR); | |
229 | } while ((lsr & (UART_LSR_DR | UART_LSR_BI)) && (max_count-- > 0)); | |
230 | spin_unlock(&up->port.lock); | |
231 | tty_flip_buffer_push(tty); | |
232 | spin_lock(&up->port.lock); | |
233 | } | |
234 | ||
235 | static void transmit_chars(struct uart_omap_port *up) | |
236 | { | |
237 | struct circ_buf *xmit = &up->port.state->xmit; | |
238 | int count; | |
239 | ||
240 | if (up->port.x_char) { | |
241 | serial_out(up, UART_TX, up->port.x_char); | |
242 | up->port.icount.tx++; | |
243 | up->port.x_char = 0; | |
244 | return; | |
245 | } | |
246 | if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) { | |
247 | serial_omap_stop_tx(&up->port); | |
248 | return; | |
249 | } | |
250 | count = up->port.fifosize / 4; | |
251 | do { | |
252 | serial_out(up, UART_TX, xmit->buf[xmit->tail]); | |
253 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); | |
254 | up->port.icount.tx++; | |
255 | if (uart_circ_empty(xmit)) | |
256 | break; | |
257 | } while (--count > 0); | |
258 | ||
259 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
260 | uart_write_wakeup(&up->port); | |
261 | ||
262 | if (uart_circ_empty(xmit)) | |
263 | serial_omap_stop_tx(&up->port); | |
264 | } | |
265 | ||
266 | static inline void serial_omap_enable_ier_thri(struct uart_omap_port *up) | |
267 | { | |
268 | if (!(up->ier & UART_IER_THRI)) { | |
269 | up->ier |= UART_IER_THRI; | |
270 | serial_out(up, UART_IER, up->ier); | |
271 | } | |
272 | } | |
273 | ||
274 | static void serial_omap_start_tx(struct uart_port *port) | |
275 | { | |
276 | struct uart_omap_port *up = (struct uart_omap_port *)port; | |
277 | struct circ_buf *xmit; | |
278 | unsigned int start; | |
279 | int ret = 0; | |
280 | ||
281 | if (!up->use_dma) { | |
fcdca757 | 282 | pm_runtime_get_sync(&up->pdev->dev); |
b612633b | 283 | serial_omap_enable_ier_thri(up); |
fcdca757 G |
284 | pm_runtime_mark_last_busy(&up->pdev->dev); |
285 | pm_runtime_put_autosuspend(&up->pdev->dev); | |
b612633b G |
286 | return; |
287 | } | |
288 | ||
289 | if (up->uart_dma.tx_dma_used) | |
290 | return; | |
291 | ||
292 | xmit = &up->port.state->xmit; | |
293 | ||
294 | if (up->uart_dma.tx_dma_channel == OMAP_UART_DMA_CH_FREE) { | |
fcdca757 | 295 | pm_runtime_get_sync(&up->pdev->dev); |
b612633b G |
296 | ret = omap_request_dma(up->uart_dma.uart_dma_tx, |
297 | "UART Tx DMA", | |
298 | (void *)uart_tx_dma_callback, up, | |
299 | &(up->uart_dma.tx_dma_channel)); | |
300 | ||
301 | if (ret < 0) { | |
302 | serial_omap_enable_ier_thri(up); | |
303 | return; | |
304 | } | |
305 | } | |
306 | spin_lock(&(up->uart_dma.tx_lock)); | |
307 | up->uart_dma.tx_dma_used = true; | |
308 | spin_unlock(&(up->uart_dma.tx_lock)); | |
309 | ||
310 | start = up->uart_dma.tx_buf_dma_phys + | |
311 | (xmit->tail & (UART_XMIT_SIZE - 1)); | |
312 | ||
313 | up->uart_dma.tx_buf_size = uart_circ_chars_pending(xmit); | |
314 | /* | |
315 | * It is a circular buffer. See if the buffer has wounded back. | |
316 | * If yes it will have to be transferred in two separate dma | |
317 | * transfers | |
318 | */ | |
319 | if (start + up->uart_dma.tx_buf_size >= | |
320 | up->uart_dma.tx_buf_dma_phys + UART_XMIT_SIZE) | |
321 | up->uart_dma.tx_buf_size = | |
322 | (up->uart_dma.tx_buf_dma_phys + | |
323 | UART_XMIT_SIZE) - start; | |
324 | ||
325 | omap_set_dma_dest_params(up->uart_dma.tx_dma_channel, 0, | |
326 | OMAP_DMA_AMODE_CONSTANT, | |
327 | up->uart_dma.uart_base, 0, 0); | |
328 | omap_set_dma_src_params(up->uart_dma.tx_dma_channel, 0, | |
329 | OMAP_DMA_AMODE_POST_INC, start, 0, 0); | |
330 | omap_set_dma_transfer_params(up->uart_dma.tx_dma_channel, | |
331 | OMAP_DMA_DATA_TYPE_S8, | |
332 | up->uart_dma.tx_buf_size, 1, | |
333 | OMAP_DMA_SYNC_ELEMENT, | |
334 | up->uart_dma.uart_dma_tx, 0); | |
335 | /* FIXME: Cache maintenance needed here? */ | |
336 | omap_start_dma(up->uart_dma.tx_dma_channel); | |
337 | } | |
338 | ||
339 | static unsigned int check_modem_status(struct uart_omap_port *up) | |
340 | { | |
341 | unsigned int status; | |
342 | ||
343 | status = serial_in(up, UART_MSR); | |
344 | status |= up->msr_saved_flags; | |
345 | up->msr_saved_flags = 0; | |
346 | if ((status & UART_MSR_ANY_DELTA) == 0) | |
347 | return status; | |
348 | ||
349 | if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI && | |
350 | up->port.state != NULL) { | |
351 | if (status & UART_MSR_TERI) | |
352 | up->port.icount.rng++; | |
353 | if (status & UART_MSR_DDSR) | |
354 | up->port.icount.dsr++; | |
355 | if (status & UART_MSR_DDCD) | |
356 | uart_handle_dcd_change | |
357 | (&up->port, status & UART_MSR_DCD); | |
358 | if (status & UART_MSR_DCTS) | |
359 | uart_handle_cts_change | |
360 | (&up->port, status & UART_MSR_CTS); | |
361 | wake_up_interruptible(&up->port.state->port.delta_msr_wait); | |
362 | } | |
363 | ||
364 | return status; | |
365 | } | |
366 | ||
367 | /** | |
368 | * serial_omap_irq() - This handles the interrupt from one port | |
369 | * @irq: uart port irq number | |
370 | * @dev_id: uart port info | |
371 | */ | |
372 | static inline irqreturn_t serial_omap_irq(int irq, void *dev_id) | |
373 | { | |
374 | struct uart_omap_port *up = dev_id; | |
375 | unsigned int iir, lsr; | |
376 | unsigned long flags; | |
377 | ||
fcdca757 | 378 | pm_runtime_get_sync(&up->pdev->dev); |
b612633b | 379 | iir = serial_in(up, UART_IIR); |
fcdca757 G |
380 | if (iir & UART_IIR_NO_INT) { |
381 | pm_runtime_mark_last_busy(&up->pdev->dev); | |
382 | pm_runtime_put_autosuspend(&up->pdev->dev); | |
b612633b | 383 | return IRQ_NONE; |
fcdca757 | 384 | } |
b612633b G |
385 | |
386 | spin_lock_irqsave(&up->port.lock, flags); | |
387 | lsr = serial_in(up, UART_LSR); | |
388 | if (iir & UART_IIR_RLSI) { | |
389 | if (!up->use_dma) { | |
390 | if (lsr & UART_LSR_DR) | |
391 | receive_chars(up, &lsr); | |
392 | } else { | |
393 | up->ier &= ~(UART_IER_RDI | UART_IER_RLSI); | |
394 | serial_out(up, UART_IER, up->ier); | |
395 | if ((serial_omap_start_rxdma(up) != 0) && | |
396 | (lsr & UART_LSR_DR)) | |
397 | receive_chars(up, &lsr); | |
398 | } | |
399 | } | |
400 | ||
401 | check_modem_status(up); | |
402 | if ((lsr & UART_LSR_THRE) && (iir & UART_IIR_THRI)) | |
403 | transmit_chars(up); | |
404 | ||
405 | spin_unlock_irqrestore(&up->port.lock, flags); | |
fcdca757 G |
406 | pm_runtime_mark_last_busy(&up->pdev->dev); |
407 | pm_runtime_put_autosuspend(&up->pdev->dev); | |
408 | ||
b612633b G |
409 | up->port_activity = jiffies; |
410 | return IRQ_HANDLED; | |
411 | } | |
412 | ||
413 | static unsigned int serial_omap_tx_empty(struct uart_port *port) | |
414 | { | |
415 | struct uart_omap_port *up = (struct uart_omap_port *)port; | |
416 | unsigned long flags = 0; | |
417 | unsigned int ret = 0; | |
418 | ||
fcdca757 | 419 | pm_runtime_get_sync(&up->pdev->dev); |
b612633b G |
420 | dev_dbg(up->port.dev, "serial_omap_tx_empty+%d\n", up->pdev->id); |
421 | spin_lock_irqsave(&up->port.lock, flags); | |
422 | ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0; | |
423 | spin_unlock_irqrestore(&up->port.lock, flags); | |
fcdca757 | 424 | pm_runtime_put(&up->pdev->dev); |
b612633b G |
425 | return ret; |
426 | } | |
427 | ||
428 | static unsigned int serial_omap_get_mctrl(struct uart_port *port) | |
429 | { | |
430 | struct uart_omap_port *up = (struct uart_omap_port *)port; | |
431 | unsigned char status; | |
432 | unsigned int ret = 0; | |
433 | ||
fcdca757 | 434 | pm_runtime_get_sync(&up->pdev->dev); |
b612633b | 435 | status = check_modem_status(up); |
fcdca757 G |
436 | pm_runtime_put(&up->pdev->dev); |
437 | ||
b612633b G |
438 | dev_dbg(up->port.dev, "serial_omap_get_mctrl+%d\n", up->pdev->id); |
439 | ||
440 | if (status & UART_MSR_DCD) | |
441 | ret |= TIOCM_CAR; | |
442 | if (status & UART_MSR_RI) | |
443 | ret |= TIOCM_RNG; | |
444 | if (status & UART_MSR_DSR) | |
445 | ret |= TIOCM_DSR; | |
446 | if (status & UART_MSR_CTS) | |
447 | ret |= TIOCM_CTS; | |
448 | return ret; | |
449 | } | |
450 | ||
451 | static void serial_omap_set_mctrl(struct uart_port *port, unsigned int mctrl) | |
452 | { | |
453 | struct uart_omap_port *up = (struct uart_omap_port *)port; | |
454 | unsigned char mcr = 0; | |
455 | ||
456 | dev_dbg(up->port.dev, "serial_omap_set_mctrl+%d\n", up->pdev->id); | |
457 | if (mctrl & TIOCM_RTS) | |
458 | mcr |= UART_MCR_RTS; | |
459 | if (mctrl & TIOCM_DTR) | |
460 | mcr |= UART_MCR_DTR; | |
461 | if (mctrl & TIOCM_OUT1) | |
462 | mcr |= UART_MCR_OUT1; | |
463 | if (mctrl & TIOCM_OUT2) | |
464 | mcr |= UART_MCR_OUT2; | |
465 | if (mctrl & TIOCM_LOOP) | |
466 | mcr |= UART_MCR_LOOP; | |
467 | ||
fcdca757 | 468 | pm_runtime_get_sync(&up->pdev->dev); |
b612633b G |
469 | mcr |= up->mcr; |
470 | serial_out(up, UART_MCR, mcr); | |
fcdca757 | 471 | pm_runtime_put(&up->pdev->dev); |
b612633b G |
472 | } |
473 | ||
474 | static void serial_omap_break_ctl(struct uart_port *port, int break_state) | |
475 | { | |
476 | struct uart_omap_port *up = (struct uart_omap_port *)port; | |
477 | unsigned long flags = 0; | |
478 | ||
479 | dev_dbg(up->port.dev, "serial_omap_break_ctl+%d\n", up->pdev->id); | |
fcdca757 | 480 | pm_runtime_get_sync(&up->pdev->dev); |
b612633b G |
481 | spin_lock_irqsave(&up->port.lock, flags); |
482 | if (break_state == -1) | |
483 | up->lcr |= UART_LCR_SBC; | |
484 | else | |
485 | up->lcr &= ~UART_LCR_SBC; | |
486 | serial_out(up, UART_LCR, up->lcr); | |
487 | spin_unlock_irqrestore(&up->port.lock, flags); | |
fcdca757 | 488 | pm_runtime_put(&up->pdev->dev); |
b612633b G |
489 | } |
490 | ||
491 | static int serial_omap_startup(struct uart_port *port) | |
492 | { | |
493 | struct uart_omap_port *up = (struct uart_omap_port *)port; | |
494 | unsigned long flags = 0; | |
495 | int retval; | |
496 | ||
497 | /* | |
498 | * Allocate the IRQ | |
499 | */ | |
500 | retval = request_irq(up->port.irq, serial_omap_irq, up->port.irqflags, | |
501 | up->name, up); | |
502 | if (retval) | |
503 | return retval; | |
504 | ||
505 | dev_dbg(up->port.dev, "serial_omap_startup+%d\n", up->pdev->id); | |
506 | ||
fcdca757 | 507 | pm_runtime_get_sync(&up->pdev->dev); |
b612633b G |
508 | /* |
509 | * Clear the FIFO buffers and disable them. | |
510 | * (they will be reenabled in set_termios()) | |
511 | */ | |
512 | serial_omap_clear_fifos(up); | |
513 | /* For Hardware flow control */ | |
514 | serial_out(up, UART_MCR, UART_MCR_RTS); | |
515 | ||
516 | /* | |
517 | * Clear the interrupt registers. | |
518 | */ | |
519 | (void) serial_in(up, UART_LSR); | |
520 | if (serial_in(up, UART_LSR) & UART_LSR_DR) | |
521 | (void) serial_in(up, UART_RX); | |
522 | (void) serial_in(up, UART_IIR); | |
523 | (void) serial_in(up, UART_MSR); | |
524 | ||
525 | /* | |
526 | * Now, initialize the UART | |
527 | */ | |
528 | serial_out(up, UART_LCR, UART_LCR_WLEN8); | |
529 | spin_lock_irqsave(&up->port.lock, flags); | |
530 | /* | |
531 | * Most PC uarts need OUT2 raised to enable interrupts. | |
532 | */ | |
533 | up->port.mctrl |= TIOCM_OUT2; | |
534 | serial_omap_set_mctrl(&up->port, up->port.mctrl); | |
535 | spin_unlock_irqrestore(&up->port.lock, flags); | |
536 | ||
537 | up->msr_saved_flags = 0; | |
538 | if (up->use_dma) { | |
539 | free_page((unsigned long)up->port.state->xmit.buf); | |
540 | up->port.state->xmit.buf = dma_alloc_coherent(NULL, | |
541 | UART_XMIT_SIZE, | |
542 | (dma_addr_t *)&(up->uart_dma.tx_buf_dma_phys), | |
543 | 0); | |
544 | init_timer(&(up->uart_dma.rx_timer)); | |
545 | up->uart_dma.rx_timer.function = serial_omap_rx_timeout; | |
546 | up->uart_dma.rx_timer.data = up->pdev->id; | |
547 | /* Currently the buffer size is 4KB. Can increase it */ | |
548 | up->uart_dma.rx_buf = dma_alloc_coherent(NULL, | |
549 | up->uart_dma.rx_buf_size, | |
550 | (dma_addr_t *)&(up->uart_dma.rx_buf_dma_phys), 0); | |
551 | } | |
552 | /* | |
553 | * Finally, enable interrupts. Note: Modem status interrupts | |
554 | * are set via set_termios(), which will be occurring imminently | |
555 | * anyway, so we don't enable them here. | |
556 | */ | |
557 | up->ier = UART_IER_RLSI | UART_IER_RDI; | |
558 | serial_out(up, UART_IER, up->ier); | |
559 | ||
78841462 JN |
560 | /* Enable module level wake up */ |
561 | serial_out(up, UART_OMAP_WER, OMAP_UART_WER_MOD_WKUP); | |
562 | ||
fcdca757 G |
563 | pm_runtime_mark_last_busy(&up->pdev->dev); |
564 | pm_runtime_put_autosuspend(&up->pdev->dev); | |
b612633b G |
565 | up->port_activity = jiffies; |
566 | return 0; | |
567 | } | |
568 | ||
569 | static void serial_omap_shutdown(struct uart_port *port) | |
570 | { | |
571 | struct uart_omap_port *up = (struct uart_omap_port *)port; | |
572 | unsigned long flags = 0; | |
573 | ||
574 | dev_dbg(up->port.dev, "serial_omap_shutdown+%d\n", up->pdev->id); | |
fcdca757 G |
575 | |
576 | pm_runtime_get_sync(&up->pdev->dev); | |
b612633b G |
577 | /* |
578 | * Disable interrupts from this port | |
579 | */ | |
580 | up->ier = 0; | |
581 | serial_out(up, UART_IER, 0); | |
582 | ||
583 | spin_lock_irqsave(&up->port.lock, flags); | |
584 | up->port.mctrl &= ~TIOCM_OUT2; | |
585 | serial_omap_set_mctrl(&up->port, up->port.mctrl); | |
586 | spin_unlock_irqrestore(&up->port.lock, flags); | |
587 | ||
588 | /* | |
589 | * Disable break condition and FIFOs | |
590 | */ | |
591 | serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC); | |
592 | serial_omap_clear_fifos(up); | |
593 | ||
594 | /* | |
595 | * Read data port to reset things, and then free the irq | |
596 | */ | |
597 | if (serial_in(up, UART_LSR) & UART_LSR_DR) | |
598 | (void) serial_in(up, UART_RX); | |
599 | if (up->use_dma) { | |
600 | dma_free_coherent(up->port.dev, | |
601 | UART_XMIT_SIZE, up->port.state->xmit.buf, | |
602 | up->uart_dma.tx_buf_dma_phys); | |
603 | up->port.state->xmit.buf = NULL; | |
604 | serial_omap_stop_rx(port); | |
605 | dma_free_coherent(up->port.dev, | |
606 | up->uart_dma.rx_buf_size, up->uart_dma.rx_buf, | |
607 | up->uart_dma.rx_buf_dma_phys); | |
608 | up->uart_dma.rx_buf = NULL; | |
609 | } | |
fcdca757 G |
610 | |
611 | pm_runtime_put(&up->pdev->dev); | |
b612633b G |
612 | free_irq(up->port.irq, up); |
613 | } | |
614 | ||
615 | static inline void | |
616 | serial_omap_configure_xonxoff | |
617 | (struct uart_omap_port *up, struct ktermios *termios) | |
618 | { | |
619 | unsigned char efr = 0; | |
620 | ||
621 | up->lcr = serial_in(up, UART_LCR); | |
662b083a | 622 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); |
b612633b G |
623 | up->efr = serial_in(up, UART_EFR); |
624 | serial_out(up, UART_EFR, up->efr & ~UART_EFR_ECB); | |
625 | ||
626 | serial_out(up, UART_XON1, termios->c_cc[VSTART]); | |
627 | serial_out(up, UART_XOFF1, termios->c_cc[VSTOP]); | |
628 | ||
629 | /* clear SW control mode bits */ | |
630 | efr = up->efr; | |
631 | efr &= OMAP_UART_SW_CLR; | |
632 | ||
633 | /* | |
634 | * IXON Flag: | |
635 | * Enable XON/XOFF flow control on output. | |
636 | * Transmit XON1, XOFF1 | |
637 | */ | |
638 | if (termios->c_iflag & IXON) | |
639 | efr |= OMAP_UART_SW_TX; | |
640 | ||
641 | /* | |
642 | * IXOFF Flag: | |
643 | * Enable XON/XOFF flow control on input. | |
644 | * Receiver compares XON1, XOFF1. | |
645 | */ | |
646 | if (termios->c_iflag & IXOFF) | |
647 | efr |= OMAP_UART_SW_RX; | |
648 | ||
649 | serial_out(up, UART_EFR, up->efr | UART_EFR_ECB); | |
662b083a | 650 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); |
b612633b G |
651 | |
652 | up->mcr = serial_in(up, UART_MCR); | |
653 | ||
654 | /* | |
655 | * IXANY Flag: | |
656 | * Enable any character to restart output. | |
657 | * Operation resumes after receiving any | |
658 | * character after recognition of the XOFF character | |
659 | */ | |
660 | if (termios->c_iflag & IXANY) | |
661 | up->mcr |= UART_MCR_XONANY; | |
662 | ||
663 | serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR); | |
662b083a | 664 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); |
b612633b G |
665 | serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG); |
666 | /* Enable special char function UARTi.EFR_REG[5] and | |
667 | * load the new software flow control mode IXON or IXOFF | |
668 | * and restore the UARTi.EFR_REG[4] ENHANCED_EN value. | |
669 | */ | |
670 | serial_out(up, UART_EFR, efr | UART_EFR_SCD); | |
662b083a | 671 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); |
b612633b G |
672 | |
673 | serial_out(up, UART_MCR, up->mcr & ~UART_MCR_TCRTLR); | |
674 | serial_out(up, UART_LCR, up->lcr); | |
675 | } | |
676 | ||
677 | static void | |
678 | serial_omap_set_termios(struct uart_port *port, struct ktermios *termios, | |
679 | struct ktermios *old) | |
680 | { | |
681 | struct uart_omap_port *up = (struct uart_omap_port *)port; | |
682 | unsigned char cval = 0; | |
683 | unsigned char efr = 0; | |
684 | unsigned long flags = 0; | |
685 | unsigned int baud, quot; | |
686 | ||
687 | switch (termios->c_cflag & CSIZE) { | |
688 | case CS5: | |
689 | cval = UART_LCR_WLEN5; | |
690 | break; | |
691 | case CS6: | |
692 | cval = UART_LCR_WLEN6; | |
693 | break; | |
694 | case CS7: | |
695 | cval = UART_LCR_WLEN7; | |
696 | break; | |
697 | default: | |
698 | case CS8: | |
699 | cval = UART_LCR_WLEN8; | |
700 | break; | |
701 | } | |
702 | ||
703 | if (termios->c_cflag & CSTOPB) | |
704 | cval |= UART_LCR_STOP; | |
705 | if (termios->c_cflag & PARENB) | |
706 | cval |= UART_LCR_PARITY; | |
707 | if (!(termios->c_cflag & PARODD)) | |
708 | cval |= UART_LCR_EPAR; | |
709 | ||
710 | /* | |
711 | * Ask the core to calculate the divisor for us. | |
712 | */ | |
713 | ||
714 | baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/13); | |
715 | quot = serial_omap_get_divisor(port, baud); | |
716 | ||
717 | up->fcr = UART_FCR_R_TRIG_01 | UART_FCR_T_TRIG_01 | | |
718 | UART_FCR_ENABLE_FIFO; | |
719 | if (up->use_dma) | |
720 | up->fcr |= UART_FCR_DMA_SELECT; | |
721 | ||
722 | /* | |
723 | * Ok, we're now changing the port state. Do it with | |
724 | * interrupts disabled. | |
725 | */ | |
fcdca757 | 726 | pm_runtime_get_sync(&up->pdev->dev); |
b612633b G |
727 | spin_lock_irqsave(&up->port.lock, flags); |
728 | ||
729 | /* | |
730 | * Update the per-port timeout. | |
731 | */ | |
732 | uart_update_timeout(port, termios->c_cflag, baud); | |
733 | ||
734 | up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR; | |
735 | if (termios->c_iflag & INPCK) | |
736 | up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE; | |
737 | if (termios->c_iflag & (BRKINT | PARMRK)) | |
738 | up->port.read_status_mask |= UART_LSR_BI; | |
739 | ||
740 | /* | |
741 | * Characters to ignore | |
742 | */ | |
743 | up->port.ignore_status_mask = 0; | |
744 | if (termios->c_iflag & IGNPAR) | |
745 | up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE; | |
746 | if (termios->c_iflag & IGNBRK) { | |
747 | up->port.ignore_status_mask |= UART_LSR_BI; | |
748 | /* | |
749 | * If we're ignoring parity and break indicators, | |
750 | * ignore overruns too (for real raw support). | |
751 | */ | |
752 | if (termios->c_iflag & IGNPAR) | |
753 | up->port.ignore_status_mask |= UART_LSR_OE; | |
754 | } | |
755 | ||
756 | /* | |
757 | * ignore all characters if CREAD is not set | |
758 | */ | |
759 | if ((termios->c_cflag & CREAD) == 0) | |
760 | up->port.ignore_status_mask |= UART_LSR_DR; | |
761 | ||
762 | /* | |
763 | * Modem status interrupts | |
764 | */ | |
765 | up->ier &= ~UART_IER_MSI; | |
766 | if (UART_ENABLE_MS(&up->port, termios->c_cflag)) | |
767 | up->ier |= UART_IER_MSI; | |
768 | serial_out(up, UART_IER, up->ier); | |
769 | serial_out(up, UART_LCR, cval); /* reset DLAB */ | |
770 | ||
771 | /* FIFOs and DMA Settings */ | |
772 | ||
773 | /* FCR can be changed only when the | |
774 | * baud clock is not running | |
775 | * DLL_REG and DLH_REG set to 0. | |
776 | */ | |
662b083a | 777 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); |
b612633b G |
778 | serial_out(up, UART_DLL, 0); |
779 | serial_out(up, UART_DLM, 0); | |
780 | serial_out(up, UART_LCR, 0); | |
781 | ||
662b083a | 782 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); |
b612633b G |
783 | |
784 | up->efr = serial_in(up, UART_EFR); | |
785 | serial_out(up, UART_EFR, up->efr | UART_EFR_ECB); | |
786 | ||
662b083a | 787 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); |
b612633b G |
788 | up->mcr = serial_in(up, UART_MCR); |
789 | serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR); | |
790 | /* FIFO ENABLE, DMA MODE */ | |
791 | serial_out(up, UART_FCR, up->fcr); | |
662b083a | 792 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); |
b612633b G |
793 | |
794 | if (up->use_dma) { | |
795 | serial_out(up, UART_TI752_TLR, 0); | |
796 | serial_out(up, UART_OMAP_SCR, | |
797 | (UART_FCR_TRIGGER_4 | UART_FCR_TRIGGER_8)); | |
798 | } | |
799 | ||
800 | serial_out(up, UART_EFR, up->efr); | |
662b083a | 801 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); |
b612633b G |
802 | serial_out(up, UART_MCR, up->mcr); |
803 | ||
804 | /* Protocol, Baud Rate, and Interrupt Settings */ | |
805 | ||
498cb951 | 806 | serial_out(up, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE); |
662b083a | 807 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); |
b612633b G |
808 | |
809 | up->efr = serial_in(up, UART_EFR); | |
810 | serial_out(up, UART_EFR, up->efr | UART_EFR_ECB); | |
811 | ||
812 | serial_out(up, UART_LCR, 0); | |
813 | serial_out(up, UART_IER, 0); | |
662b083a | 814 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); |
b612633b G |
815 | |
816 | serial_out(up, UART_DLL, quot & 0xff); /* LS of divisor */ | |
817 | serial_out(up, UART_DLM, quot >> 8); /* MS of divisor */ | |
818 | ||
819 | serial_out(up, UART_LCR, 0); | |
820 | serial_out(up, UART_IER, up->ier); | |
662b083a | 821 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); |
b612633b G |
822 | |
823 | serial_out(up, UART_EFR, up->efr); | |
824 | serial_out(up, UART_LCR, cval); | |
825 | ||
826 | if (baud > 230400 && baud != 3000000) | |
498cb951 | 827 | serial_out(up, UART_OMAP_MDR1, UART_OMAP_MDR1_13X_MODE); |
b612633b | 828 | else |
498cb951 | 829 | serial_out(up, UART_OMAP_MDR1, UART_OMAP_MDR1_16X_MODE); |
b612633b G |
830 | |
831 | /* Hardware Flow Control Configuration */ | |
832 | ||
833 | if (termios->c_cflag & CRTSCTS) { | |
834 | efr |= (UART_EFR_CTS | UART_EFR_RTS); | |
662b083a | 835 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); |
b612633b G |
836 | |
837 | up->mcr = serial_in(up, UART_MCR); | |
838 | serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR); | |
839 | ||
662b083a | 840 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); |
b612633b G |
841 | up->efr = serial_in(up, UART_EFR); |
842 | serial_out(up, UART_EFR, up->efr | UART_EFR_ECB); | |
843 | ||
844 | serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG); | |
845 | serial_out(up, UART_EFR, efr); /* Enable AUTORTS and AUTOCTS */ | |
662b083a | 846 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); |
b612633b G |
847 | serial_out(up, UART_MCR, up->mcr | UART_MCR_RTS); |
848 | serial_out(up, UART_LCR, cval); | |
849 | } | |
850 | ||
851 | serial_omap_set_mctrl(&up->port, up->port.mctrl); | |
852 | /* Software Flow Control Configuration */ | |
b280a97d | 853 | serial_omap_configure_xonxoff(up, termios); |
b612633b G |
854 | |
855 | spin_unlock_irqrestore(&up->port.lock, flags); | |
fcdca757 | 856 | pm_runtime_put(&up->pdev->dev); |
b612633b G |
857 | dev_dbg(up->port.dev, "serial_omap_set_termios+%d\n", up->pdev->id); |
858 | } | |
859 | ||
860 | static void | |
861 | serial_omap_pm(struct uart_port *port, unsigned int state, | |
862 | unsigned int oldstate) | |
863 | { | |
864 | struct uart_omap_port *up = (struct uart_omap_port *)port; | |
865 | unsigned char efr; | |
866 | ||
867 | dev_dbg(up->port.dev, "serial_omap_pm+%d\n", up->pdev->id); | |
fcdca757 G |
868 | |
869 | pm_runtime_get_sync(&up->pdev->dev); | |
662b083a | 870 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); |
b612633b G |
871 | efr = serial_in(up, UART_EFR); |
872 | serial_out(up, UART_EFR, efr | UART_EFR_ECB); | |
873 | serial_out(up, UART_LCR, 0); | |
874 | ||
875 | serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0); | |
662b083a | 876 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); |
b612633b G |
877 | serial_out(up, UART_EFR, efr); |
878 | serial_out(up, UART_LCR, 0); | |
fcdca757 G |
879 | |
880 | if (!device_may_wakeup(&up->pdev->dev)) { | |
881 | if (!state) | |
882 | pm_runtime_forbid(&up->pdev->dev); | |
883 | else | |
884 | pm_runtime_allow(&up->pdev->dev); | |
885 | } | |
886 | ||
887 | pm_runtime_put(&up->pdev->dev); | |
b612633b G |
888 | } |
889 | ||
890 | static void serial_omap_release_port(struct uart_port *port) | |
891 | { | |
892 | dev_dbg(port->dev, "serial_omap_release_port+\n"); | |
893 | } | |
894 | ||
895 | static int serial_omap_request_port(struct uart_port *port) | |
896 | { | |
897 | dev_dbg(port->dev, "serial_omap_request_port+\n"); | |
898 | return 0; | |
899 | } | |
900 | ||
901 | static void serial_omap_config_port(struct uart_port *port, int flags) | |
902 | { | |
903 | struct uart_omap_port *up = (struct uart_omap_port *)port; | |
904 | ||
905 | dev_dbg(up->port.dev, "serial_omap_config_port+%d\n", | |
906 | up->pdev->id); | |
907 | up->port.type = PORT_OMAP; | |
908 | } | |
909 | ||
910 | static int | |
911 | serial_omap_verify_port(struct uart_port *port, struct serial_struct *ser) | |
912 | { | |
913 | /* we don't want the core code to modify any port params */ | |
914 | dev_dbg(port->dev, "serial_omap_verify_port+\n"); | |
915 | return -EINVAL; | |
916 | } | |
917 | ||
918 | static const char * | |
919 | serial_omap_type(struct uart_port *port) | |
920 | { | |
921 | struct uart_omap_port *up = (struct uart_omap_port *)port; | |
922 | ||
923 | dev_dbg(up->port.dev, "serial_omap_type+%d\n", up->pdev->id); | |
924 | return up->name; | |
925 | } | |
926 | ||
b612633b G |
927 | #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE) |
928 | ||
929 | static inline void wait_for_xmitr(struct uart_omap_port *up) | |
930 | { | |
931 | unsigned int status, tmout = 10000; | |
932 | ||
933 | /* Wait up to 10ms for the character(s) to be sent. */ | |
934 | do { | |
935 | status = serial_in(up, UART_LSR); | |
936 | ||
937 | if (status & UART_LSR_BI) | |
938 | up->lsr_break_flag = UART_LSR_BI; | |
939 | ||
940 | if (--tmout == 0) | |
941 | break; | |
942 | udelay(1); | |
943 | } while ((status & BOTH_EMPTY) != BOTH_EMPTY); | |
944 | ||
945 | /* Wait up to 1s for flow control if necessary */ | |
946 | if (up->port.flags & UPF_CONS_FLOW) { | |
947 | tmout = 1000000; | |
948 | for (tmout = 1000000; tmout; tmout--) { | |
949 | unsigned int msr = serial_in(up, UART_MSR); | |
950 | ||
951 | up->msr_saved_flags |= msr & MSR_SAVE_FLAGS; | |
952 | if (msr & UART_MSR_CTS) | |
953 | break; | |
954 | ||
955 | udelay(1); | |
956 | } | |
957 | } | |
958 | } | |
959 | ||
1b41dbc1 CC |
960 | #ifdef CONFIG_CONSOLE_POLL |
961 | ||
962 | static void serial_omap_poll_put_char(struct uart_port *port, unsigned char ch) | |
963 | { | |
964 | struct uart_omap_port *up = (struct uart_omap_port *)port; | |
fcdca757 G |
965 | |
966 | pm_runtime_get_sync(&up->pdev->dev); | |
1b41dbc1 CC |
967 | wait_for_xmitr(up); |
968 | serial_out(up, UART_TX, ch); | |
fcdca757 | 969 | pm_runtime_put(&up->pdev->dev); |
1b41dbc1 CC |
970 | } |
971 | ||
972 | static int serial_omap_poll_get_char(struct uart_port *port) | |
973 | { | |
974 | struct uart_omap_port *up = (struct uart_omap_port *)port; | |
fcdca757 | 975 | unsigned int status; |
1b41dbc1 | 976 | |
fcdca757 G |
977 | pm_runtime_get_sync(&up->pdev->dev); |
978 | status = serial_in(up, UART_LSR); | |
1b41dbc1 CC |
979 | if (!(status & UART_LSR_DR)) |
980 | return NO_POLL_CHAR; | |
981 | ||
fcdca757 G |
982 | status = serial_in(up, UART_RX); |
983 | pm_runtime_put(&up->pdev->dev); | |
984 | return status; | |
1b41dbc1 CC |
985 | } |
986 | ||
987 | #endif /* CONFIG_CONSOLE_POLL */ | |
988 | ||
989 | #ifdef CONFIG_SERIAL_OMAP_CONSOLE | |
990 | ||
991 | static struct uart_omap_port *serial_omap_console_ports[4]; | |
992 | ||
993 | static struct uart_driver serial_omap_reg; | |
994 | ||
b612633b G |
995 | static void serial_omap_console_putchar(struct uart_port *port, int ch) |
996 | { | |
997 | struct uart_omap_port *up = (struct uart_omap_port *)port; | |
998 | ||
999 | wait_for_xmitr(up); | |
1000 | serial_out(up, UART_TX, ch); | |
1001 | } | |
1002 | ||
1003 | static void | |
1004 | serial_omap_console_write(struct console *co, const char *s, | |
1005 | unsigned int count) | |
1006 | { | |
1007 | struct uart_omap_port *up = serial_omap_console_ports[co->index]; | |
1008 | unsigned long flags; | |
1009 | unsigned int ier; | |
1010 | int locked = 1; | |
1011 | ||
fcdca757 G |
1012 | pm_runtime_get_sync(&up->pdev->dev); |
1013 | ||
b612633b G |
1014 | local_irq_save(flags); |
1015 | if (up->port.sysrq) | |
1016 | locked = 0; | |
1017 | else if (oops_in_progress) | |
1018 | locked = spin_trylock(&up->port.lock); | |
1019 | else | |
1020 | spin_lock(&up->port.lock); | |
1021 | ||
1022 | /* | |
1023 | * First save the IER then disable the interrupts | |
1024 | */ | |
1025 | ier = serial_in(up, UART_IER); | |
1026 | serial_out(up, UART_IER, 0); | |
1027 | ||
1028 | uart_console_write(&up->port, s, count, serial_omap_console_putchar); | |
1029 | ||
1030 | /* | |
1031 | * Finally, wait for transmitter to become empty | |
1032 | * and restore the IER | |
1033 | */ | |
1034 | wait_for_xmitr(up); | |
1035 | serial_out(up, UART_IER, ier); | |
1036 | /* | |
1037 | * The receive handling will happen properly because the | |
1038 | * receive ready bit will still be set; it is not cleared | |
1039 | * on read. However, modem control will not, we must | |
1040 | * call it if we have saved something in the saved flags | |
1041 | * while processing with interrupts off. | |
1042 | */ | |
1043 | if (up->msr_saved_flags) | |
1044 | check_modem_status(up); | |
1045 | ||
fcdca757 G |
1046 | pm_runtime_mark_last_busy(&up->pdev->dev); |
1047 | pm_runtime_put_autosuspend(&up->pdev->dev); | |
b612633b G |
1048 | if (locked) |
1049 | spin_unlock(&up->port.lock); | |
1050 | local_irq_restore(flags); | |
1051 | } | |
1052 | ||
1053 | static int __init | |
1054 | serial_omap_console_setup(struct console *co, char *options) | |
1055 | { | |
1056 | struct uart_omap_port *up; | |
1057 | int baud = 115200; | |
1058 | int bits = 8; | |
1059 | int parity = 'n'; | |
1060 | int flow = 'n'; | |
1061 | ||
1062 | if (serial_omap_console_ports[co->index] == NULL) | |
1063 | return -ENODEV; | |
1064 | up = serial_omap_console_ports[co->index]; | |
1065 | ||
1066 | if (options) | |
1067 | uart_parse_options(options, &baud, &parity, &bits, &flow); | |
1068 | ||
1069 | return uart_set_options(&up->port, co, baud, parity, bits, flow); | |
1070 | } | |
1071 | ||
1072 | static struct console serial_omap_console = { | |
1073 | .name = OMAP_SERIAL_NAME, | |
1074 | .write = serial_omap_console_write, | |
1075 | .device = uart_console_device, | |
1076 | .setup = serial_omap_console_setup, | |
1077 | .flags = CON_PRINTBUFFER, | |
1078 | .index = -1, | |
1079 | .data = &serial_omap_reg, | |
1080 | }; | |
1081 | ||
1082 | static void serial_omap_add_console_port(struct uart_omap_port *up) | |
1083 | { | |
1084 | serial_omap_console_ports[up->pdev->id] = up; | |
1085 | } | |
1086 | ||
1087 | #define OMAP_CONSOLE (&serial_omap_console) | |
1088 | ||
1089 | #else | |
1090 | ||
1091 | #define OMAP_CONSOLE NULL | |
1092 | ||
1093 | static inline void serial_omap_add_console_port(struct uart_omap_port *up) | |
1094 | {} | |
1095 | ||
1096 | #endif | |
1097 | ||
1098 | static struct uart_ops serial_omap_pops = { | |
1099 | .tx_empty = serial_omap_tx_empty, | |
1100 | .set_mctrl = serial_omap_set_mctrl, | |
1101 | .get_mctrl = serial_omap_get_mctrl, | |
1102 | .stop_tx = serial_omap_stop_tx, | |
1103 | .start_tx = serial_omap_start_tx, | |
1104 | .stop_rx = serial_omap_stop_rx, | |
1105 | .enable_ms = serial_omap_enable_ms, | |
1106 | .break_ctl = serial_omap_break_ctl, | |
1107 | .startup = serial_omap_startup, | |
1108 | .shutdown = serial_omap_shutdown, | |
1109 | .set_termios = serial_omap_set_termios, | |
1110 | .pm = serial_omap_pm, | |
1111 | .type = serial_omap_type, | |
1112 | .release_port = serial_omap_release_port, | |
1113 | .request_port = serial_omap_request_port, | |
1114 | .config_port = serial_omap_config_port, | |
1115 | .verify_port = serial_omap_verify_port, | |
1b41dbc1 CC |
1116 | #ifdef CONFIG_CONSOLE_POLL |
1117 | .poll_put_char = serial_omap_poll_put_char, | |
1118 | .poll_get_char = serial_omap_poll_get_char, | |
1119 | #endif | |
b612633b G |
1120 | }; |
1121 | ||
1122 | static struct uart_driver serial_omap_reg = { | |
1123 | .owner = THIS_MODULE, | |
1124 | .driver_name = "OMAP-SERIAL", | |
1125 | .dev_name = OMAP_SERIAL_NAME, | |
1126 | .nr = OMAP_MAX_HSUART_PORTS, | |
1127 | .cons = OMAP_CONSOLE, | |
1128 | }; | |
1129 | ||
fcdca757 G |
1130 | #ifdef CONFIG_SUSPEND |
1131 | static int serial_omap_suspend(struct device *dev) | |
b612633b | 1132 | { |
fcdca757 | 1133 | struct uart_omap_port *up = dev_get_drvdata(dev); |
b612633b G |
1134 | |
1135 | if (up) | |
1136 | uart_suspend_port(&serial_omap_reg, &up->port); | |
1137 | return 0; | |
1138 | } | |
1139 | ||
fcdca757 | 1140 | static int serial_omap_resume(struct device *dev) |
b612633b | 1141 | { |
fcdca757 | 1142 | struct uart_omap_port *up = dev_get_drvdata(dev); |
b612633b G |
1143 | |
1144 | if (up) | |
1145 | uart_resume_port(&serial_omap_reg, &up->port); | |
1146 | return 0; | |
1147 | } | |
fcdca757 | 1148 | #endif |
b612633b G |
1149 | |
1150 | static void serial_omap_rx_timeout(unsigned long uart_no) | |
1151 | { | |
1152 | struct uart_omap_port *up = ui[uart_no]; | |
1153 | unsigned int curr_dma_pos, curr_transmitted_size; | |
79fc3e21 | 1154 | int ret = 0; |
b612633b G |
1155 | |
1156 | curr_dma_pos = omap_get_dma_dst_pos(up->uart_dma.rx_dma_channel); | |
1157 | if ((curr_dma_pos == up->uart_dma.prev_rx_dma_pos) || | |
1158 | (curr_dma_pos == 0)) { | |
1159 | if (jiffies_to_msecs(jiffies - up->port_activity) < | |
1160 | RX_TIMEOUT) { | |
1161 | mod_timer(&up->uart_dma.rx_timer, jiffies + | |
1162 | usecs_to_jiffies(up->uart_dma.rx_timeout)); | |
1163 | } else { | |
1164 | serial_omap_stop_rxdma(up); | |
1165 | up->ier |= (UART_IER_RDI | UART_IER_RLSI); | |
1166 | serial_out(up, UART_IER, up->ier); | |
1167 | } | |
1168 | return; | |
1169 | } | |
1170 | ||
1171 | curr_transmitted_size = curr_dma_pos - | |
1172 | up->uart_dma.prev_rx_dma_pos; | |
1173 | up->port.icount.rx += curr_transmitted_size; | |
1174 | tty_insert_flip_string(up->port.state->port.tty, | |
1175 | up->uart_dma.rx_buf + | |
1176 | (up->uart_dma.prev_rx_dma_pos - | |
1177 | up->uart_dma.rx_buf_dma_phys), | |
1178 | curr_transmitted_size); | |
1179 | tty_flip_buffer_push(up->port.state->port.tty); | |
1180 | up->uart_dma.prev_rx_dma_pos = curr_dma_pos; | |
1181 | if (up->uart_dma.rx_buf_size + | |
1182 | up->uart_dma.rx_buf_dma_phys == curr_dma_pos) { | |
1183 | ret = serial_omap_start_rxdma(up); | |
1184 | if (ret < 0) { | |
1185 | serial_omap_stop_rxdma(up); | |
1186 | up->ier |= (UART_IER_RDI | UART_IER_RLSI); | |
1187 | serial_out(up, UART_IER, up->ier); | |
1188 | } | |
1189 | } else { | |
1190 | mod_timer(&up->uart_dma.rx_timer, jiffies + | |
1191 | usecs_to_jiffies(up->uart_dma.rx_timeout)); | |
1192 | } | |
1193 | up->port_activity = jiffies; | |
1194 | } | |
1195 | ||
1196 | static void uart_rx_dma_callback(int lch, u16 ch_status, void *data) | |
1197 | { | |
1198 | return; | |
1199 | } | |
1200 | ||
1201 | static int serial_omap_start_rxdma(struct uart_omap_port *up) | |
1202 | { | |
1203 | int ret = 0; | |
1204 | ||
1205 | if (up->uart_dma.rx_dma_channel == -1) { | |
fcdca757 | 1206 | pm_runtime_get_sync(&up->pdev->dev); |
b612633b G |
1207 | ret = omap_request_dma(up->uart_dma.uart_dma_rx, |
1208 | "UART Rx DMA", | |
1209 | (void *)uart_rx_dma_callback, up, | |
1210 | &(up->uart_dma.rx_dma_channel)); | |
1211 | if (ret < 0) | |
1212 | return ret; | |
1213 | ||
1214 | omap_set_dma_src_params(up->uart_dma.rx_dma_channel, 0, | |
1215 | OMAP_DMA_AMODE_CONSTANT, | |
1216 | up->uart_dma.uart_base, 0, 0); | |
1217 | omap_set_dma_dest_params(up->uart_dma.rx_dma_channel, 0, | |
1218 | OMAP_DMA_AMODE_POST_INC, | |
1219 | up->uart_dma.rx_buf_dma_phys, 0, 0); | |
1220 | omap_set_dma_transfer_params(up->uart_dma.rx_dma_channel, | |
1221 | OMAP_DMA_DATA_TYPE_S8, | |
1222 | up->uart_dma.rx_buf_size, 1, | |
1223 | OMAP_DMA_SYNC_ELEMENT, | |
1224 | up->uart_dma.uart_dma_rx, 0); | |
1225 | } | |
1226 | up->uart_dma.prev_rx_dma_pos = up->uart_dma.rx_buf_dma_phys; | |
1227 | /* FIXME: Cache maintenance needed here? */ | |
1228 | omap_start_dma(up->uart_dma.rx_dma_channel); | |
1229 | mod_timer(&up->uart_dma.rx_timer, jiffies + | |
1230 | usecs_to_jiffies(up->uart_dma.rx_timeout)); | |
1231 | up->uart_dma.rx_dma_used = true; | |
1232 | return ret; | |
1233 | } | |
1234 | ||
1235 | static void serial_omap_continue_tx(struct uart_omap_port *up) | |
1236 | { | |
1237 | struct circ_buf *xmit = &up->port.state->xmit; | |
1238 | unsigned int start = up->uart_dma.tx_buf_dma_phys | |
1239 | + (xmit->tail & (UART_XMIT_SIZE - 1)); | |
1240 | ||
1241 | if (uart_circ_empty(xmit)) | |
1242 | return; | |
1243 | ||
1244 | up->uart_dma.tx_buf_size = uart_circ_chars_pending(xmit); | |
1245 | /* | |
1246 | * It is a circular buffer. See if the buffer has wounded back. | |
1247 | * If yes it will have to be transferred in two separate dma | |
1248 | * transfers | |
1249 | */ | |
1250 | if (start + up->uart_dma.tx_buf_size >= | |
1251 | up->uart_dma.tx_buf_dma_phys + UART_XMIT_SIZE) | |
1252 | up->uart_dma.tx_buf_size = | |
1253 | (up->uart_dma.tx_buf_dma_phys + UART_XMIT_SIZE) - start; | |
1254 | omap_set_dma_dest_params(up->uart_dma.tx_dma_channel, 0, | |
1255 | OMAP_DMA_AMODE_CONSTANT, | |
1256 | up->uart_dma.uart_base, 0, 0); | |
1257 | omap_set_dma_src_params(up->uart_dma.tx_dma_channel, 0, | |
1258 | OMAP_DMA_AMODE_POST_INC, start, 0, 0); | |
1259 | omap_set_dma_transfer_params(up->uart_dma.tx_dma_channel, | |
1260 | OMAP_DMA_DATA_TYPE_S8, | |
1261 | up->uart_dma.tx_buf_size, 1, | |
1262 | OMAP_DMA_SYNC_ELEMENT, | |
1263 | up->uart_dma.uart_dma_tx, 0); | |
1264 | /* FIXME: Cache maintenance needed here? */ | |
1265 | omap_start_dma(up->uart_dma.tx_dma_channel); | |
1266 | } | |
1267 | ||
1268 | static void uart_tx_dma_callback(int lch, u16 ch_status, void *data) | |
1269 | { | |
1270 | struct uart_omap_port *up = (struct uart_omap_port *)data; | |
1271 | struct circ_buf *xmit = &up->port.state->xmit; | |
1272 | ||
1273 | xmit->tail = (xmit->tail + up->uart_dma.tx_buf_size) & \ | |
1274 | (UART_XMIT_SIZE - 1); | |
1275 | up->port.icount.tx += up->uart_dma.tx_buf_size; | |
1276 | ||
1277 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
1278 | uart_write_wakeup(&up->port); | |
1279 | ||
1280 | if (uart_circ_empty(xmit)) { | |
1281 | spin_lock(&(up->uart_dma.tx_lock)); | |
1282 | serial_omap_stop_tx(&up->port); | |
1283 | up->uart_dma.tx_dma_used = false; | |
1284 | spin_unlock(&(up->uart_dma.tx_lock)); | |
1285 | } else { | |
1286 | omap_stop_dma(up->uart_dma.tx_dma_channel); | |
1287 | serial_omap_continue_tx(up); | |
1288 | } | |
1289 | up->port_activity = jiffies; | |
1290 | return; | |
1291 | } | |
1292 | ||
1293 | static int serial_omap_probe(struct platform_device *pdev) | |
1294 | { | |
1295 | struct uart_omap_port *up; | |
1296 | struct resource *mem, *irq, *dma_tx, *dma_rx; | |
1297 | struct omap_uart_port_info *omap_up_info = pdev->dev.platform_data; | |
1298 | int ret = -ENOSPC; | |
1299 | ||
1300 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1301 | if (!mem) { | |
1302 | dev_err(&pdev->dev, "no mem resource?\n"); | |
1303 | return -ENODEV; | |
1304 | } | |
1305 | ||
1306 | irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); | |
1307 | if (!irq) { | |
1308 | dev_err(&pdev->dev, "no irq resource?\n"); | |
1309 | return -ENODEV; | |
1310 | } | |
1311 | ||
28f65c11 JP |
1312 | if (!request_mem_region(mem->start, resource_size(mem), |
1313 | pdev->dev.driver->name)) { | |
b612633b G |
1314 | dev_err(&pdev->dev, "memory region already claimed\n"); |
1315 | return -EBUSY; | |
1316 | } | |
1317 | ||
1318 | dma_rx = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx"); | |
1319 | if (!dma_rx) { | |
1320 | ret = -EINVAL; | |
1321 | goto err; | |
1322 | } | |
1323 | ||
1324 | dma_tx = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx"); | |
1325 | if (!dma_tx) { | |
1326 | ret = -EINVAL; | |
1327 | goto err; | |
1328 | } | |
1329 | ||
1330 | up = kzalloc(sizeof(*up), GFP_KERNEL); | |
1331 | if (up == NULL) { | |
1332 | ret = -ENOMEM; | |
1333 | goto do_release_region; | |
1334 | } | |
1335 | sprintf(up->name, "OMAP UART%d", pdev->id); | |
1336 | up->pdev = pdev; | |
1337 | up->port.dev = &pdev->dev; | |
1338 | up->port.type = PORT_OMAP; | |
1339 | up->port.iotype = UPIO_MEM; | |
1340 | up->port.irq = irq->start; | |
1341 | ||
1342 | up->port.regshift = 2; | |
1343 | up->port.fifosize = 64; | |
1344 | up->port.ops = &serial_omap_pops; | |
1345 | up->port.line = pdev->id; | |
1346 | ||
edd70ad7 G |
1347 | up->port.mapbase = mem->start; |
1348 | up->port.membase = ioremap(mem->start, resource_size(mem)); | |
1349 | if (!up->port.membase) { | |
1350 | dev_err(&pdev->dev, "can't ioremap UART\n"); | |
1351 | ret = -ENOMEM; | |
1352 | goto err; | |
1353 | } | |
1354 | ||
b612633b | 1355 | up->port.flags = omap_up_info->flags; |
b612633b G |
1356 | up->port.uartclk = omap_up_info->uartclk; |
1357 | up->uart_dma.uart_base = mem->start; | |
1358 | ||
1359 | if (omap_up_info->dma_enabled) { | |
1360 | up->uart_dma.uart_dma_tx = dma_tx->start; | |
1361 | up->uart_dma.uart_dma_rx = dma_rx->start; | |
1362 | up->use_dma = 1; | |
1363 | up->uart_dma.rx_buf_size = 4096; | |
1364 | up->uart_dma.rx_timeout = 2; | |
1365 | spin_lock_init(&(up->uart_dma.tx_lock)); | |
1366 | spin_lock_init(&(up->uart_dma.rx_lock)); | |
1367 | up->uart_dma.tx_dma_channel = OMAP_UART_DMA_CH_FREE; | |
1368 | up->uart_dma.rx_dma_channel = OMAP_UART_DMA_CH_FREE; | |
1369 | } | |
1370 | ||
fcdca757 G |
1371 | pm_runtime_use_autosuspend(&pdev->dev); |
1372 | pm_runtime_set_autosuspend_delay(&pdev->dev, | |
1373 | OMAP_UART_AUTOSUSPEND_DELAY); | |
1374 | ||
1375 | pm_runtime_irq_safe(&pdev->dev); | |
1376 | pm_runtime_enable(&pdev->dev); | |
1377 | pm_runtime_get_sync(&pdev->dev); | |
1378 | ||
b612633b G |
1379 | ui[pdev->id] = up; |
1380 | serial_omap_add_console_port(up); | |
1381 | ||
1382 | ret = uart_add_one_port(&serial_omap_reg, &up->port); | |
1383 | if (ret != 0) | |
1384 | goto do_release_region; | |
1385 | ||
fcdca757 | 1386 | pm_runtime_put(&pdev->dev); |
b612633b G |
1387 | platform_set_drvdata(pdev, up); |
1388 | return 0; | |
1389 | err: | |
1390 | dev_err(&pdev->dev, "[UART%d]: failure [%s]: %d\n", | |
1391 | pdev->id, __func__, ret); | |
1392 | do_release_region: | |
28f65c11 | 1393 | release_mem_region(mem->start, resource_size(mem)); |
b612633b G |
1394 | return ret; |
1395 | } | |
1396 | ||
1397 | static int serial_omap_remove(struct platform_device *dev) | |
1398 | { | |
1399 | struct uart_omap_port *up = platform_get_drvdata(dev); | |
1400 | ||
b612633b | 1401 | if (up) { |
fcdca757 | 1402 | pm_runtime_disable(&up->pdev->dev); |
b612633b G |
1403 | uart_remove_one_port(&serial_omap_reg, &up->port); |
1404 | kfree(up); | |
1405 | } | |
fcdca757 G |
1406 | |
1407 | platform_set_drvdata(dev, NULL); | |
1408 | return 0; | |
1409 | } | |
1410 | ||
1411 | #ifdef CONFIG_PM_RUNTIME | |
1412 | static int serial_omap_runtime_suspend(struct device *dev) | |
1413 | { | |
b612633b G |
1414 | return 0; |
1415 | } | |
1416 | ||
fcdca757 G |
1417 | static int serial_omap_runtime_resume(struct device *dev) |
1418 | { | |
1419 | return 0; | |
1420 | } | |
1421 | #endif | |
1422 | ||
1423 | static const struct dev_pm_ops serial_omap_dev_pm_ops = { | |
1424 | SET_SYSTEM_SLEEP_PM_OPS(serial_omap_suspend, serial_omap_resume) | |
1425 | SET_RUNTIME_PM_OPS(serial_omap_runtime_suspend, | |
1426 | serial_omap_runtime_resume, NULL) | |
1427 | }; | |
1428 | ||
b612633b G |
1429 | static struct platform_driver serial_omap_driver = { |
1430 | .probe = serial_omap_probe, | |
1431 | .remove = serial_omap_remove, | |
b612633b G |
1432 | .driver = { |
1433 | .name = DRIVER_NAME, | |
fcdca757 | 1434 | .pm = &serial_omap_dev_pm_ops, |
b612633b G |
1435 | }, |
1436 | }; | |
1437 | ||
1438 | static int __init serial_omap_init(void) | |
1439 | { | |
1440 | int ret; | |
1441 | ||
1442 | ret = uart_register_driver(&serial_omap_reg); | |
1443 | if (ret != 0) | |
1444 | return ret; | |
1445 | ret = platform_driver_register(&serial_omap_driver); | |
1446 | if (ret != 0) | |
1447 | uart_unregister_driver(&serial_omap_reg); | |
1448 | return ret; | |
1449 | } | |
1450 | ||
1451 | static void __exit serial_omap_exit(void) | |
1452 | { | |
1453 | platform_driver_unregister(&serial_omap_driver); | |
1454 | uart_unregister_driver(&serial_omap_reg); | |
1455 | } | |
1456 | ||
1457 | module_init(serial_omap_init); | |
1458 | module_exit(serial_omap_exit); | |
1459 | ||
1460 | MODULE_DESCRIPTION("OMAP High Speed UART driver"); | |
1461 | MODULE_LICENSE("GPL"); | |
1462 | MODULE_AUTHOR("Texas Instruments Inc"); |