Commit | Line | Data |
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b612633b G |
1 | /* |
2 | * Driver for OMAP-UART controller. | |
3 | * Based on drivers/serial/8250.c | |
4 | * | |
5 | * Copyright (C) 2010 Texas Instruments. | |
6 | * | |
7 | * Authors: | |
8 | * Govindraj R <govindraj.raja@ti.com> | |
9 | * Thara Gopinath <thara@ti.com> | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2 of the License, or | |
14 | * (at your option) any later version. | |
15 | * | |
25985edc | 16 | * Note: This driver is made separate from 8250 driver as we cannot |
b612633b G |
17 | * over load 8250 driver with omap platform specific configuration for |
18 | * features like DMA, it makes easier to implement features like DMA and | |
19 | * hardware flow control and software flow control configuration with | |
20 | * this driver as required for the omap-platform. | |
21 | */ | |
22 | ||
364a6ece TW |
23 | #if defined(CONFIG_SERIAL_OMAP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) |
24 | #define SUPPORT_SYSRQ | |
25 | #endif | |
26 | ||
b612633b G |
27 | #include <linux/module.h> |
28 | #include <linux/init.h> | |
29 | #include <linux/console.h> | |
30 | #include <linux/serial_reg.h> | |
31 | #include <linux/delay.h> | |
32 | #include <linux/slab.h> | |
33 | #include <linux/tty.h> | |
34 | #include <linux/tty_flip.h> | |
d21e4005 | 35 | #include <linux/platform_device.h> |
b612633b | 36 | #include <linux/io.h> |
b612633b G |
37 | #include <linux/clk.h> |
38 | #include <linux/serial_core.h> | |
39 | #include <linux/irq.h> | |
fcdca757 | 40 | #include <linux/pm_runtime.h> |
d92b0dfc | 41 | #include <linux/of.h> |
9574f36f | 42 | #include <linux/gpio.h> |
b612633b | 43 | |
b612633b G |
44 | #include <plat/omap-serial.h> |
45 | ||
7c77c8de G |
46 | #define UART_BUILD_REVISION(x, y) (((x) << 8) | (y)) |
47 | ||
48 | #define OMAP_UART_REV_42 0x0402 | |
49 | #define OMAP_UART_REV_46 0x0406 | |
50 | #define OMAP_UART_REV_52 0x0502 | |
51 | #define OMAP_UART_REV_63 0x0603 | |
52 | ||
8fe789dc RN |
53 | #define DEFAULT_CLK_SPEED 48000000 /* 48Mhz*/ |
54 | ||
0ba5f668 PW |
55 | /* SCR register bitmasks */ |
56 | #define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK (1 << 7) | |
57 | ||
58 | /* FCR register bitmasks */ | |
59 | #define OMAP_UART_FCR_RX_FIFO_TRIG_SHIFT 6 | |
60 | #define OMAP_UART_FCR_RX_FIFO_TRIG_MASK (0x3 << 6) | |
61 | ||
7c77c8de G |
62 | /* MVR register bitmasks */ |
63 | #define OMAP_UART_MVR_SCHEME_SHIFT 30 | |
64 | ||
65 | #define OMAP_UART_LEGACY_MVR_MAJ_MASK 0xf0 | |
66 | #define OMAP_UART_LEGACY_MVR_MAJ_SHIFT 4 | |
67 | #define OMAP_UART_LEGACY_MVR_MIN_MASK 0x0f | |
68 | ||
69 | #define OMAP_UART_MVR_MAJ_MASK 0x700 | |
70 | #define OMAP_UART_MVR_MAJ_SHIFT 8 | |
71 | #define OMAP_UART_MVR_MIN_MASK 0x3f | |
72 | ||
d37c6ceb FB |
73 | struct uart_omap_port { |
74 | struct uart_port port; | |
75 | struct uart_omap_dma uart_dma; | |
76 | struct device *dev; | |
77 | ||
78 | unsigned char ier; | |
79 | unsigned char lcr; | |
80 | unsigned char mcr; | |
81 | unsigned char fcr; | |
82 | unsigned char efr; | |
83 | unsigned char dll; | |
84 | unsigned char dlh; | |
85 | unsigned char mdr1; | |
86 | unsigned char scr; | |
87 | ||
88 | int use_dma; | |
89 | /* | |
90 | * Some bits in registers are cleared on a read, so they must | |
91 | * be saved whenever the register is read but the bits will not | |
92 | * be immediately processed. | |
93 | */ | |
94 | unsigned int lsr_break_flag; | |
95 | unsigned char msr_saved_flags; | |
96 | char name[20]; | |
97 | unsigned long port_activity; | |
98 | u32 context_loss_cnt; | |
99 | u32 errata; | |
100 | u8 wakeups_enabled; | |
101 | unsigned int irq_pending:1; | |
102 | ||
103 | struct pm_qos_request pm_qos_request; | |
104 | u32 latency; | |
105 | u32 calc_latency; | |
106 | struct work_struct qos_work; | |
107 | }; | |
108 | ||
109 | #define to_uart_omap_port(p) ((container_of((p), struct uart_omap_port, port))) | |
110 | ||
b612633b G |
111 | static struct uart_omap_port *ui[OMAP_MAX_HSUART_PORTS]; |
112 | ||
113 | /* Forward declaration of functions */ | |
94734749 | 114 | static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1); |
b612633b | 115 | |
2fd14964 | 116 | static struct workqueue_struct *serial_omap_uart_wq; |
b612633b G |
117 | |
118 | static inline unsigned int serial_in(struct uart_omap_port *up, int offset) | |
119 | { | |
120 | offset <<= up->port.regshift; | |
121 | return readw(up->port.membase + offset); | |
122 | } | |
123 | ||
124 | static inline void serial_out(struct uart_omap_port *up, int offset, int value) | |
125 | { | |
126 | offset <<= up->port.regshift; | |
127 | writew(value, up->port.membase + offset); | |
128 | } | |
129 | ||
130 | static inline void serial_omap_clear_fifos(struct uart_omap_port *up) | |
131 | { | |
132 | serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO); | |
133 | serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | | |
134 | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); | |
135 | serial_out(up, UART_FCR, 0); | |
136 | } | |
137 | ||
e5b57c03 FB |
138 | static int serial_omap_get_context_loss_count(struct uart_omap_port *up) |
139 | { | |
d8ee4ea6 | 140 | struct omap_uart_port_info *pdata = up->dev->platform_data; |
e5b57c03 FB |
141 | |
142 | if (!pdata->get_context_loss_count) | |
143 | return 0; | |
144 | ||
d8ee4ea6 | 145 | return pdata->get_context_loss_count(up->dev); |
e5b57c03 FB |
146 | } |
147 | ||
148 | static void serial_omap_set_forceidle(struct uart_omap_port *up) | |
149 | { | |
d8ee4ea6 | 150 | struct omap_uart_port_info *pdata = up->dev->platform_data; |
e5b57c03 FB |
151 | |
152 | if (pdata->set_forceidle) | |
d8ee4ea6 | 153 | pdata->set_forceidle(up->dev); |
e5b57c03 FB |
154 | } |
155 | ||
156 | static void serial_omap_set_noidle(struct uart_omap_port *up) | |
157 | { | |
d8ee4ea6 | 158 | struct omap_uart_port_info *pdata = up->dev->platform_data; |
e5b57c03 FB |
159 | |
160 | if (pdata->set_noidle) | |
d8ee4ea6 | 161 | pdata->set_noidle(up->dev); |
e5b57c03 FB |
162 | } |
163 | ||
164 | static void serial_omap_enable_wakeup(struct uart_omap_port *up, bool enable) | |
165 | { | |
d8ee4ea6 | 166 | struct omap_uart_port_info *pdata = up->dev->platform_data; |
e5b57c03 FB |
167 | |
168 | if (pdata->enable_wakeup) | |
d8ee4ea6 | 169 | pdata->enable_wakeup(up->dev, enable); |
e5b57c03 FB |
170 | } |
171 | ||
b612633b G |
172 | /* |
173 | * serial_omap_get_divisor - calculate divisor value | |
174 | * @port: uart port info | |
175 | * @baud: baudrate for which divisor needs to be calculated. | |
176 | * | |
177 | * We have written our own function to get the divisor so as to support | |
178 | * 13x mode. 3Mbps Baudrate as an different divisor. | |
179 | * Reference OMAP TRM Chapter 17: | |
180 | * Table 17-1. UART Mode Baud Rates, Divisor Values, and Error Rates | |
181 | * referring to oversampling - divisor value | |
182 | * baudrate 460,800 to 3,686,400 all have divisor 13 | |
183 | * except 3,000,000 which has divisor value 16 | |
184 | */ | |
185 | static unsigned int | |
186 | serial_omap_get_divisor(struct uart_port *port, unsigned int baud) | |
187 | { | |
188 | unsigned int divisor; | |
189 | ||
190 | if (baud > OMAP_MODE13X_SPEED && baud != 3000000) | |
191 | divisor = 13; | |
192 | else | |
193 | divisor = 16; | |
194 | return port->uartclk/(baud * divisor); | |
195 | } | |
196 | ||
b612633b G |
197 | static void serial_omap_enable_ms(struct uart_port *port) |
198 | { | |
c990f351 | 199 | struct uart_omap_port *up = to_uart_omap_port(port); |
b612633b | 200 | |
ba77433d | 201 | dev_dbg(up->port.dev, "serial_omap_enable_ms+%d\n", up->port.line); |
fcdca757 | 202 | |
d8ee4ea6 | 203 | pm_runtime_get_sync(up->dev); |
b612633b G |
204 | up->ier |= UART_IER_MSI; |
205 | serial_out(up, UART_IER, up->ier); | |
660ac5f4 FB |
206 | pm_runtime_mark_last_busy(up->dev); |
207 | pm_runtime_put_autosuspend(up->dev); | |
b612633b G |
208 | } |
209 | ||
210 | static void serial_omap_stop_tx(struct uart_port *port) | |
211 | { | |
c990f351 | 212 | struct uart_omap_port *up = to_uart_omap_port(port); |
b612633b | 213 | |
d8ee4ea6 | 214 | pm_runtime_get_sync(up->dev); |
b612633b G |
215 | if (up->ier & UART_IER_THRI) { |
216 | up->ier &= ~UART_IER_THRI; | |
217 | serial_out(up, UART_IER, up->ier); | |
218 | } | |
fcdca757 | 219 | |
49457430 | 220 | serial_omap_set_forceidle(up); |
be4b0281 | 221 | |
d8ee4ea6 FB |
222 | pm_runtime_mark_last_busy(up->dev); |
223 | pm_runtime_put_autosuspend(up->dev); | |
b612633b G |
224 | } |
225 | ||
226 | static void serial_omap_stop_rx(struct uart_port *port) | |
227 | { | |
c990f351 | 228 | struct uart_omap_port *up = to_uart_omap_port(port); |
b612633b | 229 | |
d8ee4ea6 | 230 | pm_runtime_get_sync(up->dev); |
b612633b G |
231 | up->ier &= ~UART_IER_RLSI; |
232 | up->port.read_status_mask &= ~UART_LSR_DR; | |
233 | serial_out(up, UART_IER, up->ier); | |
d8ee4ea6 FB |
234 | pm_runtime_mark_last_busy(up->dev); |
235 | pm_runtime_put_autosuspend(up->dev); | |
b612633b G |
236 | } |
237 | ||
bf63a086 | 238 | static void transmit_chars(struct uart_omap_port *up, unsigned int lsr) |
b612633b G |
239 | { |
240 | struct circ_buf *xmit = &up->port.state->xmit; | |
241 | int count; | |
242 | ||
bf63a086 FB |
243 | if (!(lsr & UART_LSR_THRE)) |
244 | return; | |
245 | ||
b612633b G |
246 | if (up->port.x_char) { |
247 | serial_out(up, UART_TX, up->port.x_char); | |
248 | up->port.icount.tx++; | |
249 | up->port.x_char = 0; | |
250 | return; | |
251 | } | |
252 | if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) { | |
253 | serial_omap_stop_tx(&up->port); | |
254 | return; | |
255 | } | |
af681cad | 256 | count = up->port.fifosize / 4; |
b612633b G |
257 | do { |
258 | serial_out(up, UART_TX, xmit->buf[xmit->tail]); | |
259 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); | |
260 | up->port.icount.tx++; | |
261 | if (uart_circ_empty(xmit)) | |
262 | break; | |
263 | } while (--count > 0); | |
264 | ||
0324a821 RK |
265 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) { |
266 | spin_unlock(&up->port.lock); | |
b612633b | 267 | uart_write_wakeup(&up->port); |
0324a821 RK |
268 | spin_lock(&up->port.lock); |
269 | } | |
b612633b G |
270 | |
271 | if (uart_circ_empty(xmit)) | |
272 | serial_omap_stop_tx(&up->port); | |
273 | } | |
274 | ||
275 | static inline void serial_omap_enable_ier_thri(struct uart_omap_port *up) | |
276 | { | |
277 | if (!(up->ier & UART_IER_THRI)) { | |
278 | up->ier |= UART_IER_THRI; | |
279 | serial_out(up, UART_IER, up->ier); | |
280 | } | |
281 | } | |
282 | ||
283 | static void serial_omap_start_tx(struct uart_port *port) | |
284 | { | |
c990f351 | 285 | struct uart_omap_port *up = to_uart_omap_port(port); |
b612633b | 286 | |
49457430 FB |
287 | pm_runtime_get_sync(up->dev); |
288 | serial_omap_enable_ier_thri(up); | |
289 | serial_omap_set_noidle(up); | |
290 | pm_runtime_mark_last_busy(up->dev); | |
291 | pm_runtime_put_autosuspend(up->dev); | |
b612633b G |
292 | } |
293 | ||
294 | static unsigned int check_modem_status(struct uart_omap_port *up) | |
295 | { | |
296 | unsigned int status; | |
297 | ||
298 | status = serial_in(up, UART_MSR); | |
299 | status |= up->msr_saved_flags; | |
300 | up->msr_saved_flags = 0; | |
301 | if ((status & UART_MSR_ANY_DELTA) == 0) | |
302 | return status; | |
303 | ||
304 | if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI && | |
305 | up->port.state != NULL) { | |
306 | if (status & UART_MSR_TERI) | |
307 | up->port.icount.rng++; | |
308 | if (status & UART_MSR_DDSR) | |
309 | up->port.icount.dsr++; | |
310 | if (status & UART_MSR_DDCD) | |
311 | uart_handle_dcd_change | |
312 | (&up->port, status & UART_MSR_DCD); | |
313 | if (status & UART_MSR_DCTS) | |
314 | uart_handle_cts_change | |
315 | (&up->port, status & UART_MSR_CTS); | |
316 | wake_up_interruptible(&up->port.state->port.delta_msr_wait); | |
317 | } | |
318 | ||
319 | return status; | |
320 | } | |
321 | ||
72256cbd FB |
322 | static void serial_omap_rlsi(struct uart_omap_port *up, unsigned int lsr) |
323 | { | |
324 | unsigned int flag; | |
325 | ||
326 | up->port.icount.rx++; | |
327 | flag = TTY_NORMAL; | |
328 | ||
329 | if (lsr & UART_LSR_BI) { | |
330 | flag = TTY_BREAK; | |
331 | lsr &= ~(UART_LSR_FE | UART_LSR_PE); | |
332 | up->port.icount.brk++; | |
333 | /* | |
334 | * We do the SysRQ and SAK checking | |
335 | * here because otherwise the break | |
336 | * may get masked by ignore_status_mask | |
337 | * or read_status_mask. | |
338 | */ | |
339 | if (uart_handle_break(&up->port)) | |
340 | return; | |
341 | ||
342 | } | |
343 | ||
344 | if (lsr & UART_LSR_PE) { | |
345 | flag = TTY_PARITY; | |
346 | up->port.icount.parity++; | |
347 | } | |
348 | ||
349 | if (lsr & UART_LSR_FE) { | |
350 | flag = TTY_FRAME; | |
351 | up->port.icount.frame++; | |
352 | } | |
353 | ||
354 | if (lsr & UART_LSR_OE) | |
355 | up->port.icount.overrun++; | |
356 | ||
357 | #ifdef CONFIG_SERIAL_OMAP_CONSOLE | |
358 | if (up->port.line == up->port.cons->index) { | |
359 | /* Recover the break flag from console xmit */ | |
360 | lsr |= up->lsr_break_flag; | |
361 | } | |
362 | #endif | |
363 | uart_insert_char(&up->port, lsr, UART_LSR_OE, 0, flag); | |
364 | } | |
365 | ||
366 | static void serial_omap_rdi(struct uart_omap_port *up, unsigned int lsr) | |
367 | { | |
368 | unsigned char ch = 0; | |
369 | unsigned int flag; | |
370 | ||
371 | if (!(lsr & UART_LSR_DR)) | |
372 | return; | |
373 | ||
374 | ch = serial_in(up, UART_RX); | |
375 | flag = TTY_NORMAL; | |
376 | up->port.icount.rx++; | |
377 | ||
378 | if (uart_handle_sysrq_char(&up->port, ch)) | |
379 | return; | |
380 | ||
381 | uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag); | |
382 | } | |
383 | ||
b612633b G |
384 | /** |
385 | * serial_omap_irq() - This handles the interrupt from one port | |
386 | * @irq: uart port irq number | |
387 | * @dev_id: uart port info | |
388 | */ | |
52c5513d | 389 | static irqreturn_t serial_omap_irq(int irq, void *dev_id) |
b612633b G |
390 | { |
391 | struct uart_omap_port *up = dev_id; | |
72256cbd | 392 | struct tty_struct *tty = up->port.state->port.tty; |
b612633b | 393 | unsigned int iir, lsr; |
81b75aef | 394 | unsigned int type; |
81b75aef | 395 | irqreturn_t ret = IRQ_NONE; |
72256cbd | 396 | int max_count = 256; |
b612633b | 397 | |
6c3a30c7 | 398 | spin_lock(&up->port.lock); |
d8ee4ea6 | 399 | pm_runtime_get_sync(up->dev); |
72256cbd FB |
400 | |
401 | do { | |
81b75aef | 402 | iir = serial_in(up, UART_IIR); |
72256cbd FB |
403 | if (iir & UART_IIR_NO_INT) |
404 | break; | |
405 | ||
406 | ret = IRQ_HANDLED; | |
407 | lsr = serial_in(up, UART_LSR); | |
408 | ||
409 | /* extract IRQ type from IIR register */ | |
410 | type = iir & 0x3e; | |
411 | ||
412 | switch (type) { | |
413 | case UART_IIR_MSI: | |
414 | check_modem_status(up); | |
415 | break; | |
416 | case UART_IIR_THRI: | |
bf63a086 | 417 | transmit_chars(up, lsr); |
72256cbd FB |
418 | break; |
419 | case UART_IIR_RX_TIMEOUT: | |
420 | /* FALLTHROUGH */ | |
421 | case UART_IIR_RDI: | |
422 | serial_omap_rdi(up, lsr); | |
423 | break; | |
424 | case UART_IIR_RLSI: | |
425 | serial_omap_rlsi(up, lsr); | |
426 | break; | |
427 | case UART_IIR_CTS_RTS_DSR: | |
428 | /* simply try again */ | |
429 | break; | |
430 | case UART_IIR_XOFF: | |
431 | /* FALLTHROUGH */ | |
432 | default: | |
433 | break; | |
434 | } | |
435 | } while (!(iir & UART_IIR_NO_INT) && max_count--); | |
b612633b | 436 | |
6c3a30c7 | 437 | spin_unlock(&up->port.lock); |
72256cbd FB |
438 | |
439 | tty_flip_buffer_push(tty); | |
440 | ||
d8ee4ea6 FB |
441 | pm_runtime_mark_last_busy(up->dev); |
442 | pm_runtime_put_autosuspend(up->dev); | |
b612633b | 443 | up->port_activity = jiffies; |
81b75aef FB |
444 | |
445 | return ret; | |
b612633b G |
446 | } |
447 | ||
448 | static unsigned int serial_omap_tx_empty(struct uart_port *port) | |
449 | { | |
c990f351 | 450 | struct uart_omap_port *up = to_uart_omap_port(port); |
b612633b G |
451 | unsigned long flags = 0; |
452 | unsigned int ret = 0; | |
453 | ||
d8ee4ea6 | 454 | pm_runtime_get_sync(up->dev); |
ba77433d | 455 | dev_dbg(up->port.dev, "serial_omap_tx_empty+%d\n", up->port.line); |
b612633b G |
456 | spin_lock_irqsave(&up->port.lock, flags); |
457 | ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0; | |
458 | spin_unlock_irqrestore(&up->port.lock, flags); | |
660ac5f4 FB |
459 | pm_runtime_mark_last_busy(up->dev); |
460 | pm_runtime_put_autosuspend(up->dev); | |
b612633b G |
461 | return ret; |
462 | } | |
463 | ||
464 | static unsigned int serial_omap_get_mctrl(struct uart_port *port) | |
465 | { | |
c990f351 | 466 | struct uart_omap_port *up = to_uart_omap_port(port); |
514f31d1 | 467 | unsigned int status; |
b612633b G |
468 | unsigned int ret = 0; |
469 | ||
d8ee4ea6 | 470 | pm_runtime_get_sync(up->dev); |
b612633b | 471 | status = check_modem_status(up); |
660ac5f4 FB |
472 | pm_runtime_mark_last_busy(up->dev); |
473 | pm_runtime_put_autosuspend(up->dev); | |
fcdca757 | 474 | |
ba77433d | 475 | dev_dbg(up->port.dev, "serial_omap_get_mctrl+%d\n", up->port.line); |
b612633b G |
476 | |
477 | if (status & UART_MSR_DCD) | |
478 | ret |= TIOCM_CAR; | |
479 | if (status & UART_MSR_RI) | |
480 | ret |= TIOCM_RNG; | |
481 | if (status & UART_MSR_DSR) | |
482 | ret |= TIOCM_DSR; | |
483 | if (status & UART_MSR_CTS) | |
484 | ret |= TIOCM_CTS; | |
485 | return ret; | |
486 | } | |
487 | ||
488 | static void serial_omap_set_mctrl(struct uart_port *port, unsigned int mctrl) | |
489 | { | |
c990f351 | 490 | struct uart_omap_port *up = to_uart_omap_port(port); |
b612633b G |
491 | unsigned char mcr = 0; |
492 | ||
ba77433d | 493 | dev_dbg(up->port.dev, "serial_omap_set_mctrl+%d\n", up->port.line); |
b612633b G |
494 | if (mctrl & TIOCM_RTS) |
495 | mcr |= UART_MCR_RTS; | |
496 | if (mctrl & TIOCM_DTR) | |
497 | mcr |= UART_MCR_DTR; | |
498 | if (mctrl & TIOCM_OUT1) | |
499 | mcr |= UART_MCR_OUT1; | |
500 | if (mctrl & TIOCM_OUT2) | |
501 | mcr |= UART_MCR_OUT2; | |
502 | if (mctrl & TIOCM_LOOP) | |
503 | mcr |= UART_MCR_LOOP; | |
504 | ||
d8ee4ea6 | 505 | pm_runtime_get_sync(up->dev); |
c538d20c G |
506 | up->mcr = serial_in(up, UART_MCR); |
507 | up->mcr |= mcr; | |
508 | serial_out(up, UART_MCR, up->mcr); | |
660ac5f4 FB |
509 | pm_runtime_mark_last_busy(up->dev); |
510 | pm_runtime_put_autosuspend(up->dev); | |
9574f36f N |
511 | |
512 | if (gpio_is_valid(up->DTR_gpio) && | |
513 | !!(mctrl & TIOCM_DTR) != up->DTR_active) { | |
514 | up->DTR_active = !up->DTR_active; | |
515 | if (gpio_cansleep(up->DTR_gpio)) | |
516 | schedule_work(&up->qos_work); | |
517 | else | |
518 | gpio_set_value(up->DTR_gpio, | |
519 | up->DTR_active != up->DTR_inverted); | |
520 | } | |
b612633b G |
521 | } |
522 | ||
523 | static void serial_omap_break_ctl(struct uart_port *port, int break_state) | |
524 | { | |
c990f351 | 525 | struct uart_omap_port *up = to_uart_omap_port(port); |
b612633b G |
526 | unsigned long flags = 0; |
527 | ||
ba77433d | 528 | dev_dbg(up->port.dev, "serial_omap_break_ctl+%d\n", up->port.line); |
d8ee4ea6 | 529 | pm_runtime_get_sync(up->dev); |
b612633b G |
530 | spin_lock_irqsave(&up->port.lock, flags); |
531 | if (break_state == -1) | |
532 | up->lcr |= UART_LCR_SBC; | |
533 | else | |
534 | up->lcr &= ~UART_LCR_SBC; | |
535 | serial_out(up, UART_LCR, up->lcr); | |
536 | spin_unlock_irqrestore(&up->port.lock, flags); | |
660ac5f4 FB |
537 | pm_runtime_mark_last_busy(up->dev); |
538 | pm_runtime_put_autosuspend(up->dev); | |
b612633b G |
539 | } |
540 | ||
541 | static int serial_omap_startup(struct uart_port *port) | |
542 | { | |
c990f351 | 543 | struct uart_omap_port *up = to_uart_omap_port(port); |
b612633b G |
544 | unsigned long flags = 0; |
545 | int retval; | |
546 | ||
547 | /* | |
548 | * Allocate the IRQ | |
549 | */ | |
550 | retval = request_irq(up->port.irq, serial_omap_irq, up->port.irqflags, | |
551 | up->name, up); | |
552 | if (retval) | |
553 | return retval; | |
554 | ||
ba77433d | 555 | dev_dbg(up->port.dev, "serial_omap_startup+%d\n", up->port.line); |
b612633b | 556 | |
d8ee4ea6 | 557 | pm_runtime_get_sync(up->dev); |
b612633b G |
558 | /* |
559 | * Clear the FIFO buffers and disable them. | |
560 | * (they will be reenabled in set_termios()) | |
561 | */ | |
562 | serial_omap_clear_fifos(up); | |
563 | /* For Hardware flow control */ | |
564 | serial_out(up, UART_MCR, UART_MCR_RTS); | |
565 | ||
566 | /* | |
567 | * Clear the interrupt registers. | |
568 | */ | |
569 | (void) serial_in(up, UART_LSR); | |
570 | if (serial_in(up, UART_LSR) & UART_LSR_DR) | |
571 | (void) serial_in(up, UART_RX); | |
572 | (void) serial_in(up, UART_IIR); | |
573 | (void) serial_in(up, UART_MSR); | |
574 | ||
575 | /* | |
576 | * Now, initialize the UART | |
577 | */ | |
578 | serial_out(up, UART_LCR, UART_LCR_WLEN8); | |
579 | spin_lock_irqsave(&up->port.lock, flags); | |
580 | /* | |
581 | * Most PC uarts need OUT2 raised to enable interrupts. | |
582 | */ | |
583 | up->port.mctrl |= TIOCM_OUT2; | |
584 | serial_omap_set_mctrl(&up->port, up->port.mctrl); | |
585 | spin_unlock_irqrestore(&up->port.lock, flags); | |
586 | ||
587 | up->msr_saved_flags = 0; | |
b612633b G |
588 | /* |
589 | * Finally, enable interrupts. Note: Modem status interrupts | |
590 | * are set via set_termios(), which will be occurring imminently | |
591 | * anyway, so we don't enable them here. | |
592 | */ | |
593 | up->ier = UART_IER_RLSI | UART_IER_RDI; | |
594 | serial_out(up, UART_IER, up->ier); | |
595 | ||
78841462 JN |
596 | /* Enable module level wake up */ |
597 | serial_out(up, UART_OMAP_WER, OMAP_UART_WER_MOD_WKUP); | |
598 | ||
d8ee4ea6 FB |
599 | pm_runtime_mark_last_busy(up->dev); |
600 | pm_runtime_put_autosuspend(up->dev); | |
b612633b G |
601 | up->port_activity = jiffies; |
602 | return 0; | |
603 | } | |
604 | ||
605 | static void serial_omap_shutdown(struct uart_port *port) | |
606 | { | |
c990f351 | 607 | struct uart_omap_port *up = to_uart_omap_port(port); |
b612633b G |
608 | unsigned long flags = 0; |
609 | ||
ba77433d | 610 | dev_dbg(up->port.dev, "serial_omap_shutdown+%d\n", up->port.line); |
fcdca757 | 611 | |
d8ee4ea6 | 612 | pm_runtime_get_sync(up->dev); |
b612633b G |
613 | /* |
614 | * Disable interrupts from this port | |
615 | */ | |
616 | up->ier = 0; | |
617 | serial_out(up, UART_IER, 0); | |
618 | ||
619 | spin_lock_irqsave(&up->port.lock, flags); | |
620 | up->port.mctrl &= ~TIOCM_OUT2; | |
621 | serial_omap_set_mctrl(&up->port, up->port.mctrl); | |
622 | spin_unlock_irqrestore(&up->port.lock, flags); | |
623 | ||
624 | /* | |
625 | * Disable break condition and FIFOs | |
626 | */ | |
627 | serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC); | |
628 | serial_omap_clear_fifos(up); | |
629 | ||
630 | /* | |
631 | * Read data port to reset things, and then free the irq | |
632 | */ | |
633 | if (serial_in(up, UART_LSR) & UART_LSR_DR) | |
634 | (void) serial_in(up, UART_RX); | |
fcdca757 | 635 | |
660ac5f4 FB |
636 | pm_runtime_mark_last_busy(up->dev); |
637 | pm_runtime_put_autosuspend(up->dev); | |
b612633b G |
638 | free_irq(up->port.irq, up); |
639 | } | |
640 | ||
641 | static inline void | |
642 | serial_omap_configure_xonxoff | |
643 | (struct uart_omap_port *up, struct ktermios *termios) | |
644 | { | |
b612633b | 645 | up->lcr = serial_in(up, UART_LCR); |
662b083a | 646 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); |
b612633b G |
647 | up->efr = serial_in(up, UART_EFR); |
648 | serial_out(up, UART_EFR, up->efr & ~UART_EFR_ECB); | |
649 | ||
650 | serial_out(up, UART_XON1, termios->c_cc[VSTART]); | |
651 | serial_out(up, UART_XOFF1, termios->c_cc[VSTOP]); | |
652 | ||
653 | /* clear SW control mode bits */ | |
c538d20c | 654 | up->efr &= OMAP_UART_SW_CLR; |
b612633b G |
655 | |
656 | /* | |
657 | * IXON Flag: | |
957ee727 VP |
658 | * Flow control for OMAP.TX |
659 | * OMAP.RX should listen for XON/XOFF | |
b612633b G |
660 | */ |
661 | if (termios->c_iflag & IXON) | |
957ee727 | 662 | up->efr |= OMAP_UART_SW_RX; |
b612633b G |
663 | |
664 | /* | |
665 | * IXOFF Flag: | |
957ee727 VP |
666 | * Flow control for OMAP.RX |
667 | * OMAP.TX should send XON/XOFF | |
b612633b G |
668 | */ |
669 | if (termios->c_iflag & IXOFF) | |
957ee727 | 670 | up->efr |= OMAP_UART_SW_TX; |
b612633b G |
671 | |
672 | serial_out(up, UART_EFR, up->efr | UART_EFR_ECB); | |
662b083a | 673 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); |
b612633b G |
674 | |
675 | up->mcr = serial_in(up, UART_MCR); | |
676 | ||
677 | /* | |
678 | * IXANY Flag: | |
679 | * Enable any character to restart output. | |
680 | * Operation resumes after receiving any | |
681 | * character after recognition of the XOFF character | |
682 | */ | |
683 | if (termios->c_iflag & IXANY) | |
684 | up->mcr |= UART_MCR_XONANY; | |
685 | ||
686 | serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR); | |
662b083a | 687 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); |
b612633b G |
688 | serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG); |
689 | /* Enable special char function UARTi.EFR_REG[5] and | |
690 | * load the new software flow control mode IXON or IXOFF | |
691 | * and restore the UARTi.EFR_REG[4] ENHANCED_EN value. | |
692 | */ | |
c538d20c | 693 | serial_out(up, UART_EFR, up->efr | UART_EFR_SCD); |
662b083a | 694 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); |
b612633b G |
695 | |
696 | serial_out(up, UART_MCR, up->mcr & ~UART_MCR_TCRTLR); | |
697 | serial_out(up, UART_LCR, up->lcr); | |
698 | } | |
699 | ||
2fd14964 G |
700 | static void serial_omap_uart_qos_work(struct work_struct *work) |
701 | { | |
702 | struct uart_omap_port *up = container_of(work, struct uart_omap_port, | |
703 | qos_work); | |
704 | ||
705 | pm_qos_update_request(&up->pm_qos_request, up->latency); | |
9574f36f N |
706 | if (gpio_is_valid(up->DTR_gpio)) |
707 | gpio_set_value_cansleep(up->DTR_gpio, | |
708 | up->DTR_active != up->DTR_inverted); | |
2fd14964 G |
709 | } |
710 | ||
b612633b G |
711 | static void |
712 | serial_omap_set_termios(struct uart_port *port, struct ktermios *termios, | |
713 | struct ktermios *old) | |
714 | { | |
c990f351 | 715 | struct uart_omap_port *up = to_uart_omap_port(port); |
b612633b G |
716 | unsigned char cval = 0; |
717 | unsigned char efr = 0; | |
718 | unsigned long flags = 0; | |
719 | unsigned int baud, quot; | |
720 | ||
721 | switch (termios->c_cflag & CSIZE) { | |
722 | case CS5: | |
723 | cval = UART_LCR_WLEN5; | |
724 | break; | |
725 | case CS6: | |
726 | cval = UART_LCR_WLEN6; | |
727 | break; | |
728 | case CS7: | |
729 | cval = UART_LCR_WLEN7; | |
730 | break; | |
731 | default: | |
732 | case CS8: | |
733 | cval = UART_LCR_WLEN8; | |
734 | break; | |
735 | } | |
736 | ||
737 | if (termios->c_cflag & CSTOPB) | |
738 | cval |= UART_LCR_STOP; | |
739 | if (termios->c_cflag & PARENB) | |
740 | cval |= UART_LCR_PARITY; | |
741 | if (!(termios->c_cflag & PARODD)) | |
742 | cval |= UART_LCR_EPAR; | |
743 | ||
744 | /* | |
745 | * Ask the core to calculate the divisor for us. | |
746 | */ | |
747 | ||
748 | baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/13); | |
749 | quot = serial_omap_get_divisor(port, baud); | |
750 | ||
2fd14964 | 751 | /* calculate wakeup latency constraint */ |
19723452 | 752 | up->calc_latency = (USEC_PER_SEC * up->port.fifosize) / (baud / 8); |
2fd14964 G |
753 | up->latency = up->calc_latency; |
754 | schedule_work(&up->qos_work); | |
755 | ||
c538d20c G |
756 | up->dll = quot & 0xff; |
757 | up->dlh = quot >> 8; | |
758 | up->mdr1 = UART_OMAP_MDR1_DISABLE; | |
759 | ||
b612633b G |
760 | up->fcr = UART_FCR_R_TRIG_01 | UART_FCR_T_TRIG_01 | |
761 | UART_FCR_ENABLE_FIFO; | |
b612633b G |
762 | |
763 | /* | |
764 | * Ok, we're now changing the port state. Do it with | |
765 | * interrupts disabled. | |
766 | */ | |
d8ee4ea6 | 767 | pm_runtime_get_sync(up->dev); |
b612633b G |
768 | spin_lock_irqsave(&up->port.lock, flags); |
769 | ||
770 | /* | |
771 | * Update the per-port timeout. | |
772 | */ | |
773 | uart_update_timeout(port, termios->c_cflag, baud); | |
774 | ||
775 | up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR; | |
776 | if (termios->c_iflag & INPCK) | |
777 | up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE; | |
778 | if (termios->c_iflag & (BRKINT | PARMRK)) | |
779 | up->port.read_status_mask |= UART_LSR_BI; | |
780 | ||
781 | /* | |
782 | * Characters to ignore | |
783 | */ | |
784 | up->port.ignore_status_mask = 0; | |
785 | if (termios->c_iflag & IGNPAR) | |
786 | up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE; | |
787 | if (termios->c_iflag & IGNBRK) { | |
788 | up->port.ignore_status_mask |= UART_LSR_BI; | |
789 | /* | |
790 | * If we're ignoring parity and break indicators, | |
791 | * ignore overruns too (for real raw support). | |
792 | */ | |
793 | if (termios->c_iflag & IGNPAR) | |
794 | up->port.ignore_status_mask |= UART_LSR_OE; | |
795 | } | |
796 | ||
797 | /* | |
798 | * ignore all characters if CREAD is not set | |
799 | */ | |
800 | if ((termios->c_cflag & CREAD) == 0) | |
801 | up->port.ignore_status_mask |= UART_LSR_DR; | |
802 | ||
803 | /* | |
804 | * Modem status interrupts | |
805 | */ | |
806 | up->ier &= ~UART_IER_MSI; | |
807 | if (UART_ENABLE_MS(&up->port, termios->c_cflag)) | |
808 | up->ier |= UART_IER_MSI; | |
809 | serial_out(up, UART_IER, up->ier); | |
810 | serial_out(up, UART_LCR, cval); /* reset DLAB */ | |
c538d20c | 811 | up->lcr = cval; |
32212897 | 812 | up->scr = OMAP_UART_SCR_TX_EMPTY; |
b612633b G |
813 | |
814 | /* FIFOs and DMA Settings */ | |
815 | ||
816 | /* FCR can be changed only when the | |
817 | * baud clock is not running | |
818 | * DLL_REG and DLH_REG set to 0. | |
819 | */ | |
662b083a | 820 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); |
b612633b G |
821 | serial_out(up, UART_DLL, 0); |
822 | serial_out(up, UART_DLM, 0); | |
823 | serial_out(up, UART_LCR, 0); | |
824 | ||
662b083a | 825 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); |
b612633b G |
826 | |
827 | up->efr = serial_in(up, UART_EFR); | |
828 | serial_out(up, UART_EFR, up->efr | UART_EFR_ECB); | |
829 | ||
662b083a | 830 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); |
b612633b G |
831 | up->mcr = serial_in(up, UART_MCR); |
832 | serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR); | |
833 | /* FIFO ENABLE, DMA MODE */ | |
0ba5f668 PW |
834 | |
835 | up->scr |= OMAP_UART_SCR_RX_TRIG_GRANU1_MASK; | |
b612633b | 836 | |
49457430 FB |
837 | /* Set receive FIFO threshold to 1 byte */ |
838 | up->fcr &= ~OMAP_UART_FCR_RX_FIFO_TRIG_MASK; | |
839 | up->fcr |= (0x1 << OMAP_UART_FCR_RX_FIFO_TRIG_SHIFT); | |
b612633b | 840 | |
0ba5f668 PW |
841 | serial_out(up, UART_FCR, up->fcr); |
842 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); | |
843 | ||
c538d20c G |
844 | serial_out(up, UART_OMAP_SCR, up->scr); |
845 | ||
b612633b | 846 | serial_out(up, UART_EFR, up->efr); |
662b083a | 847 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); |
b612633b G |
848 | serial_out(up, UART_MCR, up->mcr); |
849 | ||
850 | /* Protocol, Baud Rate, and Interrupt Settings */ | |
851 | ||
94734749 G |
852 | if (up->errata & UART_ERRATA_i202_MDR1_ACCESS) |
853 | serial_omap_mdr1_errataset(up, up->mdr1); | |
854 | else | |
855 | serial_out(up, UART_OMAP_MDR1, up->mdr1); | |
856 | ||
662b083a | 857 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); |
b612633b G |
858 | |
859 | up->efr = serial_in(up, UART_EFR); | |
860 | serial_out(up, UART_EFR, up->efr | UART_EFR_ECB); | |
861 | ||
862 | serial_out(up, UART_LCR, 0); | |
863 | serial_out(up, UART_IER, 0); | |
662b083a | 864 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); |
b612633b | 865 | |
c538d20c G |
866 | serial_out(up, UART_DLL, up->dll); /* LS of divisor */ |
867 | serial_out(up, UART_DLM, up->dlh); /* MS of divisor */ | |
b612633b G |
868 | |
869 | serial_out(up, UART_LCR, 0); | |
870 | serial_out(up, UART_IER, up->ier); | |
662b083a | 871 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); |
b612633b G |
872 | |
873 | serial_out(up, UART_EFR, up->efr); | |
874 | serial_out(up, UART_LCR, cval); | |
875 | ||
876 | if (baud > 230400 && baud != 3000000) | |
c538d20c | 877 | up->mdr1 = UART_OMAP_MDR1_13X_MODE; |
b612633b | 878 | else |
c538d20c G |
879 | up->mdr1 = UART_OMAP_MDR1_16X_MODE; |
880 | ||
94734749 G |
881 | if (up->errata & UART_ERRATA_i202_MDR1_ACCESS) |
882 | serial_omap_mdr1_errataset(up, up->mdr1); | |
883 | else | |
884 | serial_out(up, UART_OMAP_MDR1, up->mdr1); | |
b612633b G |
885 | |
886 | /* Hardware Flow Control Configuration */ | |
887 | ||
888 | if (termios->c_cflag & CRTSCTS) { | |
889 | efr |= (UART_EFR_CTS | UART_EFR_RTS); | |
662b083a | 890 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); |
b612633b G |
891 | |
892 | up->mcr = serial_in(up, UART_MCR); | |
893 | serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR); | |
894 | ||
662b083a | 895 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); |
b612633b G |
896 | up->efr = serial_in(up, UART_EFR); |
897 | serial_out(up, UART_EFR, up->efr | UART_EFR_ECB); | |
898 | ||
899 | serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG); | |
900 | serial_out(up, UART_EFR, efr); /* Enable AUTORTS and AUTOCTS */ | |
662b083a | 901 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); |
b612633b G |
902 | serial_out(up, UART_MCR, up->mcr | UART_MCR_RTS); |
903 | serial_out(up, UART_LCR, cval); | |
904 | } | |
905 | ||
906 | serial_omap_set_mctrl(&up->port, up->port.mctrl); | |
907 | /* Software Flow Control Configuration */ | |
b280a97d | 908 | serial_omap_configure_xonxoff(up, termios); |
b612633b G |
909 | |
910 | spin_unlock_irqrestore(&up->port.lock, flags); | |
660ac5f4 FB |
911 | pm_runtime_mark_last_busy(up->dev); |
912 | pm_runtime_put_autosuspend(up->dev); | |
ba77433d | 913 | dev_dbg(up->port.dev, "serial_omap_set_termios+%d\n", up->port.line); |
b612633b G |
914 | } |
915 | ||
9727faf4 FB |
916 | static int serial_omap_set_wake(struct uart_port *port, unsigned int state) |
917 | { | |
918 | struct uart_omap_port *up = to_uart_omap_port(port); | |
919 | ||
920 | serial_omap_enable_wakeup(up, state); | |
921 | ||
922 | return 0; | |
923 | } | |
924 | ||
b612633b G |
925 | static void |
926 | serial_omap_pm(struct uart_port *port, unsigned int state, | |
927 | unsigned int oldstate) | |
928 | { | |
c990f351 | 929 | struct uart_omap_port *up = to_uart_omap_port(port); |
b612633b G |
930 | unsigned char efr; |
931 | ||
ba77433d | 932 | dev_dbg(up->port.dev, "serial_omap_pm+%d\n", up->port.line); |
fcdca757 | 933 | |
d8ee4ea6 | 934 | pm_runtime_get_sync(up->dev); |
662b083a | 935 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); |
b612633b G |
936 | efr = serial_in(up, UART_EFR); |
937 | serial_out(up, UART_EFR, efr | UART_EFR_ECB); | |
938 | serial_out(up, UART_LCR, 0); | |
939 | ||
940 | serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0); | |
662b083a | 941 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); |
b612633b G |
942 | serial_out(up, UART_EFR, efr); |
943 | serial_out(up, UART_LCR, 0); | |
fcdca757 | 944 | |
d8ee4ea6 | 945 | if (!device_may_wakeup(up->dev)) { |
fcdca757 | 946 | if (!state) |
d8ee4ea6 | 947 | pm_runtime_forbid(up->dev); |
fcdca757 | 948 | else |
d8ee4ea6 | 949 | pm_runtime_allow(up->dev); |
fcdca757 G |
950 | } |
951 | ||
660ac5f4 FB |
952 | pm_runtime_mark_last_busy(up->dev); |
953 | pm_runtime_put_autosuspend(up->dev); | |
b612633b G |
954 | } |
955 | ||
956 | static void serial_omap_release_port(struct uart_port *port) | |
957 | { | |
958 | dev_dbg(port->dev, "serial_omap_release_port+\n"); | |
959 | } | |
960 | ||
961 | static int serial_omap_request_port(struct uart_port *port) | |
962 | { | |
963 | dev_dbg(port->dev, "serial_omap_request_port+\n"); | |
964 | return 0; | |
965 | } | |
966 | ||
967 | static void serial_omap_config_port(struct uart_port *port, int flags) | |
968 | { | |
c990f351 | 969 | struct uart_omap_port *up = to_uart_omap_port(port); |
b612633b G |
970 | |
971 | dev_dbg(up->port.dev, "serial_omap_config_port+%d\n", | |
ba77433d | 972 | up->port.line); |
b612633b G |
973 | up->port.type = PORT_OMAP; |
974 | } | |
975 | ||
976 | static int | |
977 | serial_omap_verify_port(struct uart_port *port, struct serial_struct *ser) | |
978 | { | |
979 | /* we don't want the core code to modify any port params */ | |
980 | dev_dbg(port->dev, "serial_omap_verify_port+\n"); | |
981 | return -EINVAL; | |
982 | } | |
983 | ||
984 | static const char * | |
985 | serial_omap_type(struct uart_port *port) | |
986 | { | |
c990f351 | 987 | struct uart_omap_port *up = to_uart_omap_port(port); |
b612633b | 988 | |
ba77433d | 989 | dev_dbg(up->port.dev, "serial_omap_type+%d\n", up->port.line); |
b612633b G |
990 | return up->name; |
991 | } | |
992 | ||
b612633b G |
993 | #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE) |
994 | ||
995 | static inline void wait_for_xmitr(struct uart_omap_port *up) | |
996 | { | |
997 | unsigned int status, tmout = 10000; | |
998 | ||
999 | /* Wait up to 10ms for the character(s) to be sent. */ | |
1000 | do { | |
1001 | status = serial_in(up, UART_LSR); | |
1002 | ||
1003 | if (status & UART_LSR_BI) | |
1004 | up->lsr_break_flag = UART_LSR_BI; | |
1005 | ||
1006 | if (--tmout == 0) | |
1007 | break; | |
1008 | udelay(1); | |
1009 | } while ((status & BOTH_EMPTY) != BOTH_EMPTY); | |
1010 | ||
1011 | /* Wait up to 1s for flow control if necessary */ | |
1012 | if (up->port.flags & UPF_CONS_FLOW) { | |
1013 | tmout = 1000000; | |
1014 | for (tmout = 1000000; tmout; tmout--) { | |
1015 | unsigned int msr = serial_in(up, UART_MSR); | |
1016 | ||
1017 | up->msr_saved_flags |= msr & MSR_SAVE_FLAGS; | |
1018 | if (msr & UART_MSR_CTS) | |
1019 | break; | |
1020 | ||
1021 | udelay(1); | |
1022 | } | |
1023 | } | |
1024 | } | |
1025 | ||
1b41dbc1 CC |
1026 | #ifdef CONFIG_CONSOLE_POLL |
1027 | ||
1028 | static void serial_omap_poll_put_char(struct uart_port *port, unsigned char ch) | |
1029 | { | |
c990f351 | 1030 | struct uart_omap_port *up = to_uart_omap_port(port); |
fcdca757 | 1031 | |
d8ee4ea6 | 1032 | pm_runtime_get_sync(up->dev); |
1b41dbc1 CC |
1033 | wait_for_xmitr(up); |
1034 | serial_out(up, UART_TX, ch); | |
660ac5f4 FB |
1035 | pm_runtime_mark_last_busy(up->dev); |
1036 | pm_runtime_put_autosuspend(up->dev); | |
1b41dbc1 CC |
1037 | } |
1038 | ||
1039 | static int serial_omap_poll_get_char(struct uart_port *port) | |
1040 | { | |
c990f351 | 1041 | struct uart_omap_port *up = to_uart_omap_port(port); |
fcdca757 | 1042 | unsigned int status; |
1b41dbc1 | 1043 | |
d8ee4ea6 | 1044 | pm_runtime_get_sync(up->dev); |
fcdca757 | 1045 | status = serial_in(up, UART_LSR); |
a6b19c33 FB |
1046 | if (!(status & UART_LSR_DR)) { |
1047 | status = NO_POLL_CHAR; | |
1048 | goto out; | |
1049 | } | |
1b41dbc1 | 1050 | |
fcdca757 | 1051 | status = serial_in(up, UART_RX); |
a6b19c33 FB |
1052 | |
1053 | out: | |
660ac5f4 FB |
1054 | pm_runtime_mark_last_busy(up->dev); |
1055 | pm_runtime_put_autosuspend(up->dev); | |
a6b19c33 | 1056 | |
fcdca757 | 1057 | return status; |
1b41dbc1 CC |
1058 | } |
1059 | ||
1060 | #endif /* CONFIG_CONSOLE_POLL */ | |
1061 | ||
1062 | #ifdef CONFIG_SERIAL_OMAP_CONSOLE | |
1063 | ||
1064 | static struct uart_omap_port *serial_omap_console_ports[4]; | |
1065 | ||
1066 | static struct uart_driver serial_omap_reg; | |
1067 | ||
b612633b G |
1068 | static void serial_omap_console_putchar(struct uart_port *port, int ch) |
1069 | { | |
c990f351 | 1070 | struct uart_omap_port *up = to_uart_omap_port(port); |
b612633b G |
1071 | |
1072 | wait_for_xmitr(up); | |
1073 | serial_out(up, UART_TX, ch); | |
1074 | } | |
1075 | ||
1076 | static void | |
1077 | serial_omap_console_write(struct console *co, const char *s, | |
1078 | unsigned int count) | |
1079 | { | |
1080 | struct uart_omap_port *up = serial_omap_console_ports[co->index]; | |
1081 | unsigned long flags; | |
1082 | unsigned int ier; | |
1083 | int locked = 1; | |
1084 | ||
d8ee4ea6 | 1085 | pm_runtime_get_sync(up->dev); |
fcdca757 | 1086 | |
b612633b G |
1087 | local_irq_save(flags); |
1088 | if (up->port.sysrq) | |
1089 | locked = 0; | |
1090 | else if (oops_in_progress) | |
1091 | locked = spin_trylock(&up->port.lock); | |
1092 | else | |
1093 | spin_lock(&up->port.lock); | |
1094 | ||
1095 | /* | |
1096 | * First save the IER then disable the interrupts | |
1097 | */ | |
1098 | ier = serial_in(up, UART_IER); | |
1099 | serial_out(up, UART_IER, 0); | |
1100 | ||
1101 | uart_console_write(&up->port, s, count, serial_omap_console_putchar); | |
1102 | ||
1103 | /* | |
1104 | * Finally, wait for transmitter to become empty | |
1105 | * and restore the IER | |
1106 | */ | |
1107 | wait_for_xmitr(up); | |
1108 | serial_out(up, UART_IER, ier); | |
1109 | /* | |
1110 | * The receive handling will happen properly because the | |
1111 | * receive ready bit will still be set; it is not cleared | |
1112 | * on read. However, modem control will not, we must | |
1113 | * call it if we have saved something in the saved flags | |
1114 | * while processing with interrupts off. | |
1115 | */ | |
1116 | if (up->msr_saved_flags) | |
1117 | check_modem_status(up); | |
1118 | ||
d8ee4ea6 FB |
1119 | pm_runtime_mark_last_busy(up->dev); |
1120 | pm_runtime_put_autosuspend(up->dev); | |
b612633b G |
1121 | if (locked) |
1122 | spin_unlock(&up->port.lock); | |
1123 | local_irq_restore(flags); | |
1124 | } | |
1125 | ||
1126 | static int __init | |
1127 | serial_omap_console_setup(struct console *co, char *options) | |
1128 | { | |
1129 | struct uart_omap_port *up; | |
1130 | int baud = 115200; | |
1131 | int bits = 8; | |
1132 | int parity = 'n'; | |
1133 | int flow = 'n'; | |
1134 | ||
1135 | if (serial_omap_console_ports[co->index] == NULL) | |
1136 | return -ENODEV; | |
1137 | up = serial_omap_console_ports[co->index]; | |
1138 | ||
1139 | if (options) | |
1140 | uart_parse_options(options, &baud, &parity, &bits, &flow); | |
1141 | ||
1142 | return uart_set_options(&up->port, co, baud, parity, bits, flow); | |
1143 | } | |
1144 | ||
1145 | static struct console serial_omap_console = { | |
1146 | .name = OMAP_SERIAL_NAME, | |
1147 | .write = serial_omap_console_write, | |
1148 | .device = uart_console_device, | |
1149 | .setup = serial_omap_console_setup, | |
1150 | .flags = CON_PRINTBUFFER, | |
1151 | .index = -1, | |
1152 | .data = &serial_omap_reg, | |
1153 | }; | |
1154 | ||
1155 | static void serial_omap_add_console_port(struct uart_omap_port *up) | |
1156 | { | |
ba77433d | 1157 | serial_omap_console_ports[up->port.line] = up; |
b612633b G |
1158 | } |
1159 | ||
1160 | #define OMAP_CONSOLE (&serial_omap_console) | |
1161 | ||
1162 | #else | |
1163 | ||
1164 | #define OMAP_CONSOLE NULL | |
1165 | ||
1166 | static inline void serial_omap_add_console_port(struct uart_omap_port *up) | |
1167 | {} | |
1168 | ||
1169 | #endif | |
1170 | ||
1171 | static struct uart_ops serial_omap_pops = { | |
1172 | .tx_empty = serial_omap_tx_empty, | |
1173 | .set_mctrl = serial_omap_set_mctrl, | |
1174 | .get_mctrl = serial_omap_get_mctrl, | |
1175 | .stop_tx = serial_omap_stop_tx, | |
1176 | .start_tx = serial_omap_start_tx, | |
1177 | .stop_rx = serial_omap_stop_rx, | |
1178 | .enable_ms = serial_omap_enable_ms, | |
1179 | .break_ctl = serial_omap_break_ctl, | |
1180 | .startup = serial_omap_startup, | |
1181 | .shutdown = serial_omap_shutdown, | |
1182 | .set_termios = serial_omap_set_termios, | |
1183 | .pm = serial_omap_pm, | |
9727faf4 | 1184 | .set_wake = serial_omap_set_wake, |
b612633b G |
1185 | .type = serial_omap_type, |
1186 | .release_port = serial_omap_release_port, | |
1187 | .request_port = serial_omap_request_port, | |
1188 | .config_port = serial_omap_config_port, | |
1189 | .verify_port = serial_omap_verify_port, | |
1b41dbc1 CC |
1190 | #ifdef CONFIG_CONSOLE_POLL |
1191 | .poll_put_char = serial_omap_poll_put_char, | |
1192 | .poll_get_char = serial_omap_poll_get_char, | |
1193 | #endif | |
b612633b G |
1194 | }; |
1195 | ||
1196 | static struct uart_driver serial_omap_reg = { | |
1197 | .owner = THIS_MODULE, | |
1198 | .driver_name = "OMAP-SERIAL", | |
1199 | .dev_name = OMAP_SERIAL_NAME, | |
1200 | .nr = OMAP_MAX_HSUART_PORTS, | |
1201 | .cons = OMAP_CONSOLE, | |
1202 | }; | |
1203 | ||
3bc4f0d8 | 1204 | #ifdef CONFIG_PM_SLEEP |
fcdca757 | 1205 | static int serial_omap_suspend(struct device *dev) |
b612633b | 1206 | { |
fcdca757 | 1207 | struct uart_omap_port *up = dev_get_drvdata(dev); |
b612633b | 1208 | |
2fd14964 | 1209 | if (up) { |
b612633b | 1210 | uart_suspend_port(&serial_omap_reg, &up->port); |
2fd14964 G |
1211 | flush_work_sync(&up->qos_work); |
1212 | } | |
1213 | ||
b612633b G |
1214 | return 0; |
1215 | } | |
1216 | ||
fcdca757 | 1217 | static int serial_omap_resume(struct device *dev) |
b612633b | 1218 | { |
fcdca757 | 1219 | struct uart_omap_port *up = dev_get_drvdata(dev); |
b612633b G |
1220 | |
1221 | if (up) | |
1222 | uart_resume_port(&serial_omap_reg, &up->port); | |
1223 | return 0; | |
1224 | } | |
fcdca757 | 1225 | #endif |
b612633b | 1226 | |
6d608ef3 | 1227 | static void __devinit omap_serial_fill_features_erratas(struct uart_omap_port *up) |
7c77c8de G |
1228 | { |
1229 | u32 mvr, scheme; | |
1230 | u16 revision, major, minor; | |
1231 | ||
1232 | mvr = serial_in(up, UART_OMAP_MVER); | |
1233 | ||
1234 | /* Check revision register scheme */ | |
1235 | scheme = mvr >> OMAP_UART_MVR_SCHEME_SHIFT; | |
1236 | ||
1237 | switch (scheme) { | |
1238 | case 0: /* Legacy Scheme: OMAP2/3 */ | |
1239 | /* MINOR_REV[0:4], MAJOR_REV[4:7] */ | |
1240 | major = (mvr & OMAP_UART_LEGACY_MVR_MAJ_MASK) >> | |
1241 | OMAP_UART_LEGACY_MVR_MAJ_SHIFT; | |
1242 | minor = (mvr & OMAP_UART_LEGACY_MVR_MIN_MASK); | |
1243 | break; | |
1244 | case 1: | |
1245 | /* New Scheme: OMAP4+ */ | |
1246 | /* MINOR_REV[0:5], MAJOR_REV[8:10] */ | |
1247 | major = (mvr & OMAP_UART_MVR_MAJ_MASK) >> | |
1248 | OMAP_UART_MVR_MAJ_SHIFT; | |
1249 | minor = (mvr & OMAP_UART_MVR_MIN_MASK); | |
1250 | break; | |
1251 | default: | |
d8ee4ea6 | 1252 | dev_warn(up->dev, |
7c77c8de G |
1253 | "Unknown %s revision, defaulting to highest\n", |
1254 | up->name); | |
1255 | /* highest possible revision */ | |
1256 | major = 0xff; | |
1257 | minor = 0xff; | |
1258 | } | |
1259 | ||
1260 | /* normalize revision for the driver */ | |
1261 | revision = UART_BUILD_REVISION(major, minor); | |
1262 | ||
1263 | switch (revision) { | |
1264 | case OMAP_UART_REV_46: | |
1265 | up->errata |= (UART_ERRATA_i202_MDR1_ACCESS | | |
1266 | UART_ERRATA_i291_DMA_FORCEIDLE); | |
1267 | break; | |
1268 | case OMAP_UART_REV_52: | |
1269 | up->errata |= (UART_ERRATA_i202_MDR1_ACCESS | | |
1270 | UART_ERRATA_i291_DMA_FORCEIDLE); | |
1271 | break; | |
1272 | case OMAP_UART_REV_63: | |
1273 | up->errata |= UART_ERRATA_i202_MDR1_ACCESS; | |
1274 | break; | |
1275 | default: | |
1276 | break; | |
1277 | } | |
1278 | } | |
1279 | ||
6d608ef3 | 1280 | static __devinit struct omap_uart_port_info *of_get_uart_port_info(struct device *dev) |
d92b0dfc RN |
1281 | { |
1282 | struct omap_uart_port_info *omap_up_info; | |
1283 | ||
1284 | omap_up_info = devm_kzalloc(dev, sizeof(*omap_up_info), GFP_KERNEL); | |
1285 | if (!omap_up_info) | |
1286 | return NULL; /* out of memory */ | |
1287 | ||
1288 | of_property_read_u32(dev->of_node, "clock-frequency", | |
1289 | &omap_up_info->uartclk); | |
1290 | return omap_up_info; | |
1291 | } | |
1292 | ||
6d608ef3 | 1293 | static int __devinit serial_omap_probe(struct platform_device *pdev) |
b612633b G |
1294 | { |
1295 | struct uart_omap_port *up; | |
49457430 | 1296 | struct resource *mem, *irq; |
b612633b | 1297 | struct omap_uart_port_info *omap_up_info = pdev->dev.platform_data; |
9574f36f | 1298 | int ret; |
b612633b | 1299 | |
d92b0dfc RN |
1300 | if (pdev->dev.of_node) |
1301 | omap_up_info = of_get_uart_port_info(&pdev->dev); | |
1302 | ||
b612633b G |
1303 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1304 | if (!mem) { | |
1305 | dev_err(&pdev->dev, "no mem resource?\n"); | |
1306 | return -ENODEV; | |
1307 | } | |
1308 | ||
1309 | irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); | |
1310 | if (!irq) { | |
1311 | dev_err(&pdev->dev, "no irq resource?\n"); | |
1312 | return -ENODEV; | |
1313 | } | |
1314 | ||
388bc262 | 1315 | if (!devm_request_mem_region(&pdev->dev, mem->start, resource_size(mem), |
28f65c11 | 1316 | pdev->dev.driver->name)) { |
b612633b G |
1317 | dev_err(&pdev->dev, "memory region already claimed\n"); |
1318 | return -EBUSY; | |
1319 | } | |
1320 | ||
9574f36f N |
1321 | if (gpio_is_valid(omap_up_info->DTR_gpio) && |
1322 | omap_up_info->DTR_present) { | |
1323 | ret = gpio_request(omap_up_info->DTR_gpio, "omap-serial"); | |
1324 | if (ret < 0) | |
1325 | return ret; | |
1326 | ret = gpio_direction_output(omap_up_info->DTR_gpio, | |
1327 | omap_up_info->DTR_inverted); | |
1328 | if (ret < 0) | |
1329 | return ret; | |
1330 | } | |
1331 | ||
388bc262 S |
1332 | up = devm_kzalloc(&pdev->dev, sizeof(*up), GFP_KERNEL); |
1333 | if (!up) | |
1334 | return -ENOMEM; | |
b612633b | 1335 | |
9574f36f N |
1336 | if (gpio_is_valid(omap_up_info->DTR_gpio) && |
1337 | omap_up_info->DTR_present) { | |
1338 | up->DTR_gpio = omap_up_info->DTR_gpio; | |
1339 | up->DTR_inverted = omap_up_info->DTR_inverted; | |
1340 | } else | |
1341 | up->DTR_gpio = -EINVAL; | |
1342 | up->DTR_active = 0; | |
1343 | ||
d8ee4ea6 | 1344 | up->dev = &pdev->dev; |
b612633b G |
1345 | up->port.dev = &pdev->dev; |
1346 | up->port.type = PORT_OMAP; | |
1347 | up->port.iotype = UPIO_MEM; | |
1348 | up->port.irq = irq->start; | |
1349 | ||
1350 | up->port.regshift = 2; | |
1351 | up->port.fifosize = 64; | |
1352 | up->port.ops = &serial_omap_pops; | |
b612633b | 1353 | |
d92b0dfc RN |
1354 | if (pdev->dev.of_node) |
1355 | up->port.line = of_alias_get_id(pdev->dev.of_node, "serial"); | |
1356 | else | |
1357 | up->port.line = pdev->id; | |
1358 | ||
1359 | if (up->port.line < 0) { | |
1360 | dev_err(&pdev->dev, "failed to get alias/pdev id, errno %d\n", | |
1361 | up->port.line); | |
1362 | ret = -ENODEV; | |
388bc262 | 1363 | goto err_port_line; |
d92b0dfc RN |
1364 | } |
1365 | ||
1366 | sprintf(up->name, "OMAP UART%d", up->port.line); | |
edd70ad7 | 1367 | up->port.mapbase = mem->start; |
388bc262 S |
1368 | up->port.membase = devm_ioremap(&pdev->dev, mem->start, |
1369 | resource_size(mem)); | |
edd70ad7 G |
1370 | if (!up->port.membase) { |
1371 | dev_err(&pdev->dev, "can't ioremap UART\n"); | |
1372 | ret = -ENOMEM; | |
388bc262 | 1373 | goto err_ioremap; |
edd70ad7 G |
1374 | } |
1375 | ||
b612633b | 1376 | up->port.flags = omap_up_info->flags; |
b612633b | 1377 | up->port.uartclk = omap_up_info->uartclk; |
8fe789dc RN |
1378 | if (!up->port.uartclk) { |
1379 | up->port.uartclk = DEFAULT_CLK_SPEED; | |
1380 | dev_warn(&pdev->dev, "No clock speed specified: using default:" | |
1381 | "%d\n", DEFAULT_CLK_SPEED); | |
1382 | } | |
b612633b | 1383 | |
2fd14964 G |
1384 | up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE; |
1385 | up->calc_latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE; | |
1386 | pm_qos_add_request(&up->pm_qos_request, | |
1387 | PM_QOS_CPU_DMA_LATENCY, up->latency); | |
1388 | serial_omap_uart_wq = create_singlethread_workqueue(up->name); | |
1389 | INIT_WORK(&up->qos_work, serial_omap_uart_qos_work); | |
1390 | ||
93220dcc | 1391 | platform_set_drvdata(pdev, up); |
856e35bf | 1392 | pm_runtime_enable(&pdev->dev); |
fcdca757 G |
1393 | pm_runtime_use_autosuspend(&pdev->dev); |
1394 | pm_runtime_set_autosuspend_delay(&pdev->dev, | |
c86845db | 1395 | omap_up_info->autosuspend_timeout); |
fcdca757 G |
1396 | |
1397 | pm_runtime_irq_safe(&pdev->dev); | |
fcdca757 G |
1398 | pm_runtime_get_sync(&pdev->dev); |
1399 | ||
7c77c8de G |
1400 | omap_serial_fill_features_erratas(up); |
1401 | ||
ba77433d | 1402 | ui[up->port.line] = up; |
b612633b G |
1403 | serial_omap_add_console_port(up); |
1404 | ||
1405 | ret = uart_add_one_port(&serial_omap_reg, &up->port); | |
1406 | if (ret != 0) | |
388bc262 | 1407 | goto err_add_port; |
b612633b | 1408 | |
660ac5f4 FB |
1409 | pm_runtime_mark_last_busy(up->dev); |
1410 | pm_runtime_put_autosuspend(up->dev); | |
b612633b | 1411 | return 0; |
388bc262 S |
1412 | |
1413 | err_add_port: | |
1414 | pm_runtime_put(&pdev->dev); | |
1415 | pm_runtime_disable(&pdev->dev); | |
1416 | err_ioremap: | |
1417 | err_port_line: | |
b612633b G |
1418 | dev_err(&pdev->dev, "[UART%d]: failure [%s]: %d\n", |
1419 | pdev->id, __func__, ret); | |
b612633b G |
1420 | return ret; |
1421 | } | |
1422 | ||
6d608ef3 | 1423 | static int __devexit serial_omap_remove(struct platform_device *dev) |
b612633b G |
1424 | { |
1425 | struct uart_omap_port *up = platform_get_drvdata(dev); | |
1426 | ||
7e9c8e7d | 1427 | pm_runtime_put_sync(up->dev); |
1b42c8b2 FB |
1428 | pm_runtime_disable(up->dev); |
1429 | uart_remove_one_port(&serial_omap_reg, &up->port); | |
1430 | pm_qos_remove_request(&up->pm_qos_request); | |
fcdca757 | 1431 | |
fcdca757 G |
1432 | return 0; |
1433 | } | |
1434 | ||
94734749 G |
1435 | /* |
1436 | * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460) | |
1437 | * The access to uart register after MDR1 Access | |
1438 | * causes UART to corrupt data. | |
1439 | * | |
1440 | * Need a delay = | |
1441 | * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS) | |
1442 | * give 10 times as much | |
1443 | */ | |
1444 | static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1) | |
1445 | { | |
1446 | u8 timeout = 255; | |
1447 | ||
1448 | serial_out(up, UART_OMAP_MDR1, mdr1); | |
1449 | udelay(2); | |
1450 | serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT | | |
1451 | UART_FCR_CLEAR_RCVR); | |
1452 | /* | |
1453 | * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and | |
1454 | * TX_FIFO_E bit is 1. | |
1455 | */ | |
1456 | while (UART_LSR_THRE != (serial_in(up, UART_LSR) & | |
1457 | (UART_LSR_THRE | UART_LSR_DR))) { | |
1458 | timeout--; | |
1459 | if (!timeout) { | |
1460 | /* Should *never* happen. we warn and carry on */ | |
d8ee4ea6 | 1461 | dev_crit(up->dev, "Errata i202: timedout %x\n", |
94734749 G |
1462 | serial_in(up, UART_LSR)); |
1463 | break; | |
1464 | } | |
1465 | udelay(1); | |
1466 | } | |
1467 | } | |
1468 | ||
b5148856 | 1469 | #ifdef CONFIG_PM_RUNTIME |
9f9ac1e8 G |
1470 | static void serial_omap_restore_context(struct uart_omap_port *up) |
1471 | { | |
94734749 G |
1472 | if (up->errata & UART_ERRATA_i202_MDR1_ACCESS) |
1473 | serial_omap_mdr1_errataset(up, UART_OMAP_MDR1_DISABLE); | |
1474 | else | |
1475 | serial_out(up, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE); | |
1476 | ||
9f9ac1e8 G |
1477 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */ |
1478 | serial_out(up, UART_EFR, UART_EFR_ECB); | |
1479 | serial_out(up, UART_LCR, 0x0); /* Operational mode */ | |
1480 | serial_out(up, UART_IER, 0x0); | |
1481 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */ | |
c538d20c G |
1482 | serial_out(up, UART_DLL, up->dll); |
1483 | serial_out(up, UART_DLM, up->dlh); | |
9f9ac1e8 G |
1484 | serial_out(up, UART_LCR, 0x0); /* Operational mode */ |
1485 | serial_out(up, UART_IER, up->ier); | |
1486 | serial_out(up, UART_FCR, up->fcr); | |
1487 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); | |
1488 | serial_out(up, UART_MCR, up->mcr); | |
1489 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */ | |
c538d20c | 1490 | serial_out(up, UART_OMAP_SCR, up->scr); |
9f9ac1e8 G |
1491 | serial_out(up, UART_EFR, up->efr); |
1492 | serial_out(up, UART_LCR, up->lcr); | |
94734749 G |
1493 | if (up->errata & UART_ERRATA_i202_MDR1_ACCESS) |
1494 | serial_omap_mdr1_errataset(up, up->mdr1); | |
1495 | else | |
1496 | serial_out(up, UART_OMAP_MDR1, up->mdr1); | |
9f9ac1e8 G |
1497 | } |
1498 | ||
fcdca757 G |
1499 | static int serial_omap_runtime_suspend(struct device *dev) |
1500 | { | |
ec3bebc6 G |
1501 | struct uart_omap_port *up = dev_get_drvdata(dev); |
1502 | struct omap_uart_port_info *pdata = dev->platform_data; | |
1503 | ||
1504 | if (!up) | |
1505 | return -EINVAL; | |
1506 | ||
e5b57c03 | 1507 | if (!pdata) |
62f3ec5f G |
1508 | return 0; |
1509 | ||
e5b57c03 | 1510 | up->context_loss_cnt = serial_omap_get_context_loss_count(up); |
ec3bebc6 | 1511 | |
62f3ec5f G |
1512 | if (device_may_wakeup(dev)) { |
1513 | if (!up->wakeups_enabled) { | |
e5b57c03 | 1514 | serial_omap_enable_wakeup(up, true); |
62f3ec5f G |
1515 | up->wakeups_enabled = true; |
1516 | } | |
1517 | } else { | |
1518 | if (up->wakeups_enabled) { | |
e5b57c03 | 1519 | serial_omap_enable_wakeup(up, false); |
62f3ec5f G |
1520 | up->wakeups_enabled = false; |
1521 | } | |
1522 | } | |
1523 | ||
2fd14964 G |
1524 | up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE; |
1525 | schedule_work(&up->qos_work); | |
1526 | ||
b612633b G |
1527 | return 0; |
1528 | } | |
1529 | ||
fcdca757 G |
1530 | static int serial_omap_runtime_resume(struct device *dev) |
1531 | { | |
9f9ac1e8 | 1532 | struct uart_omap_port *up = dev_get_drvdata(dev); |
ec3bebc6 | 1533 | struct omap_uart_port_info *pdata = dev->platform_data; |
9f9ac1e8 | 1534 | |
a5f43138 | 1535 | if (up && pdata) { |
e5b57c03 | 1536 | u32 loss_cnt = serial_omap_get_context_loss_count(up); |
ec3bebc6 G |
1537 | |
1538 | if (up->context_loss_cnt != loss_cnt) | |
1539 | serial_omap_restore_context(up); | |
94734749 | 1540 | |
2fd14964 G |
1541 | up->latency = up->calc_latency; |
1542 | schedule_work(&up->qos_work); | |
ec3bebc6 | 1543 | } |
9f9ac1e8 | 1544 | |
b612633b G |
1545 | return 0; |
1546 | } | |
fcdca757 G |
1547 | #endif |
1548 | ||
1549 | static const struct dev_pm_ops serial_omap_dev_pm_ops = { | |
1550 | SET_SYSTEM_SLEEP_PM_OPS(serial_omap_suspend, serial_omap_resume) | |
1551 | SET_RUNTIME_PM_OPS(serial_omap_runtime_suspend, | |
1552 | serial_omap_runtime_resume, NULL) | |
1553 | }; | |
1554 | ||
d92b0dfc RN |
1555 | #if defined(CONFIG_OF) |
1556 | static const struct of_device_id omap_serial_of_match[] = { | |
1557 | { .compatible = "ti,omap2-uart" }, | |
1558 | { .compatible = "ti,omap3-uart" }, | |
1559 | { .compatible = "ti,omap4-uart" }, | |
1560 | {}, | |
1561 | }; | |
1562 | MODULE_DEVICE_TABLE(of, omap_serial_of_match); | |
1563 | #endif | |
b612633b G |
1564 | |
1565 | static struct platform_driver serial_omap_driver = { | |
1566 | .probe = serial_omap_probe, | |
6d608ef3 | 1567 | .remove = __devexit_p(serial_omap_remove), |
b612633b G |
1568 | .driver = { |
1569 | .name = DRIVER_NAME, | |
fcdca757 | 1570 | .pm = &serial_omap_dev_pm_ops, |
d92b0dfc | 1571 | .of_match_table = of_match_ptr(omap_serial_of_match), |
b612633b G |
1572 | }, |
1573 | }; | |
1574 | ||
1575 | static int __init serial_omap_init(void) | |
1576 | { | |
1577 | int ret; | |
1578 | ||
1579 | ret = uart_register_driver(&serial_omap_reg); | |
1580 | if (ret != 0) | |
1581 | return ret; | |
1582 | ret = platform_driver_register(&serial_omap_driver); | |
1583 | if (ret != 0) | |
1584 | uart_unregister_driver(&serial_omap_reg); | |
1585 | return ret; | |
1586 | } | |
1587 | ||
1588 | static void __exit serial_omap_exit(void) | |
1589 | { | |
1590 | platform_driver_unregister(&serial_omap_driver); | |
1591 | uart_unregister_driver(&serial_omap_reg); | |
1592 | } | |
1593 | ||
1594 | module_init(serial_omap_init); | |
1595 | module_exit(serial_omap_exit); | |
1596 | ||
1597 | MODULE_DESCRIPTION("OMAP High Speed UART driver"); | |
1598 | MODULE_LICENSE("GPL"); | |
1599 | MODULE_AUTHOR("Texas Instruments Inc"); |