Commit | Line | Data |
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b612633b G |
1 | /* |
2 | * Driver for OMAP-UART controller. | |
3 | * Based on drivers/serial/8250.c | |
4 | * | |
5 | * Copyright (C) 2010 Texas Instruments. | |
6 | * | |
7 | * Authors: | |
8 | * Govindraj R <govindraj.raja@ti.com> | |
9 | * Thara Gopinath <thara@ti.com> | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2 of the License, or | |
14 | * (at your option) any later version. | |
15 | * | |
25985edc | 16 | * Note: This driver is made separate from 8250 driver as we cannot |
b612633b G |
17 | * over load 8250 driver with omap platform specific configuration for |
18 | * features like DMA, it makes easier to implement features like DMA and | |
19 | * hardware flow control and software flow control configuration with | |
20 | * this driver as required for the omap-platform. | |
21 | */ | |
22 | ||
364a6ece TW |
23 | #if defined(CONFIG_SERIAL_OMAP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) |
24 | #define SUPPORT_SYSRQ | |
25 | #endif | |
26 | ||
b612633b G |
27 | #include <linux/module.h> |
28 | #include <linux/init.h> | |
29 | #include <linux/console.h> | |
30 | #include <linux/serial_reg.h> | |
31 | #include <linux/delay.h> | |
32 | #include <linux/slab.h> | |
33 | #include <linux/tty.h> | |
34 | #include <linux/tty_flip.h> | |
d21e4005 | 35 | #include <linux/platform_device.h> |
b612633b | 36 | #include <linux/io.h> |
b612633b G |
37 | #include <linux/clk.h> |
38 | #include <linux/serial_core.h> | |
39 | #include <linux/irq.h> | |
fcdca757 | 40 | #include <linux/pm_runtime.h> |
ee83bd3b | 41 | #include <linux/pm_wakeirq.h> |
d92b0dfc | 42 | #include <linux/of.h> |
2a0b965c | 43 | #include <linux/of_irq.h> |
9574f36f | 44 | #include <linux/gpio.h> |
4a0ac0f5 | 45 | #include <linux/of_gpio.h> |
d9ba5737 | 46 | #include <linux/platform_data/serial-omap.h> |
b612633b | 47 | |
4a0ac0f5 MJ |
48 | #include <dt-bindings/gpio/gpio.h> |
49 | ||
7af0ea5d | 50 | #define OMAP_MAX_HSUART_PORTS 10 |
f91b55ab | 51 | |
7c77c8de G |
52 | #define UART_BUILD_REVISION(x, y) (((x) << 8) | (y)) |
53 | ||
54 | #define OMAP_UART_REV_42 0x0402 | |
55 | #define OMAP_UART_REV_46 0x0406 | |
56 | #define OMAP_UART_REV_52 0x0502 | |
57 | #define OMAP_UART_REV_63 0x0603 | |
58 | ||
f64ffda6 G |
59 | #define OMAP_UART_TX_WAKEUP_EN BIT(7) |
60 | ||
61 | /* Feature flags */ | |
62 | #define OMAP_UART_WER_HAS_TX_WAKEUP BIT(0) | |
63 | ||
f91b55ab RK |
64 | #define UART_ERRATA_i202_MDR1_ACCESS BIT(0) |
65 | #define UART_ERRATA_i291_DMA_FORCEIDLE BIT(1) | |
66 | ||
fbf7ebe4 | 67 | #define DEFAULT_CLK_SPEED 48000000 /* 48Mhz */ |
8fe789dc | 68 | |
0ba5f668 PW |
69 | /* SCR register bitmasks */ |
70 | #define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK (1 << 7) | |
1776fd05 | 71 | #define OMAP_UART_SCR_TX_TRIG_GRANU1_MASK (1 << 6) |
f91b55ab | 72 | #define OMAP_UART_SCR_TX_EMPTY (1 << 3) |
0ba5f668 PW |
73 | |
74 | /* FCR register bitmasks */ | |
0ba5f668 | 75 | #define OMAP_UART_FCR_RX_FIFO_TRIG_MASK (0x3 << 6) |
6721ab7f | 76 | #define OMAP_UART_FCR_TX_FIFO_TRIG_MASK (0x3 << 4) |
0ba5f668 | 77 | |
7c77c8de G |
78 | /* MVR register bitmasks */ |
79 | #define OMAP_UART_MVR_SCHEME_SHIFT 30 | |
80 | ||
81 | #define OMAP_UART_LEGACY_MVR_MAJ_MASK 0xf0 | |
82 | #define OMAP_UART_LEGACY_MVR_MAJ_SHIFT 4 | |
83 | #define OMAP_UART_LEGACY_MVR_MIN_MASK 0x0f | |
84 | ||
85 | #define OMAP_UART_MVR_MAJ_MASK 0x700 | |
86 | #define OMAP_UART_MVR_MAJ_SHIFT 8 | |
87 | #define OMAP_UART_MVR_MIN_MASK 0x3f | |
88 | ||
f91b55ab RK |
89 | #define OMAP_UART_DMA_CH_FREE -1 |
90 | ||
91 | #define MSR_SAVE_FLAGS UART_MSR_ANY_DELTA | |
92 | #define OMAP_MODE13X_SPEED 230400 | |
93 | ||
94 | /* WER = 0x7F | |
95 | * Enable module level wakeup in WER reg | |
96 | */ | |
fbf7ebe4 | 97 | #define OMAP_UART_WER_MOD_WKUP 0x7F |
f91b55ab RK |
98 | |
99 | /* Enable XON/XOFF flow control on output */ | |
3af08bd7 | 100 | #define OMAP_UART_SW_TX 0x08 |
f91b55ab RK |
101 | |
102 | /* Enable XON/XOFF flow control on input */ | |
3af08bd7 | 103 | #define OMAP_UART_SW_RX 0x02 |
f91b55ab RK |
104 | |
105 | #define OMAP_UART_SW_CLR 0xF0 | |
106 | ||
107 | #define OMAP_UART_TCR_TRIG 0x0F | |
108 | ||
109 | struct uart_omap_dma { | |
110 | u8 uart_dma_tx; | |
111 | u8 uart_dma_rx; | |
112 | int rx_dma_channel; | |
113 | int tx_dma_channel; | |
114 | dma_addr_t rx_buf_dma_phys; | |
115 | dma_addr_t tx_buf_dma_phys; | |
116 | unsigned int uart_base; | |
117 | /* | |
fbf7ebe4 | 118 | * Buffer for rx dma. It is not required for tx because the buffer |
f91b55ab RK |
119 | * comes from port structure. |
120 | */ | |
121 | unsigned char *rx_buf; | |
122 | unsigned int prev_rx_dma_pos; | |
123 | int tx_buf_size; | |
124 | int tx_dma_used; | |
125 | int rx_dma_used; | |
126 | spinlock_t tx_lock; | |
127 | spinlock_t rx_lock; | |
128 | /* timer to poll activity on rx dma */ | |
129 | struct timer_list rx_timer; | |
130 | unsigned int rx_buf_size; | |
131 | unsigned int rx_poll_rate; | |
132 | unsigned int rx_timeout; | |
133 | }; | |
134 | ||
d37c6ceb FB |
135 | struct uart_omap_port { |
136 | struct uart_port port; | |
137 | struct uart_omap_dma uart_dma; | |
138 | struct device *dev; | |
2a0b965c | 139 | int wakeirq; |
d37c6ceb FB |
140 | |
141 | unsigned char ier; | |
142 | unsigned char lcr; | |
143 | unsigned char mcr; | |
144 | unsigned char fcr; | |
145 | unsigned char efr; | |
146 | unsigned char dll; | |
147 | unsigned char dlh; | |
148 | unsigned char mdr1; | |
149 | unsigned char scr; | |
f64ffda6 | 150 | unsigned char wer; |
d37c6ceb FB |
151 | |
152 | int use_dma; | |
153 | /* | |
154 | * Some bits in registers are cleared on a read, so they must | |
fbf7ebe4 | 155 | * be saved whenever the register is read, but the bits will not |
d37c6ceb FB |
156 | * be immediately processed. |
157 | */ | |
158 | unsigned int lsr_break_flag; | |
159 | unsigned char msr_saved_flags; | |
160 | char name[20]; | |
161 | unsigned long port_activity; | |
39aee51d | 162 | int context_loss_cnt; |
d37c6ceb | 163 | u32 errata; |
f64ffda6 | 164 | u32 features; |
d37c6ceb | 165 | |
4a0ac0f5 MJ |
166 | int rts_gpio; |
167 | ||
d37c6ceb FB |
168 | struct pm_qos_request pm_qos_request; |
169 | u32 latency; | |
170 | u32 calc_latency; | |
171 | struct work_struct qos_work; | |
ddd85e22 | 172 | bool is_suspending; |
d37c6ceb FB |
173 | }; |
174 | ||
e5f9bf72 | 175 | #define to_uart_omap_port(p) ((container_of((p), struct uart_omap_port, port))) |
d37c6ceb | 176 | |
b612633b G |
177 | static struct uart_omap_port *ui[OMAP_MAX_HSUART_PORTS]; |
178 | ||
179 | /* Forward declaration of functions */ | |
94734749 | 180 | static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1); |
b612633b G |
181 | |
182 | static inline unsigned int serial_in(struct uart_omap_port *up, int offset) | |
183 | { | |
184 | offset <<= up->port.regshift; | |
185 | return readw(up->port.membase + offset); | |
186 | } | |
187 | ||
188 | static inline void serial_out(struct uart_omap_port *up, int offset, int value) | |
189 | { | |
190 | offset <<= up->port.regshift; | |
191 | writew(value, up->port.membase + offset); | |
192 | } | |
193 | ||
194 | static inline void serial_omap_clear_fifos(struct uart_omap_port *up) | |
195 | { | |
196 | serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO); | |
197 | serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | | |
198 | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); | |
199 | serial_out(up, UART_FCR, 0); | |
200 | } | |
201 | ||
adfb9233 | 202 | #ifdef CONFIG_PM |
e5b57c03 FB |
203 | static int serial_omap_get_context_loss_count(struct uart_omap_port *up) |
204 | { | |
574de559 | 205 | struct omap_uart_port_info *pdata = dev_get_platdata(up->dev); |
e5b57c03 | 206 | |
ce2f08de | 207 | if (!pdata || !pdata->get_context_loss_count) |
a630fbfb | 208 | return -EINVAL; |
e5b57c03 | 209 | |
d8ee4ea6 | 210 | return pdata->get_context_loss_count(up->dev); |
e5b57c03 FB |
211 | } |
212 | ||
ee83bd3b | 213 | /* REVISIT: Remove this when omap3 boots in device tree only mode */ |
e5b57c03 FB |
214 | static void serial_omap_enable_wakeup(struct uart_omap_port *up, bool enable) |
215 | { | |
574de559 | 216 | struct omap_uart_port_info *pdata = dev_get_platdata(up->dev); |
e5b57c03 | 217 | |
ce2f08de FB |
218 | if (!pdata || !pdata->enable_wakeup) |
219 | return; | |
220 | ||
221 | pdata->enable_wakeup(up->dev, enable); | |
e5b57c03 | 222 | } |
adfb9233 | 223 | #endif /* CONFIG_PM */ |
e5b57c03 | 224 | |
13d6ceb4 FK |
225 | /* |
226 | * Calculate the absolute difference between the desired and actual baud | |
227 | * rate for the given mode. | |
228 | */ | |
229 | static inline int calculate_baud_abs_diff(struct uart_port *port, | |
230 | unsigned int baud, unsigned int mode) | |
231 | { | |
232 | unsigned int n = port->uartclk / (mode * baud); | |
233 | int abs_diff; | |
234 | ||
235 | if (n == 0) | |
236 | n = 1; | |
237 | ||
238 | abs_diff = baud - (port->uartclk / (mode * n)); | |
239 | if (abs_diff < 0) | |
240 | abs_diff = -abs_diff; | |
241 | ||
242 | return abs_diff; | |
243 | } | |
244 | ||
5fe21236 AP |
245 | /* |
246 | * serial_omap_baud_is_mode16 - check if baud rate is MODE16X | |
247 | * @port: uart port info | |
248 | * @baud: baudrate for which mode needs to be determined | |
249 | * | |
250 | * Returns true if baud rate is MODE16X and false if MODE13X | |
251 | * Original table in OMAP TRM named "UART Mode Baud Rates, Divisor Values, | |
252 | * and Error Rates" determines modes not for all common baud rates. | |
253 | * E.g. for 1000000 baud rate mode must be 16x, but according to that | |
254 | * table it's determined as 13x. | |
255 | */ | |
256 | static bool | |
257 | serial_omap_baud_is_mode16(struct uart_port *port, unsigned int baud) | |
258 | { | |
13d6ceb4 FK |
259 | int abs_diff_13 = calculate_baud_abs_diff(port, baud, 13); |
260 | int abs_diff_16 = calculate_baud_abs_diff(port, baud, 16); | |
261 | ||
262 | return (abs_diff_13 >= abs_diff_16); | |
5fe21236 AP |
263 | } |
264 | ||
b612633b G |
265 | /* |
266 | * serial_omap_get_divisor - calculate divisor value | |
267 | * @port: uart port info | |
268 | * @baud: baudrate for which divisor needs to be calculated. | |
b612633b G |
269 | */ |
270 | static unsigned int | |
271 | serial_omap_get_divisor(struct uart_port *port, unsigned int baud) | |
272 | { | |
4250b5d9 | 273 | unsigned int mode; |
b612633b | 274 | |
5fe21236 | 275 | if (!serial_omap_baud_is_mode16(port, baud)) |
4250b5d9 | 276 | mode = 13; |
b612633b | 277 | else |
4250b5d9 AP |
278 | mode = 16; |
279 | return port->uartclk/(mode * baud); | |
b612633b G |
280 | } |
281 | ||
b612633b G |
282 | static void serial_omap_enable_ms(struct uart_port *port) |
283 | { | |
c990f351 | 284 | struct uart_omap_port *up = to_uart_omap_port(port); |
b612633b | 285 | |
ba77433d | 286 | dev_dbg(up->port.dev, "serial_omap_enable_ms+%d\n", up->port.line); |
fcdca757 | 287 | |
d8ee4ea6 | 288 | pm_runtime_get_sync(up->dev); |
b612633b G |
289 | up->ier |= UART_IER_MSI; |
290 | serial_out(up, UART_IER, up->ier); | |
660ac5f4 FB |
291 | pm_runtime_mark_last_busy(up->dev); |
292 | pm_runtime_put_autosuspend(up->dev); | |
b612633b G |
293 | } |
294 | ||
295 | static void serial_omap_stop_tx(struct uart_port *port) | |
296 | { | |
c990f351 | 297 | struct uart_omap_port *up = to_uart_omap_port(port); |
4a0ac0f5 | 298 | int res; |
b612633b | 299 | |
d8ee4ea6 | 300 | pm_runtime_get_sync(up->dev); |
4a0ac0f5 | 301 | |
018e7448 | 302 | /* Handle RS-485 */ |
dadd7ecb | 303 | if (port->rs485.flags & SER_RS485_ENABLED) { |
018e7448 PP |
304 | if (up->scr & OMAP_UART_SCR_TX_EMPTY) { |
305 | /* THR interrupt is fired when both TX FIFO and TX | |
306 | * shift register are empty. This means there's nothing | |
307 | * left to transmit now, so make sure the THR interrupt | |
308 | * is fired when TX FIFO is below the trigger level, | |
309 | * disable THR interrupts and toggle the RS-485 GPIO | |
310 | * data direction pin if needed. | |
311 | */ | |
312 | up->scr &= ~OMAP_UART_SCR_TX_EMPTY; | |
313 | serial_out(up, UART_OMAP_SCR, up->scr); | |
dadd7ecb RRD |
314 | res = (port->rs485.flags & SER_RS485_RTS_AFTER_SEND) ? |
315 | 1 : 0; | |
4a0ac0f5 | 316 | if (gpio_get_value(up->rts_gpio) != res) { |
dadd7ecb RRD |
317 | if (port->rs485.delay_rts_after_send > 0) |
318 | mdelay( | |
319 | port->rs485.delay_rts_after_send); | |
4a0ac0f5 MJ |
320 | gpio_set_value(up->rts_gpio, res); |
321 | } | |
018e7448 PP |
322 | } else { |
323 | /* We're asked to stop, but there's still stuff in the | |
324 | * UART FIFO, so make sure the THR interrupt is fired | |
325 | * when both TX FIFO and TX shift register are empty. | |
326 | * The next THR interrupt (if no transmission is started | |
327 | * in the meantime) will indicate the end of a | |
328 | * transmission. Therefore we _don't_ disable THR | |
329 | * interrupts in this situation. | |
330 | */ | |
331 | up->scr |= OMAP_UART_SCR_TX_EMPTY; | |
332 | serial_out(up, UART_OMAP_SCR, up->scr); | |
333 | return; | |
4a0ac0f5 MJ |
334 | } |
335 | } | |
336 | ||
b612633b G |
337 | if (up->ier & UART_IER_THRI) { |
338 | up->ier &= ~UART_IER_THRI; | |
339 | serial_out(up, UART_IER, up->ier); | |
340 | } | |
fcdca757 | 341 | |
dadd7ecb RRD |
342 | if ((port->rs485.flags & SER_RS485_ENABLED) && |
343 | !(port->rs485.flags & SER_RS485_RX_DURING_TX)) { | |
3a13884a DL |
344 | /* |
345 | * Empty the RX FIFO, we are not interested in anything | |
346 | * received during the half-duplex transmission. | |
347 | */ | |
348 | serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_RCVR); | |
349 | /* Re-enable RX interrupts */ | |
cab53dc9 DL |
350 | up->ier |= UART_IER_RLSI | UART_IER_RDI; |
351 | up->port.read_status_mask |= UART_LSR_DR; | |
4a0ac0f5 MJ |
352 | serial_out(up, UART_IER, up->ier); |
353 | } | |
354 | ||
d8ee4ea6 FB |
355 | pm_runtime_mark_last_busy(up->dev); |
356 | pm_runtime_put_autosuspend(up->dev); | |
b612633b G |
357 | } |
358 | ||
359 | static void serial_omap_stop_rx(struct uart_port *port) | |
360 | { | |
c990f351 | 361 | struct uart_omap_port *up = to_uart_omap_port(port); |
b612633b | 362 | |
d8ee4ea6 | 363 | pm_runtime_get_sync(up->dev); |
cab53dc9 | 364 | up->ier &= ~(UART_IER_RLSI | UART_IER_RDI); |
b612633b G |
365 | up->port.read_status_mask &= ~UART_LSR_DR; |
366 | serial_out(up, UART_IER, up->ier); | |
d8ee4ea6 FB |
367 | pm_runtime_mark_last_busy(up->dev); |
368 | pm_runtime_put_autosuspend(up->dev); | |
b612633b G |
369 | } |
370 | ||
bf63a086 | 371 | static void transmit_chars(struct uart_omap_port *up, unsigned int lsr) |
b612633b G |
372 | { |
373 | struct circ_buf *xmit = &up->port.state->xmit; | |
374 | int count; | |
375 | ||
376 | if (up->port.x_char) { | |
377 | serial_out(up, UART_TX, up->port.x_char); | |
378 | up->port.icount.tx++; | |
379 | up->port.x_char = 0; | |
380 | return; | |
381 | } | |
382 | if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) { | |
383 | serial_omap_stop_tx(&up->port); | |
384 | return; | |
385 | } | |
355fe568 | 386 | count = up->port.fifosize / 4; |
b612633b G |
387 | do { |
388 | serial_out(up, UART_TX, xmit->buf[xmit->tail]); | |
389 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); | |
390 | up->port.icount.tx++; | |
391 | if (uart_circ_empty(xmit)) | |
392 | break; | |
393 | } while (--count > 0); | |
394 | ||
6bf78967 | 395 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) |
b612633b G |
396 | uart_write_wakeup(&up->port); |
397 | ||
398 | if (uart_circ_empty(xmit)) | |
399 | serial_omap_stop_tx(&up->port); | |
400 | } | |
401 | ||
402 | static inline void serial_omap_enable_ier_thri(struct uart_omap_port *up) | |
403 | { | |
404 | if (!(up->ier & UART_IER_THRI)) { | |
405 | up->ier |= UART_IER_THRI; | |
406 | serial_out(up, UART_IER, up->ier); | |
407 | } | |
408 | } | |
409 | ||
410 | static void serial_omap_start_tx(struct uart_port *port) | |
411 | { | |
c990f351 | 412 | struct uart_omap_port *up = to_uart_omap_port(port); |
4a0ac0f5 | 413 | int res; |
b612633b | 414 | |
49457430 | 415 | pm_runtime_get_sync(up->dev); |
4a0ac0f5 | 416 | |
018e7448 | 417 | /* Handle RS-485 */ |
dadd7ecb | 418 | if (port->rs485.flags & SER_RS485_ENABLED) { |
018e7448 PP |
419 | /* Fire THR interrupts when FIFO is below trigger level */ |
420 | up->scr &= ~OMAP_UART_SCR_TX_EMPTY; | |
421 | serial_out(up, UART_OMAP_SCR, up->scr); | |
422 | ||
4a0ac0f5 | 423 | /* if rts not already enabled */ |
dadd7ecb | 424 | res = (port->rs485.flags & SER_RS485_RTS_ON_SEND) ? 1 : 0; |
4a0ac0f5 MJ |
425 | if (gpio_get_value(up->rts_gpio) != res) { |
426 | gpio_set_value(up->rts_gpio, res); | |
dadd7ecb RRD |
427 | if (port->rs485.delay_rts_before_send > 0) |
428 | mdelay(port->rs485.delay_rts_before_send); | |
4a0ac0f5 MJ |
429 | } |
430 | } | |
431 | ||
dadd7ecb RRD |
432 | if ((port->rs485.flags & SER_RS485_ENABLED) && |
433 | !(port->rs485.flags & SER_RS485_RX_DURING_TX)) | |
4a0ac0f5 MJ |
434 | serial_omap_stop_rx(port); |
435 | ||
49457430 | 436 | serial_omap_enable_ier_thri(up); |
49457430 FB |
437 | pm_runtime_mark_last_busy(up->dev); |
438 | pm_runtime_put_autosuspend(up->dev); | |
b612633b G |
439 | } |
440 | ||
3af08bd7 RK |
441 | static void serial_omap_throttle(struct uart_port *port) |
442 | { | |
443 | struct uart_omap_port *up = to_uart_omap_port(port); | |
444 | unsigned long flags; | |
445 | ||
446 | pm_runtime_get_sync(up->dev); | |
447 | spin_lock_irqsave(&up->port.lock, flags); | |
448 | up->ier &= ~(UART_IER_RLSI | UART_IER_RDI); | |
449 | serial_out(up, UART_IER, up->ier); | |
450 | spin_unlock_irqrestore(&up->port.lock, flags); | |
451 | pm_runtime_mark_last_busy(up->dev); | |
452 | pm_runtime_put_autosuspend(up->dev); | |
453 | } | |
454 | ||
455 | static void serial_omap_unthrottle(struct uart_port *port) | |
456 | { | |
457 | struct uart_omap_port *up = to_uart_omap_port(port); | |
458 | unsigned long flags; | |
459 | ||
460 | pm_runtime_get_sync(up->dev); | |
461 | spin_lock_irqsave(&up->port.lock, flags); | |
462 | up->ier |= UART_IER_RLSI | UART_IER_RDI; | |
463 | serial_out(up, UART_IER, up->ier); | |
464 | spin_unlock_irqrestore(&up->port.lock, flags); | |
465 | pm_runtime_mark_last_busy(up->dev); | |
466 | pm_runtime_put_autosuspend(up->dev); | |
467 | } | |
468 | ||
b612633b G |
469 | static unsigned int check_modem_status(struct uart_omap_port *up) |
470 | { | |
471 | unsigned int status; | |
472 | ||
473 | status = serial_in(up, UART_MSR); | |
474 | status |= up->msr_saved_flags; | |
475 | up->msr_saved_flags = 0; | |
476 | if ((status & UART_MSR_ANY_DELTA) == 0) | |
477 | return status; | |
478 | ||
479 | if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI && | |
480 | up->port.state != NULL) { | |
481 | if (status & UART_MSR_TERI) | |
482 | up->port.icount.rng++; | |
483 | if (status & UART_MSR_DDSR) | |
484 | up->port.icount.dsr++; | |
485 | if (status & UART_MSR_DDCD) | |
486 | uart_handle_dcd_change | |
487 | (&up->port, status & UART_MSR_DCD); | |
488 | if (status & UART_MSR_DCTS) | |
489 | uart_handle_cts_change | |
490 | (&up->port, status & UART_MSR_CTS); | |
491 | wake_up_interruptible(&up->port.state->port.delta_msr_wait); | |
492 | } | |
493 | ||
494 | return status; | |
495 | } | |
496 | ||
72256cbd FB |
497 | static void serial_omap_rlsi(struct uart_omap_port *up, unsigned int lsr) |
498 | { | |
499 | unsigned int flag; | |
9a12fcf8 S |
500 | unsigned char ch = 0; |
501 | ||
502 | if (likely(lsr & UART_LSR_DR)) | |
503 | ch = serial_in(up, UART_RX); | |
72256cbd FB |
504 | |
505 | up->port.icount.rx++; | |
506 | flag = TTY_NORMAL; | |
507 | ||
508 | if (lsr & UART_LSR_BI) { | |
509 | flag = TTY_BREAK; | |
510 | lsr &= ~(UART_LSR_FE | UART_LSR_PE); | |
511 | up->port.icount.brk++; | |
512 | /* | |
513 | * We do the SysRQ and SAK checking | |
514 | * here because otherwise the break | |
515 | * may get masked by ignore_status_mask | |
516 | * or read_status_mask. | |
517 | */ | |
518 | if (uart_handle_break(&up->port)) | |
519 | return; | |
520 | ||
521 | } | |
522 | ||
523 | if (lsr & UART_LSR_PE) { | |
524 | flag = TTY_PARITY; | |
525 | up->port.icount.parity++; | |
526 | } | |
527 | ||
528 | if (lsr & UART_LSR_FE) { | |
529 | flag = TTY_FRAME; | |
530 | up->port.icount.frame++; | |
531 | } | |
532 | ||
533 | if (lsr & UART_LSR_OE) | |
534 | up->port.icount.overrun++; | |
535 | ||
536 | #ifdef CONFIG_SERIAL_OMAP_CONSOLE | |
537 | if (up->port.line == up->port.cons->index) { | |
538 | /* Recover the break flag from console xmit */ | |
539 | lsr |= up->lsr_break_flag; | |
540 | } | |
541 | #endif | |
542 | uart_insert_char(&up->port, lsr, UART_LSR_OE, 0, flag); | |
543 | } | |
544 | ||
545 | static void serial_omap_rdi(struct uart_omap_port *up, unsigned int lsr) | |
546 | { | |
547 | unsigned char ch = 0; | |
548 | unsigned int flag; | |
549 | ||
550 | if (!(lsr & UART_LSR_DR)) | |
551 | return; | |
552 | ||
553 | ch = serial_in(up, UART_RX); | |
554 | flag = TTY_NORMAL; | |
555 | up->port.icount.rx++; | |
556 | ||
557 | if (uart_handle_sysrq_char(&up->port, ch)) | |
558 | return; | |
559 | ||
560 | uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag); | |
561 | } | |
562 | ||
b612633b G |
563 | /** |
564 | * serial_omap_irq() - This handles the interrupt from one port | |
565 | * @irq: uart port irq number | |
566 | * @dev_id: uart port info | |
567 | */ | |
52c5513d | 568 | static irqreturn_t serial_omap_irq(int irq, void *dev_id) |
b612633b G |
569 | { |
570 | struct uart_omap_port *up = dev_id; | |
571 | unsigned int iir, lsr; | |
81b75aef | 572 | unsigned int type; |
7b013e44 | 573 | irqreturn_t ret = IRQ_NONE; |
72256cbd | 574 | int max_count = 256; |
b612633b | 575 | |
6c3a30c7 | 576 | spin_lock(&up->port.lock); |
d8ee4ea6 | 577 | pm_runtime_get_sync(up->dev); |
72256cbd FB |
578 | |
579 | do { | |
81b75aef | 580 | iir = serial_in(up, UART_IIR); |
72256cbd FB |
581 | if (iir & UART_IIR_NO_INT) |
582 | break; | |
583 | ||
7b013e44 | 584 | ret = IRQ_HANDLED; |
72256cbd FB |
585 | lsr = serial_in(up, UART_LSR); |
586 | ||
587 | /* extract IRQ type from IIR register */ | |
588 | type = iir & 0x3e; | |
589 | ||
590 | switch (type) { | |
591 | case UART_IIR_MSI: | |
592 | check_modem_status(up); | |
593 | break; | |
594 | case UART_IIR_THRI: | |
bf63a086 | 595 | transmit_chars(up, lsr); |
72256cbd FB |
596 | break; |
597 | case UART_IIR_RX_TIMEOUT: | |
598 | /* FALLTHROUGH */ | |
599 | case UART_IIR_RDI: | |
600 | serial_omap_rdi(up, lsr); | |
601 | break; | |
602 | case UART_IIR_RLSI: | |
603 | serial_omap_rlsi(up, lsr); | |
604 | break; | |
605 | case UART_IIR_CTS_RTS_DSR: | |
606 | /* simply try again */ | |
607 | break; | |
608 | case UART_IIR_XOFF: | |
609 | /* FALLTHROUGH */ | |
610 | default: | |
611 | break; | |
612 | } | |
613 | } while (!(iir & UART_IIR_NO_INT) && max_count--); | |
b612633b | 614 | |
6c3a30c7 | 615 | spin_unlock(&up->port.lock); |
72256cbd | 616 | |
2e124b4a | 617 | tty_flip_buffer_push(&up->port.state->port); |
72256cbd | 618 | |
d8ee4ea6 FB |
619 | pm_runtime_mark_last_busy(up->dev); |
620 | pm_runtime_put_autosuspend(up->dev); | |
b612633b | 621 | up->port_activity = jiffies; |
81b75aef | 622 | |
7b013e44 | 623 | return ret; |
b612633b G |
624 | } |
625 | ||
626 | static unsigned int serial_omap_tx_empty(struct uart_port *port) | |
627 | { | |
c990f351 | 628 | struct uart_omap_port *up = to_uart_omap_port(port); |
b612633b G |
629 | unsigned long flags = 0; |
630 | unsigned int ret = 0; | |
631 | ||
d8ee4ea6 | 632 | pm_runtime_get_sync(up->dev); |
ba77433d | 633 | dev_dbg(up->port.dev, "serial_omap_tx_empty+%d\n", up->port.line); |
b612633b G |
634 | spin_lock_irqsave(&up->port.lock, flags); |
635 | ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0; | |
636 | spin_unlock_irqrestore(&up->port.lock, flags); | |
660ac5f4 FB |
637 | pm_runtime_mark_last_busy(up->dev); |
638 | pm_runtime_put_autosuspend(up->dev); | |
b612633b G |
639 | return ret; |
640 | } | |
641 | ||
642 | static unsigned int serial_omap_get_mctrl(struct uart_port *port) | |
643 | { | |
c990f351 | 644 | struct uart_omap_port *up = to_uart_omap_port(port); |
514f31d1 | 645 | unsigned int status; |
b612633b G |
646 | unsigned int ret = 0; |
647 | ||
d8ee4ea6 | 648 | pm_runtime_get_sync(up->dev); |
b612633b | 649 | status = check_modem_status(up); |
660ac5f4 FB |
650 | pm_runtime_mark_last_busy(up->dev); |
651 | pm_runtime_put_autosuspend(up->dev); | |
fcdca757 | 652 | |
ba77433d | 653 | dev_dbg(up->port.dev, "serial_omap_get_mctrl+%d\n", up->port.line); |
b612633b G |
654 | |
655 | if (status & UART_MSR_DCD) | |
656 | ret |= TIOCM_CAR; | |
657 | if (status & UART_MSR_RI) | |
658 | ret |= TIOCM_RNG; | |
659 | if (status & UART_MSR_DSR) | |
660 | ret |= TIOCM_DSR; | |
661 | if (status & UART_MSR_CTS) | |
662 | ret |= TIOCM_CTS; | |
663 | return ret; | |
664 | } | |
665 | ||
666 | static void serial_omap_set_mctrl(struct uart_port *port, unsigned int mctrl) | |
667 | { | |
c990f351 | 668 | struct uart_omap_port *up = to_uart_omap_port(port); |
348f9bb3 | 669 | unsigned char mcr = 0, old_mcr, lcr; |
b612633b | 670 | |
ba77433d | 671 | dev_dbg(up->port.dev, "serial_omap_set_mctrl+%d\n", up->port.line); |
b612633b G |
672 | if (mctrl & TIOCM_RTS) |
673 | mcr |= UART_MCR_RTS; | |
674 | if (mctrl & TIOCM_DTR) | |
675 | mcr |= UART_MCR_DTR; | |
676 | if (mctrl & TIOCM_OUT1) | |
677 | mcr |= UART_MCR_OUT1; | |
678 | if (mctrl & TIOCM_OUT2) | |
679 | mcr |= UART_MCR_OUT2; | |
680 | if (mctrl & TIOCM_LOOP) | |
681 | mcr |= UART_MCR_LOOP; | |
682 | ||
d8ee4ea6 | 683 | pm_runtime_get_sync(up->dev); |
9363f8fa RK |
684 | old_mcr = serial_in(up, UART_MCR); |
685 | old_mcr &= ~(UART_MCR_LOOP | UART_MCR_OUT2 | UART_MCR_OUT1 | | |
686 | UART_MCR_DTR | UART_MCR_RTS); | |
687 | up->mcr = old_mcr | mcr; | |
c538d20c | 688 | serial_out(up, UART_MCR, up->mcr); |
348f9bb3 PH |
689 | |
690 | /* Turn off autoRTS if RTS is lowered; restore autoRTS if RTS raised */ | |
691 | lcr = serial_in(up, UART_LCR); | |
692 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); | |
693 | if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS)) | |
694 | up->efr |= UART_EFR_RTS; | |
695 | else | |
696 | up->efr &= UART_EFR_RTS; | |
697 | serial_out(up, UART_EFR, up->efr); | |
698 | serial_out(up, UART_LCR, lcr); | |
699 | ||
660ac5f4 FB |
700 | pm_runtime_mark_last_busy(up->dev); |
701 | pm_runtime_put_autosuspend(up->dev); | |
b612633b G |
702 | } |
703 | ||
704 | static void serial_omap_break_ctl(struct uart_port *port, int break_state) | |
705 | { | |
c990f351 | 706 | struct uart_omap_port *up = to_uart_omap_port(port); |
b612633b G |
707 | unsigned long flags = 0; |
708 | ||
ba77433d | 709 | dev_dbg(up->port.dev, "serial_omap_break_ctl+%d\n", up->port.line); |
d8ee4ea6 | 710 | pm_runtime_get_sync(up->dev); |
b612633b G |
711 | spin_lock_irqsave(&up->port.lock, flags); |
712 | if (break_state == -1) | |
713 | up->lcr |= UART_LCR_SBC; | |
714 | else | |
715 | up->lcr &= ~UART_LCR_SBC; | |
716 | serial_out(up, UART_LCR, up->lcr); | |
717 | spin_unlock_irqrestore(&up->port.lock, flags); | |
660ac5f4 FB |
718 | pm_runtime_mark_last_busy(up->dev); |
719 | pm_runtime_put_autosuspend(up->dev); | |
b612633b G |
720 | } |
721 | ||
722 | static int serial_omap_startup(struct uart_port *port) | |
723 | { | |
c990f351 | 724 | struct uart_omap_port *up = to_uart_omap_port(port); |
b612633b G |
725 | unsigned long flags = 0; |
726 | int retval; | |
727 | ||
728 | /* | |
729 | * Allocate the IRQ | |
730 | */ | |
731 | retval = request_irq(up->port.irq, serial_omap_irq, up->port.irqflags, | |
732 | up->name, up); | |
733 | if (retval) | |
734 | return retval; | |
735 | ||
2a0b965c TL |
736 | /* Optional wake-up IRQ */ |
737 | if (up->wakeirq) { | |
ee83bd3b | 738 | retval = dev_pm_set_dedicated_wake_irq(up->dev, up->wakeirq); |
2a0b965c TL |
739 | if (retval) { |
740 | free_irq(up->port.irq, up); | |
741 | return retval; | |
742 | } | |
2a0b965c TL |
743 | } |
744 | ||
ba77433d | 745 | dev_dbg(up->port.dev, "serial_omap_startup+%d\n", up->port.line); |
b612633b | 746 | |
d8ee4ea6 | 747 | pm_runtime_get_sync(up->dev); |
b612633b G |
748 | /* |
749 | * Clear the FIFO buffers and disable them. | |
750 | * (they will be reenabled in set_termios()) | |
751 | */ | |
752 | serial_omap_clear_fifos(up); | |
b612633b G |
753 | |
754 | /* | |
755 | * Clear the interrupt registers. | |
756 | */ | |
757 | (void) serial_in(up, UART_LSR); | |
758 | if (serial_in(up, UART_LSR) & UART_LSR_DR) | |
759 | (void) serial_in(up, UART_RX); | |
760 | (void) serial_in(up, UART_IIR); | |
761 | (void) serial_in(up, UART_MSR); | |
762 | ||
763 | /* | |
764 | * Now, initialize the UART | |
765 | */ | |
766 | serial_out(up, UART_LCR, UART_LCR_WLEN8); | |
767 | spin_lock_irqsave(&up->port.lock, flags); | |
768 | /* | |
769 | * Most PC uarts need OUT2 raised to enable interrupts. | |
770 | */ | |
771 | up->port.mctrl |= TIOCM_OUT2; | |
772 | serial_omap_set_mctrl(&up->port, up->port.mctrl); | |
773 | spin_unlock_irqrestore(&up->port.lock, flags); | |
774 | ||
775 | up->msr_saved_flags = 0; | |
b612633b G |
776 | /* |
777 | * Finally, enable interrupts. Note: Modem status interrupts | |
778 | * are set via set_termios(), which will be occurring imminently | |
779 | * anyway, so we don't enable them here. | |
780 | */ | |
781 | up->ier = UART_IER_RLSI | UART_IER_RDI; | |
782 | serial_out(up, UART_IER, up->ier); | |
783 | ||
78841462 | 784 | /* Enable module level wake up */ |
f64ffda6 G |
785 | up->wer = OMAP_UART_WER_MOD_WKUP; |
786 | if (up->features & OMAP_UART_WER_HAS_TX_WAKEUP) | |
787 | up->wer |= OMAP_UART_TX_WAKEUP_EN; | |
788 | ||
789 | serial_out(up, UART_OMAP_WER, up->wer); | |
78841462 | 790 | |
d8ee4ea6 FB |
791 | pm_runtime_mark_last_busy(up->dev); |
792 | pm_runtime_put_autosuspend(up->dev); | |
b612633b G |
793 | up->port_activity = jiffies; |
794 | return 0; | |
795 | } | |
796 | ||
797 | static void serial_omap_shutdown(struct uart_port *port) | |
798 | { | |
c990f351 | 799 | struct uart_omap_port *up = to_uart_omap_port(port); |
b612633b G |
800 | unsigned long flags = 0; |
801 | ||
ba77433d | 802 | dev_dbg(up->port.dev, "serial_omap_shutdown+%d\n", up->port.line); |
fcdca757 | 803 | |
d8ee4ea6 | 804 | pm_runtime_get_sync(up->dev); |
b612633b G |
805 | /* |
806 | * Disable interrupts from this port | |
807 | */ | |
808 | up->ier = 0; | |
809 | serial_out(up, UART_IER, 0); | |
810 | ||
811 | spin_lock_irqsave(&up->port.lock, flags); | |
812 | up->port.mctrl &= ~TIOCM_OUT2; | |
813 | serial_omap_set_mctrl(&up->port, up->port.mctrl); | |
814 | spin_unlock_irqrestore(&up->port.lock, flags); | |
815 | ||
816 | /* | |
817 | * Disable break condition and FIFOs | |
818 | */ | |
819 | serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC); | |
820 | serial_omap_clear_fifos(up); | |
821 | ||
822 | /* | |
823 | * Read data port to reset things, and then free the irq | |
824 | */ | |
825 | if (serial_in(up, UART_LSR) & UART_LSR_DR) | |
826 | (void) serial_in(up, UART_RX); | |
fcdca757 | 827 | |
660ac5f4 FB |
828 | pm_runtime_mark_last_busy(up->dev); |
829 | pm_runtime_put_autosuspend(up->dev); | |
b612633b | 830 | free_irq(up->port.irq, up); |
ee83bd3b | 831 | dev_pm_clear_wake_irq(up->dev); |
b612633b G |
832 | } |
833 | ||
2fd14964 G |
834 | static void serial_omap_uart_qos_work(struct work_struct *work) |
835 | { | |
836 | struct uart_omap_port *up = container_of(work, struct uart_omap_port, | |
837 | qos_work); | |
838 | ||
839 | pm_qos_update_request(&up->pm_qos_request, up->latency); | |
840 | } | |
841 | ||
b612633b G |
842 | static void |
843 | serial_omap_set_termios(struct uart_port *port, struct ktermios *termios, | |
844 | struct ktermios *old) | |
845 | { | |
c990f351 | 846 | struct uart_omap_port *up = to_uart_omap_port(port); |
b612633b | 847 | unsigned char cval = 0; |
b612633b G |
848 | unsigned long flags = 0; |
849 | unsigned int baud, quot; | |
850 | ||
851 | switch (termios->c_cflag & CSIZE) { | |
852 | case CS5: | |
853 | cval = UART_LCR_WLEN5; | |
854 | break; | |
855 | case CS6: | |
856 | cval = UART_LCR_WLEN6; | |
857 | break; | |
858 | case CS7: | |
859 | cval = UART_LCR_WLEN7; | |
860 | break; | |
861 | default: | |
862 | case CS8: | |
863 | cval = UART_LCR_WLEN8; | |
864 | break; | |
865 | } | |
866 | ||
867 | if (termios->c_cflag & CSTOPB) | |
868 | cval |= UART_LCR_STOP; | |
869 | if (termios->c_cflag & PARENB) | |
870 | cval |= UART_LCR_PARITY; | |
871 | if (!(termios->c_cflag & PARODD)) | |
872 | cval |= UART_LCR_EPAR; | |
fdbc7353 EBS |
873 | if (termios->c_cflag & CMSPAR) |
874 | cval |= UART_LCR_SPAR; | |
b612633b G |
875 | |
876 | /* | |
877 | * Ask the core to calculate the divisor for us. | |
878 | */ | |
879 | ||
880 | baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/13); | |
881 | quot = serial_omap_get_divisor(port, baud); | |
882 | ||
2fd14964 | 883 | /* calculate wakeup latency constraint */ |
19723452 | 884 | up->calc_latency = (USEC_PER_SEC * up->port.fifosize) / (baud / 8); |
2fd14964 G |
885 | up->latency = up->calc_latency; |
886 | schedule_work(&up->qos_work); | |
887 | ||
c538d20c G |
888 | up->dll = quot & 0xff; |
889 | up->dlh = quot >> 8; | |
890 | up->mdr1 = UART_OMAP_MDR1_DISABLE; | |
891 | ||
b612633b G |
892 | up->fcr = UART_FCR_R_TRIG_01 | UART_FCR_T_TRIG_01 | |
893 | UART_FCR_ENABLE_FIFO; | |
b612633b G |
894 | |
895 | /* | |
896 | * Ok, we're now changing the port state. Do it with | |
897 | * interrupts disabled. | |
898 | */ | |
d8ee4ea6 | 899 | pm_runtime_get_sync(up->dev); |
b612633b G |
900 | spin_lock_irqsave(&up->port.lock, flags); |
901 | ||
902 | /* | |
903 | * Update the per-port timeout. | |
904 | */ | |
905 | uart_update_timeout(port, termios->c_cflag, baud); | |
906 | ||
907 | up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR; | |
908 | if (termios->c_iflag & INPCK) | |
909 | up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE; | |
910 | if (termios->c_iflag & (BRKINT | PARMRK)) | |
911 | up->port.read_status_mask |= UART_LSR_BI; | |
912 | ||
913 | /* | |
914 | * Characters to ignore | |
915 | */ | |
916 | up->port.ignore_status_mask = 0; | |
917 | if (termios->c_iflag & IGNPAR) | |
918 | up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE; | |
919 | if (termios->c_iflag & IGNBRK) { | |
920 | up->port.ignore_status_mask |= UART_LSR_BI; | |
921 | /* | |
922 | * If we're ignoring parity and break indicators, | |
923 | * ignore overruns too (for real raw support). | |
924 | */ | |
925 | if (termios->c_iflag & IGNPAR) | |
926 | up->port.ignore_status_mask |= UART_LSR_OE; | |
927 | } | |
928 | ||
929 | /* | |
930 | * ignore all characters if CREAD is not set | |
931 | */ | |
932 | if ((termios->c_cflag & CREAD) == 0) | |
933 | up->port.ignore_status_mask |= UART_LSR_DR; | |
934 | ||
935 | /* | |
936 | * Modem status interrupts | |
937 | */ | |
938 | up->ier &= ~UART_IER_MSI; | |
939 | if (UART_ENABLE_MS(&up->port, termios->c_cflag)) | |
940 | up->ier |= UART_IER_MSI; | |
941 | serial_out(up, UART_IER, up->ier); | |
942 | serial_out(up, UART_LCR, cval); /* reset DLAB */ | |
c538d20c | 943 | up->lcr = cval; |
1776fd05 | 944 | up->scr = 0; |
b612633b G |
945 | |
946 | /* FIFOs and DMA Settings */ | |
947 | ||
948 | /* FCR can be changed only when the | |
949 | * baud clock is not running | |
950 | * DLL_REG and DLH_REG set to 0. | |
951 | */ | |
662b083a | 952 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); |
b612633b G |
953 | serial_out(up, UART_DLL, 0); |
954 | serial_out(up, UART_DLM, 0); | |
955 | serial_out(up, UART_LCR, 0); | |
956 | ||
662b083a | 957 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); |
b612633b | 958 | |
08bd4903 | 959 | up->efr = serial_in(up, UART_EFR) & ~UART_EFR_ECB; |
d864c03b | 960 | up->efr &= ~UART_EFR_SCD; |
b612633b G |
961 | serial_out(up, UART_EFR, up->efr | UART_EFR_ECB); |
962 | ||
662b083a | 963 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); |
08bd4903 | 964 | up->mcr = serial_in(up, UART_MCR) & ~UART_MCR_TCRTLR; |
b612633b G |
965 | serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR); |
966 | /* FIFO ENABLE, DMA MODE */ | |
0ba5f668 | 967 | |
1f663966 AP |
968 | up->scr |= OMAP_UART_SCR_RX_TRIG_GRANU1_MASK; |
969 | /* | |
970 | * NOTE: Setting OMAP_UART_SCR_RX_TRIG_GRANU1_MASK | |
971 | * sets Enables the granularity of 1 for TRIGGER RX | |
972 | * level. Along with setting RX FIFO trigger level | |
973 | * to 1 (as noted below, 16 characters) and TLR[3:0] | |
974 | * to zero this will result RX FIFO threshold level | |
975 | * to 1 character, instead of 16 as noted in comment | |
976 | * below. | |
977 | */ | |
978 | ||
6721ab7f | 979 | /* Set receive FIFO threshold to 16 characters and |
018e7448 | 980 | * transmit FIFO threshold to 32 spaces |
6721ab7f | 981 | */ |
49457430 | 982 | up->fcr &= ~OMAP_UART_FCR_RX_FIFO_TRIG_MASK; |
6721ab7f FB |
983 | up->fcr &= ~OMAP_UART_FCR_TX_FIFO_TRIG_MASK; |
984 | up->fcr |= UART_FCR6_R_TRIGGER_16 | UART_FCR6_T_TRIGGER_24 | | |
985 | UART_FCR_ENABLE_FIFO; | |
b612633b | 986 | |
0ba5f668 PW |
987 | serial_out(up, UART_FCR, up->fcr); |
988 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); | |
989 | ||
c538d20c G |
990 | serial_out(up, UART_OMAP_SCR, up->scr); |
991 | ||
08bd4903 | 992 | /* Reset UART_MCR_TCRTLR: this must be done with the EFR_ECB bit set */ |
662b083a | 993 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); |
b612633b | 994 | serial_out(up, UART_MCR, up->mcr); |
08bd4903 RK |
995 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); |
996 | serial_out(up, UART_EFR, up->efr); | |
997 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); | |
b612633b G |
998 | |
999 | /* Protocol, Baud Rate, and Interrupt Settings */ | |
1000 | ||
94734749 G |
1001 | if (up->errata & UART_ERRATA_i202_MDR1_ACCESS) |
1002 | serial_omap_mdr1_errataset(up, up->mdr1); | |
1003 | else | |
1004 | serial_out(up, UART_OMAP_MDR1, up->mdr1); | |
1005 | ||
662b083a | 1006 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); |
b612633b G |
1007 | serial_out(up, UART_EFR, up->efr | UART_EFR_ECB); |
1008 | ||
1009 | serial_out(up, UART_LCR, 0); | |
1010 | serial_out(up, UART_IER, 0); | |
662b083a | 1011 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); |
b612633b | 1012 | |
c538d20c G |
1013 | serial_out(up, UART_DLL, up->dll); /* LS of divisor */ |
1014 | serial_out(up, UART_DLM, up->dlh); /* MS of divisor */ | |
b612633b G |
1015 | |
1016 | serial_out(up, UART_LCR, 0); | |
1017 | serial_out(up, UART_IER, up->ier); | |
662b083a | 1018 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); |
b612633b G |
1019 | |
1020 | serial_out(up, UART_EFR, up->efr); | |
1021 | serial_out(up, UART_LCR, cval); | |
1022 | ||
5fe21236 | 1023 | if (!serial_omap_baud_is_mode16(port, baud)) |
c538d20c | 1024 | up->mdr1 = UART_OMAP_MDR1_13X_MODE; |
b612633b | 1025 | else |
c538d20c G |
1026 | up->mdr1 = UART_OMAP_MDR1_16X_MODE; |
1027 | ||
94734749 G |
1028 | if (up->errata & UART_ERRATA_i202_MDR1_ACCESS) |
1029 | serial_omap_mdr1_errataset(up, up->mdr1); | |
1030 | else | |
1031 | serial_out(up, UART_OMAP_MDR1, up->mdr1); | |
b612633b | 1032 | |
c533e51b | 1033 | /* Configure flow control */ |
c7d059ca | 1034 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); |
c533e51b RK |
1035 | |
1036 | /* XON1/XOFF1 accessible mode B, TCRTLR=0, ECB=0 */ | |
1037 | serial_out(up, UART_XON1, termios->c_cc[VSTART]); | |
1038 | serial_out(up, UART_XOFF1, termios->c_cc[VSTOP]); | |
1039 | ||
1040 | /* Enable access to TCR/TLR */ | |
c7d059ca RK |
1041 | serial_out(up, UART_EFR, up->efr | UART_EFR_ECB); |
1042 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); | |
1043 | serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR); | |
b612633b | 1044 | |
c7d059ca | 1045 | serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG); |
b612633b | 1046 | |
391f93f2 PH |
1047 | up->port.status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS | UPSTAT_AUTOXOFF); |
1048 | ||
c7d059ca | 1049 | if (termios->c_cflag & CRTSCTS && up->port.flags & UPF_HARD_FLOW) { |
348f9bb3 | 1050 | /* Enable AUTOCTS (autoRTS is enabled when RTS is raised) */ |
391f93f2 | 1051 | up->port.status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS; |
348f9bb3 | 1052 | up->efr |= UART_EFR_CTS; |
0d5b1663 RK |
1053 | } else { |
1054 | /* Disable AUTORTS and AUTOCTS */ | |
1055 | up->efr &= ~(UART_EFR_CTS | UART_EFR_RTS); | |
b612633b | 1056 | } |
b612633b | 1057 | |
01d70bb3 | 1058 | if (up->port.flags & UPF_SOFT_FLOW) { |
01d70bb3 RK |
1059 | /* clear SW control mode bits */ |
1060 | up->efr &= OMAP_UART_SW_CLR; | |
b612633b | 1061 | |
01d70bb3 RK |
1062 | /* |
1063 | * IXON Flag: | |
3af08bd7 RK |
1064 | * Enable XON/XOFF flow control on input. |
1065 | * Receiver compares XON1, XOFF1. | |
01d70bb3 RK |
1066 | */ |
1067 | if (termios->c_iflag & IXON) | |
3af08bd7 | 1068 | up->efr |= OMAP_UART_SW_RX; |
b612633b | 1069 | |
01d70bb3 RK |
1070 | /* |
1071 | * IXOFF Flag: | |
3af08bd7 RK |
1072 | * Enable XON/XOFF flow control on output. |
1073 | * Transmit XON1, XOFF1 | |
01d70bb3 | 1074 | */ |
391f93f2 PH |
1075 | if (termios->c_iflag & IXOFF) { |
1076 | up->port.status |= UPSTAT_AUTOXOFF; | |
3af08bd7 | 1077 | up->efr |= OMAP_UART_SW_TX; |
391f93f2 | 1078 | } |
b612633b | 1079 | |
01d70bb3 RK |
1080 | /* |
1081 | * IXANY Flag: | |
1082 | * Enable any character to restart output. | |
1083 | * Operation resumes after receiving any | |
1084 | * character after recognition of the XOFF character | |
1085 | */ | |
1086 | if (termios->c_iflag & IXANY) | |
1087 | up->mcr |= UART_MCR_XONANY; | |
1088 | else | |
1089 | up->mcr &= ~UART_MCR_XONANY; | |
b612633b | 1090 | } |
c7d059ca | 1091 | serial_out(up, UART_MCR, up->mcr); |
18f360f8 RK |
1092 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); |
1093 | serial_out(up, UART_EFR, up->efr); | |
1094 | serial_out(up, UART_LCR, up->lcr); | |
b612633b G |
1095 | |
1096 | serial_omap_set_mctrl(&up->port, up->port.mctrl); | |
b612633b G |
1097 | |
1098 | spin_unlock_irqrestore(&up->port.lock, flags); | |
660ac5f4 FB |
1099 | pm_runtime_mark_last_busy(up->dev); |
1100 | pm_runtime_put_autosuspend(up->dev); | |
ba77433d | 1101 | dev_dbg(up->port.dev, "serial_omap_set_termios+%d\n", up->port.line); |
b612633b G |
1102 | } |
1103 | ||
1104 | static void | |
1105 | serial_omap_pm(struct uart_port *port, unsigned int state, | |
1106 | unsigned int oldstate) | |
1107 | { | |
c990f351 | 1108 | struct uart_omap_port *up = to_uart_omap_port(port); |
b612633b G |
1109 | unsigned char efr; |
1110 | ||
ba77433d | 1111 | dev_dbg(up->port.dev, "serial_omap_pm+%d\n", up->port.line); |
fcdca757 | 1112 | |
d8ee4ea6 | 1113 | pm_runtime_get_sync(up->dev); |
662b083a | 1114 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); |
b612633b G |
1115 | efr = serial_in(up, UART_EFR); |
1116 | serial_out(up, UART_EFR, efr | UART_EFR_ECB); | |
1117 | serial_out(up, UART_LCR, 0); | |
1118 | ||
1119 | serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0); | |
662b083a | 1120 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); |
b612633b G |
1121 | serial_out(up, UART_EFR, efr); |
1122 | serial_out(up, UART_LCR, 0); | |
fcdca757 | 1123 | |
660ac5f4 FB |
1124 | pm_runtime_mark_last_busy(up->dev); |
1125 | pm_runtime_put_autosuspend(up->dev); | |
b612633b G |
1126 | } |
1127 | ||
1128 | static void serial_omap_release_port(struct uart_port *port) | |
1129 | { | |
1130 | dev_dbg(port->dev, "serial_omap_release_port+\n"); | |
1131 | } | |
1132 | ||
1133 | static int serial_omap_request_port(struct uart_port *port) | |
1134 | { | |
1135 | dev_dbg(port->dev, "serial_omap_request_port+\n"); | |
1136 | return 0; | |
1137 | } | |
1138 | ||
1139 | static void serial_omap_config_port(struct uart_port *port, int flags) | |
1140 | { | |
c990f351 | 1141 | struct uart_omap_port *up = to_uart_omap_port(port); |
b612633b G |
1142 | |
1143 | dev_dbg(up->port.dev, "serial_omap_config_port+%d\n", | |
ba77433d | 1144 | up->port.line); |
b612633b | 1145 | up->port.type = PORT_OMAP; |
3af08bd7 | 1146 | up->port.flags |= UPF_SOFT_FLOW | UPF_HARD_FLOW; |
b612633b G |
1147 | } |
1148 | ||
1149 | static int | |
1150 | serial_omap_verify_port(struct uart_port *port, struct serial_struct *ser) | |
1151 | { | |
1152 | /* we don't want the core code to modify any port params */ | |
1153 | dev_dbg(port->dev, "serial_omap_verify_port+\n"); | |
1154 | return -EINVAL; | |
1155 | } | |
1156 | ||
1157 | static const char * | |
1158 | serial_omap_type(struct uart_port *port) | |
1159 | { | |
c990f351 | 1160 | struct uart_omap_port *up = to_uart_omap_port(port); |
b612633b | 1161 | |
ba77433d | 1162 | dev_dbg(up->port.dev, "serial_omap_type+%d\n", up->port.line); |
b612633b G |
1163 | return up->name; |
1164 | } | |
1165 | ||
b612633b G |
1166 | #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE) |
1167 | ||
2172076d | 1168 | static void wait_for_xmitr(struct uart_omap_port *up) |
b612633b G |
1169 | { |
1170 | unsigned int status, tmout = 10000; | |
1171 | ||
1172 | /* Wait up to 10ms for the character(s) to be sent. */ | |
1173 | do { | |
1174 | status = serial_in(up, UART_LSR); | |
1175 | ||
1176 | if (status & UART_LSR_BI) | |
1177 | up->lsr_break_flag = UART_LSR_BI; | |
1178 | ||
1179 | if (--tmout == 0) | |
1180 | break; | |
1181 | udelay(1); | |
1182 | } while ((status & BOTH_EMPTY) != BOTH_EMPTY); | |
1183 | ||
1184 | /* Wait up to 1s for flow control if necessary */ | |
1185 | if (up->port.flags & UPF_CONS_FLOW) { | |
1186 | tmout = 1000000; | |
1187 | for (tmout = 1000000; tmout; tmout--) { | |
1188 | unsigned int msr = serial_in(up, UART_MSR); | |
1189 | ||
1190 | up->msr_saved_flags |= msr & MSR_SAVE_FLAGS; | |
1191 | if (msr & UART_MSR_CTS) | |
1192 | break; | |
1193 | ||
1194 | udelay(1); | |
1195 | } | |
1196 | } | |
1197 | } | |
1198 | ||
1b41dbc1 CC |
1199 | #ifdef CONFIG_CONSOLE_POLL |
1200 | ||
1201 | static void serial_omap_poll_put_char(struct uart_port *port, unsigned char ch) | |
1202 | { | |
c990f351 | 1203 | struct uart_omap_port *up = to_uart_omap_port(port); |
fcdca757 | 1204 | |
d8ee4ea6 | 1205 | pm_runtime_get_sync(up->dev); |
1b41dbc1 CC |
1206 | wait_for_xmitr(up); |
1207 | serial_out(up, UART_TX, ch); | |
660ac5f4 FB |
1208 | pm_runtime_mark_last_busy(up->dev); |
1209 | pm_runtime_put_autosuspend(up->dev); | |
1b41dbc1 CC |
1210 | } |
1211 | ||
1212 | static int serial_omap_poll_get_char(struct uart_port *port) | |
1213 | { | |
c990f351 | 1214 | struct uart_omap_port *up = to_uart_omap_port(port); |
fcdca757 | 1215 | unsigned int status; |
1b41dbc1 | 1216 | |
d8ee4ea6 | 1217 | pm_runtime_get_sync(up->dev); |
fcdca757 | 1218 | status = serial_in(up, UART_LSR); |
a6b19c33 FB |
1219 | if (!(status & UART_LSR_DR)) { |
1220 | status = NO_POLL_CHAR; | |
1221 | goto out; | |
1222 | } | |
1b41dbc1 | 1223 | |
fcdca757 | 1224 | status = serial_in(up, UART_RX); |
a6b19c33 FB |
1225 | |
1226 | out: | |
660ac5f4 FB |
1227 | pm_runtime_mark_last_busy(up->dev); |
1228 | pm_runtime_put_autosuspend(up->dev); | |
a6b19c33 | 1229 | |
fcdca757 | 1230 | return status; |
1b41dbc1 CC |
1231 | } |
1232 | ||
1233 | #endif /* CONFIG_CONSOLE_POLL */ | |
1234 | ||
1235 | #ifdef CONFIG_SERIAL_OMAP_CONSOLE | |
1236 | ||
40477d0e | 1237 | static struct uart_omap_port *serial_omap_console_ports[OMAP_MAX_HSUART_PORTS]; |
1b41dbc1 CC |
1238 | |
1239 | static struct uart_driver serial_omap_reg; | |
1240 | ||
b612633b G |
1241 | static void serial_omap_console_putchar(struct uart_port *port, int ch) |
1242 | { | |
c990f351 | 1243 | struct uart_omap_port *up = to_uart_omap_port(port); |
b612633b G |
1244 | |
1245 | wait_for_xmitr(up); | |
1246 | serial_out(up, UART_TX, ch); | |
1247 | } | |
1248 | ||
1249 | static void | |
1250 | serial_omap_console_write(struct console *co, const char *s, | |
1251 | unsigned int count) | |
1252 | { | |
1253 | struct uart_omap_port *up = serial_omap_console_ports[co->index]; | |
1254 | unsigned long flags; | |
1255 | unsigned int ier; | |
1256 | int locked = 1; | |
1257 | ||
d8ee4ea6 | 1258 | pm_runtime_get_sync(up->dev); |
fcdca757 | 1259 | |
b612633b G |
1260 | local_irq_save(flags); |
1261 | if (up->port.sysrq) | |
1262 | locked = 0; | |
1263 | else if (oops_in_progress) | |
1264 | locked = spin_trylock(&up->port.lock); | |
1265 | else | |
1266 | spin_lock(&up->port.lock); | |
1267 | ||
1268 | /* | |
1269 | * First save the IER then disable the interrupts | |
1270 | */ | |
1271 | ier = serial_in(up, UART_IER); | |
1272 | serial_out(up, UART_IER, 0); | |
1273 | ||
1274 | uart_console_write(&up->port, s, count, serial_omap_console_putchar); | |
1275 | ||
1276 | /* | |
1277 | * Finally, wait for transmitter to become empty | |
1278 | * and restore the IER | |
1279 | */ | |
1280 | wait_for_xmitr(up); | |
1281 | serial_out(up, UART_IER, ier); | |
1282 | /* | |
1283 | * The receive handling will happen properly because the | |
1284 | * receive ready bit will still be set; it is not cleared | |
1285 | * on read. However, modem control will not, we must | |
1286 | * call it if we have saved something in the saved flags | |
1287 | * while processing with interrupts off. | |
1288 | */ | |
1289 | if (up->msr_saved_flags) | |
1290 | check_modem_status(up); | |
1291 | ||
d8ee4ea6 FB |
1292 | pm_runtime_mark_last_busy(up->dev); |
1293 | pm_runtime_put_autosuspend(up->dev); | |
b612633b G |
1294 | if (locked) |
1295 | spin_unlock(&up->port.lock); | |
1296 | local_irq_restore(flags); | |
1297 | } | |
1298 | ||
1299 | static int __init | |
1300 | serial_omap_console_setup(struct console *co, char *options) | |
1301 | { | |
1302 | struct uart_omap_port *up; | |
1303 | int baud = 115200; | |
1304 | int bits = 8; | |
1305 | int parity = 'n'; | |
1306 | int flow = 'n'; | |
1307 | ||
1308 | if (serial_omap_console_ports[co->index] == NULL) | |
1309 | return -ENODEV; | |
1310 | up = serial_omap_console_ports[co->index]; | |
1311 | ||
1312 | if (options) | |
1313 | uart_parse_options(options, &baud, &parity, &bits, &flow); | |
1314 | ||
1315 | return uart_set_options(&up->port, co, baud, parity, bits, flow); | |
1316 | } | |
1317 | ||
1318 | static struct console serial_omap_console = { | |
1319 | .name = OMAP_SERIAL_NAME, | |
1320 | .write = serial_omap_console_write, | |
1321 | .device = uart_console_device, | |
1322 | .setup = serial_omap_console_setup, | |
1323 | .flags = CON_PRINTBUFFER, | |
1324 | .index = -1, | |
1325 | .data = &serial_omap_reg, | |
1326 | }; | |
1327 | ||
1328 | static void serial_omap_add_console_port(struct uart_omap_port *up) | |
1329 | { | |
ba77433d | 1330 | serial_omap_console_ports[up->port.line] = up; |
b612633b G |
1331 | } |
1332 | ||
1333 | #define OMAP_CONSOLE (&serial_omap_console) | |
1334 | ||
1335 | #else | |
1336 | ||
1337 | #define OMAP_CONSOLE NULL | |
1338 | ||
1339 | static inline void serial_omap_add_console_port(struct uart_omap_port *up) | |
1340 | {} | |
1341 | ||
1342 | #endif | |
1343 | ||
4a0ac0f5 | 1344 | /* Enable or disable the rs485 support */ |
dadd7ecb | 1345 | static int |
4a0ac0f5 MJ |
1346 | serial_omap_config_rs485(struct uart_port *port, struct serial_rs485 *rs485conf) |
1347 | { | |
1348 | struct uart_omap_port *up = to_uart_omap_port(port); | |
4a0ac0f5 MJ |
1349 | unsigned int mode; |
1350 | int val; | |
1351 | ||
1352 | pm_runtime_get_sync(up->dev); | |
4a0ac0f5 | 1353 | |
4a0ac0f5 MJ |
1354 | /* Disable interrupts from this port */ |
1355 | mode = up->ier; | |
1356 | up->ier = 0; | |
1357 | serial_out(up, UART_IER, 0); | |
1358 | ||
1359 | /* store new config */ | |
dadd7ecb | 1360 | port->rs485 = *rs485conf; |
4a0ac0f5 MJ |
1361 | |
1362 | /* | |
1363 | * Just as a precaution, only allow rs485 | |
1364 | * to be enabled if the gpio pin is valid | |
1365 | */ | |
1366 | if (gpio_is_valid(up->rts_gpio)) { | |
1367 | /* enable / disable rts */ | |
dadd7ecb | 1368 | val = (port->rs485.flags & SER_RS485_ENABLED) ? |
4a0ac0f5 | 1369 | SER_RS485_RTS_AFTER_SEND : SER_RS485_RTS_ON_SEND; |
dadd7ecb | 1370 | val = (port->rs485.flags & val) ? 1 : 0; |
4a0ac0f5 MJ |
1371 | gpio_set_value(up->rts_gpio, val); |
1372 | } else | |
dadd7ecb | 1373 | port->rs485.flags &= ~SER_RS485_ENABLED; |
4a0ac0f5 MJ |
1374 | |
1375 | /* Enable interrupts */ | |
1376 | up->ier = mode; | |
1377 | serial_out(up, UART_IER, up->ier); | |
1378 | ||
018e7448 PP |
1379 | /* If RS-485 is disabled, make sure the THR interrupt is fired when |
1380 | * TX FIFO is below the trigger level. | |
1381 | */ | |
dadd7ecb | 1382 | if (!(port->rs485.flags & SER_RS485_ENABLED) && |
018e7448 PP |
1383 | (up->scr & OMAP_UART_SCR_TX_EMPTY)) { |
1384 | up->scr &= ~OMAP_UART_SCR_TX_EMPTY; | |
1385 | serial_out(up, UART_OMAP_SCR, up->scr); | |
1386 | } | |
1387 | ||
4a0ac0f5 MJ |
1388 | pm_runtime_mark_last_busy(up->dev); |
1389 | pm_runtime_put_autosuspend(up->dev); | |
4a0ac0f5 | 1390 | |
4a0ac0f5 MJ |
1391 | return 0; |
1392 | } | |
1393 | ||
b612633b G |
1394 | static struct uart_ops serial_omap_pops = { |
1395 | .tx_empty = serial_omap_tx_empty, | |
1396 | .set_mctrl = serial_omap_set_mctrl, | |
1397 | .get_mctrl = serial_omap_get_mctrl, | |
1398 | .stop_tx = serial_omap_stop_tx, | |
1399 | .start_tx = serial_omap_start_tx, | |
3af08bd7 RK |
1400 | .throttle = serial_omap_throttle, |
1401 | .unthrottle = serial_omap_unthrottle, | |
b612633b G |
1402 | .stop_rx = serial_omap_stop_rx, |
1403 | .enable_ms = serial_omap_enable_ms, | |
1404 | .break_ctl = serial_omap_break_ctl, | |
1405 | .startup = serial_omap_startup, | |
1406 | .shutdown = serial_omap_shutdown, | |
1407 | .set_termios = serial_omap_set_termios, | |
1408 | .pm = serial_omap_pm, | |
1409 | .type = serial_omap_type, | |
1410 | .release_port = serial_omap_release_port, | |
1411 | .request_port = serial_omap_request_port, | |
1412 | .config_port = serial_omap_config_port, | |
1413 | .verify_port = serial_omap_verify_port, | |
1b41dbc1 CC |
1414 | #ifdef CONFIG_CONSOLE_POLL |
1415 | .poll_put_char = serial_omap_poll_put_char, | |
1416 | .poll_get_char = serial_omap_poll_get_char, | |
1417 | #endif | |
b612633b G |
1418 | }; |
1419 | ||
1420 | static struct uart_driver serial_omap_reg = { | |
1421 | .owner = THIS_MODULE, | |
1422 | .driver_name = "OMAP-SERIAL", | |
1423 | .dev_name = OMAP_SERIAL_NAME, | |
1424 | .nr = OMAP_MAX_HSUART_PORTS, | |
1425 | .cons = OMAP_CONSOLE, | |
1426 | }; | |
1427 | ||
3bc4f0d8 | 1428 | #ifdef CONFIG_PM_SLEEP |
ddd85e22 SP |
1429 | static int serial_omap_prepare(struct device *dev) |
1430 | { | |
1431 | struct uart_omap_port *up = dev_get_drvdata(dev); | |
1432 | ||
1433 | up->is_suspending = true; | |
1434 | ||
1435 | return 0; | |
1436 | } | |
1437 | ||
1438 | static void serial_omap_complete(struct device *dev) | |
1439 | { | |
1440 | struct uart_omap_port *up = dev_get_drvdata(dev); | |
1441 | ||
1442 | up->is_suspending = false; | |
1443 | } | |
1444 | ||
fcdca757 | 1445 | static int serial_omap_suspend(struct device *dev) |
b612633b | 1446 | { |
fcdca757 | 1447 | struct uart_omap_port *up = dev_get_drvdata(dev); |
b612633b | 1448 | |
ac57e7f3 | 1449 | uart_suspend_port(&serial_omap_reg, &up->port); |
033d9959 | 1450 | flush_work(&up->qos_work); |
2fd14964 | 1451 | |
d758c9c1 TL |
1452 | if (device_may_wakeup(dev)) |
1453 | serial_omap_enable_wakeup(up, true); | |
1454 | else | |
1455 | serial_omap_enable_wakeup(up, false); | |
1456 | ||
b612633b G |
1457 | return 0; |
1458 | } | |
1459 | ||
fcdca757 | 1460 | static int serial_omap_resume(struct device *dev) |
b612633b | 1461 | { |
fcdca757 | 1462 | struct uart_omap_port *up = dev_get_drvdata(dev); |
b612633b | 1463 | |
d758c9c1 TL |
1464 | if (device_may_wakeup(dev)) |
1465 | serial_omap_enable_wakeup(up, false); | |
1466 | ||
ac57e7f3 SP |
1467 | uart_resume_port(&serial_omap_reg, &up->port); |
1468 | ||
b612633b G |
1469 | return 0; |
1470 | } | |
ddd85e22 SP |
1471 | #else |
1472 | #define serial_omap_prepare NULL | |
2cb5a2fa | 1473 | #define serial_omap_complete NULL |
ddd85e22 | 1474 | #endif /* CONFIG_PM_SLEEP */ |
b612633b | 1475 | |
9671f099 | 1476 | static void omap_serial_fill_features_erratas(struct uart_omap_port *up) |
7c77c8de G |
1477 | { |
1478 | u32 mvr, scheme; | |
1479 | u16 revision, major, minor; | |
1480 | ||
76bac198 | 1481 | mvr = readl(up->port.membase + (UART_OMAP_MVER << up->port.regshift)); |
7c77c8de G |
1482 | |
1483 | /* Check revision register scheme */ | |
1484 | scheme = mvr >> OMAP_UART_MVR_SCHEME_SHIFT; | |
1485 | ||
1486 | switch (scheme) { | |
1487 | case 0: /* Legacy Scheme: OMAP2/3 */ | |
1488 | /* MINOR_REV[0:4], MAJOR_REV[4:7] */ | |
1489 | major = (mvr & OMAP_UART_LEGACY_MVR_MAJ_MASK) >> | |
1490 | OMAP_UART_LEGACY_MVR_MAJ_SHIFT; | |
1491 | minor = (mvr & OMAP_UART_LEGACY_MVR_MIN_MASK); | |
1492 | break; | |
1493 | case 1: | |
1494 | /* New Scheme: OMAP4+ */ | |
1495 | /* MINOR_REV[0:5], MAJOR_REV[8:10] */ | |
1496 | major = (mvr & OMAP_UART_MVR_MAJ_MASK) >> | |
1497 | OMAP_UART_MVR_MAJ_SHIFT; | |
1498 | minor = (mvr & OMAP_UART_MVR_MIN_MASK); | |
1499 | break; | |
1500 | default: | |
d8ee4ea6 | 1501 | dev_warn(up->dev, |
7c77c8de G |
1502 | "Unknown %s revision, defaulting to highest\n", |
1503 | up->name); | |
1504 | /* highest possible revision */ | |
1505 | major = 0xff; | |
1506 | minor = 0xff; | |
1507 | } | |
1508 | ||
1509 | /* normalize revision for the driver */ | |
1510 | revision = UART_BUILD_REVISION(major, minor); | |
1511 | ||
1512 | switch (revision) { | |
1513 | case OMAP_UART_REV_46: | |
1514 | up->errata |= (UART_ERRATA_i202_MDR1_ACCESS | | |
1515 | UART_ERRATA_i291_DMA_FORCEIDLE); | |
1516 | break; | |
1517 | case OMAP_UART_REV_52: | |
1518 | up->errata |= (UART_ERRATA_i202_MDR1_ACCESS | | |
1519 | UART_ERRATA_i291_DMA_FORCEIDLE); | |
f64ffda6 | 1520 | up->features |= OMAP_UART_WER_HAS_TX_WAKEUP; |
7c77c8de G |
1521 | break; |
1522 | case OMAP_UART_REV_63: | |
1523 | up->errata |= UART_ERRATA_i202_MDR1_ACCESS; | |
f64ffda6 | 1524 | up->features |= OMAP_UART_WER_HAS_TX_WAKEUP; |
7c77c8de G |
1525 | break; |
1526 | default: | |
1527 | break; | |
1528 | } | |
1529 | } | |
1530 | ||
9671f099 | 1531 | static struct omap_uart_port_info *of_get_uart_port_info(struct device *dev) |
d92b0dfc RN |
1532 | { |
1533 | struct omap_uart_port_info *omap_up_info; | |
1534 | ||
1535 | omap_up_info = devm_kzalloc(dev, sizeof(*omap_up_info), GFP_KERNEL); | |
1536 | if (!omap_up_info) | |
1537 | return NULL; /* out of memory */ | |
1538 | ||
1539 | of_property_read_u32(dev->of_node, "clock-frequency", | |
1540 | &omap_up_info->uartclk); | |
1541 | return omap_up_info; | |
1542 | } | |
1543 | ||
4a0ac0f5 MJ |
1544 | static int serial_omap_probe_rs485(struct uart_omap_port *up, |
1545 | struct device_node *np) | |
1546 | { | |
dadd7ecb | 1547 | struct serial_rs485 *rs485conf = &up->port.rs485; |
4a0ac0f5 MJ |
1548 | u32 rs485_delay[2]; |
1549 | enum of_gpio_flags flags; | |
1550 | int ret; | |
1551 | ||
1552 | rs485conf->flags = 0; | |
1553 | up->rts_gpio = -EINVAL; | |
1554 | ||
1555 | if (!np) | |
1556 | return 0; | |
1557 | ||
1558 | if (of_property_read_bool(np, "rs485-rts-active-high")) | |
1559 | rs485conf->flags |= SER_RS485_RTS_ON_SEND; | |
1560 | else | |
1561 | rs485conf->flags |= SER_RS485_RTS_AFTER_SEND; | |
1562 | ||
1563 | /* check for tx enable gpio */ | |
1564 | up->rts_gpio = of_get_named_gpio_flags(np, "rts-gpio", 0, &flags); | |
1565 | if (gpio_is_valid(up->rts_gpio)) { | |
404dc57c | 1566 | ret = devm_gpio_request(up->dev, up->rts_gpio, "omap-serial"); |
4a0ac0f5 MJ |
1567 | if (ret < 0) |
1568 | return ret; | |
1569 | ret = gpio_direction_output(up->rts_gpio, | |
1570 | flags & SER_RS485_RTS_AFTER_SEND); | |
1571 | if (ret < 0) | |
1572 | return ret; | |
a64c1a1c MG |
1573 | } else if (up->rts_gpio == -EPROBE_DEFER) { |
1574 | return -EPROBE_DEFER; | |
1575 | } else { | |
4a0ac0f5 | 1576 | up->rts_gpio = -EINVAL; |
a64c1a1c | 1577 | } |
4a0ac0f5 MJ |
1578 | |
1579 | if (of_property_read_u32_array(np, "rs485-rts-delay", | |
1580 | rs485_delay, 2) == 0) { | |
1581 | rs485conf->delay_rts_before_send = rs485_delay[0]; | |
1582 | rs485conf->delay_rts_after_send = rs485_delay[1]; | |
1583 | } | |
1584 | ||
1585 | if (of_property_read_bool(np, "rs485-rx-during-tx")) | |
1586 | rs485conf->flags |= SER_RS485_RX_DURING_TX; | |
1587 | ||
1588 | if (of_property_read_bool(np, "linux,rs485-enabled-at-boot-time")) | |
1589 | rs485conf->flags |= SER_RS485_ENABLED; | |
1590 | ||
1591 | return 0; | |
1592 | } | |
1593 | ||
9671f099 | 1594 | static int serial_omap_probe(struct platform_device *pdev) |
b612633b | 1595 | { |
574de559 | 1596 | struct omap_uart_port_info *omap_up_info = dev_get_platdata(&pdev->dev); |
cc51638a FB |
1597 | struct uart_omap_port *up; |
1598 | struct resource *mem; | |
d044d235 | 1599 | void __iomem *base; |
cc51638a FB |
1600 | int uartirq = 0; |
1601 | int wakeirq = 0; | |
1602 | int ret; | |
b612633b | 1603 | |
2a0b965c | 1604 | /* The optional wakeirq may be specified in the board dts file */ |
a0a490f9 | 1605 | if (pdev->dev.of_node) { |
2a0b965c TL |
1606 | uartirq = irq_of_parse_and_map(pdev->dev.of_node, 0); |
1607 | if (!uartirq) | |
1608 | return -EPROBE_DEFER; | |
1609 | wakeirq = irq_of_parse_and_map(pdev->dev.of_node, 1); | |
d92b0dfc | 1610 | omap_up_info = of_get_uart_port_info(&pdev->dev); |
a0a490f9 | 1611 | pdev->dev.platform_data = omap_up_info; |
2a0b965c | 1612 | } else { |
54af692c FB |
1613 | uartirq = platform_get_irq(pdev, 0); |
1614 | if (uartirq < 0) | |
1615 | return -EPROBE_DEFER; | |
a0a490f9 | 1616 | } |
d92b0dfc | 1617 | |
d044d235 FB |
1618 | up = devm_kzalloc(&pdev->dev, sizeof(*up), GFP_KERNEL); |
1619 | if (!up) | |
1620 | return -ENOMEM; | |
b612633b | 1621 | |
d044d235 FB |
1622 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1623 | base = devm_ioremap_resource(&pdev->dev, mem); | |
1624 | if (IS_ERR(base)) | |
1625 | return PTR_ERR(base); | |
b612633b | 1626 | |
d8ee4ea6 | 1627 | up->dev = &pdev->dev; |
b612633b G |
1628 | up->port.dev = &pdev->dev; |
1629 | up->port.type = PORT_OMAP; | |
1630 | up->port.iotype = UPIO_MEM; | |
2a0b965c | 1631 | up->port.irq = uartirq; |
b612633b G |
1632 | up->port.regshift = 2; |
1633 | up->port.fifosize = 64; | |
1634 | up->port.ops = &serial_omap_pops; | |
b612633b | 1635 | |
d92b0dfc | 1636 | if (pdev->dev.of_node) |
3c59958d | 1637 | ret = of_alias_get_id(pdev->dev.of_node, "serial"); |
d92b0dfc | 1638 | else |
3c59958d | 1639 | ret = pdev->id; |
d92b0dfc | 1640 | |
3c59958d | 1641 | if (ret < 0) { |
d92b0dfc | 1642 | dev_err(&pdev->dev, "failed to get alias/pdev id, errno %d\n", |
3c59958d | 1643 | ret); |
388bc262 | 1644 | goto err_port_line; |
d92b0dfc | 1645 | } |
3c59958d | 1646 | up->port.line = ret; |
d92b0dfc | 1647 | |
7af0ea5d NM |
1648 | if (up->port.line >= OMAP_MAX_HSUART_PORTS) { |
1649 | dev_err(&pdev->dev, "uart ID %d > MAX %d.\n", up->port.line, | |
1650 | OMAP_MAX_HSUART_PORTS); | |
1651 | ret = -ENXIO; | |
1652 | goto err_port_line; | |
1653 | } | |
1654 | ||
1cf94d3a DK |
1655 | up->wakeirq = wakeirq; |
1656 | if (!up->wakeirq) | |
1657 | dev_info(up->port.dev, "no wakeirq for uart%d\n", | |
1658 | up->port.line); | |
1659 | ||
4a0ac0f5 MJ |
1660 | ret = serial_omap_probe_rs485(up, pdev->dev.of_node); |
1661 | if (ret < 0) | |
1662 | goto err_rs485; | |
1663 | ||
d92b0dfc | 1664 | sprintf(up->name, "OMAP UART%d", up->port.line); |
edd70ad7 | 1665 | up->port.mapbase = mem->start; |
d044d235 | 1666 | up->port.membase = base; |
b612633b | 1667 | up->port.flags = omap_up_info->flags; |
b612633b | 1668 | up->port.uartclk = omap_up_info->uartclk; |
dadd7ecb | 1669 | up->port.rs485_config = serial_omap_config_rs485; |
8fe789dc RN |
1670 | if (!up->port.uartclk) { |
1671 | up->port.uartclk = DEFAULT_CLK_SPEED; | |
e5f9bf72 | 1672 | dev_warn(&pdev->dev, |
80d8611d | 1673 | "No clock speed specified: using default: %d\n", |
e5f9bf72 | 1674 | DEFAULT_CLK_SPEED); |
8fe789dc | 1675 | } |
b612633b | 1676 | |
2fd14964 G |
1677 | up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE; |
1678 | up->calc_latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE; | |
1679 | pm_qos_add_request(&up->pm_qos_request, | |
1680 | PM_QOS_CPU_DMA_LATENCY, up->latency); | |
2fd14964 G |
1681 | INIT_WORK(&up->qos_work, serial_omap_uart_qos_work); |
1682 | ||
93220dcc | 1683 | platform_set_drvdata(pdev, up); |
a630fbfb TL |
1684 | if (omap_up_info->autosuspend_timeout == 0) |
1685 | omap_up_info->autosuspend_timeout = -1; | |
5b6acc79 | 1686 | |
a630fbfb | 1687 | device_init_wakeup(up->dev, true); |
fcdca757 G |
1688 | pm_runtime_use_autosuspend(&pdev->dev); |
1689 | pm_runtime_set_autosuspend_delay(&pdev->dev, | |
c86845db | 1690 | omap_up_info->autosuspend_timeout); |
fcdca757 G |
1691 | |
1692 | pm_runtime_irq_safe(&pdev->dev); | |
3026d14a GS |
1693 | pm_runtime_enable(&pdev->dev); |
1694 | ||
fcdca757 G |
1695 | pm_runtime_get_sync(&pdev->dev); |
1696 | ||
7c77c8de G |
1697 | omap_serial_fill_features_erratas(up); |
1698 | ||
ba77433d | 1699 | ui[up->port.line] = up; |
b612633b G |
1700 | serial_omap_add_console_port(up); |
1701 | ||
1702 | ret = uart_add_one_port(&serial_omap_reg, &up->port); | |
1703 | if (ret != 0) | |
388bc262 | 1704 | goto err_add_port; |
b612633b | 1705 | |
660ac5f4 FB |
1706 | pm_runtime_mark_last_busy(up->dev); |
1707 | pm_runtime_put_autosuspend(up->dev); | |
b612633b | 1708 | return 0; |
388bc262 S |
1709 | |
1710 | err_add_port: | |
1711 | pm_runtime_put(&pdev->dev); | |
1712 | pm_runtime_disable(&pdev->dev); | |
66cf1d84 SP |
1713 | pm_qos_remove_request(&up->pm_qos_request); |
1714 | device_init_wakeup(up->dev, false); | |
4a0ac0f5 | 1715 | err_rs485: |
388bc262 | 1716 | err_port_line: |
b612633b G |
1717 | return ret; |
1718 | } | |
1719 | ||
ae8d8a14 | 1720 | static int serial_omap_remove(struct platform_device *dev) |
b612633b G |
1721 | { |
1722 | struct uart_omap_port *up = platform_get_drvdata(dev); | |
1723 | ||
7e9c8e7d | 1724 | pm_runtime_put_sync(up->dev); |
1b42c8b2 FB |
1725 | pm_runtime_disable(up->dev); |
1726 | uart_remove_one_port(&serial_omap_reg, &up->port); | |
1727 | pm_qos_remove_request(&up->pm_qos_request); | |
93a2e470 | 1728 | device_init_wakeup(&dev->dev, false); |
fcdca757 | 1729 | |
fcdca757 G |
1730 | return 0; |
1731 | } | |
1732 | ||
94734749 G |
1733 | /* |
1734 | * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460) | |
1735 | * The access to uart register after MDR1 Access | |
1736 | * causes UART to corrupt data. | |
1737 | * | |
1738 | * Need a delay = | |
1739 | * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS) | |
1740 | * give 10 times as much | |
1741 | */ | |
1742 | static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1) | |
1743 | { | |
1744 | u8 timeout = 255; | |
1745 | ||
1746 | serial_out(up, UART_OMAP_MDR1, mdr1); | |
1747 | udelay(2); | |
1748 | serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT | | |
1749 | UART_FCR_CLEAR_RCVR); | |
1750 | /* | |
1751 | * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and | |
1752 | * TX_FIFO_E bit is 1. | |
1753 | */ | |
1754 | while (UART_LSR_THRE != (serial_in(up, UART_LSR) & | |
1755 | (UART_LSR_THRE | UART_LSR_DR))) { | |
1756 | timeout--; | |
1757 | if (!timeout) { | |
1758 | /* Should *never* happen. we warn and carry on */ | |
d8ee4ea6 | 1759 | dev_crit(up->dev, "Errata i202: timedout %x\n", |
94734749 G |
1760 | serial_in(up, UART_LSR)); |
1761 | break; | |
1762 | } | |
1763 | udelay(1); | |
1764 | } | |
1765 | } | |
1766 | ||
d39fe4e5 | 1767 | #ifdef CONFIG_PM |
9f9ac1e8 G |
1768 | static void serial_omap_restore_context(struct uart_omap_port *up) |
1769 | { | |
94734749 G |
1770 | if (up->errata & UART_ERRATA_i202_MDR1_ACCESS) |
1771 | serial_omap_mdr1_errataset(up, UART_OMAP_MDR1_DISABLE); | |
1772 | else | |
1773 | serial_out(up, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE); | |
1774 | ||
9f9ac1e8 G |
1775 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */ |
1776 | serial_out(up, UART_EFR, UART_EFR_ECB); | |
1777 | serial_out(up, UART_LCR, 0x0); /* Operational mode */ | |
1778 | serial_out(up, UART_IER, 0x0); | |
1779 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */ | |
c538d20c G |
1780 | serial_out(up, UART_DLL, up->dll); |
1781 | serial_out(up, UART_DLM, up->dlh); | |
9f9ac1e8 G |
1782 | serial_out(up, UART_LCR, 0x0); /* Operational mode */ |
1783 | serial_out(up, UART_IER, up->ier); | |
1784 | serial_out(up, UART_FCR, up->fcr); | |
1785 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); | |
1786 | serial_out(up, UART_MCR, up->mcr); | |
1787 | serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */ | |
c538d20c | 1788 | serial_out(up, UART_OMAP_SCR, up->scr); |
9f9ac1e8 G |
1789 | serial_out(up, UART_EFR, up->efr); |
1790 | serial_out(up, UART_LCR, up->lcr); | |
94734749 G |
1791 | if (up->errata & UART_ERRATA_i202_MDR1_ACCESS) |
1792 | serial_omap_mdr1_errataset(up, up->mdr1); | |
1793 | else | |
1794 | serial_out(up, UART_OMAP_MDR1, up->mdr1); | |
f64ffda6 | 1795 | serial_out(up, UART_OMAP_WER, up->wer); |
9f9ac1e8 G |
1796 | } |
1797 | ||
fcdca757 G |
1798 | static int serial_omap_runtime_suspend(struct device *dev) |
1799 | { | |
ec3bebc6 | 1800 | struct uart_omap_port *up = dev_get_drvdata(dev); |
ec3bebc6 | 1801 | |
7f25301d WY |
1802 | if (!up) |
1803 | return -EINVAL; | |
1804 | ||
ddd85e22 SP |
1805 | /* |
1806 | * When using 'no_console_suspend', the console UART must not be | |
1807 | * suspended. Since driver suspend is managed by runtime suspend, | |
1808 | * preventing runtime suspend (by returning error) will keep device | |
1809 | * active during suspend. | |
1810 | */ | |
1811 | if (up->is_suspending && !console_suspend_enabled && | |
1812 | uart_console(&up->port)) | |
1813 | return -EBUSY; | |
1814 | ||
e5b57c03 | 1815 | up->context_loss_cnt = serial_omap_get_context_loss_count(up); |
ec3bebc6 | 1816 | |
d758c9c1 | 1817 | serial_omap_enable_wakeup(up, true); |
62f3ec5f | 1818 | |
2fd14964 G |
1819 | up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE; |
1820 | schedule_work(&up->qos_work); | |
1821 | ||
b612633b G |
1822 | return 0; |
1823 | } | |
1824 | ||
fcdca757 G |
1825 | static int serial_omap_runtime_resume(struct device *dev) |
1826 | { | |
9f9ac1e8 G |
1827 | struct uart_omap_port *up = dev_get_drvdata(dev); |
1828 | ||
39aee51d | 1829 | int loss_cnt = serial_omap_get_context_loss_count(up); |
ec3bebc6 | 1830 | |
d758c9c1 TL |
1831 | serial_omap_enable_wakeup(up, false); |
1832 | ||
39aee51d | 1833 | if (loss_cnt < 0) { |
a630fbfb | 1834 | dev_dbg(dev, "serial_omap_get_context_loss_count failed : %d\n", |
39aee51d | 1835 | loss_cnt); |
ac57e7f3 | 1836 | serial_omap_restore_context(up); |
39aee51d S |
1837 | } else if (up->context_loss_cnt != loss_cnt) { |
1838 | serial_omap_restore_context(up); | |
1839 | } | |
ac57e7f3 SP |
1840 | up->latency = up->calc_latency; |
1841 | schedule_work(&up->qos_work); | |
9f9ac1e8 | 1842 | |
b612633b G |
1843 | return 0; |
1844 | } | |
fcdca757 G |
1845 | #endif |
1846 | ||
1847 | static const struct dev_pm_ops serial_omap_dev_pm_ops = { | |
1848 | SET_SYSTEM_SLEEP_PM_OPS(serial_omap_suspend, serial_omap_resume) | |
1849 | SET_RUNTIME_PM_OPS(serial_omap_runtime_suspend, | |
1850 | serial_omap_runtime_resume, NULL) | |
ddd85e22 SP |
1851 | .prepare = serial_omap_prepare, |
1852 | .complete = serial_omap_complete, | |
fcdca757 G |
1853 | }; |
1854 | ||
d92b0dfc RN |
1855 | #if defined(CONFIG_OF) |
1856 | static const struct of_device_id omap_serial_of_match[] = { | |
1857 | { .compatible = "ti,omap2-uart" }, | |
1858 | { .compatible = "ti,omap3-uart" }, | |
1859 | { .compatible = "ti,omap4-uart" }, | |
1860 | {}, | |
1861 | }; | |
1862 | MODULE_DEVICE_TABLE(of, omap_serial_of_match); | |
1863 | #endif | |
b612633b G |
1864 | |
1865 | static struct platform_driver serial_omap_driver = { | |
1866 | .probe = serial_omap_probe, | |
2d47b716 | 1867 | .remove = serial_omap_remove, |
b612633b G |
1868 | .driver = { |
1869 | .name = DRIVER_NAME, | |
fcdca757 | 1870 | .pm = &serial_omap_dev_pm_ops, |
d92b0dfc | 1871 | .of_match_table = of_match_ptr(omap_serial_of_match), |
b612633b G |
1872 | }, |
1873 | }; | |
1874 | ||
1875 | static int __init serial_omap_init(void) | |
1876 | { | |
1877 | int ret; | |
1878 | ||
1879 | ret = uart_register_driver(&serial_omap_reg); | |
1880 | if (ret != 0) | |
1881 | return ret; | |
1882 | ret = platform_driver_register(&serial_omap_driver); | |
1883 | if (ret != 0) | |
1884 | uart_unregister_driver(&serial_omap_reg); | |
1885 | return ret; | |
1886 | } | |
1887 | ||
1888 | static void __exit serial_omap_exit(void) | |
1889 | { | |
1890 | platform_driver_unregister(&serial_omap_driver); | |
1891 | uart_unregister_driver(&serial_omap_reg); | |
1892 | } | |
1893 | ||
1894 | module_init(serial_omap_init); | |
1895 | module_exit(serial_omap_exit); | |
1896 | ||
1897 | MODULE_DESCRIPTION("OMAP High Speed UART driver"); | |
1898 | MODULE_LICENSE("GPL"); | |
1899 | MODULE_AUTHOR("Texas Instruments Inc"); |