[linux-2.6-block.git] / drivers / tty / serial / of_serial.c

/*
 *  Serial Port driver for Open Firmware platform devices
 *
 *    Copyright (C) 2006 Arnd Bergmann <arnd@arndb.de>, IBM Corp.
 *
 *  This program is free software; you can redistribute it and/or
 *  modify it under the terms of the GNU General Public License
 *  as published by the Free Software Foundation; either version
 *  2 of the License, or (at your option) any later version.
 *
 */
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/delay.h>
#include <linux/serial_core.h>
#include <linux/serial_reg.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/of_platform.h>
#include <linux/nwpserial.h>
#include <linux/clk.h>

#include "8250/8250.h"

struct of_serial_info {
	struct clk *clk;
	int type;
	int line;
};

#ifdef CONFIG_ARCH_TEGRA
void tegra_serial_handle_break(struct uart_port *p)
{
	unsigned int status, tmout = 10000;

	do {
		status = p->serial_in(p, UART_LSR);
		if (status & (UART_LSR_FIFOE | UART_LSR_BRK_ERROR_BITS))
			status = p->serial_in(p, UART_RX);
		else
			break;
		if (--tmout == 0)
			break;
		udelay(1);
	} while (1);
}
#else
static inline void tegra_serial_handle_break(struct uart_port *port)
{
}
#endif

/*
 * Fill a struct uart_port for a given device node
 */
static int of_platform_serial_setup(struct platform_device *ofdev,
			int type, struct uart_port *port,
			struct of_serial_info *info)
{
	struct resource resource;
	struct device_node *np = ofdev->dev.of_node;
	u32 clk, spd, prop;
	int ret;

	memset(port, 0, sizeof *port);
	if (of_property_read_u32(np, "clock-frequency", &clk)) {

		/* Get clk rate through clk driver if present */
		info->clk = clk_get(&ofdev->dev, NULL);
		if (IS_ERR(info->clk)) {
			dev_warn(&ofdev->dev,
				"clk or clock-frequency not defined\n");
			return PTR_ERR(info->clk);
		}

		clk_prepare_enable(info->clk);
		clk = clk_get_rate(info->clk);
	}
	/* If current-speed was set, then try not to change it. */
	if (of_property_read_u32(np, "current-speed", &spd) == 0)
		port->custom_divisor = clk / (16 * spd);

	ret = of_address_to_resource(np, 0, &resource);
	if (ret) {
		dev_warn(&ofdev->dev, "invalid address\n");
		goto out;
	}

	spin_lock_init(&port->lock);
	port->mapbase = resource.start;

	/* Check for shifted address mapping */
	if (of_property_read_u32(np, "reg-offset", &prop) == 0)
		port->mapbase += prop;

	/* Check for registers offset within the devices address range */
	if (of_property_read_u32(np, "reg-shift", &prop) == 0)
		port->regshift = prop;

	/* Check for fifo size */
	if (of_property_read_u32(np, "fifo-size", &prop) == 0)
		port->fifosize = prop;

	port->irq = irq_of_parse_and_map(np, 0);
	port->iotype = UPIO_MEM;
	if (of_property_read_u32(np, "reg-io-width", &prop) == 0) {
		switch (prop) {
		case 1:
			port->iotype = UPIO_MEM;
			break;
		case 4:
			port->iotype = UPIO_MEM32;
			break;
		default:
			dev_warn(&ofdev->dev, "unsupported reg-io-width (%d)\n",
				 prop);
			ret = -EINVAL;
			goto out;
		}
	}

	port->type = type;
	port->uartclk = clk;
	port->flags = UPF_SHARE_IRQ | UPF_BOOT_AUTOCONF | UPF_IOREMAP
		| UPF_FIXED_PORT | UPF_FIXED_TYPE;

	if (of_find_property(np, "no-loopback-test", NULL))
		port->flags |= UPF_SKIP_TEST;

	port->dev = &ofdev->dev;

	if (type == PORT_TEGRA)
		port->handle_break = tegra_serial_handle_break;

	return 0;
out:
	if (info->clk)
		clk_disable_unprepare(info->clk);
	return ret;
}

/*
 * Try to register a serial port
 */
static struct of_device_id of_platform_serial_table[];
static int of_platform_serial_probe(struct platform_device *ofdev)
{
	const struct of_device_id *match;
	struct of_serial_info *info;
	struct uart_port port;
	int port_type;
	int ret;

	match = of_match_device(of_platform_serial_table, &ofdev->dev);
	if (!match)
		return -EINVAL;

	if (of_find_property(ofdev->dev.of_node, "used-by-rtas", NULL))
		return -EBUSY;

	info = kzalloc(sizeof(*info), GFP_KERNEL);
	if (info == NULL)
		return -ENOMEM;

	port_type = (unsigned long)match->data;
	ret = of_platform_serial_setup(ofdev, port_type, &port, info);
	if (ret)
		goto out;

	switch (port_type) {
#ifdef CONFIG_SERIAL_8250
	case PORT_8250 ... PORT_MAX_8250:
	{
		struct uart_8250_port port8250;
		memset(&port8250, 0, sizeof(port8250));
		port.type = port_type;
		port8250.port = port;

		if (port.fifosize)
			port8250.capabilities = UART_CAP_FIFO;

		if (of_property_read_bool(ofdev->dev.of_node,
					  "auto-flow-control"))
			port8250.capabilities |= UART_CAP_AFE;

		ret = serial8250_register_8250_port(&port8250);
		break;
	}
#endif
#ifdef CONFIG_SERIAL_OF_PLATFORM_NWPSERIAL
	case PORT_NWPSERIAL:
		ret = nwpserial_register_port(&port);
		break;
#endif
	default:
		/* need to add code for these */
	case PORT_UNKNOWN:
		dev_info(&ofdev->dev, "Unknown serial port found, ignored\n");
		ret = -ENODEV;
		break;
	}
	if (ret < 0)
		goto out;

	info->type = port_type;
	info->line = ret;
	platform_set_drvdata(ofdev, info);
	return 0;
out:
	kfree(info);
	irq_dispose_mapping(port.irq);
	return ret;
}

/*
 * Release a line
 */
static int of_platform_serial_remove(struct platform_device *ofdev)
{
	struct of_serial_info *info = platform_get_drvdata(ofdev);
	switch (info->type) {
#ifdef CONFIG_SERIAL_8250
	case PORT_8250 ... PORT_MAX_8250:
		serial8250_unregister_port(info->line);
		break;
#endif
#ifdef CONFIG_SERIAL_OF_PLATFORM_NWPSERIAL
	case PORT_NWPSERIAL:
		nwpserial_unregister_port(info->line);
		break;
#endif
	default:
		/* need to add code for these */
		break;
	}

	if (info->clk)
		clk_disable_unprepare(info->clk);
	kfree(info);
	return 0;
}

/*
 * A few common types, add more as needed.
 */
static struct of_device_id of_platform_serial_table[] = {
	{ .compatible = "ns8250",   .data = (void *)PORT_8250, },
	{ .compatible = "ns16450",  .data = (void *)PORT_16450, },
	{ .compatible = "ns16550a", .data = (void *)PORT_16550A, },
	{ .compatible = "ns16550",  .data = (void *)PORT_16550, },
	{ .compatible = "ns16750",  .data = (void *)PORT_16750, },
	{ .compatible = "ns16850",  .data = (void *)PORT_16850, },
	{ .compatible = "nvidia,tegra20-uart", .data = (void *)PORT_TEGRA, },
	{ .compatible = "nxp,lpc3220-uart", .data = (void *)PORT_LPC3220, },
	{ .compatible = "altr,16550-FIFO32",
		.data = (void *)PORT_ALTR_16550_F32, },
	{ .compatible = "altr,16550-FIFO64",
		.data = (void *)PORT_ALTR_16550_F64, },
	{ .compatible = "altr,16550-FIFO128",
		.data = (void *)PORT_ALTR_16550_F128, },
#ifdef CONFIG_SERIAL_OF_PLATFORM_NWPSERIAL
	{ .compatible = "ibm,qpace-nwp-serial",
		.data = (void *)PORT_NWPSERIAL, },
#endif
	{ .type = "serial",         .data = (void *)PORT_UNKNOWN, },
	{ /* end of list */ },
};

static struct platform_driver of_platform_serial_driver = {
	.driver = {
		.name = "of_serial",
		.owner = THIS_MODULE,
		.of_match_table = of_platform_serial_table,
	},
	.probe = of_platform_serial_probe,
	.remove = of_platform_serial_remove,
};

module_platform_driver(of_platform_serial_driver);

MODULE_AUTHOR("Arnd Bergmann <arnd@arndb.de>");
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("Serial Port driver for Open Firmware platform devices");
Commit	Line	Data
8d38a5b2 AB	1	/*
	2	* Serial Port driver for Open Firmware platform devices
	3	*
	4	* Copyright (C) 2006 Arnd Bergmann <arnd@arndb.de>, IBM Corp.
	5	*
	6	* This program is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU General Public License
	8	* as published by the Free Software Foundation; either version
	9	* 2 of the License, or (at your option) any later version.
	10	*
	11	*/
8d38a5b2	12	#include <linux/module.h>
5a0e3ad6	13	#include <linux/slab.h>
bf03f65b	14	#include <linux/delay.h>
8d38a5b2	15	#include <linux/serial_core.h>
bf03f65b	16	#include <linux/serial_reg.h>
f1ca09b2	17	#include <linux/of_address.h>
73930a85	18	#include <linux/of_irq.h>
c401b044	19	#include <linux/of_platform.h>
5886188d	20	#include <linux/nwpserial.h>
0bbeb3c3	21	#include <linux/clk.h>
8d38a5b2	22
b0b8c84c HK	23	#include "8250/8250.h"
b0b8c84c HK	24
e34b9c94	25	struct of_serial_info {
0bbeb3c3	26	struct clk *clk;
e34b9c94 IK	27	int type;
	28	int line;
	29	};
	30
bf03f65b DW	31	#ifdef CONFIG_ARCH_TEGRA
	32	void tegra_serial_handle_break(struct uart_port *p)
	33	{
	34	unsigned int status, tmout = 10000;
	35
	36	do {
	37	status = p->serial_in(p, UART_LSR);
	38	if (status & (UART_LSR_FIFOE \| UART_LSR_BRK_ERROR_BITS))
	39	status = p->serial_in(p, UART_RX);
	40	else
	41	break;
	42	if (--tmout == 0)
	43	break;
	44	udelay(1);
	45	} while (1);
	46	}
f26402e8 SW	47	#else
	48	static inline void tegra_serial_handle_break(struct uart_port *port)
	49	{
	50	}
bf03f65b DW	51	#endif
bf03f65b DW	52
8d38a5b2 AB	53	/*
	54	* Fill a struct uart_port for a given device node
	55	*/
9671f099	56	static int of_platform_serial_setup(struct platform_device *ofdev,
0bbeb3c3 MK	57	int type, struct uart_port *port,
0bbeb3c3 MK	58	struct of_serial_info *info)
8d38a5b2 AB	59	{
8d38a5b2 AB	60	struct resource resource;
61c7a080	61	struct device_node *np = ofdev->dev.of_node;
b84e7731 GL	62	u32 clk, spd, prop;
b84e7731 GL	63	int ret;
8d38a5b2 AB	64
8d38a5b2 AB	65	memset(port, 0, sizeof *port);
b84e7731	66	if (of_property_read_u32(np, "clock-frequency", &clk)) {
0bbeb3c3 MK	67
	68	/* Get clk rate through clk driver if present */
	69	info->clk = clk_get(&ofdev->dev, NULL);
76cc4386	70	if (IS_ERR(info->clk)) {
0bbeb3c3 MK	71	dev_warn(&ofdev->dev,
0bbeb3c3 MK	72	"clk or clock-frequency not defined\n");
76cc4386	73	return PTR_ERR(info->clk);
0bbeb3c3 MK	74	}
	75
	76	clk_prepare_enable(info->clk);
	77	clk = clk_get_rate(info->clk);
8d38a5b2	78	}
b84e7731 GL	79	/* If current-speed was set, then try not to change it. */
	80	if (of_property_read_u32(np, "current-speed", &spd) == 0)
	81	port->custom_divisor = clk / (16 * spd);
8d38a5b2 AB	82
	83	ret = of_address_to_resource(np, 0, &resource);
	84	if (ret) {
	85	dev_warn(&ofdev->dev, "invalid address\n");
0bbeb3c3	86	goto out;
8d38a5b2 AB	87	}
	88
	89	spin_lock_init(&port->lock);
	90	port->mapbase = resource.start;
b912b5e2 JL	91
b912b5e2 JL	92	/* Check for shifted address mapping */
b84e7731 GL	93	if (of_property_read_u32(np, "reg-offset", &prop) == 0)
b84e7731 GL	94	port->mapbase += prop;
b912b5e2 JL	95
b912b5e2 JL	96	/* Check for registers offset within the devices address range */
b84e7731 GL	97	if (of_property_read_u32(np, "reg-shift", &prop) == 0)
b84e7731 GL	98	port->regshift = prop;
b912b5e2	99
9f1ca068 HK	100	/* Check for fifo size */
	101	if (of_property_read_u32(np, "fifo-size", &prop) == 0)
	102	port->fifosize = prop;
	103
8d38a5b2 AB	104	port->irq = irq_of_parse_and_map(np, 0);
8d38a5b2 AB	105	port->iotype = UPIO_MEM;
b84e7731 GL	106	if (of_property_read_u32(np, "reg-io-width", &prop) == 0) {
b84e7731 GL	107	switch (prop) {
7423734e JI	108	case 1:
	109	port->iotype = UPIO_MEM;
	110	break;
	111	case 4:
	112	port->iotype = UPIO_MEM32;
	113	break;
	114	default:
b84e7731 GL	115	dev_warn(&ofdev->dev, "unsupported reg-io-width (%d)\n",
b84e7731 GL	116	prop);
0bbeb3c3 MK	117	ret = -EINVAL;
0bbeb3c3 MK	118	goto out;
7423734e JI	119	}
	120	}
	121
8d38a5b2	122	port->type = type;
b84e7731	123	port->uartclk = clk;
abb4a239	124	port->flags = UPF_SHARE_IRQ \| UPF_BOOT_AUTOCONF \| UPF_IOREMAP
eedacbf0	125	\| UPF_FIXED_PORT \| UPF_FIXED_TYPE;
fde8be29 GJ	126
	127	if (of_find_property(np, "no-loopback-test", NULL))
	128	port->flags \|= UPF_SKIP_TEST;
	129
8d38a5b2	130	port->dev = &ofdev->dev;
8d38a5b2	131
bf03f65b DW	132	if (type == PORT_TEGRA)
	133	port->handle_break = tegra_serial_handle_break;
	134
8d38a5b2	135	return 0;
0bbeb3c3 MK	136	out:
	137	if (info->clk)
	138	clk_disable_unprepare(info->clk);
	139	return ret;
8d38a5b2 AB	140	}
	141
	142	/*
	143	* Try to register a serial port
	144	*/
b1608d69	145	static struct of_device_id of_platform_serial_table[];
9671f099	146	static int of_platform_serial_probe(struct platform_device *ofdev)
8d38a5b2	147	{
b1608d69	148	const struct of_device_id *match;
e34b9c94	149	struct of_serial_info *info;
8d38a5b2 AB	150	struct uart_port port;
	151	int port_type;
	152	int ret;
	153
b1608d69 GL	154	match = of_match_device(of_platform_serial_table, &ofdev->dev);
b1608d69 GL	155	if (!match)
793218df GL	156	return -EINVAL;
793218df GL	157
61c7a080	158	if (of_find_property(ofdev->dev.of_node, "used-by-rtas", NULL))
8d38a5b2 AB	159	return -EBUSY;
8d38a5b2 AB	160
7e12e675	161	info = kzalloc(sizeof(*info), GFP_KERNEL);
e34b9c94 IK	162	if (info == NULL)
	163	return -ENOMEM;
	164
b1608d69	165	port_type = (unsigned long)match->data;
0bbeb3c3	166	ret = of_platform_serial_setup(ofdev, port_type, &port, info);
8d38a5b2 AB	167	if (ret)
	168	goto out;
	169
	170	switch (port_type) {
5886188d	171	#ifdef CONFIG_SERIAL_8250
8d38a5b2	172	case PORT_8250 ... PORT_MAX_8250:
ce7240e4	173	{
ce7240e4 AC	174	struct uart_8250_port port8250;
ce7240e4 AC	175	memset(&port8250, 0, sizeof(port8250));
7fa21dd8	176	port.type = port_type;
ce7240e4	177	port8250.port = port;
b0b8c84c HK	178
	179	if (port.fifosize)
	180	port8250.capabilities = UART_CAP_FIFO;
	181
	182	if (of_property_read_bool(ofdev->dev.of_node,
	183	"auto-flow-control"))
	184	port8250.capabilities \|= UART_CAP_AFE;
	185
ce7240e4	186	ret = serial8250_register_8250_port(&port8250);
8d38a5b2	187	break;
ce7240e4	188	}
5886188d BK	189	#endif
	190	#ifdef CONFIG_SERIAL_OF_PLATFORM_NWPSERIAL
	191	case PORT_NWPSERIAL:
	192	ret = nwpserial_register_port(&port);
	193	break;
	194	#endif
8d38a5b2 AB	195	default:
8d38a5b2 AB	196	/* need to add code for these */
1558f9b4 IK	197	case PORT_UNKNOWN:
1558f9b4 IK	198	dev_info(&ofdev->dev, "Unknown serial port found, ignored\n");
8d38a5b2 AB	199	ret = -ENODEV;
	200	break;
	201	}
	202	if (ret < 0)
	203	goto out;
	204
e34b9c94 IK	205	info->type = port_type;
e34b9c94 IK	206	info->line = ret;
696faedd	207	platform_set_drvdata(ofdev, info);
8d38a5b2 AB	208	return 0;
8d38a5b2 AB	209	out:
e34b9c94	210	kfree(info);
8d38a5b2 AB	211	irq_dispose_mapping(port.irq);
	212	return ret;
	213	}
	214
	215	/*
	216	* Release a line
	217	*/
2dc11581	218	static int of_platform_serial_remove(struct platform_device *ofdev)
8d38a5b2	219	{
696faedd	220	struct of_serial_info *info = platform_get_drvdata(ofdev);
e34b9c94	221	switch (info->type) {
5886188d	222	#ifdef CONFIG_SERIAL_8250
e34b9c94 IK	223	case PORT_8250 ... PORT_MAX_8250:
	224	serial8250_unregister_port(info->line);
	225	break;
5886188d BK	226	#endif
	227	#ifdef CONFIG_SERIAL_OF_PLATFORM_NWPSERIAL
	228	case PORT_NWPSERIAL:
	229	nwpserial_unregister_port(info->line);
	230	break;
	231	#endif
e34b9c94 IK	232	default:
	233	/* need to add code for these */
	234	break;
	235	}
0bbeb3c3 MK	236
	237	if (info->clk)
	238	clk_disable_unprepare(info->clk);
e34b9c94	239	kfree(info);
8d38a5b2 AB	240	return 0;
	241	}
	242
	243	/*
	244	* A few common types, add more as needed.
	245	*/
de88b340	246	static struct of_device_id of_platform_serial_table[] = {
8c6e9112 GL	247	{ .compatible = "ns8250", .data = (void *)PORT_8250, },
	248	{ .compatible = "ns16450", .data = (void *)PORT_16450, },
	249	{ .compatible = "ns16550a", .data = (void *)PORT_16550A, },
	250	{ .compatible = "ns16550", .data = (void *)PORT_16550, },
	251	{ .compatible = "ns16750", .data = (void *)PORT_16750, },
	252	{ .compatible = "ns16850", .data = (void *)PORT_16850, },
2e39e5be	253	{ .compatible = "nvidia,tegra20-uart", .data = (void *)PORT_TEGRA, },
e4305f0c	254	{ .compatible = "nxp,lpc3220-uart", .data = (void *)PORT_LPC3220, },
e06c93ca LFT	255	{ .compatible = "altr,16550-FIFO32",
	256	.data = (void *)PORT_ALTR_16550_F32, },
	257	{ .compatible = "altr,16550-FIFO64",
	258	.data = (void *)PORT_ALTR_16550_F64, },
	259	{ .compatible = "altr,16550-FIFO128",
	260	.data = (void *)PORT_ALTR_16550_F128, },
5886188d	261	#ifdef CONFIG_SERIAL_OF_PLATFORM_NWPSERIAL
8c6e9112 GL	262	{ .compatible = "ibm,qpace-nwp-serial",
8c6e9112 GL	263	.data = (void *)PORT_NWPSERIAL, },
5886188d	264	#endif
8c6e9112	265	{ .type = "serial", .data = (void *)PORT_UNKNOWN, },
8d38a5b2 AB	266	{ /* end of list */ },
	267	};
	268
793218df	269	static struct platform_driver of_platform_serial_driver = {
4018294b GL	270	.driver = {
	271	.name = "of_serial",
	272	.owner = THIS_MODULE,
	273	.of_match_table = of_platform_serial_table,
	274	},
8d38a5b2 AB	275	.probe = of_platform_serial_probe,
8d38a5b2 AB	276	.remove = of_platform_serial_remove,
8d38a5b2 AB	277	};
8d38a5b2 AB	278
940ab889	279	module_platform_driver(of_platform_serial_driver);
8d38a5b2 AB	280
	281	MODULE_AUTHOR("Arnd Bergmann <arnd@arndb.de>");
	282	MODULE_LICENSE("GPL");
	283	MODULE_DESCRIPTION("Serial Port driver for Open Firmware platform devices");