[linux-2.6-block.git] / drivers / tty / serial / netx-serial.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (c) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
 */

#if defined(CONFIG_SERIAL_NETX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
#define SUPPORT_SYSRQ
#endif

#include <linux/device.h>
#include <linux/module.h>
#include <linux/ioport.h>
#include <linux/init.h>
#include <linux/console.h>
#include <linux/sysrq.h>
#include <linux/platform_device.h>
#include <linux/tty.h>
#include <linux/tty_flip.h>
#include <linux/serial_core.h>
#include <linux/serial.h>

#include <asm/io.h>
#include <asm/irq.h>
#include <mach/hardware.h>
#include <mach/netx-regs.h>

/* We've been assigned a range on the "Low-density serial ports" major */
#define SERIAL_NX_MAJOR	204
#define MINOR_START	170

enum uart_regs {
	UART_DR              = 0x00,
	UART_SR              = 0x04,
	UART_LINE_CR         = 0x08,
	UART_BAUDDIV_MSB     = 0x0c,
	UART_BAUDDIV_LSB     = 0x10,
	UART_CR              = 0x14,
	UART_FR              = 0x18,
	UART_IIR             = 0x1c,
	UART_ILPR            = 0x20,
	UART_RTS_CR          = 0x24,
	UART_RTS_LEAD        = 0x28,
	UART_RTS_TRAIL       = 0x2c,
	UART_DRV_ENABLE      = 0x30,
	UART_BRM_CR          = 0x34,
	UART_RXFIFO_IRQLEVEL = 0x38,
	UART_TXFIFO_IRQLEVEL = 0x3c,
};

#define SR_FE (1<<0)
#define SR_PE (1<<1)
#define SR_BE (1<<2)
#define SR_OE (1<<3)

#define LINE_CR_BRK       (1<<0)
#define LINE_CR_PEN       (1<<1)
#define LINE_CR_EPS       (1<<2)
#define LINE_CR_STP2      (1<<3)
#define LINE_CR_FEN       (1<<4)
#define LINE_CR_5BIT      (0<<5)
#define LINE_CR_6BIT      (1<<5)
#define LINE_CR_7BIT      (2<<5)
#define LINE_CR_8BIT      (3<<5)
#define LINE_CR_BITS_MASK (3<<5)

#define CR_UART_EN (1<<0)
#define CR_SIREN   (1<<1)
#define CR_SIRLP   (1<<2)
#define CR_MSIE    (1<<3)
#define CR_RIE     (1<<4)
#define CR_TIE     (1<<5)
#define CR_RTIE    (1<<6)
#define CR_LBE     (1<<7)

#define FR_CTS  (1<<0)
#define FR_DSR  (1<<1)
#define FR_DCD  (1<<2)
#define FR_BUSY (1<<3)
#define FR_RXFE (1<<4)
#define FR_TXFF (1<<5)
#define FR_RXFF (1<<6)
#define FR_TXFE (1<<7)

#define IIR_MIS (1<<0)
#define IIR_RIS (1<<1)
#define IIR_TIS (1<<2)
#define IIR_RTIS (1<<3)
#define IIR_MASK 0xf

#define RTS_CR_AUTO (1<<0)
#define RTS_CR_RTS  (1<<1)
#define RTS_CR_COUNT (1<<2)
#define RTS_CR_MOD2  (1<<3)
#define RTS_CR_RTS_POL (1<<4)
#define RTS_CR_CTS_CTR (1<<5)
#define RTS_CR_CTS_POL (1<<6)
#define RTS_CR_STICK   (1<<7)

#define UART_PORT_SIZE 0x40
#define DRIVER_NAME "netx-uart"

struct netx_port {
	struct uart_port	port;
};

static void netx_stop_tx(struct uart_port *port)
{
	unsigned int val;
	val = readl(port->membase + UART_CR);
	writel(val & ~CR_TIE,  port->membase + UART_CR);
}

static void netx_stop_rx(struct uart_port *port)
{
	unsigned int val;
	val = readl(port->membase + UART_CR);
	writel(val & ~CR_RIE,  port->membase + UART_CR);
}

static void netx_enable_ms(struct uart_port *port)
{
	unsigned int val;
	val = readl(port->membase + UART_CR);
	writel(val | CR_MSIE, port->membase + UART_CR);
}

static inline void netx_transmit_buffer(struct uart_port *port)
{
	struct circ_buf *xmit = &port->state->xmit;

	if (port->x_char) {
		writel(port->x_char, port->membase + UART_DR);
		port->icount.tx++;
		port->x_char = 0;
		return;
	}

	if (uart_tx_stopped(port) || uart_circ_empty(xmit)) {
		netx_stop_tx(port);
		return;
	}

	do {
		/* send xmit->buf[xmit->tail]
		 * out the port here */
		writel(xmit->buf[xmit->tail], port->membase + UART_DR);
		xmit->tail = (xmit->tail + 1) &
		         (UART_XMIT_SIZE - 1);
		port->icount.tx++;
		if (uart_circ_empty(xmit))
			break;
	} while (!(readl(port->membase + UART_FR) & FR_TXFF));

	if (uart_circ_empty(xmit))
		netx_stop_tx(port);
}

static void netx_start_tx(struct uart_port *port)
{
	writel(
	    readl(port->membase + UART_CR) | CR_TIE, port->membase + UART_CR);

	if (!(readl(port->membase + UART_FR) & FR_TXFF))
		netx_transmit_buffer(port);
}

static unsigned int netx_tx_empty(struct uart_port *port)
{
	return readl(port->membase + UART_FR) & FR_BUSY ? 0 : TIOCSER_TEMT;
}

static void netx_txint(struct uart_port *port)
{
	struct circ_buf *xmit = &port->state->xmit;

	if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
		netx_stop_tx(port);
		return;
	}

	netx_transmit_buffer(port);

	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
		uart_write_wakeup(port);
}

static void netx_rxint(struct uart_port *port, unsigned long *flags)
{
	unsigned char rx, flg, status;

	while (!(readl(port->membase + UART_FR) & FR_RXFE)) {
		rx = readl(port->membase + UART_DR);
		flg = TTY_NORMAL;
		port->icount.rx++;
		status = readl(port->membase + UART_SR);
		if (status & SR_BE) {
			writel(0, port->membase + UART_SR);
			if (uart_handle_break(port))
				continue;
		}

		if (unlikely(status & (SR_FE | SR_PE | SR_OE))) {

			if (status & SR_PE)
				port->icount.parity++;
			else if (status & SR_FE)
				port->icount.frame++;
			if (status & SR_OE)
				port->icount.overrun++;

			status &= port->read_status_mask;

			if (status & SR_BE)
				flg = TTY_BREAK;
			else if (status & SR_PE)
				flg = TTY_PARITY;
			else if (status & SR_FE)
				flg = TTY_FRAME;
		}

		if (uart_handle_sysrq_char(port, rx))
			continue;

		uart_insert_char(port, status, SR_OE, rx, flg);
	}

	spin_unlock_irqrestore(&port->lock, *flags);
	tty_flip_buffer_push(&port->state->port);
	spin_lock_irqsave(&port->lock, *flags);
}

static irqreturn_t netx_int(int irq, void *dev_id)
{
	struct uart_port *port = dev_id;
	unsigned long flags;
	unsigned char status;

	spin_lock_irqsave(&port->lock,flags);

	status = readl(port->membase + UART_IIR) & IIR_MASK;
	while (status) {
		if (status & IIR_RIS)
			netx_rxint(port, &flags);
		if (status & IIR_TIS)
			netx_txint(port);
		if (status & IIR_MIS) {
			if (readl(port->membase + UART_FR) & FR_CTS)
				uart_handle_cts_change(port, 1);
			else
				uart_handle_cts_change(port, 0);
		}
		writel(0, port->membase + UART_IIR);
		status = readl(port->membase + UART_IIR) & IIR_MASK;
	}

	spin_unlock_irqrestore(&port->lock,flags);
	return IRQ_HANDLED;
}

static unsigned int netx_get_mctrl(struct uart_port *port)
{
	unsigned int ret = TIOCM_DSR | TIOCM_CAR;

	if (readl(port->membase + UART_FR) & FR_CTS)
		ret |= TIOCM_CTS;

	return ret;
}

static void netx_set_mctrl(struct uart_port *port, unsigned int mctrl)
{
	unsigned int val;

	/* FIXME: Locking needed ? */
	if (mctrl & TIOCM_RTS) {
		val = readl(port->membase + UART_RTS_CR);
		writel(val | RTS_CR_RTS, port->membase + UART_RTS_CR);
	}
}

static void netx_break_ctl(struct uart_port *port, int break_state)
{
	unsigned int line_cr;
	spin_lock_irq(&port->lock);

	line_cr = readl(port->membase + UART_LINE_CR);
	if (break_state != 0)
		line_cr |= LINE_CR_BRK;
	else
		line_cr &= ~LINE_CR_BRK;
	writel(line_cr, port->membase + UART_LINE_CR);

	spin_unlock_irq(&port->lock);
}

static int netx_startup(struct uart_port *port)
{
	int ret;

	ret = request_irq(port->irq, netx_int, 0,
			     DRIVER_NAME, port);
	if (ret) {
		dev_err(port->dev, "unable to grab irq%d\n",port->irq);
		goto exit;
	}

	writel(readl(port->membase + UART_LINE_CR) | LINE_CR_FEN,
		port->membase + UART_LINE_CR);

	writel(CR_MSIE | CR_RIE | CR_TIE | CR_RTIE | CR_UART_EN,
		port->membase + UART_CR);

exit:
	return ret;
}

static void netx_shutdown(struct uart_port *port)
{
	writel(0, port->membase + UART_CR) ;

	free_irq(port->irq, port);
}

static void
netx_set_termios(struct uart_port *port, struct ktermios *termios,
		   struct ktermios *old)
{
	unsigned int baud, quot;
	unsigned char old_cr;
	unsigned char line_cr = LINE_CR_FEN;
	unsigned char rts_cr = 0;

	switch (termios->c_cflag & CSIZE) {
	case CS5:
		line_cr |= LINE_CR_5BIT;
		break;
	case CS6:
		line_cr |= LINE_CR_6BIT;
		break;
	case CS7:
		line_cr |= LINE_CR_7BIT;
		break;
	case CS8:
		line_cr |= LINE_CR_8BIT;
		break;
	}

	if (termios->c_cflag & CSTOPB)
		line_cr |= LINE_CR_STP2;

	if (termios->c_cflag & PARENB) {
		line_cr |= LINE_CR_PEN;
		if (!(termios->c_cflag & PARODD))
			line_cr |= LINE_CR_EPS;
	}

	if (termios->c_cflag & CRTSCTS)
		rts_cr = RTS_CR_AUTO | RTS_CR_CTS_CTR | RTS_CR_RTS_POL;

	baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
	quot = baud * 4096;
	quot /= 1000;
	quot *= 256;
	quot /= 100000;

	spin_lock_irq(&port->lock);

	uart_update_timeout(port, termios->c_cflag, baud);

	old_cr = readl(port->membase + UART_CR);

	/* disable interrupts */
	writel(old_cr & ~(CR_MSIE | CR_RIE | CR_TIE | CR_RTIE),
		port->membase + UART_CR);

	/* drain transmitter */
	while (readl(port->membase + UART_FR) & FR_BUSY);

	/* disable UART */
	writel(old_cr & ~CR_UART_EN, port->membase + UART_CR);

	/* modem status interrupts */
	old_cr &= ~CR_MSIE;
	if (UART_ENABLE_MS(port, termios->c_cflag))
		old_cr |= CR_MSIE;

	writel((quot>>8) & 0xff, port->membase + UART_BAUDDIV_MSB);
	writel(quot & 0xff, port->membase + UART_BAUDDIV_LSB);
	writel(line_cr, port->membase + UART_LINE_CR);

	writel(rts_cr, port->membase + UART_RTS_CR);

	/*
	 * Characters to ignore
	 */
	port->ignore_status_mask = 0;
	if (termios->c_iflag & IGNPAR)
		port->ignore_status_mask |= SR_PE;
	if (termios->c_iflag & IGNBRK) {
		port->ignore_status_mask |= SR_BE;
		/*
		 * If we're ignoring parity and break indicators,
		 * ignore overruns too (for real raw support).
		 */
		if (termios->c_iflag & IGNPAR)
			port->ignore_status_mask |= SR_PE;
	}

	port->read_status_mask = 0;
	if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
		port->read_status_mask |= SR_BE;
	if (termios->c_iflag & INPCK)
		port->read_status_mask |= SR_PE | SR_FE;

	writel(old_cr, port->membase + UART_CR);

	spin_unlock_irq(&port->lock);
}

static const char *netx_type(struct uart_port *port)
{
	return port->type == PORT_NETX ? "NETX" : NULL;
}

static void netx_release_port(struct uart_port *port)
{
	release_mem_region(port->mapbase, UART_PORT_SIZE);
}

static int netx_request_port(struct uart_port *port)
{
	return request_mem_region(port->mapbase, UART_PORT_SIZE,
			DRIVER_NAME) != NULL ? 0 : -EBUSY;
}

static void netx_config_port(struct uart_port *port, int flags)
{
	if (flags & UART_CONFIG_TYPE && netx_request_port(port) == 0)
		port->type = PORT_NETX;
}

static int
netx_verify_port(struct uart_port *port, struct serial_struct *ser)
{
	int ret = 0;

	if (ser->type != PORT_UNKNOWN && ser->type != PORT_NETX)
		ret = -EINVAL;

	return ret;
}

static struct uart_ops netx_pops = {
	.tx_empty	= netx_tx_empty,
	.set_mctrl	= netx_set_mctrl,
	.get_mctrl	= netx_get_mctrl,
	.stop_tx	= netx_stop_tx,
	.start_tx	= netx_start_tx,
	.stop_rx	= netx_stop_rx,
	.enable_ms	= netx_enable_ms,
	.break_ctl	= netx_break_ctl,
	.startup	= netx_startup,
	.shutdown	= netx_shutdown,
	.set_termios	= netx_set_termios,
	.type		= netx_type,
	.release_port	= netx_release_port,
	.request_port	= netx_request_port,
	.config_port	= netx_config_port,
	.verify_port	= netx_verify_port,
};

static struct netx_port netx_ports[] = {
	{
	.port = {
		.type = PORT_NETX,
		.iotype = UPIO_MEM,
		.membase = (char __iomem *)io_p2v(NETX_PA_UART0),
		.mapbase = NETX_PA_UART0,
		.irq = NETX_IRQ_UART0,
		.uartclk = 100000000,
		.fifosize = 16,
		.flags = UPF_BOOT_AUTOCONF,
		.ops = &netx_pops,
		.line = 0,
	},
	}, {
	.port = {
		.type = PORT_NETX,
		.iotype = UPIO_MEM,
		.membase = (char __iomem *)io_p2v(NETX_PA_UART1),
		.mapbase = NETX_PA_UART1,
		.irq = NETX_IRQ_UART1,
		.uartclk = 100000000,
		.fifosize = 16,
		.flags = UPF_BOOT_AUTOCONF,
		.ops = &netx_pops,
		.line = 1,
	},
	}, {
	.port = {
		.type = PORT_NETX,
		.iotype = UPIO_MEM,
		.membase = (char __iomem *)io_p2v(NETX_PA_UART2),
		.mapbase = NETX_PA_UART2,
		.irq = NETX_IRQ_UART2,
		.uartclk = 100000000,
		.fifosize = 16,
		.flags = UPF_BOOT_AUTOCONF,
		.ops = &netx_pops,
		.line = 2,
	},
	}
};

#ifdef CONFIG_SERIAL_NETX_CONSOLE

static void netx_console_putchar(struct uart_port *port, int ch)
{
	while (readl(port->membase + UART_FR) & FR_BUSY);
	writel(ch, port->membase + UART_DR);
}

static void
netx_console_write(struct console *co, const char *s, unsigned int count)
{
	struct uart_port *port = &netx_ports[co->index].port;
	unsigned char cr_save;

	cr_save = readl(port->membase + UART_CR);
	writel(cr_save | CR_UART_EN, port->membase + UART_CR);

	uart_console_write(port, s, count, netx_console_putchar);

	while (readl(port->membase + UART_FR) & FR_BUSY);
	writel(cr_save, port->membase + UART_CR);
}

static void __init
netx_console_get_options(struct uart_port *port, int *baud,
			int *parity, int *bits, int *flow)
{
	unsigned char line_cr;

	*baud = (readl(port->membase + UART_BAUDDIV_MSB) << 8) |
		readl(port->membase + UART_BAUDDIV_LSB);
	*baud *= 1000;
	*baud /= 4096;
	*baud *= 1000;
	*baud /= 256;
	*baud *= 100;

	line_cr = readl(port->membase + UART_LINE_CR);
	*parity = 'n';
	if (line_cr & LINE_CR_PEN) {
		if (line_cr & LINE_CR_EPS)
			*parity = 'e';
		else
			*parity = 'o';
	}

	switch (line_cr & LINE_CR_BITS_MASK) {
	case LINE_CR_8BIT:
		*bits = 8;
		break;
	case LINE_CR_7BIT:
		*bits = 7;
		break;
	case LINE_CR_6BIT:
		*bits = 6;
		break;
	case LINE_CR_5BIT:
		*bits = 5;
		break;
	}

	if (readl(port->membase + UART_RTS_CR) & RTS_CR_AUTO)
		*flow = 'r';
}

static int __init
netx_console_setup(struct console *co, char *options)
{
	struct netx_port *sport;
	int baud = 9600;
	int bits = 8;
	int parity = 'n';
	int flow = 'n';

	/*
	 * Check whether an invalid uart number has been specified, and
	 * if so, search for the first available port that does have
	 * console support.
	 */
	if (co->index == -1 || co->index >= ARRAY_SIZE(netx_ports))
		co->index = 0;
	sport = &netx_ports[co->index];

	if (options) {
		uart_parse_options(options, &baud, &parity, &bits, &flow);
	} else {
		/* if the UART is enabled, assume it has been correctly setup
		 * by the bootloader and get the options
		 */
		if (readl(sport->port.membase + UART_CR) & CR_UART_EN) {
			netx_console_get_options(&sport->port, &baud,
			&parity, &bits, &flow);
		}

	}

	return uart_set_options(&sport->port, co, baud, parity, bits, flow);
}

static struct uart_driver netx_reg;
static struct console netx_console = {
	.name		= "ttyNX",
	.write		= netx_console_write,
	.device		= uart_console_device,
	.setup		= netx_console_setup,
	.flags		= CON_PRINTBUFFER,
	.index		= -1,
	.data		= &netx_reg,
};

static int __init netx_console_init(void)
{
	register_console(&netx_console);
	return 0;
}
console_initcall(netx_console_init);

#define NETX_CONSOLE	&netx_console
#else
#define NETX_CONSOLE	NULL
#endif

static struct uart_driver netx_reg = {
	.owner          = THIS_MODULE,
	.driver_name    = DRIVER_NAME,
	.dev_name       = "ttyNX",
	.major          = SERIAL_NX_MAJOR,
	.minor          = MINOR_START,
	.nr             = ARRAY_SIZE(netx_ports),
	.cons           = NETX_CONSOLE,
};

static int serial_netx_suspend(struct platform_device *pdev, pm_message_t state)
{
	struct netx_port *sport = platform_get_drvdata(pdev);

	if (sport)
		uart_suspend_port(&netx_reg, &sport->port);

	return 0;
}

static int serial_netx_resume(struct platform_device *pdev)
{
	struct netx_port *sport = platform_get_drvdata(pdev);

	if (sport)
		uart_resume_port(&netx_reg, &sport->port);

	return 0;
}

static int serial_netx_probe(struct platform_device *pdev)
{
	struct uart_port *port = &netx_ports[pdev->id].port;

	dev_info(&pdev->dev, "initialising\n");

	port->dev = &pdev->dev;

	writel(1, port->membase + UART_RXFIFO_IRQLEVEL);
	uart_add_one_port(&netx_reg, &netx_ports[pdev->id].port);
	platform_set_drvdata(pdev, &netx_ports[pdev->id]);

	return 0;
}

static int serial_netx_remove(struct platform_device *pdev)
{
	struct netx_port *sport = platform_get_drvdata(pdev);

	if (sport)
		uart_remove_one_port(&netx_reg, &sport->port);

	return 0;
}

static struct platform_driver serial_netx_driver = {
	.probe          = serial_netx_probe,
	.remove         = serial_netx_remove,

	.suspend	= serial_netx_suspend,
	.resume		= serial_netx_resume,

	.driver		= {
		.name   = DRIVER_NAME,
	},
};

static int __init netx_serial_init(void)
{
	int ret;

	printk(KERN_INFO "Serial: NetX driver\n");

	ret = uart_register_driver(&netx_reg);
	if (ret)
		return ret;

	ret = platform_driver_register(&serial_netx_driver);
	if (ret != 0)
		uart_unregister_driver(&netx_reg);

	return 0;
}

static void __exit netx_serial_exit(void)
{
	platform_driver_unregister(&serial_netx_driver);
	uart_unregister_driver(&netx_reg);
}

module_init(netx_serial_init);
module_exit(netx_serial_exit);

MODULE_AUTHOR("Sascha Hauer");
MODULE_DESCRIPTION("NetX serial port driver");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:" DRIVER_NAME);
Commit	Line	Data
e3b3d0f5	1	// SPDX-License-Identifier: GPL-2.0
f8441e13	2	/*
f8441e13	3	* Copyright (c) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
f8441e13 SH	4	*/
f8441e13 SH	5
f8441e13 SH	6	#if defined(CONFIG_SERIAL_NETX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
	7	#define SUPPORT_SYSRQ
	8	#endif
	9
	10	#include <linux/device.h>
	11	#include <linux/module.h>
	12	#include <linux/ioport.h>
	13	#include <linux/init.h>
	14	#include <linux/console.h>
	15	#include <linux/sysrq.h>
	16	#include <linux/platform_device.h>
	17	#include <linux/tty.h>
	18	#include <linux/tty_flip.h>
	19	#include <linux/serial_core.h>
	20	#include <linux/serial.h>
	21
	22	#include <asm/io.h>
	23	#include <asm/irq.h>
a09e64fb RK	24	#include <mach/hardware.h>
a09e64fb RK	25	#include <mach/netx-regs.h>
f8441e13 SH	26
	27	/* We've been assigned a range on the "Low-density serial ports" major */
	28	#define SERIAL_NX_MAJOR 204
	29	#define MINOR_START 170
	30
f8441e13 SH	31	enum uart_regs {
	32	UART_DR = 0x00,
	33	UART_SR = 0x04,
	34	UART_LINE_CR = 0x08,
	35	UART_BAUDDIV_MSB = 0x0c,
	36	UART_BAUDDIV_LSB = 0x10,
	37	UART_CR = 0x14,
	38	UART_FR = 0x18,
	39	UART_IIR = 0x1c,
	40	UART_ILPR = 0x20,
	41	UART_RTS_CR = 0x24,
	42	UART_RTS_LEAD = 0x28,
	43	UART_RTS_TRAIL = 0x2c,
	44	UART_DRV_ENABLE = 0x30,
	45	UART_BRM_CR = 0x34,
	46	UART_RXFIFO_IRQLEVEL = 0x38,
	47	UART_TXFIFO_IRQLEVEL = 0x3c,
	48	};
	49
	50	#define SR_FE (1<<0)
	51	#define SR_PE (1<<1)
	52	#define SR_BE (1<<2)
	53	#define SR_OE (1<<3)
	54
	55	#define LINE_CR_BRK (1<<0)
	56	#define LINE_CR_PEN (1<<1)
	57	#define LINE_CR_EPS (1<<2)
	58	#define LINE_CR_STP2 (1<<3)
	59	#define LINE_CR_FEN (1<<4)
	60	#define LINE_CR_5BIT (0<<5)
	61	#define LINE_CR_6BIT (1<<5)
	62	#define LINE_CR_7BIT (2<<5)
	63	#define LINE_CR_8BIT (3<<5)
	64	#define LINE_CR_BITS_MASK (3<<5)
	65
	66	#define CR_UART_EN (1<<0)
	67	#define CR_SIREN (1<<1)
	68	#define CR_SIRLP (1<<2)
	69	#define CR_MSIE (1<<3)
	70	#define CR_RIE (1<<4)
	71	#define CR_TIE (1<<5)
	72	#define CR_RTIE (1<<6)
	73	#define CR_LBE (1<<7)
	74
	75	#define FR_CTS (1<<0)
	76	#define FR_DSR (1<<1)
	77	#define FR_DCD (1<<2)
	78	#define FR_BUSY (1<<3)
	79	#define FR_RXFE (1<<4)
	80	#define FR_TXFF (1<<5)
	81	#define FR_RXFF (1<<6)
	82	#define FR_TXFE (1<<7)
	83
	84	#define IIR_MIS (1<<0)
	85	#define IIR_RIS (1<<1)
	86	#define IIR_TIS (1<<2)
	87	#define IIR_RTIS (1<<3)
	88	#define IIR_MASK 0xf
	89
	90	#define RTS_CR_AUTO (1<<0)
	91	#define RTS_CR_RTS (1<<1)
	92	#define RTS_CR_COUNT (1<<2)
	93	#define RTS_CR_MOD2 (1<<3)
	94	#define RTS_CR_RTS_POL (1<<4)
95	#define RTS_CR_CTS_CTR (1<<5)
96	#define RTS_CR_CTS_POL (1<<6)
97	#define RTS_CR_STICK (1<<7)
98
99	#define UART_PORT_SIZE 0x40
100	#define DRIVER_NAME "netx-uart"
101
102	struct netx_port {
103	struct uart_port port;
104	};
105
106	static void netx_stop_tx(struct uart_port *port)
107	{
108	unsigned int val;
109	val = readl(port->membase + UART_CR);
110	writel(val & ~CR_TIE, port->membase + UART_CR);
111	}
112
113	static void netx_stop_rx(struct uart_port *port)
114	{
115	unsigned int val;
116	val = readl(port->membase + UART_CR);
117	writel(val & ~CR_RIE, port->membase + UART_CR);
118	}
119
120	static void netx_enable_ms(struct uart_port *port)
121	{
122	unsigned int val;
123	val = readl(port->membase + UART_CR);
124	writel(val \| CR_MSIE, port->membase + UART_CR);
125	}
126
127	static inline void netx_transmit_buffer(struct uart_port *port)
128	{
ebd2c8f6	129	struct circ_buf *xmit = &port->state->xmit;
f8441e13 SH	130
	131	if (port->x_char) {
	132	writel(port->x_char, port->membase + UART_DR);
	133	port->icount.tx++;
	134	port->x_char = 0;
	135	return;
	136	}
	137
	138	if (uart_tx_stopped(port) \|\| uart_circ_empty(xmit)) {
	139	netx_stop_tx(port);
	140	return;
	141	}
	142
	143	do {
	144	/* send xmit->buf[xmit->tail]
	145	* out the port here */
	146	writel(xmit->buf[xmit->tail], port->membase + UART_DR);
	147	xmit->tail = (xmit->tail + 1) &
	148	(UART_XMIT_SIZE - 1);
	149	port->icount.tx++;
	150	if (uart_circ_empty(xmit))
	151	break;
	152	} while (!(readl(port->membase + UART_FR) & FR_TXFF));
	153
	154	if (uart_circ_empty(xmit))
	155	netx_stop_tx(port);
	156	}
	157
	158	static void netx_start_tx(struct uart_port *port)
	159	{
	160	writel(
	161	readl(port->membase + UART_CR) \| CR_TIE, port->membase + UART_CR);
	162
	163	if (!(readl(port->membase + UART_FR) & FR_TXFF))
	164	netx_transmit_buffer(port);
	165	}
	166
	167	static unsigned int netx_tx_empty(struct uart_port *port)
	168	{
	169	return readl(port->membase + UART_FR) & FR_BUSY ? 0 : TIOCSER_TEMT;
	170	}
	171
	172	static void netx_txint(struct uart_port *port)
	173	{
ebd2c8f6	174	struct circ_buf *xmit = &port->state->xmit;
f8441e13 SH	175
	176	if (uart_circ_empty(xmit) \|\| uart_tx_stopped(port)) {
	177	netx_stop_tx(port);
	178	return;
	179	}
	180
	181	netx_transmit_buffer(port);
	182
	183	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
	184	uart_write_wakeup(port);
	185	}
	186
c8db1d97	187	static void netx_rxint(struct uart_port port, unsigned long flags)
f8441e13 SH	188	{
f8441e13 SH	189	unsigned char rx, flg, status;
f8441e13 SH	190
	191	while (!(readl(port->membase + UART_FR) & FR_RXFE)) {
	192	rx = readl(port->membase + UART_DR);
	193	flg = TTY_NORMAL;
	194	port->icount.rx++;
	195	status = readl(port->membase + UART_SR);
	196	if (status & SR_BE) {
	197	writel(0, port->membase + UART_SR);
	198	if (uart_handle_break(port))
	199	continue;
	200	}
	201
	202	if (unlikely(status & (SR_FE \| SR_PE \| SR_OE))) {
	203
	204	if (status & SR_PE)
	205	port->icount.parity++;
	206	else if (status & SR_FE)
	207	port->icount.frame++;
	208	if (status & SR_OE)
	209	port->icount.overrun++;
	210
	211	status &= port->read_status_mask;
	212
	213	if (status & SR_BE)
	214	flg = TTY_BREAK;
	215	else if (status & SR_PE)
	216	flg = TTY_PARITY;
	217	else if (status & SR_FE)
	218	flg = TTY_FRAME;
	219	}
	220
7d12e780	221	if (uart_handle_sysrq_char(port, rx))
f8441e13 SH	222	continue;
	223
	224	uart_insert_char(port, status, SR_OE, rx, flg);
	225	}
	226
c8db1d97	227	spin_unlock_irqrestore(&port->lock, *flags);
2e124b4a	228	tty_flip_buffer_push(&port->state->port);
c8db1d97	229	spin_lock_irqsave(&port->lock, *flags);
f8441e13 SH	230	}
f8441e13 SH	231
7d12e780	232	static irqreturn_t netx_int(int irq, void *dev_id)
f8441e13	233	{
c7bec5ab	234	struct uart_port *port = dev_id;
f8441e13 SH	235	unsigned long flags;
	236	unsigned char status;
	237
	238	spin_lock_irqsave(&port->lock,flags);
	239
	240	status = readl(port->membase + UART_IIR) & IIR_MASK;
	241	while (status) {
	242	if (status & IIR_RIS)
c8db1d97	243	netx_rxint(port, &flags);
f8441e13 SH	244	if (status & IIR_TIS)
	245	netx_txint(port);
	246	if (status & IIR_MIS) {
	247	if (readl(port->membase + UART_FR) & FR_CTS)
	248	uart_handle_cts_change(port, 1);
	249	else
	250	uart_handle_cts_change(port, 0);
	251	}
	252	writel(0, port->membase + UART_IIR);
	253	status = readl(port->membase + UART_IIR) & IIR_MASK;
	254	}
	255
	256	spin_unlock_irqrestore(&port->lock,flags);
	257	return IRQ_HANDLED;
	258	}
	259
	260	static unsigned int netx_get_mctrl(struct uart_port *port)
	261	{
	262	unsigned int ret = TIOCM_DSR \| TIOCM_CAR;
	263
	264	if (readl(port->membase + UART_FR) & FR_CTS)
	265	ret \|= TIOCM_CTS;
	266
	267	return ret;
	268	}
	269
	270	static void netx_set_mctrl(struct uart_port *port, unsigned int mctrl)
	271	{
	272	unsigned int val;
	273
978e595f	274	/* FIXME: Locking needed ? */
f8441e13 SH	275	if (mctrl & TIOCM_RTS) {
	276	val = readl(port->membase + UART_RTS_CR);
	277	writel(val \| RTS_CR_RTS, port->membase + UART_RTS_CR);
	278	}
	279	}
	280
	281	static void netx_break_ctl(struct uart_port *port, int break_state)
	282	{
	283	unsigned int line_cr;
	284	spin_lock_irq(&port->lock);
	285
	286	line_cr = readl(port->membase + UART_LINE_CR);
	287	if (break_state != 0)
	288	line_cr \|= LINE_CR_BRK;
	289	else
	290	line_cr &= ~LINE_CR_BRK;
	291	writel(line_cr, port->membase + UART_LINE_CR);
	292
	293	spin_unlock_irq(&port->lock);
	294	}
	295
	296	static int netx_startup(struct uart_port *port)
	297	{
	298	int ret;
	299
	300	ret = request_irq(port->irq, netx_int, 0,
	301	DRIVER_NAME, port);
	302	if (ret) {
	303	dev_err(port->dev, "unable to grab irq%d\n",port->irq);
	304	goto exit;
	305	}
	306
	307	writel(readl(port->membase + UART_LINE_CR) \| LINE_CR_FEN,
	308	port->membase + UART_LINE_CR);
	309
	310	writel(CR_MSIE \| CR_RIE \| CR_TIE \| CR_RTIE \| CR_UART_EN,
	311	port->membase + UART_CR);
	312
	313	exit:
	314	return ret;
	315	}
	316
	317	static void netx_shutdown(struct uart_port *port)
	318	{
	319	writel(0, port->membase + UART_CR) ;
	320
	321	free_irq(port->irq, port);
	322	}
	323
	324	static void
606d099c AC	325	netx_set_termios(struct uart_port port, struct ktermios termios,
606d099c AC	326	struct ktermios *old)
f8441e13 SH	327	{
	328	unsigned int baud, quot;
	329	unsigned char old_cr;
	330	unsigned char line_cr = LINE_CR_FEN;
	331	unsigned char rts_cr = 0;
	332
	333	switch (termios->c_cflag & CSIZE) {
	334	case CS5:
	335	line_cr \|= LINE_CR_5BIT;
	336	break;
	337	case CS6:
	338	line_cr \|= LINE_CR_6BIT;
	339	break;
	340	case CS7:
	341	line_cr \|= LINE_CR_7BIT;
	342	break;
	343	case CS8:
	344	line_cr \|= LINE_CR_8BIT;
	345	break;
	346	}
	347
	348	if (termios->c_cflag & CSTOPB)
	349	line_cr \|= LINE_CR_STP2;
	350
	351	if (termios->c_cflag & PARENB) {
	352	line_cr \|= LINE_CR_PEN;
	353	if (!(termios->c_cflag & PARODD))
	354	line_cr \|= LINE_CR_EPS;
	355	}
	356
	357	if (termios->c_cflag & CRTSCTS)
	358	rts_cr = RTS_CR_AUTO \| RTS_CR_CTS_CTR \| RTS_CR_RTS_POL;
	359
	360	baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
	361	quot = baud * 4096;
	362	quot /= 1000;
	363	quot *= 256;
	364	quot /= 100000;
	365
	366	spin_lock_irq(&port->lock);
	367
	368	uart_update_timeout(port, termios->c_cflag, baud);
	369
	370	old_cr = readl(port->membase + UART_CR);
	371
	372	/* disable interrupts */
	373	writel(old_cr & ~(CR_MSIE \| CR_RIE \| CR_TIE \| CR_RTIE),
	374	port->membase + UART_CR);
	375
	376	/* drain transmitter */
	377	while (readl(port->membase + UART_FR) & FR_BUSY);
	378
	379	/* disable UART */
	380	writel(old_cr & ~CR_UART_EN, port->membase + UART_CR);
	381
	382	/* modem status interrupts */
	383	old_cr &= ~CR_MSIE;
	384	if (UART_ENABLE_MS(port, termios->c_cflag))
	385	old_cr \|= CR_MSIE;
	386
	387	writel((quot>>8) & 0xff, port->membase + UART_BAUDDIV_MSB);
	388	writel(quot & 0xff, port->membase + UART_BAUDDIV_LSB);
	389	writel(line_cr, port->membase + UART_LINE_CR);
	390
391	writel(rts_cr, port->membase + UART_RTS_CR);
392
393	/*
394	* Characters to ignore
395	*/
396	port->ignore_status_mask = 0;
397	if (termios->c_iflag & IGNPAR)
398	port->ignore_status_mask \|= SR_PE;
399	if (termios->c_iflag & IGNBRK) {
400	port->ignore_status_mask \|= SR_BE;
401	/*
402	* If we're ignoring parity and break indicators,
403	* ignore overruns too (for real raw support).
404	*/
405	if (termios->c_iflag & IGNPAR)
406	port->ignore_status_mask \|= SR_PE;
407	}
408
409	port->read_status_mask = 0;
ef8b9ddc	410	if (termios->c_iflag & (IGNBRK \| BRKINT \| PARMRK))
f8441e13 SH	411	port->read_status_mask \|= SR_BE;
	412	if (termios->c_iflag & INPCK)
	413	port->read_status_mask \|= SR_PE \| SR_FE;
	414
	415	writel(old_cr, port->membase + UART_CR);
	416
	417	spin_unlock_irq(&port->lock);
	418	}
	419
	420	static const char netx_type(struct uart_port port)
	421	{
	422	return port->type == PORT_NETX ? "NETX" : NULL;
	423	}
	424
	425	static void netx_release_port(struct uart_port *port)
	426	{
	427	release_mem_region(port->mapbase, UART_PORT_SIZE);
	428	}
	429
	430	static int netx_request_port(struct uart_port *port)
	431	{
	432	return request_mem_region(port->mapbase, UART_PORT_SIZE,
	433	DRIVER_NAME) != NULL ? 0 : -EBUSY;
	434	}
	435
	436	static void netx_config_port(struct uart_port *port, int flags)
	437	{
	438	if (flags & UART_CONFIG_TYPE && netx_request_port(port) == 0)
	439	port->type = PORT_NETX;
	440	}
	441
	442	static int
	443	netx_verify_port(struct uart_port port, struct serial_struct ser)
	444	{
	445	int ret = 0;
	446
	447	if (ser->type != PORT_UNKNOWN && ser->type != PORT_NETX)
	448	ret = -EINVAL;
	449
	450	return ret;
	451	}
	452
	453	static struct uart_ops netx_pops = {
	454	.tx_empty = netx_tx_empty,
	455	.set_mctrl = netx_set_mctrl,
	456	.get_mctrl = netx_get_mctrl,
	457	.stop_tx = netx_stop_tx,
	458	.start_tx = netx_start_tx,
	459	.stop_rx = netx_stop_rx,
	460	.enable_ms = netx_enable_ms,
	461	.break_ctl = netx_break_ctl,
	462	.startup = netx_startup,
	463	.shutdown = netx_shutdown,
	464	.set_termios = netx_set_termios,
	465	.type = netx_type,
	466	.release_port = netx_release_port,
	467	.request_port = netx_request_port,
	468	.config_port = netx_config_port,
	469	.verify_port = netx_verify_port,
	470	};
	471
	472	static struct netx_port netx_ports[] = {
	473	{
	474	.port = {
475	.type = PORT_NETX,
476	.iotype = UPIO_MEM,
477	.membase = (char __iomem *)io_p2v(NETX_PA_UART0),
478	.mapbase = NETX_PA_UART0,
479	.irq = NETX_IRQ_UART0,
480	.uartclk = 100000000,
481	.fifosize = 16,
482	.flags = UPF_BOOT_AUTOCONF,
483	.ops = &netx_pops,
484	.line = 0,
485	},
486	}, {
487	.port = {
488	.type = PORT_NETX,
489	.iotype = UPIO_MEM,
490	.membase = (char __iomem *)io_p2v(NETX_PA_UART1),
491	.mapbase = NETX_PA_UART1,
492	.irq = NETX_IRQ_UART1,
493	.uartclk = 100000000,
494	.fifosize = 16,
495	.flags = UPF_BOOT_AUTOCONF,
496	.ops = &netx_pops,
497	.line = 1,
498	},
499	}, {
500	.port = {
501	.type = PORT_NETX,
502	.iotype = UPIO_MEM,
503	.membase = (char __iomem *)io_p2v(NETX_PA_UART2),
504	.mapbase = NETX_PA_UART2,
505	.irq = NETX_IRQ_UART2,
506	.uartclk = 100000000,
507	.fifosize = 16,
508	.flags = UPF_BOOT_AUTOCONF,
509	.ops = &netx_pops,
510	.line = 2,
511	},
512	}
513	};
514
fb881f78 PB	515	#ifdef CONFIG_SERIAL_NETX_CONSOLE
fb881f78 PB	516
f8441e13 SH	517	static void netx_console_putchar(struct uart_port *port, int ch)
	518	{
	519	while (readl(port->membase + UART_FR) & FR_BUSY);
	520	writel(ch, port->membase + UART_DR);
	521	}
	522
	523	static void
	524	netx_console_write(struct console co, const char s, unsigned int count)
	525	{
	526	struct uart_port *port = &netx_ports[co->index].port;
	527	unsigned char cr_save;
	528
	529	cr_save = readl(port->membase + UART_CR);
	530	writel(cr_save \| CR_UART_EN, port->membase + UART_CR);
	531
	532	uart_console_write(port, s, count, netx_console_putchar);
	533
	534	while (readl(port->membase + UART_FR) & FR_BUSY);
	535	writel(cr_save, port->membase + UART_CR);
	536	}
	537
	538	static void __init
	539	netx_console_get_options(struct uart_port port, int baud,
	540	int parity, int bits, int *flow)
	541	{
	542	unsigned char line_cr;
	543
	544	*baud = (readl(port->membase + UART_BAUDDIV_MSB) << 8) \|
	545	readl(port->membase + UART_BAUDDIV_LSB);
	546	baud = 1000;
	547	*baud /= 4096;
	548	baud = 1000;
	549	*baud /= 256;
	550	baud = 100;
	551
	552	line_cr = readl(port->membase + UART_LINE_CR);
	553	*parity = 'n';
	554	if (line_cr & LINE_CR_PEN) {
	555	if (line_cr & LINE_CR_EPS)
	556	*parity = 'e';
	557	else
	558	*parity = 'o';
	559	}
	560
	561	switch (line_cr & LINE_CR_BITS_MASK) {
	562	case LINE_CR_8BIT:
	563	*bits = 8;
	564	break;
	565	case LINE_CR_7BIT:
	566	*bits = 7;
	567	break;
	568	case LINE_CR_6BIT:
	569	*bits = 6;
	570	break;
	571	case LINE_CR_5BIT:
	572	*bits = 5;
	573	break;
	574	}
	575
	576	if (readl(port->membase + UART_RTS_CR) & RTS_CR_AUTO)
	577	*flow = 'r';
	578	}
	579
	580	static int __init
581	netx_console_setup(struct console co, char options)
582	{
583	struct netx_port *sport;
584	int baud = 9600;
585	int bits = 8;
586	int parity = 'n';
587	int flow = 'n';
588
589	/*
590	* Check whether an invalid uart number has been specified, and
591	* if so, search for the first available port that does have
592	* console support.
593	*/
594	if (co->index == -1 \|\| co->index >= ARRAY_SIZE(netx_ports))
595	co->index = 0;
596	sport = &netx_ports[co->index];
597
598	if (options) {
599	uart_parse_options(options, &baud, &parity, &bits, &flow);
600	} else {
601	/* if the UART is enabled, assume it has been correctly setup
602	* by the bootloader and get the options
603	*/
604	if (readl(sport->port.membase + UART_CR) & CR_UART_EN) {
605	netx_console_get_options(&sport->port, &baud,
606	&parity, &bits, &flow);
607	}
608
609	}
610
611	return uart_set_options(&sport->port, co, baud, parity, bits, flow);
612	}
613
614	static struct uart_driver netx_reg;
615	static struct console netx_console = {
616	.name = "ttyNX",
617	.write = netx_console_write,
618	.device = uart_console_device,
619	.setup = netx_console_setup,
620	.flags = CON_PRINTBUFFER,
621	.index = -1,
622	.data = &netx_reg,
623	};
624
625	static int __init netx_console_init(void)
626	{
627	register_console(&netx_console);
628	return 0;
629	}
630	console_initcall(netx_console_init);
631
632	#define NETX_CONSOLE &netx_console
633	#else
634	#define NETX_CONSOLE NULL
635	#endif
636
637	static struct uart_driver netx_reg = {
638	.owner = THIS_MODULE,
639	.driver_name = DRIVER_NAME,
640	.dev_name = "ttyNX",
641	.major = SERIAL_NX_MAJOR,
642	.minor = MINOR_START,
643	.nr = ARRAY_SIZE(netx_ports),
644	.cons = NETX_CONSOLE,
645	};
646
647	static int serial_netx_suspend(struct platform_device *pdev, pm_message_t state)
648	{
649	struct netx_port *sport = platform_get_drvdata(pdev);
650
651	if (sport)
652	uart_suspend_port(&netx_reg, &sport->port);
653
654	return 0;
655	}
656
657	static int serial_netx_resume(struct platform_device *pdev)
658	{
659	struct netx_port *sport = platform_get_drvdata(pdev);
660
661	if (sport)
662	uart_resume_port(&netx_reg, &sport->port);
663
664	return 0;
665	}
666
667	static int serial_netx_probe(struct platform_device *pdev)
668	{
669	struct uart_port *port = &netx_ports[pdev->id].port;
670
671	dev_info(&pdev->dev, "initialising\n");
672
673	port->dev = &pdev->dev;
674
675	writel(1, port->membase + UART_RXFIFO_IRQLEVEL);
676	uart_add_one_port(&netx_reg, &netx_ports[pdev->id].port);
677	platform_set_drvdata(pdev, &netx_ports[pdev->id]);
678
679	return 0;
680	}
681
682	static int serial_netx_remove(struct platform_device *pdev)
683	{
684	struct netx_port *sport = platform_get_drvdata(pdev);
685
f8441e13 SH	686	if (sport)
	687	uart_remove_one_port(&netx_reg, &sport->port);
	688
	689	return 0;
	690	}
	691
	692	static struct platform_driver serial_netx_driver = {
	693	.probe = serial_netx_probe,
	694	.remove = serial_netx_remove,
	695
	696	.suspend = serial_netx_suspend,
	697	.resume = serial_netx_resume,
	698
	699	.driver = {
	700	.name = DRIVER_NAME,
	701	},
	702	};
	703
	704	static int __init netx_serial_init(void)
	705	{
	706	int ret;
	707
	708	printk(KERN_INFO "Serial: NetX driver\n");
	709
	710	ret = uart_register_driver(&netx_reg);
	711	if (ret)
	712	return ret;
	713
	714	ret = platform_driver_register(&serial_netx_driver);
	715	if (ret != 0)
	716	uart_unregister_driver(&netx_reg);
	717
	718	return 0;
	719	}
	720
	721	static void __exit netx_serial_exit(void)
	722	{
	723	platform_driver_unregister(&serial_netx_driver);
	724	uart_unregister_driver(&netx_reg);
	725	}
	726
	727	module_init(netx_serial_init);
	728	module_exit(netx_serial_exit);
	729
	730	MODULE_AUTHOR("Sascha Hauer");
	731	MODULE_DESCRIPTION("NetX serial port driver");
	732	MODULE_LICENSE("GPL");
e169c139	733	MODULE_ALIAS("platform:" DRIVER_NAME);