[linux-block.git] / drivers / tty / serial / netx-serial.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (c) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2
 * as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */

#if defined(CONFIG_SERIAL_NETX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
#define SUPPORT_SYSRQ
#endif

#include <linux/device.h>
#include <linux/module.h>
#include <linux/ioport.h>
#include <linux/init.h>
#include <linux/console.h>
#include <linux/sysrq.h>
#include <linux/platform_device.h>
#include <linux/tty.h>
#include <linux/tty_flip.h>
#include <linux/serial_core.h>
#include <linux/serial.h>

#include <asm/io.h>
#include <asm/irq.h>
#include <mach/hardware.h>
#include <mach/netx-regs.h>

/* We've been assigned a range on the "Low-density serial ports" major */
#define SERIAL_NX_MAJOR	204
#define MINOR_START	170

enum uart_regs {
	UART_DR              = 0x00,
	UART_SR              = 0x04,
	UART_LINE_CR         = 0x08,
	UART_BAUDDIV_MSB     = 0x0c,
	UART_BAUDDIV_LSB     = 0x10,
	UART_CR              = 0x14,
	UART_FR              = 0x18,
	UART_IIR             = 0x1c,
	UART_ILPR            = 0x20,
	UART_RTS_CR          = 0x24,
	UART_RTS_LEAD        = 0x28,
	UART_RTS_TRAIL       = 0x2c,
	UART_DRV_ENABLE      = 0x30,
	UART_BRM_CR          = 0x34,
	UART_RXFIFO_IRQLEVEL = 0x38,
	UART_TXFIFO_IRQLEVEL = 0x3c,
};

#define SR_FE (1<<0)
#define SR_PE (1<<1)
#define SR_BE (1<<2)
#define SR_OE (1<<3)

#define LINE_CR_BRK       (1<<0)
#define LINE_CR_PEN       (1<<1)
#define LINE_CR_EPS       (1<<2)
#define LINE_CR_STP2      (1<<3)
#define LINE_CR_FEN       (1<<4)
#define LINE_CR_5BIT      (0<<5)
#define LINE_CR_6BIT      (1<<5)
#define LINE_CR_7BIT      (2<<5)
#define LINE_CR_8BIT      (3<<5)
#define LINE_CR_BITS_MASK (3<<5)

#define CR_UART_EN (1<<0)
#define CR_SIREN   (1<<1)
#define CR_SIRLP   (1<<2)
#define CR_MSIE    (1<<3)
#define CR_RIE     (1<<4)
#define CR_TIE     (1<<5)
#define CR_RTIE    (1<<6)
#define CR_LBE     (1<<7)

#define FR_CTS  (1<<0)
#define FR_DSR  (1<<1)
#define FR_DCD  (1<<2)
#define FR_BUSY (1<<3)
#define FR_RXFE (1<<4)
#define FR_TXFF (1<<5)
#define FR_RXFF (1<<6)
#define FR_TXFE (1<<7)

#define IIR_MIS (1<<0)
#define IIR_RIS (1<<1)
#define IIR_TIS (1<<2)
#define IIR_RTIS (1<<3)
#define IIR_MASK 0xf

#define RTS_CR_AUTO (1<<0)
#define RTS_CR_RTS  (1<<1)
#define RTS_CR_COUNT (1<<2)
#define RTS_CR_MOD2  (1<<3)
#define RTS_CR_RTS_POL (1<<4)
#define RTS_CR_CTS_CTR (1<<5)
#define RTS_CR_CTS_POL (1<<6)
#define RTS_CR_STICK   (1<<7)

#define UART_PORT_SIZE 0x40
#define DRIVER_NAME "netx-uart"

struct netx_port {
	struct uart_port	port;
};

static void netx_stop_tx(struct uart_port *port)
{
	unsigned int val;
	val = readl(port->membase + UART_CR);
	writel(val & ~CR_TIE,  port->membase + UART_CR);
}

static void netx_stop_rx(struct uart_port *port)
{
	unsigned int val;
	val = readl(port->membase + UART_CR);
	writel(val & ~CR_RIE,  port->membase + UART_CR);
}

static void netx_enable_ms(struct uart_port *port)
{
	unsigned int val;
	val = readl(port->membase + UART_CR);
	writel(val | CR_MSIE, port->membase + UART_CR);
}

static inline void netx_transmit_buffer(struct uart_port *port)
{
	struct circ_buf *xmit = &port->state->xmit;

	if (port->x_char) {
		writel(port->x_char, port->membase + UART_DR);
		port->icount.tx++;
		port->x_char = 0;
		return;
	}

	if (uart_tx_stopped(port) || uart_circ_empty(xmit)) {
		netx_stop_tx(port);
		return;
	}

	do {
		/* send xmit->buf[xmit->tail]
		 * out the port here */
		writel(xmit->buf[xmit->tail], port->membase + UART_DR);
		xmit->tail = (xmit->tail + 1) &
		         (UART_XMIT_SIZE - 1);
		port->icount.tx++;
		if (uart_circ_empty(xmit))
			break;
	} while (!(readl(port->membase + UART_FR) & FR_TXFF));

	if (uart_circ_empty(xmit))
		netx_stop_tx(port);
}

static void netx_start_tx(struct uart_port *port)
{
	writel(
	    readl(port->membase + UART_CR) | CR_TIE, port->membase + UART_CR);

	if (!(readl(port->membase + UART_FR) & FR_TXFF))
		netx_transmit_buffer(port);
}

static unsigned int netx_tx_empty(struct uart_port *port)
{
	return readl(port->membase + UART_FR) & FR_BUSY ? 0 : TIOCSER_TEMT;
}

static void netx_txint(struct uart_port *port)
{
	struct circ_buf *xmit = &port->state->xmit;

	if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
		netx_stop_tx(port);
		return;
	}

	netx_transmit_buffer(port);

	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
		uart_write_wakeup(port);
}

static void netx_rxint(struct uart_port *port, unsigned long *flags)
{
	unsigned char rx, flg, status;

	while (!(readl(port->membase + UART_FR) & FR_RXFE)) {
		rx = readl(port->membase + UART_DR);
		flg = TTY_NORMAL;
		port->icount.rx++;
		status = readl(port->membase + UART_SR);
		if (status & SR_BE) {
			writel(0, port->membase + UART_SR);
			if (uart_handle_break(port))
				continue;
		}

		if (unlikely(status & (SR_FE | SR_PE | SR_OE))) {

			if (status & SR_PE)
				port->icount.parity++;
			else if (status & SR_FE)
				port->icount.frame++;
			if (status & SR_OE)
				port->icount.overrun++;

			status &= port->read_status_mask;

			if (status & SR_BE)
				flg = TTY_BREAK;
			else if (status & SR_PE)
				flg = TTY_PARITY;
			else if (status & SR_FE)
				flg = TTY_FRAME;
		}

		if (uart_handle_sysrq_char(port, rx))
			continue;

		uart_insert_char(port, status, SR_OE, rx, flg);
	}

	spin_unlock_irqrestore(&port->lock, *flags);
	tty_flip_buffer_push(&port->state->port);
	spin_lock_irqsave(&port->lock, *flags);
}

static irqreturn_t netx_int(int irq, void *dev_id)
{
	struct uart_port *port = dev_id;
	unsigned long flags;
	unsigned char status;

	spin_lock_irqsave(&port->lock,flags);

	status = readl(port->membase + UART_IIR) & IIR_MASK;
	while (status) {
		if (status & IIR_RIS)
			netx_rxint(port, &flags);
		if (status & IIR_TIS)
			netx_txint(port);
		if (status & IIR_MIS) {
			if (readl(port->membase + UART_FR) & FR_CTS)
				uart_handle_cts_change(port, 1);
			else
				uart_handle_cts_change(port, 0);
		}
		writel(0, port->membase + UART_IIR);
		status = readl(port->membase + UART_IIR) & IIR_MASK;
	}

	spin_unlock_irqrestore(&port->lock,flags);
	return IRQ_HANDLED;
}

static unsigned int netx_get_mctrl(struct uart_port *port)
{
	unsigned int ret = TIOCM_DSR | TIOCM_CAR;

	if (readl(port->membase + UART_FR) & FR_CTS)
		ret |= TIOCM_CTS;

	return ret;
}

static void netx_set_mctrl(struct uart_port *port, unsigned int mctrl)
{
	unsigned int val;

	/* FIXME: Locking needed ? */
	if (mctrl & TIOCM_RTS) {
		val = readl(port->membase + UART_RTS_CR);
		writel(val | RTS_CR_RTS, port->membase + UART_RTS_CR);
	}
}

static void netx_break_ctl(struct uart_port *port, int break_state)
{
	unsigned int line_cr;
	spin_lock_irq(&port->lock);

	line_cr = readl(port->membase + UART_LINE_CR);
	if (break_state != 0)
		line_cr |= LINE_CR_BRK;
	else
		line_cr &= ~LINE_CR_BRK;
	writel(line_cr, port->membase + UART_LINE_CR);

	spin_unlock_irq(&port->lock);
}

static int netx_startup(struct uart_port *port)
{
	int ret;

	ret = request_irq(port->irq, netx_int, 0,
			     DRIVER_NAME, port);
	if (ret) {
		dev_err(port->dev, "unable to grab irq%d\n",port->irq);
		goto exit;
	}

	writel(readl(port->membase + UART_LINE_CR) | LINE_CR_FEN,
		port->membase + UART_LINE_CR);

	writel(CR_MSIE | CR_RIE | CR_TIE | CR_RTIE | CR_UART_EN,
		port->membase + UART_CR);

exit:
	return ret;
}

static void netx_shutdown(struct uart_port *port)
{
	writel(0, port->membase + UART_CR) ;

	free_irq(port->irq, port);
}

static void
netx_set_termios(struct uart_port *port, struct ktermios *termios,
		   struct ktermios *old)
{
	unsigned int baud, quot;
	unsigned char old_cr;
	unsigned char line_cr = LINE_CR_FEN;
	unsigned char rts_cr = 0;

	switch (termios->c_cflag & CSIZE) {
	case CS5:
		line_cr |= LINE_CR_5BIT;
		break;
	case CS6:
		line_cr |= LINE_CR_6BIT;
		break;
	case CS7:
		line_cr |= LINE_CR_7BIT;
		break;
	case CS8:
		line_cr |= LINE_CR_8BIT;
		break;
	}

	if (termios->c_cflag & CSTOPB)
		line_cr |= LINE_CR_STP2;

	if (termios->c_cflag & PARENB) {
		line_cr |= LINE_CR_PEN;
		if (!(termios->c_cflag & PARODD))
			line_cr |= LINE_CR_EPS;
	}

	if (termios->c_cflag & CRTSCTS)
		rts_cr = RTS_CR_AUTO | RTS_CR_CTS_CTR | RTS_CR_RTS_POL;

	baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
	quot = baud * 4096;
	quot /= 1000;
	quot *= 256;
	quot /= 100000;

	spin_lock_irq(&port->lock);

	uart_update_timeout(port, termios->c_cflag, baud);

	old_cr = readl(port->membase + UART_CR);

	/* disable interrupts */
	writel(old_cr & ~(CR_MSIE | CR_RIE | CR_TIE | CR_RTIE),
		port->membase + UART_CR);

	/* drain transmitter */
	while (readl(port->membase + UART_FR) & FR_BUSY);

	/* disable UART */
	writel(old_cr & ~CR_UART_EN, port->membase + UART_CR);

	/* modem status interrupts */
	old_cr &= ~CR_MSIE;
	if (UART_ENABLE_MS(port, termios->c_cflag))
		old_cr |= CR_MSIE;

	writel((quot>>8) & 0xff, port->membase + UART_BAUDDIV_MSB);
	writel(quot & 0xff, port->membase + UART_BAUDDIV_LSB);
	writel(line_cr, port->membase + UART_LINE_CR);

	writel(rts_cr, port->membase + UART_RTS_CR);

	/*
	 * Characters to ignore
	 */
	port->ignore_status_mask = 0;
	if (termios->c_iflag & IGNPAR)
		port->ignore_status_mask |= SR_PE;
	if (termios->c_iflag & IGNBRK) {
		port->ignore_status_mask |= SR_BE;
		/*
		 * If we're ignoring parity and break indicators,
		 * ignore overruns too (for real raw support).
		 */
		if (termios->c_iflag & IGNPAR)
			port->ignore_status_mask |= SR_PE;
	}

	port->read_status_mask = 0;
	if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
		port->read_status_mask |= SR_BE;
	if (termios->c_iflag & INPCK)
		port->read_status_mask |= SR_PE | SR_FE;

	writel(old_cr, port->membase + UART_CR);

	spin_unlock_irq(&port->lock);
}

static const char *netx_type(struct uart_port *port)
{
	return port->type == PORT_NETX ? "NETX" : NULL;
}

static void netx_release_port(struct uart_port *port)
{
	release_mem_region(port->mapbase, UART_PORT_SIZE);
}

static int netx_request_port(struct uart_port *port)
{
	return request_mem_region(port->mapbase, UART_PORT_SIZE,
			DRIVER_NAME) != NULL ? 0 : -EBUSY;
}

static void netx_config_port(struct uart_port *port, int flags)
{
	if (flags & UART_CONFIG_TYPE && netx_request_port(port) == 0)
		port->type = PORT_NETX;
}

static int
netx_verify_port(struct uart_port *port, struct serial_struct *ser)
{
	int ret = 0;

	if (ser->type != PORT_UNKNOWN && ser->type != PORT_NETX)
		ret = -EINVAL;

	return ret;
}

static struct uart_ops netx_pops = {
	.tx_empty	= netx_tx_empty,
	.set_mctrl	= netx_set_mctrl,
	.get_mctrl	= netx_get_mctrl,
	.stop_tx	= netx_stop_tx,
	.start_tx	= netx_start_tx,
	.stop_rx	= netx_stop_rx,
	.enable_ms	= netx_enable_ms,
	.break_ctl	= netx_break_ctl,
	.startup	= netx_startup,
	.shutdown	= netx_shutdown,
	.set_termios	= netx_set_termios,
	.type		= netx_type,
	.release_port	= netx_release_port,
	.request_port	= netx_request_port,
	.config_port	= netx_config_port,
	.verify_port	= netx_verify_port,
};

static struct netx_port netx_ports[] = {
	{
	.port = {
		.type = PORT_NETX,
		.iotype = UPIO_MEM,
		.membase = (char __iomem *)io_p2v(NETX_PA_UART0),
		.mapbase = NETX_PA_UART0,
		.irq = NETX_IRQ_UART0,
		.uartclk = 100000000,
		.fifosize = 16,
		.flags = UPF_BOOT_AUTOCONF,
		.ops = &netx_pops,
		.line = 0,
	},
	}, {
	.port = {
		.type = PORT_NETX,
		.iotype = UPIO_MEM,
		.membase = (char __iomem *)io_p2v(NETX_PA_UART1),
		.mapbase = NETX_PA_UART1,
		.irq = NETX_IRQ_UART1,
		.uartclk = 100000000,
		.fifosize = 16,
		.flags = UPF_BOOT_AUTOCONF,
		.ops = &netx_pops,
		.line = 1,
	},
	}, {
	.port = {
		.type = PORT_NETX,
		.iotype = UPIO_MEM,
		.membase = (char __iomem *)io_p2v(NETX_PA_UART2),
		.mapbase = NETX_PA_UART2,
		.irq = NETX_IRQ_UART2,
		.uartclk = 100000000,
		.fifosize = 16,
		.flags = UPF_BOOT_AUTOCONF,
		.ops = &netx_pops,
		.line = 2,
	},
	}
};

#ifdef CONFIG_SERIAL_NETX_CONSOLE

static void netx_console_putchar(struct uart_port *port, int ch)
{
	while (readl(port->membase + UART_FR) & FR_BUSY);
	writel(ch, port->membase + UART_DR);
}

static void
netx_console_write(struct console *co, const char *s, unsigned int count)
{
	struct uart_port *port = &netx_ports[co->index].port;
	unsigned char cr_save;

	cr_save = readl(port->membase + UART_CR);
	writel(cr_save | CR_UART_EN, port->membase + UART_CR);

	uart_console_write(port, s, count, netx_console_putchar);

	while (readl(port->membase + UART_FR) & FR_BUSY);
	writel(cr_save, port->membase + UART_CR);
}

static void __init
netx_console_get_options(struct uart_port *port, int *baud,
			int *parity, int *bits, int *flow)
{
	unsigned char line_cr;

	*baud = (readl(port->membase + UART_BAUDDIV_MSB) << 8) |
		readl(port->membase + UART_BAUDDIV_LSB);
	*baud *= 1000;
	*baud /= 4096;
	*baud *= 1000;
	*baud /= 256;
	*baud *= 100;

	line_cr = readl(port->membase + UART_LINE_CR);
	*parity = 'n';
	if (line_cr & LINE_CR_PEN) {
		if (line_cr & LINE_CR_EPS)
			*parity = 'e';
		else
			*parity = 'o';
	}

	switch (line_cr & LINE_CR_BITS_MASK) {
	case LINE_CR_8BIT:
		*bits = 8;
		break;
	case LINE_CR_7BIT:
		*bits = 7;
		break;
	case LINE_CR_6BIT:
		*bits = 6;
		break;
	case LINE_CR_5BIT:
		*bits = 5;
		break;
	}

	if (readl(port->membase + UART_RTS_CR) & RTS_CR_AUTO)
		*flow = 'r';
}

static int __init
netx_console_setup(struct console *co, char *options)
{
	struct netx_port *sport;
	int baud = 9600;
	int bits = 8;
	int parity = 'n';
	int flow = 'n';

	/*
	 * Check whether an invalid uart number has been specified, and
	 * if so, search for the first available port that does have
	 * console support.
	 */
	if (co->index == -1 || co->index >= ARRAY_SIZE(netx_ports))
		co->index = 0;
	sport = &netx_ports[co->index];

	if (options) {
		uart_parse_options(options, &baud, &parity, &bits, &flow);
	} else {
		/* if the UART is enabled, assume it has been correctly setup
		 * by the bootloader and get the options
		 */
		if (readl(sport->port.membase + UART_CR) & CR_UART_EN) {
			netx_console_get_options(&sport->port, &baud,
			&parity, &bits, &flow);
		}

	}

	return uart_set_options(&sport->port, co, baud, parity, bits, flow);
}

static struct uart_driver netx_reg;
static struct console netx_console = {
	.name		= "ttyNX",
	.write		= netx_console_write,
	.device		= uart_console_device,
	.setup		= netx_console_setup,
	.flags		= CON_PRINTBUFFER,
	.index		= -1,
	.data		= &netx_reg,
};

static int __init netx_console_init(void)
{
	register_console(&netx_console);
	return 0;
}
console_initcall(netx_console_init);

#define NETX_CONSOLE	&netx_console
#else
#define NETX_CONSOLE	NULL
#endif

static struct uart_driver netx_reg = {
	.owner          = THIS_MODULE,
	.driver_name    = DRIVER_NAME,
	.dev_name       = "ttyNX",
	.major          = SERIAL_NX_MAJOR,
	.minor          = MINOR_START,
	.nr             = ARRAY_SIZE(netx_ports),
	.cons           = NETX_CONSOLE,
};

static int serial_netx_suspend(struct platform_device *pdev, pm_message_t state)
{
	struct netx_port *sport = platform_get_drvdata(pdev);

	if (sport)
		uart_suspend_port(&netx_reg, &sport->port);

	return 0;
}

static int serial_netx_resume(struct platform_device *pdev)
{
	struct netx_port *sport = platform_get_drvdata(pdev);

	if (sport)
		uart_resume_port(&netx_reg, &sport->port);

	return 0;
}

static int serial_netx_probe(struct platform_device *pdev)
{
	struct uart_port *port = &netx_ports[pdev->id].port;

	dev_info(&pdev->dev, "initialising\n");

	port->dev = &pdev->dev;

	writel(1, port->membase + UART_RXFIFO_IRQLEVEL);
	uart_add_one_port(&netx_reg, &netx_ports[pdev->id].port);
	platform_set_drvdata(pdev, &netx_ports[pdev->id]);

	return 0;
}

static int serial_netx_remove(struct platform_device *pdev)
{
	struct netx_port *sport = platform_get_drvdata(pdev);

	if (sport)
		uart_remove_one_port(&netx_reg, &sport->port);

	return 0;
}

static struct platform_driver serial_netx_driver = {
	.probe          = serial_netx_probe,
	.remove         = serial_netx_remove,

	.suspend	= serial_netx_suspend,
	.resume		= serial_netx_resume,

	.driver		= {
		.name   = DRIVER_NAME,
	},
};

static int __init netx_serial_init(void)
{
	int ret;

	printk(KERN_INFO "Serial: NetX driver\n");

	ret = uart_register_driver(&netx_reg);
	if (ret)
		return ret;

	ret = platform_driver_register(&serial_netx_driver);
	if (ret != 0)
		uart_unregister_driver(&netx_reg);

	return 0;
}

static void __exit netx_serial_exit(void)
{
	platform_driver_unregister(&serial_netx_driver);
	uart_unregister_driver(&netx_reg);
}

module_init(netx_serial_init);
module_exit(netx_serial_exit);

MODULE_AUTHOR("Sascha Hauer");
MODULE_DESCRIPTION("NetX serial port driver");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:" DRIVER_NAME);
Commit	Line	Data
e3b3d0f5	1	// SPDX-License-Identifier: GPL-2.0
f8441e13	2	/*
f8441e13 SH	3	* Copyright (c) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
	4	*
	5	* This program is free software; you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License version 2
	7	* as published by the Free Software Foundation.
	8	*
	9	* This program is distributed in the hope that it will be useful,
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	* GNU General Public License for more details.
	13	*
	14	* You should have received a copy of the GNU General Public License
	15	* along with this program; if not, write to the Free Software
	16	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	17	*/
	18
f8441e13 SH	19	#if defined(CONFIG_SERIAL_NETX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
	20	#define SUPPORT_SYSRQ
	21	#endif
	22
	23	#include <linux/device.h>
	24	#include <linux/module.h>
	25	#include <linux/ioport.h>
	26	#include <linux/init.h>
	27	#include <linux/console.h>
	28	#include <linux/sysrq.h>
	29	#include <linux/platform_device.h>
	30	#include <linux/tty.h>
	31	#include <linux/tty_flip.h>
	32	#include <linux/serial_core.h>
	33	#include <linux/serial.h>
	34
	35	#include <asm/io.h>
	36	#include <asm/irq.h>
a09e64fb RK	37	#include <mach/hardware.h>
a09e64fb RK	38	#include <mach/netx-regs.h>
f8441e13 SH	39
	40	/* We've been assigned a range on the "Low-density serial ports" major */
	41	#define SERIAL_NX_MAJOR 204
	42	#define MINOR_START 170
	43
f8441e13 SH	44	enum uart_regs {
	45	UART_DR = 0x00,
	46	UART_SR = 0x04,
	47	UART_LINE_CR = 0x08,
	48	UART_BAUDDIV_MSB = 0x0c,
	49	UART_BAUDDIV_LSB = 0x10,
	50	UART_CR = 0x14,
	51	UART_FR = 0x18,
	52	UART_IIR = 0x1c,
	53	UART_ILPR = 0x20,
	54	UART_RTS_CR = 0x24,
	55	UART_RTS_LEAD = 0x28,
	56	UART_RTS_TRAIL = 0x2c,
	57	UART_DRV_ENABLE = 0x30,
	58	UART_BRM_CR = 0x34,
	59	UART_RXFIFO_IRQLEVEL = 0x38,
	60	UART_TXFIFO_IRQLEVEL = 0x3c,
	61	};
	62
	63	#define SR_FE (1<<0)
	64	#define SR_PE (1<<1)
	65	#define SR_BE (1<<2)
	66	#define SR_OE (1<<3)
	67
	68	#define LINE_CR_BRK (1<<0)
	69	#define LINE_CR_PEN (1<<1)
	70	#define LINE_CR_EPS (1<<2)
	71	#define LINE_CR_STP2 (1<<3)
	72	#define LINE_CR_FEN (1<<4)
	73	#define LINE_CR_5BIT (0<<5)
	74	#define LINE_CR_6BIT (1<<5)
	75	#define LINE_CR_7BIT (2<<5)
	76	#define LINE_CR_8BIT (3<<5)
	77	#define LINE_CR_BITS_MASK (3<<5)
	78
	79	#define CR_UART_EN (1<<0)
	80	#define CR_SIREN (1<<1)
	81	#define CR_SIRLP (1<<2)
	82	#define CR_MSIE (1<<3)
	83	#define CR_RIE (1<<4)
	84	#define CR_TIE (1<<5)
	85	#define CR_RTIE (1<<6)
	86	#define CR_LBE (1<<7)
	87
	88	#define FR_CTS (1<<0)
	89	#define FR_DSR (1<<1)
	90	#define FR_DCD (1<<2)
	91	#define FR_BUSY (1<<3)
	92	#define FR_RXFE (1<<4)
	93	#define FR_TXFF (1<<5)
	94	#define FR_RXFF (1<<6)
	95	#define FR_TXFE (1<<7)
	96
	97	#define IIR_MIS (1<<0)
	98	#define IIR_RIS (1<<1)
	99	#define IIR_TIS (1<<2)
	100	#define IIR_RTIS (1<<3)
	101	#define IIR_MASK 0xf
	102
	103	#define RTS_CR_AUTO (1<<0)
	104	#define RTS_CR_RTS (1<<1)
	105	#define RTS_CR_COUNT (1<<2)
	106	#define RTS_CR_MOD2 (1<<3)
	107	#define RTS_CR_RTS_POL (1<<4)
108	#define RTS_CR_CTS_CTR (1<<5)
109	#define RTS_CR_CTS_POL (1<<6)
110	#define RTS_CR_STICK (1<<7)
111
112	#define UART_PORT_SIZE 0x40
113	#define DRIVER_NAME "netx-uart"
114
115	struct netx_port {
116	struct uart_port port;
117	};
118
119	static void netx_stop_tx(struct uart_port *port)
120	{
121	unsigned int val;
122	val = readl(port->membase + UART_CR);
123	writel(val & ~CR_TIE, port->membase + UART_CR);
124	}
125
126	static void netx_stop_rx(struct uart_port *port)
127	{
128	unsigned int val;
129	val = readl(port->membase + UART_CR);
130	writel(val & ~CR_RIE, port->membase + UART_CR);
131	}
132
133	static void netx_enable_ms(struct uart_port *port)
134	{
135	unsigned int val;
136	val = readl(port->membase + UART_CR);
137	writel(val \| CR_MSIE, port->membase + UART_CR);
138	}
139
140	static inline void netx_transmit_buffer(struct uart_port *port)
141	{
ebd2c8f6	142	struct circ_buf *xmit = &port->state->xmit;
f8441e13 SH	143
	144	if (port->x_char) {
	145	writel(port->x_char, port->membase + UART_DR);
	146	port->icount.tx++;
	147	port->x_char = 0;
	148	return;
	149	}
	150
	151	if (uart_tx_stopped(port) \|\| uart_circ_empty(xmit)) {
	152	netx_stop_tx(port);
	153	return;
	154	}
	155
	156	do {
	157	/* send xmit->buf[xmit->tail]
	158	* out the port here */
	159	writel(xmit->buf[xmit->tail], port->membase + UART_DR);
	160	xmit->tail = (xmit->tail + 1) &
	161	(UART_XMIT_SIZE - 1);
	162	port->icount.tx++;
	163	if (uart_circ_empty(xmit))
	164	break;
	165	} while (!(readl(port->membase + UART_FR) & FR_TXFF));
	166
	167	if (uart_circ_empty(xmit))
	168	netx_stop_tx(port);
	169	}
	170
	171	static void netx_start_tx(struct uart_port *port)
	172	{
	173	writel(
	174	readl(port->membase + UART_CR) \| CR_TIE, port->membase + UART_CR);
	175
	176	if (!(readl(port->membase + UART_FR) & FR_TXFF))
	177	netx_transmit_buffer(port);
	178	}
	179
	180	static unsigned int netx_tx_empty(struct uart_port *port)
	181	{
	182	return readl(port->membase + UART_FR) & FR_BUSY ? 0 : TIOCSER_TEMT;
	183	}
	184
	185	static void netx_txint(struct uart_port *port)
	186	{
ebd2c8f6	187	struct circ_buf *xmit = &port->state->xmit;
f8441e13 SH	188
	189	if (uart_circ_empty(xmit) \|\| uart_tx_stopped(port)) {
	190	netx_stop_tx(port);
	191	return;
	192	}
	193
	194	netx_transmit_buffer(port);
	195
	196	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
	197	uart_write_wakeup(port);
	198	}
	199
c8db1d97	200	static void netx_rxint(struct uart_port port, unsigned long flags)
f8441e13 SH	201	{
f8441e13 SH	202	unsigned char rx, flg, status;
f8441e13 SH	203
	204	while (!(readl(port->membase + UART_FR) & FR_RXFE)) {
	205	rx = readl(port->membase + UART_DR);
	206	flg = TTY_NORMAL;
	207	port->icount.rx++;
	208	status = readl(port->membase + UART_SR);
	209	if (status & SR_BE) {
	210	writel(0, port->membase + UART_SR);
	211	if (uart_handle_break(port))
	212	continue;
	213	}
	214
	215	if (unlikely(status & (SR_FE \| SR_PE \| SR_OE))) {
	216
	217	if (status & SR_PE)
	218	port->icount.parity++;
	219	else if (status & SR_FE)
	220	port->icount.frame++;
	221	if (status & SR_OE)
	222	port->icount.overrun++;
	223
	224	status &= port->read_status_mask;
	225
	226	if (status & SR_BE)
	227	flg = TTY_BREAK;
	228	else if (status & SR_PE)
	229	flg = TTY_PARITY;
	230	else if (status & SR_FE)
	231	flg = TTY_FRAME;
	232	}
	233
7d12e780	234	if (uart_handle_sysrq_char(port, rx))
f8441e13 SH	235	continue;
	236
	237	uart_insert_char(port, status, SR_OE, rx, flg);
	238	}
	239
c8db1d97	240	spin_unlock_irqrestore(&port->lock, *flags);
2e124b4a	241	tty_flip_buffer_push(&port->state->port);
c8db1d97	242	spin_lock_irqsave(&port->lock, *flags);
f8441e13 SH	243	}
f8441e13 SH	244
7d12e780	245	static irqreturn_t netx_int(int irq, void *dev_id)
f8441e13	246	{
c7bec5ab	247	struct uart_port *port = dev_id;
f8441e13 SH	248	unsigned long flags;
	249	unsigned char status;
	250
	251	spin_lock_irqsave(&port->lock,flags);
	252
	253	status = readl(port->membase + UART_IIR) & IIR_MASK;
	254	while (status) {
	255	if (status & IIR_RIS)
c8db1d97	256	netx_rxint(port, &flags);
f8441e13 SH	257	if (status & IIR_TIS)
	258	netx_txint(port);
	259	if (status & IIR_MIS) {
	260	if (readl(port->membase + UART_FR) & FR_CTS)
	261	uart_handle_cts_change(port, 1);
	262	else
	263	uart_handle_cts_change(port, 0);
	264	}
	265	writel(0, port->membase + UART_IIR);
	266	status = readl(port->membase + UART_IIR) & IIR_MASK;
	267	}
	268
	269	spin_unlock_irqrestore(&port->lock,flags);
	270	return IRQ_HANDLED;
	271	}
	272
	273	static unsigned int netx_get_mctrl(struct uart_port *port)
	274	{
	275	unsigned int ret = TIOCM_DSR \| TIOCM_CAR;
	276
	277	if (readl(port->membase + UART_FR) & FR_CTS)
	278	ret \|= TIOCM_CTS;
	279
	280	return ret;
	281	}
	282
	283	static void netx_set_mctrl(struct uart_port *port, unsigned int mctrl)
	284	{
	285	unsigned int val;
	286
978e595f	287	/* FIXME: Locking needed ? */
f8441e13 SH	288	if (mctrl & TIOCM_RTS) {
	289	val = readl(port->membase + UART_RTS_CR);
	290	writel(val \| RTS_CR_RTS, port->membase + UART_RTS_CR);
	291	}
	292	}
	293
	294	static void netx_break_ctl(struct uart_port *port, int break_state)
	295	{
	296	unsigned int line_cr;
	297	spin_lock_irq(&port->lock);
	298
	299	line_cr = readl(port->membase + UART_LINE_CR);
	300	if (break_state != 0)
	301	line_cr \|= LINE_CR_BRK;
	302	else
	303	line_cr &= ~LINE_CR_BRK;
	304	writel(line_cr, port->membase + UART_LINE_CR);
	305
	306	spin_unlock_irq(&port->lock);
	307	}
	308
	309	static int netx_startup(struct uart_port *port)
	310	{
	311	int ret;
	312
	313	ret = request_irq(port->irq, netx_int, 0,
	314	DRIVER_NAME, port);
	315	if (ret) {
	316	dev_err(port->dev, "unable to grab irq%d\n",port->irq);
	317	goto exit;
	318	}
	319
	320	writel(readl(port->membase + UART_LINE_CR) \| LINE_CR_FEN,
	321	port->membase + UART_LINE_CR);
	322
	323	writel(CR_MSIE \| CR_RIE \| CR_TIE \| CR_RTIE \| CR_UART_EN,
	324	port->membase + UART_CR);
	325
	326	exit:
	327	return ret;
	328	}
	329
	330	static void netx_shutdown(struct uart_port *port)
	331	{
	332	writel(0, port->membase + UART_CR) ;
	333
	334	free_irq(port->irq, port);
	335	}
	336
	337	static void
606d099c AC	338	netx_set_termios(struct uart_port port, struct ktermios termios,
606d099c AC	339	struct ktermios *old)
f8441e13 SH	340	{
	341	unsigned int baud, quot;
	342	unsigned char old_cr;
	343	unsigned char line_cr = LINE_CR_FEN;
	344	unsigned char rts_cr = 0;
	345
	346	switch (termios->c_cflag & CSIZE) {
	347	case CS5:
	348	line_cr \|= LINE_CR_5BIT;
	349	break;
	350	case CS6:
	351	line_cr \|= LINE_CR_6BIT;
	352	break;
	353	case CS7:
	354	line_cr \|= LINE_CR_7BIT;
	355	break;
	356	case CS8:
	357	line_cr \|= LINE_CR_8BIT;
	358	break;
	359	}
	360
	361	if (termios->c_cflag & CSTOPB)
	362	line_cr \|= LINE_CR_STP2;
	363
	364	if (termios->c_cflag & PARENB) {
	365	line_cr \|= LINE_CR_PEN;
	366	if (!(termios->c_cflag & PARODD))
	367	line_cr \|= LINE_CR_EPS;
	368	}
	369
	370	if (termios->c_cflag & CRTSCTS)
	371	rts_cr = RTS_CR_AUTO \| RTS_CR_CTS_CTR \| RTS_CR_RTS_POL;
	372
	373	baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
	374	quot = baud * 4096;
	375	quot /= 1000;
	376	quot *= 256;
	377	quot /= 100000;
	378
	379	spin_lock_irq(&port->lock);
	380
	381	uart_update_timeout(port, termios->c_cflag, baud);
	382
	383	old_cr = readl(port->membase + UART_CR);
	384
	385	/* disable interrupts */
	386	writel(old_cr & ~(CR_MSIE \| CR_RIE \| CR_TIE \| CR_RTIE),
	387	port->membase + UART_CR);
	388
	389	/* drain transmitter */
	390	while (readl(port->membase + UART_FR) & FR_BUSY);
	391
	392	/* disable UART */
	393	writel(old_cr & ~CR_UART_EN, port->membase + UART_CR);
	394
	395	/* modem status interrupts */
	396	old_cr &= ~CR_MSIE;
	397	if (UART_ENABLE_MS(port, termios->c_cflag))
	398	old_cr \|= CR_MSIE;
	399
	400	writel((quot>>8) & 0xff, port->membase + UART_BAUDDIV_MSB);
	401	writel(quot & 0xff, port->membase + UART_BAUDDIV_LSB);
	402	writel(line_cr, port->membase + UART_LINE_CR);
	403
404	writel(rts_cr, port->membase + UART_RTS_CR);
405
406	/*
407	* Characters to ignore
408	*/
409	port->ignore_status_mask = 0;
410	if (termios->c_iflag & IGNPAR)
411	port->ignore_status_mask \|= SR_PE;
412	if (termios->c_iflag & IGNBRK) {
413	port->ignore_status_mask \|= SR_BE;
414	/*
415	* If we're ignoring parity and break indicators,
416	* ignore overruns too (for real raw support).
417	*/
418	if (termios->c_iflag & IGNPAR)
419	port->ignore_status_mask \|= SR_PE;
420	}
421
422	port->read_status_mask = 0;
ef8b9ddc	423	if (termios->c_iflag & (IGNBRK \| BRKINT \| PARMRK))
f8441e13 SH	424	port->read_status_mask \|= SR_BE;
	425	if (termios->c_iflag & INPCK)
	426	port->read_status_mask \|= SR_PE \| SR_FE;
	427
	428	writel(old_cr, port->membase + UART_CR);
	429
	430	spin_unlock_irq(&port->lock);
	431	}
	432
	433	static const char netx_type(struct uart_port port)
	434	{
	435	return port->type == PORT_NETX ? "NETX" : NULL;
	436	}
	437
	438	static void netx_release_port(struct uart_port *port)
	439	{
	440	release_mem_region(port->mapbase, UART_PORT_SIZE);
	441	}
	442
	443	static int netx_request_port(struct uart_port *port)
	444	{
	445	return request_mem_region(port->mapbase, UART_PORT_SIZE,
	446	DRIVER_NAME) != NULL ? 0 : -EBUSY;
	447	}
	448
	449	static void netx_config_port(struct uart_port *port, int flags)
	450	{
	451	if (flags & UART_CONFIG_TYPE && netx_request_port(port) == 0)
	452	port->type = PORT_NETX;
	453	}
	454
	455	static int
	456	netx_verify_port(struct uart_port port, struct serial_struct ser)
	457	{
	458	int ret = 0;
	459
	460	if (ser->type != PORT_UNKNOWN && ser->type != PORT_NETX)
	461	ret = -EINVAL;
	462
	463	return ret;
	464	}
	465
	466	static struct uart_ops netx_pops = {
	467	.tx_empty = netx_tx_empty,
	468	.set_mctrl = netx_set_mctrl,
	469	.get_mctrl = netx_get_mctrl,
	470	.stop_tx = netx_stop_tx,
	471	.start_tx = netx_start_tx,
	472	.stop_rx = netx_stop_rx,
	473	.enable_ms = netx_enable_ms,
	474	.break_ctl = netx_break_ctl,
	475	.startup = netx_startup,
	476	.shutdown = netx_shutdown,
	477	.set_termios = netx_set_termios,
	478	.type = netx_type,
	479	.release_port = netx_release_port,
	480	.request_port = netx_request_port,
	481	.config_port = netx_config_port,
	482	.verify_port = netx_verify_port,
	483	};
	484
	485	static struct netx_port netx_ports[] = {
	486	{
	487	.port = {
488	.type = PORT_NETX,
489	.iotype = UPIO_MEM,
490	.membase = (char __iomem *)io_p2v(NETX_PA_UART0),
491	.mapbase = NETX_PA_UART0,
492	.irq = NETX_IRQ_UART0,
493	.uartclk = 100000000,
494	.fifosize = 16,
495	.flags = UPF_BOOT_AUTOCONF,
496	.ops = &netx_pops,
497	.line = 0,
498	},
499	}, {
500	.port = {
501	.type = PORT_NETX,
502	.iotype = UPIO_MEM,
503	.membase = (char __iomem *)io_p2v(NETX_PA_UART1),
504	.mapbase = NETX_PA_UART1,
505	.irq = NETX_IRQ_UART1,
506	.uartclk = 100000000,
507	.fifosize = 16,
508	.flags = UPF_BOOT_AUTOCONF,
509	.ops = &netx_pops,
510	.line = 1,
511	},
512	}, {
513	.port = {
514	.type = PORT_NETX,
515	.iotype = UPIO_MEM,
516	.membase = (char __iomem *)io_p2v(NETX_PA_UART2),
517	.mapbase = NETX_PA_UART2,
518	.irq = NETX_IRQ_UART2,
519	.uartclk = 100000000,
520	.fifosize = 16,
521	.flags = UPF_BOOT_AUTOCONF,
522	.ops = &netx_pops,
523	.line = 2,
524	},
525	}
526	};
527
fb881f78 PB	528	#ifdef CONFIG_SERIAL_NETX_CONSOLE
fb881f78 PB	529
f8441e13 SH	530	static void netx_console_putchar(struct uart_port *port, int ch)
	531	{
	532	while (readl(port->membase + UART_FR) & FR_BUSY);
	533	writel(ch, port->membase + UART_DR);
	534	}
	535
	536	static void
	537	netx_console_write(struct console co, const char s, unsigned int count)
	538	{
	539	struct uart_port *port = &netx_ports[co->index].port;
	540	unsigned char cr_save;
	541
	542	cr_save = readl(port->membase + UART_CR);
	543	writel(cr_save \| CR_UART_EN, port->membase + UART_CR);
	544
	545	uart_console_write(port, s, count, netx_console_putchar);
	546
	547	while (readl(port->membase + UART_FR) & FR_BUSY);
	548	writel(cr_save, port->membase + UART_CR);
	549	}
	550
	551	static void __init
	552	netx_console_get_options(struct uart_port port, int baud,
	553	int parity, int bits, int *flow)
	554	{
	555	unsigned char line_cr;
	556
	557	*baud = (readl(port->membase + UART_BAUDDIV_MSB) << 8) \|
	558	readl(port->membase + UART_BAUDDIV_LSB);
	559	baud = 1000;
	560	*baud /= 4096;
	561	baud = 1000;
	562	*baud /= 256;
	563	baud = 100;
	564
	565	line_cr = readl(port->membase + UART_LINE_CR);
	566	*parity = 'n';
	567	if (line_cr & LINE_CR_PEN) {
	568	if (line_cr & LINE_CR_EPS)
	569	*parity = 'e';
	570	else
	571	*parity = 'o';
	572	}
	573
	574	switch (line_cr & LINE_CR_BITS_MASK) {
	575	case LINE_CR_8BIT:
	576	*bits = 8;
	577	break;
	578	case LINE_CR_7BIT:
	579	*bits = 7;
	580	break;
	581	case LINE_CR_6BIT:
	582	*bits = 6;
	583	break;
	584	case LINE_CR_5BIT:
	585	*bits = 5;
	586	break;
	587	}
	588
	589	if (readl(port->membase + UART_RTS_CR) & RTS_CR_AUTO)
	590	*flow = 'r';
	591	}
	592
	593	static int __init
594	netx_console_setup(struct console co, char options)
595	{
596	struct netx_port *sport;
597	int baud = 9600;
598	int bits = 8;
599	int parity = 'n';
600	int flow = 'n';
601
602	/*
603	* Check whether an invalid uart number has been specified, and
604	* if so, search for the first available port that does have
605	* console support.
606	*/
607	if (co->index == -1 \|\| co->index >= ARRAY_SIZE(netx_ports))
608	co->index = 0;
609	sport = &netx_ports[co->index];
610
611	if (options) {
612	uart_parse_options(options, &baud, &parity, &bits, &flow);
613	} else {
614	/* if the UART is enabled, assume it has been correctly setup
615	* by the bootloader and get the options
616	*/
617	if (readl(sport->port.membase + UART_CR) & CR_UART_EN) {
618	netx_console_get_options(&sport->port, &baud,
619	&parity, &bits, &flow);
620	}
621
622	}
623
624	return uart_set_options(&sport->port, co, baud, parity, bits, flow);
625	}
626
627	static struct uart_driver netx_reg;
628	static struct console netx_console = {
629	.name = "ttyNX",
630	.write = netx_console_write,
631	.device = uart_console_device,
632	.setup = netx_console_setup,
633	.flags = CON_PRINTBUFFER,
634	.index = -1,
635	.data = &netx_reg,
636	};
637
638	static int __init netx_console_init(void)
639	{
640	register_console(&netx_console);
641	return 0;
642	}
643	console_initcall(netx_console_init);
644
645	#define NETX_CONSOLE &netx_console
646	#else
647	#define NETX_CONSOLE NULL
648	#endif
649
650	static struct uart_driver netx_reg = {
651	.owner = THIS_MODULE,
652	.driver_name = DRIVER_NAME,
653	.dev_name = "ttyNX",
654	.major = SERIAL_NX_MAJOR,
655	.minor = MINOR_START,
656	.nr = ARRAY_SIZE(netx_ports),
657	.cons = NETX_CONSOLE,
658	};
659
660	static int serial_netx_suspend(struct platform_device *pdev, pm_message_t state)
661	{
662	struct netx_port *sport = platform_get_drvdata(pdev);
663
664	if (sport)
665	uart_suspend_port(&netx_reg, &sport->port);
666
667	return 0;
668	}
669
670	static int serial_netx_resume(struct platform_device *pdev)
671	{
672	struct netx_port *sport = platform_get_drvdata(pdev);
673
674	if (sport)
675	uart_resume_port(&netx_reg, &sport->port);
676
677	return 0;
678	}
679
680	static int serial_netx_probe(struct platform_device *pdev)
681	{
682	struct uart_port *port = &netx_ports[pdev->id].port;
683
684	dev_info(&pdev->dev, "initialising\n");
685
686	port->dev = &pdev->dev;
687
688	writel(1, port->membase + UART_RXFIFO_IRQLEVEL);
689	uart_add_one_port(&netx_reg, &netx_ports[pdev->id].port);
690	platform_set_drvdata(pdev, &netx_ports[pdev->id]);
691
692	return 0;
693	}
694
695	static int serial_netx_remove(struct platform_device *pdev)
696	{
697	struct netx_port *sport = platform_get_drvdata(pdev);
698
f8441e13 SH	699	if (sport)
	700	uart_remove_one_port(&netx_reg, &sport->port);
	701
	702	return 0;
	703	}
	704
	705	static struct platform_driver serial_netx_driver = {
	706	.probe = serial_netx_probe,
	707	.remove = serial_netx_remove,
	708
	709	.suspend = serial_netx_suspend,
	710	.resume = serial_netx_resume,
	711
	712	.driver = {
	713	.name = DRIVER_NAME,
	714	},
	715	};
	716
	717	static int __init netx_serial_init(void)
	718	{
	719	int ret;
	720
	721	printk(KERN_INFO "Serial: NetX driver\n");
	722
	723	ret = uart_register_driver(&netx_reg);
	724	if (ret)
	725	return ret;
	726
	727	ret = platform_driver_register(&serial_netx_driver);
	728	if (ret != 0)
	729	uart_unregister_driver(&netx_reg);
	730
	731	return 0;
	732	}
	733
	734	static void __exit netx_serial_exit(void)
	735	{
	736	platform_driver_unregister(&serial_netx_driver);
	737	uart_unregister_driver(&netx_reg);
	738	}
	739
	740	module_init(netx_serial_init);
	741	module_exit(netx_serial_exit);
	742
	743	MODULE_AUTHOR("Sascha Hauer");
	744	MODULE_DESCRIPTION("NetX serial port driver");
	745	MODULE_LICENSE("GPL");
e169c139	746	MODULE_ALIAS("platform:" DRIVER_NAME);